2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
38 #include "instr-a3xx.h"
40 #include "ir3_context.h"
43 ir3_handle_bindless_cat6(struct ir3_instruction
*instr
, nir_src rsrc
)
45 nir_intrinsic_instr
*intrin
= ir3_bindless_resource(rsrc
);
49 instr
->flags
|= IR3_INSTR_B
;
50 instr
->cat6
.base
= nir_intrinsic_desc_set(intrin
);
53 static struct ir3_instruction
*
54 create_indirect_load(struct ir3_context
*ctx
, unsigned arrsz
, int n
,
55 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
57 struct ir3_block
*block
= ctx
->block
;
58 struct ir3_instruction
*mov
;
59 struct ir3_register
*src
;
61 mov
= ir3_instr_create(block
, OPC_MOV
);
62 mov
->cat1
.src_type
= TYPE_U32
;
63 mov
->cat1
.dst_type
= TYPE_U32
;
65 src
= __ssa_src(mov
, collect
, IR3_REG_RELATIV
);
67 src
->array
.offset
= n
;
69 ir3_instr_set_address(mov
, address
);
74 static struct ir3_instruction
*
75 create_input(struct ir3_context
*ctx
, unsigned compmask
)
77 struct ir3_instruction
*in
;
79 in
= ir3_instr_create(ctx
->in_block
, OPC_META_INPUT
);
80 in
->input
.sysval
= ~0;
81 __ssa_dst(in
)->wrmask
= compmask
;
83 array_insert(ctx
->ir
, ctx
->ir
->inputs
, in
);
88 static struct ir3_instruction
*
89 create_frag_input(struct ir3_context
*ctx
, bool use_ldlv
, unsigned n
)
91 struct ir3_block
*block
= ctx
->block
;
92 struct ir3_instruction
*instr
;
93 /* packed inloc is fixed up later: */
94 struct ir3_instruction
*inloc
= create_immed(block
, n
);
97 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
98 instr
->cat6
.type
= TYPE_U32
;
99 instr
->cat6
.iim_val
= 1;
101 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->ij
[IJ_PERSP_PIXEL
], 0);
102 instr
->regs
[2]->wrmask
= 0x3;
108 static struct ir3_instruction
*
109 create_driver_param(struct ir3_context
*ctx
, enum ir3_driver_param dp
)
111 /* first four vec4 sysval's reserved for UBOs: */
112 /* NOTE: dp is in scalar, but there can be >4 dp components: */
113 struct ir3_const_state
*const_state
= ir3_const_state(ctx
->so
);
114 unsigned n
= const_state
->offsets
.driver_param
;
115 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
116 return create_uniform(ctx
->block
, r
);
120 * Adreno's comparisons produce a 1 for true and 0 for false, in either 16 or
121 * 32-bit registers. We use NIR's 1-bit integers to represent bools, and
122 * trust that we will only see and/or/xor on those 1-bit values, so we can
123 * safely store NIR i1s in a 32-bit reg while always containing either a 1 or
128 * alu/sfu instructions:
131 static struct ir3_instruction
*
132 create_cov(struct ir3_context
*ctx
, struct ir3_instruction
*src
,
133 unsigned src_bitsize
, nir_op op
)
135 type_t src_type
, dst_type
;
139 case nir_op_f2f16_rtne
:
140 case nir_op_f2f16_rtz
:
148 switch (src_bitsize
) {
156 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
165 switch (src_bitsize
) {
176 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
185 switch (src_bitsize
) {
196 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
209 ir3_context_error(ctx
, "invalid conversion op: %u", op
);
220 case nir_op_f2f16_rtne
:
221 case nir_op_f2f16_rtz
:
263 ir3_context_error(ctx
, "invalid conversion op: %u", op
);
266 if (src_type
== dst_type
)
269 struct ir3_instruction
*cov
=
270 ir3_COV(ctx
->block
, src
, src_type
, dst_type
);
272 if (op
== nir_op_f2f16_rtne
)
273 cov
->regs
[0]->flags
|= IR3_REG_EVEN
;
279 emit_alu(struct ir3_context
*ctx
, nir_alu_instr
*alu
)
281 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
282 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
283 unsigned bs
[info
->num_inputs
]; /* bit size */
284 struct ir3_block
*b
= ctx
->block
;
285 unsigned dst_sz
, wrmask
;
286 type_t dst_type
= nir_dest_bit_size(alu
->dest
.dest
) == 16 ?
289 if (alu
->dest
.dest
.is_ssa
) {
290 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
291 wrmask
= (1 << dst_sz
) - 1;
293 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
294 wrmask
= alu
->dest
.write_mask
;
297 dst
= ir3_get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
299 /* Vectors are special in that they have non-scalarized writemasks,
300 * and just take the first swizzle channel for each argument in
301 * order into each writemask channel.
303 if ((alu
->op
== nir_op_vec2
) ||
304 (alu
->op
== nir_op_vec3
) ||
305 (alu
->op
== nir_op_vec4
)) {
307 for (int i
= 0; i
< info
->num_inputs
; i
++) {
308 nir_alu_src
*asrc
= &alu
->src
[i
];
310 compile_assert(ctx
, !asrc
->abs
);
311 compile_assert(ctx
, !asrc
->negate
);
313 src
[i
] = ir3_get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
315 src
[i
] = create_immed_typed(ctx
->block
, 0, dst_type
);
316 dst
[i
] = ir3_MOV(b
, src
[i
], dst_type
);
319 ir3_put_dst(ctx
, &alu
->dest
.dest
);
323 /* We also get mov's with more than one component for mov's so
324 * handle those specially:
326 if (alu
->op
== nir_op_mov
) {
327 nir_alu_src
*asrc
= &alu
->src
[0];
328 struct ir3_instruction
*const *src0
= ir3_get_src(ctx
, &asrc
->src
);
330 for (unsigned i
= 0; i
< dst_sz
; i
++) {
331 if (wrmask
& (1 << i
)) {
332 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], dst_type
);
338 ir3_put_dst(ctx
, &alu
->dest
.dest
);
342 /* General case: We can just grab the one used channel per src. */
343 for (int i
= 0; i
< info
->num_inputs
; i
++) {
344 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
345 nir_alu_src
*asrc
= &alu
->src
[i
];
347 compile_assert(ctx
, !asrc
->abs
);
348 compile_assert(ctx
, !asrc
->negate
);
350 src
[i
] = ir3_get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
351 bs
[i
] = nir_src_bit_size(asrc
->src
);
353 compile_assert(ctx
, src
[i
]);
358 case nir_op_f2f16_rtne
:
359 case nir_op_f2f16_rtz
:
382 dst
[0] = create_cov(ctx
, src
[0], bs
[0], alu
->op
);
385 case nir_op_fquantize2f16
:
386 dst
[0] = create_cov(ctx
,
387 create_cov(ctx
, src
[0], 32, nir_op_f2f16
),
391 dst
[0] = ir3_CMPS_F(b
,
393 create_immed_typed(b
, 0, bs
[0] == 16 ? TYPE_F16
: TYPE_F32
), 0);
394 dst
[0]->cat2
.condition
= IR3_COND_NE
;
398 /* i2b1 will appear when translating from nir_load_ubo or
399 * nir_intrinsic_load_ssbo, where any non-zero value is true.
401 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
402 dst
[0]->cat2
.condition
= IR3_COND_NE
;
406 /* b2b1 will appear when translating from
408 * - nir_intrinsic_load_shared of a 32-bit 0/~0 value.
409 * - nir_intrinsic_load_constant of a 32-bit 0/~0 value
411 * A negate can turn those into a 1 or 0 for us.
413 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
417 /* b2b32 will appear when converting our 1-bit bools to a store_shared
420 * A negate can turn those into a ~0 for us.
422 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
426 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
429 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
432 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
435 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
438 /* if there is just a single use of the src, and it supports
439 * (sat) bit, we can just fold the (sat) flag back to the
440 * src instruction and create a mov. This is easier for cp
443 * NOTE: a3xx definitely seen not working with flat bary.f. Same test
444 * uses ldlv on a4xx+, so not definitive. Seems rare enough to apply
447 * TODO probably opc_cat==4 is ok too
449 if (alu
->src
[0].src
.is_ssa
&&
450 src
[0]->opc
!= OPC_BARY_F
&&
451 (list_length(&alu
->src
[0].src
.ssa
->uses
) == 1) &&
452 ((opc_cat(src
[0]->opc
) == 2) || (opc_cat(src
[0]->opc
) == 3))) {
453 src
[0]->flags
|= IR3_INSTR_SAT
;
454 dst
[0] = ir3_MOV(b
, src
[0], dst_type
);
456 /* otherwise generate a max.f that saturates.. blob does
457 * similar (generating a cat2 mov using max.f)
459 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[0], 0);
460 dst
[0]->flags
|= IR3_INSTR_SAT
;
464 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
467 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
470 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
473 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
476 case nir_op_fddx_coarse
:
477 dst
[0] = ir3_DSX(b
, src
[0], 0);
478 dst
[0]->cat5
.type
= TYPE_F32
;
480 case nir_op_fddx_fine
:
481 dst
[0] = ir3_DSXPP_MACRO(b
, src
[0], 0);
482 dst
[0]->cat5
.type
= TYPE_F32
;
485 case nir_op_fddy_coarse
:
486 dst
[0] = ir3_DSY(b
, src
[0], 0);
487 dst
[0]->cat5
.type
= TYPE_F32
;
490 case nir_op_fddy_fine
:
491 dst
[0] = ir3_DSYPP_MACRO(b
, src
[0], 0);
492 dst
[0]->cat5
.type
= TYPE_F32
;
495 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
496 dst
[0]->cat2
.condition
= IR3_COND_LT
;
499 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
500 dst
[0]->cat2
.condition
= IR3_COND_GE
;
503 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
504 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
507 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
508 dst
[0]->cat2
.condition
= IR3_COND_NE
;
511 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
514 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
517 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
519 case nir_op_fround_even
:
520 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
523 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
527 dst
[0] = ir3_SIN(b
, src
[0], 0);
530 dst
[0] = ir3_COS(b
, src
[0], 0);
533 dst
[0] = ir3_RSQ(b
, src
[0], 0);
536 dst
[0] = ir3_RCP(b
, src
[0], 0);
539 dst
[0] = ir3_LOG2(b
, src
[0], 0);
542 dst
[0] = ir3_EXP2(b
, src
[0], 0);
545 dst
[0] = ir3_SQRT(b
, src
[0], 0);
549 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
552 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
555 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
558 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
561 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
564 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
567 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
569 case nir_op_umul_low
:
570 dst
[0] = ir3_MULL_U(b
, src
[0], 0, src
[1], 0);
572 case nir_op_imadsh_mix16
:
573 dst
[0] = ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0, src
[2], 0);
575 case nir_op_imad24_ir3
:
576 dst
[0] = ir3_MAD_S24(b
, src
[0], 0, src
[1], 0, src
[2], 0);
579 dst
[0] = ir3_MUL_S24(b
, src
[0], 0, src
[1], 0);
582 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
586 dst
[0] = ir3_SUB_U(b
, create_immed(ctx
->block
, 1), 0, src
[0], 0);
588 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
592 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
595 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
598 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
601 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
604 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
607 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
610 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
611 dst
[0]->cat2
.condition
= IR3_COND_LT
;
614 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
615 dst
[0]->cat2
.condition
= IR3_COND_GE
;
618 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
619 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
622 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
623 dst
[0]->cat2
.condition
= IR3_COND_NE
;
626 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
627 dst
[0]->cat2
.condition
= IR3_COND_LT
;
630 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
631 dst
[0]->cat2
.condition
= IR3_COND_GE
;
635 struct ir3_instruction
*cond
= src
[0];
637 /* If src[0] is a negation (likely as a result of an ir3_b2n(cond)),
638 * we can ignore that and use original cond, since the nonzero-ness of
639 * cond stays the same.
641 if (cond
->opc
== OPC_ABSNEG_S
&&
643 (cond
->regs
[1]->flags
& (IR3_REG_SNEG
| IR3_REG_SABS
)) == IR3_REG_SNEG
) {
644 cond
= cond
->regs
[1]->instr
;
647 compile_assert(ctx
, bs
[1] == bs
[2]);
648 /* The condition's size has to match the other two arguments' size, so
649 * convert down if necessary.
652 struct hash_entry
*prev_entry
=
653 _mesa_hash_table_search(ctx
->sel_cond_conversions
, src
[0]);
655 cond
= prev_entry
->data
;
657 cond
= ir3_COV(b
, cond
, TYPE_U32
, TYPE_U16
);
658 _mesa_hash_table_insert(ctx
->sel_cond_conversions
, src
[0], cond
);
663 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, cond
, 0, src
[2], 0);
665 dst
[0] = ir3_SEL_B16(b
, src
[1], 0, cond
, 0, src
[2], 0);
668 case nir_op_bit_count
: {
669 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
670 // double check on earlier gen's. Once half-precision support is
671 // in place, this should probably move to a NIR lowering pass:
672 struct ir3_instruction
*hi
, *lo
;
674 hi
= ir3_COV(b
, ir3_SHR_B(b
, src
[0], 0, create_immed(b
, 16), 0),
676 lo
= ir3_COV(b
, src
[0], TYPE_U32
, TYPE_U16
);
678 hi
= ir3_CBITS_B(b
, hi
, 0);
679 lo
= ir3_CBITS_B(b
, lo
, 0);
681 // TODO maybe the builders should default to making dst half-precision
682 // if the src's were half precision, to make this less awkward.. otoh
683 // we should probably just do this lowering in NIR.
684 hi
->regs
[0]->flags
|= IR3_REG_HALF
;
685 lo
->regs
[0]->flags
|= IR3_REG_HALF
;
687 dst
[0] = ir3_ADD_S(b
, hi
, 0, lo
, 0);
688 dst
[0]->regs
[0]->flags
|= IR3_REG_HALF
;
689 dst
[0] = ir3_COV(b
, dst
[0], TYPE_U16
, TYPE_U32
);
692 case nir_op_ifind_msb
: {
693 struct ir3_instruction
*cmp
;
694 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
695 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
696 cmp
->cat2
.condition
= IR3_COND_GE
;
697 dst
[0] = ir3_SEL_B32(b
,
698 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
702 case nir_op_ufind_msb
:
703 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
704 dst
[0] = ir3_SEL_B32(b
,
705 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
706 src
[0], 0, dst
[0], 0);
708 case nir_op_find_lsb
:
709 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
710 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
712 case nir_op_bitfield_reverse
:
713 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
717 ir3_context_error(ctx
, "Unhandled ALU op: %s\n",
718 nir_op_infos
[alu
->op
].name
);
722 if (nir_alu_type_get_base_type(info
->output_type
) == nir_type_bool
) {
723 assert(nir_dest_bit_size(alu
->dest
.dest
) == 1 ||
724 alu
->op
== nir_op_b2b32
);
727 /* 1-bit values stored in 32-bit registers are only valid for certain
738 compile_assert(ctx
, nir_dest_bit_size(alu
->dest
.dest
) != 1);
742 ir3_put_dst(ctx
, &alu
->dest
.dest
);
746 emit_intrinsic_load_ubo_ldc(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
747 struct ir3_instruction
**dst
)
749 struct ir3_block
*b
= ctx
->block
;
751 unsigned ncomp
= intr
->num_components
;
752 struct ir3_instruction
*offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
753 struct ir3_instruction
*idx
= ir3_get_src(ctx
, &intr
->src
[0])[0];
754 struct ir3_instruction
*ldc
= ir3_LDC(b
, idx
, 0, offset
, 0);
755 ldc
->regs
[0]->wrmask
= MASK(ncomp
);
756 ldc
->cat6
.iim_val
= ncomp
;
757 ldc
->cat6
.d
= nir_intrinsic_base(intr
);
758 ldc
->cat6
.type
= TYPE_U32
;
760 ir3_handle_bindless_cat6(ldc
, intr
->src
[0]);
761 if (ldc
->flags
& IR3_INSTR_B
)
762 ctx
->so
->bindless_ubo
= true;
764 ir3_split_dest(b
, dst
, ldc
, 0, ncomp
);
768 /* handles direct/indirect UBO reads: */
770 emit_intrinsic_load_ubo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
771 struct ir3_instruction
**dst
)
773 struct ir3_block
*b
= ctx
->block
;
774 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
775 const struct ir3_const_state
*const_state
= ir3_const_state(ctx
->so
);
776 unsigned ubo
= regid(const_state
->offsets
.ubo
, 0);
777 const unsigned ptrsz
= ir3_pointer_size(ctx
->compiler
);
781 /* First src is ubo index, which could either be an immed or not: */
782 src0
= ir3_get_src(ctx
, &intr
->src
[0])[0];
783 if (is_same_type_mov(src0
) &&
784 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
785 base_lo
= create_uniform(b
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
786 base_hi
= create_uniform(b
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
788 base_lo
= create_uniform_indirect(b
, ubo
, ir3_get_addr0(ctx
, src0
, ptrsz
));
789 base_hi
= create_uniform_indirect(b
, ubo
+ 1, ir3_get_addr0(ctx
, src0
, ptrsz
));
791 /* NOTE: since relative addressing is used, make sure constlen is
792 * at least big enough to cover all the UBO addresses, since the
793 * assembler won't know what the max address reg is.
795 ctx
->so
->constlen
= MAX2(ctx
->so
->constlen
,
796 const_state
->offsets
.ubo
+ (ctx
->s
->info
.num_ubos
* ptrsz
));
799 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
802 if (nir_src_is_const(intr
->src
[1])) {
803 off
+= nir_src_as_uint(intr
->src
[1]);
805 /* For load_ubo_indirect, second src is indirect offset: */
806 src1
= ir3_get_src(ctx
, &intr
->src
[1])[0];
808 /* and add offset to addr: */
809 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
812 /* if offset is to large to encode in the ldg, split it out: */
813 if ((off
+ (intr
->num_components
* 4)) > 1024) {
814 /* split out the minimal amount to improve the odds that
815 * cp can fit the immediate in the add.s instruction:
817 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
818 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
823 struct ir3_instruction
*carry
;
825 /* handle 32b rollover, ie:
826 * if (addr < base_lo)
829 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
830 carry
->cat2
.condition
= IR3_COND_LT
;
831 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
833 addr
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
836 for (int i
= 0; i
< intr
->num_components
; i
++) {
837 struct ir3_instruction
*load
=
838 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0, /* num components */
839 create_immed(b
, off
+ i
* 4), 0);
840 load
->cat6
.type
= TYPE_U32
;
845 /* src[] = { block_index } */
847 emit_intrinsic_ssbo_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
848 struct ir3_instruction
**dst
)
850 if (ir3_bindless_resource(intr
->src
[0])) {
851 struct ir3_block
*b
= ctx
->block
;
852 struct ir3_instruction
*ibo
= ir3_ssbo_to_ibo(ctx
, intr
->src
[0]);
853 struct ir3_instruction
*resinfo
= ir3_RESINFO(b
, ibo
, 0);
854 resinfo
->cat6
.iim_val
= 1;
856 resinfo
->cat6
.type
= TYPE_U32
;
857 resinfo
->cat6
.typed
= false;
858 /* resinfo has no writemask and always writes out 3 components */
859 resinfo
->regs
[0]->wrmask
= MASK(3);
860 ir3_handle_bindless_cat6(resinfo
, intr
->src
[0]);
861 struct ir3_instruction
*resinfo_dst
;
862 ir3_split_dest(b
, &resinfo_dst
, resinfo
, 0, 1);
863 /* Unfortunately resinfo returns the array length, i.e. in dwords,
864 * while NIR expects us to return the size in bytes.
866 * TODO: fix this in NIR.
868 *dst
= ir3_SHL_B(b
, resinfo_dst
, 0, create_immed(b
, 2), 0);
872 /* SSBO size stored as a const starting at ssbo_sizes: */
873 const struct ir3_const_state
*const_state
= ir3_const_state(ctx
->so
);
874 unsigned blk_idx
= nir_src_as_uint(intr
->src
[0]);
875 unsigned idx
= regid(const_state
->offsets
.ssbo_sizes
, 0) +
876 const_state
->ssbo_size
.off
[blk_idx
];
878 debug_assert(const_state
->ssbo_size
.mask
& (1 << blk_idx
));
880 dst
[0] = create_uniform(ctx
->block
, idx
);
883 /* src[] = { offset }. const_index[] = { base } */
885 emit_intrinsic_load_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
886 struct ir3_instruction
**dst
)
888 struct ir3_block
*b
= ctx
->block
;
889 struct ir3_instruction
*ldl
, *offset
;
892 offset
= ir3_get_src(ctx
, &intr
->src
[0])[0];
893 base
= nir_intrinsic_base(intr
);
895 ldl
= ir3_LDL(b
, offset
, 0,
896 create_immed(b
, intr
->num_components
), 0,
897 create_immed(b
, base
), 0);
899 ldl
->cat6
.type
= utype_dst(intr
->dest
);
900 ldl
->regs
[0]->wrmask
= MASK(intr
->num_components
);
902 ldl
->barrier_class
= IR3_BARRIER_SHARED_R
;
903 ldl
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
905 ir3_split_dest(b
, dst
, ldl
, 0, intr
->num_components
);
908 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
910 emit_intrinsic_store_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
912 struct ir3_block
*b
= ctx
->block
;
913 struct ir3_instruction
*stl
, *offset
;
914 struct ir3_instruction
* const *value
;
915 unsigned base
, wrmask
, ncomp
;
917 value
= ir3_get_src(ctx
, &intr
->src
[0]);
918 offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
920 base
= nir_intrinsic_base(intr
);
921 wrmask
= nir_intrinsic_write_mask(intr
);
922 ncomp
= ffs(~wrmask
) - 1;
924 assert(wrmask
== BITFIELD_MASK(intr
->num_components
));
926 stl
= ir3_STL(b
, offset
, 0,
927 ir3_create_collect(ctx
, value
, ncomp
), 0,
928 create_immed(b
, ncomp
), 0);
929 stl
->cat6
.dst_offset
= base
;
930 stl
->cat6
.type
= utype_src(intr
->src
[0]);
931 stl
->barrier_class
= IR3_BARRIER_SHARED_W
;
932 stl
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
934 array_insert(b
, b
->keeps
, stl
);
937 /* src[] = { offset }. const_index[] = { base } */
939 emit_intrinsic_load_shared_ir3(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
940 struct ir3_instruction
**dst
)
942 struct ir3_block
*b
= ctx
->block
;
943 struct ir3_instruction
*load
, *offset
;
946 offset
= ir3_get_src(ctx
, &intr
->src
[0])[0];
947 base
= nir_intrinsic_base(intr
);
949 load
= ir3_LDLW(b
, offset
, 0,
950 create_immed(b
, intr
->num_components
), 0,
951 create_immed(b
, base
), 0);
953 /* for a650, use LDL for tess ctrl inputs: */
954 if (ctx
->so
->type
== MESA_SHADER_TESS_CTRL
&& ctx
->compiler
->tess_use_shared
)
957 load
->cat6
.type
= utype_dst(intr
->dest
);
958 load
->regs
[0]->wrmask
= MASK(intr
->num_components
);
960 load
->barrier_class
= IR3_BARRIER_SHARED_R
;
961 load
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
963 ir3_split_dest(b
, dst
, load
, 0, intr
->num_components
);
966 /* src[] = { value, offset }. const_index[] = { base } */
968 emit_intrinsic_store_shared_ir3(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
970 struct ir3_block
*b
= ctx
->block
;
971 struct ir3_instruction
*store
, *offset
;
972 struct ir3_instruction
* const *value
;
974 value
= ir3_get_src(ctx
, &intr
->src
[0]);
975 offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
977 store
= ir3_STLW(b
, offset
, 0,
978 ir3_create_collect(ctx
, value
, intr
->num_components
), 0,
979 create_immed(b
, intr
->num_components
), 0);
981 /* for a650, use STL for vertex outputs used by tess ctrl shader: */
982 if (ctx
->so
->type
== MESA_SHADER_VERTEX
&& ctx
->so
->key
.tessellation
&&
983 ctx
->compiler
->tess_use_shared
)
984 store
->opc
= OPC_STL
;
986 store
->cat6
.dst_offset
= nir_intrinsic_base(intr
);
987 store
->cat6
.type
= utype_src(intr
->src
[0]);
988 store
->barrier_class
= IR3_BARRIER_SHARED_W
;
989 store
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
991 array_insert(b
, b
->keeps
, store
);
995 * CS shared variable atomic intrinsics
997 * All of the shared variable atomic memory operations read a value from
998 * memory, compute a new value using one of the operations below, write the
999 * new value to memory, and return the original value read.
1001 * All operations take 2 sources except CompSwap that takes 3. These
1002 * sources represent:
1004 * 0: The offset into the shared variable storage region that the atomic
1005 * operation will operate on.
1006 * 1: The data parameter to the atomic function (i.e. the value to add
1007 * in shared_atomic_add, etc).
1008 * 2: For CompSwap only: the second data parameter.
1010 static struct ir3_instruction
*
1011 emit_intrinsic_atomic_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1013 struct ir3_block
*b
= ctx
->block
;
1014 struct ir3_instruction
*atomic
, *src0
, *src1
;
1015 type_t type
= TYPE_U32
;
1017 src0
= ir3_get_src(ctx
, &intr
->src
[0])[0]; /* offset */
1018 src1
= ir3_get_src(ctx
, &intr
->src
[1])[0]; /* value */
1020 switch (intr
->intrinsic
) {
1021 case nir_intrinsic_shared_atomic_add
:
1022 atomic
= ir3_ATOMIC_ADD(b
, src0
, 0, src1
, 0);
1024 case nir_intrinsic_shared_atomic_imin
:
1025 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1028 case nir_intrinsic_shared_atomic_umin
:
1029 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1031 case nir_intrinsic_shared_atomic_imax
:
1032 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1035 case nir_intrinsic_shared_atomic_umax
:
1036 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1038 case nir_intrinsic_shared_atomic_and
:
1039 atomic
= ir3_ATOMIC_AND(b
, src0
, 0, src1
, 0);
1041 case nir_intrinsic_shared_atomic_or
:
1042 atomic
= ir3_ATOMIC_OR(b
, src0
, 0, src1
, 0);
1044 case nir_intrinsic_shared_atomic_xor
:
1045 atomic
= ir3_ATOMIC_XOR(b
, src0
, 0, src1
, 0);
1047 case nir_intrinsic_shared_atomic_exchange
:
1048 atomic
= ir3_ATOMIC_XCHG(b
, src0
, 0, src1
, 0);
1050 case nir_intrinsic_shared_atomic_comp_swap
:
1051 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1052 src1
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1053 ir3_get_src(ctx
, &intr
->src
[2])[0],
1056 atomic
= ir3_ATOMIC_CMPXCHG(b
, src0
, 0, src1
, 0);
1062 atomic
->cat6
.iim_val
= 1;
1064 atomic
->cat6
.type
= type
;
1065 atomic
->barrier_class
= IR3_BARRIER_SHARED_W
;
1066 atomic
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1068 /* even if nothing consume the result, we can't DCE the instruction: */
1069 array_insert(b
, b
->keeps
, atomic
);
1074 struct tex_src_info
{
1076 unsigned tex_base
, samp_base
, tex_idx
, samp_idx
;
1077 /* For normal tex instructions */
1078 unsigned base
, combined_idx
, a1_val
, flags
;
1079 struct ir3_instruction
*samp_tex
;
1082 /* TODO handle actual indirect/dynamic case.. which is going to be weird
1083 * to handle with the image_mapping table..
1085 static struct tex_src_info
1086 get_image_samp_tex_src(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1088 struct ir3_block
*b
= ctx
->block
;
1089 struct tex_src_info info
= { 0 };
1090 nir_intrinsic_instr
*bindless_tex
= ir3_bindless_resource(intr
->src
[0]);
1091 ctx
->so
->bindless_tex
= true;
1095 info
.flags
|= IR3_INSTR_B
;
1097 /* Gather information required to determine which encoding to
1098 * choose as well as for prefetch.
1100 info
.tex_base
= nir_intrinsic_desc_set(bindless_tex
);
1101 bool tex_const
= nir_src_is_const(bindless_tex
->src
[0]);
1103 info
.tex_idx
= nir_src_as_uint(bindless_tex
->src
[0]);
1106 /* Choose encoding. */
1107 if (tex_const
&& info
.tex_idx
< 256) {
1108 if (info
.tex_idx
< 16) {
1109 /* Everything fits within the instruction */
1110 info
.base
= info
.tex_base
;
1111 info
.combined_idx
= info
.samp_idx
| (info
.tex_idx
<< 4);
1113 info
.base
= info
.tex_base
;
1114 info
.a1_val
= info
.tex_idx
<< 3;
1115 info
.combined_idx
= 0;
1116 info
.flags
|= IR3_INSTR_A1EN
;
1118 info
.samp_tex
= NULL
;
1120 info
.flags
|= IR3_INSTR_S2EN
;
1121 info
.base
= info
.tex_base
;
1123 /* Note: the indirect source is now a vec2 instead of hvec2 */
1124 struct ir3_instruction
*texture
, *sampler
;
1126 texture
= ir3_get_src(ctx
, &intr
->src
[0])[0];
1127 sampler
= create_immed(b
, 0);
1128 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1134 info
.flags
|= IR3_INSTR_S2EN
;
1135 unsigned slot
= nir_src_as_uint(intr
->src
[0]);
1136 unsigned tex_idx
= ir3_image_to_tex(&ctx
->so
->image_mapping
, slot
);
1137 struct ir3_instruction
*texture
, *sampler
;
1139 texture
= create_immed_typed(ctx
->block
, tex_idx
, TYPE_U16
);
1140 sampler
= create_immed_typed(ctx
->block
, tex_idx
, TYPE_U16
);
1142 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1151 static struct ir3_instruction
*
1152 emit_sam(struct ir3_context
*ctx
, opc_t opc
, struct tex_src_info info
,
1153 type_t type
, unsigned wrmask
, struct ir3_instruction
*src0
,
1154 struct ir3_instruction
*src1
)
1156 struct ir3_instruction
*sam
, *addr
;
1157 if (info
.flags
& IR3_INSTR_A1EN
) {
1158 addr
= ir3_get_addr1(ctx
, info
.a1_val
);
1160 sam
= ir3_SAM(ctx
->block
, opc
, type
, 0b1111, info
.flags
,
1161 info
.samp_tex
, src0
, src1
);
1162 if (info
.flags
& IR3_INSTR_A1EN
) {
1163 ir3_instr_set_address(sam
, addr
);
1165 if (info
.flags
& IR3_INSTR_B
) {
1166 sam
->cat5
.tex_base
= info
.base
;
1167 sam
->cat5
.samp
= info
.combined_idx
;
1172 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1174 emit_intrinsic_load_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1175 struct ir3_instruction
**dst
)
1177 struct ir3_block
*b
= ctx
->block
;
1178 struct tex_src_info info
= get_image_samp_tex_src(ctx
, intr
);
1179 struct ir3_instruction
*sam
;
1180 struct ir3_instruction
* const *src0
= ir3_get_src(ctx
, &intr
->src
[1]);
1181 struct ir3_instruction
*coords
[4];
1182 unsigned flags
, ncoords
= ir3_get_image_coords(intr
, &flags
);
1183 type_t type
= ir3_get_type_for_image_intrinsic(intr
);
1185 /* hmm, this seems a bit odd, but it is what blob does and (at least
1186 * a5xx) just faults on bogus addresses otherwise:
1188 if (flags
& IR3_INSTR_3D
) {
1189 flags
&= ~IR3_INSTR_3D
;
1190 flags
|= IR3_INSTR_A
;
1192 info
.flags
|= flags
;
1194 for (unsigned i
= 0; i
< ncoords
; i
++)
1195 coords
[i
] = src0
[i
];
1198 coords
[ncoords
++] = create_immed(b
, 0);
1200 sam
= emit_sam(ctx
, OPC_ISAM
, info
, type
, 0b1111,
1201 ir3_create_collect(ctx
, coords
, ncoords
), NULL
);
1203 sam
->barrier_class
= IR3_BARRIER_IMAGE_R
;
1204 sam
->barrier_conflict
= IR3_BARRIER_IMAGE_W
;
1206 ir3_split_dest(b
, dst
, sam
, 0, 4);
1209 /* A4xx version of image_size, see ir3_a6xx.c for newer resinfo version. */
1211 emit_intrinsic_image_size_tex(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1212 struct ir3_instruction
**dst
)
1214 struct ir3_block
*b
= ctx
->block
;
1215 struct tex_src_info info
= get_image_samp_tex_src(ctx
, intr
);
1216 struct ir3_instruction
*sam
, *lod
;
1217 unsigned flags
, ncoords
= ir3_get_image_coords(intr
, &flags
);
1218 type_t dst_type
= nir_dest_bit_size(intr
->dest
) == 16 ?
1219 TYPE_U16
: TYPE_U32
;
1221 info
.flags
|= flags
;
1222 lod
= create_immed(b
, 0);
1223 sam
= emit_sam(ctx
, OPC_GETSIZE
, info
, dst_type
, 0b1111, lod
, NULL
);
1225 /* Array size actually ends up in .w rather than .z. This doesn't
1226 * matter for miplevel 0, but for higher mips the value in z is
1227 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1228 * returned, which means that we have to add 1 to it for arrays for
1231 * Note use a temporary dst and then copy, since the size of the dst
1232 * array that is passed in is based on nir's understanding of the
1233 * result size, not the hardware's
1235 struct ir3_instruction
*tmp
[4];
1237 ir3_split_dest(b
, tmp
, sam
, 0, 4);
1239 /* get_size instruction returns size in bytes instead of texels
1240 * for imageBuffer, so we need to divide it by the pixel size
1241 * of the image format.
1243 * TODO: This is at least true on a5xx. Check other gens.
1245 if (nir_intrinsic_image_dim(intr
) == GLSL_SAMPLER_DIM_BUF
) {
1246 /* Since all the possible values the divisor can take are
1247 * power-of-two (4, 8, or 16), the division is implemented
1249 * During shader setup, the log2 of the image format's
1250 * bytes-per-pixel should have been emitted in 2nd slot of
1251 * image_dims. See ir3_shader::emit_image_dims().
1253 const struct ir3_const_state
*const_state
=
1254 ir3_const_state(ctx
->so
);
1255 unsigned cb
= regid(const_state
->offsets
.image_dims
, 0) +
1256 const_state
->image_dims
.off
[nir_src_as_uint(intr
->src
[0])];
1257 struct ir3_instruction
*aux
= create_uniform(b
, cb
+ 1);
1259 tmp
[0] = ir3_SHR_B(b
, tmp
[0], 0, aux
, 0);
1262 for (unsigned i
= 0; i
< ncoords
; i
++)
1265 if (flags
& IR3_INSTR_A
) {
1266 if (ctx
->compiler
->levels_add_one
) {
1267 dst
[ncoords
-1] = ir3_ADD_U(b
, tmp
[3], 0, create_immed(b
, 1), 0);
1269 dst
[ncoords
-1] = ir3_MOV(b
, tmp
[3], TYPE_U32
);
1275 emit_intrinsic_barrier(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1277 struct ir3_block
*b
= ctx
->block
;
1278 struct ir3_instruction
*barrier
;
1280 switch (intr
->intrinsic
) {
1281 case nir_intrinsic_control_barrier
:
1282 barrier
= ir3_BAR(b
);
1283 barrier
->cat7
.g
= true;
1284 barrier
->cat7
.l
= true;
1285 barrier
->flags
= IR3_INSTR_SS
| IR3_INSTR_SY
;
1286 barrier
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1288 case nir_intrinsic_memory_barrier
:
1289 barrier
= ir3_FENCE(b
);
1290 barrier
->cat7
.g
= true;
1291 barrier
->cat7
.r
= true;
1292 barrier
->cat7
.w
= true;
1293 barrier
->cat7
.l
= true;
1294 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
|
1295 IR3_BARRIER_BUFFER_W
;
1296 barrier
->barrier_conflict
=
1297 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1298 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1300 case nir_intrinsic_memory_barrier_buffer
:
1301 barrier
= ir3_FENCE(b
);
1302 barrier
->cat7
.g
= true;
1303 barrier
->cat7
.r
= true;
1304 barrier
->cat7
.w
= true;
1305 barrier
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1306 barrier
->barrier_conflict
= IR3_BARRIER_BUFFER_R
|
1307 IR3_BARRIER_BUFFER_W
;
1309 case nir_intrinsic_memory_barrier_image
:
1310 // TODO double check if this should have .g set
1311 barrier
= ir3_FENCE(b
);
1312 barrier
->cat7
.g
= true;
1313 barrier
->cat7
.r
= true;
1314 barrier
->cat7
.w
= true;
1315 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1316 barrier
->barrier_conflict
= IR3_BARRIER_IMAGE_R
|
1317 IR3_BARRIER_IMAGE_W
;
1319 case nir_intrinsic_memory_barrier_shared
:
1320 barrier
= ir3_FENCE(b
);
1321 barrier
->cat7
.g
= true;
1322 barrier
->cat7
.l
= true;
1323 barrier
->cat7
.r
= true;
1324 barrier
->cat7
.w
= true;
1325 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
;
1326 barrier
->barrier_conflict
= IR3_BARRIER_SHARED_R
|
1327 IR3_BARRIER_SHARED_W
;
1329 case nir_intrinsic_group_memory_barrier
:
1330 barrier
= ir3_FENCE(b
);
1331 barrier
->cat7
.g
= true;
1332 barrier
->cat7
.l
= true;
1333 barrier
->cat7
.r
= true;
1334 barrier
->cat7
.w
= true;
1335 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
|
1336 IR3_BARRIER_IMAGE_W
|
1337 IR3_BARRIER_BUFFER_W
;
1338 barrier
->barrier_conflict
=
1339 IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
|
1340 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1341 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1347 /* make sure barrier doesn't get DCE'd */
1348 array_insert(b
, b
->keeps
, barrier
);
1351 static void add_sysval_input_compmask(struct ir3_context
*ctx
,
1352 gl_system_value slot
, unsigned compmask
,
1353 struct ir3_instruction
*instr
)
1355 struct ir3_shader_variant
*so
= ctx
->so
;
1356 unsigned n
= so
->inputs_count
++;
1358 assert(instr
->opc
== OPC_META_INPUT
);
1359 instr
->input
.inidx
= n
;
1360 instr
->input
.sysval
= slot
;
1362 so
->inputs
[n
].sysval
= true;
1363 so
->inputs
[n
].slot
= slot
;
1364 so
->inputs
[n
].compmask
= compmask
;
1365 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
1369 static struct ir3_instruction
*
1370 create_sysval_input(struct ir3_context
*ctx
, gl_system_value slot
,
1374 struct ir3_instruction
*sysval
= create_input(ctx
, compmask
);
1375 add_sysval_input_compmask(ctx
, slot
, compmask
, sysval
);
1379 static struct ir3_instruction
*
1380 get_barycentric(struct ir3_context
*ctx
, enum ir3_bary bary
)
1382 static const gl_system_value sysval_base
= SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
;
1384 STATIC_ASSERT(sysval_base
+ IJ_PERSP_PIXEL
== SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
);
1385 STATIC_ASSERT(sysval_base
+ IJ_PERSP_SAMPLE
== SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE
);
1386 STATIC_ASSERT(sysval_base
+ IJ_PERSP_CENTROID
== SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID
);
1387 STATIC_ASSERT(sysval_base
+ IJ_PERSP_SIZE
== SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE
);
1388 STATIC_ASSERT(sysval_base
+ IJ_LINEAR_PIXEL
== SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL
);
1389 STATIC_ASSERT(sysval_base
+ IJ_LINEAR_CENTROID
== SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID
);
1390 STATIC_ASSERT(sysval_base
+ IJ_LINEAR_SAMPLE
== SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE
);
1392 if (!ctx
->ij
[bary
]) {
1393 struct ir3_instruction
*xy
[2];
1394 struct ir3_instruction
*ij
;
1396 ij
= create_sysval_input(ctx
, sysval_base
+ bary
, 0x3);
1397 ir3_split_dest(ctx
->block
, xy
, ij
, 0, 2);
1399 ctx
->ij
[bary
] = ir3_create_collect(ctx
, xy
, 2);
1402 return ctx
->ij
[bary
];
1405 /* TODO: make this a common NIR helper?
1406 * there is a nir_system_value_from_intrinsic but it takes nir_intrinsic_op so it
1407 * can't be extended to work with this
1409 static gl_system_value
1410 nir_intrinsic_barycentric_sysval(nir_intrinsic_instr
*intr
)
1412 enum glsl_interp_mode interp_mode
= nir_intrinsic_interp_mode(intr
);
1413 gl_system_value sysval
;
1415 switch (intr
->intrinsic
) {
1416 case nir_intrinsic_load_barycentric_pixel
:
1417 if (interp_mode
== INTERP_MODE_NOPERSPECTIVE
)
1418 sysval
= SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL
;
1420 sysval
= SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
;
1422 case nir_intrinsic_load_barycentric_centroid
:
1423 if (interp_mode
== INTERP_MODE_NOPERSPECTIVE
)
1424 sysval
= SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID
;
1426 sysval
= SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID
;
1428 case nir_intrinsic_load_barycentric_sample
:
1429 if (interp_mode
== INTERP_MODE_NOPERSPECTIVE
)
1430 sysval
= SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE
;
1432 sysval
= SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE
;
1435 unreachable("invalid barycentric intrinsic");
1442 emit_intrinsic_barycentric(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1443 struct ir3_instruction
**dst
)
1445 gl_system_value sysval
= nir_intrinsic_barycentric_sysval(intr
);
1447 if (!ctx
->so
->key
.msaa
) {
1448 if (sysval
== SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE
)
1449 sysval
= SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
;
1450 if (sysval
== SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE
)
1451 sysval
= SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL
;
1454 enum ir3_bary bary
= sysval
- SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
;
1456 struct ir3_instruction
*ij
= get_barycentric(ctx
, bary
);
1457 ir3_split_dest(ctx
->block
, dst
, ij
, 0, 2);
1460 static struct ir3_instruction
*
1461 get_frag_coord(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1463 if (!ctx
->frag_coord
) {
1464 struct ir3_block
*b
= ctx
->in_block
;
1465 struct ir3_instruction
*xyzw
[4];
1466 struct ir3_instruction
*hw_frag_coord
;
1468 hw_frag_coord
= create_sysval_input(ctx
, SYSTEM_VALUE_FRAG_COORD
, 0xf);
1469 ir3_split_dest(b
, xyzw
, hw_frag_coord
, 0, 4);
1471 /* for frag_coord.xy, we get unsigned values.. we need
1472 * to subtract (integer) 8 and divide by 16 (right-
1473 * shift by 4) then convert to float:
1477 * mov.u32f32 dst, tmp
1480 for (int i
= 0; i
< 2; i
++) {
1481 xyzw
[i
] = ir3_COV(b
, xyzw
[i
], TYPE_U32
, TYPE_F32
);
1482 xyzw
[i
] = ir3_MUL_F(b
, xyzw
[i
], 0, create_immed(b
, fui(1.0 / 16.0)), 0);
1485 ctx
->frag_coord
= ir3_create_collect(ctx
, xyzw
, 4);
1488 ctx
->so
->fragcoord_compmask
|=
1489 nir_ssa_def_components_read(&intr
->dest
.ssa
);
1491 return ctx
->frag_coord
;
1495 emit_intrinsic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1497 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1498 struct ir3_instruction
**dst
;
1499 struct ir3_instruction
* const *src
;
1500 struct ir3_block
*b
= ctx
->block
;
1501 unsigned dest_components
= nir_intrinsic_dest_components(intr
);
1504 if (info
->has_dest
) {
1505 dst
= ir3_get_dst(ctx
, &intr
->dest
, dest_components
);
1510 const struct ir3_const_state
*const_state
= ir3_const_state(ctx
->so
);
1511 const unsigned primitive_param
= const_state
->offsets
.primitive_param
* 4;
1512 const unsigned primitive_map
= const_state
->offsets
.primitive_map
* 4;
1514 switch (intr
->intrinsic
) {
1515 case nir_intrinsic_load_uniform
:
1516 idx
= nir_intrinsic_base(intr
);
1517 if (nir_src_is_const(intr
->src
[0])) {
1518 idx
+= nir_src_as_uint(intr
->src
[0]);
1519 for (int i
= 0; i
< dest_components
; i
++) {
1520 dst
[i
] = create_uniform_typed(b
, idx
+ i
,
1521 nir_dest_bit_size(intr
->dest
) == 16 ? TYPE_F16
: TYPE_F32
);
1524 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1525 for (int i
= 0; i
< dest_components
; i
++) {
1526 dst
[i
] = create_uniform_indirect(b
, idx
+ i
,
1527 ir3_get_addr0(ctx
, src
[0], 1));
1529 /* NOTE: if relative addressing is used, we set
1530 * constlen in the compiler (to worst-case value)
1531 * since we don't know in the assembler what the max
1532 * addr reg value can be:
1534 ctx
->so
->constlen
= MAX2(ctx
->so
->constlen
,
1535 const_state
->ubo_state
.size
/ 16);
1539 case nir_intrinsic_load_vs_primitive_stride_ir3
:
1540 dst
[0] = create_uniform(b
, primitive_param
+ 0);
1542 case nir_intrinsic_load_vs_vertex_stride_ir3
:
1543 dst
[0] = create_uniform(b
, primitive_param
+ 1);
1545 case nir_intrinsic_load_hs_patch_stride_ir3
:
1546 dst
[0] = create_uniform(b
, primitive_param
+ 2);
1548 case nir_intrinsic_load_patch_vertices_in
:
1549 dst
[0] = create_uniform(b
, primitive_param
+ 3);
1551 case nir_intrinsic_load_tess_param_base_ir3
:
1552 dst
[0] = create_uniform(b
, primitive_param
+ 4);
1553 dst
[1] = create_uniform(b
, primitive_param
+ 5);
1555 case nir_intrinsic_load_tess_factor_base_ir3
:
1556 dst
[0] = create_uniform(b
, primitive_param
+ 6);
1557 dst
[1] = create_uniform(b
, primitive_param
+ 7);
1560 case nir_intrinsic_load_primitive_location_ir3
:
1561 idx
= nir_intrinsic_driver_location(intr
);
1562 dst
[0] = create_uniform(b
, primitive_map
+ idx
);
1565 case nir_intrinsic_load_gs_header_ir3
:
1566 dst
[0] = ctx
->gs_header
;
1568 case nir_intrinsic_load_tcs_header_ir3
:
1569 dst
[0] = ctx
->tcs_header
;
1572 case nir_intrinsic_load_primitive_id
:
1573 dst
[0] = ctx
->primitive_id
;
1576 case nir_intrinsic_load_tess_coord
:
1577 if (!ctx
->tess_coord
) {
1579 create_sysval_input(ctx
, SYSTEM_VALUE_TESS_COORD
, 0x3);
1581 ir3_split_dest(b
, dst
, ctx
->tess_coord
, 0, 2);
1583 /* Unused, but ir3_put_dst() below wants to free something */
1584 dst
[2] = create_immed(b
, 0);
1587 case nir_intrinsic_end_patch_ir3
:
1588 assert(ctx
->so
->type
== MESA_SHADER_TESS_CTRL
);
1589 struct ir3_instruction
*end
= ir3_PREDE(b
);
1590 array_insert(b
, b
->keeps
, end
);
1592 end
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1593 end
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
1596 case nir_intrinsic_store_global_ir3
: {
1597 struct ir3_instruction
*value
, *addr
, *offset
;
1598 unsigned ncomp
= nir_intrinsic_src_components(intr
, 0);
1600 addr
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1601 ir3_get_src(ctx
, &intr
->src
[1])[0],
1602 ir3_get_src(ctx
, &intr
->src
[1])[1]
1605 offset
= ir3_get_src(ctx
, &intr
->src
[2])[0];
1607 value
= ir3_create_collect(ctx
, ir3_get_src(ctx
, &intr
->src
[0]), ncomp
);
1609 struct ir3_instruction
*stg
=
1610 ir3_STG_G(ctx
->block
, addr
, 0, value
, 0,
1611 create_immed(ctx
->block
, ncomp
), 0, offset
, 0);
1612 stg
->cat6
.type
= TYPE_U32
;
1613 stg
->cat6
.iim_val
= 1;
1615 array_insert(b
, b
->keeps
, stg
);
1617 stg
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1618 stg
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1622 case nir_intrinsic_load_global_ir3
: {
1623 struct ir3_instruction
*addr
, *offset
;
1625 addr
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1626 ir3_get_src(ctx
, &intr
->src
[0])[0],
1627 ir3_get_src(ctx
, &intr
->src
[0])[1]
1630 offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
1632 struct ir3_instruction
*load
=
1633 ir3_LDG(b
, addr
, 0, create_immed(ctx
->block
, dest_components
),
1635 load
->cat6
.type
= TYPE_U32
;
1636 load
->regs
[0]->wrmask
= MASK(dest_components
);
1638 load
->barrier_class
= IR3_BARRIER_BUFFER_R
;
1639 load
->barrier_conflict
= IR3_BARRIER_BUFFER_W
;
1641 ir3_split_dest(b
, dst
, load
, 0, dest_components
);
1645 case nir_intrinsic_load_ubo
:
1646 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1648 case nir_intrinsic_load_ubo_ir3
:
1649 emit_intrinsic_load_ubo_ldc(ctx
, intr
, dst
);
1651 case nir_intrinsic_load_frag_coord
:
1652 ir3_split_dest(b
, dst
, get_frag_coord(ctx
, intr
), 0, 4);
1654 case nir_intrinsic_load_sample_pos_from_id
: {
1655 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1656 * but that doesn't seem necessary.
1658 struct ir3_instruction
*offset
=
1659 ir3_RGETPOS(b
, ir3_get_src(ctx
, &intr
->src
[0])[0], 0);
1660 offset
->regs
[0]->wrmask
= 0x3;
1661 offset
->cat5
.type
= TYPE_F32
;
1663 ir3_split_dest(b
, dst
, offset
, 0, 2);
1667 case nir_intrinsic_load_size_ir3
:
1668 if (!ctx
->ij
[IJ_PERSP_SIZE
]) {
1669 ctx
->ij
[IJ_PERSP_SIZE
] =
1670 create_sysval_input(ctx
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE
, 0x1);
1672 dst
[0] = ctx
->ij
[IJ_PERSP_SIZE
];
1674 case nir_intrinsic_load_barycentric_centroid
:
1675 case nir_intrinsic_load_barycentric_sample
:
1676 case nir_intrinsic_load_barycentric_pixel
:
1677 emit_intrinsic_barycentric(ctx
, intr
, dst
);
1679 case nir_intrinsic_load_interpolated_input
:
1680 idx
= nir_intrinsic_base(intr
);
1681 comp
= nir_intrinsic_component(intr
);
1682 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1683 if (nir_src_is_const(intr
->src
[1])) {
1684 struct ir3_instruction
*coord
= ir3_create_collect(ctx
, src
, 2);
1685 idx
+= nir_src_as_uint(intr
->src
[1]);
1686 for (int i
= 0; i
< dest_components
; i
++) {
1687 unsigned inloc
= idx
* 4 + i
+ comp
;
1688 if (ctx
->so
->inputs
[idx
].bary
&&
1689 !ctx
->so
->inputs
[idx
].use_ldlv
) {
1690 dst
[i
] = ir3_BARY_F(b
, create_immed(b
, inloc
), 0, coord
, 0);
1692 /* for non-varyings use the pre-setup input, since
1693 * that is easier than mapping things back to a
1694 * nir_variable to figure out what it is.
1696 dst
[i
] = ctx
->inputs
[inloc
];
1697 compile_assert(ctx
, dst
[i
]);
1701 ir3_context_error(ctx
, "unhandled");
1704 case nir_intrinsic_load_input
:
1705 idx
= nir_intrinsic_base(intr
);
1706 comp
= nir_intrinsic_component(intr
);
1707 if (nir_src_is_const(intr
->src
[0])) {
1708 idx
+= nir_src_as_uint(intr
->src
[0]);
1709 for (int i
= 0; i
< dest_components
; i
++) {
1710 unsigned n
= idx
* 4 + i
+ comp
;
1711 dst
[i
] = ctx
->inputs
[n
];
1712 compile_assert(ctx
, ctx
->inputs
[n
]);
1715 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1716 struct ir3_instruction
*collect
=
1717 ir3_create_collect(ctx
, ctx
->ir
->inputs
, ctx
->ninputs
);
1718 struct ir3_instruction
*addr
= ir3_get_addr0(ctx
, src
[0], 4);
1719 for (int i
= 0; i
< dest_components
; i
++) {
1720 unsigned n
= idx
* 4 + i
+ comp
;
1721 dst
[i
] = create_indirect_load(ctx
, ctx
->ninputs
,
1726 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1727 * pass and replaced by an ir3-specifc version that adds the
1728 * dword-offset in the last source.
1730 case nir_intrinsic_load_ssbo_ir3
:
1731 ctx
->funcs
->emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
1733 case nir_intrinsic_store_ssbo_ir3
:
1734 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1735 !ctx
->s
->info
.fs
.early_fragment_tests
)
1736 ctx
->so
->no_earlyz
= true;
1737 ctx
->funcs
->emit_intrinsic_store_ssbo(ctx
, intr
);
1739 case nir_intrinsic_get_buffer_size
:
1740 emit_intrinsic_ssbo_size(ctx
, intr
, dst
);
1742 case nir_intrinsic_ssbo_atomic_add_ir3
:
1743 case nir_intrinsic_ssbo_atomic_imin_ir3
:
1744 case nir_intrinsic_ssbo_atomic_umin_ir3
:
1745 case nir_intrinsic_ssbo_atomic_imax_ir3
:
1746 case nir_intrinsic_ssbo_atomic_umax_ir3
:
1747 case nir_intrinsic_ssbo_atomic_and_ir3
:
1748 case nir_intrinsic_ssbo_atomic_or_ir3
:
1749 case nir_intrinsic_ssbo_atomic_xor_ir3
:
1750 case nir_intrinsic_ssbo_atomic_exchange_ir3
:
1751 case nir_intrinsic_ssbo_atomic_comp_swap_ir3
:
1752 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1753 !ctx
->s
->info
.fs
.early_fragment_tests
)
1754 ctx
->so
->no_earlyz
= true;
1755 dst
[0] = ctx
->funcs
->emit_intrinsic_atomic_ssbo(ctx
, intr
);
1757 case nir_intrinsic_load_shared
:
1758 emit_intrinsic_load_shared(ctx
, intr
, dst
);
1760 case nir_intrinsic_store_shared
:
1761 emit_intrinsic_store_shared(ctx
, intr
);
1763 case nir_intrinsic_shared_atomic_add
:
1764 case nir_intrinsic_shared_atomic_imin
:
1765 case nir_intrinsic_shared_atomic_umin
:
1766 case nir_intrinsic_shared_atomic_imax
:
1767 case nir_intrinsic_shared_atomic_umax
:
1768 case nir_intrinsic_shared_atomic_and
:
1769 case nir_intrinsic_shared_atomic_or
:
1770 case nir_intrinsic_shared_atomic_xor
:
1771 case nir_intrinsic_shared_atomic_exchange
:
1772 case nir_intrinsic_shared_atomic_comp_swap
:
1773 dst
[0] = emit_intrinsic_atomic_shared(ctx
, intr
);
1775 case nir_intrinsic_image_load
:
1776 emit_intrinsic_load_image(ctx
, intr
, dst
);
1778 case nir_intrinsic_bindless_image_load
:
1779 /* Bindless uses the IBO state, which doesn't have swizzle filled out,
1780 * so using isam doesn't work.
1782 * TODO: can we use isam if we fill out more fields?
1784 ctx
->funcs
->emit_intrinsic_load_image(ctx
, intr
, dst
);
1786 case nir_intrinsic_image_store
:
1787 case nir_intrinsic_bindless_image_store
:
1788 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1789 !ctx
->s
->info
.fs
.early_fragment_tests
)
1790 ctx
->so
->no_earlyz
= true;
1791 ctx
->funcs
->emit_intrinsic_store_image(ctx
, intr
);
1793 case nir_intrinsic_image_size
:
1794 case nir_intrinsic_bindless_image_size
:
1795 ctx
->funcs
->emit_intrinsic_image_size(ctx
, intr
, dst
);
1797 case nir_intrinsic_image_atomic_add
:
1798 case nir_intrinsic_bindless_image_atomic_add
:
1799 case nir_intrinsic_image_atomic_imin
:
1800 case nir_intrinsic_bindless_image_atomic_imin
:
1801 case nir_intrinsic_image_atomic_umin
:
1802 case nir_intrinsic_bindless_image_atomic_umin
:
1803 case nir_intrinsic_image_atomic_imax
:
1804 case nir_intrinsic_bindless_image_atomic_imax
:
1805 case nir_intrinsic_image_atomic_umax
:
1806 case nir_intrinsic_bindless_image_atomic_umax
:
1807 case nir_intrinsic_image_atomic_and
:
1808 case nir_intrinsic_bindless_image_atomic_and
:
1809 case nir_intrinsic_image_atomic_or
:
1810 case nir_intrinsic_bindless_image_atomic_or
:
1811 case nir_intrinsic_image_atomic_xor
:
1812 case nir_intrinsic_bindless_image_atomic_xor
:
1813 case nir_intrinsic_image_atomic_exchange
:
1814 case nir_intrinsic_bindless_image_atomic_exchange
:
1815 case nir_intrinsic_image_atomic_comp_swap
:
1816 case nir_intrinsic_bindless_image_atomic_comp_swap
:
1817 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1818 !ctx
->s
->info
.fs
.early_fragment_tests
)
1819 ctx
->so
->no_earlyz
= true;
1820 dst
[0] = ctx
->funcs
->emit_intrinsic_atomic_image(ctx
, intr
);
1822 case nir_intrinsic_control_barrier
:
1823 case nir_intrinsic_memory_barrier
:
1824 case nir_intrinsic_group_memory_barrier
:
1825 case nir_intrinsic_memory_barrier_buffer
:
1826 case nir_intrinsic_memory_barrier_image
:
1827 case nir_intrinsic_memory_barrier_shared
:
1828 emit_intrinsic_barrier(ctx
, intr
);
1829 /* note that blk ptr no longer valid, make that obvious: */
1832 case nir_intrinsic_store_output
:
1833 idx
= nir_intrinsic_base(intr
);
1834 comp
= nir_intrinsic_component(intr
);
1835 compile_assert(ctx
, nir_src_is_const(intr
->src
[1]));
1836 idx
+= nir_src_as_uint(intr
->src
[1]);
1838 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1839 for (int i
= 0; i
< nir_intrinsic_src_components(intr
, 0); i
++) {
1840 unsigned n
= idx
* 4 + i
+ comp
;
1841 ctx
->outputs
[n
] = src
[i
];
1844 case nir_intrinsic_load_base_vertex
:
1845 case nir_intrinsic_load_first_vertex
:
1846 if (!ctx
->basevertex
) {
1847 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
1849 dst
[0] = ctx
->basevertex
;
1851 case nir_intrinsic_load_draw_id
:
1852 if (!ctx
->draw_id
) {
1853 ctx
->draw_id
= create_driver_param(ctx
, IR3_DP_DRAWID
);
1855 dst
[0] = ctx
->draw_id
;
1857 case nir_intrinsic_load_base_instance
:
1858 if (!ctx
->base_instance
) {
1859 ctx
->base_instance
= create_driver_param(ctx
, IR3_DP_INSTID_BASE
);
1861 dst
[0] = ctx
->base_instance
;
1863 case nir_intrinsic_load_vertex_id_zero_base
:
1864 case nir_intrinsic_load_vertex_id
:
1865 if (!ctx
->vertex_id
) {
1866 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
1867 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
1868 ctx
->vertex_id
= create_sysval_input(ctx
, sv
, 0x1);
1870 dst
[0] = ctx
->vertex_id
;
1872 case nir_intrinsic_load_instance_id
:
1873 if (!ctx
->instance_id
) {
1874 ctx
->instance_id
= create_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
, 0x1);
1876 dst
[0] = ctx
->instance_id
;
1878 case nir_intrinsic_load_sample_id
:
1879 ctx
->so
->per_samp
= true;
1881 case nir_intrinsic_load_sample_id_no_per_sample
:
1882 if (!ctx
->samp_id
) {
1883 ctx
->samp_id
= create_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_ID
, 0x1);
1884 ctx
->samp_id
->regs
[0]->flags
|= IR3_REG_HALF
;
1886 dst
[0] = ir3_COV(b
, ctx
->samp_id
, TYPE_U16
, TYPE_U32
);
1888 case nir_intrinsic_load_sample_mask_in
:
1889 if (!ctx
->samp_mask_in
) {
1890 ctx
->samp_mask_in
= create_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_MASK_IN
, 0x1);
1892 dst
[0] = ctx
->samp_mask_in
;
1894 case nir_intrinsic_load_user_clip_plane
:
1895 idx
= nir_intrinsic_ucp_id(intr
);
1896 for (int i
= 0; i
< dest_components
; i
++) {
1897 unsigned n
= idx
* 4 + i
;
1898 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
1901 case nir_intrinsic_load_front_face
:
1902 if (!ctx
->frag_face
) {
1903 ctx
->so
->frag_face
= true;
1904 ctx
->frag_face
= create_sysval_input(ctx
, SYSTEM_VALUE_FRONT_FACE
, 0x1);
1905 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
1907 /* for fragface, we get -1 for back and 0 for front. However this is
1908 * the inverse of what nir expects (where ~0 is true).
1910 dst
[0] = ir3_CMPS_S(b
,
1912 create_immed_typed(b
, 0, TYPE_U16
), 0);
1913 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1915 case nir_intrinsic_load_local_invocation_id
:
1916 if (!ctx
->local_invocation_id
) {
1917 ctx
->local_invocation_id
=
1918 create_sysval_input(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
, 0x7);
1920 ir3_split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
1922 case nir_intrinsic_load_work_group_id
:
1923 if (!ctx
->work_group_id
) {
1924 ctx
->work_group_id
=
1925 create_sysval_input(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
, 0x7);
1926 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
1928 ir3_split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
1930 case nir_intrinsic_load_num_work_groups
:
1931 for (int i
= 0; i
< dest_components
; i
++) {
1932 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
1935 case nir_intrinsic_load_local_group_size
:
1936 for (int i
= 0; i
< dest_components
; i
++) {
1937 dst
[i
] = create_driver_param(ctx
, IR3_DP_LOCAL_GROUP_SIZE_X
+ i
);
1940 case nir_intrinsic_discard_if
:
1941 case nir_intrinsic_discard
: {
1942 struct ir3_instruction
*cond
, *kill
;
1944 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1945 /* conditional discard: */
1946 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1949 /* unconditional discard: */
1950 cond
= create_immed(b
, 1);
1953 /* NOTE: only cmps.*.* can write p0.x: */
1954 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1955 cond
->cat2
.condition
= IR3_COND_NE
;
1957 /* condition always goes in predicate register: */
1958 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1959 cond
->regs
[0]->flags
&= ~IR3_REG_SSA
;
1961 kill
= ir3_KILL(b
, cond
, 0);
1962 kill
->regs
[1]->num
= regid(REG_P0
, 0);
1963 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
1965 array_insert(b
, b
->keeps
, kill
);
1966 ctx
->so
->has_kill
= true;
1971 case nir_intrinsic_cond_end_ir3
: {
1972 struct ir3_instruction
*cond
, *kill
;
1974 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1977 /* NOTE: only cmps.*.* can write p0.x: */
1978 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1979 cond
->cat2
.condition
= IR3_COND_NE
;
1981 /* condition always goes in predicate register: */
1982 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1984 kill
= ir3_PREDT(b
, cond
, 0);
1986 kill
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1987 kill
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
1989 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
1990 array_insert(b
, b
->keeps
, kill
);
1994 case nir_intrinsic_load_shared_ir3
:
1995 emit_intrinsic_load_shared_ir3(ctx
, intr
, dst
);
1997 case nir_intrinsic_store_shared_ir3
:
1998 emit_intrinsic_store_shared_ir3(ctx
, intr
);
2000 case nir_intrinsic_bindless_resource_ir3
:
2001 dst
[0] = ir3_get_src(ctx
, &intr
->src
[0])[0];
2004 ir3_context_error(ctx
, "Unhandled intrinsic type: %s\n",
2005 nir_intrinsic_infos
[intr
->intrinsic
].name
);
2010 ir3_put_dst(ctx
, &intr
->dest
);
2014 emit_load_const(struct ir3_context
*ctx
, nir_load_const_instr
*instr
)
2016 struct ir3_instruction
**dst
= ir3_get_dst_ssa(ctx
, &instr
->def
,
2017 instr
->def
.num_components
);
2019 if (instr
->def
.bit_size
== 16) {
2020 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
2021 dst
[i
] = create_immed_typed(ctx
->block
,
2022 instr
->value
[i
].u16
,
2025 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
2026 dst
[i
] = create_immed_typed(ctx
->block
,
2027 instr
->value
[i
].u32
,
2034 emit_undef(struct ir3_context
*ctx
, nir_ssa_undef_instr
*undef
)
2036 struct ir3_instruction
**dst
= ir3_get_dst_ssa(ctx
, &undef
->def
,
2037 undef
->def
.num_components
);
2038 type_t type
= (undef
->def
.bit_size
== 16) ? TYPE_U16
: TYPE_U32
;
2040 /* backend doesn't want undefined instructions, so just plug
2043 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
2044 dst
[i
] = create_immed_typed(ctx
->block
, fui(0.0), type
);
2048 * texture fetch/sample instructions:
2052 get_tex_dest_type(nir_tex_instr
*tex
)
2056 switch (nir_alu_type_get_base_type(tex
->dest_type
)) {
2057 case nir_type_invalid
:
2058 case nir_type_float
:
2059 type
= nir_dest_bit_size(tex
->dest
) == 16 ? TYPE_F16
: TYPE_F32
;
2062 type
= nir_dest_bit_size(tex
->dest
) == 16 ? TYPE_S16
: TYPE_S32
;
2066 type
= nir_dest_bit_size(tex
->dest
) == 16 ? TYPE_U16
: TYPE_U32
;
2069 unreachable("bad dest_type");
2076 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
2078 unsigned coords
= glsl_get_sampler_dim_coordinate_components(tex
->sampler_dim
);
2081 /* note: would use tex->coord_components.. except txs.. also,
2082 * since array index goes after shadow ref, we don't want to
2086 flags
|= IR3_INSTR_3D
;
2088 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2089 flags
|= IR3_INSTR_S
;
2091 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
2092 flags
|= IR3_INSTR_A
;
2098 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
2099 * or immediate (in which case it will get lowered later to a non .s2en
2100 * version of the tex instruction which encode tex/samp as immediates:
2102 static struct tex_src_info
2103 get_tex_samp_tex_src(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2105 struct ir3_block
*b
= ctx
->block
;
2106 struct tex_src_info info
= { 0 };
2107 int texture_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_texture_handle
);
2108 int sampler_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_sampler_handle
);
2109 struct ir3_instruction
*texture
, *sampler
;
2111 if (texture_idx
>= 0 || sampler_idx
>= 0) {
2113 info
.flags
|= IR3_INSTR_B
;
2115 /* Gather information required to determine which encoding to
2116 * choose as well as for prefetch.
2118 nir_intrinsic_instr
*bindless_tex
= NULL
;
2120 if (texture_idx
>= 0) {
2121 ctx
->so
->bindless_tex
= true;
2122 bindless_tex
= ir3_bindless_resource(tex
->src
[texture_idx
].src
);
2123 assert(bindless_tex
);
2124 info
.tex_base
= nir_intrinsic_desc_set(bindless_tex
);
2125 tex_const
= nir_src_is_const(bindless_tex
->src
[0]);
2127 info
.tex_idx
= nir_src_as_uint(bindless_tex
->src
[0]);
2129 /* To simplify some of the logic below, assume the index is
2130 * constant 0 when it's not enabled.
2135 nir_intrinsic_instr
*bindless_samp
= NULL
;
2137 if (sampler_idx
>= 0) {
2138 ctx
->so
->bindless_samp
= true;
2139 bindless_samp
= ir3_bindless_resource(tex
->src
[sampler_idx
].src
);
2140 assert(bindless_samp
);
2141 info
.samp_base
= nir_intrinsic_desc_set(bindless_samp
);
2142 samp_const
= nir_src_is_const(bindless_samp
->src
[0]);
2144 info
.samp_idx
= nir_src_as_uint(bindless_samp
->src
[0]);
2150 /* Choose encoding. */
2151 if (tex_const
&& samp_const
&& info
.tex_idx
< 256 && info
.samp_idx
< 256) {
2152 if (info
.tex_idx
< 16 && info
.samp_idx
< 16 &&
2153 (!bindless_tex
|| !bindless_samp
|| info
.tex_base
== info
.samp_base
)) {
2154 /* Everything fits within the instruction */
2155 info
.base
= info
.tex_base
;
2156 info
.combined_idx
= info
.samp_idx
| (info
.tex_idx
<< 4);
2158 info
.base
= info
.tex_base
;
2159 info
.a1_val
= info
.tex_idx
<< 3 | info
.samp_base
;
2160 info
.combined_idx
= info
.samp_idx
;
2161 info
.flags
|= IR3_INSTR_A1EN
;
2163 info
.samp_tex
= NULL
;
2165 info
.flags
|= IR3_INSTR_S2EN
;
2166 /* In the indirect case, we only use a1.x to store the sampler
2167 * base if it differs from the texture base.
2169 if (!bindless_tex
|| !bindless_samp
|| info
.tex_base
== info
.samp_base
) {
2170 info
.base
= info
.tex_base
;
2172 info
.base
= info
.tex_base
;
2173 info
.a1_val
= info
.samp_base
;
2174 info
.flags
|= IR3_INSTR_A1EN
;
2177 /* Note: the indirect source is now a vec2 instead of hvec2, and
2178 * for some reason the texture and sampler are swapped.
2180 struct ir3_instruction
*texture
, *sampler
;
2183 texture
= ir3_get_src(ctx
, &tex
->src
[texture_idx
].src
)[0];
2185 texture
= create_immed(b
, 0);
2188 if (bindless_samp
) {
2189 sampler
= ir3_get_src(ctx
, &tex
->src
[sampler_idx
].src
)[0];
2191 sampler
= create_immed(b
, 0);
2193 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
2199 info
.flags
|= IR3_INSTR_S2EN
;
2200 texture_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_texture_offset
);
2201 sampler_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_sampler_offset
);
2202 if (texture_idx
>= 0) {
2203 texture
= ir3_get_src(ctx
, &tex
->src
[texture_idx
].src
)[0];
2204 texture
= ir3_COV(ctx
->block
, texture
, TYPE_U32
, TYPE_U16
);
2206 /* TODO what to do for dynamic case? I guess we only need the
2207 * max index for astc srgb workaround so maybe not a problem
2208 * to worry about if we don't enable indirect samplers for
2211 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex
->texture_index
);
2212 texture
= create_immed_typed(ctx
->block
, tex
->texture_index
, TYPE_U16
);
2213 info
.tex_idx
= tex
->texture_index
;
2216 if (sampler_idx
>= 0) {
2217 sampler
= ir3_get_src(ctx
, &tex
->src
[sampler_idx
].src
)[0];
2218 sampler
= ir3_COV(ctx
->block
, sampler
, TYPE_U32
, TYPE_U16
);
2220 sampler
= create_immed_typed(ctx
->block
, tex
->sampler_index
, TYPE_U16
);
2221 info
.samp_idx
= tex
->texture_index
;
2224 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
2234 emit_tex(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2236 struct ir3_block
*b
= ctx
->block
;
2237 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
2238 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
2239 struct ir3_instruction
*lod
, *compare
, *proj
, *sample_index
;
2240 struct tex_src_info info
= { 0 };
2241 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
2242 unsigned i
, coords
, flags
, ncomp
;
2243 unsigned nsrc0
= 0, nsrc1
= 0;
2247 ncomp
= nir_dest_num_components(tex
->dest
);
2249 coord
= off
= ddx
= ddy
= NULL
;
2250 lod
= proj
= compare
= sample_index
= NULL
;
2252 dst
= ir3_get_dst(ctx
, &tex
->dest
, ncomp
);
2254 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
2255 switch (tex
->src
[i
].src_type
) {
2256 case nir_tex_src_coord
:
2257 coord
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
2259 case nir_tex_src_bias
:
2260 lod
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2263 case nir_tex_src_lod
:
2264 lod
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2267 case nir_tex_src_comparator
: /* shadow comparator */
2268 compare
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2270 case nir_tex_src_projector
:
2271 proj
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2274 case nir_tex_src_offset
:
2275 off
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
2278 case nir_tex_src_ddx
:
2279 ddx
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
2281 case nir_tex_src_ddy
:
2282 ddy
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
2284 case nir_tex_src_ms_index
:
2285 sample_index
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2287 case nir_tex_src_texture_offset
:
2288 case nir_tex_src_sampler_offset
:
2289 case nir_tex_src_texture_handle
:
2290 case nir_tex_src_sampler_handle
:
2291 /* handled in get_tex_samp_src() */
2294 ir3_context_error(ctx
, "Unhandled NIR tex src type: %d\n",
2295 tex
->src
[i
].src_type
);
2301 case nir_texop_tex_prefetch
:
2302 compile_assert(ctx
, !has_bias
);
2303 compile_assert(ctx
, !has_lod
);
2304 compile_assert(ctx
, !compare
);
2305 compile_assert(ctx
, !has_proj
);
2306 compile_assert(ctx
, !has_off
);
2307 compile_assert(ctx
, !ddx
);
2308 compile_assert(ctx
, !ddy
);
2309 compile_assert(ctx
, !sample_index
);
2310 compile_assert(ctx
, nir_tex_instr_src_index(tex
, nir_tex_src_texture_offset
) < 0);
2311 compile_assert(ctx
, nir_tex_instr_src_index(tex
, nir_tex_src_sampler_offset
) < 0);
2313 if (ctx
->so
->num_sampler_prefetch
< ctx
->prefetch_limit
) {
2314 opc
= OPC_META_TEX_PREFETCH
;
2315 ctx
->so
->num_sampler_prefetch
++;
2319 case nir_texop_tex
: opc
= has_lod
? OPC_SAML
: OPC_SAM
; break;
2320 case nir_texop_txb
: opc
= OPC_SAMB
; break;
2321 case nir_texop_txl
: opc
= OPC_SAML
; break;
2322 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
2323 case nir_texop_txf
: opc
= OPC_ISAML
; break;
2324 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
2326 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2327 * what blob does, seems gather is broken?), and a3xx did
2328 * not support it (but probably could also emulate).
2330 switch (tex
->component
) {
2331 case 0: opc
= OPC_GATHER4R
; break;
2332 case 1: opc
= OPC_GATHER4G
; break;
2333 case 2: opc
= OPC_GATHER4B
; break;
2334 case 3: opc
= OPC_GATHER4A
; break;
2337 case nir_texop_txf_ms_fb
:
2338 case nir_texop_txf_ms
: opc
= OPC_ISAMM
; break;
2340 ir3_context_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
2344 tex_info(tex
, &flags
, &coords
);
2347 * lay out the first argument in the proper order:
2348 * - actual coordinates first
2349 * - shadow reference
2352 * - starting at offset 4, dpdx.xy, dpdy.xy
2354 * bias/lod go into the second arg
2357 /* insert tex coords: */
2358 for (i
= 0; i
< coords
; i
++)
2363 /* scale up integer coords for TXF based on the LOD */
2364 if (ctx
->compiler
->unminify_coords
&& (opc
== OPC_ISAML
)) {
2366 for (i
= 0; i
< coords
; i
++)
2367 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
2371 /* hw doesn't do 1d, so we treat it as 2d with
2372 * height of 1, and patch up the y coord.
2375 src0
[nsrc0
++] = create_immed(b
, 0);
2377 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
2381 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2382 src0
[nsrc0
++] = compare
;
2384 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
2385 struct ir3_instruction
*idx
= coord
[coords
];
2387 /* the array coord for cube arrays needs 0.5 added to it */
2388 if (ctx
->compiler
->array_index_add_half
&& !is_isam(opc
))
2389 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
2391 src0
[nsrc0
++] = idx
;
2395 src0
[nsrc0
++] = proj
;
2396 flags
|= IR3_INSTR_P
;
2399 /* pad to 4, then ddx/ddy: */
2400 if (tex
->op
== nir_texop_txd
) {
2402 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2403 for (i
= 0; i
< coords
; i
++)
2404 src0
[nsrc0
++] = ddx
[i
];
2406 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2407 for (i
= 0; i
< coords
; i
++)
2408 src0
[nsrc0
++] = ddy
[i
];
2410 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2413 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2414 * with scaled x coord according to requested sample:
2416 if (opc
== OPC_ISAMM
) {
2417 if (ctx
->compiler
->txf_ms_with_isaml
) {
2418 /* the samples are laid out in x dimension as
2420 * x_ms = (x << ms) + sample_index;
2422 struct ir3_instruction
*ms
;
2423 ms
= create_immed(b
, (ctx
->samples
>> (2 * tex
->texture_index
)) & 3);
2425 src0
[0] = ir3_SHL_B(b
, src0
[0], 0, ms
, 0);
2426 src0
[0] = ir3_ADD_U(b
, src0
[0], 0, sample_index
, 0);
2430 src0
[nsrc0
++] = sample_index
;
2435 * second argument (if applicable):
2440 if (has_off
| has_lod
| has_bias
) {
2442 unsigned off_coords
= coords
;
2443 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2445 for (i
= 0; i
< off_coords
; i
++)
2446 src1
[nsrc1
++] = off
[i
];
2448 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
2449 flags
|= IR3_INSTR_O
;
2452 if (has_lod
| has_bias
)
2453 src1
[nsrc1
++] = lod
;
2456 type
= get_tex_dest_type(tex
);
2458 if (opc
== OPC_GETLOD
)
2462 if (tex
->op
== nir_texop_txf_ms_fb
) {
2463 /* only expect a single txf_ms_fb per shader: */
2464 compile_assert(ctx
, !ctx
->so
->fb_read
);
2465 compile_assert(ctx
, ctx
->so
->type
== MESA_SHADER_FRAGMENT
);
2467 ctx
->so
->fb_read
= true;
2468 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
2469 create_immed_typed(ctx
->block
, ctx
->so
->num_samp
, TYPE_U16
),
2470 create_immed_typed(ctx
->block
, ctx
->so
->num_samp
, TYPE_U16
),
2472 info
.flags
= IR3_INSTR_S2EN
;
2474 ctx
->so
->num_samp
++;
2476 info
= get_tex_samp_tex_src(ctx
, tex
);
2479 struct ir3_instruction
*col0
= ir3_create_collect(ctx
, src0
, nsrc0
);
2480 struct ir3_instruction
*col1
= ir3_create_collect(ctx
, src1
, nsrc1
);
2482 if (opc
== OPC_META_TEX_PREFETCH
) {
2483 int idx
= nir_tex_instr_src_index(tex
, nir_tex_src_coord
);
2485 compile_assert(ctx
, tex
->src
[idx
].src
.is_ssa
);
2487 sam
= ir3_META_TEX_PREFETCH(b
);
2488 __ssa_dst(sam
)->wrmask
= MASK(ncomp
); /* dst */
2489 __ssa_src(sam
, get_barycentric(ctx
, IJ_PERSP_PIXEL
), 0);
2490 sam
->prefetch
.input_offset
=
2491 ir3_nir_coord_offset(tex
->src
[idx
].src
.ssa
);
2492 /* make sure not to add irrelevant flags like S2EN */
2493 sam
->flags
= flags
| (info
.flags
& IR3_INSTR_B
);
2494 sam
->prefetch
.tex
= info
.tex_idx
;
2495 sam
->prefetch
.samp
= info
.samp_idx
;
2496 sam
->prefetch
.tex_base
= info
.tex_base
;
2497 sam
->prefetch
.samp_base
= info
.samp_base
;
2499 info
.flags
|= flags
;
2500 sam
= emit_sam(ctx
, opc
, info
, type
, MASK(ncomp
), col0
, col1
);
2503 if ((ctx
->astc_srgb
& (1 << tex
->texture_index
)) && !nir_tex_instr_is_query(tex
)) {
2504 assert(opc
!= OPC_META_TEX_PREFETCH
);
2506 /* only need first 3 components: */
2507 sam
->regs
[0]->wrmask
= 0x7;
2508 ir3_split_dest(b
, dst
, sam
, 0, 3);
2510 /* we need to sample the alpha separately with a non-ASTC
2513 sam
= ir3_SAM(b
, opc
, type
, 0b1000, flags
| info
.flags
,
2514 info
.samp_tex
, col0
, col1
);
2516 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
2518 /* fixup .w component: */
2519 ir3_split_dest(b
, &dst
[3], sam
, 3, 1);
2521 /* normal (non-workaround) case: */
2522 ir3_split_dest(b
, dst
, sam
, 0, ncomp
);
2525 /* GETLOD returns results in 4.8 fixed point */
2526 if (opc
== OPC_GETLOD
) {
2527 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
2529 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
2530 for (i
= 0; i
< 2; i
++) {
2531 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_S32
, TYPE_F32
), 0,
2536 ir3_put_dst(ctx
, &tex
->dest
);
2540 emit_tex_info(struct ir3_context
*ctx
, nir_tex_instr
*tex
, unsigned idx
)
2542 struct ir3_block
*b
= ctx
->block
;
2543 struct ir3_instruction
**dst
, *sam
;
2544 type_t dst_type
= get_tex_dest_type(tex
);
2545 struct tex_src_info info
= get_tex_samp_tex_src(ctx
, tex
);
2547 dst
= ir3_get_dst(ctx
, &tex
->dest
, 1);
2549 sam
= emit_sam(ctx
, OPC_GETINFO
, info
, dst_type
, 1 << idx
, NULL
, NULL
);
2551 /* even though there is only one component, since it ends
2552 * up in .y/.z/.w rather than .x, we need a split_dest()
2554 ir3_split_dest(b
, dst
, sam
, idx
, 1);
2556 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2557 * the value in TEX_CONST_0 is zero-based.
2559 if (ctx
->compiler
->levels_add_one
)
2560 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
2562 ir3_put_dst(ctx
, &tex
->dest
);
2566 emit_tex_txs(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2568 struct ir3_block
*b
= ctx
->block
;
2569 struct ir3_instruction
**dst
, *sam
;
2570 struct ir3_instruction
*lod
;
2571 unsigned flags
, coords
;
2572 type_t dst_type
= get_tex_dest_type(tex
);
2573 struct tex_src_info info
= get_tex_samp_tex_src(ctx
, tex
);
2575 tex_info(tex
, &flags
, &coords
);
2576 info
.flags
|= flags
;
2578 /* Actually we want the number of dimensions, not coordinates. This
2579 * distinction only matters for cubes.
2581 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2584 dst
= ir3_get_dst(ctx
, &tex
->dest
, 4);
2586 int lod_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_lod
);
2587 compile_assert(ctx
, lod_idx
>= 0);
2589 lod
= ir3_get_src(ctx
, &tex
->src
[lod_idx
].src
)[0];
2591 sam
= emit_sam(ctx
, OPC_GETSIZE
, info
, dst_type
, 0b1111, lod
, NULL
);
2592 ir3_split_dest(b
, dst
, sam
, 0, 4);
2594 /* Array size actually ends up in .w rather than .z. This doesn't
2595 * matter for miplevel 0, but for higher mips the value in z is
2596 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2597 * returned, which means that we have to add 1 to it for arrays.
2599 if (tex
->is_array
) {
2600 if (ctx
->compiler
->levels_add_one
) {
2601 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
2603 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
2607 ir3_put_dst(ctx
, &tex
->dest
);
2611 emit_jump(struct ir3_context
*ctx
, nir_jump_instr
*jump
)
2613 switch (jump
->type
) {
2614 case nir_jump_break
:
2615 case nir_jump_continue
:
2616 case nir_jump_return
:
2617 /* I *think* we can simply just ignore this, and use the
2618 * successor block link to figure out where we need to
2619 * jump to for break/continue
2623 ir3_context_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
2629 emit_instr(struct ir3_context
*ctx
, nir_instr
*instr
)
2631 switch (instr
->type
) {
2632 case nir_instr_type_alu
:
2633 emit_alu(ctx
, nir_instr_as_alu(instr
));
2635 case nir_instr_type_deref
:
2636 /* ignored, handled as part of the intrinsic they are src to */
2638 case nir_instr_type_intrinsic
:
2639 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2641 case nir_instr_type_load_const
:
2642 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2644 case nir_instr_type_ssa_undef
:
2645 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
2647 case nir_instr_type_tex
: {
2648 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2649 /* couple tex instructions get special-cased:
2653 emit_tex_txs(ctx
, tex
);
2655 case nir_texop_query_levels
:
2656 emit_tex_info(ctx
, tex
, 2);
2658 case nir_texop_texture_samples
:
2659 emit_tex_info(ctx
, tex
, 3);
2667 case nir_instr_type_jump
:
2668 emit_jump(ctx
, nir_instr_as_jump(instr
));
2670 case nir_instr_type_phi
:
2671 /* we have converted phi webs to regs in NIR by now */
2672 ir3_context_error(ctx
, "Unexpected NIR instruction type: %d\n", instr
->type
);
2674 case nir_instr_type_call
:
2675 case nir_instr_type_parallel_copy
:
2676 ir3_context_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
2681 static struct ir3_block
*
2682 get_block(struct ir3_context
*ctx
, const nir_block
*nblock
)
2684 struct ir3_block
*block
;
2685 struct hash_entry
*hentry
;
2687 hentry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
2689 return hentry
->data
;
2691 block
= ir3_block_create(ctx
->ir
);
2692 block
->nblock
= nblock
;
2693 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
2695 set_foreach(nblock
->predecessors
, sentry
) {
2696 _mesa_set_add(block
->predecessors
, get_block(ctx
, sentry
->key
));
2703 emit_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2705 struct ir3_block
*block
= get_block(ctx
, nblock
);
2707 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
2708 if (nblock
->successors
[i
]) {
2709 block
->successors
[i
] =
2710 get_block(ctx
, nblock
->successors
[i
]);
2715 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
2717 /* re-emit addr register in each block if needed: */
2718 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr0_ht
); i
++) {
2719 _mesa_hash_table_destroy(ctx
->addr0_ht
[i
], NULL
);
2720 ctx
->addr0_ht
[i
] = NULL
;
2723 _mesa_hash_table_u64_destroy(ctx
->addr1_ht
, NULL
);
2724 ctx
->addr1_ht
= NULL
;
2726 nir_foreach_instr (instr
, nblock
) {
2727 ctx
->cur_instr
= instr
;
2728 emit_instr(ctx
, instr
);
2729 ctx
->cur_instr
= NULL
;
2734 _mesa_hash_table_clear(ctx
->sel_cond_conversions
, NULL
);
2737 static void emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
);
2740 emit_if(struct ir3_context
*ctx
, nir_if
*nif
)
2742 struct ir3_instruction
*condition
= ir3_get_src(ctx
, &nif
->condition
)[0];
2744 ctx
->block
->condition
= ir3_get_predicate(ctx
, condition
);
2746 emit_cf_list(ctx
, &nif
->then_list
);
2747 emit_cf_list(ctx
, &nif
->else_list
);
2751 emit_loop(struct ir3_context
*ctx
, nir_loop
*nloop
)
2753 emit_cf_list(ctx
, &nloop
->body
);
2758 stack_push(struct ir3_context
*ctx
)
2761 ctx
->max_stack
= MAX2(ctx
->max_stack
, ctx
->stack
);
2765 stack_pop(struct ir3_context
*ctx
)
2767 compile_assert(ctx
, ctx
->stack
> 0);
2772 emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
)
2774 foreach_list_typed (nir_cf_node
, node
, node
, list
) {
2775 switch (node
->type
) {
2776 case nir_cf_node_block
:
2777 emit_block(ctx
, nir_cf_node_as_block(node
));
2779 case nir_cf_node_if
:
2781 emit_if(ctx
, nir_cf_node_as_if(node
));
2784 case nir_cf_node_loop
:
2786 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2789 case nir_cf_node_function
:
2790 ir3_context_error(ctx
, "TODO\n");
2796 /* emit stream-out code. At this point, the current block is the original
2797 * (nir) end block, and nir ensures that all flow control paths terminate
2798 * into the end block. We re-purpose the original end block to generate
2799 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2800 * block holding stream-out write instructions, followed by the new end
2804 * p0.x = (vtxcnt < maxvtxcnt)
2805 * // succs: blockStreamOut, blockNewEnd
2808 * // preds: blockOrigEnd
2809 * ... stream-out instructions ...
2810 * // succs: blockNewEnd
2813 * // preds: blockOrigEnd, blockStreamOut
2817 emit_stream_out(struct ir3_context
*ctx
)
2819 struct ir3
*ir
= ctx
->ir
;
2820 struct ir3_stream_output_info
*strmout
=
2821 &ctx
->so
->shader
->stream_output
;
2822 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2823 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2824 struct ir3_instruction
*bases
[IR3_MAX_SO_BUFFERS
];
2826 /* create vtxcnt input in input block at top of shader,
2827 * so that it is seen as live over the entire duration
2830 vtxcnt
= create_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, 0x1);
2831 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2833 /* at this point, we are at the original 'end' block,
2834 * re-purpose this block to stream-out condition, then
2835 * append stream-out block and new-end block
2837 orig_end_block
= ctx
->block
;
2839 // maybe w/ store_global intrinsic, we could do this
2840 // stuff in nir->nir pass
2842 stream_out_block
= ir3_block_create(ir
);
2843 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2845 new_end_block
= ir3_block_create(ir
);
2846 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2848 orig_end_block
->successors
[0] = stream_out_block
;
2849 orig_end_block
->successors
[1] = new_end_block
;
2851 stream_out_block
->successors
[0] = new_end_block
;
2852 _mesa_set_add(stream_out_block
->predecessors
, orig_end_block
);
2854 _mesa_set_add(new_end_block
->predecessors
, orig_end_block
);
2855 _mesa_set_add(new_end_block
->predecessors
, stream_out_block
);
2857 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2858 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2859 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2860 cond
->regs
[0]->flags
&= ~IR3_REG_SSA
;
2861 cond
->cat2
.condition
= IR3_COND_LT
;
2863 /* condition goes on previous block to the conditional,
2864 * since it is used to pick which of the two successor
2867 orig_end_block
->condition
= cond
;
2869 /* switch to stream_out_block to generate the stream-out
2872 ctx
->block
= stream_out_block
;
2874 /* Calculate base addresses based on vtxcnt. Instructions
2875 * generated for bases not used in following loop will be
2876 * stripped out in the backend.
2878 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
2879 const struct ir3_const_state
*const_state
=
2880 ir3_const_state(ctx
->so
);
2881 unsigned stride
= strmout
->stride
[i
];
2882 struct ir3_instruction
*base
, *off
;
2884 base
= create_uniform(ctx
->block
, regid(const_state
->offsets
.tfbo
, i
));
2886 /* 24-bit should be enough: */
2887 off
= ir3_MUL_U24(ctx
->block
, vtxcnt
, 0,
2888 create_immed(ctx
->block
, stride
* 4), 0);
2890 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2893 /* Generate the per-output store instructions: */
2894 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2895 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2896 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2897 struct ir3_instruction
*base
, *out
, *stg
;
2899 base
= bases
[strmout
->output
[i
].output_buffer
];
2900 out
= ctx
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2902 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2903 create_immed(ctx
->block
, 1), 0);
2904 stg
->cat6
.type
= TYPE_U32
;
2905 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2907 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
2911 /* and finally switch to the new_end_block: */
2912 ctx
->block
= new_end_block
;
2916 emit_function(struct ir3_context
*ctx
, nir_function_impl
*impl
)
2918 nir_metadata_require(impl
, nir_metadata_block_index
);
2920 compile_assert(ctx
, ctx
->stack
== 0);
2922 emit_cf_list(ctx
, &impl
->body
);
2923 emit_block(ctx
, impl
->end_block
);
2925 compile_assert(ctx
, ctx
->stack
== 0);
2927 /* at this point, we should have a single empty block,
2928 * into which we emit the 'end' instruction.
2930 compile_assert(ctx
, list_is_empty(&ctx
->block
->instr_list
));
2932 /* If stream-out (aka transform-feedback) enabled, emit the
2933 * stream-out instructions, followed by a new empty block (into
2934 * which the 'end' instruction lands).
2936 * NOTE: it is done in this order, rather than inserting before
2937 * we emit end_block, because NIR guarantees that all blocks
2938 * flow into end_block, and that end_block has no successors.
2939 * So by re-purposing end_block as the first block of stream-
2940 * out, we guarantee that all exit paths flow into the stream-
2943 if ((ctx
->compiler
->gpu_id
< 500) &&
2944 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2945 !ctx
->so
->binning_pass
) {
2946 debug_assert(ctx
->so
->type
== MESA_SHADER_VERTEX
);
2947 emit_stream_out(ctx
);
2950 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2951 * NOP and has an epilogue that writes the VS outputs to local storage, to
2952 * be read by the HS. Then it resets execution mask (chmask) and chains
2953 * to the next shader (chsh).
2955 if ((ctx
->so
->type
== MESA_SHADER_VERTEX
&&
2956 (ctx
->so
->key
.has_gs
|| ctx
->so
->key
.tessellation
)) ||
2957 (ctx
->so
->type
== MESA_SHADER_TESS_EVAL
&& ctx
->so
->key
.has_gs
)) {
2958 struct ir3_instruction
*chmask
=
2959 ir3_CHMASK(ctx
->block
);
2960 chmask
->barrier_class
= IR3_BARRIER_EVERYTHING
;
2961 chmask
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
2963 struct ir3_instruction
*chsh
=
2964 ir3_CHSH(ctx
->block
);
2965 chsh
->barrier_class
= IR3_BARRIER_EVERYTHING
;
2966 chsh
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
2968 ir3_END(ctx
->block
);
2973 setup_input(struct ir3_context
*ctx
, nir_variable
*in
)
2975 struct ir3_shader_variant
*so
= ctx
->so
;
2976 unsigned ncomp
= glsl_get_components(in
->type
);
2977 unsigned n
= in
->data
.driver_location
;
2978 unsigned frac
= in
->data
.location_frac
;
2979 unsigned slot
= in
->data
.location
;
2981 /* Inputs are loaded using ldlw or ldg for these stages. */
2982 if (ctx
->so
->type
== MESA_SHADER_TESS_CTRL
||
2983 ctx
->so
->type
== MESA_SHADER_TESS_EVAL
||
2984 ctx
->so
->type
== MESA_SHADER_GEOMETRY
)
2987 /* skip unread inputs, we could end up with (for example), unsplit
2988 * matrix/etc inputs in the case they are not read, so just silently
2994 so
->inputs
[n
].slot
= slot
;
2995 so
->inputs
[n
].compmask
|= (1 << (ncomp
+ frac
)) - 1;
2996 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2997 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2999 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
3001 /* if any varyings have 'sample' qualifer, that triggers us
3002 * to run in per-sample mode:
3004 so
->per_samp
|= in
->data
.sample
;
3006 for (int i
= 0; i
< ncomp
; i
++) {
3007 struct ir3_instruction
*instr
= NULL
;
3008 unsigned idx
= (n
* 4) + i
+ frac
;
3010 if (slot
== VARYING_SLOT_POS
) {
3011 ir3_context_error(ctx
, "fragcoord should be a sysval!\n");
3013 /* detect the special case for front/back colors where
3014 * we need to do flat vs smooth shading depending on
3017 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
3019 case VARYING_SLOT_COL0
:
3020 case VARYING_SLOT_COL1
:
3021 case VARYING_SLOT_BFC0
:
3022 case VARYING_SLOT_BFC1
:
3023 so
->inputs
[n
].rasterflat
= true;
3030 if (ctx
->compiler
->flat_bypass
) {
3031 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
3032 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
3033 so
->inputs
[n
].use_ldlv
= true;
3036 so
->inputs
[n
].bary
= true;
3038 instr
= create_frag_input(ctx
, so
->inputs
[n
].use_ldlv
, idx
);
3041 compile_assert(ctx
, idx
< ctx
->ninputs
);
3043 ctx
->inputs
[idx
] = instr
;
3045 } else if (ctx
->so
->type
== MESA_SHADER_VERTEX
) {
3046 struct ir3_instruction
*input
= NULL
;
3047 struct ir3_instruction
*components
[4];
3048 /* input as setup as frac=0 with "ncomp + frac" components,
3049 * this avoids getting a sparse writemask
3051 unsigned mask
= (1 << (ncomp
+ frac
)) - 1;
3053 foreach_input (in
, ctx
->ir
) {
3054 if (in
->input
.inidx
== n
) {
3061 input
= create_input(ctx
, mask
);
3062 input
->input
.inidx
= n
;
3064 /* For aliased inputs, just append to the wrmask.. ie. if we
3065 * first see a vec2 index at slot N, and then later a vec4,
3066 * the wrmask of the resulting overlapped vec2 and vec4 is 0xf
3068 * If the new input that aliases a previously processed input
3069 * sets no new bits, then just bail as there is nothing to see
3072 if (!(mask
& ~input
->regs
[0]->wrmask
))
3074 input
->regs
[0]->wrmask
|= mask
;
3077 ir3_split_dest(ctx
->block
, components
, input
, 0, ncomp
+ frac
);
3079 for (int i
= 0; i
< ncomp
+ frac
; i
++) {
3080 unsigned idx
= (n
* 4) + i
;
3081 compile_assert(ctx
, idx
< ctx
->ninputs
);
3083 /* With aliased inputs, since we add to the wrmask above, we
3084 * can end up with stale meta:split instructions in the inputs
3085 * table. This is basically harmless, since eventually they
3086 * will get swept away by DCE, but the mismatch wrmask (since
3087 * they would be using the previous wrmask before we OR'd in
3088 * more bits) angers ir3_validate. So just preemptively clean
3091 * dEQP-GLES2.functional.attribute_location.bind_aliasing.cond_vec2
3093 * Note however that split_dest() will return the src if it is
3094 * scalar, so the previous ctx->inputs[idx] could be the input
3095 * itself (which we don't want to remove)
3097 if (ctx
->inputs
[idx
] && (ctx
->inputs
[idx
] != input
)) {
3098 list_del(&ctx
->inputs
[idx
]->node
);
3101 ctx
->inputs
[idx
] = components
[i
];
3104 ir3_context_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3107 /* note: this can be wrong for sparse vertex inputs, this happens with
3108 * vulkan, only a3xx/a4xx use this value for VS, so it shouldn't matter
3110 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== MESA_SHADER_VERTEX
)) {
3111 so
->total_in
+= ncomp
;
3115 /* Initially we assign non-packed inloc's for varyings, as we don't really
3116 * know up-front which components will be unused. After all the compilation
3117 * stages we scan the shader to see which components are actually used, and
3118 * re-pack the inlocs to eliminate unneeded varyings.
3121 pack_inlocs(struct ir3_context
*ctx
)
3123 struct ir3_shader_variant
*so
= ctx
->so
;
3124 uint8_t used_components
[so
->inputs_count
];
3126 memset(used_components
, 0, sizeof(used_components
));
3129 * First Step: scan shader to find which bary.f/ldlv remain:
3132 foreach_block (block
, &ctx
->ir
->block_list
) {
3133 foreach_instr (instr
, &block
->instr_list
) {
3134 if (is_input(instr
)) {
3135 unsigned inloc
= instr
->regs
[1]->iim_val
;
3136 unsigned i
= inloc
/ 4;
3137 unsigned j
= inloc
% 4;
3139 compile_assert(ctx
, instr
->regs
[1]->flags
& IR3_REG_IMMED
);
3140 compile_assert(ctx
, i
< so
->inputs_count
);
3142 used_components
[i
] |= 1 << j
;
3143 } else if (instr
->opc
== OPC_META_TEX_PREFETCH
) {
3144 for (int n
= 0; n
< 2; n
++) {
3145 unsigned inloc
= instr
->prefetch
.input_offset
+ n
;
3146 unsigned i
= inloc
/ 4;
3147 unsigned j
= inloc
% 4;
3149 compile_assert(ctx
, i
< so
->inputs_count
);
3151 used_components
[i
] |= 1 << j
;
3158 * Second Step: reassign varying inloc/slots:
3161 unsigned actual_in
= 0;
3164 for (unsigned i
= 0; i
< so
->inputs_count
; i
++) {
3165 unsigned compmask
= 0, maxcomp
= 0;
3167 so
->inputs
[i
].inloc
= inloc
;
3168 so
->inputs
[i
].bary
= false;
3170 for (unsigned j
= 0; j
< 4; j
++) {
3171 if (!(used_components
[i
] & (1 << j
)))
3174 compmask
|= (1 << j
);
3178 /* at this point, since used_components[i] mask is only
3179 * considering varyings (ie. not sysvals) we know this
3182 so
->inputs
[i
].bary
= true;
3185 if (so
->inputs
[i
].bary
) {
3187 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
3193 * Third Step: reassign packed inloc's:
3196 foreach_block (block
, &ctx
->ir
->block_list
) {
3197 foreach_instr (instr
, &block
->instr_list
) {
3198 if (is_input(instr
)) {
3199 unsigned inloc
= instr
->regs
[1]->iim_val
;
3200 unsigned i
= inloc
/ 4;
3201 unsigned j
= inloc
% 4;
3203 instr
->regs
[1]->iim_val
= so
->inputs
[i
].inloc
+ j
;
3204 } else if (instr
->opc
== OPC_META_TEX_PREFETCH
) {
3205 unsigned i
= instr
->prefetch
.input_offset
/ 4;
3206 unsigned j
= instr
->prefetch
.input_offset
% 4;
3207 instr
->prefetch
.input_offset
= so
->inputs
[i
].inloc
+ j
;
3214 setup_output(struct ir3_context
*ctx
, nir_variable
*out
)
3216 struct ir3_shader_variant
*so
= ctx
->so
;
3217 unsigned slots
= glsl_count_vec4_slots(out
->type
, false, false);
3218 unsigned ncomp
= glsl_get_components(glsl_without_array(out
->type
));
3219 unsigned n
= out
->data
.driver_location
;
3220 unsigned frac
= out
->data
.location_frac
;
3221 unsigned slot
= out
->data
.location
;
3223 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
3225 case FRAG_RESULT_DEPTH
:
3226 so
->writes_pos
= true;
3228 case FRAG_RESULT_COLOR
:
3231 case FRAG_RESULT_SAMPLE_MASK
:
3232 so
->writes_smask
= true;
3234 case FRAG_RESULT_STENCIL
:
3235 so
->writes_stencilref
= true;
3238 slot
+= out
->data
.index
; /* For dual-src blend */
3239 if (slot
>= FRAG_RESULT_DATA0
)
3241 ir3_context_error(ctx
, "unknown FS output name: %s\n",
3242 gl_frag_result_name(slot
));
3244 } else if (ctx
->so
->type
== MESA_SHADER_VERTEX
||
3245 ctx
->so
->type
== MESA_SHADER_TESS_EVAL
||
3246 ctx
->so
->type
== MESA_SHADER_GEOMETRY
) {
3248 case VARYING_SLOT_POS
:
3249 so
->writes_pos
= true;
3251 case VARYING_SLOT_PSIZ
:
3252 so
->writes_psize
= true;
3254 case VARYING_SLOT_PRIMITIVE_ID
:
3255 case VARYING_SLOT_LAYER
:
3256 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3
:
3257 debug_assert(ctx
->so
->type
== MESA_SHADER_GEOMETRY
);
3259 case VARYING_SLOT_COL0
:
3260 case VARYING_SLOT_COL1
:
3261 case VARYING_SLOT_BFC0
:
3262 case VARYING_SLOT_BFC1
:
3263 case VARYING_SLOT_FOGC
:
3264 case VARYING_SLOT_CLIP_DIST0
:
3265 case VARYING_SLOT_CLIP_DIST1
:
3266 case VARYING_SLOT_CLIP_VERTEX
:
3269 if (slot
>= VARYING_SLOT_VAR0
)
3271 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
3273 ir3_context_error(ctx
, "unknown %s shader output name: %s\n",
3274 _mesa_shader_stage_to_string(ctx
->so
->type
),
3275 gl_varying_slot_name(slot
));
3277 } else if (ctx
->so
->type
== MESA_SHADER_TESS_CTRL
) {
3278 /* output lowered to buffer writes. */
3281 ir3_context_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3285 so
->outputs_count
= out
->data
.driver_location
+ slots
;
3286 compile_assert(ctx
, so
->outputs_count
< ARRAY_SIZE(so
->outputs
));
3288 for (int i
= 0; i
< slots
; i
++) {
3289 int slot_base
= n
+ i
;
3290 so
->outputs
[slot_base
].slot
= slot
+ i
;
3292 for (int i
= 0; i
< ncomp
; i
++) {
3293 unsigned idx
= (slot_base
* 4) + i
+ frac
;
3294 compile_assert(ctx
, idx
< ctx
->noutputs
);
3295 ctx
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
3298 /* if varying packing doesn't happen, we could end up in a situation
3299 * with "holes" in the output, and since the per-generation code that
3300 * sets up varying linkage registers doesn't expect to have more than
3301 * one varying per vec4 slot, pad the holes.
3303 * Note that this should probably generate a performance warning of
3306 for (int i
= 0; i
< frac
; i
++) {
3307 unsigned idx
= (slot_base
* 4) + i
;
3308 if (!ctx
->outputs
[idx
]) {
3309 ctx
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
3316 emit_instructions(struct ir3_context
*ctx
)
3318 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
3320 ctx
->ninputs
= ctx
->s
->num_inputs
* 4;
3321 ctx
->noutputs
= ctx
->s
->num_outputs
* 4;
3322 ctx
->inputs
= rzalloc_array(ctx
, struct ir3_instruction
*, ctx
->ninputs
);
3323 ctx
->outputs
= rzalloc_array(ctx
, struct ir3_instruction
*, ctx
->noutputs
);
3325 ctx
->ir
= ir3_create(ctx
->compiler
, ctx
->so
);
3327 /* Create inputs in first block: */
3328 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
3329 ctx
->in_block
= ctx
->block
;
3331 /* for fragment shader, the vcoord input register is used as the
3332 * base for bary.f varying fetch instrs:
3334 * TODO defer creating ctx->ij_pixel and corresponding sysvals
3335 * until emit_intrinsic when we know they are actually needed.
3336 * For now, we defer creating ctx->ij_centroid, etc, since we
3337 * only need ij_pixel for "old style" varying inputs (ie.
3340 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
3341 ctx
->ij
[IJ_PERSP_PIXEL
] = create_input(ctx
, 0x3);
3345 nir_foreach_shader_in_variable (var
, ctx
->s
) {
3346 setup_input(ctx
, var
);
3349 /* Defer add_sysval_input() stuff until after setup_inputs(),
3350 * because sysvals need to be appended after varyings:
3352 if (ctx
->ij
[IJ_PERSP_PIXEL
]) {
3353 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
,
3354 0x3, ctx
->ij
[IJ_PERSP_PIXEL
]);
3358 /* Tesselation shaders always need primitive ID for indexing the
3359 * BO. Geometry shaders don't always need it but when they do it has be
3360 * delivered and unclobbered in the VS. To make things easy, we always
3361 * make room for it in VS/DS.
3363 bool has_tess
= ctx
->so
->key
.tessellation
!= IR3_TESS_NONE
;
3364 bool has_gs
= ctx
->so
->key
.has_gs
;
3365 switch (ctx
->so
->type
) {
3366 case MESA_SHADER_VERTEX
:
3368 ctx
->tcs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_TCS_HEADER_IR3
, 0x1);
3369 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3370 } else if (has_gs
) {
3371 ctx
->gs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_GS_HEADER_IR3
, 0x1);
3372 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3375 case MESA_SHADER_TESS_CTRL
:
3376 ctx
->tcs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_TCS_HEADER_IR3
, 0x1);
3377 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3379 case MESA_SHADER_TESS_EVAL
:
3381 ctx
->gs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_GS_HEADER_IR3
, 0x1);
3382 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3384 case MESA_SHADER_GEOMETRY
:
3385 ctx
->gs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_GS_HEADER_IR3
, 0x1);
3386 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3392 /* Setup outputs: */
3393 nir_foreach_shader_out_variable (var
, ctx
->s
) {
3394 setup_output(ctx
, var
);
3397 /* Find # of samplers. Just assume that we'll be reading from images.. if
3398 * it is write-only we don't have to count it, but after lowering derefs
3399 * is too late to compact indices for that.
3401 ctx
->so
->num_samp
= util_last_bit(ctx
->s
->info
.textures_used
) + ctx
->s
->info
.num_images
;
3403 /* NOTE: need to do something more clever when we support >1 fxn */
3404 nir_foreach_register (reg
, &fxn
->registers
) {
3405 ir3_declare_array(ctx
, reg
);
3407 /* And emit the body: */
3409 emit_function(ctx
, fxn
);
3412 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3413 * need to assign the tex state indexes for these after we know the
3417 fixup_astc_srgb(struct ir3_context
*ctx
)
3419 struct ir3_shader_variant
*so
= ctx
->so
;
3420 /* indexed by original tex idx, value is newly assigned alpha sampler
3421 * state tex idx. Zero is invalid since there is at least one sampler
3424 unsigned alt_tex_state
[16] = {0};
3425 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
3428 so
->astc_srgb
.base
= tex_idx
;
3430 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
3431 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
3433 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
3435 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
3436 /* assign new alternate/alpha tex state slot: */
3437 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
3438 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
3439 so
->astc_srgb
.count
++;
3442 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
3447 fixup_binning_pass(struct ir3_context
*ctx
)
3449 struct ir3_shader_variant
*so
= ctx
->so
;
3450 struct ir3
*ir
= ctx
->ir
;
3453 /* first pass, remove unused outputs from the IR level outputs: */
3454 for (i
= 0, j
= 0; i
< ir
->outputs_count
; i
++) {
3455 struct ir3_instruction
*out
= ir
->outputs
[i
];
3456 assert(out
->opc
== OPC_META_COLLECT
);
3457 unsigned outidx
= out
->collect
.outidx
;
3458 unsigned slot
= so
->outputs
[outidx
].slot
;
3460 /* throw away everything but first position/psize */
3461 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3462 ir
->outputs
[j
] = ir
->outputs
[i
];
3466 ir
->outputs_count
= j
;
3468 /* second pass, cleanup the unused slots in ir3_shader_variant::outputs
3471 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
3472 unsigned slot
= so
->outputs
[i
].slot
;
3474 /* throw away everything but first position/psize */
3475 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3476 so
->outputs
[j
] = so
->outputs
[i
];
3478 /* fixup outidx to point to new output table entry: */
3479 foreach_output (out
, ir
) {
3480 if (out
->collect
.outidx
== i
) {
3481 out
->collect
.outidx
= j
;
3489 so
->outputs_count
= j
;
3493 collect_tex_prefetches(struct ir3_context
*ctx
, struct ir3
*ir
)
3497 /* Collect sampling instructions eligible for pre-dispatch. */
3498 foreach_block (block
, &ir
->block_list
) {
3499 foreach_instr_safe (instr
, &block
->instr_list
) {
3500 if (instr
->opc
== OPC_META_TEX_PREFETCH
) {
3501 assert(idx
< ARRAY_SIZE(ctx
->so
->sampler_prefetch
));
3502 struct ir3_sampler_prefetch
*fetch
=
3503 &ctx
->so
->sampler_prefetch
[idx
];
3506 if (instr
->flags
& IR3_INSTR_B
) {
3507 fetch
->cmd
= IR3_SAMPLER_BINDLESS_PREFETCH_CMD
;
3508 /* In bindless mode, the index is actually the base */
3509 fetch
->tex_id
= instr
->prefetch
.tex_base
;
3510 fetch
->samp_id
= instr
->prefetch
.samp_base
;
3511 fetch
->tex_bindless_id
= instr
->prefetch
.tex
;
3512 fetch
->samp_bindless_id
= instr
->prefetch
.samp
;
3514 fetch
->cmd
= IR3_SAMPLER_PREFETCH_CMD
;
3515 fetch
->tex_id
= instr
->prefetch
.tex
;
3516 fetch
->samp_id
= instr
->prefetch
.samp
;
3518 fetch
->wrmask
= instr
->regs
[0]->wrmask
;
3519 fetch
->dst
= instr
->regs
[0]->num
;
3520 fetch
->src
= instr
->prefetch
.input_offset
;
3522 /* These are the limits on a5xx/a6xx, we might need to
3523 * revisit if SP_FS_PREFETCH[n] changes on later gens:
3525 assert(fetch
->dst
<= 0x3f);
3526 assert(fetch
->tex_id
<= 0x1f);
3527 assert(fetch
->samp_id
< 0xf);
3530 MAX2(ctx
->so
->total_in
, instr
->prefetch
.input_offset
+ 2);
3532 fetch
->half_precision
= !!(instr
->regs
[0]->flags
& IR3_REG_HALF
);
3534 /* Remove the prefetch placeholder instruction: */
3535 list_delinit(&instr
->node
);
3542 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
3543 struct ir3_shader_variant
*so
)
3545 struct ir3_context
*ctx
;
3547 int ret
= 0, max_bary
;
3552 ctx
= ir3_context_init(compiler
, so
);
3554 DBG("INIT failed!");
3559 emit_instructions(ctx
);
3562 DBG("EMIT failed!");
3567 ir
= so
->ir
= ctx
->ir
;
3569 assert((ctx
->noutputs
% 4) == 0);
3571 /* Setup IR level outputs, which are "collects" that gather
3572 * the scalar components of outputs.
3574 for (unsigned i
= 0; i
< ctx
->noutputs
; i
+= 4) {
3576 /* figure out the # of components written:
3578 * TODO do we need to handle holes, ie. if .x and .z
3579 * components written, but .y component not written?
3581 for (unsigned j
= 0; j
< 4; j
++) {
3582 if (!ctx
->outputs
[i
+ j
])
3587 /* Note that in some stages, like TCS, store_output is
3588 * lowered to memory writes, so no components of the
3589 * are "written" from the PoV of traditional store-
3590 * output instructions:
3595 struct ir3_instruction
*out
=
3596 ir3_create_collect(ctx
, &ctx
->outputs
[i
], ncomp
);
3599 assert(outidx
< so
->outputs_count
);
3601 /* stash index into so->outputs[] so we can map the
3602 * output back to slot/etc later:
3604 out
->collect
.outidx
= outidx
;
3606 array_insert(ir
, ir
->outputs
, out
);
3609 /* Set up the gs header as an output for the vertex shader so it won't
3610 * clobber it for the tess ctrl shader.
3612 * TODO this could probably be done more cleanly in a nir pass.
3614 if (ctx
->so
->type
== MESA_SHADER_VERTEX
||
3615 (ctx
->so
->key
.has_gs
&& ctx
->so
->type
== MESA_SHADER_TESS_EVAL
)) {
3616 if (ctx
->primitive_id
) {
3617 unsigned n
= so
->outputs_count
++;
3618 so
->outputs
[n
].slot
= VARYING_SLOT_PRIMITIVE_ID
;
3620 struct ir3_instruction
*out
=
3621 ir3_create_collect(ctx
, &ctx
->primitive_id
, 1);
3622 out
->collect
.outidx
= n
;
3623 array_insert(ir
, ir
->outputs
, out
);
3626 if (ctx
->gs_header
) {
3627 unsigned n
= so
->outputs_count
++;
3628 so
->outputs
[n
].slot
= VARYING_SLOT_GS_HEADER_IR3
;
3629 struct ir3_instruction
*out
=
3630 ir3_create_collect(ctx
, &ctx
->gs_header
, 1);
3631 out
->collect
.outidx
= n
;
3632 array_insert(ir
, ir
->outputs
, out
);
3635 if (ctx
->tcs_header
) {
3636 unsigned n
= so
->outputs_count
++;
3637 so
->outputs
[n
].slot
= VARYING_SLOT_TCS_HEADER_IR3
;
3638 struct ir3_instruction
*out
=
3639 ir3_create_collect(ctx
, &ctx
->tcs_header
, 1);
3640 out
->collect
.outidx
= n
;
3641 array_insert(ir
, ir
->outputs
, out
);
3645 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3646 * need to make sure not to remove any inputs that are used by
3647 * the nonbinning VS.
3649 if (ctx
->compiler
->gpu_id
>= 600 && so
->binning_pass
&&
3650 so
->type
== MESA_SHADER_VERTEX
) {
3651 for (int i
= 0; i
< ctx
->ninputs
; i
++) {
3652 struct ir3_instruction
*in
= ctx
->inputs
[i
];
3660 debug_assert(n
< so
->nonbinning
->inputs_count
);
3662 if (so
->nonbinning
->inputs
[n
].sysval
)
3665 /* be sure to keep inputs, even if only used in VS */
3666 if (so
->nonbinning
->inputs
[n
].compmask
& (1 << c
))
3667 array_insert(in
->block
, in
->block
->keeps
, in
);
3671 /* at this point, for binning pass, throw away unneeded outputs: */
3672 if (so
->binning_pass
&& (ctx
->compiler
->gpu_id
< 600))
3673 fixup_binning_pass(ctx
);
3675 ir3_debug_print(ir
, "AFTER: nir->ir3");
3681 progress
|= IR3_PASS(ir
, ir3_cf
);
3682 progress
|= IR3_PASS(ir
, ir3_cp
, so
);
3683 progress
|= IR3_PASS(ir
, ir3_dce
, so
);
3686 /* at this point, for binning pass, throw away unneeded outputs:
3687 * Note that for a6xx and later, we do this after ir3_cp to ensure
3688 * that the uniform/constant layout for BS and VS matches, so that
3689 * we can re-use same VS_CONST state group.
3691 if (so
->binning_pass
&& (ctx
->compiler
->gpu_id
>= 600)) {
3692 fixup_binning_pass(ctx
);
3693 /* cleanup the result of removing unneeded outputs: */
3694 while (IR3_PASS(ir
, ir3_dce
, so
)) {}
3697 IR3_PASS(ir
, ir3_sched_add_deps
);
3699 /* Group left/right neighbors, inserting mov's where needed to
3702 IR3_PASS(ir
, ir3_group
);
3704 /* At this point, all the dead code should be long gone: */
3705 assert(!IR3_PASS(ir
, ir3_dce
, so
));
3707 ret
= ir3_sched(ir
);
3709 DBG("SCHED failed!");
3713 ir3_debug_print(ir
, "AFTER: ir3_sched");
3715 if (IR3_PASS(ir
, ir3_cp_postsched
)) {
3716 /* cleanup the result of removing unneeded mov's: */
3717 while (IR3_PASS(ir
, ir3_dce
, so
)) {}
3720 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3721 * with draw pass VS, so binning and draw pass can both use the
3724 * Note that VS inputs are expected to be full precision.
3726 bool pre_assign_inputs
= (ir
->compiler
->gpu_id
>= 600) &&
3727 (ir
->type
== MESA_SHADER_VERTEX
) &&
3730 if (pre_assign_inputs
) {
3731 for (unsigned i
= 0; i
< ctx
->ninputs
; i
++) {
3732 struct ir3_instruction
*instr
= ctx
->inputs
[i
];
3739 unsigned regid
= so
->nonbinning
->inputs
[n
].regid
+ c
;
3741 instr
->regs
[0]->num
= regid
;
3744 ret
= ir3_ra(so
, ctx
->inputs
, ctx
->ninputs
);
3745 } else if (ctx
->tcs_header
) {
3746 /* We need to have these values in the same registers between VS and TCS
3747 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3750 ctx
->tcs_header
->regs
[0]->num
= regid(0, 0);
3751 ctx
->primitive_id
->regs
[0]->num
= regid(0, 1);
3752 struct ir3_instruction
*precolor
[] = { ctx
->tcs_header
, ctx
->primitive_id
};
3753 ret
= ir3_ra(so
, precolor
, ARRAY_SIZE(precolor
));
3754 } else if (ctx
->gs_header
) {
3755 /* We need to have these values in the same registers between producer
3756 * (VS or DS) and GS since the producer chains to GS and doesn't get
3757 * the sysvals redelivered.
3760 ctx
->gs_header
->regs
[0]->num
= regid(0, 0);
3761 ctx
->primitive_id
->regs
[0]->num
= regid(0, 1);
3762 struct ir3_instruction
*precolor
[] = { ctx
->gs_header
, ctx
->primitive_id
};
3763 ret
= ir3_ra(so
, precolor
, ARRAY_SIZE(precolor
));
3764 } else if (so
->num_sampler_prefetch
) {
3765 assert(so
->type
== MESA_SHADER_FRAGMENT
);
3766 struct ir3_instruction
*precolor
[2];
3769 foreach_input (instr
, ir
) {
3770 if (instr
->input
.sysval
!= SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
)
3773 assert(idx
< ARRAY_SIZE(precolor
));
3775 precolor
[idx
] = instr
;
3776 instr
->regs
[0]->num
= idx
;
3780 ret
= ir3_ra(so
, precolor
, idx
);
3782 ret
= ir3_ra(so
, NULL
, 0);
3790 IR3_PASS(ir
, ir3_postsched
, so
);
3792 if (compiler
->gpu_id
>= 600) {
3793 IR3_PASS(ir
, ir3_a6xx_fixup_atomic_dests
, so
);
3796 if (so
->type
== MESA_SHADER_FRAGMENT
)
3800 * Fixup inputs/outputs to point to the actual registers assigned:
3802 * 1) initialize to r63.x (invalid/unused)
3803 * 2) iterate IR level inputs/outputs and update the variants
3804 * inputs/outputs table based on the assigned registers for
3805 * the remaining inputs/outputs.
3808 for (unsigned i
= 0; i
< so
->inputs_count
; i
++)
3809 so
->inputs
[i
].regid
= INVALID_REG
;
3810 for (unsigned i
= 0; i
< so
->outputs_count
; i
++)
3811 so
->outputs
[i
].regid
= INVALID_REG
;
3813 foreach_output (out
, ir
) {
3814 assert(out
->opc
== OPC_META_COLLECT
);
3815 unsigned outidx
= out
->collect
.outidx
;
3817 so
->outputs
[outidx
].regid
= out
->regs
[0]->num
;
3818 so
->outputs
[outidx
].half
= !!(out
->regs
[0]->flags
& IR3_REG_HALF
);
3821 foreach_input (in
, ir
) {
3822 assert(in
->opc
== OPC_META_INPUT
);
3823 unsigned inidx
= in
->input
.inidx
;
3825 if (pre_assign_inputs
&& !so
->inputs
[inidx
].sysval
) {
3826 if (VALIDREG(so
->nonbinning
->inputs
[inidx
].regid
)) {
3827 compile_assert(ctx
, in
->regs
[0]->num
==
3828 so
->nonbinning
->inputs
[inidx
].regid
);
3829 compile_assert(ctx
, !!(in
->regs
[0]->flags
& IR3_REG_HALF
) ==
3830 so
->nonbinning
->inputs
[inidx
].half
);
3832 so
->inputs
[inidx
].regid
= so
->nonbinning
->inputs
[inidx
].regid
;
3833 so
->inputs
[inidx
].half
= so
->nonbinning
->inputs
[inidx
].half
;
3835 so
->inputs
[inidx
].regid
= in
->regs
[0]->num
;
3836 so
->inputs
[inidx
].half
= !!(in
->regs
[0]->flags
& IR3_REG_HALF
);
3841 fixup_astc_srgb(ctx
);
3843 /* We need to do legalize after (for frag shader's) the "bary.f"
3844 * offsets (inloc) have been assigned.
3846 IR3_PASS(ir
, ir3_legalize
, so
, &max_bary
);
3848 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3849 * know what we might have to wait on when coming in from VS chsh.
3851 if (so
->type
== MESA_SHADER_TESS_CTRL
||
3852 so
->type
== MESA_SHADER_GEOMETRY
) {
3853 foreach_block (block
, &ir
->block_list
) {
3854 foreach_instr (instr
, &block
->instr_list
) {
3855 instr
->flags
|= IR3_INSTR_SS
| IR3_INSTR_SY
;
3861 so
->branchstack
= ctx
->max_stack
;
3863 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3864 if (so
->type
== MESA_SHADER_FRAGMENT
)
3865 so
->total_in
= max_bary
+ 1;
3867 /* Collect sampling instructions eligible for pre-dispatch. */
3868 collect_tex_prefetches(ctx
, ir
);
3870 if (so
->type
== MESA_SHADER_FRAGMENT
&&
3871 ctx
->s
->info
.fs
.needs_helper_invocations
)
3872 so
->need_pixlod
= true;
3877 ir3_destroy(so
->ir
);
3880 ir3_context_free(ctx
);