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[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_shader.h"
35 #include "ir3_nir.h"
36
37 #include "instr-a3xx.h"
38 #include "ir3.h"
39 #include "ir3_context.h"
40
41
42 static struct ir3_instruction *
43 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
44 struct ir3_instruction *address, struct ir3_instruction *collect)
45 {
46 struct ir3_block *block = ctx->block;
47 struct ir3_instruction *mov;
48 struct ir3_register *src;
49
50 mov = ir3_instr_create(block, OPC_MOV);
51 mov->cat1.src_type = TYPE_U32;
52 mov->cat1.dst_type = TYPE_U32;
53 ir3_reg_create(mov, 0, 0);
54 src = ir3_reg_create(mov, 0, IR3_REG_SSA | IR3_REG_RELATIV);
55 src->instr = collect;
56 src->size = arrsz;
57 src->array.offset = n;
58
59 ir3_instr_set_address(mov, address);
60
61 return mov;
62 }
63
64 static struct ir3_instruction *
65 create_input_compmask(struct ir3_context *ctx, unsigned n, unsigned compmask)
66 {
67 struct ir3_instruction *in;
68
69 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
70 in->inout.block = ctx->in_block;
71 ir3_reg_create(in, n, 0);
72
73 in->regs[0]->wrmask = compmask;
74
75 return in;
76 }
77
78 static struct ir3_instruction *
79 create_input(struct ir3_context *ctx, unsigned n)
80 {
81 return create_input_compmask(ctx, n, 0x1);
82 }
83
84 static struct ir3_instruction *
85 create_frag_input(struct ir3_context *ctx, bool use_ldlv)
86 {
87 struct ir3_block *block = ctx->block;
88 struct ir3_instruction *instr;
89 /* actual inloc is assigned and fixed up later: */
90 struct ir3_instruction *inloc = create_immed(block, 0);
91
92 if (use_ldlv) {
93 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
94 instr->cat6.type = TYPE_U32;
95 instr->cat6.iim_val = 1;
96 } else {
97 instr = ir3_BARY_F(block, inloc, 0, ctx->frag_vcoord, 0);
98 instr->regs[2]->wrmask = 0x3;
99 }
100
101 return instr;
102 }
103
104 static struct ir3_instruction *
105 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
106 {
107 /* first four vec4 sysval's reserved for UBOs: */
108 /* NOTE: dp is in scalar, but there can be >4 dp components: */
109 unsigned n = ctx->so->constbase.driver_param;
110 unsigned r = regid(n + dp / 4, dp % 4);
111 return create_uniform(ctx->block, r);
112 }
113
114 /*
115 * Adreno uses uint rather than having dedicated bool type,
116 * which (potentially) requires some conversion, in particular
117 * when using output of an bool instr to int input, or visa
118 * versa.
119 *
120 * | Adreno | NIR |
121 * -------+---------+-------+-
122 * true | 1 | ~0 |
123 * false | 0 | 0 |
124 *
125 * To convert from an adreno bool (uint) to nir, use:
126 *
127 * absneg.s dst, (neg)src
128 *
129 * To convert back in the other direction:
130 *
131 * absneg.s dst, (abs)arc
132 *
133 * The CP step can clean up the absneg.s that cancel each other
134 * out, and with a slight bit of extra cleverness (to recognize
135 * the instructions which produce either a 0 or 1) can eliminate
136 * the absneg.s's completely when an instruction that wants
137 * 0/1 consumes the result. For example, when a nir 'bcsel'
138 * consumes the result of 'feq'. So we should be able to get by
139 * without a boolean resolve step, and without incuring any
140 * extra penalty in instruction count.
141 */
142
143 /* NIR bool -> native (adreno): */
144 static struct ir3_instruction *
145 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
146 {
147 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
148 }
149
150 /* native (adreno) -> NIR bool: */
151 static struct ir3_instruction *
152 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
153 {
154 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
155 }
156
157 /*
158 * alu/sfu instructions:
159 */
160
161 static struct ir3_instruction *
162 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
163 unsigned src_bitsize, nir_op op)
164 {
165 type_t src_type, dst_type;
166
167 switch (op) {
168 case nir_op_f2f32:
169 case nir_op_f2f16_rtne:
170 case nir_op_f2f16_rtz:
171 case nir_op_f2f16:
172 case nir_op_f2i32:
173 case nir_op_f2i16:
174 case nir_op_f2i8:
175 case nir_op_f2u32:
176 case nir_op_f2u16:
177 case nir_op_f2u8:
178 switch (src_bitsize) {
179 case 32:
180 src_type = TYPE_F32;
181 break;
182 case 16:
183 src_type = TYPE_F16;
184 break;
185 default:
186 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
187 }
188 break;
189
190 case nir_op_i2f32:
191 case nir_op_i2f16:
192 case nir_op_i2i32:
193 case nir_op_i2i16:
194 case nir_op_i2i8:
195 switch (src_bitsize) {
196 case 32:
197 src_type = TYPE_S32;
198 break;
199 case 16:
200 src_type = TYPE_S16;
201 break;
202 case 8:
203 src_type = TYPE_S8;
204 break;
205 default:
206 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
207 }
208 break;
209
210 case nir_op_u2f32:
211 case nir_op_u2f16:
212 case nir_op_u2u32:
213 case nir_op_u2u16:
214 case nir_op_u2u8:
215 switch (src_bitsize) {
216 case 32:
217 src_type = TYPE_U32;
218 break;
219 case 16:
220 src_type = TYPE_U16;
221 break;
222 case 8:
223 src_type = TYPE_U8;
224 break;
225 default:
226 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
227 }
228 break;
229
230 default:
231 ir3_context_error(ctx, "invalid conversion op: %u", op);
232 }
233
234 switch (op) {
235 case nir_op_f2f32:
236 case nir_op_i2f32:
237 case nir_op_u2f32:
238 dst_type = TYPE_F32;
239 break;
240
241 case nir_op_f2f16_rtne:
242 case nir_op_f2f16_rtz:
243 case nir_op_f2f16:
244 /* TODO how to handle rounding mode? */
245 case nir_op_i2f16:
246 case nir_op_u2f16:
247 dst_type = TYPE_F16;
248 break;
249
250 case nir_op_f2i32:
251 case nir_op_i2i32:
252 dst_type = TYPE_S32;
253 break;
254
255 case nir_op_f2i16:
256 case nir_op_i2i16:
257 dst_type = TYPE_S16;
258 break;
259
260 case nir_op_f2i8:
261 case nir_op_i2i8:
262 dst_type = TYPE_S8;
263 break;
264
265 case nir_op_f2u32:
266 case nir_op_u2u32:
267 dst_type = TYPE_U32;
268 break;
269
270 case nir_op_f2u16:
271 case nir_op_u2u16:
272 dst_type = TYPE_U16;
273 break;
274
275 case nir_op_f2u8:
276 case nir_op_u2u8:
277 dst_type = TYPE_U8;
278 break;
279
280 default:
281 ir3_context_error(ctx, "invalid conversion op: %u", op);
282 }
283
284 return ir3_COV(ctx->block, src, src_type, dst_type);
285 }
286
287 static void
288 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
289 {
290 const nir_op_info *info = &nir_op_infos[alu->op];
291 struct ir3_instruction **dst, *src[info->num_inputs];
292 unsigned bs[info->num_inputs]; /* bit size */
293 struct ir3_block *b = ctx->block;
294 unsigned dst_sz, wrmask;
295
296 if (alu->dest.dest.is_ssa) {
297 dst_sz = alu->dest.dest.ssa.num_components;
298 wrmask = (1 << dst_sz) - 1;
299 } else {
300 dst_sz = alu->dest.dest.reg.reg->num_components;
301 wrmask = alu->dest.write_mask;
302 }
303
304 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
305
306 /* Vectors are special in that they have non-scalarized writemasks,
307 * and just take the first swizzle channel for each argument in
308 * order into each writemask channel.
309 */
310 if ((alu->op == nir_op_vec2) ||
311 (alu->op == nir_op_vec3) ||
312 (alu->op == nir_op_vec4)) {
313
314 for (int i = 0; i < info->num_inputs; i++) {
315 nir_alu_src *asrc = &alu->src[i];
316
317 compile_assert(ctx, !asrc->abs);
318 compile_assert(ctx, !asrc->negate);
319
320 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
321 if (!src[i])
322 src[i] = create_immed(ctx->block, 0);
323 dst[i] = ir3_MOV(b, src[i], TYPE_U32);
324 }
325
326 put_dst(ctx, &alu->dest.dest);
327 return;
328 }
329
330 /* We also get mov's with more than one component for mov's so
331 * handle those specially:
332 */
333 if ((alu->op == nir_op_imov) || (alu->op == nir_op_fmov)) {
334 type_t type = (alu->op == nir_op_imov) ? TYPE_U32 : TYPE_F32;
335 nir_alu_src *asrc = &alu->src[0];
336 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
337
338 for (unsigned i = 0; i < dst_sz; i++) {
339 if (wrmask & (1 << i)) {
340 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], type);
341 } else {
342 dst[i] = NULL;
343 }
344 }
345
346 put_dst(ctx, &alu->dest.dest);
347 return;
348 }
349
350 /* General case: We can just grab the one used channel per src. */
351 for (int i = 0; i < info->num_inputs; i++) {
352 unsigned chan = ffs(alu->dest.write_mask) - 1;
353 nir_alu_src *asrc = &alu->src[i];
354
355 compile_assert(ctx, !asrc->abs);
356 compile_assert(ctx, !asrc->negate);
357
358 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
359 bs[i] = nir_src_bit_size(asrc->src);
360
361 compile_assert(ctx, src[i]);
362 }
363
364 switch (alu->op) {
365 case nir_op_f2f32:
366 case nir_op_f2f16_rtne:
367 case nir_op_f2f16_rtz:
368 case nir_op_f2f16:
369 case nir_op_f2i32:
370 case nir_op_f2i16:
371 case nir_op_f2i8:
372 case nir_op_f2u32:
373 case nir_op_f2u16:
374 case nir_op_f2u8:
375 case nir_op_i2f32:
376 case nir_op_i2f16:
377 case nir_op_i2i32:
378 case nir_op_i2i16:
379 case nir_op_i2i8:
380 case nir_op_u2f32:
381 case nir_op_u2f16:
382 case nir_op_u2u32:
383 case nir_op_u2u16:
384 case nir_op_u2u8:
385 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
386 break;
387 case nir_op_f2b32:
388 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
389 dst[0]->cat2.condition = IR3_COND_NE;
390 dst[0] = ir3_n2b(b, dst[0]);
391 break;
392 case nir_op_b2f16:
393 case nir_op_b2f32:
394 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
395 break;
396 case nir_op_b2i8:
397 case nir_op_b2i16:
398 case nir_op_b2i32:
399 dst[0] = ir3_b2n(b, src[0]);
400 break;
401 case nir_op_i2b32:
402 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
403 dst[0]->cat2.condition = IR3_COND_NE;
404 dst[0] = ir3_n2b(b, dst[0]);
405 break;
406
407 case nir_op_fneg:
408 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
409 break;
410 case nir_op_fabs:
411 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
412 break;
413 case nir_op_fmax:
414 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
415 break;
416 case nir_op_fmin:
417 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
418 break;
419 case nir_op_fsat:
420 /* if there is just a single use of the src, and it supports
421 * (sat) bit, we can just fold the (sat) flag back to the
422 * src instruction and create a mov. This is easier for cp
423 * to eliminate.
424 *
425 * TODO probably opc_cat==4 is ok too
426 */
427 if (alu->src[0].src.is_ssa &&
428 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
429 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
430 src[0]->flags |= IR3_INSTR_SAT;
431 dst[0] = ir3_MOV(b, src[0], TYPE_U32);
432 } else {
433 /* otherwise generate a max.f that saturates.. blob does
434 * similar (generating a cat2 mov using max.f)
435 */
436 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
437 dst[0]->flags |= IR3_INSTR_SAT;
438 }
439 break;
440 case nir_op_fmul:
441 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
442 break;
443 case nir_op_fadd:
444 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
445 break;
446 case nir_op_fsub:
447 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
448 break;
449 case nir_op_ffma:
450 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
451 break;
452 case nir_op_fddx:
453 dst[0] = ir3_DSX(b, src[0], 0);
454 dst[0]->cat5.type = TYPE_F32;
455 break;
456 case nir_op_fddy:
457 dst[0] = ir3_DSY(b, src[0], 0);
458 dst[0]->cat5.type = TYPE_F32;
459 break;
460 break;
461 case nir_op_flt32:
462 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
463 dst[0]->cat2.condition = IR3_COND_LT;
464 dst[0] = ir3_n2b(b, dst[0]);
465 break;
466 case nir_op_fge32:
467 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
468 dst[0]->cat2.condition = IR3_COND_GE;
469 dst[0] = ir3_n2b(b, dst[0]);
470 break;
471 case nir_op_feq32:
472 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
473 dst[0]->cat2.condition = IR3_COND_EQ;
474 dst[0] = ir3_n2b(b, dst[0]);
475 break;
476 case nir_op_fne32:
477 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
478 dst[0]->cat2.condition = IR3_COND_NE;
479 dst[0] = ir3_n2b(b, dst[0]);
480 break;
481 case nir_op_fceil:
482 dst[0] = ir3_CEIL_F(b, src[0], 0);
483 break;
484 case nir_op_ffloor:
485 dst[0] = ir3_FLOOR_F(b, src[0], 0);
486 break;
487 case nir_op_ftrunc:
488 dst[0] = ir3_TRUNC_F(b, src[0], 0);
489 break;
490 case nir_op_fround_even:
491 dst[0] = ir3_RNDNE_F(b, src[0], 0);
492 break;
493 case nir_op_fsign:
494 dst[0] = ir3_SIGN_F(b, src[0], 0);
495 break;
496
497 case nir_op_fsin:
498 dst[0] = ir3_SIN(b, src[0], 0);
499 break;
500 case nir_op_fcos:
501 dst[0] = ir3_COS(b, src[0], 0);
502 break;
503 case nir_op_frsq:
504 dst[0] = ir3_RSQ(b, src[0], 0);
505 break;
506 case nir_op_frcp:
507 dst[0] = ir3_RCP(b, src[0], 0);
508 break;
509 case nir_op_flog2:
510 dst[0] = ir3_LOG2(b, src[0], 0);
511 break;
512 case nir_op_fexp2:
513 dst[0] = ir3_EXP2(b, src[0], 0);
514 break;
515 case nir_op_fsqrt:
516 dst[0] = ir3_SQRT(b, src[0], 0);
517 break;
518
519 case nir_op_iabs:
520 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
521 break;
522 case nir_op_iadd:
523 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
524 break;
525 case nir_op_iand:
526 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
527 break;
528 case nir_op_imax:
529 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
530 break;
531 case nir_op_umax:
532 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
533 break;
534 case nir_op_imin:
535 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
536 break;
537 case nir_op_umin:
538 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
539 break;
540 case nir_op_imul:
541 /*
542 * dst = (al * bl) + (ah * bl << 16) + (al * bh << 16)
543 * mull.u tmp0, a, b ; mul low, i.e. al * bl
544 * madsh.m16 tmp1, a, b, tmp0 ; mul-add shift high mix, i.e. ah * bl << 16
545 * madsh.m16 dst, b, a, tmp1 ; i.e. al * bh << 16
546 */
547 dst[0] = ir3_MADSH_M16(b, src[1], 0, src[0], 0,
548 ir3_MADSH_M16(b, src[0], 0, src[1], 0,
549 ir3_MULL_U(b, src[0], 0, src[1], 0), 0), 0);
550 break;
551 case nir_op_ineg:
552 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
553 break;
554 case nir_op_inot:
555 dst[0] = ir3_NOT_B(b, src[0], 0);
556 break;
557 case nir_op_ior:
558 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
559 break;
560 case nir_op_ishl:
561 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
562 break;
563 case nir_op_ishr:
564 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
565 break;
566 case nir_op_isign: {
567 /* maybe this would be sane to lower in nir.. */
568 struct ir3_instruction *neg, *pos;
569
570 neg = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
571 neg->cat2.condition = IR3_COND_LT;
572
573 pos = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
574 pos->cat2.condition = IR3_COND_GT;
575
576 dst[0] = ir3_SUB_U(b, pos, 0, neg, 0);
577
578 break;
579 }
580 case nir_op_isub:
581 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
582 break;
583 case nir_op_ixor:
584 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
585 break;
586 case nir_op_ushr:
587 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
588 break;
589 case nir_op_ilt32:
590 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
591 dst[0]->cat2.condition = IR3_COND_LT;
592 dst[0] = ir3_n2b(b, dst[0]);
593 break;
594 case nir_op_ige32:
595 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
596 dst[0]->cat2.condition = IR3_COND_GE;
597 dst[0] = ir3_n2b(b, dst[0]);
598 break;
599 case nir_op_ieq32:
600 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
601 dst[0]->cat2.condition = IR3_COND_EQ;
602 dst[0] = ir3_n2b(b, dst[0]);
603 break;
604 case nir_op_ine32:
605 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
606 dst[0]->cat2.condition = IR3_COND_NE;
607 dst[0] = ir3_n2b(b, dst[0]);
608 break;
609 case nir_op_ult32:
610 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
611 dst[0]->cat2.condition = IR3_COND_LT;
612 dst[0] = ir3_n2b(b, dst[0]);
613 break;
614 case nir_op_uge32:
615 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
616 dst[0]->cat2.condition = IR3_COND_GE;
617 dst[0] = ir3_n2b(b, dst[0]);
618 break;
619
620 case nir_op_b32csel: {
621 struct ir3_instruction *cond = ir3_b2n(b, src[0]);
622 compile_assert(ctx, bs[1] == bs[2]);
623 /* the boolean condition is 32b even if src[1] and src[2] are
624 * half-precision, but sel.b16 wants all three src's to be the
625 * same type.
626 */
627 if (bs[1] < 32)
628 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
629 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
630 break;
631 }
632 case nir_op_bit_count:
633 dst[0] = ir3_CBITS_B(b, src[0], 0);
634 break;
635 case nir_op_ifind_msb: {
636 struct ir3_instruction *cmp;
637 dst[0] = ir3_CLZ_S(b, src[0], 0);
638 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
639 cmp->cat2.condition = IR3_COND_GE;
640 dst[0] = ir3_SEL_B32(b,
641 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
642 cmp, 0, dst[0], 0);
643 break;
644 }
645 case nir_op_ufind_msb:
646 dst[0] = ir3_CLZ_B(b, src[0], 0);
647 dst[0] = ir3_SEL_B32(b,
648 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
649 src[0], 0, dst[0], 0);
650 break;
651 case nir_op_find_lsb:
652 dst[0] = ir3_BFREV_B(b, src[0], 0);
653 dst[0] = ir3_CLZ_B(b, dst[0], 0);
654 break;
655 case nir_op_bitfield_reverse:
656 dst[0] = ir3_BFREV_B(b, src[0], 0);
657 break;
658
659 default:
660 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
661 nir_op_infos[alu->op].name);
662 break;
663 }
664
665 put_dst(ctx, &alu->dest.dest);
666 }
667
668 /* handles direct/indirect UBO reads: */
669 static void
670 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
671 struct ir3_instruction **dst)
672 {
673 struct ir3_block *b = ctx->block;
674 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
675 nir_const_value *const_offset;
676 /* UBO addresses are the first driver params: */
677 unsigned ubo = regid(ctx->so->constbase.ubo, 0);
678 const unsigned ptrsz = ir3_pointer_size(ctx);
679
680 int off = 0;
681
682 /* First src is ubo index, which could either be an immed or not: */
683 src0 = ir3_get_src(ctx, &intr->src[0])[0];
684 if (is_same_type_mov(src0) &&
685 (src0->regs[1]->flags & IR3_REG_IMMED)) {
686 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
687 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
688 } else {
689 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, 4));
690 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, 4));
691 }
692
693 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
694 addr = base_lo;
695
696 const_offset = nir_src_as_const_value(intr->src[1]);
697 if (const_offset) {
698 off += const_offset->u32[0];
699 } else {
700 /* For load_ubo_indirect, second src is indirect offset: */
701 src1 = ir3_get_src(ctx, &intr->src[1])[0];
702
703 /* and add offset to addr: */
704 addr = ir3_ADD_S(b, addr, 0, src1, 0);
705 }
706
707 /* if offset is to large to encode in the ldg, split it out: */
708 if ((off + (intr->num_components * 4)) > 1024) {
709 /* split out the minimal amount to improve the odds that
710 * cp can fit the immediate in the add.s instruction:
711 */
712 unsigned off2 = off + (intr->num_components * 4) - 1024;
713 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
714 off -= off2;
715 }
716
717 if (ptrsz == 2) {
718 struct ir3_instruction *carry;
719
720 /* handle 32b rollover, ie:
721 * if (addr < base_lo)
722 * base_hi++
723 */
724 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
725 carry->cat2.condition = IR3_COND_LT;
726 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
727
728 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
729 }
730
731 for (int i = 0; i < intr->num_components; i++) {
732 struct ir3_instruction *load =
733 ir3_LDG(b, addr, 0, create_immed(b, 1), 0);
734 load->cat6.type = TYPE_U32;
735 load->cat6.src_offset = off + i * 4; /* byte offset */
736 dst[i] = load;
737 }
738 }
739
740 /* src[] = { buffer_index, offset }. No const_index */
741 static void
742 emit_intrinsic_load_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
743 struct ir3_instruction **dst)
744 {
745 struct ir3_block *b = ctx->block;
746 struct ir3_instruction *ldgb, *src0, *src1, *offset;
747 nir_const_value *const_offset;
748
749 /* can this be non-const buffer_index? how do we handle that? */
750 const_offset = nir_src_as_const_value(intr->src[0]);
751 compile_assert(ctx, const_offset);
752
753 offset = ir3_get_src(ctx, &intr->src[1])[0];
754
755 /* src0 is uvec2(offset*4, 0), src1 is offset.. nir already *= 4: */
756 src0 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
757 offset,
758 create_immed(b, 0),
759 }, 2);
760 src1 = ir3_SHR_B(b, offset, 0, create_immed(b, 2), 0);
761
762 ldgb = ir3_LDGB(b, create_immed(b, const_offset->u32[0]), 0,
763 src0, 0, src1, 0);
764 ldgb->regs[0]->wrmask = MASK(intr->num_components);
765 ldgb->cat6.iim_val = intr->num_components;
766 ldgb->cat6.d = 4;
767 ldgb->cat6.type = TYPE_U32;
768 ldgb->barrier_class = IR3_BARRIER_BUFFER_R;
769 ldgb->barrier_conflict = IR3_BARRIER_BUFFER_W;
770
771 ir3_split_dest(b, dst, ldgb, 0, intr->num_components);
772 }
773
774 /* src[] = { value, block_index, offset }. const_index[] = { write_mask } */
775 static void
776 emit_intrinsic_store_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr)
777 {
778 struct ir3_block *b = ctx->block;
779 struct ir3_instruction *stgb, *src0, *src1, *src2, *offset;
780 nir_const_value *const_offset;
781 /* TODO handle wrmask properly, see _store_shared().. but I think
782 * it is more a PITA than that, since blob ends up loading the
783 * masked components and writing them back out.
784 */
785 unsigned wrmask = intr->const_index[0];
786 unsigned ncomp = ffs(~wrmask) - 1;
787
788 /* can this be non-const buffer_index? how do we handle that? */
789 const_offset = nir_src_as_const_value(intr->src[1]);
790 compile_assert(ctx, const_offset);
791
792 offset = ir3_get_src(ctx, &intr->src[2])[0];
793
794 /* src0 is value, src1 is offset, src2 is uvec2(offset*4, 0)..
795 * nir already *= 4:
796 */
797 src0 = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]), ncomp);
798 src1 = ir3_SHR_B(b, offset, 0, create_immed(b, 2), 0);
799 src2 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
800 offset,
801 create_immed(b, 0),
802 }, 2);
803
804 stgb = ir3_STGB(b, create_immed(b, const_offset->u32[0]), 0,
805 src0, 0, src1, 0, src2, 0);
806 stgb->cat6.iim_val = ncomp;
807 stgb->cat6.d = 4;
808 stgb->cat6.type = TYPE_U32;
809 stgb->barrier_class = IR3_BARRIER_BUFFER_W;
810 stgb->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
811
812 array_insert(b, b->keeps, stgb);
813 }
814
815 /* src[] = { block_index } */
816 static void
817 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
818 struct ir3_instruction **dst)
819 {
820 /* SSBO size stored as a const starting at ssbo_sizes: */
821 unsigned blk_idx = nir_src_as_const_value(intr->src[0])->u32[0];
822 unsigned idx = regid(ctx->so->constbase.ssbo_sizes, 0) +
823 ctx->so->const_layout.ssbo_size.off[blk_idx];
824
825 debug_assert(ctx->so->const_layout.ssbo_size.mask & (1 << blk_idx));
826
827 dst[0] = create_uniform(ctx->block, idx);
828 }
829
830 /*
831 * SSBO atomic intrinsics
832 *
833 * All of the SSBO atomic memory operations read a value from memory,
834 * compute a new value using one of the operations below, write the new
835 * value to memory, and return the original value read.
836 *
837 * All operations take 3 sources except CompSwap that takes 4. These
838 * sources represent:
839 *
840 * 0: The SSBO buffer index.
841 * 1: The offset into the SSBO buffer of the variable that the atomic
842 * operation will operate on.
843 * 2: The data parameter to the atomic function (i.e. the value to add
844 * in ssbo_atomic_add, etc).
845 * 3: For CompSwap only: the second data parameter.
846 */
847 static struct ir3_instruction *
848 emit_intrinsic_atomic_ssbo(struct ir3_context *ctx, nir_intrinsic_instr *intr)
849 {
850 struct ir3_block *b = ctx->block;
851 struct ir3_instruction *atomic, *ssbo, *src0, *src1, *src2, *offset;
852 nir_const_value *const_offset;
853 type_t type = TYPE_U32;
854
855 /* can this be non-const buffer_index? how do we handle that? */
856 const_offset = nir_src_as_const_value(intr->src[0]);
857 compile_assert(ctx, const_offset);
858 ssbo = create_immed(b, const_offset->u32[0]);
859
860 offset = ir3_get_src(ctx, &intr->src[1])[0];
861
862 /* src0 is data (or uvec2(data, compare))
863 * src1 is offset
864 * src2 is uvec2(offset*4, 0) (appears to be 64b byte offset)
865 *
866 * Note that nir already multiplies the offset by four
867 */
868 src0 = ir3_get_src(ctx, &intr->src[2])[0];
869 src1 = ir3_SHR_B(b, offset, 0, create_immed(b, 2), 0);
870 src2 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
871 offset,
872 create_immed(b, 0),
873 }, 2);
874
875 switch (intr->intrinsic) {
876 case nir_intrinsic_ssbo_atomic_add:
877 atomic = ir3_ATOMIC_ADD_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
878 break;
879 case nir_intrinsic_ssbo_atomic_imin:
880 atomic = ir3_ATOMIC_MIN_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
881 type = TYPE_S32;
882 break;
883 case nir_intrinsic_ssbo_atomic_umin:
884 atomic = ir3_ATOMIC_MIN_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
885 break;
886 case nir_intrinsic_ssbo_atomic_imax:
887 atomic = ir3_ATOMIC_MAX_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
888 type = TYPE_S32;
889 break;
890 case nir_intrinsic_ssbo_atomic_umax:
891 atomic = ir3_ATOMIC_MAX_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
892 break;
893 case nir_intrinsic_ssbo_atomic_and:
894 atomic = ir3_ATOMIC_AND_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
895 break;
896 case nir_intrinsic_ssbo_atomic_or:
897 atomic = ir3_ATOMIC_OR_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
898 break;
899 case nir_intrinsic_ssbo_atomic_xor:
900 atomic = ir3_ATOMIC_XOR_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
901 break;
902 case nir_intrinsic_ssbo_atomic_exchange:
903 atomic = ir3_ATOMIC_XCHG_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
904 break;
905 case nir_intrinsic_ssbo_atomic_comp_swap:
906 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
907 src0 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
908 ir3_get_src(ctx, &intr->src[3])[0],
909 src0,
910 }, 2);
911 atomic = ir3_ATOMIC_CMPXCHG_G(b, ssbo, 0, src0, 0, src1, 0, src2, 0);
912 break;
913 default:
914 unreachable("boo");
915 }
916
917 atomic->cat6.iim_val = 1;
918 atomic->cat6.d = 4;
919 atomic->cat6.type = type;
920 atomic->barrier_class = IR3_BARRIER_BUFFER_W;
921 atomic->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
922
923 /* even if nothing consume the result, we can't DCE the instruction: */
924 array_insert(b, b->keeps, atomic);
925
926 return atomic;
927 }
928
929 /* src[] = { offset }. const_index[] = { base } */
930 static void
931 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
932 struct ir3_instruction **dst)
933 {
934 struct ir3_block *b = ctx->block;
935 struct ir3_instruction *ldl, *offset;
936 unsigned base;
937
938 offset = ir3_get_src(ctx, &intr->src[0])[0];
939 base = nir_intrinsic_base(intr);
940
941 ldl = ir3_LDL(b, offset, 0, create_immed(b, intr->num_components), 0);
942 ldl->cat6.src_offset = base;
943 ldl->cat6.type = utype_dst(intr->dest);
944 ldl->regs[0]->wrmask = MASK(intr->num_components);
945
946 ldl->barrier_class = IR3_BARRIER_SHARED_R;
947 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
948
949 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
950 }
951
952 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
953 static void
954 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
955 {
956 struct ir3_block *b = ctx->block;
957 struct ir3_instruction *stl, *offset;
958 struct ir3_instruction * const *value;
959 unsigned base, wrmask;
960
961 value = ir3_get_src(ctx, &intr->src[0]);
962 offset = ir3_get_src(ctx, &intr->src[1])[0];
963
964 base = nir_intrinsic_base(intr);
965 wrmask = nir_intrinsic_write_mask(intr);
966
967 /* Combine groups of consecutive enabled channels in one write
968 * message. We use ffs to find the first enabled channel and then ffs on
969 * the bit-inverse, down-shifted writemask to determine the length of
970 * the block of enabled bits.
971 *
972 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
973 */
974 while (wrmask) {
975 unsigned first_component = ffs(wrmask) - 1;
976 unsigned length = ffs(~(wrmask >> first_component)) - 1;
977
978 stl = ir3_STL(b, offset, 0,
979 ir3_create_collect(ctx, &value[first_component], length), 0,
980 create_immed(b, length), 0);
981 stl->cat6.dst_offset = first_component + base;
982 stl->cat6.type = utype_src(intr->src[0]);
983 stl->barrier_class = IR3_BARRIER_SHARED_W;
984 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
985
986 array_insert(b, b->keeps, stl);
987
988 /* Clear the bits in the writemask that we just wrote, then try
989 * again to see if more channels are left.
990 */
991 wrmask &= (15 << (first_component + length));
992 }
993 }
994
995 /*
996 * CS shared variable atomic intrinsics
997 *
998 * All of the shared variable atomic memory operations read a value from
999 * memory, compute a new value using one of the operations below, write the
1000 * new value to memory, and return the original value read.
1001 *
1002 * All operations take 2 sources except CompSwap that takes 3. These
1003 * sources represent:
1004 *
1005 * 0: The offset into the shared variable storage region that the atomic
1006 * operation will operate on.
1007 * 1: The data parameter to the atomic function (i.e. the value to add
1008 * in shared_atomic_add, etc).
1009 * 2: For CompSwap only: the second data parameter.
1010 */
1011 static struct ir3_instruction *
1012 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1013 {
1014 struct ir3_block *b = ctx->block;
1015 struct ir3_instruction *atomic, *src0, *src1;
1016 type_t type = TYPE_U32;
1017
1018 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
1019 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
1020
1021 switch (intr->intrinsic) {
1022 case nir_intrinsic_shared_atomic_add:
1023 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
1024 break;
1025 case nir_intrinsic_shared_atomic_imin:
1026 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
1027 type = TYPE_S32;
1028 break;
1029 case nir_intrinsic_shared_atomic_umin:
1030 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
1031 break;
1032 case nir_intrinsic_shared_atomic_imax:
1033 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1034 type = TYPE_S32;
1035 break;
1036 case nir_intrinsic_shared_atomic_umax:
1037 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1038 break;
1039 case nir_intrinsic_shared_atomic_and:
1040 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
1041 break;
1042 case nir_intrinsic_shared_atomic_or:
1043 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
1044 break;
1045 case nir_intrinsic_shared_atomic_xor:
1046 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
1047 break;
1048 case nir_intrinsic_shared_atomic_exchange:
1049 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
1050 break;
1051 case nir_intrinsic_shared_atomic_comp_swap:
1052 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1053 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1054 ir3_get_src(ctx, &intr->src[2])[0],
1055 src1,
1056 }, 2);
1057 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
1058 break;
1059 default:
1060 unreachable("boo");
1061 }
1062
1063 atomic->cat6.iim_val = 1;
1064 atomic->cat6.d = 1;
1065 atomic->cat6.type = type;
1066 atomic->barrier_class = IR3_BARRIER_SHARED_W;
1067 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
1068
1069 /* even if nothing consume the result, we can't DCE the instruction: */
1070 array_insert(b, b->keeps, atomic);
1071
1072 return atomic;
1073 }
1074
1075 /* Images get mapped into SSBO/image state (for store/atomic) and texture
1076 * state block (for load). To simplify things, invert the image id and
1077 * map it from end of state block, ie. image 0 becomes num-1, image 1
1078 * becomes num-2, etc. This potentially avoids needing to re-emit texture
1079 * state when switching shaders.
1080 *
1081 * TODO is max # of samplers and SSBOs the same. This shouldn't be hard-
1082 * coded. Also, since all the gl shader stages (ie. everything but CS)
1083 * share the same SSBO/image state block, this might require some more
1084 * logic if we supported images in anything other than FS..
1085 */
1086 static unsigned
1087 get_image_slot(struct ir3_context *ctx, nir_deref_instr *deref)
1088 {
1089 unsigned int loc = 0;
1090 unsigned inner_size = 1;
1091
1092 while (deref->deref_type != nir_deref_type_var) {
1093 assert(deref->deref_type == nir_deref_type_array);
1094 nir_const_value *const_index = nir_src_as_const_value(deref->arr.index);
1095 assert(const_index);
1096
1097 /* Go to the next instruction */
1098 deref = nir_deref_instr_parent(deref);
1099
1100 assert(glsl_type_is_array(deref->type));
1101 const unsigned array_len = glsl_get_length(deref->type);
1102 loc += MIN2(const_index->u32[0], array_len - 1) * inner_size;
1103
1104 /* Update the inner size */
1105 inner_size *= array_len;
1106 }
1107
1108 loc += deref->var->data.driver_location;
1109
1110 /* TODO figure out real limit per generation, and don't hardcode: */
1111 const unsigned max_samplers = 16;
1112 return max_samplers - loc - 1;
1113 }
1114
1115 /* see tex_info() for equiv logic for texture instructions.. it would be
1116 * nice if this could be better unified..
1117 */
1118 static unsigned
1119 get_image_coords(const nir_variable *var, unsigned *flagsp)
1120 {
1121 const struct glsl_type *type = glsl_without_array(var->type);
1122 unsigned coords, flags = 0;
1123
1124 switch (glsl_get_sampler_dim(type)) {
1125 case GLSL_SAMPLER_DIM_1D:
1126 case GLSL_SAMPLER_DIM_BUF:
1127 coords = 1;
1128 break;
1129 case GLSL_SAMPLER_DIM_2D:
1130 case GLSL_SAMPLER_DIM_RECT:
1131 case GLSL_SAMPLER_DIM_EXTERNAL:
1132 case GLSL_SAMPLER_DIM_MS:
1133 coords = 2;
1134 break;
1135 case GLSL_SAMPLER_DIM_3D:
1136 case GLSL_SAMPLER_DIM_CUBE:
1137 flags |= IR3_INSTR_3D;
1138 coords = 3;
1139 break;
1140 default:
1141 unreachable("bad sampler dim");
1142 return 0;
1143 }
1144
1145 if (glsl_sampler_type_is_array(type)) {
1146 /* note: unlike tex_info(), adjust # of coords to include array idx: */
1147 coords++;
1148 flags |= IR3_INSTR_A;
1149 }
1150
1151 if (flagsp)
1152 *flagsp = flags;
1153
1154 return coords;
1155 }
1156
1157 static type_t
1158 get_image_type(const nir_variable *var)
1159 {
1160 switch (glsl_get_sampler_result_type(glsl_without_array(var->type))) {
1161 case GLSL_TYPE_UINT:
1162 return TYPE_U32;
1163 case GLSL_TYPE_INT:
1164 return TYPE_S32;
1165 case GLSL_TYPE_FLOAT:
1166 return TYPE_F32;
1167 default:
1168 unreachable("bad sampler type.");
1169 return 0;
1170 }
1171 }
1172
1173 static struct ir3_instruction *
1174 get_image_offset(struct ir3_context *ctx, const nir_variable *var,
1175 struct ir3_instruction * const *coords, bool byteoff)
1176 {
1177 struct ir3_block *b = ctx->block;
1178 struct ir3_instruction *offset;
1179 unsigned ncoords = get_image_coords(var, NULL);
1180
1181 /* to calculate the byte offset (yes, uggg) we need (up to) three
1182 * const values to know the bytes per pixel, and y and z stride:
1183 */
1184 unsigned cb = regid(ctx->so->constbase.image_dims, 0) +
1185 ctx->so->const_layout.image_dims.off[var->data.driver_location];
1186
1187 debug_assert(ctx->so->const_layout.image_dims.mask &
1188 (1 << var->data.driver_location));
1189
1190 /* offset = coords.x * bytes_per_pixel: */
1191 offset = ir3_MUL_S(b, coords[0], 0, create_uniform(b, cb + 0), 0);
1192 if (ncoords > 1) {
1193 /* offset += coords.y * y_pitch: */
1194 offset = ir3_MAD_S24(b, create_uniform(b, cb + 1), 0,
1195 coords[1], 0, offset, 0);
1196 }
1197 if (ncoords > 2) {
1198 /* offset += coords.z * z_pitch: */
1199 offset = ir3_MAD_S24(b, create_uniform(b, cb + 2), 0,
1200 coords[2], 0, offset, 0);
1201 }
1202
1203 if (!byteoff) {
1204 /* Some cases, like atomics, seem to use dword offset instead
1205 * of byte offsets.. blob just puts an extra shr.b in there
1206 * in those cases:
1207 */
1208 offset = ir3_SHR_B(b, offset, 0, create_immed(b, 2), 0);
1209 }
1210
1211 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1212 offset,
1213 create_immed(b, 0),
1214 }, 2);
1215 }
1216
1217 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1218 static void
1219 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1220 struct ir3_instruction **dst)
1221 {
1222 struct ir3_block *b = ctx->block;
1223 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1224 struct ir3_instruction *sam;
1225 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
1226 struct ir3_instruction *coords[4];
1227 unsigned flags, ncoords = get_image_coords(var, &flags);
1228 unsigned tex_idx = get_image_slot(ctx, nir_src_as_deref(intr->src[0]));
1229 type_t type = get_image_type(var);
1230
1231 /* hmm, this seems a bit odd, but it is what blob does and (at least
1232 * a5xx) just faults on bogus addresses otherwise:
1233 */
1234 if (flags & IR3_INSTR_3D) {
1235 flags &= ~IR3_INSTR_3D;
1236 flags |= IR3_INSTR_A;
1237 }
1238
1239 for (unsigned i = 0; i < ncoords; i++)
1240 coords[i] = src0[i];
1241
1242 if (ncoords == 1)
1243 coords[ncoords++] = create_immed(b, 0);
1244
1245 sam = ir3_SAM(b, OPC_ISAM, type, 0b1111, flags,
1246 tex_idx, tex_idx, ir3_create_collect(ctx, coords, ncoords), NULL);
1247
1248 sam->barrier_class = IR3_BARRIER_IMAGE_R;
1249 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
1250
1251 ir3_split_dest(b, dst, sam, 0, 4);
1252 }
1253
1254 /* src[] = { deref, coord, sample_index, value }. const_index[] = {} */
1255 static void
1256 emit_intrinsic_store_image(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1257 {
1258 struct ir3_block *b = ctx->block;
1259 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1260 struct ir3_instruction *stib, *offset;
1261 struct ir3_instruction * const *value = ir3_get_src(ctx, &intr->src[3]);
1262 struct ir3_instruction * const *coords = ir3_get_src(ctx, &intr->src[1]);
1263 unsigned ncoords = get_image_coords(var, NULL);
1264 unsigned tex_idx = get_image_slot(ctx, nir_src_as_deref(intr->src[0]));
1265
1266 /* src0 is value
1267 * src1 is coords
1268 * src2 is 64b byte offset
1269 */
1270
1271 offset = get_image_offset(ctx, var, coords, true);
1272
1273 /* NOTE: stib seems to take byte offset, but stgb.typed can be used
1274 * too and takes a dword offset.. not quite sure yet why blob uses
1275 * one over the other in various cases.
1276 */
1277
1278 stib = ir3_STIB(b, create_immed(b, tex_idx), 0,
1279 ir3_create_collect(ctx, value, 4), 0,
1280 ir3_create_collect(ctx, coords, ncoords), 0,
1281 offset, 0);
1282 stib->cat6.iim_val = 4;
1283 stib->cat6.d = ncoords;
1284 stib->cat6.type = get_image_type(var);
1285 stib->cat6.typed = true;
1286 stib->barrier_class = IR3_BARRIER_IMAGE_W;
1287 stib->barrier_conflict = IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W;
1288
1289 array_insert(b, b->keeps, stib);
1290 }
1291
1292 static void
1293 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1294 struct ir3_instruction **dst)
1295 {
1296 struct ir3_block *b = ctx->block;
1297 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1298 unsigned tex_idx = get_image_slot(ctx, nir_src_as_deref(intr->src[0]));
1299 struct ir3_instruction *sam, *lod;
1300 unsigned flags, ncoords = get_image_coords(var, &flags);
1301
1302 lod = create_immed(b, 0);
1303 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
1304 tex_idx, tex_idx, lod, NULL);
1305
1306 /* Array size actually ends up in .w rather than .z. This doesn't
1307 * matter for miplevel 0, but for higher mips the value in z is
1308 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1309 * returned, which means that we have to add 1 to it for arrays for
1310 * a3xx.
1311 *
1312 * Note use a temporary dst and then copy, since the size of the dst
1313 * array that is passed in is based on nir's understanding of the
1314 * result size, not the hardware's
1315 */
1316 struct ir3_instruction *tmp[4];
1317
1318 ir3_split_dest(b, tmp, sam, 0, 4);
1319
1320 /* get_size instruction returns size in bytes instead of texels
1321 * for imageBuffer, so we need to divide it by the pixel size
1322 * of the image format.
1323 *
1324 * TODO: This is at least true on a5xx. Check other gens.
1325 */
1326 enum glsl_sampler_dim dim =
1327 glsl_get_sampler_dim(glsl_without_array(var->type));
1328 if (dim == GLSL_SAMPLER_DIM_BUF) {
1329 /* Since all the possible values the divisor can take are
1330 * power-of-two (4, 8, or 16), the division is implemented
1331 * as a shift-right.
1332 * During shader setup, the log2 of the image format's
1333 * bytes-per-pixel should have been emitted in 2nd slot of
1334 * image_dims. See ir3_shader::emit_image_dims().
1335 */
1336 unsigned cb = regid(ctx->so->constbase.image_dims, 0) +
1337 ctx->so->const_layout.image_dims.off[var->data.driver_location];
1338 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1339
1340 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1341 }
1342
1343 for (unsigned i = 0; i < ncoords; i++)
1344 dst[i] = tmp[i];
1345
1346 if (flags & IR3_INSTR_A) {
1347 if (ctx->compiler->levels_add_one) {
1348 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1349 } else {
1350 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1351 }
1352 }
1353 }
1354
1355 /* src[] = { deref, coord, sample_index, value, compare }. const_index[] = {} */
1356 static struct ir3_instruction *
1357 emit_intrinsic_atomic_image(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1358 {
1359 struct ir3_block *b = ctx->block;
1360 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1361 struct ir3_instruction *atomic, *image, *src0, *src1, *src2;
1362 struct ir3_instruction * const *coords = ir3_get_src(ctx, &intr->src[1]);
1363 unsigned ncoords = get_image_coords(var, NULL);
1364
1365 image = create_immed(b, get_image_slot(ctx, nir_src_as_deref(intr->src[0])));
1366
1367 /* src0 is value (or uvec2(value, compare))
1368 * src1 is coords
1369 * src2 is 64b byte offset
1370 */
1371 src0 = ir3_get_src(ctx, &intr->src[3])[0];
1372 src1 = ir3_create_collect(ctx, coords, ncoords);
1373 src2 = get_image_offset(ctx, var, coords, false);
1374
1375 switch (intr->intrinsic) {
1376 case nir_intrinsic_image_deref_atomic_add:
1377 atomic = ir3_ATOMIC_ADD_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1378 break;
1379 case nir_intrinsic_image_deref_atomic_min:
1380 atomic = ir3_ATOMIC_MIN_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1381 break;
1382 case nir_intrinsic_image_deref_atomic_max:
1383 atomic = ir3_ATOMIC_MAX_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1384 break;
1385 case nir_intrinsic_image_deref_atomic_and:
1386 atomic = ir3_ATOMIC_AND_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1387 break;
1388 case nir_intrinsic_image_deref_atomic_or:
1389 atomic = ir3_ATOMIC_OR_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1390 break;
1391 case nir_intrinsic_image_deref_atomic_xor:
1392 atomic = ir3_ATOMIC_XOR_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1393 break;
1394 case nir_intrinsic_image_deref_atomic_exchange:
1395 atomic = ir3_ATOMIC_XCHG_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1396 break;
1397 case nir_intrinsic_image_deref_atomic_comp_swap:
1398 /* for cmpxchg, src0 is [ui]vec2(data, compare): */
1399 src0 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1400 ir3_get_src(ctx, &intr->src[4])[0],
1401 src0,
1402 }, 2);
1403 atomic = ir3_ATOMIC_CMPXCHG_G(b, image, 0, src0, 0, src1, 0, src2, 0);
1404 break;
1405 default:
1406 unreachable("boo");
1407 }
1408
1409 atomic->cat6.iim_val = 1;
1410 atomic->cat6.d = ncoords;
1411 atomic->cat6.type = get_image_type(var);
1412 atomic->cat6.typed = true;
1413 atomic->barrier_class = IR3_BARRIER_IMAGE_W;
1414 atomic->barrier_conflict = IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W;
1415
1416 /* even if nothing consume the result, we can't DCE the instruction: */
1417 array_insert(b, b->keeps, atomic);
1418
1419 return atomic;
1420 }
1421
1422 static void
1423 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1424 {
1425 struct ir3_block *b = ctx->block;
1426 struct ir3_instruction *barrier;
1427
1428 switch (intr->intrinsic) {
1429 case nir_intrinsic_barrier:
1430 barrier = ir3_BAR(b);
1431 barrier->cat7.g = true;
1432 barrier->cat7.l = true;
1433 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1434 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1435 break;
1436 case nir_intrinsic_memory_barrier:
1437 barrier = ir3_FENCE(b);
1438 barrier->cat7.g = true;
1439 barrier->cat7.r = true;
1440 barrier->cat7.w = true;
1441 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1442 IR3_BARRIER_BUFFER_W;
1443 barrier->barrier_conflict =
1444 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1445 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1446 break;
1447 case nir_intrinsic_memory_barrier_atomic_counter:
1448 case nir_intrinsic_memory_barrier_buffer:
1449 barrier = ir3_FENCE(b);
1450 barrier->cat7.g = true;
1451 barrier->cat7.r = true;
1452 barrier->cat7.w = true;
1453 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1454 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1455 IR3_BARRIER_BUFFER_W;
1456 break;
1457 case nir_intrinsic_memory_barrier_image:
1458 // TODO double check if this should have .g set
1459 barrier = ir3_FENCE(b);
1460 barrier->cat7.g = true;
1461 barrier->cat7.r = true;
1462 barrier->cat7.w = true;
1463 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1464 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1465 IR3_BARRIER_IMAGE_W;
1466 break;
1467 case nir_intrinsic_memory_barrier_shared:
1468 barrier = ir3_FENCE(b);
1469 barrier->cat7.g = true;
1470 barrier->cat7.l = true;
1471 barrier->cat7.r = true;
1472 barrier->cat7.w = true;
1473 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1474 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1475 IR3_BARRIER_SHARED_W;
1476 break;
1477 case nir_intrinsic_group_memory_barrier:
1478 barrier = ir3_FENCE(b);
1479 barrier->cat7.g = true;
1480 barrier->cat7.l = true;
1481 barrier->cat7.r = true;
1482 barrier->cat7.w = true;
1483 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1484 IR3_BARRIER_IMAGE_W |
1485 IR3_BARRIER_BUFFER_W;
1486 barrier->barrier_conflict =
1487 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1488 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1489 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1490 break;
1491 default:
1492 unreachable("boo");
1493 }
1494
1495 /* make sure barrier doesn't get DCE'd */
1496 array_insert(b, b->keeps, barrier);
1497 }
1498
1499 static void add_sysval_input_compmask(struct ir3_context *ctx,
1500 gl_system_value slot, unsigned compmask,
1501 struct ir3_instruction *instr)
1502 {
1503 struct ir3_shader_variant *so = ctx->so;
1504 unsigned r = regid(so->inputs_count, 0);
1505 unsigned n = so->inputs_count++;
1506
1507 so->inputs[n].sysval = true;
1508 so->inputs[n].slot = slot;
1509 so->inputs[n].compmask = compmask;
1510 so->inputs[n].regid = r;
1511 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1512 so->total_in++;
1513
1514 ctx->ir->ninputs = MAX2(ctx->ir->ninputs, r + 1);
1515 ctx->ir->inputs[r] = instr;
1516 }
1517
1518 static void add_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1519 struct ir3_instruction *instr)
1520 {
1521 add_sysval_input_compmask(ctx, slot, 0x1, instr);
1522 }
1523
1524 static void
1525 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1526 {
1527 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1528 struct ir3_instruction **dst;
1529 struct ir3_instruction * const *src;
1530 struct ir3_block *b = ctx->block;
1531 nir_const_value *const_offset;
1532 int idx, comp;
1533
1534 if (info->has_dest) {
1535 unsigned n = nir_intrinsic_dest_components(intr);
1536 dst = ir3_get_dst(ctx, &intr->dest, n);
1537 } else {
1538 dst = NULL;
1539 }
1540
1541 switch (intr->intrinsic) {
1542 case nir_intrinsic_load_uniform:
1543 idx = nir_intrinsic_base(intr);
1544 const_offset = nir_src_as_const_value(intr->src[0]);
1545 if (const_offset) {
1546 idx += const_offset->u32[0];
1547 for (int i = 0; i < intr->num_components; i++) {
1548 unsigned n = idx * 4 + i;
1549 dst[i] = create_uniform(b, n);
1550 }
1551 } else {
1552 src = ir3_get_src(ctx, &intr->src[0]);
1553 for (int i = 0; i < intr->num_components; i++) {
1554 int n = idx * 4 + i;
1555 dst[i] = create_uniform_indirect(b, n,
1556 ir3_get_addr(ctx, src[0], 4));
1557 }
1558 /* NOTE: if relative addressing is used, we set
1559 * constlen in the compiler (to worst-case value)
1560 * since we don't know in the assembler what the max
1561 * addr reg value can be:
1562 */
1563 ctx->so->constlen = ctx->s->num_uniforms;
1564 }
1565 break;
1566 case nir_intrinsic_load_ubo:
1567 emit_intrinsic_load_ubo(ctx, intr, dst);
1568 break;
1569 case nir_intrinsic_load_input:
1570 idx = nir_intrinsic_base(intr);
1571 comp = nir_intrinsic_component(intr);
1572 const_offset = nir_src_as_const_value(intr->src[0]);
1573 if (const_offset) {
1574 idx += const_offset->u32[0];
1575 for (int i = 0; i < intr->num_components; i++) {
1576 unsigned n = idx * 4 + i + comp;
1577 dst[i] = ctx->ir->inputs[n];
1578 }
1579 } else {
1580 src = ir3_get_src(ctx, &intr->src[0]);
1581 struct ir3_instruction *collect =
1582 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ir->ninputs);
1583 struct ir3_instruction *addr = ir3_get_addr(ctx, src[0], 4);
1584 for (int i = 0; i < intr->num_components; i++) {
1585 unsigned n = idx * 4 + i + comp;
1586 dst[i] = create_indirect_load(ctx, ctx->ir->ninputs,
1587 n, addr, collect);
1588 }
1589 }
1590 break;
1591 case nir_intrinsic_load_ssbo:
1592 emit_intrinsic_load_ssbo(ctx, intr, dst);
1593 break;
1594 case nir_intrinsic_store_ssbo:
1595 emit_intrinsic_store_ssbo(ctx, intr);
1596 break;
1597 case nir_intrinsic_get_buffer_size:
1598 emit_intrinsic_ssbo_size(ctx, intr, dst);
1599 break;
1600 case nir_intrinsic_ssbo_atomic_add:
1601 case nir_intrinsic_ssbo_atomic_imin:
1602 case nir_intrinsic_ssbo_atomic_umin:
1603 case nir_intrinsic_ssbo_atomic_imax:
1604 case nir_intrinsic_ssbo_atomic_umax:
1605 case nir_intrinsic_ssbo_atomic_and:
1606 case nir_intrinsic_ssbo_atomic_or:
1607 case nir_intrinsic_ssbo_atomic_xor:
1608 case nir_intrinsic_ssbo_atomic_exchange:
1609 case nir_intrinsic_ssbo_atomic_comp_swap:
1610 dst[0] = emit_intrinsic_atomic_ssbo(ctx, intr);
1611 break;
1612 case nir_intrinsic_load_shared:
1613 emit_intrinsic_load_shared(ctx, intr, dst);
1614 break;
1615 case nir_intrinsic_store_shared:
1616 emit_intrinsic_store_shared(ctx, intr);
1617 break;
1618 case nir_intrinsic_shared_atomic_add:
1619 case nir_intrinsic_shared_atomic_imin:
1620 case nir_intrinsic_shared_atomic_umin:
1621 case nir_intrinsic_shared_atomic_imax:
1622 case nir_intrinsic_shared_atomic_umax:
1623 case nir_intrinsic_shared_atomic_and:
1624 case nir_intrinsic_shared_atomic_or:
1625 case nir_intrinsic_shared_atomic_xor:
1626 case nir_intrinsic_shared_atomic_exchange:
1627 case nir_intrinsic_shared_atomic_comp_swap:
1628 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1629 break;
1630 case nir_intrinsic_image_deref_load:
1631 emit_intrinsic_load_image(ctx, intr, dst);
1632 break;
1633 case nir_intrinsic_image_deref_store:
1634 emit_intrinsic_store_image(ctx, intr);
1635 break;
1636 case nir_intrinsic_image_deref_size:
1637 emit_intrinsic_image_size(ctx, intr, dst);
1638 break;
1639 case nir_intrinsic_image_deref_atomic_add:
1640 case nir_intrinsic_image_deref_atomic_min:
1641 case nir_intrinsic_image_deref_atomic_max:
1642 case nir_intrinsic_image_deref_atomic_and:
1643 case nir_intrinsic_image_deref_atomic_or:
1644 case nir_intrinsic_image_deref_atomic_xor:
1645 case nir_intrinsic_image_deref_atomic_exchange:
1646 case nir_intrinsic_image_deref_atomic_comp_swap:
1647 dst[0] = emit_intrinsic_atomic_image(ctx, intr);
1648 break;
1649 case nir_intrinsic_barrier:
1650 case nir_intrinsic_memory_barrier:
1651 case nir_intrinsic_group_memory_barrier:
1652 case nir_intrinsic_memory_barrier_atomic_counter:
1653 case nir_intrinsic_memory_barrier_buffer:
1654 case nir_intrinsic_memory_barrier_image:
1655 case nir_intrinsic_memory_barrier_shared:
1656 emit_intrinsic_barrier(ctx, intr);
1657 /* note that blk ptr no longer valid, make that obvious: */
1658 b = NULL;
1659 break;
1660 case nir_intrinsic_store_output:
1661 idx = nir_intrinsic_base(intr);
1662 comp = nir_intrinsic_component(intr);
1663 const_offset = nir_src_as_const_value(intr->src[1]);
1664 compile_assert(ctx, const_offset != NULL);
1665 idx += const_offset->u32[0];
1666
1667 src = ir3_get_src(ctx, &intr->src[0]);
1668 for (int i = 0; i < intr->num_components; i++) {
1669 unsigned n = idx * 4 + i + comp;
1670 ctx->ir->outputs[n] = src[i];
1671 }
1672 break;
1673 case nir_intrinsic_load_base_vertex:
1674 case nir_intrinsic_load_first_vertex:
1675 if (!ctx->basevertex) {
1676 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1677 add_sysval_input(ctx, SYSTEM_VALUE_FIRST_VERTEX, ctx->basevertex);
1678 }
1679 dst[0] = ctx->basevertex;
1680 break;
1681 case nir_intrinsic_load_vertex_id_zero_base:
1682 case nir_intrinsic_load_vertex_id:
1683 if (!ctx->vertex_id) {
1684 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1685 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1686 ctx->vertex_id = create_input(ctx, 0);
1687 add_sysval_input(ctx, sv, ctx->vertex_id);
1688 }
1689 dst[0] = ctx->vertex_id;
1690 break;
1691 case nir_intrinsic_load_instance_id:
1692 if (!ctx->instance_id) {
1693 ctx->instance_id = create_input(ctx, 0);
1694 add_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID,
1695 ctx->instance_id);
1696 }
1697 dst[0] = ctx->instance_id;
1698 break;
1699 case nir_intrinsic_load_sample_id:
1700 case nir_intrinsic_load_sample_id_no_per_sample:
1701 if (!ctx->samp_id) {
1702 ctx->samp_id = create_input(ctx, 0);
1703 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1704 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID,
1705 ctx->samp_id);
1706 }
1707 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1708 break;
1709 case nir_intrinsic_load_sample_mask_in:
1710 if (!ctx->samp_mask_in) {
1711 ctx->samp_mask_in = create_input(ctx, 0);
1712 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN,
1713 ctx->samp_mask_in);
1714 }
1715 dst[0] = ctx->samp_mask_in;
1716 break;
1717 case nir_intrinsic_load_user_clip_plane:
1718 idx = nir_intrinsic_ucp_id(intr);
1719 for (int i = 0; i < intr->num_components; i++) {
1720 unsigned n = idx * 4 + i;
1721 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1722 }
1723 break;
1724 case nir_intrinsic_load_front_face:
1725 if (!ctx->frag_face) {
1726 ctx->so->frag_face = true;
1727 ctx->frag_face = create_input(ctx, 0);
1728 add_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, ctx->frag_face);
1729 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1730 }
1731 /* for fragface, we get -1 for back and 0 for front. However this is
1732 * the inverse of what nir expects (where ~0 is true).
1733 */
1734 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1735 dst[0] = ir3_NOT_B(b, dst[0], 0);
1736 break;
1737 case nir_intrinsic_load_local_invocation_id:
1738 if (!ctx->local_invocation_id) {
1739 ctx->local_invocation_id = create_input_compmask(ctx, 0, 0x7);
1740 add_sysval_input_compmask(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID,
1741 0x7, ctx->local_invocation_id);
1742 }
1743 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1744 break;
1745 case nir_intrinsic_load_work_group_id:
1746 if (!ctx->work_group_id) {
1747 ctx->work_group_id = create_input_compmask(ctx, 0, 0x7);
1748 add_sysval_input_compmask(ctx, SYSTEM_VALUE_WORK_GROUP_ID,
1749 0x7, ctx->work_group_id);
1750 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1751 }
1752 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1753 break;
1754 case nir_intrinsic_load_num_work_groups:
1755 for (int i = 0; i < intr->num_components; i++) {
1756 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1757 }
1758 break;
1759 case nir_intrinsic_load_local_group_size:
1760 for (int i = 0; i < intr->num_components; i++) {
1761 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1762 }
1763 break;
1764 case nir_intrinsic_discard_if:
1765 case nir_intrinsic_discard: {
1766 struct ir3_instruction *cond, *kill;
1767
1768 if (intr->intrinsic == nir_intrinsic_discard_if) {
1769 /* conditional discard: */
1770 src = ir3_get_src(ctx, &intr->src[0]);
1771 cond = ir3_b2n(b, src[0]);
1772 } else {
1773 /* unconditional discard: */
1774 cond = create_immed(b, 1);
1775 }
1776
1777 /* NOTE: only cmps.*.* can write p0.x: */
1778 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1779 cond->cat2.condition = IR3_COND_NE;
1780
1781 /* condition always goes in predicate register: */
1782 cond->regs[0]->num = regid(REG_P0, 0);
1783
1784 kill = ir3_KILL(b, cond, 0);
1785 array_insert(ctx->ir, ctx->ir->predicates, kill);
1786
1787 array_insert(b, b->keeps, kill);
1788 ctx->so->has_kill = true;
1789
1790 break;
1791 }
1792 default:
1793 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1794 nir_intrinsic_infos[intr->intrinsic].name);
1795 break;
1796 }
1797
1798 if (info->has_dest)
1799 put_dst(ctx, &intr->dest);
1800 }
1801
1802 static void
1803 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1804 {
1805 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1806 instr->def.num_components);
1807 type_t type = (instr->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1808
1809 for (int i = 0; i < instr->def.num_components; i++)
1810 dst[i] = create_immed_typed(ctx->block, instr->value.u32[i], type);
1811 }
1812
1813 static void
1814 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1815 {
1816 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1817 undef->def.num_components);
1818 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1819
1820 /* backend doesn't want undefined instructions, so just plug
1821 * in 0.0..
1822 */
1823 for (int i = 0; i < undef->def.num_components; i++)
1824 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1825 }
1826
1827 /*
1828 * texture fetch/sample instructions:
1829 */
1830
1831 static void
1832 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1833 {
1834 unsigned coords, flags = 0;
1835
1836 /* note: would use tex->coord_components.. except txs.. also,
1837 * since array index goes after shadow ref, we don't want to
1838 * count it:
1839 */
1840 switch (tex->sampler_dim) {
1841 case GLSL_SAMPLER_DIM_1D:
1842 case GLSL_SAMPLER_DIM_BUF:
1843 coords = 1;
1844 break;
1845 case GLSL_SAMPLER_DIM_2D:
1846 case GLSL_SAMPLER_DIM_RECT:
1847 case GLSL_SAMPLER_DIM_EXTERNAL:
1848 case GLSL_SAMPLER_DIM_MS:
1849 coords = 2;
1850 break;
1851 case GLSL_SAMPLER_DIM_3D:
1852 case GLSL_SAMPLER_DIM_CUBE:
1853 coords = 3;
1854 flags |= IR3_INSTR_3D;
1855 break;
1856 default:
1857 unreachable("bad sampler_dim");
1858 }
1859
1860 if (tex->is_shadow && tex->op != nir_texop_lod)
1861 flags |= IR3_INSTR_S;
1862
1863 if (tex->is_array && tex->op != nir_texop_lod)
1864 flags |= IR3_INSTR_A;
1865
1866 *flagsp = flags;
1867 *coordsp = coords;
1868 }
1869
1870 static void
1871 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
1872 {
1873 struct ir3_block *b = ctx->block;
1874 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1875 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
1876 struct ir3_instruction *lod, *compare, *proj, *sample_index;
1877 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1878 unsigned i, coords, flags;
1879 unsigned nsrc0 = 0, nsrc1 = 0;
1880 type_t type;
1881 opc_t opc = 0;
1882
1883 coord = off = ddx = ddy = NULL;
1884 lod = proj = compare = sample_index = NULL;
1885
1886 /* TODO: might just be one component for gathers? */
1887 dst = ir3_get_dst(ctx, &tex->dest, 4);
1888
1889 for (unsigned i = 0; i < tex->num_srcs; i++) {
1890 switch (tex->src[i].src_type) {
1891 case nir_tex_src_coord:
1892 coord = ir3_get_src(ctx, &tex->src[i].src);
1893 break;
1894 case nir_tex_src_bias:
1895 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1896 has_bias = true;
1897 break;
1898 case nir_tex_src_lod:
1899 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1900 has_lod = true;
1901 break;
1902 case nir_tex_src_comparator: /* shadow comparator */
1903 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
1904 break;
1905 case nir_tex_src_projector:
1906 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
1907 has_proj = true;
1908 break;
1909 case nir_tex_src_offset:
1910 off = ir3_get_src(ctx, &tex->src[i].src);
1911 has_off = true;
1912 break;
1913 case nir_tex_src_ddx:
1914 ddx = ir3_get_src(ctx, &tex->src[i].src);
1915 break;
1916 case nir_tex_src_ddy:
1917 ddy = ir3_get_src(ctx, &tex->src[i].src);
1918 break;
1919 case nir_tex_src_ms_index:
1920 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
1921 break;
1922 default:
1923 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
1924 tex->src[i].src_type);
1925 return;
1926 }
1927 }
1928
1929 switch (tex->op) {
1930 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
1931 case nir_texop_txb: opc = OPC_SAMB; break;
1932 case nir_texop_txl: opc = OPC_SAML; break;
1933 case nir_texop_txd: opc = OPC_SAMGQ; break;
1934 case nir_texop_txf: opc = OPC_ISAML; break;
1935 case nir_texop_lod: opc = OPC_GETLOD; break;
1936 case nir_texop_tg4:
1937 /* NOTE: a4xx might need to emulate gather w/ txf (this is
1938 * what blob does, seems gather is broken?), and a3xx did
1939 * not support it (but probably could also emulate).
1940 */
1941 switch (tex->component) {
1942 case 0: opc = OPC_GATHER4R; break;
1943 case 1: opc = OPC_GATHER4G; break;
1944 case 2: opc = OPC_GATHER4B; break;
1945 case 3: opc = OPC_GATHER4A; break;
1946 }
1947 break;
1948 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
1949 case nir_texop_txs:
1950 case nir_texop_query_levels:
1951 case nir_texop_texture_samples:
1952 case nir_texop_samples_identical:
1953 case nir_texop_txf_ms_mcs:
1954 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
1955 return;
1956 }
1957
1958 tex_info(tex, &flags, &coords);
1959
1960 /*
1961 * lay out the first argument in the proper order:
1962 * - actual coordinates first
1963 * - shadow reference
1964 * - array index
1965 * - projection w
1966 * - starting at offset 4, dpdx.xy, dpdy.xy
1967 *
1968 * bias/lod go into the second arg
1969 */
1970
1971 /* insert tex coords: */
1972 for (i = 0; i < coords; i++)
1973 src0[i] = coord[i];
1974
1975 nsrc0 = i;
1976
1977 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
1978 * with scaled x coord according to requested sample:
1979 */
1980 if (tex->op == nir_texop_txf_ms) {
1981 if (ctx->compiler->txf_ms_with_isaml) {
1982 /* the samples are laid out in x dimension as
1983 * 0 1 2 3
1984 * x_ms = (x << ms) + sample_index;
1985 */
1986 struct ir3_instruction *ms;
1987 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
1988
1989 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
1990 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
1991
1992 opc = OPC_ISAML;
1993 } else {
1994 src0[nsrc0++] = sample_index;
1995 }
1996 }
1997
1998 /* scale up integer coords for TXF based on the LOD */
1999 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
2000 assert(has_lod);
2001 for (i = 0; i < coords; i++)
2002 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
2003 }
2004
2005 if (coords == 1) {
2006 /* hw doesn't do 1d, so we treat it as 2d with
2007 * height of 1, and patch up the y coord.
2008 * TODO: y coord should be (int)0 in some cases..
2009 */
2010 src0[nsrc0++] = create_immed(b, fui(0.5));
2011 }
2012
2013 if (tex->is_shadow && tex->op != nir_texop_lod)
2014 src0[nsrc0++] = compare;
2015
2016 if (tex->is_array && tex->op != nir_texop_lod) {
2017 struct ir3_instruction *idx = coord[coords];
2018
2019 /* the array coord for cube arrays needs 0.5 added to it */
2020 if (ctx->compiler->array_index_add_half && (opc != OPC_ISAML))
2021 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
2022
2023 src0[nsrc0++] = idx;
2024 }
2025
2026 if (has_proj) {
2027 src0[nsrc0++] = proj;
2028 flags |= IR3_INSTR_P;
2029 }
2030
2031 /* pad to 4, then ddx/ddy: */
2032 if (tex->op == nir_texop_txd) {
2033 while (nsrc0 < 4)
2034 src0[nsrc0++] = create_immed(b, fui(0.0));
2035 for (i = 0; i < coords; i++)
2036 src0[nsrc0++] = ddx[i];
2037 if (coords < 2)
2038 src0[nsrc0++] = create_immed(b, fui(0.0));
2039 for (i = 0; i < coords; i++)
2040 src0[nsrc0++] = ddy[i];
2041 if (coords < 2)
2042 src0[nsrc0++] = create_immed(b, fui(0.0));
2043 }
2044
2045 /*
2046 * second argument (if applicable):
2047 * - offsets
2048 * - lod
2049 * - bias
2050 */
2051 if (has_off | has_lod | has_bias) {
2052 if (has_off) {
2053 unsigned off_coords = coords;
2054 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2055 off_coords--;
2056 for (i = 0; i < off_coords; i++)
2057 src1[nsrc1++] = off[i];
2058 if (off_coords < 2)
2059 src1[nsrc1++] = create_immed(b, fui(0.0));
2060 flags |= IR3_INSTR_O;
2061 }
2062
2063 if (has_lod | has_bias)
2064 src1[nsrc1++] = lod;
2065 }
2066
2067 switch (tex->dest_type) {
2068 case nir_type_invalid:
2069 case nir_type_float:
2070 type = TYPE_F32;
2071 break;
2072 case nir_type_int:
2073 type = TYPE_S32;
2074 break;
2075 case nir_type_uint:
2076 case nir_type_bool:
2077 type = TYPE_U32;
2078 break;
2079 default:
2080 unreachable("bad dest_type");
2081 }
2082
2083 if (opc == OPC_GETLOD)
2084 type = TYPE_U32;
2085
2086 unsigned tex_idx = tex->texture_index;
2087
2088 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex_idx);
2089
2090 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
2091 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
2092
2093 sam = ir3_SAM(b, opc, type, 0b1111, flags,
2094 tex_idx, tex_idx, col0, col1);
2095
2096 if ((ctx->astc_srgb & (1 << tex_idx)) && !nir_tex_instr_is_query(tex)) {
2097 /* only need first 3 components: */
2098 sam->regs[0]->wrmask = 0x7;
2099 ir3_split_dest(b, dst, sam, 0, 3);
2100
2101 /* we need to sample the alpha separately with a non-ASTC
2102 * texture state:
2103 */
2104 sam = ir3_SAM(b, opc, type, 0b1000, flags,
2105 tex_idx, tex_idx, col0, col1);
2106
2107 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
2108
2109 /* fixup .w component: */
2110 ir3_split_dest(b, &dst[3], sam, 3, 1);
2111 } else {
2112 /* normal (non-workaround) case: */
2113 ir3_split_dest(b, dst, sam, 0, 4);
2114 }
2115
2116 /* GETLOD returns results in 4.8 fixed point */
2117 if (opc == OPC_GETLOD) {
2118 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
2119
2120 compile_assert(ctx, tex->dest_type == nir_type_float);
2121 for (i = 0; i < 2; i++) {
2122 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_U32, TYPE_F32), 0,
2123 factor, 0);
2124 }
2125 }
2126
2127 put_dst(ctx, &tex->dest);
2128 }
2129
2130 static void
2131 emit_tex_query_levels(struct ir3_context *ctx, nir_tex_instr *tex)
2132 {
2133 struct ir3_block *b = ctx->block;
2134 struct ir3_instruction **dst, *sam;
2135
2136 dst = ir3_get_dst(ctx, &tex->dest, 1);
2137
2138 sam = ir3_SAM(b, OPC_GETINFO, TYPE_U32, 0b0100, 0,
2139 tex->texture_index, tex->texture_index, NULL, NULL);
2140
2141 /* even though there is only one component, since it ends
2142 * up in .z rather than .x, we need a split_dest()
2143 */
2144 ir3_split_dest(b, dst, sam, 0, 3);
2145
2146 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2147 * the value in TEX_CONST_0 is zero-based.
2148 */
2149 if (ctx->compiler->levels_add_one)
2150 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2151
2152 put_dst(ctx, &tex->dest);
2153 }
2154
2155 static void
2156 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2157 {
2158 struct ir3_block *b = ctx->block;
2159 struct ir3_instruction **dst, *sam;
2160 struct ir3_instruction *lod;
2161 unsigned flags, coords;
2162
2163 tex_info(tex, &flags, &coords);
2164
2165 /* Actually we want the number of dimensions, not coordinates. This
2166 * distinction only matters for cubes.
2167 */
2168 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2169 coords = 2;
2170
2171 dst = ir3_get_dst(ctx, &tex->dest, 4);
2172
2173 compile_assert(ctx, tex->num_srcs == 1);
2174 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
2175
2176 lod = ir3_get_src(ctx, &tex->src[0].src)[0];
2177
2178 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
2179 tex->texture_index, tex->texture_index, lod, NULL);
2180
2181 ir3_split_dest(b, dst, sam, 0, 4);
2182
2183 /* Array size actually ends up in .w rather than .z. This doesn't
2184 * matter for miplevel 0, but for higher mips the value in z is
2185 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2186 * returned, which means that we have to add 1 to it for arrays.
2187 */
2188 if (tex->is_array) {
2189 if (ctx->compiler->levels_add_one) {
2190 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2191 } else {
2192 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2193 }
2194 }
2195
2196 put_dst(ctx, &tex->dest);
2197 }
2198
2199 static void
2200 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2201 {
2202 switch (jump->type) {
2203 case nir_jump_break:
2204 case nir_jump_continue:
2205 case nir_jump_return:
2206 /* I *think* we can simply just ignore this, and use the
2207 * successor block link to figure out where we need to
2208 * jump to for break/continue
2209 */
2210 break;
2211 default:
2212 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2213 break;
2214 }
2215 }
2216
2217 static void
2218 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2219 {
2220 switch (instr->type) {
2221 case nir_instr_type_alu:
2222 emit_alu(ctx, nir_instr_as_alu(instr));
2223 break;
2224 case nir_instr_type_deref:
2225 /* ignored, handled as part of the intrinsic they are src to */
2226 break;
2227 case nir_instr_type_intrinsic:
2228 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2229 break;
2230 case nir_instr_type_load_const:
2231 emit_load_const(ctx, nir_instr_as_load_const(instr));
2232 break;
2233 case nir_instr_type_ssa_undef:
2234 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2235 break;
2236 case nir_instr_type_tex: {
2237 nir_tex_instr *tex = nir_instr_as_tex(instr);
2238 /* couple tex instructions get special-cased:
2239 */
2240 switch (tex->op) {
2241 case nir_texop_txs:
2242 emit_tex_txs(ctx, tex);
2243 break;
2244 case nir_texop_query_levels:
2245 emit_tex_query_levels(ctx, tex);
2246 break;
2247 default:
2248 emit_tex(ctx, tex);
2249 break;
2250 }
2251 break;
2252 }
2253 case nir_instr_type_jump:
2254 emit_jump(ctx, nir_instr_as_jump(instr));
2255 break;
2256 case nir_instr_type_phi:
2257 /* we have converted phi webs to regs in NIR by now */
2258 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2259 break;
2260 case nir_instr_type_call:
2261 case nir_instr_type_parallel_copy:
2262 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2263 break;
2264 }
2265 }
2266
2267 static struct ir3_block *
2268 get_block(struct ir3_context *ctx, const nir_block *nblock)
2269 {
2270 struct ir3_block *block;
2271 struct hash_entry *hentry;
2272 unsigned i;
2273
2274 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2275 if (hentry)
2276 return hentry->data;
2277
2278 block = ir3_block_create(ctx->ir);
2279 block->nblock = nblock;
2280 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2281
2282 block->predecessors_count = nblock->predecessors->entries;
2283 block->predecessors = ralloc_array_size(block,
2284 sizeof(block->predecessors[0]), block->predecessors_count);
2285 i = 0;
2286 set_foreach(nblock->predecessors, sentry) {
2287 block->predecessors[i++] = get_block(ctx, sentry->key);
2288 }
2289
2290 return block;
2291 }
2292
2293 static void
2294 emit_block(struct ir3_context *ctx, nir_block *nblock)
2295 {
2296 struct ir3_block *block = get_block(ctx, nblock);
2297
2298 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2299 if (nblock->successors[i]) {
2300 block->successors[i] =
2301 get_block(ctx, nblock->successors[i]);
2302 }
2303 }
2304
2305 ctx->block = block;
2306 list_addtail(&block->node, &ctx->ir->block_list);
2307
2308 /* re-emit addr register in each block if needed: */
2309 for (int i = 0; i < ARRAY_SIZE(ctx->addr_ht); i++) {
2310 _mesa_hash_table_destroy(ctx->addr_ht[i], NULL);
2311 ctx->addr_ht[i] = NULL;
2312 }
2313
2314 nir_foreach_instr(instr, nblock) {
2315 ctx->cur_instr = instr;
2316 emit_instr(ctx, instr);
2317 ctx->cur_instr = NULL;
2318 if (ctx->error)
2319 return;
2320 }
2321 }
2322
2323 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2324
2325 static void
2326 emit_if(struct ir3_context *ctx, nir_if *nif)
2327 {
2328 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2329
2330 ctx->block->condition =
2331 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
2332
2333 emit_cf_list(ctx, &nif->then_list);
2334 emit_cf_list(ctx, &nif->else_list);
2335 }
2336
2337 static void
2338 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2339 {
2340 emit_cf_list(ctx, &nloop->body);
2341 }
2342
2343 static void
2344 stack_push(struct ir3_context *ctx)
2345 {
2346 ctx->stack++;
2347 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2348 }
2349
2350 static void
2351 stack_pop(struct ir3_context *ctx)
2352 {
2353 compile_assert(ctx, ctx->stack > 0);
2354 ctx->stack--;
2355 }
2356
2357 static void
2358 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2359 {
2360 foreach_list_typed(nir_cf_node, node, node, list) {
2361 switch (node->type) {
2362 case nir_cf_node_block:
2363 emit_block(ctx, nir_cf_node_as_block(node));
2364 break;
2365 case nir_cf_node_if:
2366 stack_push(ctx);
2367 emit_if(ctx, nir_cf_node_as_if(node));
2368 stack_pop(ctx);
2369 break;
2370 case nir_cf_node_loop:
2371 stack_push(ctx);
2372 emit_loop(ctx, nir_cf_node_as_loop(node));
2373 stack_pop(ctx);
2374 break;
2375 case nir_cf_node_function:
2376 ir3_context_error(ctx, "TODO\n");
2377 break;
2378 }
2379 }
2380 }
2381
2382 /* emit stream-out code. At this point, the current block is the original
2383 * (nir) end block, and nir ensures that all flow control paths terminate
2384 * into the end block. We re-purpose the original end block to generate
2385 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2386 * block holding stream-out write instructions, followed by the new end
2387 * block:
2388 *
2389 * blockOrigEnd {
2390 * p0.x = (vtxcnt < maxvtxcnt)
2391 * // succs: blockStreamOut, blockNewEnd
2392 * }
2393 * blockStreamOut {
2394 * ... stream-out instructions ...
2395 * // succs: blockNewEnd
2396 * }
2397 * blockNewEnd {
2398 * }
2399 */
2400 static void
2401 emit_stream_out(struct ir3_context *ctx)
2402 {
2403 struct ir3_shader_variant *v = ctx->so;
2404 struct ir3 *ir = ctx->ir;
2405 struct ir3_stream_output_info *strmout =
2406 &ctx->so->shader->stream_output;
2407 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2408 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2409 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2410
2411 /* create vtxcnt input in input block at top of shader,
2412 * so that it is seen as live over the entire duration
2413 * of the shader:
2414 */
2415 vtxcnt = create_input(ctx, 0);
2416 add_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, vtxcnt);
2417
2418 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2419
2420 /* at this point, we are at the original 'end' block,
2421 * re-purpose this block to stream-out condition, then
2422 * append stream-out block and new-end block
2423 */
2424 orig_end_block = ctx->block;
2425
2426 // TODO these blocks need to update predecessors..
2427 // maybe w/ store_global intrinsic, we could do this
2428 // stuff in nir->nir pass
2429
2430 stream_out_block = ir3_block_create(ir);
2431 list_addtail(&stream_out_block->node, &ir->block_list);
2432
2433 new_end_block = ir3_block_create(ir);
2434 list_addtail(&new_end_block->node, &ir->block_list);
2435
2436 orig_end_block->successors[0] = stream_out_block;
2437 orig_end_block->successors[1] = new_end_block;
2438 stream_out_block->successors[0] = new_end_block;
2439
2440 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2441 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2442 cond->regs[0]->num = regid(REG_P0, 0);
2443 cond->cat2.condition = IR3_COND_LT;
2444
2445 /* condition goes on previous block to the conditional,
2446 * since it is used to pick which of the two successor
2447 * paths to take:
2448 */
2449 orig_end_block->condition = cond;
2450
2451 /* switch to stream_out_block to generate the stream-out
2452 * instructions:
2453 */
2454 ctx->block = stream_out_block;
2455
2456 /* Calculate base addresses based on vtxcnt. Instructions
2457 * generated for bases not used in following loop will be
2458 * stripped out in the backend.
2459 */
2460 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2461 unsigned stride = strmout->stride[i];
2462 struct ir3_instruction *base, *off;
2463
2464 base = create_uniform(ctx->block, regid(v->constbase.tfbo, i));
2465
2466 /* 24-bit should be enough: */
2467 off = ir3_MUL_U(ctx->block, vtxcnt, 0,
2468 create_immed(ctx->block, stride * 4), 0);
2469
2470 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2471 }
2472
2473 /* Generate the per-output store instructions: */
2474 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2475 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2476 unsigned c = j + strmout->output[i].start_component;
2477 struct ir3_instruction *base, *out, *stg;
2478
2479 base = bases[strmout->output[i].output_buffer];
2480 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2481
2482 stg = ir3_STG(ctx->block, base, 0, out, 0,
2483 create_immed(ctx->block, 1), 0);
2484 stg->cat6.type = TYPE_U32;
2485 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2486
2487 array_insert(ctx->block, ctx->block->keeps, stg);
2488 }
2489 }
2490
2491 /* and finally switch to the new_end_block: */
2492 ctx->block = new_end_block;
2493 }
2494
2495 static void
2496 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2497 {
2498 nir_metadata_require(impl, nir_metadata_block_index);
2499
2500 compile_assert(ctx, ctx->stack == 0);
2501
2502 emit_cf_list(ctx, &impl->body);
2503 emit_block(ctx, impl->end_block);
2504
2505 compile_assert(ctx, ctx->stack == 0);
2506
2507 /* at this point, we should have a single empty block,
2508 * into which we emit the 'end' instruction.
2509 */
2510 compile_assert(ctx, list_empty(&ctx->block->instr_list));
2511
2512 /* If stream-out (aka transform-feedback) enabled, emit the
2513 * stream-out instructions, followed by a new empty block (into
2514 * which the 'end' instruction lands).
2515 *
2516 * NOTE: it is done in this order, rather than inserting before
2517 * we emit end_block, because NIR guarantees that all blocks
2518 * flow into end_block, and that end_block has no successors.
2519 * So by re-purposing end_block as the first block of stream-
2520 * out, we guarantee that all exit paths flow into the stream-
2521 * out instructions.
2522 */
2523 if ((ctx->compiler->gpu_id < 500) &&
2524 (ctx->so->shader->stream_output.num_outputs > 0) &&
2525 !ctx->so->binning_pass) {
2526 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2527 emit_stream_out(ctx);
2528 }
2529
2530 ir3_END(ctx->block);
2531 }
2532
2533 static struct ir3_instruction *
2534 create_frag_coord(struct ir3_context *ctx, unsigned comp)
2535 {
2536 struct ir3_block *block = ctx->block;
2537 struct ir3_instruction *instr;
2538
2539 if (!ctx->frag_coord) {
2540 ctx->frag_coord = create_input_compmask(ctx, 0, 0xf);
2541 /* defer add_sysval_input() until after all inputs created */
2542 }
2543
2544 ir3_split_dest(block, &instr, ctx->frag_coord, comp, 1);
2545
2546 switch (comp) {
2547 case 0: /* .x */
2548 case 1: /* .y */
2549 /* for frag_coord, we get unsigned values.. we need
2550 * to subtract (integer) 8 and divide by 16 (right-
2551 * shift by 4) then convert to float:
2552 *
2553 * sub.s tmp, src, 8
2554 * shr.b tmp, tmp, 4
2555 * mov.u32f32 dst, tmp
2556 *
2557 */
2558 instr = ir3_SUB_S(block, instr, 0,
2559 create_immed(block, 8), 0);
2560 instr = ir3_SHR_B(block, instr, 0,
2561 create_immed(block, 4), 0);
2562 instr = ir3_COV(block, instr, TYPE_U32, TYPE_F32);
2563
2564 return instr;
2565 case 2: /* .z */
2566 case 3: /* .w */
2567 default:
2568 /* seems that we can use these as-is: */
2569 return instr;
2570 }
2571 }
2572
2573 static void
2574 setup_input(struct ir3_context *ctx, nir_variable *in)
2575 {
2576 struct ir3_shader_variant *so = ctx->so;
2577 unsigned ncomp = glsl_get_components(in->type);
2578 unsigned n = in->data.driver_location;
2579 unsigned slot = in->data.location;
2580
2581 /* let's pretend things other than vec4 don't exist: */
2582 ncomp = MAX2(ncomp, 4);
2583
2584 /* skip unread inputs, we could end up with (for example), unsplit
2585 * matrix/etc inputs in the case they are not read, so just silently
2586 * skip these.
2587 */
2588 if (ncomp > 4)
2589 return;
2590
2591 compile_assert(ctx, ncomp == 4);
2592
2593 so->inputs[n].slot = slot;
2594 so->inputs[n].compmask = (1 << ncomp) - 1;
2595 so->inputs_count = MAX2(so->inputs_count, n + 1);
2596 so->inputs[n].interpolate = in->data.interpolation;
2597
2598 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2599 for (int i = 0; i < ncomp; i++) {
2600 struct ir3_instruction *instr = NULL;
2601 unsigned idx = (n * 4) + i;
2602
2603 if (slot == VARYING_SLOT_POS) {
2604 so->inputs[n].bary = false;
2605 so->frag_coord = true;
2606 instr = create_frag_coord(ctx, i);
2607 } else if (slot == VARYING_SLOT_PNTC) {
2608 /* see for example st_nir_fixup_varying_slots().. this is
2609 * maybe a bit mesa/st specific. But we need things to line
2610 * up for this in fdN_program:
2611 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2612 * if (emit->sprite_coord_enable & texmask) {
2613 * ...
2614 * }
2615 */
2616 so->inputs[n].slot = VARYING_SLOT_VAR8;
2617 so->inputs[n].bary = true;
2618 instr = create_frag_input(ctx, false);
2619 } else {
2620 bool use_ldlv = false;
2621
2622 /* detect the special case for front/back colors where
2623 * we need to do flat vs smooth shading depending on
2624 * rast state:
2625 */
2626 if (in->data.interpolation == INTERP_MODE_NONE) {
2627 switch (slot) {
2628 case VARYING_SLOT_COL0:
2629 case VARYING_SLOT_COL1:
2630 case VARYING_SLOT_BFC0:
2631 case VARYING_SLOT_BFC1:
2632 so->inputs[n].rasterflat = true;
2633 break;
2634 default:
2635 break;
2636 }
2637 }
2638
2639 if (ctx->compiler->flat_bypass) {
2640 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2641 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2642 use_ldlv = true;
2643 }
2644
2645 so->inputs[n].bary = true;
2646
2647 instr = create_frag_input(ctx, use_ldlv);
2648 }
2649
2650 compile_assert(ctx, idx < ctx->ir->ninputs);
2651
2652 ctx->ir->inputs[idx] = instr;
2653 }
2654 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2655 for (int i = 0; i < ncomp; i++) {
2656 unsigned idx = (n * 4) + i;
2657 compile_assert(ctx, idx < ctx->ir->ninputs);
2658 ctx->ir->inputs[idx] = create_input(ctx, idx);
2659 }
2660 } else {
2661 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2662 }
2663
2664 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
2665 so->total_in += ncomp;
2666 }
2667 }
2668
2669 static void
2670 setup_output(struct ir3_context *ctx, nir_variable *out)
2671 {
2672 struct ir3_shader_variant *so = ctx->so;
2673 unsigned ncomp = glsl_get_components(out->type);
2674 unsigned n = out->data.driver_location;
2675 unsigned slot = out->data.location;
2676 unsigned comp = 0;
2677
2678 /* let's pretend things other than vec4 don't exist: */
2679 ncomp = MAX2(ncomp, 4);
2680 compile_assert(ctx, ncomp == 4);
2681
2682 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2683 switch (slot) {
2684 case FRAG_RESULT_DEPTH:
2685 comp = 2; /* tgsi will write to .z component */
2686 so->writes_pos = true;
2687 break;
2688 case FRAG_RESULT_COLOR:
2689 so->color0_mrt = 1;
2690 break;
2691 default:
2692 if (slot >= FRAG_RESULT_DATA0)
2693 break;
2694 ir3_context_error(ctx, "unknown FS output name: %s\n",
2695 gl_frag_result_name(slot));
2696 }
2697 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2698 switch (slot) {
2699 case VARYING_SLOT_POS:
2700 so->writes_pos = true;
2701 break;
2702 case VARYING_SLOT_PSIZ:
2703 so->writes_psize = true;
2704 break;
2705 case VARYING_SLOT_COL0:
2706 case VARYING_SLOT_COL1:
2707 case VARYING_SLOT_BFC0:
2708 case VARYING_SLOT_BFC1:
2709 case VARYING_SLOT_FOGC:
2710 case VARYING_SLOT_CLIP_DIST0:
2711 case VARYING_SLOT_CLIP_DIST1:
2712 case VARYING_SLOT_CLIP_VERTEX:
2713 break;
2714 default:
2715 if (slot >= VARYING_SLOT_VAR0)
2716 break;
2717 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
2718 break;
2719 ir3_context_error(ctx, "unknown VS output name: %s\n",
2720 gl_varying_slot_name(slot));
2721 }
2722 } else {
2723 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2724 }
2725
2726 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
2727
2728 so->outputs[n].slot = slot;
2729 so->outputs[n].regid = regid(n, comp);
2730 so->outputs_count = MAX2(so->outputs_count, n + 1);
2731
2732 for (int i = 0; i < ncomp; i++) {
2733 unsigned idx = (n * 4) + i;
2734 compile_assert(ctx, idx < ctx->ir->noutputs);
2735 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2736 }
2737 }
2738
2739 static int
2740 max_drvloc(struct exec_list *vars)
2741 {
2742 int drvloc = -1;
2743 nir_foreach_variable(var, vars) {
2744 drvloc = MAX2(drvloc, (int)var->data.driver_location);
2745 }
2746 return drvloc;
2747 }
2748
2749 static const unsigned max_sysvals[] = {
2750 [MESA_SHADER_FRAGMENT] = 24, // TODO
2751 [MESA_SHADER_VERTEX] = 16,
2752 [MESA_SHADER_COMPUTE] = 16, // TODO how many do we actually need?
2753 };
2754
2755 static void
2756 emit_instructions(struct ir3_context *ctx)
2757 {
2758 unsigned ninputs, noutputs;
2759 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
2760
2761 ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4;
2762 noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4;
2763
2764 /* we need to leave room for sysvals:
2765 */
2766 ninputs += max_sysvals[ctx->so->type];
2767
2768 ctx->ir = ir3_create(ctx->compiler, ninputs, noutputs);
2769
2770 /* Create inputs in first block: */
2771 ctx->block = get_block(ctx, nir_start_block(fxn));
2772 ctx->in_block = ctx->block;
2773 list_addtail(&ctx->block->node, &ctx->ir->block_list);
2774
2775 ninputs -= max_sysvals[ctx->so->type];
2776
2777 /* for fragment shader, the vcoord input register is used as the
2778 * base for bary.f varying fetch instrs:
2779 */
2780 struct ir3_instruction *vcoord = NULL;
2781 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2782 struct ir3_instruction *xy[2];
2783
2784 vcoord = create_input_compmask(ctx, 0, 0x3);
2785 ir3_split_dest(ctx->block, xy, vcoord, 0, 2);
2786
2787 ctx->frag_vcoord = ir3_create_collect(ctx, xy, 2);
2788 }
2789
2790 /* Setup inputs: */
2791 nir_foreach_variable(var, &ctx->s->inputs) {
2792 setup_input(ctx, var);
2793 }
2794
2795 /* Defer add_sysval_input() stuff until after setup_inputs(),
2796 * because sysvals need to be appended after varyings:
2797 */
2798 if (vcoord) {
2799 add_sysval_input_compmask(ctx, SYSTEM_VALUE_VARYING_COORD,
2800 0x3, vcoord);
2801 }
2802
2803 if (ctx->frag_coord) {
2804 add_sysval_input_compmask(ctx, SYSTEM_VALUE_FRAG_COORD,
2805 0xf, ctx->frag_coord);
2806 }
2807
2808 /* Setup outputs: */
2809 nir_foreach_variable(var, &ctx->s->outputs) {
2810 setup_output(ctx, var);
2811 }
2812
2813 /* Setup registers (which should only be arrays): */
2814 nir_foreach_register(reg, &ctx->s->registers) {
2815 ir3_declare_array(ctx, reg);
2816 }
2817
2818 /* NOTE: need to do something more clever when we support >1 fxn */
2819 nir_foreach_register(reg, &fxn->registers) {
2820 ir3_declare_array(ctx, reg);
2821 }
2822 /* And emit the body: */
2823 ctx->impl = fxn;
2824 emit_function(ctx, fxn);
2825 }
2826
2827 /* from NIR perspective, we actually have varying inputs. But the varying
2828 * inputs, from an IR standpoint, are just bary.f/ldlv instructions. The
2829 * only actual inputs are the sysvals.
2830 */
2831 static void
2832 fixup_frag_inputs(struct ir3_context *ctx)
2833 {
2834 struct ir3_shader_variant *so = ctx->so;
2835 struct ir3 *ir = ctx->ir;
2836 unsigned i = 0;
2837
2838 /* sysvals should appear at the end of the inputs, drop everything else: */
2839 while ((i < so->inputs_count) && !so->inputs[i].sysval)
2840 i++;
2841
2842 /* at IR level, inputs are always blocks of 4 scalars: */
2843 i *= 4;
2844
2845 ir->inputs = &ir->inputs[i];
2846 ir->ninputs -= i;
2847 }
2848
2849 /* Fixup tex sampler state for astc/srgb workaround instructions. We
2850 * need to assign the tex state indexes for these after we know the
2851 * max tex index.
2852 */
2853 static void
2854 fixup_astc_srgb(struct ir3_context *ctx)
2855 {
2856 struct ir3_shader_variant *so = ctx->so;
2857 /* indexed by original tex idx, value is newly assigned alpha sampler
2858 * state tex idx. Zero is invalid since there is at least one sampler
2859 * if we get here.
2860 */
2861 unsigned alt_tex_state[16] = {0};
2862 unsigned tex_idx = ctx->max_texture_index + 1;
2863 unsigned idx = 0;
2864
2865 so->astc_srgb.base = tex_idx;
2866
2867 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
2868 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
2869
2870 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
2871
2872 if (alt_tex_state[sam->cat5.tex] == 0) {
2873 /* assign new alternate/alpha tex state slot: */
2874 alt_tex_state[sam->cat5.tex] = tex_idx++;
2875 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
2876 so->astc_srgb.count++;
2877 }
2878
2879 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
2880 }
2881 }
2882
2883 static void
2884 fixup_binning_pass(struct ir3_context *ctx)
2885 {
2886 struct ir3_shader_variant *so = ctx->so;
2887 struct ir3 *ir = ctx->ir;
2888 unsigned i, j;
2889
2890 for (i = 0, j = 0; i < so->outputs_count; i++) {
2891 unsigned slot = so->outputs[i].slot;
2892
2893 /* throw away everything but first position/psize */
2894 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
2895 if (i != j) {
2896 so->outputs[j] = so->outputs[i];
2897 ir->outputs[(j*4)+0] = ir->outputs[(i*4)+0];
2898 ir->outputs[(j*4)+1] = ir->outputs[(i*4)+1];
2899 ir->outputs[(j*4)+2] = ir->outputs[(i*4)+2];
2900 ir->outputs[(j*4)+3] = ir->outputs[(i*4)+3];
2901 }
2902 j++;
2903 }
2904 }
2905 so->outputs_count = j;
2906 ir->noutputs = j * 4;
2907 }
2908
2909 int
2910 ir3_compile_shader_nir(struct ir3_compiler *compiler,
2911 struct ir3_shader_variant *so)
2912 {
2913 struct ir3_context *ctx;
2914 struct ir3 *ir;
2915 struct ir3_instruction **inputs;
2916 unsigned i, actual_in, inloc;
2917 int ret = 0, max_bary;
2918
2919 assert(!so->ir);
2920
2921 ctx = ir3_context_init(compiler, so);
2922 if (!ctx) {
2923 DBG("INIT failed!");
2924 ret = -1;
2925 goto out;
2926 }
2927
2928 emit_instructions(ctx);
2929
2930 if (ctx->error) {
2931 DBG("EMIT failed!");
2932 ret = -1;
2933 goto out;
2934 }
2935
2936 ir = so->ir = ctx->ir;
2937
2938 /* keep track of the inputs from TGSI perspective.. */
2939 inputs = ir->inputs;
2940
2941 /* but fixup actual inputs for frag shader: */
2942 if (so->type == MESA_SHADER_FRAGMENT)
2943 fixup_frag_inputs(ctx);
2944
2945 /* at this point, for binning pass, throw away unneeded outputs: */
2946 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
2947 fixup_binning_pass(ctx);
2948
2949 /* if we want half-precision outputs, mark the output registers
2950 * as half:
2951 */
2952 if (so->key.half_precision) {
2953 for (i = 0; i < ir->noutputs; i++) {
2954 struct ir3_instruction *out = ir->outputs[i];
2955
2956 if (!out)
2957 continue;
2958
2959 /* if frag shader writes z, that needs to be full precision: */
2960 if (so->outputs[i/4].slot == FRAG_RESULT_DEPTH)
2961 continue;
2962
2963 out->regs[0]->flags |= IR3_REG_HALF;
2964 /* output could be a fanout (ie. texture fetch output)
2965 * in which case we need to propagate the half-reg flag
2966 * up to the definer so that RA sees it:
2967 */
2968 if (out->opc == OPC_META_FO) {
2969 out = out->regs[1]->instr;
2970 out->regs[0]->flags |= IR3_REG_HALF;
2971 }
2972
2973 if (out->opc == OPC_MOV) {
2974 out->cat1.dst_type = half_type(out->cat1.dst_type);
2975 }
2976 }
2977 }
2978
2979 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
2980 printf("BEFORE CP:\n");
2981 ir3_print(ir);
2982 }
2983
2984 ir3_cp(ir, so);
2985
2986 /* at this point, for binning pass, throw away unneeded outputs:
2987 * Note that for a6xx and later, we do this after ir3_cp to ensure
2988 * that the uniform/constant layout for BS and VS matches, so that
2989 * we can re-use same VS_CONST state group.
2990 */
2991 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
2992 fixup_binning_pass(ctx);
2993
2994 /* Insert mov if there's same instruction for each output.
2995 * eg. dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_expression.vertex.sampler2dshadow
2996 */
2997 for (int i = ir->noutputs - 1; i >= 0; i--) {
2998 if (!ir->outputs[i])
2999 continue;
3000 for (unsigned j = 0; j < i; j++) {
3001 if (ir->outputs[i] == ir->outputs[j]) {
3002 ir->outputs[i] =
3003 ir3_MOV(ir->outputs[i]->block, ir->outputs[i], TYPE_F32);
3004 }
3005 }
3006 }
3007
3008 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3009 printf("BEFORE GROUPING:\n");
3010 ir3_print(ir);
3011 }
3012
3013 ir3_sched_add_deps(ir);
3014
3015 /* Group left/right neighbors, inserting mov's where needed to
3016 * solve conflicts:
3017 */
3018 ir3_group(ir);
3019
3020 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3021 printf("AFTER GROUPING:\n");
3022 ir3_print(ir);
3023 }
3024
3025 ir3_depth(ir);
3026
3027 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3028 printf("AFTER DEPTH:\n");
3029 ir3_print(ir);
3030 }
3031
3032 ret = ir3_sched(ir);
3033 if (ret) {
3034 DBG("SCHED failed!");
3035 goto out;
3036 }
3037
3038 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3039 printf("AFTER SCHED:\n");
3040 ir3_print(ir);
3041 }
3042
3043 ret = ir3_ra(ir, so->type, so->frag_coord, so->frag_face);
3044 if (ret) {
3045 DBG("RA failed!");
3046 goto out;
3047 }
3048
3049 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3050 printf("AFTER RA:\n");
3051 ir3_print(ir);
3052 }
3053
3054 /* fixup input/outputs: */
3055 for (i = 0; i < so->outputs_count; i++) {
3056 so->outputs[i].regid = ir->outputs[i*4]->regs[0]->num;
3057 }
3058
3059 /* Note that some or all channels of an input may be unused: */
3060 actual_in = 0;
3061 inloc = 0;
3062 for (i = 0; i < so->inputs_count; i++) {
3063 unsigned j, reg = regid(63,0), compmask = 0, maxcomp = 0;
3064 so->inputs[i].ncomp = 0;
3065 so->inputs[i].inloc = inloc;
3066 for (j = 0; j < 4; j++) {
3067 struct ir3_instruction *in = inputs[(i*4) + j];
3068 if (in && !(in->flags & IR3_INSTR_UNUSED)) {
3069 compmask |= (1 << j);
3070 reg = in->regs[0]->num - j;
3071 actual_in++;
3072 so->inputs[i].ncomp++;
3073 if ((so->type == MESA_SHADER_FRAGMENT) && so->inputs[i].bary) {
3074 /* assign inloc: */
3075 assert(in->regs[1]->flags & IR3_REG_IMMED);
3076 in->regs[1]->iim_val = inloc + j;
3077 maxcomp = j + 1;
3078 }
3079 }
3080 }
3081 if ((so->type == MESA_SHADER_FRAGMENT) && compmask && so->inputs[i].bary) {
3082 so->varying_in++;
3083 so->inputs[i].compmask = (1 << maxcomp) - 1;
3084 inloc += maxcomp;
3085 } else if (!so->inputs[i].sysval) {
3086 so->inputs[i].compmask = compmask;
3087 }
3088 so->inputs[i].regid = reg;
3089 }
3090
3091 if (ctx->astc_srgb)
3092 fixup_astc_srgb(ctx);
3093
3094 /* We need to do legalize after (for frag shader's) the "bary.f"
3095 * offsets (inloc) have been assigned.
3096 */
3097 ir3_legalize(ir, &so->num_samp, &so->has_ssbo, &max_bary);
3098
3099 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3100 printf("AFTER LEGALIZE:\n");
3101 ir3_print(ir);
3102 }
3103
3104 so->branchstack = ctx->max_stack;
3105
3106 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3107 if (so->type == MESA_SHADER_VERTEX)
3108 so->total_in = actual_in;
3109 else
3110 so->total_in = max_bary + 1;
3111
3112 out:
3113 if (ret) {
3114 if (so->ir)
3115 ir3_destroy(so->ir);
3116 so->ir = NULL;
3117 }
3118 ir3_context_free(ctx);
3119
3120 return ret;
3121 }