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freedreno/ir3: remove indirect input load
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42 void
43 ir3_handle_bindless_cat6(struct ir3_instruction *instr, nir_src rsrc)
44 {
45 nir_intrinsic_instr *intrin = ir3_bindless_resource(rsrc);
46 if (!intrin)
47 return;
48
49 instr->flags |= IR3_INSTR_B;
50 instr->cat6.base = nir_intrinsic_desc_set(intrin);
51 }
52
53 static struct ir3_instruction *
54 create_input(struct ir3_context *ctx, unsigned compmask)
55 {
56 struct ir3_instruction *in;
57
58 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
59 in->input.sysval = ~0;
60 __ssa_dst(in)->wrmask = compmask;
61
62 array_insert(ctx->ir, ctx->ir->inputs, in);
63
64 return in;
65 }
66
67 static struct ir3_instruction *
68 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
69 {
70 struct ir3_block *block = ctx->block;
71 struct ir3_instruction *instr;
72 /* packed inloc is fixed up later: */
73 struct ir3_instruction *inloc = create_immed(block, n);
74
75 if (use_ldlv) {
76 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
77 instr->cat6.type = TYPE_U32;
78 instr->cat6.iim_val = 1;
79 } else {
80 instr = ir3_BARY_F(block, inloc, 0, ctx->ij[IJ_PERSP_PIXEL], 0);
81 instr->regs[2]->wrmask = 0x3;
82 }
83
84 return instr;
85 }
86
87 static struct ir3_instruction *
88 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
89 {
90 /* first four vec4 sysval's reserved for UBOs: */
91 /* NOTE: dp is in scalar, but there can be >4 dp components: */
92 struct ir3_const_state *const_state = ir3_const_state(ctx->so);
93 unsigned n = const_state->offsets.driver_param;
94 unsigned r = regid(n + dp / 4, dp % 4);
95 return create_uniform(ctx->block, r);
96 }
97
98 /*
99 * Adreno's comparisons produce a 1 for true and 0 for false, in either 16 or
100 * 32-bit registers. We use NIR's 1-bit integers to represent bools, and
101 * trust that we will only see and/or/xor on those 1-bit values, so we can
102 * safely store NIR i1s in a 32-bit reg while always containing either a 1 or
103 * 0.
104 */
105
106 /*
107 * alu/sfu instructions:
108 */
109
110 static struct ir3_instruction *
111 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
112 unsigned src_bitsize, nir_op op)
113 {
114 type_t src_type, dst_type;
115
116 switch (op) {
117 case nir_op_f2f32:
118 case nir_op_f2f16_rtne:
119 case nir_op_f2f16_rtz:
120 case nir_op_f2f16:
121 case nir_op_f2i32:
122 case nir_op_f2i16:
123 case nir_op_f2i8:
124 case nir_op_f2u32:
125 case nir_op_f2u16:
126 case nir_op_f2u8:
127 switch (src_bitsize) {
128 case 32:
129 src_type = TYPE_F32;
130 break;
131 case 16:
132 src_type = TYPE_F16;
133 break;
134 default:
135 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
136 }
137 break;
138
139 case nir_op_i2f32:
140 case nir_op_i2f16:
141 case nir_op_i2i32:
142 case nir_op_i2i16:
143 case nir_op_i2i8:
144 switch (src_bitsize) {
145 case 32:
146 src_type = TYPE_S32;
147 break;
148 case 16:
149 src_type = TYPE_S16;
150 break;
151 case 8:
152 src_type = TYPE_S8;
153 break;
154 default:
155 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
156 }
157 break;
158
159 case nir_op_u2f32:
160 case nir_op_u2f16:
161 case nir_op_u2u32:
162 case nir_op_u2u16:
163 case nir_op_u2u8:
164 switch (src_bitsize) {
165 case 32:
166 src_type = TYPE_U32;
167 break;
168 case 16:
169 src_type = TYPE_U16;
170 break;
171 case 8:
172 src_type = TYPE_U8;
173 break;
174 default:
175 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
176 }
177 break;
178
179 case nir_op_b2f16:
180 case nir_op_b2f32:
181 case nir_op_b2i8:
182 case nir_op_b2i16:
183 case nir_op_b2i32:
184 src_type = TYPE_U32;
185 break;
186
187 default:
188 ir3_context_error(ctx, "invalid conversion op: %u", op);
189 }
190
191 switch (op) {
192 case nir_op_f2f32:
193 case nir_op_i2f32:
194 case nir_op_u2f32:
195 case nir_op_b2f32:
196 dst_type = TYPE_F32;
197 break;
198
199 case nir_op_f2f16_rtne:
200 case nir_op_f2f16_rtz:
201 case nir_op_f2f16:
202 case nir_op_i2f16:
203 case nir_op_u2f16:
204 case nir_op_b2f16:
205 dst_type = TYPE_F16;
206 break;
207
208 case nir_op_f2i32:
209 case nir_op_i2i32:
210 case nir_op_b2i32:
211 dst_type = TYPE_S32;
212 break;
213
214 case nir_op_f2i16:
215 case nir_op_i2i16:
216 case nir_op_b2i16:
217 dst_type = TYPE_S16;
218 break;
219
220 case nir_op_f2i8:
221 case nir_op_i2i8:
222 case nir_op_b2i8:
223 dst_type = TYPE_S8;
224 break;
225
226 case nir_op_f2u32:
227 case nir_op_u2u32:
228 dst_type = TYPE_U32;
229 break;
230
231 case nir_op_f2u16:
232 case nir_op_u2u16:
233 dst_type = TYPE_U16;
234 break;
235
236 case nir_op_f2u8:
237 case nir_op_u2u8:
238 dst_type = TYPE_U8;
239 break;
240
241 default:
242 ir3_context_error(ctx, "invalid conversion op: %u", op);
243 }
244
245 if (src_type == dst_type)
246 return src;
247
248 struct ir3_instruction *cov =
249 ir3_COV(ctx->block, src, src_type, dst_type);
250
251 if (op == nir_op_f2f16_rtne)
252 cov->regs[0]->flags |= IR3_REG_EVEN;
253
254 return cov;
255 }
256
257 static void
258 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
259 {
260 const nir_op_info *info = &nir_op_infos[alu->op];
261 struct ir3_instruction **dst, *src[info->num_inputs];
262 unsigned bs[info->num_inputs]; /* bit size */
263 struct ir3_block *b = ctx->block;
264 unsigned dst_sz, wrmask;
265 type_t dst_type = nir_dest_bit_size(alu->dest.dest) == 16 ?
266 TYPE_U16 : TYPE_U32;
267
268 if (alu->dest.dest.is_ssa) {
269 dst_sz = alu->dest.dest.ssa.num_components;
270 wrmask = (1 << dst_sz) - 1;
271 } else {
272 dst_sz = alu->dest.dest.reg.reg->num_components;
273 wrmask = alu->dest.write_mask;
274 }
275
276 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
277
278 /* Vectors are special in that they have non-scalarized writemasks,
279 * and just take the first swizzle channel for each argument in
280 * order into each writemask channel.
281 */
282 if ((alu->op == nir_op_vec2) ||
283 (alu->op == nir_op_vec3) ||
284 (alu->op == nir_op_vec4)) {
285
286 for (int i = 0; i < info->num_inputs; i++) {
287 nir_alu_src *asrc = &alu->src[i];
288
289 compile_assert(ctx, !asrc->abs);
290 compile_assert(ctx, !asrc->negate);
291
292 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
293 if (!src[i])
294 src[i] = create_immed_typed(ctx->block, 0, dst_type);
295 dst[i] = ir3_MOV(b, src[i], dst_type);
296 }
297
298 ir3_put_dst(ctx, &alu->dest.dest);
299 return;
300 }
301
302 /* We also get mov's with more than one component for mov's so
303 * handle those specially:
304 */
305 if (alu->op == nir_op_mov) {
306 nir_alu_src *asrc = &alu->src[0];
307 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
308
309 for (unsigned i = 0; i < dst_sz; i++) {
310 if (wrmask & (1 << i)) {
311 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
312 } else {
313 dst[i] = NULL;
314 }
315 }
316
317 ir3_put_dst(ctx, &alu->dest.dest);
318 return;
319 }
320
321 /* General case: We can just grab the one used channel per src. */
322 for (int i = 0; i < info->num_inputs; i++) {
323 unsigned chan = ffs(alu->dest.write_mask) - 1;
324 nir_alu_src *asrc = &alu->src[i];
325
326 compile_assert(ctx, !asrc->abs);
327 compile_assert(ctx, !asrc->negate);
328
329 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
330 bs[i] = nir_src_bit_size(asrc->src);
331
332 compile_assert(ctx, src[i]);
333 }
334
335 switch (alu->op) {
336 case nir_op_f2f32:
337 case nir_op_f2f16_rtne:
338 case nir_op_f2f16_rtz:
339 case nir_op_f2f16:
340 case nir_op_f2i32:
341 case nir_op_f2i16:
342 case nir_op_f2i8:
343 case nir_op_f2u32:
344 case nir_op_f2u16:
345 case nir_op_f2u8:
346 case nir_op_i2f32:
347 case nir_op_i2f16:
348 case nir_op_i2i32:
349 case nir_op_i2i16:
350 case nir_op_i2i8:
351 case nir_op_u2f32:
352 case nir_op_u2f16:
353 case nir_op_u2u32:
354 case nir_op_u2u16:
355 case nir_op_u2u8:
356 case nir_op_b2f16:
357 case nir_op_b2f32:
358 case nir_op_b2i8:
359 case nir_op_b2i16:
360 case nir_op_b2i32:
361 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
362 break;
363
364 case nir_op_fquantize2f16:
365 dst[0] = create_cov(ctx,
366 create_cov(ctx, src[0], 32, nir_op_f2f16),
367 16, nir_op_f2f32);
368 break;
369 case nir_op_f2b1:
370 dst[0] = ir3_CMPS_F(b,
371 src[0], 0,
372 create_immed_typed(b, 0, bs[0] == 16 ? TYPE_F16 : TYPE_F32), 0);
373 dst[0]->cat2.condition = IR3_COND_NE;
374 break;
375
376 case nir_op_i2b1:
377 /* i2b1 will appear when translating from nir_load_ubo or
378 * nir_intrinsic_load_ssbo, where any non-zero value is true.
379 */
380 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
381 dst[0]->cat2.condition = IR3_COND_NE;
382 break;
383
384 case nir_op_b2b1:
385 /* b2b1 will appear when translating from
386 *
387 * - nir_intrinsic_load_shared of a 32-bit 0/~0 value.
388 * - nir_intrinsic_load_constant of a 32-bit 0/~0 value
389 *
390 * A negate can turn those into a 1 or 0 for us.
391 */
392 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
393 break;
394
395 case nir_op_b2b32:
396 /* b2b32 will appear when converting our 1-bit bools to a store_shared
397 * argument.
398 *
399 * A negate can turn those into a ~0 for us.
400 */
401 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
402 break;
403
404 case nir_op_fneg:
405 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
406 break;
407 case nir_op_fabs:
408 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
409 break;
410 case nir_op_fmax:
411 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
412 break;
413 case nir_op_fmin:
414 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
415 break;
416 case nir_op_fsat:
417 /* if there is just a single use of the src, and it supports
418 * (sat) bit, we can just fold the (sat) flag back to the
419 * src instruction and create a mov. This is easier for cp
420 * to eliminate.
421 *
422 * NOTE: a3xx definitely seen not working with flat bary.f. Same test
423 * uses ldlv on a4xx+, so not definitive. Seems rare enough to apply
424 * everywhere.
425 *
426 * TODO probably opc_cat==4 is ok too
427 */
428 if (alu->src[0].src.is_ssa &&
429 src[0]->opc != OPC_BARY_F &&
430 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
431 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
432 src[0]->flags |= IR3_INSTR_SAT;
433 dst[0] = ir3_MOV(b, src[0], dst_type);
434 } else {
435 /* otherwise generate a max.f that saturates.. blob does
436 * similar (generating a cat2 mov using max.f)
437 */
438 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
439 dst[0]->flags |= IR3_INSTR_SAT;
440 }
441 break;
442 case nir_op_fmul:
443 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
444 break;
445 case nir_op_fadd:
446 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
447 break;
448 case nir_op_fsub:
449 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
450 break;
451 case nir_op_ffma:
452 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
453 break;
454 case nir_op_fddx:
455 case nir_op_fddx_coarse:
456 dst[0] = ir3_DSX(b, src[0], 0);
457 dst[0]->cat5.type = TYPE_F32;
458 break;
459 case nir_op_fddx_fine:
460 dst[0] = ir3_DSXPP_MACRO(b, src[0], 0);
461 dst[0]->cat5.type = TYPE_F32;
462 break;
463 case nir_op_fddy:
464 case nir_op_fddy_coarse:
465 dst[0] = ir3_DSY(b, src[0], 0);
466 dst[0]->cat5.type = TYPE_F32;
467 break;
468 break;
469 case nir_op_fddy_fine:
470 dst[0] = ir3_DSYPP_MACRO(b, src[0], 0);
471 dst[0]->cat5.type = TYPE_F32;
472 break;
473 case nir_op_flt:
474 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
475 dst[0]->cat2.condition = IR3_COND_LT;
476 break;
477 case nir_op_fge:
478 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
479 dst[0]->cat2.condition = IR3_COND_GE;
480 break;
481 case nir_op_feq:
482 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
483 dst[0]->cat2.condition = IR3_COND_EQ;
484 break;
485 case nir_op_fneu:
486 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
487 dst[0]->cat2.condition = IR3_COND_NE;
488 break;
489 case nir_op_fceil:
490 dst[0] = ir3_CEIL_F(b, src[0], 0);
491 break;
492 case nir_op_ffloor:
493 dst[0] = ir3_FLOOR_F(b, src[0], 0);
494 break;
495 case nir_op_ftrunc:
496 dst[0] = ir3_TRUNC_F(b, src[0], 0);
497 break;
498 case nir_op_fround_even:
499 dst[0] = ir3_RNDNE_F(b, src[0], 0);
500 break;
501 case nir_op_fsign:
502 dst[0] = ir3_SIGN_F(b, src[0], 0);
503 break;
504
505 case nir_op_fsin:
506 dst[0] = ir3_SIN(b, src[0], 0);
507 break;
508 case nir_op_fcos:
509 dst[0] = ir3_COS(b, src[0], 0);
510 break;
511 case nir_op_frsq:
512 dst[0] = ir3_RSQ(b, src[0], 0);
513 break;
514 case nir_op_frcp:
515 dst[0] = ir3_RCP(b, src[0], 0);
516 break;
517 case nir_op_flog2:
518 dst[0] = ir3_LOG2(b, src[0], 0);
519 break;
520 case nir_op_fexp2:
521 dst[0] = ir3_EXP2(b, src[0], 0);
522 break;
523 case nir_op_fsqrt:
524 dst[0] = ir3_SQRT(b, src[0], 0);
525 break;
526
527 case nir_op_iabs:
528 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
529 break;
530 case nir_op_iadd:
531 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
532 break;
533 case nir_op_iand:
534 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
535 break;
536 case nir_op_imax:
537 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
538 break;
539 case nir_op_umax:
540 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
541 break;
542 case nir_op_imin:
543 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
544 break;
545 case nir_op_umin:
546 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
547 break;
548 case nir_op_umul_low:
549 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
550 break;
551 case nir_op_imadsh_mix16:
552 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
553 break;
554 case nir_op_imad24_ir3:
555 dst[0] = ir3_MAD_S24(b, src[0], 0, src[1], 0, src[2], 0);
556 break;
557 case nir_op_imul24:
558 dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
559 break;
560 case nir_op_ineg:
561 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
562 break;
563 case nir_op_inot:
564 if (bs[0] == 1) {
565 dst[0] = ir3_SUB_U(b, create_immed(ctx->block, 1), 0, src[0], 0);
566 } else {
567 dst[0] = ir3_NOT_B(b, src[0], 0);
568 }
569 break;
570 case nir_op_ior:
571 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
572 break;
573 case nir_op_ishl:
574 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
575 break;
576 case nir_op_ishr:
577 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
578 break;
579 case nir_op_isub:
580 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
581 break;
582 case nir_op_ixor:
583 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
584 break;
585 case nir_op_ushr:
586 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
587 break;
588 case nir_op_ilt:
589 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
590 dst[0]->cat2.condition = IR3_COND_LT;
591 break;
592 case nir_op_ige:
593 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
594 dst[0]->cat2.condition = IR3_COND_GE;
595 break;
596 case nir_op_ieq:
597 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
598 dst[0]->cat2.condition = IR3_COND_EQ;
599 break;
600 case nir_op_ine:
601 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
602 dst[0]->cat2.condition = IR3_COND_NE;
603 break;
604 case nir_op_ult:
605 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
606 dst[0]->cat2.condition = IR3_COND_LT;
607 break;
608 case nir_op_uge:
609 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
610 dst[0]->cat2.condition = IR3_COND_GE;
611 break;
612
613 case nir_op_bcsel: {
614 struct ir3_instruction *cond = src[0];
615
616 /* If src[0] is a negation (likely as a result of an ir3_b2n(cond)),
617 * we can ignore that and use original cond, since the nonzero-ness of
618 * cond stays the same.
619 */
620 if (cond->opc == OPC_ABSNEG_S &&
621 cond->flags == 0 &&
622 (cond->regs[1]->flags & (IR3_REG_SNEG | IR3_REG_SABS)) == IR3_REG_SNEG) {
623 cond = cond->regs[1]->instr;
624 }
625
626 compile_assert(ctx, bs[1] == bs[2]);
627 /* The condition's size has to match the other two arguments' size, so
628 * convert down if necessary.
629 */
630 if (bs[1] == 16) {
631 struct hash_entry *prev_entry =
632 _mesa_hash_table_search(ctx->sel_cond_conversions, src[0]);
633 if (prev_entry) {
634 cond = prev_entry->data;
635 } else {
636 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
637 _mesa_hash_table_insert(ctx->sel_cond_conversions, src[0], cond);
638 }
639 }
640
641 if (bs[1] != 16)
642 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
643 else
644 dst[0] = ir3_SEL_B16(b, src[1], 0, cond, 0, src[2], 0);
645 break;
646 }
647 case nir_op_bit_count: {
648 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
649 // double check on earlier gen's. Once half-precision support is
650 // in place, this should probably move to a NIR lowering pass:
651 struct ir3_instruction *hi, *lo;
652
653 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
654 TYPE_U32, TYPE_U16);
655 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
656
657 hi = ir3_CBITS_B(b, hi, 0);
658 lo = ir3_CBITS_B(b, lo, 0);
659
660 // TODO maybe the builders should default to making dst half-precision
661 // if the src's were half precision, to make this less awkward.. otoh
662 // we should probably just do this lowering in NIR.
663 hi->regs[0]->flags |= IR3_REG_HALF;
664 lo->regs[0]->flags |= IR3_REG_HALF;
665
666 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
667 dst[0]->regs[0]->flags |= IR3_REG_HALF;
668 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
669 break;
670 }
671 case nir_op_ifind_msb: {
672 struct ir3_instruction *cmp;
673 dst[0] = ir3_CLZ_S(b, src[0], 0);
674 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
675 cmp->cat2.condition = IR3_COND_GE;
676 dst[0] = ir3_SEL_B32(b,
677 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
678 cmp, 0, dst[0], 0);
679 break;
680 }
681 case nir_op_ufind_msb:
682 dst[0] = ir3_CLZ_B(b, src[0], 0);
683 dst[0] = ir3_SEL_B32(b,
684 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
685 src[0], 0, dst[0], 0);
686 break;
687 case nir_op_find_lsb:
688 dst[0] = ir3_BFREV_B(b, src[0], 0);
689 dst[0] = ir3_CLZ_B(b, dst[0], 0);
690 break;
691 case nir_op_bitfield_reverse:
692 dst[0] = ir3_BFREV_B(b, src[0], 0);
693 break;
694
695 default:
696 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
697 nir_op_infos[alu->op].name);
698 break;
699 }
700
701 if (nir_alu_type_get_base_type(info->output_type) == nir_type_bool) {
702 assert(nir_dest_bit_size(alu->dest.dest) == 1 ||
703 alu->op == nir_op_b2b32);
704 assert(dst_sz == 1);
705 } else {
706 /* 1-bit values stored in 32-bit registers are only valid for certain
707 * ALU ops.
708 */
709 switch (alu->op) {
710 case nir_op_iand:
711 case nir_op_ior:
712 case nir_op_ixor:
713 case nir_op_inot:
714 case nir_op_bcsel:
715 break;
716 default:
717 compile_assert(ctx, nir_dest_bit_size(alu->dest.dest) != 1);
718 }
719 }
720
721 ir3_put_dst(ctx, &alu->dest.dest);
722 }
723
724 static void
725 emit_intrinsic_load_ubo_ldc(struct ir3_context *ctx, nir_intrinsic_instr *intr,
726 struct ir3_instruction **dst)
727 {
728 struct ir3_block *b = ctx->block;
729
730 unsigned ncomp = intr->num_components;
731 struct ir3_instruction *offset = ir3_get_src(ctx, &intr->src[1])[0];
732 struct ir3_instruction *idx = ir3_get_src(ctx, &intr->src[0])[0];
733 struct ir3_instruction *ldc = ir3_LDC(b, idx, 0, offset, 0);
734 ldc->regs[0]->wrmask = MASK(ncomp);
735 ldc->cat6.iim_val = ncomp;
736 ldc->cat6.d = nir_intrinsic_component(intr);
737 ldc->cat6.type = TYPE_U32;
738
739 ir3_handle_bindless_cat6(ldc, intr->src[0]);
740 if (ldc->flags & IR3_INSTR_B)
741 ctx->so->bindless_ubo = true;
742
743 ir3_split_dest(b, dst, ldc, 0, ncomp);
744 }
745
746
747 /* handles direct/indirect UBO reads: */
748 static void
749 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
750 struct ir3_instruction **dst)
751 {
752 struct ir3_block *b = ctx->block;
753 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
754 const struct ir3_const_state *const_state = ir3_const_state(ctx->so);
755 unsigned ubo = regid(const_state->offsets.ubo, 0);
756 const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
757
758 int off = 0;
759
760 /* First src is ubo index, which could either be an immed or not: */
761 src0 = ir3_get_src(ctx, &intr->src[0])[0];
762 if (is_same_type_mov(src0) &&
763 (src0->regs[1]->flags & IR3_REG_IMMED)) {
764 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
765 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
766 } else {
767 base_lo = create_uniform_indirect(b, ubo, TYPE_U32, ir3_get_addr0(ctx, src0, ptrsz));
768 base_hi = create_uniform_indirect(b, ubo + 1, TYPE_U32, ir3_get_addr0(ctx, src0, ptrsz));
769
770 /* NOTE: since relative addressing is used, make sure constlen is
771 * at least big enough to cover all the UBO addresses, since the
772 * assembler won't know what the max address reg is.
773 */
774 ctx->so->constlen = MAX2(ctx->so->constlen,
775 const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
776 }
777
778 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
779 addr = base_lo;
780
781 if (nir_src_is_const(intr->src[1])) {
782 off += nir_src_as_uint(intr->src[1]);
783 } else {
784 /* For load_ubo_indirect, second src is indirect offset: */
785 src1 = ir3_get_src(ctx, &intr->src[1])[0];
786
787 /* and add offset to addr: */
788 addr = ir3_ADD_S(b, addr, 0, src1, 0);
789 }
790
791 /* if offset is to large to encode in the ldg, split it out: */
792 if ((off + (intr->num_components * 4)) > 1024) {
793 /* split out the minimal amount to improve the odds that
794 * cp can fit the immediate in the add.s instruction:
795 */
796 unsigned off2 = off + (intr->num_components * 4) - 1024;
797 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
798 off -= off2;
799 }
800
801 if (ptrsz == 2) {
802 struct ir3_instruction *carry;
803
804 /* handle 32b rollover, ie:
805 * if (addr < base_lo)
806 * base_hi++
807 */
808 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
809 carry->cat2.condition = IR3_COND_LT;
810 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
811
812 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
813 }
814
815 for (int i = 0; i < intr->num_components; i++) {
816 struct ir3_instruction *load =
817 ir3_LDG(b, addr, 0, create_immed(b, 1), 0, /* num components */
818 create_immed(b, off + i * 4), 0);
819 load->cat6.type = TYPE_U32;
820 dst[i] = load;
821 }
822 }
823
824 /* src[] = { block_index } */
825 static void
826 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
827 struct ir3_instruction **dst)
828 {
829 if (ir3_bindless_resource(intr->src[0])) {
830 struct ir3_block *b = ctx->block;
831 struct ir3_instruction *ibo = ir3_ssbo_to_ibo(ctx, intr->src[0]);
832 struct ir3_instruction *resinfo = ir3_RESINFO(b, ibo, 0);
833 resinfo->cat6.iim_val = 1;
834 resinfo->cat6.d = 1;
835 resinfo->cat6.type = TYPE_U32;
836 resinfo->cat6.typed = false;
837 /* resinfo has no writemask and always writes out 3 components */
838 resinfo->regs[0]->wrmask = MASK(3);
839 ir3_handle_bindless_cat6(resinfo, intr->src[0]);
840 struct ir3_instruction *resinfo_dst;
841 ir3_split_dest(b, &resinfo_dst, resinfo, 0, 1);
842 /* Unfortunately resinfo returns the array length, i.e. in dwords,
843 * while NIR expects us to return the size in bytes.
844 *
845 * TODO: fix this in NIR.
846 */
847 *dst = ir3_SHL_B(b, resinfo_dst, 0, create_immed(b, 2), 0);
848 return;
849 }
850
851 /* SSBO size stored as a const starting at ssbo_sizes: */
852 const struct ir3_const_state *const_state = ir3_const_state(ctx->so);
853 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
854 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
855 const_state->ssbo_size.off[blk_idx];
856
857 debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
858
859 dst[0] = create_uniform(ctx->block, idx);
860 }
861
862 /* src[] = { offset }. const_index[] = { base } */
863 static void
864 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
865 struct ir3_instruction **dst)
866 {
867 struct ir3_block *b = ctx->block;
868 struct ir3_instruction *ldl, *offset;
869 unsigned base;
870
871 offset = ir3_get_src(ctx, &intr->src[0])[0];
872 base = nir_intrinsic_base(intr);
873
874 ldl = ir3_LDL(b, offset, 0,
875 create_immed(b, intr->num_components), 0,
876 create_immed(b, base), 0);
877
878 ldl->cat6.type = utype_dst(intr->dest);
879 ldl->regs[0]->wrmask = MASK(intr->num_components);
880
881 ldl->barrier_class = IR3_BARRIER_SHARED_R;
882 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
883
884 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
885 }
886
887 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
888 static void
889 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
890 {
891 struct ir3_block *b = ctx->block;
892 struct ir3_instruction *stl, *offset;
893 struct ir3_instruction * const *value;
894 unsigned base, wrmask, ncomp;
895
896 value = ir3_get_src(ctx, &intr->src[0]);
897 offset = ir3_get_src(ctx, &intr->src[1])[0];
898
899 base = nir_intrinsic_base(intr);
900 wrmask = nir_intrinsic_write_mask(intr);
901 ncomp = ffs(~wrmask) - 1;
902
903 assert(wrmask == BITFIELD_MASK(intr->num_components));
904
905 stl = ir3_STL(b, offset, 0,
906 ir3_create_collect(ctx, value, ncomp), 0,
907 create_immed(b, ncomp), 0);
908 stl->cat6.dst_offset = base;
909 stl->cat6.type = utype_src(intr->src[0]);
910 stl->barrier_class = IR3_BARRIER_SHARED_W;
911 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
912
913 array_insert(b, b->keeps, stl);
914 }
915
916 /* src[] = { offset }. const_index[] = { base } */
917 static void
918 emit_intrinsic_load_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr,
919 struct ir3_instruction **dst)
920 {
921 struct ir3_block *b = ctx->block;
922 struct ir3_instruction *load, *offset;
923 unsigned base;
924
925 offset = ir3_get_src(ctx, &intr->src[0])[0];
926 base = nir_intrinsic_base(intr);
927
928 load = ir3_LDLW(b, offset, 0,
929 create_immed(b, intr->num_components), 0,
930 create_immed(b, base), 0);
931
932 /* for a650, use LDL for tess ctrl inputs: */
933 if (ctx->so->type == MESA_SHADER_TESS_CTRL && ctx->compiler->tess_use_shared)
934 load->opc = OPC_LDL;
935
936 load->cat6.type = utype_dst(intr->dest);
937 load->regs[0]->wrmask = MASK(intr->num_components);
938
939 load->barrier_class = IR3_BARRIER_SHARED_R;
940 load->barrier_conflict = IR3_BARRIER_SHARED_W;
941
942 ir3_split_dest(b, dst, load, 0, intr->num_components);
943 }
944
945 /* src[] = { value, offset }. const_index[] = { base } */
946 static void
947 emit_intrinsic_store_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr)
948 {
949 struct ir3_block *b = ctx->block;
950 struct ir3_instruction *store, *offset;
951 struct ir3_instruction * const *value;
952
953 value = ir3_get_src(ctx, &intr->src[0]);
954 offset = ir3_get_src(ctx, &intr->src[1])[0];
955
956 store = ir3_STLW(b, offset, 0,
957 ir3_create_collect(ctx, value, intr->num_components), 0,
958 create_immed(b, intr->num_components), 0);
959
960 /* for a650, use STL for vertex outputs used by tess ctrl shader: */
961 if (ctx->so->type == MESA_SHADER_VERTEX && ctx->so->key.tessellation &&
962 ctx->compiler->tess_use_shared)
963 store->opc = OPC_STL;
964
965 store->cat6.dst_offset = nir_intrinsic_base(intr);
966 store->cat6.type = utype_src(intr->src[0]);
967 store->barrier_class = IR3_BARRIER_SHARED_W;
968 store->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
969
970 array_insert(b, b->keeps, store);
971 }
972
973 /*
974 * CS shared variable atomic intrinsics
975 *
976 * All of the shared variable atomic memory operations read a value from
977 * memory, compute a new value using one of the operations below, write the
978 * new value to memory, and return the original value read.
979 *
980 * All operations take 2 sources except CompSwap that takes 3. These
981 * sources represent:
982 *
983 * 0: The offset into the shared variable storage region that the atomic
984 * operation will operate on.
985 * 1: The data parameter to the atomic function (i.e. the value to add
986 * in shared_atomic_add, etc).
987 * 2: For CompSwap only: the second data parameter.
988 */
989 static struct ir3_instruction *
990 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
991 {
992 struct ir3_block *b = ctx->block;
993 struct ir3_instruction *atomic, *src0, *src1;
994 type_t type = TYPE_U32;
995
996 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
997 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
998
999 switch (intr->intrinsic) {
1000 case nir_intrinsic_shared_atomic_add:
1001 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
1002 break;
1003 case nir_intrinsic_shared_atomic_imin:
1004 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
1005 type = TYPE_S32;
1006 break;
1007 case nir_intrinsic_shared_atomic_umin:
1008 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
1009 break;
1010 case nir_intrinsic_shared_atomic_imax:
1011 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1012 type = TYPE_S32;
1013 break;
1014 case nir_intrinsic_shared_atomic_umax:
1015 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1016 break;
1017 case nir_intrinsic_shared_atomic_and:
1018 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
1019 break;
1020 case nir_intrinsic_shared_atomic_or:
1021 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
1022 break;
1023 case nir_intrinsic_shared_atomic_xor:
1024 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
1025 break;
1026 case nir_intrinsic_shared_atomic_exchange:
1027 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
1028 break;
1029 case nir_intrinsic_shared_atomic_comp_swap:
1030 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1031 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1032 ir3_get_src(ctx, &intr->src[2])[0],
1033 src1,
1034 }, 2);
1035 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
1036 break;
1037 default:
1038 unreachable("boo");
1039 }
1040
1041 atomic->cat6.iim_val = 1;
1042 atomic->cat6.d = 1;
1043 atomic->cat6.type = type;
1044 atomic->barrier_class = IR3_BARRIER_SHARED_W;
1045 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
1046
1047 /* even if nothing consume the result, we can't DCE the instruction: */
1048 array_insert(b, b->keeps, atomic);
1049
1050 return atomic;
1051 }
1052
1053 struct tex_src_info {
1054 /* For prefetch */
1055 unsigned tex_base, samp_base, tex_idx, samp_idx;
1056 /* For normal tex instructions */
1057 unsigned base, combined_idx, a1_val, flags;
1058 struct ir3_instruction *samp_tex;
1059 };
1060
1061 /* TODO handle actual indirect/dynamic case.. which is going to be weird
1062 * to handle with the image_mapping table..
1063 */
1064 static struct tex_src_info
1065 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1066 {
1067 struct ir3_block *b = ctx->block;
1068 struct tex_src_info info = { 0 };
1069 nir_intrinsic_instr *bindless_tex = ir3_bindless_resource(intr->src[0]);
1070 ctx->so->bindless_tex = true;
1071
1072 if (bindless_tex) {
1073 /* Bindless case */
1074 info.flags |= IR3_INSTR_B;
1075
1076 /* Gather information required to determine which encoding to
1077 * choose as well as for prefetch.
1078 */
1079 info.tex_base = nir_intrinsic_desc_set(bindless_tex);
1080 bool tex_const = nir_src_is_const(bindless_tex->src[0]);
1081 if (tex_const)
1082 info.tex_idx = nir_src_as_uint(bindless_tex->src[0]);
1083 info.samp_idx = 0;
1084
1085 /* Choose encoding. */
1086 if (tex_const && info.tex_idx < 256) {
1087 if (info.tex_idx < 16) {
1088 /* Everything fits within the instruction */
1089 info.base = info.tex_base;
1090 info.combined_idx = info.samp_idx | (info.tex_idx << 4);
1091 } else {
1092 info.base = info.tex_base;
1093 info.a1_val = info.tex_idx << 3;
1094 info.combined_idx = 0;
1095 info.flags |= IR3_INSTR_A1EN;
1096 }
1097 info.samp_tex = NULL;
1098 } else {
1099 info.flags |= IR3_INSTR_S2EN;
1100 info.base = info.tex_base;
1101
1102 /* Note: the indirect source is now a vec2 instead of hvec2 */
1103 struct ir3_instruction *texture, *sampler;
1104
1105 texture = ir3_get_src(ctx, &intr->src[0])[0];
1106 sampler = create_immed(b, 0);
1107 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1108 texture,
1109 sampler,
1110 }, 2);
1111 }
1112 } else {
1113 info.flags |= IR3_INSTR_S2EN;
1114 unsigned slot = nir_src_as_uint(intr->src[0]);
1115 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
1116 struct ir3_instruction *texture, *sampler;
1117
1118 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1119 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1120
1121 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1122 sampler,
1123 texture,
1124 }, 2);
1125 }
1126
1127 return info;
1128 }
1129
1130 static struct ir3_instruction *
1131 emit_sam(struct ir3_context *ctx, opc_t opc, struct tex_src_info info,
1132 type_t type, unsigned wrmask, struct ir3_instruction *src0,
1133 struct ir3_instruction *src1)
1134 {
1135 struct ir3_instruction *sam, *addr;
1136 if (info.flags & IR3_INSTR_A1EN) {
1137 addr = ir3_get_addr1(ctx, info.a1_val);
1138 }
1139 sam = ir3_SAM(ctx->block, opc, type, 0b1111, info.flags,
1140 info.samp_tex, src0, src1);
1141 if (info.flags & IR3_INSTR_A1EN) {
1142 ir3_instr_set_address(sam, addr);
1143 }
1144 if (info.flags & IR3_INSTR_B) {
1145 sam->cat5.tex_base = info.base;
1146 sam->cat5.samp = info.combined_idx;
1147 }
1148 return sam;
1149 }
1150
1151 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1152 static void
1153 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1154 struct ir3_instruction **dst)
1155 {
1156 struct ir3_block *b = ctx->block;
1157 struct tex_src_info info = get_image_samp_tex_src(ctx, intr);
1158 struct ir3_instruction *sam;
1159 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
1160 struct ir3_instruction *coords[4];
1161 unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
1162 type_t type = ir3_get_type_for_image_intrinsic(intr);
1163
1164 /* hmm, this seems a bit odd, but it is what blob does and (at least
1165 * a5xx) just faults on bogus addresses otherwise:
1166 */
1167 if (flags & IR3_INSTR_3D) {
1168 flags &= ~IR3_INSTR_3D;
1169 flags |= IR3_INSTR_A;
1170 }
1171 info.flags |= flags;
1172
1173 for (unsigned i = 0; i < ncoords; i++)
1174 coords[i] = src0[i];
1175
1176 if (ncoords == 1)
1177 coords[ncoords++] = create_immed(b, 0);
1178
1179 sam = emit_sam(ctx, OPC_ISAM, info, type, 0b1111,
1180 ir3_create_collect(ctx, coords, ncoords), NULL);
1181
1182 sam->barrier_class = IR3_BARRIER_IMAGE_R;
1183 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
1184
1185 ir3_split_dest(b, dst, sam, 0, 4);
1186 }
1187
1188 /* A4xx version of image_size, see ir3_a6xx.c for newer resinfo version. */
1189 void
1190 emit_intrinsic_image_size_tex(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1191 struct ir3_instruction **dst)
1192 {
1193 struct ir3_block *b = ctx->block;
1194 struct tex_src_info info = get_image_samp_tex_src(ctx, intr);
1195 struct ir3_instruction *sam, *lod;
1196 unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
1197 type_t dst_type = nir_dest_bit_size(intr->dest) == 16 ?
1198 TYPE_U16 : TYPE_U32;
1199
1200 info.flags |= flags;
1201 assert(nir_src_as_uint(intr->src[1]) == 0);
1202 lod = create_immed(b, 0);
1203 sam = emit_sam(ctx, OPC_GETSIZE, info, dst_type, 0b1111, lod, NULL);
1204
1205 /* Array size actually ends up in .w rather than .z. This doesn't
1206 * matter for miplevel 0, but for higher mips the value in z is
1207 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1208 * returned, which means that we have to add 1 to it for arrays for
1209 * a3xx.
1210 *
1211 * Note use a temporary dst and then copy, since the size of the dst
1212 * array that is passed in is based on nir's understanding of the
1213 * result size, not the hardware's
1214 */
1215 struct ir3_instruction *tmp[4];
1216
1217 ir3_split_dest(b, tmp, sam, 0, 4);
1218
1219 /* get_size instruction returns size in bytes instead of texels
1220 * for imageBuffer, so we need to divide it by the pixel size
1221 * of the image format.
1222 *
1223 * TODO: This is at least true on a5xx. Check other gens.
1224 */
1225 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF) {
1226 /* Since all the possible values the divisor can take are
1227 * power-of-two (4, 8, or 16), the division is implemented
1228 * as a shift-right.
1229 * During shader setup, the log2 of the image format's
1230 * bytes-per-pixel should have been emitted in 2nd slot of
1231 * image_dims. See ir3_shader::emit_image_dims().
1232 */
1233 const struct ir3_const_state *const_state =
1234 ir3_const_state(ctx->so);
1235 unsigned cb = regid(const_state->offsets.image_dims, 0) +
1236 const_state->image_dims.off[nir_src_as_uint(intr->src[0])];
1237 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1238
1239 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1240 }
1241
1242 for (unsigned i = 0; i < ncoords; i++)
1243 dst[i] = tmp[i];
1244
1245 if (flags & IR3_INSTR_A) {
1246 if (ctx->compiler->levels_add_one) {
1247 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1248 } else {
1249 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1250 }
1251 }
1252 }
1253
1254 static void
1255 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1256 {
1257 struct ir3_block *b = ctx->block;
1258 struct ir3_instruction *barrier;
1259
1260 switch (intr->intrinsic) {
1261 case nir_intrinsic_control_barrier:
1262 barrier = ir3_BAR(b);
1263 barrier->cat7.g = true;
1264 barrier->cat7.l = true;
1265 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1266 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1267 break;
1268 case nir_intrinsic_memory_barrier:
1269 barrier = ir3_FENCE(b);
1270 barrier->cat7.g = true;
1271 barrier->cat7.r = true;
1272 barrier->cat7.w = true;
1273 barrier->cat7.l = true;
1274 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1275 IR3_BARRIER_BUFFER_W;
1276 barrier->barrier_conflict =
1277 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1278 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1279 break;
1280 case nir_intrinsic_memory_barrier_buffer:
1281 barrier = ir3_FENCE(b);
1282 barrier->cat7.g = true;
1283 barrier->cat7.r = true;
1284 barrier->cat7.w = true;
1285 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1286 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1287 IR3_BARRIER_BUFFER_W;
1288 break;
1289 case nir_intrinsic_memory_barrier_image:
1290 // TODO double check if this should have .g set
1291 barrier = ir3_FENCE(b);
1292 barrier->cat7.g = true;
1293 barrier->cat7.r = true;
1294 barrier->cat7.w = true;
1295 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1296 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1297 IR3_BARRIER_IMAGE_W;
1298 break;
1299 case nir_intrinsic_memory_barrier_shared:
1300 barrier = ir3_FENCE(b);
1301 barrier->cat7.g = true;
1302 barrier->cat7.l = true;
1303 barrier->cat7.r = true;
1304 barrier->cat7.w = true;
1305 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1306 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1307 IR3_BARRIER_SHARED_W;
1308 break;
1309 case nir_intrinsic_group_memory_barrier:
1310 barrier = ir3_FENCE(b);
1311 barrier->cat7.g = true;
1312 barrier->cat7.l = true;
1313 barrier->cat7.r = true;
1314 barrier->cat7.w = true;
1315 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1316 IR3_BARRIER_IMAGE_W |
1317 IR3_BARRIER_BUFFER_W;
1318 barrier->barrier_conflict =
1319 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1320 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1321 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1322 break;
1323 default:
1324 unreachable("boo");
1325 }
1326
1327 /* make sure barrier doesn't get DCE'd */
1328 array_insert(b, b->keeps, barrier);
1329 }
1330
1331 static void add_sysval_input_compmask(struct ir3_context *ctx,
1332 gl_system_value slot, unsigned compmask,
1333 struct ir3_instruction *instr)
1334 {
1335 struct ir3_shader_variant *so = ctx->so;
1336 unsigned n = so->inputs_count++;
1337
1338 assert(instr->opc == OPC_META_INPUT);
1339 instr->input.inidx = n;
1340 instr->input.sysval = slot;
1341
1342 so->inputs[n].sysval = true;
1343 so->inputs[n].slot = slot;
1344 so->inputs[n].compmask = compmask;
1345 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1346 so->total_in++;
1347 }
1348
1349 static struct ir3_instruction *
1350 create_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1351 unsigned compmask)
1352 {
1353 assert(compmask);
1354 struct ir3_instruction *sysval = create_input(ctx, compmask);
1355 add_sysval_input_compmask(ctx, slot, compmask, sysval);
1356 return sysval;
1357 }
1358
1359 static struct ir3_instruction *
1360 get_barycentric(struct ir3_context *ctx, enum ir3_bary bary)
1361 {
1362 static const gl_system_value sysval_base = SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL;
1363
1364 STATIC_ASSERT(sysval_base + IJ_PERSP_PIXEL == SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL);
1365 STATIC_ASSERT(sysval_base + IJ_PERSP_SAMPLE == SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE);
1366 STATIC_ASSERT(sysval_base + IJ_PERSP_CENTROID == SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID);
1367 STATIC_ASSERT(sysval_base + IJ_PERSP_SIZE == SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE);
1368 STATIC_ASSERT(sysval_base + IJ_LINEAR_PIXEL == SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL);
1369 STATIC_ASSERT(sysval_base + IJ_LINEAR_CENTROID == SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID);
1370 STATIC_ASSERT(sysval_base + IJ_LINEAR_SAMPLE == SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE);
1371
1372 if (!ctx->ij[bary]) {
1373 struct ir3_instruction *xy[2];
1374 struct ir3_instruction *ij;
1375
1376 ij = create_sysval_input(ctx, sysval_base + bary, 0x3);
1377 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1378
1379 ctx->ij[bary] = ir3_create_collect(ctx, xy, 2);
1380 }
1381
1382 return ctx->ij[bary];
1383 }
1384
1385 /* TODO: make this a common NIR helper?
1386 * there is a nir_system_value_from_intrinsic but it takes nir_intrinsic_op so it
1387 * can't be extended to work with this
1388 */
1389 static gl_system_value
1390 nir_intrinsic_barycentric_sysval(nir_intrinsic_instr *intr)
1391 {
1392 enum glsl_interp_mode interp_mode = nir_intrinsic_interp_mode(intr);
1393 gl_system_value sysval;
1394
1395 switch (intr->intrinsic) {
1396 case nir_intrinsic_load_barycentric_pixel:
1397 if (interp_mode == INTERP_MODE_NOPERSPECTIVE)
1398 sysval = SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL;
1399 else
1400 sysval = SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL;
1401 break;
1402 case nir_intrinsic_load_barycentric_centroid:
1403 if (interp_mode == INTERP_MODE_NOPERSPECTIVE)
1404 sysval = SYSTEM_VALUE_BARYCENTRIC_LINEAR_CENTROID;
1405 else
1406 sysval = SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID;
1407 break;
1408 case nir_intrinsic_load_barycentric_sample:
1409 if (interp_mode == INTERP_MODE_NOPERSPECTIVE)
1410 sysval = SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE;
1411 else
1412 sysval = SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE;
1413 break;
1414 default:
1415 unreachable("invalid barycentric intrinsic");
1416 }
1417
1418 return sysval;
1419 }
1420
1421 static void
1422 emit_intrinsic_barycentric(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1423 struct ir3_instruction **dst)
1424 {
1425 gl_system_value sysval = nir_intrinsic_barycentric_sysval(intr);
1426
1427 if (!ctx->so->key.msaa) {
1428 if (sysval == SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE)
1429 sysval = SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL;
1430 if (sysval == SYSTEM_VALUE_BARYCENTRIC_LINEAR_SAMPLE)
1431 sysval = SYSTEM_VALUE_BARYCENTRIC_LINEAR_PIXEL;
1432 }
1433
1434 enum ir3_bary bary = sysval - SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL;
1435
1436 struct ir3_instruction *ij = get_barycentric(ctx, bary);
1437 ir3_split_dest(ctx->block, dst, ij, 0, 2);
1438 }
1439
1440 static struct ir3_instruction *
1441 get_frag_coord(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1442 {
1443 if (!ctx->frag_coord) {
1444 struct ir3_block *b = ctx->in_block;
1445 struct ir3_instruction *xyzw[4];
1446 struct ir3_instruction *hw_frag_coord;
1447
1448 hw_frag_coord = create_sysval_input(ctx, SYSTEM_VALUE_FRAG_COORD, 0xf);
1449 ir3_split_dest(b, xyzw, hw_frag_coord, 0, 4);
1450
1451 /* for frag_coord.xy, we get unsigned values.. we need
1452 * to subtract (integer) 8 and divide by 16 (right-
1453 * shift by 4) then convert to float:
1454 *
1455 * sub.s tmp, src, 8
1456 * shr.b tmp, tmp, 4
1457 * mov.u32f32 dst, tmp
1458 *
1459 */
1460 for (int i = 0; i < 2; i++) {
1461 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1462 xyzw[i] = ir3_MUL_F(b, xyzw[i], 0, create_immed(b, fui(1.0 / 16.0)), 0);
1463 }
1464
1465 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1466 }
1467
1468 ctx->so->fragcoord_compmask |=
1469 nir_ssa_def_components_read(&intr->dest.ssa);
1470
1471 return ctx->frag_coord;
1472 }
1473
1474 static void
1475 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1476 {
1477 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1478 struct ir3_instruction **dst;
1479 struct ir3_instruction * const *src;
1480 struct ir3_block *b = ctx->block;
1481 unsigned dest_components = nir_intrinsic_dest_components(intr);
1482 int idx, comp;
1483
1484 if (info->has_dest) {
1485 dst = ir3_get_dst(ctx, &intr->dest, dest_components);
1486 } else {
1487 dst = NULL;
1488 }
1489
1490 const struct ir3_const_state *const_state = ir3_const_state(ctx->so);
1491 const unsigned primitive_param = const_state->offsets.primitive_param * 4;
1492 const unsigned primitive_map = const_state->offsets.primitive_map * 4;
1493
1494 switch (intr->intrinsic) {
1495 case nir_intrinsic_load_uniform:
1496 idx = nir_intrinsic_base(intr);
1497 if (nir_src_is_const(intr->src[0])) {
1498 idx += nir_src_as_uint(intr->src[0]);
1499 for (int i = 0; i < dest_components; i++) {
1500 dst[i] = create_uniform_typed(b, idx + i,
1501 nir_dest_bit_size(intr->dest) == 16 ? TYPE_F16 : TYPE_F32);
1502 }
1503 } else {
1504 src = ir3_get_src(ctx, &intr->src[0]);
1505 for (int i = 0; i < dest_components; i++) {
1506 dst[i] = create_uniform_indirect(b, idx + i,
1507 nir_dest_bit_size(intr->dest) == 16 ? TYPE_F16 : TYPE_F32,
1508 ir3_get_addr0(ctx, src[0], 1));
1509 }
1510 /* NOTE: if relative addressing is used, we set
1511 * constlen in the compiler (to worst-case value)
1512 * since we don't know in the assembler what the max
1513 * addr reg value can be:
1514 */
1515 ctx->so->constlen = MAX2(ctx->so->constlen,
1516 const_state->ubo_state.size / 16);
1517 }
1518 break;
1519
1520 case nir_intrinsic_load_vs_primitive_stride_ir3:
1521 dst[0] = create_uniform(b, primitive_param + 0);
1522 break;
1523 case nir_intrinsic_load_vs_vertex_stride_ir3:
1524 dst[0] = create_uniform(b, primitive_param + 1);
1525 break;
1526 case nir_intrinsic_load_hs_patch_stride_ir3:
1527 dst[0] = create_uniform(b, primitive_param + 2);
1528 break;
1529 case nir_intrinsic_load_patch_vertices_in:
1530 dst[0] = create_uniform(b, primitive_param + 3);
1531 break;
1532 case nir_intrinsic_load_tess_param_base_ir3:
1533 dst[0] = create_uniform(b, primitive_param + 4);
1534 dst[1] = create_uniform(b, primitive_param + 5);
1535 break;
1536 case nir_intrinsic_load_tess_factor_base_ir3:
1537 dst[0] = create_uniform(b, primitive_param + 6);
1538 dst[1] = create_uniform(b, primitive_param + 7);
1539 break;
1540
1541 case nir_intrinsic_load_primitive_location_ir3:
1542 idx = nir_intrinsic_driver_location(intr);
1543 dst[0] = create_uniform(b, primitive_map + idx);
1544 break;
1545
1546 case nir_intrinsic_load_gs_header_ir3:
1547 dst[0] = ctx->gs_header;
1548 break;
1549 case nir_intrinsic_load_tcs_header_ir3:
1550 dst[0] = ctx->tcs_header;
1551 break;
1552
1553 case nir_intrinsic_load_primitive_id:
1554 dst[0] = ctx->primitive_id;
1555 break;
1556
1557 case nir_intrinsic_load_tess_coord:
1558 if (!ctx->tess_coord) {
1559 ctx->tess_coord =
1560 create_sysval_input(ctx, SYSTEM_VALUE_TESS_COORD, 0x3);
1561 }
1562 ir3_split_dest(b, dst, ctx->tess_coord, 0, 2);
1563
1564 /* Unused, but ir3_put_dst() below wants to free something */
1565 dst[2] = create_immed(b, 0);
1566 break;
1567
1568 case nir_intrinsic_end_patch_ir3:
1569 assert(ctx->so->type == MESA_SHADER_TESS_CTRL);
1570 struct ir3_instruction *end = ir3_PREDE(b);
1571 array_insert(b, b->keeps, end);
1572
1573 end->barrier_class = IR3_BARRIER_EVERYTHING;
1574 end->barrier_conflict = IR3_BARRIER_EVERYTHING;
1575 break;
1576
1577 case nir_intrinsic_store_global_ir3: {
1578 struct ir3_instruction *value, *addr, *offset;
1579 unsigned ncomp = nir_intrinsic_src_components(intr, 0);
1580
1581 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1582 ir3_get_src(ctx, &intr->src[1])[0],
1583 ir3_get_src(ctx, &intr->src[1])[1]
1584 }, 2);
1585
1586 offset = ir3_get_src(ctx, &intr->src[2])[0];
1587
1588 value = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]), ncomp);
1589
1590 struct ir3_instruction *stg =
1591 ir3_STG_G(ctx->block, addr, 0, value, 0,
1592 create_immed(ctx->block, ncomp), 0, offset, 0);
1593 stg->cat6.type = TYPE_U32;
1594 stg->cat6.iim_val = 1;
1595
1596 array_insert(b, b->keeps, stg);
1597
1598 stg->barrier_class = IR3_BARRIER_BUFFER_W;
1599 stg->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1600 break;
1601 }
1602
1603 case nir_intrinsic_load_global_ir3: {
1604 struct ir3_instruction *addr, *offset;
1605
1606 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1607 ir3_get_src(ctx, &intr->src[0])[0],
1608 ir3_get_src(ctx, &intr->src[0])[1]
1609 }, 2);
1610
1611 offset = ir3_get_src(ctx, &intr->src[1])[0];
1612
1613 struct ir3_instruction *load =
1614 ir3_LDG(b, addr, 0, create_immed(ctx->block, dest_components),
1615 0, offset, 0);
1616 load->cat6.type = TYPE_U32;
1617 load->regs[0]->wrmask = MASK(dest_components);
1618
1619 load->barrier_class = IR3_BARRIER_BUFFER_R;
1620 load->barrier_conflict = IR3_BARRIER_BUFFER_W;
1621
1622 ir3_split_dest(b, dst, load, 0, dest_components);
1623 break;
1624 }
1625
1626 case nir_intrinsic_load_ubo:
1627 emit_intrinsic_load_ubo(ctx, intr, dst);
1628 break;
1629 case nir_intrinsic_load_ubo_vec4:
1630 emit_intrinsic_load_ubo_ldc(ctx, intr, dst);
1631 break;
1632 case nir_intrinsic_load_frag_coord:
1633 ir3_split_dest(b, dst, get_frag_coord(ctx, intr), 0, 4);
1634 break;
1635 case nir_intrinsic_load_sample_pos_from_id: {
1636 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1637 * but that doesn't seem necessary.
1638 */
1639 struct ir3_instruction *offset =
1640 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1641 offset->regs[0]->wrmask = 0x3;
1642 offset->cat5.type = TYPE_F32;
1643
1644 ir3_split_dest(b, dst, offset, 0, 2);
1645
1646 break;
1647 }
1648 case nir_intrinsic_load_size_ir3:
1649 if (!ctx->ij[IJ_PERSP_SIZE]) {
1650 ctx->ij[IJ_PERSP_SIZE] =
1651 create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE, 0x1);
1652 }
1653 dst[0] = ctx->ij[IJ_PERSP_SIZE];
1654 break;
1655 case nir_intrinsic_load_barycentric_centroid:
1656 case nir_intrinsic_load_barycentric_sample:
1657 case nir_intrinsic_load_barycentric_pixel:
1658 emit_intrinsic_barycentric(ctx, intr, dst);
1659 break;
1660 case nir_intrinsic_load_interpolated_input:
1661 idx = nir_intrinsic_base(intr);
1662 comp = nir_intrinsic_component(intr);
1663 src = ir3_get_src(ctx, &intr->src[0]);
1664 if (nir_src_is_const(intr->src[1])) {
1665 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1666 idx += nir_src_as_uint(intr->src[1]);
1667 for (int i = 0; i < dest_components; i++) {
1668 unsigned inloc = idx * 4 + i + comp;
1669 if (ctx->so->inputs[idx].bary &&
1670 !ctx->so->inputs[idx].use_ldlv) {
1671 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1672 } else {
1673 /* for non-varyings use the pre-setup input, since
1674 * that is easier than mapping things back to a
1675 * nir_variable to figure out what it is.
1676 */
1677 dst[i] = ctx->inputs[inloc];
1678 compile_assert(ctx, dst[i]);
1679 }
1680 }
1681 } else {
1682 ir3_context_error(ctx, "unhandled");
1683 }
1684 break;
1685 case nir_intrinsic_load_input:
1686 idx = nir_intrinsic_base(intr);
1687 comp = nir_intrinsic_component(intr);
1688 if (nir_src_is_const(intr->src[0])) {
1689 idx += nir_src_as_uint(intr->src[0]);
1690 for (int i = 0; i < dest_components; i++) {
1691 unsigned n = idx * 4 + i + comp;
1692 dst[i] = ctx->inputs[n];
1693 compile_assert(ctx, ctx->inputs[n]);
1694 }
1695 } else {
1696 ir3_context_error(ctx, "unhandled");
1697 }
1698 break;
1699 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1700 * pass and replaced by an ir3-specifc version that adds the
1701 * dword-offset in the last source.
1702 */
1703 case nir_intrinsic_load_ssbo_ir3:
1704 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1705 break;
1706 case nir_intrinsic_store_ssbo_ir3:
1707 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1708 !ctx->s->info.fs.early_fragment_tests)
1709 ctx->so->no_earlyz = true;
1710 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1711 break;
1712 case nir_intrinsic_get_buffer_size:
1713 emit_intrinsic_ssbo_size(ctx, intr, dst);
1714 break;
1715 case nir_intrinsic_ssbo_atomic_add_ir3:
1716 case nir_intrinsic_ssbo_atomic_imin_ir3:
1717 case nir_intrinsic_ssbo_atomic_umin_ir3:
1718 case nir_intrinsic_ssbo_atomic_imax_ir3:
1719 case nir_intrinsic_ssbo_atomic_umax_ir3:
1720 case nir_intrinsic_ssbo_atomic_and_ir3:
1721 case nir_intrinsic_ssbo_atomic_or_ir3:
1722 case nir_intrinsic_ssbo_atomic_xor_ir3:
1723 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1724 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1725 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1726 !ctx->s->info.fs.early_fragment_tests)
1727 ctx->so->no_earlyz = true;
1728 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1729 break;
1730 case nir_intrinsic_load_shared:
1731 emit_intrinsic_load_shared(ctx, intr, dst);
1732 break;
1733 case nir_intrinsic_store_shared:
1734 emit_intrinsic_store_shared(ctx, intr);
1735 break;
1736 case nir_intrinsic_shared_atomic_add:
1737 case nir_intrinsic_shared_atomic_imin:
1738 case nir_intrinsic_shared_atomic_umin:
1739 case nir_intrinsic_shared_atomic_imax:
1740 case nir_intrinsic_shared_atomic_umax:
1741 case nir_intrinsic_shared_atomic_and:
1742 case nir_intrinsic_shared_atomic_or:
1743 case nir_intrinsic_shared_atomic_xor:
1744 case nir_intrinsic_shared_atomic_exchange:
1745 case nir_intrinsic_shared_atomic_comp_swap:
1746 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1747 break;
1748 case nir_intrinsic_image_load:
1749 emit_intrinsic_load_image(ctx, intr, dst);
1750 break;
1751 case nir_intrinsic_bindless_image_load:
1752 /* Bindless uses the IBO state, which doesn't have swizzle filled out,
1753 * so using isam doesn't work.
1754 *
1755 * TODO: can we use isam if we fill out more fields?
1756 */
1757 ctx->funcs->emit_intrinsic_load_image(ctx, intr, dst);
1758 break;
1759 case nir_intrinsic_image_store:
1760 case nir_intrinsic_bindless_image_store:
1761 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1762 !ctx->s->info.fs.early_fragment_tests)
1763 ctx->so->no_earlyz = true;
1764 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1765 break;
1766 case nir_intrinsic_image_size:
1767 case nir_intrinsic_bindless_image_size:
1768 ctx->funcs->emit_intrinsic_image_size(ctx, intr, dst);
1769 break;
1770 case nir_intrinsic_image_atomic_add:
1771 case nir_intrinsic_bindless_image_atomic_add:
1772 case nir_intrinsic_image_atomic_imin:
1773 case nir_intrinsic_bindless_image_atomic_imin:
1774 case nir_intrinsic_image_atomic_umin:
1775 case nir_intrinsic_bindless_image_atomic_umin:
1776 case nir_intrinsic_image_atomic_imax:
1777 case nir_intrinsic_bindless_image_atomic_imax:
1778 case nir_intrinsic_image_atomic_umax:
1779 case nir_intrinsic_bindless_image_atomic_umax:
1780 case nir_intrinsic_image_atomic_and:
1781 case nir_intrinsic_bindless_image_atomic_and:
1782 case nir_intrinsic_image_atomic_or:
1783 case nir_intrinsic_bindless_image_atomic_or:
1784 case nir_intrinsic_image_atomic_xor:
1785 case nir_intrinsic_bindless_image_atomic_xor:
1786 case nir_intrinsic_image_atomic_exchange:
1787 case nir_intrinsic_bindless_image_atomic_exchange:
1788 case nir_intrinsic_image_atomic_comp_swap:
1789 case nir_intrinsic_bindless_image_atomic_comp_swap:
1790 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1791 !ctx->s->info.fs.early_fragment_tests)
1792 ctx->so->no_earlyz = true;
1793 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1794 break;
1795 case nir_intrinsic_control_barrier:
1796 case nir_intrinsic_memory_barrier:
1797 case nir_intrinsic_group_memory_barrier:
1798 case nir_intrinsic_memory_barrier_buffer:
1799 case nir_intrinsic_memory_barrier_image:
1800 case nir_intrinsic_memory_barrier_shared:
1801 emit_intrinsic_barrier(ctx, intr);
1802 /* note that blk ptr no longer valid, make that obvious: */
1803 b = NULL;
1804 break;
1805 case nir_intrinsic_store_output:
1806 idx = nir_intrinsic_base(intr);
1807 comp = nir_intrinsic_component(intr);
1808 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1809 idx += nir_src_as_uint(intr->src[1]);
1810
1811 src = ir3_get_src(ctx, &intr->src[0]);
1812 for (int i = 0; i < nir_intrinsic_src_components(intr, 0); i++) {
1813 unsigned n = idx * 4 + i + comp;
1814 ctx->outputs[n] = src[i];
1815 }
1816 break;
1817 case nir_intrinsic_load_base_vertex:
1818 case nir_intrinsic_load_first_vertex:
1819 if (!ctx->basevertex) {
1820 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1821 }
1822 dst[0] = ctx->basevertex;
1823 break;
1824 case nir_intrinsic_load_draw_id:
1825 if (!ctx->draw_id) {
1826 ctx->draw_id = create_driver_param(ctx, IR3_DP_DRAWID);
1827 }
1828 dst[0] = ctx->draw_id;
1829 break;
1830 case nir_intrinsic_load_base_instance:
1831 if (!ctx->base_instance) {
1832 ctx->base_instance = create_driver_param(ctx, IR3_DP_INSTID_BASE);
1833 }
1834 dst[0] = ctx->base_instance;
1835 break;
1836 case nir_intrinsic_load_view_index:
1837 if (!ctx->view_index) {
1838 ctx->view_index = create_sysval_input(ctx, SYSTEM_VALUE_VIEW_INDEX, 0x1);
1839 }
1840 dst[0] = ctx->view_index;
1841 break;
1842 case nir_intrinsic_load_vertex_id_zero_base:
1843 case nir_intrinsic_load_vertex_id:
1844 if (!ctx->vertex_id) {
1845 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1846 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1847 ctx->vertex_id = create_sysval_input(ctx, sv, 0x1);
1848 }
1849 dst[0] = ctx->vertex_id;
1850 break;
1851 case nir_intrinsic_load_instance_id:
1852 if (!ctx->instance_id) {
1853 ctx->instance_id = create_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID, 0x1);
1854 }
1855 dst[0] = ctx->instance_id;
1856 break;
1857 case nir_intrinsic_load_sample_id:
1858 ctx->so->per_samp = true;
1859 /* fall-thru */
1860 case nir_intrinsic_load_sample_id_no_per_sample:
1861 if (!ctx->samp_id) {
1862 ctx->samp_id = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID, 0x1);
1863 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1864 }
1865 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1866 break;
1867 case nir_intrinsic_load_sample_mask_in:
1868 if (!ctx->samp_mask_in) {
1869 ctx->samp_mask_in = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN, 0x1);
1870 }
1871 dst[0] = ctx->samp_mask_in;
1872 break;
1873 case nir_intrinsic_load_user_clip_plane:
1874 idx = nir_intrinsic_ucp_id(intr);
1875 for (int i = 0; i < dest_components; i++) {
1876 unsigned n = idx * 4 + i;
1877 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1878 }
1879 break;
1880 case nir_intrinsic_load_front_face:
1881 if (!ctx->frag_face) {
1882 ctx->so->frag_face = true;
1883 ctx->frag_face = create_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, 0x1);
1884 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1885 }
1886 /* for fragface, we get -1 for back and 0 for front. However this is
1887 * the inverse of what nir expects (where ~0 is true).
1888 */
1889 dst[0] = ir3_CMPS_S(b,
1890 ctx->frag_face, 0,
1891 create_immed_typed(b, 0, TYPE_U16), 0);
1892 dst[0]->cat2.condition = IR3_COND_EQ;
1893 break;
1894 case nir_intrinsic_load_local_invocation_id:
1895 if (!ctx->local_invocation_id) {
1896 ctx->local_invocation_id =
1897 create_sysval_input(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID, 0x7);
1898 }
1899 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1900 break;
1901 case nir_intrinsic_load_work_group_id:
1902 if (!ctx->work_group_id) {
1903 ctx->work_group_id =
1904 create_sysval_input(ctx, SYSTEM_VALUE_WORK_GROUP_ID, 0x7);
1905 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1906 }
1907 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1908 break;
1909 case nir_intrinsic_load_num_work_groups:
1910 for (int i = 0; i < dest_components; i++) {
1911 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1912 }
1913 break;
1914 case nir_intrinsic_load_local_group_size:
1915 for (int i = 0; i < dest_components; i++) {
1916 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1917 }
1918 break;
1919 case nir_intrinsic_discard_if:
1920 case nir_intrinsic_discard: {
1921 struct ir3_instruction *cond, *kill;
1922
1923 if (intr->intrinsic == nir_intrinsic_discard_if) {
1924 /* conditional discard: */
1925 src = ir3_get_src(ctx, &intr->src[0]);
1926 cond = src[0];
1927 } else {
1928 /* unconditional discard: */
1929 cond = create_immed(b, 1);
1930 }
1931
1932 /* NOTE: only cmps.*.* can write p0.x: */
1933 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1934 cond->cat2.condition = IR3_COND_NE;
1935
1936 /* condition always goes in predicate register: */
1937 cond->regs[0]->num = regid(REG_P0, 0);
1938 cond->regs[0]->flags &= ~IR3_REG_SSA;
1939
1940 kill = ir3_KILL(b, cond, 0);
1941 kill->regs[1]->num = regid(REG_P0, 0);
1942 array_insert(ctx->ir, ctx->ir->predicates, kill);
1943
1944 array_insert(b, b->keeps, kill);
1945 ctx->so->has_kill = true;
1946
1947 break;
1948 }
1949
1950 case nir_intrinsic_cond_end_ir3: {
1951 struct ir3_instruction *cond, *kill;
1952
1953 src = ir3_get_src(ctx, &intr->src[0]);
1954 cond = src[0];
1955
1956 /* NOTE: only cmps.*.* can write p0.x: */
1957 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1958 cond->cat2.condition = IR3_COND_NE;
1959
1960 /* condition always goes in predicate register: */
1961 cond->regs[0]->num = regid(REG_P0, 0);
1962
1963 kill = ir3_PREDT(b, cond, 0);
1964
1965 kill->barrier_class = IR3_BARRIER_EVERYTHING;
1966 kill->barrier_conflict = IR3_BARRIER_EVERYTHING;
1967
1968 array_insert(ctx->ir, ctx->ir->predicates, kill);
1969 array_insert(b, b->keeps, kill);
1970 break;
1971 }
1972
1973 case nir_intrinsic_load_shared_ir3:
1974 emit_intrinsic_load_shared_ir3(ctx, intr, dst);
1975 break;
1976 case nir_intrinsic_store_shared_ir3:
1977 emit_intrinsic_store_shared_ir3(ctx, intr);
1978 break;
1979 case nir_intrinsic_bindless_resource_ir3:
1980 dst[0] = ir3_get_src(ctx, &intr->src[0])[0];
1981 break;
1982 default:
1983 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1984 nir_intrinsic_infos[intr->intrinsic].name);
1985 break;
1986 }
1987
1988 if (info->has_dest)
1989 ir3_put_dst(ctx, &intr->dest);
1990 }
1991
1992 static void
1993 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1994 {
1995 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1996 instr->def.num_components);
1997
1998 if (instr->def.bit_size == 16) {
1999 for (int i = 0; i < instr->def.num_components; i++)
2000 dst[i] = create_immed_typed(ctx->block,
2001 instr->value[i].u16,
2002 TYPE_U16);
2003 } else {
2004 for (int i = 0; i < instr->def.num_components; i++)
2005 dst[i] = create_immed_typed(ctx->block,
2006 instr->value[i].u32,
2007 TYPE_U32);
2008 }
2009
2010 }
2011
2012 static void
2013 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
2014 {
2015 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
2016 undef->def.num_components);
2017 type_t type = (undef->def.bit_size == 16) ? TYPE_U16 : TYPE_U32;
2018
2019 /* backend doesn't want undefined instructions, so just plug
2020 * in 0.0..
2021 */
2022 for (int i = 0; i < undef->def.num_components; i++)
2023 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
2024 }
2025
2026 /*
2027 * texture fetch/sample instructions:
2028 */
2029
2030 static type_t
2031 get_tex_dest_type(nir_tex_instr *tex)
2032 {
2033 type_t type;
2034
2035 switch (nir_alu_type_get_base_type(tex->dest_type)) {
2036 case nir_type_invalid:
2037 case nir_type_float:
2038 type = nir_dest_bit_size(tex->dest) == 16 ? TYPE_F16 : TYPE_F32;
2039 break;
2040 case nir_type_int:
2041 type = nir_dest_bit_size(tex->dest) == 16 ? TYPE_S16 : TYPE_S32;
2042 break;
2043 case nir_type_uint:
2044 case nir_type_bool:
2045 type = nir_dest_bit_size(tex->dest) == 16 ? TYPE_U16 : TYPE_U32;
2046 break;
2047 default:
2048 unreachable("bad dest_type");
2049 }
2050
2051 return type;
2052 }
2053
2054 static void
2055 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
2056 {
2057 unsigned coords = glsl_get_sampler_dim_coordinate_components(tex->sampler_dim);
2058 unsigned flags = 0;
2059
2060 /* note: would use tex->coord_components.. except txs.. also,
2061 * since array index goes after shadow ref, we don't want to
2062 * count it:
2063 */
2064 if (coords == 3)
2065 flags |= IR3_INSTR_3D;
2066
2067 if (tex->is_shadow && tex->op != nir_texop_lod)
2068 flags |= IR3_INSTR_S;
2069
2070 if (tex->is_array && tex->op != nir_texop_lod)
2071 flags |= IR3_INSTR_A;
2072
2073 *flagsp = flags;
2074 *coordsp = coords;
2075 }
2076
2077 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
2078 * or immediate (in which case it will get lowered later to a non .s2en
2079 * version of the tex instruction which encode tex/samp as immediates:
2080 */
2081 static struct tex_src_info
2082 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
2083 {
2084 struct ir3_block *b = ctx->block;
2085 struct tex_src_info info = { 0 };
2086 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_handle);
2087 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_handle);
2088 struct ir3_instruction *texture, *sampler;
2089
2090 if (texture_idx >= 0 || sampler_idx >= 0) {
2091 /* Bindless case */
2092 info.flags |= IR3_INSTR_B;
2093
2094 /* Gather information required to determine which encoding to
2095 * choose as well as for prefetch.
2096 */
2097 nir_intrinsic_instr *bindless_tex = NULL;
2098 bool tex_const;
2099 if (texture_idx >= 0) {
2100 ctx->so->bindless_tex = true;
2101 bindless_tex = ir3_bindless_resource(tex->src[texture_idx].src);
2102 assert(bindless_tex);
2103 info.tex_base = nir_intrinsic_desc_set(bindless_tex);
2104 tex_const = nir_src_is_const(bindless_tex->src[0]);
2105 if (tex_const)
2106 info.tex_idx = nir_src_as_uint(bindless_tex->src[0]);
2107 } else {
2108 /* To simplify some of the logic below, assume the index is
2109 * constant 0 when it's not enabled.
2110 */
2111 tex_const = true;
2112 info.tex_idx = 0;
2113 }
2114 nir_intrinsic_instr *bindless_samp = NULL;
2115 bool samp_const;
2116 if (sampler_idx >= 0) {
2117 ctx->so->bindless_samp = true;
2118 bindless_samp = ir3_bindless_resource(tex->src[sampler_idx].src);
2119 assert(bindless_samp);
2120 info.samp_base = nir_intrinsic_desc_set(bindless_samp);
2121 samp_const = nir_src_is_const(bindless_samp->src[0]);
2122 if (samp_const)
2123 info.samp_idx = nir_src_as_uint(bindless_samp->src[0]);
2124 } else {
2125 samp_const = true;
2126 info.samp_idx = 0;
2127 }
2128
2129 /* Choose encoding. */
2130 if (tex_const && samp_const && info.tex_idx < 256 && info.samp_idx < 256) {
2131 if (info.tex_idx < 16 && info.samp_idx < 16 &&
2132 (!bindless_tex || !bindless_samp || info.tex_base == info.samp_base)) {
2133 /* Everything fits within the instruction */
2134 info.base = info.tex_base;
2135 info.combined_idx = info.samp_idx | (info.tex_idx << 4);
2136 } else {
2137 info.base = info.tex_base;
2138 info.a1_val = info.tex_idx << 3 | info.samp_base;
2139 info.combined_idx = info.samp_idx;
2140 info.flags |= IR3_INSTR_A1EN;
2141 }
2142 info.samp_tex = NULL;
2143 } else {
2144 info.flags |= IR3_INSTR_S2EN;
2145 /* In the indirect case, we only use a1.x to store the sampler
2146 * base if it differs from the texture base.
2147 */
2148 if (!bindless_tex || !bindless_samp || info.tex_base == info.samp_base) {
2149 info.base = info.tex_base;
2150 } else {
2151 info.base = info.tex_base;
2152 info.a1_val = info.samp_base;
2153 info.flags |= IR3_INSTR_A1EN;
2154 }
2155
2156 /* Note: the indirect source is now a vec2 instead of hvec2, and
2157 * for some reason the texture and sampler are swapped.
2158 */
2159 struct ir3_instruction *texture, *sampler;
2160
2161 if (bindless_tex) {
2162 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
2163 } else {
2164 texture = create_immed(b, 0);
2165 }
2166
2167 if (bindless_samp) {
2168 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
2169 } else {
2170 sampler = create_immed(b, 0);
2171 }
2172 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2173 texture,
2174 sampler,
2175 }, 2);
2176 }
2177 } else {
2178 info.flags |= IR3_INSTR_S2EN;
2179 texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
2180 sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
2181 if (texture_idx >= 0) {
2182 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
2183 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
2184 } else {
2185 /* TODO what to do for dynamic case? I guess we only need the
2186 * max index for astc srgb workaround so maybe not a problem
2187 * to worry about if we don't enable indirect samplers for
2188 * a4xx?
2189 */
2190 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
2191 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
2192 info.tex_idx = tex->texture_index;
2193 }
2194
2195 if (sampler_idx >= 0) {
2196 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
2197 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
2198 } else {
2199 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
2200 info.samp_idx = tex->texture_index;
2201 }
2202
2203 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2204 sampler,
2205 texture,
2206 }, 2);
2207 }
2208
2209 return info;
2210 }
2211
2212 static void
2213 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
2214 {
2215 struct ir3_block *b = ctx->block;
2216 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
2217 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
2218 struct ir3_instruction *lod, *compare, *proj, *sample_index;
2219 struct tex_src_info info = { 0 };
2220 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
2221 unsigned i, coords, flags, ncomp;
2222 unsigned nsrc0 = 0, nsrc1 = 0;
2223 type_t type;
2224 opc_t opc = 0;
2225
2226 ncomp = nir_dest_num_components(tex->dest);
2227
2228 coord = off = ddx = ddy = NULL;
2229 lod = proj = compare = sample_index = NULL;
2230
2231 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
2232
2233 for (unsigned i = 0; i < tex->num_srcs; i++) {
2234 switch (tex->src[i].src_type) {
2235 case nir_tex_src_coord:
2236 coord = ir3_get_src(ctx, &tex->src[i].src);
2237 break;
2238 case nir_tex_src_bias:
2239 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
2240 has_bias = true;
2241 break;
2242 case nir_tex_src_lod:
2243 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
2244 has_lod = true;
2245 break;
2246 case nir_tex_src_comparator: /* shadow comparator */
2247 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
2248 break;
2249 case nir_tex_src_projector:
2250 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
2251 has_proj = true;
2252 break;
2253 case nir_tex_src_offset:
2254 off = ir3_get_src(ctx, &tex->src[i].src);
2255 has_off = true;
2256 break;
2257 case nir_tex_src_ddx:
2258 ddx = ir3_get_src(ctx, &tex->src[i].src);
2259 break;
2260 case nir_tex_src_ddy:
2261 ddy = ir3_get_src(ctx, &tex->src[i].src);
2262 break;
2263 case nir_tex_src_ms_index:
2264 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
2265 break;
2266 case nir_tex_src_texture_offset:
2267 case nir_tex_src_sampler_offset:
2268 case nir_tex_src_texture_handle:
2269 case nir_tex_src_sampler_handle:
2270 /* handled in get_tex_samp_src() */
2271 break;
2272 default:
2273 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
2274 tex->src[i].src_type);
2275 return;
2276 }
2277 }
2278
2279 switch (tex->op) {
2280 case nir_texop_tex_prefetch:
2281 compile_assert(ctx, !has_bias);
2282 compile_assert(ctx, !has_lod);
2283 compile_assert(ctx, !compare);
2284 compile_assert(ctx, !has_proj);
2285 compile_assert(ctx, !has_off);
2286 compile_assert(ctx, !ddx);
2287 compile_assert(ctx, !ddy);
2288 compile_assert(ctx, !sample_index);
2289 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_texture_offset) < 0);
2290 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset) < 0);
2291
2292 if (ctx->so->num_sampler_prefetch < ctx->prefetch_limit) {
2293 opc = OPC_META_TEX_PREFETCH;
2294 ctx->so->num_sampler_prefetch++;
2295 break;
2296 }
2297 /* fallthru */
2298 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
2299 case nir_texop_txb: opc = OPC_SAMB; break;
2300 case nir_texop_txl: opc = OPC_SAML; break;
2301 case nir_texop_txd: opc = OPC_SAMGQ; break;
2302 case nir_texop_txf: opc = OPC_ISAML; break;
2303 case nir_texop_lod: opc = OPC_GETLOD; break;
2304 case nir_texop_tg4:
2305 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2306 * what blob does, seems gather is broken?), and a3xx did
2307 * not support it (but probably could also emulate).
2308 */
2309 switch (tex->component) {
2310 case 0: opc = OPC_GATHER4R; break;
2311 case 1: opc = OPC_GATHER4G; break;
2312 case 2: opc = OPC_GATHER4B; break;
2313 case 3: opc = OPC_GATHER4A; break;
2314 }
2315 break;
2316 case nir_texop_txf_ms_fb:
2317 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
2318 default:
2319 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
2320 return;
2321 }
2322
2323 tex_info(tex, &flags, &coords);
2324
2325 /*
2326 * lay out the first argument in the proper order:
2327 * - actual coordinates first
2328 * - shadow reference
2329 * - array index
2330 * - projection w
2331 * - starting at offset 4, dpdx.xy, dpdy.xy
2332 *
2333 * bias/lod go into the second arg
2334 */
2335
2336 /* insert tex coords: */
2337 for (i = 0; i < coords; i++)
2338 src0[i] = coord[i];
2339
2340 nsrc0 = i;
2341
2342 /* scale up integer coords for TXF based on the LOD */
2343 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
2344 assert(has_lod);
2345 for (i = 0; i < coords; i++)
2346 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
2347 }
2348
2349 if (coords == 1) {
2350 /* hw doesn't do 1d, so we treat it as 2d with
2351 * height of 1, and patch up the y coord.
2352 */
2353 if (is_isam(opc)) {
2354 src0[nsrc0++] = create_immed(b, 0);
2355 } else {
2356 src0[nsrc0++] = create_immed(b, fui(0.5));
2357 }
2358 }
2359
2360 if (tex->is_shadow && tex->op != nir_texop_lod)
2361 src0[nsrc0++] = compare;
2362
2363 if (tex->is_array && tex->op != nir_texop_lod) {
2364 struct ir3_instruction *idx = coord[coords];
2365
2366 /* the array coord for cube arrays needs 0.5 added to it */
2367 if (ctx->compiler->array_index_add_half && !is_isam(opc))
2368 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
2369
2370 src0[nsrc0++] = idx;
2371 }
2372
2373 if (has_proj) {
2374 src0[nsrc0++] = proj;
2375 flags |= IR3_INSTR_P;
2376 }
2377
2378 /* pad to 4, then ddx/ddy: */
2379 if (tex->op == nir_texop_txd) {
2380 while (nsrc0 < 4)
2381 src0[nsrc0++] = create_immed(b, fui(0.0));
2382 for (i = 0; i < coords; i++)
2383 src0[nsrc0++] = ddx[i];
2384 if (coords < 2)
2385 src0[nsrc0++] = create_immed(b, fui(0.0));
2386 for (i = 0; i < coords; i++)
2387 src0[nsrc0++] = ddy[i];
2388 if (coords < 2)
2389 src0[nsrc0++] = create_immed(b, fui(0.0));
2390 }
2391
2392 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2393 * with scaled x coord according to requested sample:
2394 */
2395 if (opc == OPC_ISAMM) {
2396 if (ctx->compiler->txf_ms_with_isaml) {
2397 /* the samples are laid out in x dimension as
2398 * 0 1 2 3
2399 * x_ms = (x << ms) + sample_index;
2400 */
2401 struct ir3_instruction *ms;
2402 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
2403
2404 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
2405 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
2406
2407 opc = OPC_ISAML;
2408 } else {
2409 src0[nsrc0++] = sample_index;
2410 }
2411 }
2412
2413 /*
2414 * second argument (if applicable):
2415 * - offsets
2416 * - lod
2417 * - bias
2418 */
2419 if (has_off | has_lod | has_bias) {
2420 if (has_off) {
2421 unsigned off_coords = coords;
2422 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2423 off_coords--;
2424 for (i = 0; i < off_coords; i++)
2425 src1[nsrc1++] = off[i];
2426 if (off_coords < 2)
2427 src1[nsrc1++] = create_immed(b, fui(0.0));
2428 flags |= IR3_INSTR_O;
2429 }
2430
2431 if (has_lod | has_bias)
2432 src1[nsrc1++] = lod;
2433 }
2434
2435 type = get_tex_dest_type(tex);
2436
2437 if (opc == OPC_GETLOD)
2438 type = TYPE_S32;
2439
2440
2441 if (tex->op == nir_texop_txf_ms_fb) {
2442 /* only expect a single txf_ms_fb per shader: */
2443 compile_assert(ctx, !ctx->so->fb_read);
2444 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
2445
2446 ctx->so->fb_read = true;
2447 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2448 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2449 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2450 }, 2);
2451 info.flags = IR3_INSTR_S2EN;
2452
2453 ctx->so->num_samp++;
2454 } else {
2455 info = get_tex_samp_tex_src(ctx, tex);
2456 }
2457
2458 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
2459 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
2460
2461 if (opc == OPC_META_TEX_PREFETCH) {
2462 int idx = nir_tex_instr_src_index(tex, nir_tex_src_coord);
2463
2464 compile_assert(ctx, tex->src[idx].src.is_ssa);
2465
2466 sam = ir3_META_TEX_PREFETCH(b);
2467 __ssa_dst(sam)->wrmask = MASK(ncomp); /* dst */
2468 __ssa_src(sam, get_barycentric(ctx, IJ_PERSP_PIXEL), 0);
2469 sam->prefetch.input_offset =
2470 ir3_nir_coord_offset(tex->src[idx].src.ssa);
2471 /* make sure not to add irrelevant flags like S2EN */
2472 sam->flags = flags | (info.flags & IR3_INSTR_B);
2473 sam->prefetch.tex = info.tex_idx;
2474 sam->prefetch.samp = info.samp_idx;
2475 sam->prefetch.tex_base = info.tex_base;
2476 sam->prefetch.samp_base = info.samp_base;
2477 } else {
2478 info.flags |= flags;
2479 sam = emit_sam(ctx, opc, info, type, MASK(ncomp), col0, col1);
2480 }
2481
2482 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
2483 assert(opc != OPC_META_TEX_PREFETCH);
2484
2485 /* only need first 3 components: */
2486 sam->regs[0]->wrmask = 0x7;
2487 ir3_split_dest(b, dst, sam, 0, 3);
2488
2489 /* we need to sample the alpha separately with a non-ASTC
2490 * texture state:
2491 */
2492 sam = ir3_SAM(b, opc, type, 0b1000, flags | info.flags,
2493 info.samp_tex, col0, col1);
2494
2495 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
2496
2497 /* fixup .w component: */
2498 ir3_split_dest(b, &dst[3], sam, 3, 1);
2499 } else {
2500 /* normal (non-workaround) case: */
2501 ir3_split_dest(b, dst, sam, 0, ncomp);
2502 }
2503
2504 /* GETLOD returns results in 4.8 fixed point */
2505 if (opc == OPC_GETLOD) {
2506 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
2507
2508 compile_assert(ctx, tex->dest_type == nir_type_float);
2509 for (i = 0; i < 2; i++) {
2510 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_S32, TYPE_F32), 0,
2511 factor, 0);
2512 }
2513 }
2514
2515 ir3_put_dst(ctx, &tex->dest);
2516 }
2517
2518 static void
2519 emit_tex_info(struct ir3_context *ctx, nir_tex_instr *tex, unsigned idx)
2520 {
2521 struct ir3_block *b = ctx->block;
2522 struct ir3_instruction **dst, *sam;
2523 type_t dst_type = get_tex_dest_type(tex);
2524 struct tex_src_info info = get_tex_samp_tex_src(ctx, tex);
2525
2526 dst = ir3_get_dst(ctx, &tex->dest, 1);
2527
2528 sam = emit_sam(ctx, OPC_GETINFO, info, dst_type, 1 << idx, NULL, NULL);
2529
2530 /* even though there is only one component, since it ends
2531 * up in .y/.z/.w rather than .x, we need a split_dest()
2532 */
2533 ir3_split_dest(b, dst, sam, idx, 1);
2534
2535 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2536 * the value in TEX_CONST_0 is zero-based.
2537 */
2538 if (ctx->compiler->levels_add_one)
2539 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2540
2541 ir3_put_dst(ctx, &tex->dest);
2542 }
2543
2544 static void
2545 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2546 {
2547 struct ir3_block *b = ctx->block;
2548 struct ir3_instruction **dst, *sam;
2549 struct ir3_instruction *lod;
2550 unsigned flags, coords;
2551 type_t dst_type = get_tex_dest_type(tex);
2552 struct tex_src_info info = get_tex_samp_tex_src(ctx, tex);
2553
2554 tex_info(tex, &flags, &coords);
2555 info.flags |= flags;
2556
2557 /* Actually we want the number of dimensions, not coordinates. This
2558 * distinction only matters for cubes.
2559 */
2560 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2561 coords = 2;
2562
2563 dst = ir3_get_dst(ctx, &tex->dest, 4);
2564
2565 int lod_idx = nir_tex_instr_src_index(tex, nir_tex_src_lod);
2566 compile_assert(ctx, lod_idx >= 0);
2567
2568 lod = ir3_get_src(ctx, &tex->src[lod_idx].src)[0];
2569
2570 sam = emit_sam(ctx, OPC_GETSIZE, info, dst_type, 0b1111, lod, NULL);
2571 ir3_split_dest(b, dst, sam, 0, 4);
2572
2573 /* Array size actually ends up in .w rather than .z. This doesn't
2574 * matter for miplevel 0, but for higher mips the value in z is
2575 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2576 * returned, which means that we have to add 1 to it for arrays.
2577 */
2578 if (tex->is_array) {
2579 if (ctx->compiler->levels_add_one) {
2580 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2581 } else {
2582 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2583 }
2584 }
2585
2586 ir3_put_dst(ctx, &tex->dest);
2587 }
2588
2589 static void
2590 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2591 {
2592 switch (jump->type) {
2593 case nir_jump_break:
2594 case nir_jump_continue:
2595 case nir_jump_return:
2596 /* I *think* we can simply just ignore this, and use the
2597 * successor block link to figure out where we need to
2598 * jump to for break/continue
2599 */
2600 break;
2601 default:
2602 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2603 break;
2604 }
2605 }
2606
2607 static void
2608 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2609 {
2610 switch (instr->type) {
2611 case nir_instr_type_alu:
2612 emit_alu(ctx, nir_instr_as_alu(instr));
2613 break;
2614 case nir_instr_type_deref:
2615 /* ignored, handled as part of the intrinsic they are src to */
2616 break;
2617 case nir_instr_type_intrinsic:
2618 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2619 break;
2620 case nir_instr_type_load_const:
2621 emit_load_const(ctx, nir_instr_as_load_const(instr));
2622 break;
2623 case nir_instr_type_ssa_undef:
2624 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2625 break;
2626 case nir_instr_type_tex: {
2627 nir_tex_instr *tex = nir_instr_as_tex(instr);
2628 /* couple tex instructions get special-cased:
2629 */
2630 switch (tex->op) {
2631 case nir_texop_txs:
2632 emit_tex_txs(ctx, tex);
2633 break;
2634 case nir_texop_query_levels:
2635 emit_tex_info(ctx, tex, 2);
2636 break;
2637 case nir_texop_texture_samples:
2638 emit_tex_info(ctx, tex, 3);
2639 break;
2640 default:
2641 emit_tex(ctx, tex);
2642 break;
2643 }
2644 break;
2645 }
2646 case nir_instr_type_jump:
2647 emit_jump(ctx, nir_instr_as_jump(instr));
2648 break;
2649 case nir_instr_type_phi:
2650 /* we have converted phi webs to regs in NIR by now */
2651 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2652 break;
2653 case nir_instr_type_call:
2654 case nir_instr_type_parallel_copy:
2655 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2656 break;
2657 }
2658 }
2659
2660 static struct ir3_block *
2661 get_block(struct ir3_context *ctx, const nir_block *nblock)
2662 {
2663 struct ir3_block *block;
2664 struct hash_entry *hentry;
2665
2666 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2667 if (hentry)
2668 return hentry->data;
2669
2670 block = ir3_block_create(ctx->ir);
2671 block->nblock = nblock;
2672 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2673
2674 set_foreach(nblock->predecessors, sentry) {
2675 _mesa_set_add(block->predecessors, get_block(ctx, sentry->key));
2676 }
2677
2678 return block;
2679 }
2680
2681 static void
2682 emit_block(struct ir3_context *ctx, nir_block *nblock)
2683 {
2684 struct ir3_block *block = get_block(ctx, nblock);
2685
2686 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2687 if (nblock->successors[i]) {
2688 block->successors[i] =
2689 get_block(ctx, nblock->successors[i]);
2690 }
2691 }
2692
2693 ctx->block = block;
2694 list_addtail(&block->node, &ctx->ir->block_list);
2695
2696 /* re-emit addr register in each block if needed: */
2697 for (int i = 0; i < ARRAY_SIZE(ctx->addr0_ht); i++) {
2698 _mesa_hash_table_destroy(ctx->addr0_ht[i], NULL);
2699 ctx->addr0_ht[i] = NULL;
2700 }
2701
2702 _mesa_hash_table_u64_destroy(ctx->addr1_ht, NULL);
2703 ctx->addr1_ht = NULL;
2704
2705 nir_foreach_instr (instr, nblock) {
2706 ctx->cur_instr = instr;
2707 emit_instr(ctx, instr);
2708 ctx->cur_instr = NULL;
2709 if (ctx->error)
2710 return;
2711 }
2712
2713 _mesa_hash_table_clear(ctx->sel_cond_conversions, NULL);
2714 }
2715
2716 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2717
2718 static void
2719 emit_if(struct ir3_context *ctx, nir_if *nif)
2720 {
2721 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2722
2723 ctx->block->condition = ir3_get_predicate(ctx, condition);
2724
2725 emit_cf_list(ctx, &nif->then_list);
2726 emit_cf_list(ctx, &nif->else_list);
2727 }
2728
2729 static void
2730 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2731 {
2732 emit_cf_list(ctx, &nloop->body);
2733 ctx->so->loops++;
2734 }
2735
2736 static void
2737 stack_push(struct ir3_context *ctx)
2738 {
2739 ctx->stack++;
2740 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2741 }
2742
2743 static void
2744 stack_pop(struct ir3_context *ctx)
2745 {
2746 compile_assert(ctx, ctx->stack > 0);
2747 ctx->stack--;
2748 }
2749
2750 static void
2751 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2752 {
2753 foreach_list_typed (nir_cf_node, node, node, list) {
2754 switch (node->type) {
2755 case nir_cf_node_block:
2756 emit_block(ctx, nir_cf_node_as_block(node));
2757 break;
2758 case nir_cf_node_if:
2759 stack_push(ctx);
2760 emit_if(ctx, nir_cf_node_as_if(node));
2761 stack_pop(ctx);
2762 break;
2763 case nir_cf_node_loop:
2764 stack_push(ctx);
2765 emit_loop(ctx, nir_cf_node_as_loop(node));
2766 stack_pop(ctx);
2767 break;
2768 case nir_cf_node_function:
2769 ir3_context_error(ctx, "TODO\n");
2770 break;
2771 }
2772 }
2773 }
2774
2775 /* emit stream-out code. At this point, the current block is the original
2776 * (nir) end block, and nir ensures that all flow control paths terminate
2777 * into the end block. We re-purpose the original end block to generate
2778 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2779 * block holding stream-out write instructions, followed by the new end
2780 * block:
2781 *
2782 * blockOrigEnd {
2783 * p0.x = (vtxcnt < maxvtxcnt)
2784 * // succs: blockStreamOut, blockNewEnd
2785 * }
2786 * blockStreamOut {
2787 * // preds: blockOrigEnd
2788 * ... stream-out instructions ...
2789 * // succs: blockNewEnd
2790 * }
2791 * blockNewEnd {
2792 * // preds: blockOrigEnd, blockStreamOut
2793 * }
2794 */
2795 static void
2796 emit_stream_out(struct ir3_context *ctx)
2797 {
2798 struct ir3 *ir = ctx->ir;
2799 struct ir3_stream_output_info *strmout =
2800 &ctx->so->shader->stream_output;
2801 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2802 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2803 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2804
2805 /* create vtxcnt input in input block at top of shader,
2806 * so that it is seen as live over the entire duration
2807 * of the shader:
2808 */
2809 vtxcnt = create_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, 0x1);
2810 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2811
2812 /* at this point, we are at the original 'end' block,
2813 * re-purpose this block to stream-out condition, then
2814 * append stream-out block and new-end block
2815 */
2816 orig_end_block = ctx->block;
2817
2818 // maybe w/ store_global intrinsic, we could do this
2819 // stuff in nir->nir pass
2820
2821 stream_out_block = ir3_block_create(ir);
2822 list_addtail(&stream_out_block->node, &ir->block_list);
2823
2824 new_end_block = ir3_block_create(ir);
2825 list_addtail(&new_end_block->node, &ir->block_list);
2826
2827 orig_end_block->successors[0] = stream_out_block;
2828 orig_end_block->successors[1] = new_end_block;
2829
2830 stream_out_block->successors[0] = new_end_block;
2831 _mesa_set_add(stream_out_block->predecessors, orig_end_block);
2832
2833 _mesa_set_add(new_end_block->predecessors, orig_end_block);
2834 _mesa_set_add(new_end_block->predecessors, stream_out_block);
2835
2836 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2837 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2838 cond->regs[0]->num = regid(REG_P0, 0);
2839 cond->regs[0]->flags &= ~IR3_REG_SSA;
2840 cond->cat2.condition = IR3_COND_LT;
2841
2842 /* condition goes on previous block to the conditional,
2843 * since it is used to pick which of the two successor
2844 * paths to take:
2845 */
2846 orig_end_block->condition = cond;
2847
2848 /* switch to stream_out_block to generate the stream-out
2849 * instructions:
2850 */
2851 ctx->block = stream_out_block;
2852
2853 /* Calculate base addresses based on vtxcnt. Instructions
2854 * generated for bases not used in following loop will be
2855 * stripped out in the backend.
2856 */
2857 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2858 const struct ir3_const_state *const_state =
2859 ir3_const_state(ctx->so);
2860 unsigned stride = strmout->stride[i];
2861 struct ir3_instruction *base, *off;
2862
2863 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
2864
2865 /* 24-bit should be enough: */
2866 off = ir3_MUL_U24(ctx->block, vtxcnt, 0,
2867 create_immed(ctx->block, stride * 4), 0);
2868
2869 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2870 }
2871
2872 /* Generate the per-output store instructions: */
2873 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2874 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2875 unsigned c = j + strmout->output[i].start_component;
2876 struct ir3_instruction *base, *out, *stg;
2877
2878 base = bases[strmout->output[i].output_buffer];
2879 out = ctx->outputs[regid(strmout->output[i].register_index, c)];
2880
2881 stg = ir3_STG(ctx->block, base, 0, out, 0,
2882 create_immed(ctx->block, 1), 0);
2883 stg->cat6.type = TYPE_U32;
2884 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2885
2886 array_insert(ctx->block, ctx->block->keeps, stg);
2887 }
2888 }
2889
2890 /* and finally switch to the new_end_block: */
2891 ctx->block = new_end_block;
2892 }
2893
2894 static void
2895 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2896 {
2897 nir_metadata_require(impl, nir_metadata_block_index);
2898
2899 compile_assert(ctx, ctx->stack == 0);
2900
2901 emit_cf_list(ctx, &impl->body);
2902 emit_block(ctx, impl->end_block);
2903
2904 compile_assert(ctx, ctx->stack == 0);
2905
2906 /* at this point, we should have a single empty block,
2907 * into which we emit the 'end' instruction.
2908 */
2909 compile_assert(ctx, list_is_empty(&ctx->block->instr_list));
2910
2911 /* If stream-out (aka transform-feedback) enabled, emit the
2912 * stream-out instructions, followed by a new empty block (into
2913 * which the 'end' instruction lands).
2914 *
2915 * NOTE: it is done in this order, rather than inserting before
2916 * we emit end_block, because NIR guarantees that all blocks
2917 * flow into end_block, and that end_block has no successors.
2918 * So by re-purposing end_block as the first block of stream-
2919 * out, we guarantee that all exit paths flow into the stream-
2920 * out instructions.
2921 */
2922 if ((ctx->compiler->gpu_id < 500) &&
2923 (ctx->so->shader->stream_output.num_outputs > 0) &&
2924 !ctx->so->binning_pass) {
2925 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2926 emit_stream_out(ctx);
2927 }
2928
2929 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2930 * NOP and has an epilogue that writes the VS outputs to local storage, to
2931 * be read by the HS. Then it resets execution mask (chmask) and chains
2932 * to the next shader (chsh).
2933 */
2934 if ((ctx->so->type == MESA_SHADER_VERTEX &&
2935 (ctx->so->key.has_gs || ctx->so->key.tessellation)) ||
2936 (ctx->so->type == MESA_SHADER_TESS_EVAL && ctx->so->key.has_gs)) {
2937 struct ir3_instruction *chmask =
2938 ir3_CHMASK(ctx->block);
2939 chmask->barrier_class = IR3_BARRIER_EVERYTHING;
2940 chmask->barrier_conflict = IR3_BARRIER_EVERYTHING;
2941
2942 struct ir3_instruction *chsh =
2943 ir3_CHSH(ctx->block);
2944 chsh->barrier_class = IR3_BARRIER_EVERYTHING;
2945 chsh->barrier_conflict = IR3_BARRIER_EVERYTHING;
2946 } else {
2947 ir3_END(ctx->block);
2948 }
2949 }
2950
2951 static void
2952 setup_input(struct ir3_context *ctx, nir_variable *in)
2953 {
2954 struct ir3_shader_variant *so = ctx->so;
2955 unsigned ncomp = glsl_get_components(in->type);
2956 unsigned n = in->data.driver_location;
2957 unsigned frac = in->data.location_frac;
2958 unsigned slot = in->data.location;
2959
2960 /* Inputs are loaded using ldlw or ldg for these stages. */
2961 if (ctx->so->type == MESA_SHADER_TESS_CTRL ||
2962 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2963 ctx->so->type == MESA_SHADER_GEOMETRY)
2964 return;
2965
2966 /* skip unread inputs, we could end up with (for example), unsplit
2967 * matrix/etc inputs in the case they are not read, so just silently
2968 * skip these.
2969 */
2970 if (ncomp > 4)
2971 return;
2972
2973 so->inputs[n].slot = slot;
2974 so->inputs[n].compmask |= (1 << (ncomp + frac)) - 1;
2975 so->inputs_count = MAX2(so->inputs_count, n + 1);
2976 so->inputs[n].interpolate = in->data.interpolation;
2977
2978 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2979
2980 /* if any varyings have 'sample' qualifer, that triggers us
2981 * to run in per-sample mode:
2982 */
2983 so->per_samp |= in->data.sample;
2984
2985 for (int i = 0; i < ncomp; i++) {
2986 struct ir3_instruction *instr = NULL;
2987 unsigned idx = (n * 4) + i + frac;
2988
2989 if (slot == VARYING_SLOT_POS) {
2990 ir3_context_error(ctx, "fragcoord should be a sysval!\n");
2991 } else {
2992 /* detect the special case for front/back colors where
2993 * we need to do flat vs smooth shading depending on
2994 * rast state:
2995 */
2996 if (in->data.interpolation == INTERP_MODE_NONE) {
2997 switch (slot) {
2998 case VARYING_SLOT_COL0:
2999 case VARYING_SLOT_COL1:
3000 case VARYING_SLOT_BFC0:
3001 case VARYING_SLOT_BFC1:
3002 so->inputs[n].rasterflat = true;
3003 break;
3004 default:
3005 break;
3006 }
3007 }
3008
3009 if (ctx->compiler->flat_bypass) {
3010 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
3011 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
3012 so->inputs[n].use_ldlv = true;
3013 }
3014
3015 so->inputs[n].bary = true;
3016
3017 instr = create_frag_input(ctx, so->inputs[n].use_ldlv, idx);
3018 }
3019
3020 compile_assert(ctx, idx < ctx->ninputs);
3021
3022 ctx->inputs[idx] = instr;
3023 }
3024 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
3025 struct ir3_instruction *input = NULL;
3026 struct ir3_instruction *components[4];
3027 /* input as setup as frac=0 with "ncomp + frac" components,
3028 * this avoids getting a sparse writemask
3029 */
3030 unsigned mask = (1 << (ncomp + frac)) - 1;
3031
3032 foreach_input (in, ctx->ir) {
3033 if (in->input.inidx == n) {
3034 input = in;
3035 break;
3036 }
3037 }
3038
3039 if (!input) {
3040 input = create_input(ctx, mask);
3041 input->input.inidx = n;
3042 } else {
3043 /* For aliased inputs, just append to the wrmask.. ie. if we
3044 * first see a vec2 index at slot N, and then later a vec4,
3045 * the wrmask of the resulting overlapped vec2 and vec4 is 0xf
3046 *
3047 * If the new input that aliases a previously processed input
3048 * sets no new bits, then just bail as there is nothing to see
3049 * here.
3050 */
3051 if (!(mask & ~input->regs[0]->wrmask))
3052 return;
3053 input->regs[0]->wrmask |= mask;
3054 }
3055
3056 ir3_split_dest(ctx->block, components, input, 0, ncomp + frac);
3057
3058 for (int i = 0; i < ncomp + frac; i++) {
3059 unsigned idx = (n * 4) + i;
3060 compile_assert(ctx, idx < ctx->ninputs);
3061
3062 /* With aliased inputs, since we add to the wrmask above, we
3063 * can end up with stale meta:split instructions in the inputs
3064 * table. This is basically harmless, since eventually they
3065 * will get swept away by DCE, but the mismatch wrmask (since
3066 * they would be using the previous wrmask before we OR'd in
3067 * more bits) angers ir3_validate. So just preemptively clean
3068 * them up. See:
3069 *
3070 * dEQP-GLES2.functional.attribute_location.bind_aliasing.cond_vec2
3071 *
3072 * Note however that split_dest() will return the src if it is
3073 * scalar, so the previous ctx->inputs[idx] could be the input
3074 * itself (which we don't want to remove)
3075 */
3076 if (ctx->inputs[idx] && (ctx->inputs[idx] != input)) {
3077 list_del(&ctx->inputs[idx]->node);
3078 }
3079
3080 ctx->inputs[idx] = components[i];
3081 }
3082 } else {
3083 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
3084 }
3085
3086 /* note: this can be wrong for sparse vertex inputs, this happens with
3087 * vulkan, only a3xx/a4xx use this value for VS, so it shouldn't matter
3088 */
3089 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
3090 so->total_in += ncomp;
3091 }
3092 }
3093
3094 /* Initially we assign non-packed inloc's for varyings, as we don't really
3095 * know up-front which components will be unused. After all the compilation
3096 * stages we scan the shader to see which components are actually used, and
3097 * re-pack the inlocs to eliminate unneeded varyings.
3098 */
3099 static void
3100 pack_inlocs(struct ir3_context *ctx)
3101 {
3102 struct ir3_shader_variant *so = ctx->so;
3103 uint8_t used_components[so->inputs_count];
3104
3105 memset(used_components, 0, sizeof(used_components));
3106
3107 /*
3108 * First Step: scan shader to find which bary.f/ldlv remain:
3109 */
3110
3111 foreach_block (block, &ctx->ir->block_list) {
3112 foreach_instr (instr, &block->instr_list) {
3113 if (is_input(instr)) {
3114 unsigned inloc = instr->regs[1]->iim_val;
3115 unsigned i = inloc / 4;
3116 unsigned j = inloc % 4;
3117
3118 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
3119 compile_assert(ctx, i < so->inputs_count);
3120
3121 used_components[i] |= 1 << j;
3122 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
3123 for (int n = 0; n < 2; n++) {
3124 unsigned inloc = instr->prefetch.input_offset + n;
3125 unsigned i = inloc / 4;
3126 unsigned j = inloc % 4;
3127
3128 compile_assert(ctx, i < so->inputs_count);
3129
3130 used_components[i] |= 1 << j;
3131 }
3132 }
3133 }
3134 }
3135
3136 /*
3137 * Second Step: reassign varying inloc/slots:
3138 */
3139
3140 unsigned actual_in = 0;
3141 unsigned inloc = 0;
3142
3143 for (unsigned i = 0; i < so->inputs_count; i++) {
3144 unsigned compmask = 0, maxcomp = 0;
3145
3146 so->inputs[i].inloc = inloc;
3147 so->inputs[i].bary = false;
3148
3149 for (unsigned j = 0; j < 4; j++) {
3150 if (!(used_components[i] & (1 << j)))
3151 continue;
3152
3153 compmask |= (1 << j);
3154 actual_in++;
3155 maxcomp = j + 1;
3156
3157 /* at this point, since used_components[i] mask is only
3158 * considering varyings (ie. not sysvals) we know this
3159 * is a varying:
3160 */
3161 so->inputs[i].bary = true;
3162 }
3163
3164 if (so->inputs[i].bary) {
3165 so->varying_in++;
3166 so->inputs[i].compmask = (1 << maxcomp) - 1;
3167 inloc += maxcomp;
3168 }
3169 }
3170
3171 /*
3172 * Third Step: reassign packed inloc's:
3173 */
3174
3175 foreach_block (block, &ctx->ir->block_list) {
3176 foreach_instr (instr, &block->instr_list) {
3177 if (is_input(instr)) {
3178 unsigned inloc = instr->regs[1]->iim_val;
3179 unsigned i = inloc / 4;
3180 unsigned j = inloc % 4;
3181
3182 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
3183 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
3184 unsigned i = instr->prefetch.input_offset / 4;
3185 unsigned j = instr->prefetch.input_offset % 4;
3186 instr->prefetch.input_offset = so->inputs[i].inloc + j;
3187 }
3188 }
3189 }
3190 }
3191
3192 static void
3193 setup_output(struct ir3_context *ctx, nir_variable *out)
3194 {
3195 struct ir3_shader_variant *so = ctx->so;
3196 unsigned slots = glsl_count_vec4_slots(out->type, false, false);
3197 unsigned ncomp = glsl_get_components(glsl_without_array(out->type));
3198 unsigned n = out->data.driver_location;
3199 unsigned frac = out->data.location_frac;
3200 unsigned slot = out->data.location;
3201
3202 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3203 switch (slot) {
3204 case FRAG_RESULT_DEPTH:
3205 so->writes_pos = true;
3206 break;
3207 case FRAG_RESULT_COLOR:
3208 so->color0_mrt = 1;
3209 break;
3210 case FRAG_RESULT_SAMPLE_MASK:
3211 so->writes_smask = true;
3212 break;
3213 case FRAG_RESULT_STENCIL:
3214 so->writes_stencilref = true;
3215 break;
3216 default:
3217 slot += out->data.index; /* For dual-src blend */
3218 if (slot >= FRAG_RESULT_DATA0)
3219 break;
3220 ir3_context_error(ctx, "unknown FS output name: %s\n",
3221 gl_frag_result_name(slot));
3222 }
3223 } else if (ctx->so->type == MESA_SHADER_VERTEX ||
3224 ctx->so->type == MESA_SHADER_TESS_EVAL ||
3225 ctx->so->type == MESA_SHADER_GEOMETRY) {
3226 switch (slot) {
3227 case VARYING_SLOT_POS:
3228 so->writes_pos = true;
3229 break;
3230 case VARYING_SLOT_PSIZ:
3231 so->writes_psize = true;
3232 break;
3233 case VARYING_SLOT_PRIMITIVE_ID:
3234 case VARYING_SLOT_LAYER:
3235 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
3236 debug_assert(ctx->so->type == MESA_SHADER_GEOMETRY);
3237 /* fall through */
3238 case VARYING_SLOT_COL0:
3239 case VARYING_SLOT_COL1:
3240 case VARYING_SLOT_BFC0:
3241 case VARYING_SLOT_BFC1:
3242 case VARYING_SLOT_FOGC:
3243 case VARYING_SLOT_CLIP_DIST0:
3244 case VARYING_SLOT_CLIP_DIST1:
3245 case VARYING_SLOT_CLIP_VERTEX:
3246 break;
3247 default:
3248 if (slot >= VARYING_SLOT_VAR0)
3249 break;
3250 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
3251 break;
3252 ir3_context_error(ctx, "unknown %s shader output name: %s\n",
3253 _mesa_shader_stage_to_string(ctx->so->type),
3254 gl_varying_slot_name(slot));
3255 }
3256 } else if (ctx->so->type == MESA_SHADER_TESS_CTRL) {
3257 /* output lowered to buffer writes. */
3258 return;
3259 } else {
3260 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
3261 }
3262
3263
3264 so->outputs_count = out->data.driver_location + slots;
3265 compile_assert(ctx, so->outputs_count < ARRAY_SIZE(so->outputs));
3266
3267 for (int i = 0; i < slots; i++) {
3268 int slot_base = n + i;
3269 so->outputs[slot_base].slot = slot + i;
3270
3271 for (int i = 0; i < ncomp; i++) {
3272 unsigned idx = (slot_base * 4) + i + frac;
3273 compile_assert(ctx, idx < ctx->noutputs);
3274 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
3275 }
3276
3277 /* if varying packing doesn't happen, we could end up in a situation
3278 * with "holes" in the output, and since the per-generation code that
3279 * sets up varying linkage registers doesn't expect to have more than
3280 * one varying per vec4 slot, pad the holes.
3281 *
3282 * Note that this should probably generate a performance warning of
3283 * some sort.
3284 */
3285 for (int i = 0; i < frac; i++) {
3286 unsigned idx = (slot_base * 4) + i;
3287 if (!ctx->outputs[idx]) {
3288 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
3289 }
3290 }
3291 }
3292 }
3293
3294 static void
3295 emit_instructions(struct ir3_context *ctx)
3296 {
3297 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
3298
3299 ctx->ninputs = ctx->s->num_inputs * 4;
3300 ctx->noutputs = ctx->s->num_outputs * 4;
3301 ctx->inputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->ninputs);
3302 ctx->outputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->noutputs);
3303
3304 ctx->ir = ir3_create(ctx->compiler, ctx->so);
3305
3306 /* Create inputs in first block: */
3307 ctx->block = get_block(ctx, nir_start_block(fxn));
3308 ctx->in_block = ctx->block;
3309
3310 /* for fragment shader, the vcoord input register is used as the
3311 * base for bary.f varying fetch instrs:
3312 *
3313 * TODO defer creating ctx->ij_pixel and corresponding sysvals
3314 * until emit_intrinsic when we know they are actually needed.
3315 * For now, we defer creating ctx->ij_centroid, etc, since we
3316 * only need ij_pixel for "old style" varying inputs (ie.
3317 * tgsi_to_nir)
3318 */
3319 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3320 ctx->ij[IJ_PERSP_PIXEL] = create_input(ctx, 0x3);
3321 }
3322
3323 /* Setup inputs: */
3324 nir_foreach_shader_in_variable (var, ctx->s) {
3325 setup_input(ctx, var);
3326 }
3327
3328 /* Defer add_sysval_input() stuff until after setup_inputs(),
3329 * because sysvals need to be appended after varyings:
3330 */
3331 if (ctx->ij[IJ_PERSP_PIXEL]) {
3332 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL,
3333 0x3, ctx->ij[IJ_PERSP_PIXEL]);
3334 }
3335
3336
3337 /* Tesselation shaders always need primitive ID for indexing the
3338 * BO. Geometry shaders don't always need it but when they do it has be
3339 * delivered and unclobbered in the VS. To make things easy, we always
3340 * make room for it in VS/DS.
3341 */
3342 bool has_tess = ctx->so->key.tessellation != IR3_TESS_NONE;
3343 bool has_gs = ctx->so->key.has_gs;
3344 switch (ctx->so->type) {
3345 case MESA_SHADER_VERTEX:
3346 if (has_tess) {
3347 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3348 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3349 } else if (has_gs) {
3350 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3351 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3352 }
3353 break;
3354 case MESA_SHADER_TESS_CTRL:
3355 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3356 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3357 break;
3358 case MESA_SHADER_TESS_EVAL:
3359 if (has_gs)
3360 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3361 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3362 break;
3363 case MESA_SHADER_GEOMETRY:
3364 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3365 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3366 break;
3367 default:
3368 break;
3369 }
3370
3371 /* Setup outputs: */
3372 nir_foreach_shader_out_variable (var, ctx->s) {
3373 setup_output(ctx, var);
3374 }
3375
3376 /* Find # of samplers. Just assume that we'll be reading from images.. if
3377 * it is write-only we don't have to count it, but after lowering derefs
3378 * is too late to compact indices for that.
3379 */
3380 ctx->so->num_samp = util_last_bit(ctx->s->info.textures_used) + ctx->s->info.num_images;
3381
3382 /* NOTE: need to do something more clever when we support >1 fxn */
3383 nir_foreach_register (reg, &fxn->registers) {
3384 ir3_declare_array(ctx, reg);
3385 }
3386 /* And emit the body: */
3387 ctx->impl = fxn;
3388 emit_function(ctx, fxn);
3389 }
3390
3391 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3392 * need to assign the tex state indexes for these after we know the
3393 * max tex index.
3394 */
3395 static void
3396 fixup_astc_srgb(struct ir3_context *ctx)
3397 {
3398 struct ir3_shader_variant *so = ctx->so;
3399 /* indexed by original tex idx, value is newly assigned alpha sampler
3400 * state tex idx. Zero is invalid since there is at least one sampler
3401 * if we get here.
3402 */
3403 unsigned alt_tex_state[16] = {0};
3404 unsigned tex_idx = ctx->max_texture_index + 1;
3405 unsigned idx = 0;
3406
3407 so->astc_srgb.base = tex_idx;
3408
3409 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
3410 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
3411
3412 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
3413
3414 if (alt_tex_state[sam->cat5.tex] == 0) {
3415 /* assign new alternate/alpha tex state slot: */
3416 alt_tex_state[sam->cat5.tex] = tex_idx++;
3417 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
3418 so->astc_srgb.count++;
3419 }
3420
3421 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
3422 }
3423 }
3424
3425 static void
3426 fixup_binning_pass(struct ir3_context *ctx)
3427 {
3428 struct ir3_shader_variant *so = ctx->so;
3429 struct ir3 *ir = ctx->ir;
3430 unsigned i, j;
3431
3432 /* first pass, remove unused outputs from the IR level outputs: */
3433 for (i = 0, j = 0; i < ir->outputs_count; i++) {
3434 struct ir3_instruction *out = ir->outputs[i];
3435 assert(out->opc == OPC_META_COLLECT);
3436 unsigned outidx = out->collect.outidx;
3437 unsigned slot = so->outputs[outidx].slot;
3438
3439 /* throw away everything but first position/psize */
3440 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3441 ir->outputs[j] = ir->outputs[i];
3442 j++;
3443 }
3444 }
3445 ir->outputs_count = j;
3446
3447 /* second pass, cleanup the unused slots in ir3_shader_variant::outputs
3448 * table:
3449 */
3450 for (i = 0, j = 0; i < so->outputs_count; i++) {
3451 unsigned slot = so->outputs[i].slot;
3452
3453 /* throw away everything but first position/psize */
3454 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3455 so->outputs[j] = so->outputs[i];
3456
3457 /* fixup outidx to point to new output table entry: */
3458 foreach_output (out, ir) {
3459 if (out->collect.outidx == i) {
3460 out->collect.outidx = j;
3461 break;
3462 }
3463 }
3464
3465 j++;
3466 }
3467 }
3468 so->outputs_count = j;
3469 }
3470
3471 static void
3472 collect_tex_prefetches(struct ir3_context *ctx, struct ir3 *ir)
3473 {
3474 unsigned idx = 0;
3475
3476 /* Collect sampling instructions eligible for pre-dispatch. */
3477 foreach_block (block, &ir->block_list) {
3478 foreach_instr_safe (instr, &block->instr_list) {
3479 if (instr->opc == OPC_META_TEX_PREFETCH) {
3480 assert(idx < ARRAY_SIZE(ctx->so->sampler_prefetch));
3481 struct ir3_sampler_prefetch *fetch =
3482 &ctx->so->sampler_prefetch[idx];
3483 idx++;
3484
3485 if (instr->flags & IR3_INSTR_B) {
3486 fetch->cmd = IR3_SAMPLER_BINDLESS_PREFETCH_CMD;
3487 /* In bindless mode, the index is actually the base */
3488 fetch->tex_id = instr->prefetch.tex_base;
3489 fetch->samp_id = instr->prefetch.samp_base;
3490 fetch->tex_bindless_id = instr->prefetch.tex;
3491 fetch->samp_bindless_id = instr->prefetch.samp;
3492 } else {
3493 fetch->cmd = IR3_SAMPLER_PREFETCH_CMD;
3494 fetch->tex_id = instr->prefetch.tex;
3495 fetch->samp_id = instr->prefetch.samp;
3496 }
3497 fetch->wrmask = instr->regs[0]->wrmask;
3498 fetch->dst = instr->regs[0]->num;
3499 fetch->src = instr->prefetch.input_offset;
3500
3501 /* These are the limits on a5xx/a6xx, we might need to
3502 * revisit if SP_FS_PREFETCH[n] changes on later gens:
3503 */
3504 assert(fetch->dst <= 0x3f);
3505 assert(fetch->tex_id <= 0x1f);
3506 assert(fetch->samp_id < 0xf);
3507
3508 ctx->so->total_in =
3509 MAX2(ctx->so->total_in, instr->prefetch.input_offset + 2);
3510
3511 fetch->half_precision = !!(instr->regs[0]->flags & IR3_REG_HALF);
3512
3513 /* Remove the prefetch placeholder instruction: */
3514 list_delinit(&instr->node);
3515 }
3516 }
3517 }
3518 }
3519
3520 int
3521 ir3_compile_shader_nir(struct ir3_compiler *compiler,
3522 struct ir3_shader_variant *so)
3523 {
3524 struct ir3_context *ctx;
3525 struct ir3 *ir;
3526 int ret = 0, max_bary;
3527 bool progress;
3528
3529 assert(!so->ir);
3530
3531 ctx = ir3_context_init(compiler, so);
3532 if (!ctx) {
3533 DBG("INIT failed!");
3534 ret = -1;
3535 goto out;
3536 }
3537
3538 emit_instructions(ctx);
3539
3540 if (ctx->error) {
3541 DBG("EMIT failed!");
3542 ret = -1;
3543 goto out;
3544 }
3545
3546 ir = so->ir = ctx->ir;
3547
3548 assert((ctx->noutputs % 4) == 0);
3549
3550 /* Setup IR level outputs, which are "collects" that gather
3551 * the scalar components of outputs.
3552 */
3553 for (unsigned i = 0; i < ctx->noutputs; i += 4) {
3554 unsigned ncomp = 0;
3555 /* figure out the # of components written:
3556 *
3557 * TODO do we need to handle holes, ie. if .x and .z
3558 * components written, but .y component not written?
3559 */
3560 for (unsigned j = 0; j < 4; j++) {
3561 if (!ctx->outputs[i + j])
3562 break;
3563 ncomp++;
3564 }
3565
3566 /* Note that in some stages, like TCS, store_output is
3567 * lowered to memory writes, so no components of the
3568 * are "written" from the PoV of traditional store-
3569 * output instructions:
3570 */
3571 if (!ncomp)
3572 continue;
3573
3574 struct ir3_instruction *out =
3575 ir3_create_collect(ctx, &ctx->outputs[i], ncomp);
3576
3577 int outidx = i / 4;
3578 assert(outidx < so->outputs_count);
3579
3580 /* stash index into so->outputs[] so we can map the
3581 * output back to slot/etc later:
3582 */
3583 out->collect.outidx = outidx;
3584
3585 array_insert(ir, ir->outputs, out);
3586 }
3587
3588 /* Set up the gs header as an output for the vertex shader so it won't
3589 * clobber it for the tess ctrl shader.
3590 *
3591 * TODO this could probably be done more cleanly in a nir pass.
3592 */
3593 if (ctx->so->type == MESA_SHADER_VERTEX ||
3594 (ctx->so->key.has_gs && ctx->so->type == MESA_SHADER_TESS_EVAL)) {
3595 if (ctx->primitive_id) {
3596 unsigned n = so->outputs_count++;
3597 so->outputs[n].slot = VARYING_SLOT_PRIMITIVE_ID;
3598
3599 struct ir3_instruction *out =
3600 ir3_create_collect(ctx, &ctx->primitive_id, 1);
3601 out->collect.outidx = n;
3602 array_insert(ir, ir->outputs, out);
3603 }
3604
3605 if (ctx->gs_header) {
3606 unsigned n = so->outputs_count++;
3607 so->outputs[n].slot = VARYING_SLOT_GS_HEADER_IR3;
3608 struct ir3_instruction *out =
3609 ir3_create_collect(ctx, &ctx->gs_header, 1);
3610 out->collect.outidx = n;
3611 array_insert(ir, ir->outputs, out);
3612 }
3613
3614 if (ctx->tcs_header) {
3615 unsigned n = so->outputs_count++;
3616 so->outputs[n].slot = VARYING_SLOT_TCS_HEADER_IR3;
3617 struct ir3_instruction *out =
3618 ir3_create_collect(ctx, &ctx->tcs_header, 1);
3619 out->collect.outidx = n;
3620 array_insert(ir, ir->outputs, out);
3621 }
3622 }
3623
3624 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3625 * need to make sure not to remove any inputs that are used by
3626 * the nonbinning VS.
3627 */
3628 if (ctx->compiler->gpu_id >= 600 && so->binning_pass &&
3629 so->type == MESA_SHADER_VERTEX) {
3630 for (int i = 0; i < ctx->ninputs; i++) {
3631 struct ir3_instruction *in = ctx->inputs[i];
3632
3633 if (!in)
3634 continue;
3635
3636 unsigned n = i / 4;
3637 unsigned c = i % 4;
3638
3639 debug_assert(n < so->nonbinning->inputs_count);
3640
3641 if (so->nonbinning->inputs[n].sysval)
3642 continue;
3643
3644 /* be sure to keep inputs, even if only used in VS */
3645 if (so->nonbinning->inputs[n].compmask & (1 << c))
3646 array_insert(in->block, in->block->keeps, in);
3647 }
3648 }
3649
3650 /* at this point, for binning pass, throw away unneeded outputs: */
3651 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
3652 fixup_binning_pass(ctx);
3653
3654 ir3_debug_print(ir, "AFTER: nir->ir3");
3655 ir3_validate(ir);
3656
3657 do {
3658 progress = false;
3659
3660 progress |= IR3_PASS(ir, ir3_cf);
3661 progress |= IR3_PASS(ir, ir3_cp, so);
3662 progress |= IR3_PASS(ir, ir3_dce, so);
3663 } while (progress);
3664
3665 /* at this point, for binning pass, throw away unneeded outputs:
3666 * Note that for a6xx and later, we do this after ir3_cp to ensure
3667 * that the uniform/constant layout for BS and VS matches, so that
3668 * we can re-use same VS_CONST state group.
3669 */
3670 if (so->binning_pass && (ctx->compiler->gpu_id >= 600)) {
3671 fixup_binning_pass(ctx);
3672 /* cleanup the result of removing unneeded outputs: */
3673 while (IR3_PASS(ir, ir3_dce, so)) {}
3674 }
3675
3676 IR3_PASS(ir, ir3_sched_add_deps);
3677
3678 /* Group left/right neighbors, inserting mov's where needed to
3679 * solve conflicts:
3680 */
3681 IR3_PASS(ir, ir3_group);
3682
3683 /* At this point, all the dead code should be long gone: */
3684 assert(!IR3_PASS(ir, ir3_dce, so));
3685
3686 ret = ir3_sched(ir);
3687 if (ret) {
3688 DBG("SCHED failed!");
3689 goto out;
3690 }
3691
3692 ir3_debug_print(ir, "AFTER: ir3_sched");
3693
3694 if (IR3_PASS(ir, ir3_cp_postsched)) {
3695 /* cleanup the result of removing unneeded mov's: */
3696 while (IR3_PASS(ir, ir3_dce, so)) {}
3697 }
3698
3699 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3700 * with draw pass VS, so binning and draw pass can both use the
3701 * same VBO state.
3702 *
3703 * Note that VS inputs are expected to be full precision.
3704 */
3705 bool pre_assign_inputs = (ir->compiler->gpu_id >= 600) &&
3706 (ir->type == MESA_SHADER_VERTEX) &&
3707 so->binning_pass;
3708
3709 if (pre_assign_inputs) {
3710 for (unsigned i = 0; i < ctx->ninputs; i++) {
3711 struct ir3_instruction *instr = ctx->inputs[i];
3712
3713 if (!instr)
3714 continue;
3715
3716 unsigned n = i / 4;
3717 unsigned c = i % 4;
3718 unsigned regid = so->nonbinning->inputs[n].regid + c;
3719
3720 instr->regs[0]->num = regid;
3721 }
3722
3723 ret = ir3_ra(so, ctx->inputs, ctx->ninputs);
3724 } else if (ctx->tcs_header) {
3725 /* We need to have these values in the same registers between VS and TCS
3726 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3727 */
3728
3729 ctx->tcs_header->regs[0]->num = regid(0, 0);
3730 ctx->primitive_id->regs[0]->num = regid(0, 1);
3731 struct ir3_instruction *precolor[] = { ctx->tcs_header, ctx->primitive_id };
3732 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3733 } else if (ctx->gs_header) {
3734 /* We need to have these values in the same registers between producer
3735 * (VS or DS) and GS since the producer chains to GS and doesn't get
3736 * the sysvals redelivered.
3737 */
3738
3739 ctx->gs_header->regs[0]->num = regid(0, 0);
3740 ctx->primitive_id->regs[0]->num = regid(0, 1);
3741 struct ir3_instruction *precolor[] = { ctx->gs_header, ctx->primitive_id };
3742 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3743 } else if (so->num_sampler_prefetch) {
3744 assert(so->type == MESA_SHADER_FRAGMENT);
3745 struct ir3_instruction *precolor[2];
3746 int idx = 0;
3747
3748 foreach_input (instr, ir) {
3749 if (instr->input.sysval != SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL)
3750 continue;
3751
3752 assert(idx < ARRAY_SIZE(precolor));
3753
3754 precolor[idx] = instr;
3755 instr->regs[0]->num = idx;
3756
3757 idx++;
3758 }
3759 ret = ir3_ra(so, precolor, idx);
3760 } else {
3761 ret = ir3_ra(so, NULL, 0);
3762 }
3763
3764 if (ret) {
3765 DBG("RA failed!");
3766 goto out;
3767 }
3768
3769 IR3_PASS(ir, ir3_postsched, so);
3770
3771 if (compiler->gpu_id >= 600) {
3772 IR3_PASS(ir, ir3_a6xx_fixup_atomic_dests, so);
3773 }
3774
3775 if (so->type == MESA_SHADER_FRAGMENT)
3776 pack_inlocs(ctx);
3777
3778 /*
3779 * Fixup inputs/outputs to point to the actual registers assigned:
3780 *
3781 * 1) initialize to r63.x (invalid/unused)
3782 * 2) iterate IR level inputs/outputs and update the variants
3783 * inputs/outputs table based on the assigned registers for
3784 * the remaining inputs/outputs.
3785 */
3786
3787 for (unsigned i = 0; i < so->inputs_count; i++)
3788 so->inputs[i].regid = INVALID_REG;
3789 for (unsigned i = 0; i < so->outputs_count; i++)
3790 so->outputs[i].regid = INVALID_REG;
3791
3792 foreach_output (out, ir) {
3793 assert(out->opc == OPC_META_COLLECT);
3794 unsigned outidx = out->collect.outidx;
3795
3796 so->outputs[outidx].regid = out->regs[0]->num;
3797 so->outputs[outidx].half = !!(out->regs[0]->flags & IR3_REG_HALF);
3798 }
3799
3800 foreach_input (in, ir) {
3801 assert(in->opc == OPC_META_INPUT);
3802 unsigned inidx = in->input.inidx;
3803
3804 if (pre_assign_inputs && !so->inputs[inidx].sysval) {
3805 if (VALIDREG(so->nonbinning->inputs[inidx].regid)) {
3806 compile_assert(ctx, in->regs[0]->num ==
3807 so->nonbinning->inputs[inidx].regid);
3808 compile_assert(ctx, !!(in->regs[0]->flags & IR3_REG_HALF) ==
3809 so->nonbinning->inputs[inidx].half);
3810 }
3811 so->inputs[inidx].regid = so->nonbinning->inputs[inidx].regid;
3812 so->inputs[inidx].half = so->nonbinning->inputs[inidx].half;
3813 } else {
3814 so->inputs[inidx].regid = in->regs[0]->num;
3815 so->inputs[inidx].half = !!(in->regs[0]->flags & IR3_REG_HALF);
3816 }
3817 }
3818
3819 if (ctx->astc_srgb)
3820 fixup_astc_srgb(ctx);
3821
3822 /* We need to do legalize after (for frag shader's) the "bary.f"
3823 * offsets (inloc) have been assigned.
3824 */
3825 IR3_PASS(ir, ir3_legalize, so, &max_bary);
3826
3827 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3828 * know what we might have to wait on when coming in from VS chsh.
3829 */
3830 if (so->type == MESA_SHADER_TESS_CTRL ||
3831 so->type == MESA_SHADER_GEOMETRY ) {
3832 foreach_block (block, &ir->block_list) {
3833 foreach_instr (instr, &block->instr_list) {
3834 instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
3835 break;
3836 }
3837 }
3838 }
3839
3840 so->branchstack = ctx->max_stack;
3841
3842 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3843 if (so->type == MESA_SHADER_FRAGMENT)
3844 so->total_in = max_bary + 1;
3845
3846 /* Collect sampling instructions eligible for pre-dispatch. */
3847 collect_tex_prefetches(ctx, ir);
3848
3849 if (so->type == MESA_SHADER_FRAGMENT &&
3850 ctx->s->info.fs.needs_helper_invocations)
3851 so->need_pixlod = true;
3852
3853 out:
3854 if (ret) {
3855 if (so->ir)
3856 ir3_destroy(so->ir);
3857 so->ir = NULL;
3858 }
3859 ir3_context_free(ctx);
3860
3861 return ret;
3862 }