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freedreno/ir3: cleanup by removing repeated code
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 __ssa_dst(mov);
55 src = __ssa_src(mov, collect, IR3_REG_RELATIV);
56 src->size = arrsz;
57 src->array.offset = n;
58
59 ir3_instr_set_address(mov, address);
60
61 return mov;
62 }
63
64 static struct ir3_instruction *
65 create_input(struct ir3_context *ctx, unsigned compmask)
66 {
67 struct ir3_instruction *in;
68
69 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
70 in->input.sysval = ~0;
71 __ssa_dst(in)->wrmask = compmask;
72
73 array_insert(ctx->ir, ctx->ir->inputs, in);
74
75 return in;
76 }
77
78 static struct ir3_instruction *
79 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
80 {
81 struct ir3_block *block = ctx->block;
82 struct ir3_instruction *instr;
83 /* packed inloc is fixed up later: */
84 struct ir3_instruction *inloc = create_immed(block, n);
85
86 if (use_ldlv) {
87 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
88 instr->cat6.type = TYPE_U32;
89 instr->cat6.iim_val = 1;
90 } else {
91 instr = ir3_BARY_F(block, inloc, 0, ctx->ij_pixel, 0);
92 instr->regs[2]->wrmask = 0x3;
93 }
94
95 return instr;
96 }
97
98 static struct ir3_instruction *
99 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
100 {
101 /* first four vec4 sysval's reserved for UBOs: */
102 /* NOTE: dp is in scalar, but there can be >4 dp components: */
103 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
104 unsigned n = const_state->offsets.driver_param;
105 unsigned r = regid(n + dp / 4, dp % 4);
106 return create_uniform(ctx->block, r);
107 }
108
109 /*
110 * Adreno uses uint rather than having dedicated bool type,
111 * which (potentially) requires some conversion, in particular
112 * when using output of an bool instr to int input, or visa
113 * versa.
114 *
115 * | Adreno | NIR |
116 * -------+---------+-------+-
117 * true | 1 | ~0 |
118 * false | 0 | 0 |
119 *
120 * To convert from an adreno bool (uint) to nir, use:
121 *
122 * absneg.s dst, (neg)src
123 *
124 * To convert back in the other direction:
125 *
126 * absneg.s dst, (abs)arc
127 *
128 * The CP step can clean up the absneg.s that cancel each other
129 * out, and with a slight bit of extra cleverness (to recognize
130 * the instructions which produce either a 0 or 1) can eliminate
131 * the absneg.s's completely when an instruction that wants
132 * 0/1 consumes the result. For example, when a nir 'bcsel'
133 * consumes the result of 'feq'. So we should be able to get by
134 * without a boolean resolve step, and without incuring any
135 * extra penalty in instruction count.
136 */
137
138 /* NIR bool -> native (adreno): */
139 static struct ir3_instruction *
140 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
141 {
142 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
143 }
144
145 /* native (adreno) -> NIR bool: */
146 static struct ir3_instruction *
147 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
148 {
149 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
150 }
151
152 /*
153 * alu/sfu instructions:
154 */
155
156 static struct ir3_instruction *
157 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
158 unsigned src_bitsize, nir_op op)
159 {
160 type_t src_type, dst_type;
161
162 switch (op) {
163 case nir_op_f2f32:
164 case nir_op_f2f16_rtne:
165 case nir_op_f2f16_rtz:
166 case nir_op_f2f16:
167 case nir_op_f2i32:
168 case nir_op_f2i16:
169 case nir_op_f2i8:
170 case nir_op_f2u32:
171 case nir_op_f2u16:
172 case nir_op_f2u8:
173 switch (src_bitsize) {
174 case 32:
175 src_type = TYPE_F32;
176 break;
177 case 16:
178 src_type = TYPE_F16;
179 break;
180 default:
181 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
182 }
183 break;
184
185 case nir_op_i2f32:
186 case nir_op_i2f16:
187 case nir_op_i2i32:
188 case nir_op_i2i16:
189 case nir_op_i2i8:
190 switch (src_bitsize) {
191 case 32:
192 src_type = TYPE_S32;
193 break;
194 case 16:
195 src_type = TYPE_S16;
196 break;
197 case 8:
198 src_type = TYPE_S8;
199 break;
200 default:
201 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
202 }
203 break;
204
205 case nir_op_u2f32:
206 case nir_op_u2f16:
207 case nir_op_u2u32:
208 case nir_op_u2u16:
209 case nir_op_u2u8:
210 switch (src_bitsize) {
211 case 32:
212 src_type = TYPE_U32;
213 break;
214 case 16:
215 src_type = TYPE_U16;
216 break;
217 case 8:
218 src_type = TYPE_U8;
219 break;
220 default:
221 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
222 }
223 break;
224
225 default:
226 ir3_context_error(ctx, "invalid conversion op: %u", op);
227 }
228
229 switch (op) {
230 case nir_op_f2f32:
231 case nir_op_i2f32:
232 case nir_op_u2f32:
233 dst_type = TYPE_F32;
234 break;
235
236 case nir_op_f2f16_rtne:
237 case nir_op_f2f16_rtz:
238 case nir_op_f2f16:
239 /* TODO how to handle rounding mode? */
240 case nir_op_i2f16:
241 case nir_op_u2f16:
242 dst_type = TYPE_F16;
243 break;
244
245 case nir_op_f2i32:
246 case nir_op_i2i32:
247 dst_type = TYPE_S32;
248 break;
249
250 case nir_op_f2i16:
251 case nir_op_i2i16:
252 dst_type = TYPE_S16;
253 break;
254
255 case nir_op_f2i8:
256 case nir_op_i2i8:
257 dst_type = TYPE_S8;
258 break;
259
260 case nir_op_f2u32:
261 case nir_op_u2u32:
262 dst_type = TYPE_U32;
263 break;
264
265 case nir_op_f2u16:
266 case nir_op_u2u16:
267 dst_type = TYPE_U16;
268 break;
269
270 case nir_op_f2u8:
271 case nir_op_u2u8:
272 dst_type = TYPE_U8;
273 break;
274
275 default:
276 ir3_context_error(ctx, "invalid conversion op: %u", op);
277 }
278
279 return ir3_COV(ctx->block, src, src_type, dst_type);
280 }
281
282 static void
283 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
284 {
285 const nir_op_info *info = &nir_op_infos[alu->op];
286 struct ir3_instruction **dst, *src[info->num_inputs];
287 unsigned bs[info->num_inputs]; /* bit size */
288 struct ir3_block *b = ctx->block;
289 unsigned dst_sz, wrmask;
290 type_t dst_type = nir_dest_bit_size(alu->dest.dest) < 32 ?
291 TYPE_U16 : TYPE_U32;
292
293 if (alu->dest.dest.is_ssa) {
294 dst_sz = alu->dest.dest.ssa.num_components;
295 wrmask = (1 << dst_sz) - 1;
296 } else {
297 dst_sz = alu->dest.dest.reg.reg->num_components;
298 wrmask = alu->dest.write_mask;
299 }
300
301 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
302
303 /* Vectors are special in that they have non-scalarized writemasks,
304 * and just take the first swizzle channel for each argument in
305 * order into each writemask channel.
306 */
307 if ((alu->op == nir_op_vec2) ||
308 (alu->op == nir_op_vec3) ||
309 (alu->op == nir_op_vec4)) {
310
311 for (int i = 0; i < info->num_inputs; i++) {
312 nir_alu_src *asrc = &alu->src[i];
313
314 compile_assert(ctx, !asrc->abs);
315 compile_assert(ctx, !asrc->negate);
316
317 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
318 if (!src[i])
319 src[i] = create_immed_typed(ctx->block, 0, dst_type);
320 dst[i] = ir3_MOV(b, src[i], dst_type);
321 }
322
323 ir3_put_dst(ctx, &alu->dest.dest);
324 return;
325 }
326
327 /* We also get mov's with more than one component for mov's so
328 * handle those specially:
329 */
330 if (alu->op == nir_op_mov) {
331 nir_alu_src *asrc = &alu->src[0];
332 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
333
334 for (unsigned i = 0; i < dst_sz; i++) {
335 if (wrmask & (1 << i)) {
336 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
337 } else {
338 dst[i] = NULL;
339 }
340 }
341
342 ir3_put_dst(ctx, &alu->dest.dest);
343 return;
344 }
345
346 /* General case: We can just grab the one used channel per src. */
347 for (int i = 0; i < info->num_inputs; i++) {
348 unsigned chan = ffs(alu->dest.write_mask) - 1;
349 nir_alu_src *asrc = &alu->src[i];
350
351 compile_assert(ctx, !asrc->abs);
352 compile_assert(ctx, !asrc->negate);
353
354 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
355 bs[i] = nir_src_bit_size(asrc->src);
356
357 compile_assert(ctx, src[i]);
358 }
359
360 switch (alu->op) {
361 case nir_op_f2f32:
362 case nir_op_f2f16_rtne:
363 case nir_op_f2f16_rtz:
364 case nir_op_f2f16:
365 case nir_op_f2i32:
366 case nir_op_f2i16:
367 case nir_op_f2i8:
368 case nir_op_f2u32:
369 case nir_op_f2u16:
370 case nir_op_f2u8:
371 case nir_op_i2f32:
372 case nir_op_i2f16:
373 case nir_op_i2i32:
374 case nir_op_i2i16:
375 case nir_op_i2i8:
376 case nir_op_u2f32:
377 case nir_op_u2f16:
378 case nir_op_u2u32:
379 case nir_op_u2u16:
380 case nir_op_u2u8:
381 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
382 break;
383 case nir_op_fquantize2f16:
384 dst[0] = create_cov(ctx,
385 create_cov(ctx, src[0], 32, nir_op_f2f16),
386 16, nir_op_f2f32);
387 break;
388 case nir_op_f2b32:
389 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
390 dst[0]->cat2.condition = IR3_COND_NE;
391 break;
392 case nir_op_b2f16:
393 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F16);
394 break;
395 case nir_op_b2f32:
396 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
397 break;
398 case nir_op_b2i8:
399 case nir_op_b2i16:
400 case nir_op_b2i32:
401 dst[0] = ir3_b2n(b, src[0]);
402 break;
403 case nir_op_i2b32:
404 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
405 dst[0]->cat2.condition = IR3_COND_NE;
406 break;
407
408 case nir_op_fneg:
409 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
410 break;
411 case nir_op_fabs:
412 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
413 break;
414 case nir_op_fmax:
415 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
416 break;
417 case nir_op_fmin:
418 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
419 break;
420 case nir_op_fsat:
421 /* if there is just a single use of the src, and it supports
422 * (sat) bit, we can just fold the (sat) flag back to the
423 * src instruction and create a mov. This is easier for cp
424 * to eliminate.
425 *
426 * TODO probably opc_cat==4 is ok too
427 */
428 if (alu->src[0].src.is_ssa &&
429 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
430 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
431 src[0]->flags |= IR3_INSTR_SAT;
432 dst[0] = ir3_MOV(b, src[0], dst_type);
433 } else {
434 /* otherwise generate a max.f that saturates.. blob does
435 * similar (generating a cat2 mov using max.f)
436 */
437 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
438 dst[0]->flags |= IR3_INSTR_SAT;
439 }
440 break;
441 case nir_op_fmul:
442 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
443 break;
444 case nir_op_fadd:
445 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
446 break;
447 case nir_op_fsub:
448 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
449 break;
450 case nir_op_ffma:
451 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
452 break;
453 case nir_op_fddx:
454 case nir_op_fddx_coarse:
455 dst[0] = ir3_DSX(b, src[0], 0);
456 dst[0]->cat5.type = TYPE_F32;
457 break;
458 case nir_op_fddy:
459 case nir_op_fddy_coarse:
460 dst[0] = ir3_DSY(b, src[0], 0);
461 dst[0]->cat5.type = TYPE_F32;
462 break;
463 break;
464 case nir_op_flt32:
465 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
466 dst[0]->cat2.condition = IR3_COND_LT;
467 break;
468 case nir_op_fge32:
469 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
470 dst[0]->cat2.condition = IR3_COND_GE;
471 break;
472 case nir_op_feq32:
473 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
474 dst[0]->cat2.condition = IR3_COND_EQ;
475 break;
476 case nir_op_fne32:
477 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
478 dst[0]->cat2.condition = IR3_COND_NE;
479 break;
480 case nir_op_fceil:
481 dst[0] = ir3_CEIL_F(b, src[0], 0);
482 break;
483 case nir_op_ffloor:
484 dst[0] = ir3_FLOOR_F(b, src[0], 0);
485 break;
486 case nir_op_ftrunc:
487 dst[0] = ir3_TRUNC_F(b, src[0], 0);
488 break;
489 case nir_op_fround_even:
490 dst[0] = ir3_RNDNE_F(b, src[0], 0);
491 break;
492 case nir_op_fsign:
493 dst[0] = ir3_SIGN_F(b, src[0], 0);
494 break;
495
496 case nir_op_fsin:
497 dst[0] = ir3_SIN(b, src[0], 0);
498 break;
499 case nir_op_fcos:
500 dst[0] = ir3_COS(b, src[0], 0);
501 break;
502 case nir_op_frsq:
503 dst[0] = ir3_RSQ(b, src[0], 0);
504 break;
505 case nir_op_frcp:
506 dst[0] = ir3_RCP(b, src[0], 0);
507 break;
508 case nir_op_flog2:
509 dst[0] = ir3_LOG2(b, src[0], 0);
510 break;
511 case nir_op_fexp2:
512 dst[0] = ir3_EXP2(b, src[0], 0);
513 break;
514 case nir_op_fsqrt:
515 dst[0] = ir3_SQRT(b, src[0], 0);
516 break;
517
518 case nir_op_iabs:
519 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
520 break;
521 case nir_op_iadd:
522 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
523 break;
524 case nir_op_iand:
525 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
526 break;
527 case nir_op_imax:
528 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
529 break;
530 case nir_op_umax:
531 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
532 break;
533 case nir_op_imin:
534 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
535 break;
536 case nir_op_umin:
537 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
538 break;
539 case nir_op_umul_low:
540 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
541 break;
542 case nir_op_imadsh_mix16:
543 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
544 break;
545 case nir_op_imad24_ir3:
546 dst[0] = ir3_MAD_S24(b, src[0], 0, src[1], 0, src[2], 0);
547 break;
548 case nir_op_imul24:
549 dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
550 break;
551 case nir_op_ineg:
552 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
553 break;
554 case nir_op_inot:
555 dst[0] = ir3_NOT_B(b, src[0], 0);
556 break;
557 case nir_op_ior:
558 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
559 break;
560 case nir_op_ishl:
561 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
562 break;
563 case nir_op_ishr:
564 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
565 break;
566 case nir_op_isub:
567 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
568 break;
569 case nir_op_ixor:
570 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
571 break;
572 case nir_op_ushr:
573 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
574 break;
575 case nir_op_ilt32:
576 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
577 dst[0]->cat2.condition = IR3_COND_LT;
578 break;
579 case nir_op_ige32:
580 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
581 dst[0]->cat2.condition = IR3_COND_GE;
582 break;
583 case nir_op_ieq32:
584 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
585 dst[0]->cat2.condition = IR3_COND_EQ;
586 break;
587 case nir_op_ine32:
588 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
589 dst[0]->cat2.condition = IR3_COND_NE;
590 break;
591 case nir_op_ult32:
592 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
593 dst[0]->cat2.condition = IR3_COND_LT;
594 break;
595 case nir_op_uge32:
596 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
597 dst[0]->cat2.condition = IR3_COND_GE;
598 break;
599
600 case nir_op_b32csel: {
601 struct ir3_instruction *cond = ir3_b2n(b, src[0]);
602 compile_assert(ctx, bs[1] == bs[2]);
603 /* the boolean condition is 32b even if src[1] and src[2] are
604 * half-precision, but sel.b16 wants all three src's to be the
605 * same type.
606 */
607 if (bs[1] < 32)
608 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
609 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
610 break;
611 }
612 case nir_op_bit_count: {
613 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
614 // double check on earlier gen's. Once half-precision support is
615 // in place, this should probably move to a NIR lowering pass:
616 struct ir3_instruction *hi, *lo;
617
618 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
619 TYPE_U32, TYPE_U16);
620 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
621
622 hi = ir3_CBITS_B(b, hi, 0);
623 lo = ir3_CBITS_B(b, lo, 0);
624
625 // TODO maybe the builders should default to making dst half-precision
626 // if the src's were half precision, to make this less awkward.. otoh
627 // we should probably just do this lowering in NIR.
628 hi->regs[0]->flags |= IR3_REG_HALF;
629 lo->regs[0]->flags |= IR3_REG_HALF;
630
631 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
632 dst[0]->regs[0]->flags |= IR3_REG_HALF;
633 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
634 break;
635 }
636 case nir_op_ifind_msb: {
637 struct ir3_instruction *cmp;
638 dst[0] = ir3_CLZ_S(b, src[0], 0);
639 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
640 cmp->cat2.condition = IR3_COND_GE;
641 dst[0] = ir3_SEL_B32(b,
642 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
643 cmp, 0, dst[0], 0);
644 break;
645 }
646 case nir_op_ufind_msb:
647 dst[0] = ir3_CLZ_B(b, src[0], 0);
648 dst[0] = ir3_SEL_B32(b,
649 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
650 src[0], 0, dst[0], 0);
651 break;
652 case nir_op_find_lsb:
653 dst[0] = ir3_BFREV_B(b, src[0], 0);
654 dst[0] = ir3_CLZ_B(b, dst[0], 0);
655 break;
656 case nir_op_bitfield_reverse:
657 dst[0] = ir3_BFREV_B(b, src[0], 0);
658 break;
659
660 default:
661 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
662 nir_op_infos[alu->op].name);
663 break;
664 }
665
666 if (nir_alu_type_get_base_type(info->output_type) == nir_type_bool) {
667 assert(dst_sz == 1);
668 dst[0] = ir3_n2b(b, dst[0]);
669 }
670
671 ir3_put_dst(ctx, &alu->dest.dest);
672 }
673
674 /* handles direct/indirect UBO reads: */
675 static void
676 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
677 struct ir3_instruction **dst)
678 {
679 struct ir3_block *b = ctx->block;
680 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
681 /* UBO addresses are the first driver params, but subtract 2 here to
682 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
683 * is the uniforms: */
684 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
685 unsigned ubo = regid(const_state->offsets.ubo, 0) - 2;
686 const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
687
688 int off = 0;
689
690 /* First src is ubo index, which could either be an immed or not: */
691 src0 = ir3_get_src(ctx, &intr->src[0])[0];
692 if (is_same_type_mov(src0) &&
693 (src0->regs[1]->flags & IR3_REG_IMMED)) {
694 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
695 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
696 } else {
697 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, ptrsz));
698 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, ptrsz));
699
700 /* NOTE: since relative addressing is used, make sure constlen is
701 * at least big enough to cover all the UBO addresses, since the
702 * assembler won't know what the max address reg is.
703 */
704 ctx->so->constlen = MAX2(ctx->so->constlen,
705 const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
706 }
707
708 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
709 addr = base_lo;
710
711 if (nir_src_is_const(intr->src[1])) {
712 off += nir_src_as_uint(intr->src[1]);
713 } else {
714 /* For load_ubo_indirect, second src is indirect offset: */
715 src1 = ir3_get_src(ctx, &intr->src[1])[0];
716
717 /* and add offset to addr: */
718 addr = ir3_ADD_S(b, addr, 0, src1, 0);
719 }
720
721 /* if offset is to large to encode in the ldg, split it out: */
722 if ((off + (intr->num_components * 4)) > 1024) {
723 /* split out the minimal amount to improve the odds that
724 * cp can fit the immediate in the add.s instruction:
725 */
726 unsigned off2 = off + (intr->num_components * 4) - 1024;
727 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
728 off -= off2;
729 }
730
731 if (ptrsz == 2) {
732 struct ir3_instruction *carry;
733
734 /* handle 32b rollover, ie:
735 * if (addr < base_lo)
736 * base_hi++
737 */
738 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
739 carry->cat2.condition = IR3_COND_LT;
740 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
741
742 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
743 }
744
745 for (int i = 0; i < intr->num_components; i++) {
746 struct ir3_instruction *load =
747 ir3_LDG(b, addr, 0, create_immed(b, 1), 0, /* num components */
748 create_immed(b, off + i * 4), 0);
749 load->cat6.type = TYPE_U32;
750 dst[i] = load;
751 }
752 }
753
754 /* src[] = { block_index } */
755 static void
756 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
757 struct ir3_instruction **dst)
758 {
759 /* SSBO size stored as a const starting at ssbo_sizes: */
760 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
761 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
762 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
763 const_state->ssbo_size.off[blk_idx];
764
765 debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
766
767 dst[0] = create_uniform(ctx->block, idx);
768 }
769
770 /* src[] = { offset }. const_index[] = { base } */
771 static void
772 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
773 struct ir3_instruction **dst)
774 {
775 struct ir3_block *b = ctx->block;
776 struct ir3_instruction *ldl, *offset;
777 unsigned base;
778
779 offset = ir3_get_src(ctx, &intr->src[0])[0];
780 base = nir_intrinsic_base(intr);
781
782 ldl = ir3_LDL(b, offset, 0,
783 create_immed(b, intr->num_components), 0,
784 create_immed(b, base), 0);
785
786 ldl->cat6.type = utype_dst(intr->dest);
787 ldl->regs[0]->wrmask = MASK(intr->num_components);
788
789 ldl->barrier_class = IR3_BARRIER_SHARED_R;
790 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
791
792 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
793 }
794
795 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
796 static void
797 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
798 {
799 struct ir3_block *b = ctx->block;
800 struct ir3_instruction *stl, *offset;
801 struct ir3_instruction * const *value;
802 unsigned base, wrmask;
803
804 value = ir3_get_src(ctx, &intr->src[0]);
805 offset = ir3_get_src(ctx, &intr->src[1])[0];
806
807 base = nir_intrinsic_base(intr);
808 wrmask = nir_intrinsic_write_mask(intr);
809
810 /* Combine groups of consecutive enabled channels in one write
811 * message. We use ffs to find the first enabled channel and then ffs on
812 * the bit-inverse, down-shifted writemask to determine the length of
813 * the block of enabled bits.
814 *
815 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
816 */
817 while (wrmask) {
818 unsigned first_component = ffs(wrmask) - 1;
819 unsigned length = ffs(~(wrmask >> first_component)) - 1;
820
821 stl = ir3_STL(b, offset, 0,
822 ir3_create_collect(ctx, &value[first_component], length), 0,
823 create_immed(b, length), 0);
824 stl->cat6.dst_offset = first_component + base;
825 stl->cat6.type = utype_src(intr->src[0]);
826 stl->barrier_class = IR3_BARRIER_SHARED_W;
827 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
828
829 array_insert(b, b->keeps, stl);
830
831 /* Clear the bits in the writemask that we just wrote, then try
832 * again to see if more channels are left.
833 */
834 wrmask &= (15 << (first_component + length));
835 }
836 }
837
838 /* src[] = { offset }. const_index[] = { base } */
839 static void
840 emit_intrinsic_load_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr,
841 struct ir3_instruction **dst)
842 {
843 struct ir3_block *b = ctx->block;
844 struct ir3_instruction *load, *offset;
845 unsigned base;
846
847 offset = ir3_get_src(ctx, &intr->src[0])[0];
848 base = nir_intrinsic_base(intr);
849
850 load = ir3_LDLW(b, offset, 0,
851 create_immed(b, intr->num_components), 0,
852 create_immed(b, base), 0);
853
854 load->cat6.type = utype_dst(intr->dest);
855 load->regs[0]->wrmask = MASK(intr->num_components);
856
857 load->barrier_class = IR3_BARRIER_SHARED_R;
858 load->barrier_conflict = IR3_BARRIER_SHARED_W;
859
860 ir3_split_dest(b, dst, load, 0, intr->num_components);
861 }
862
863 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
864 static void
865 emit_intrinsic_store_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr)
866 {
867 struct ir3_block *b = ctx->block;
868 struct ir3_instruction *store, *offset;
869 struct ir3_instruction * const *value;
870 unsigned base, wrmask;
871
872 value = ir3_get_src(ctx, &intr->src[0]);
873 offset = ir3_get_src(ctx, &intr->src[1])[0];
874
875 base = nir_intrinsic_base(intr);
876 wrmask = nir_intrinsic_write_mask(intr);
877
878 /* Combine groups of consecutive enabled channels in one write
879 * message. We use ffs to find the first enabled channel and then ffs on
880 * the bit-inverse, down-shifted writemask to determine the length of
881 * the block of enabled bits.
882 *
883 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
884 */
885 while (wrmask) {
886 unsigned first_component = ffs(wrmask) - 1;
887 unsigned length = ffs(~(wrmask >> first_component)) - 1;
888
889 store = ir3_STLW(b, offset, 0,
890 ir3_create_collect(ctx, &value[first_component], length), 0,
891 create_immed(b, length), 0);
892
893 store->cat6.dst_offset = first_component + base;
894 store->cat6.type = utype_src(intr->src[0]);
895 store->barrier_class = IR3_BARRIER_SHARED_W;
896 store->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
897
898 array_insert(b, b->keeps, store);
899
900 /* Clear the bits in the writemask that we just wrote, then try
901 * again to see if more channels are left.
902 */
903 wrmask &= (15 << (first_component + length));
904 }
905 }
906
907 /*
908 * CS shared variable atomic intrinsics
909 *
910 * All of the shared variable atomic memory operations read a value from
911 * memory, compute a new value using one of the operations below, write the
912 * new value to memory, and return the original value read.
913 *
914 * All operations take 2 sources except CompSwap that takes 3. These
915 * sources represent:
916 *
917 * 0: The offset into the shared variable storage region that the atomic
918 * operation will operate on.
919 * 1: The data parameter to the atomic function (i.e. the value to add
920 * in shared_atomic_add, etc).
921 * 2: For CompSwap only: the second data parameter.
922 */
923 static struct ir3_instruction *
924 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
925 {
926 struct ir3_block *b = ctx->block;
927 struct ir3_instruction *atomic, *src0, *src1;
928 type_t type = TYPE_U32;
929
930 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
931 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
932
933 switch (intr->intrinsic) {
934 case nir_intrinsic_shared_atomic_add:
935 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
936 break;
937 case nir_intrinsic_shared_atomic_imin:
938 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
939 type = TYPE_S32;
940 break;
941 case nir_intrinsic_shared_atomic_umin:
942 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
943 break;
944 case nir_intrinsic_shared_atomic_imax:
945 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
946 type = TYPE_S32;
947 break;
948 case nir_intrinsic_shared_atomic_umax:
949 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
950 break;
951 case nir_intrinsic_shared_atomic_and:
952 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
953 break;
954 case nir_intrinsic_shared_atomic_or:
955 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
956 break;
957 case nir_intrinsic_shared_atomic_xor:
958 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
959 break;
960 case nir_intrinsic_shared_atomic_exchange:
961 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
962 break;
963 case nir_intrinsic_shared_atomic_comp_swap:
964 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
965 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
966 ir3_get_src(ctx, &intr->src[2])[0],
967 src1,
968 }, 2);
969 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
970 break;
971 default:
972 unreachable("boo");
973 }
974
975 atomic->cat6.iim_val = 1;
976 atomic->cat6.d = 1;
977 atomic->cat6.type = type;
978 atomic->barrier_class = IR3_BARRIER_SHARED_W;
979 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
980
981 /* even if nothing consume the result, we can't DCE the instruction: */
982 array_insert(b, b->keeps, atomic);
983
984 return atomic;
985 }
986
987 /* TODO handle actual indirect/dynamic case.. which is going to be weird
988 * to handle with the image_mapping table..
989 */
990 static struct ir3_instruction *
991 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
992 {
993 unsigned slot = ir3_get_image_slot(nir_src_as_deref(intr->src[0]));
994 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
995 struct ir3_instruction *texture, *sampler;
996
997 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
998 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
999
1000 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1001 sampler,
1002 texture,
1003 }, 2);
1004 }
1005
1006 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1007 static void
1008 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1009 struct ir3_instruction **dst)
1010 {
1011 struct ir3_block *b = ctx->block;
1012 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1013 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
1014 struct ir3_instruction *sam;
1015 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
1016 struct ir3_instruction *coords[4];
1017 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
1018 type_t type = ir3_get_image_type(var);
1019
1020 /* hmm, this seems a bit odd, but it is what blob does and (at least
1021 * a5xx) just faults on bogus addresses otherwise:
1022 */
1023 if (flags & IR3_INSTR_3D) {
1024 flags &= ~IR3_INSTR_3D;
1025 flags |= IR3_INSTR_A;
1026 }
1027
1028 for (unsigned i = 0; i < ncoords; i++)
1029 coords[i] = src0[i];
1030
1031 if (ncoords == 1)
1032 coords[ncoords++] = create_immed(b, 0);
1033
1034 sam = ir3_SAM(b, OPC_ISAM, type, 0b1111, flags,
1035 samp_tex, ir3_create_collect(ctx, coords, ncoords), NULL);
1036
1037 sam->barrier_class = IR3_BARRIER_IMAGE_R;
1038 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
1039
1040 ir3_split_dest(b, dst, sam, 0, 4);
1041 }
1042
1043 static void
1044 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1045 struct ir3_instruction **dst)
1046 {
1047 struct ir3_block *b = ctx->block;
1048 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1049 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
1050 struct ir3_instruction *sam, *lod;
1051 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
1052
1053 lod = create_immed(b, 0);
1054 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
1055 samp_tex, lod, NULL);
1056
1057 /* Array size actually ends up in .w rather than .z. This doesn't
1058 * matter for miplevel 0, but for higher mips the value in z is
1059 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1060 * returned, which means that we have to add 1 to it for arrays for
1061 * a3xx.
1062 *
1063 * Note use a temporary dst and then copy, since the size of the dst
1064 * array that is passed in is based on nir's understanding of the
1065 * result size, not the hardware's
1066 */
1067 struct ir3_instruction *tmp[4];
1068
1069 ir3_split_dest(b, tmp, sam, 0, 4);
1070
1071 /* get_size instruction returns size in bytes instead of texels
1072 * for imageBuffer, so we need to divide it by the pixel size
1073 * of the image format.
1074 *
1075 * TODO: This is at least true on a5xx. Check other gens.
1076 */
1077 enum glsl_sampler_dim dim =
1078 glsl_get_sampler_dim(glsl_without_array(var->type));
1079 if (dim == GLSL_SAMPLER_DIM_BUF) {
1080 /* Since all the possible values the divisor can take are
1081 * power-of-two (4, 8, or 16), the division is implemented
1082 * as a shift-right.
1083 * During shader setup, the log2 of the image format's
1084 * bytes-per-pixel should have been emitted in 2nd slot of
1085 * image_dims. See ir3_shader::emit_image_dims().
1086 */
1087 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
1088 unsigned cb = regid(const_state->offsets.image_dims, 0) +
1089 const_state->image_dims.off[var->data.driver_location];
1090 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1091
1092 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1093 }
1094
1095 for (unsigned i = 0; i < ncoords; i++)
1096 dst[i] = tmp[i];
1097
1098 if (flags & IR3_INSTR_A) {
1099 if (ctx->compiler->levels_add_one) {
1100 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1101 } else {
1102 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1103 }
1104 }
1105 }
1106
1107 static void
1108 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1109 {
1110 struct ir3_block *b = ctx->block;
1111 struct ir3_instruction *barrier;
1112
1113 switch (intr->intrinsic) {
1114 case nir_intrinsic_barrier:
1115 barrier = ir3_BAR(b);
1116 barrier->cat7.g = true;
1117 barrier->cat7.l = true;
1118 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1119 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1120 break;
1121 case nir_intrinsic_memory_barrier:
1122 barrier = ir3_FENCE(b);
1123 barrier->cat7.g = true;
1124 barrier->cat7.r = true;
1125 barrier->cat7.w = true;
1126 barrier->cat7.l = true;
1127 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1128 IR3_BARRIER_BUFFER_W;
1129 barrier->barrier_conflict =
1130 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1131 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1132 break;
1133 case nir_intrinsic_memory_barrier_atomic_counter:
1134 case nir_intrinsic_memory_barrier_buffer:
1135 barrier = ir3_FENCE(b);
1136 barrier->cat7.g = true;
1137 barrier->cat7.r = true;
1138 barrier->cat7.w = true;
1139 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1140 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1141 IR3_BARRIER_BUFFER_W;
1142 break;
1143 case nir_intrinsic_memory_barrier_image:
1144 // TODO double check if this should have .g set
1145 barrier = ir3_FENCE(b);
1146 barrier->cat7.g = true;
1147 barrier->cat7.r = true;
1148 barrier->cat7.w = true;
1149 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1150 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1151 IR3_BARRIER_IMAGE_W;
1152 break;
1153 case nir_intrinsic_memory_barrier_shared:
1154 barrier = ir3_FENCE(b);
1155 barrier->cat7.g = true;
1156 barrier->cat7.l = true;
1157 barrier->cat7.r = true;
1158 barrier->cat7.w = true;
1159 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1160 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1161 IR3_BARRIER_SHARED_W;
1162 break;
1163 case nir_intrinsic_group_memory_barrier:
1164 barrier = ir3_FENCE(b);
1165 barrier->cat7.g = true;
1166 barrier->cat7.l = true;
1167 barrier->cat7.r = true;
1168 barrier->cat7.w = true;
1169 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1170 IR3_BARRIER_IMAGE_W |
1171 IR3_BARRIER_BUFFER_W;
1172 barrier->barrier_conflict =
1173 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1174 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1175 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1176 break;
1177 default:
1178 unreachable("boo");
1179 }
1180
1181 /* make sure barrier doesn't get DCE'd */
1182 array_insert(b, b->keeps, barrier);
1183 }
1184
1185 static void add_sysval_input_compmask(struct ir3_context *ctx,
1186 gl_system_value slot, unsigned compmask,
1187 struct ir3_instruction *instr)
1188 {
1189 struct ir3_shader_variant *so = ctx->so;
1190 unsigned n = so->inputs_count++;
1191
1192 assert(instr->opc == OPC_META_INPUT);
1193 instr->input.inidx = n;
1194 instr->input.sysval = slot;
1195
1196 so->inputs[n].sysval = true;
1197 so->inputs[n].slot = slot;
1198 so->inputs[n].compmask = compmask;
1199 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1200 so->total_in++;
1201 }
1202
1203 static struct ir3_instruction *
1204 create_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1205 unsigned compmask)
1206 {
1207 assert(compmask);
1208 struct ir3_instruction *sysval = create_input(ctx, compmask);
1209 add_sysval_input_compmask(ctx, slot, compmask, sysval);
1210 return sysval;
1211 }
1212
1213 static struct ir3_instruction *
1214 get_barycentric_centroid(struct ir3_context *ctx)
1215 {
1216 if (!ctx->ij_centroid) {
1217 struct ir3_instruction *xy[2];
1218 struct ir3_instruction *ij;
1219
1220 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_CENTROID, 0x3);
1221 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1222
1223 ctx->ij_centroid = ir3_create_collect(ctx, xy, 2);
1224 }
1225
1226 return ctx->ij_centroid;
1227 }
1228
1229 static struct ir3_instruction *
1230 get_barycentric_sample(struct ir3_context *ctx)
1231 {
1232 if (!ctx->ij_sample) {
1233 struct ir3_instruction *xy[2];
1234 struct ir3_instruction *ij;
1235
1236 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_SAMPLE, 0x3);
1237 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1238
1239 ctx->ij_sample = ir3_create_collect(ctx, xy, 2);
1240 }
1241
1242 return ctx->ij_sample;
1243 }
1244
1245 static struct ir3_instruction *
1246 get_barycentric_pixel(struct ir3_context *ctx)
1247 {
1248 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1249 * this to create ij_pixel only on demand:
1250 */
1251 return ctx->ij_pixel;
1252 }
1253
1254 static struct ir3_instruction *
1255 get_frag_coord(struct ir3_context *ctx)
1256 {
1257 if (!ctx->frag_coord) {
1258 struct ir3_block *b = ctx->block;
1259 struct ir3_instruction *xyzw[4];
1260 struct ir3_instruction *hw_frag_coord;
1261
1262 hw_frag_coord = create_sysval_input(ctx, SYSTEM_VALUE_FRAG_COORD, 0xf);
1263 ir3_split_dest(ctx->block, xyzw, hw_frag_coord, 0, 4);
1264
1265 /* for frag_coord.xy, we get unsigned values.. we need
1266 * to subtract (integer) 8 and divide by 16 (right-
1267 * shift by 4) then convert to float:
1268 *
1269 * sub.s tmp, src, 8
1270 * shr.b tmp, tmp, 4
1271 * mov.u32f32 dst, tmp
1272 *
1273 */
1274 for (int i = 0; i < 2; i++) {
1275 xyzw[i] = ir3_SUB_S(b, xyzw[i], 0,
1276 create_immed(b, 8), 0);
1277 xyzw[i] = ir3_SHR_B(b, xyzw[i], 0,
1278 create_immed(b, 4), 0);
1279 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1280 }
1281
1282 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1283 ctx->so->frag_coord = true;
1284 }
1285
1286 return ctx->frag_coord;
1287 }
1288
1289 static void
1290 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1291 {
1292 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1293 struct ir3_instruction **dst;
1294 struct ir3_instruction * const *src;
1295 struct ir3_block *b = ctx->block;
1296 int idx, comp;
1297
1298 if (info->has_dest) {
1299 unsigned n = nir_intrinsic_dest_components(intr);
1300 dst = ir3_get_dst(ctx, &intr->dest, n);
1301 } else {
1302 dst = NULL;
1303 }
1304
1305 const unsigned primitive_param = ctx->so->shader->const_state.offsets.primitive_param * 4;
1306 const unsigned primitive_map = ctx->so->shader->const_state.offsets.primitive_map * 4;
1307
1308 switch (intr->intrinsic) {
1309 case nir_intrinsic_load_uniform:
1310 idx = nir_intrinsic_base(intr);
1311 if (nir_src_is_const(intr->src[0])) {
1312 idx += nir_src_as_uint(intr->src[0]);
1313 for (int i = 0; i < intr->num_components; i++) {
1314 dst[i] = create_uniform_typed(b, idx + i,
1315 nir_dest_bit_size(intr->dest) < 32 ? TYPE_F16 : TYPE_F32);
1316 }
1317 } else {
1318 src = ir3_get_src(ctx, &intr->src[0]);
1319 for (int i = 0; i < intr->num_components; i++) {
1320 dst[i] = create_uniform_indirect(b, idx + i,
1321 ir3_get_addr(ctx, src[0], 1));
1322 }
1323 /* NOTE: if relative addressing is used, we set
1324 * constlen in the compiler (to worst-case value)
1325 * since we don't know in the assembler what the max
1326 * addr reg value can be:
1327 */
1328 ctx->so->constlen = MAX2(ctx->so->constlen,
1329 ctx->so->shader->ubo_state.size / 16);
1330 }
1331 break;
1332
1333 case nir_intrinsic_load_vs_primitive_stride_ir3:
1334 dst[0] = create_uniform(b, primitive_param + 0);
1335 break;
1336 case nir_intrinsic_load_vs_vertex_stride_ir3:
1337 dst[0] = create_uniform(b, primitive_param + 1);
1338 break;
1339 case nir_intrinsic_load_hs_patch_stride_ir3:
1340 dst[0] = create_uniform(b, primitive_param + 2);
1341 break;
1342 case nir_intrinsic_load_patch_vertices_in:
1343 dst[0] = create_uniform(b, primitive_param + 3);
1344 break;
1345 case nir_intrinsic_load_tess_param_base_ir3:
1346 dst[0] = create_uniform(b, primitive_param + 4);
1347 dst[1] = create_uniform(b, primitive_param + 5);
1348 break;
1349 case nir_intrinsic_load_tess_factor_base_ir3:
1350 dst[0] = create_uniform(b, primitive_param + 6);
1351 dst[1] = create_uniform(b, primitive_param + 7);
1352 break;
1353
1354 case nir_intrinsic_load_primitive_location_ir3:
1355 idx = nir_intrinsic_driver_location(intr);
1356 dst[0] = create_uniform(b, primitive_map + idx);
1357 break;
1358
1359 case nir_intrinsic_load_gs_header_ir3:
1360 dst[0] = ctx->gs_header;
1361 break;
1362 case nir_intrinsic_load_tcs_header_ir3:
1363 dst[0] = ctx->tcs_header;
1364 break;
1365
1366 case nir_intrinsic_load_primitive_id:
1367 dst[0] = ctx->primitive_id;
1368 break;
1369
1370 case nir_intrinsic_load_tess_coord:
1371 if (!ctx->tess_coord) {
1372 ctx->tess_coord =
1373 create_sysval_input(ctx, SYSTEM_VALUE_TESS_COORD, 0x3);
1374 }
1375 ir3_split_dest(b, dst, ctx->tess_coord, 0, 2);
1376
1377 /* Unused, but ir3_put_dst() below wants to free something */
1378 dst[2] = create_immed(b, 0);
1379 break;
1380
1381 case nir_intrinsic_end_patch_ir3:
1382 assert(ctx->so->type == MESA_SHADER_TESS_CTRL);
1383 struct ir3_instruction *end = ir3_ENDPATCH(b);
1384 array_insert(b, b->keeps, end);
1385
1386 end->barrier_class = IR3_BARRIER_EVERYTHING;
1387 end->barrier_conflict = IR3_BARRIER_EVERYTHING;
1388 break;
1389
1390 case nir_intrinsic_store_global_ir3: {
1391 struct ir3_instruction *value, *addr, *offset;
1392
1393 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1394 ir3_get_src(ctx, &intr->src[1])[0],
1395 ir3_get_src(ctx, &intr->src[1])[1]
1396 }, 2);
1397
1398 offset = ir3_get_src(ctx, &intr->src[2])[0];
1399
1400 value = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]),
1401 intr->num_components);
1402
1403 struct ir3_instruction *stg =
1404 ir3_STG_G(ctx->block, addr, 0, value, 0,
1405 create_immed(ctx->block, intr->num_components), 0, offset, 0);
1406 stg->cat6.type = TYPE_U32;
1407 stg->cat6.iim_val = 1;
1408
1409 array_insert(b, b->keeps, stg);
1410
1411 stg->barrier_class = IR3_BARRIER_BUFFER_W;
1412 stg->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1413 break;
1414 }
1415
1416 case nir_intrinsic_load_global_ir3: {
1417 struct ir3_instruction *addr, *offset;
1418
1419 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1420 ir3_get_src(ctx, &intr->src[0])[0],
1421 ir3_get_src(ctx, &intr->src[0])[1]
1422 }, 2);
1423
1424 offset = ir3_get_src(ctx, &intr->src[1])[0];
1425
1426 struct ir3_instruction *load =
1427 ir3_LDG(b, addr, 0, create_immed(ctx->block, intr->num_components),
1428 0, offset, 0);
1429 load->cat6.type = TYPE_U32;
1430 load->regs[0]->wrmask = MASK(intr->num_components);
1431
1432 load->barrier_class = IR3_BARRIER_BUFFER_R;
1433 load->barrier_conflict = IR3_BARRIER_BUFFER_W;
1434
1435 ir3_split_dest(b, dst, load, 0, intr->num_components);
1436 break;
1437 }
1438
1439 case nir_intrinsic_load_ubo:
1440 emit_intrinsic_load_ubo(ctx, intr, dst);
1441 break;
1442 case nir_intrinsic_load_frag_coord:
1443 ir3_split_dest(b, dst, get_frag_coord(ctx), 0, 4);
1444 break;
1445 case nir_intrinsic_load_sample_pos_from_id: {
1446 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1447 * but that doesn't seem necessary.
1448 */
1449 struct ir3_instruction *offset =
1450 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1451 offset->regs[0]->wrmask = 0x3;
1452 offset->cat5.type = TYPE_F32;
1453
1454 ir3_split_dest(b, dst, offset, 0, 2);
1455
1456 break;
1457 }
1458 case nir_intrinsic_load_size_ir3:
1459 if (!ctx->ij_size) {
1460 ctx->ij_size =
1461 create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_SIZE, 0x1);
1462 }
1463 dst[0] = ctx->ij_size;
1464 break;
1465 case nir_intrinsic_load_barycentric_centroid:
1466 ir3_split_dest(b, dst, get_barycentric_centroid(ctx), 0, 2);
1467 break;
1468 case nir_intrinsic_load_barycentric_sample:
1469 if (ctx->so->key.msaa) {
1470 ir3_split_dest(b, dst, get_barycentric_sample(ctx), 0, 2);
1471 } else {
1472 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1473 }
1474 break;
1475 case nir_intrinsic_load_barycentric_pixel:
1476 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1477 break;
1478 case nir_intrinsic_load_interpolated_input:
1479 idx = nir_intrinsic_base(intr);
1480 comp = nir_intrinsic_component(intr);
1481 src = ir3_get_src(ctx, &intr->src[0]);
1482 if (nir_src_is_const(intr->src[1])) {
1483 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1484 idx += nir_src_as_uint(intr->src[1]);
1485 for (int i = 0; i < intr->num_components; i++) {
1486 unsigned inloc = idx * 4 + i + comp;
1487 if (ctx->so->inputs[idx].bary &&
1488 !ctx->so->inputs[idx].use_ldlv) {
1489 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1490 } else {
1491 /* for non-varyings use the pre-setup input, since
1492 * that is easier than mapping things back to a
1493 * nir_variable to figure out what it is.
1494 */
1495 dst[i] = ctx->ir->inputs[inloc];
1496 }
1497 }
1498 } else {
1499 ir3_context_error(ctx, "unhandled");
1500 }
1501 break;
1502 case nir_intrinsic_load_input:
1503 idx = nir_intrinsic_base(intr);
1504 comp = nir_intrinsic_component(intr);
1505 if (nir_src_is_const(intr->src[0])) {
1506 idx += nir_src_as_uint(intr->src[0]);
1507 for (int i = 0; i < intr->num_components; i++) {
1508 unsigned n = idx * 4 + i + comp;
1509 dst[i] = ctx->inputs[n];
1510 compile_assert(ctx, ctx->inputs[n]);
1511 }
1512 } else {
1513 src = ir3_get_src(ctx, &intr->src[0]);
1514 struct ir3_instruction *collect =
1515 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ninputs);
1516 struct ir3_instruction *addr = ir3_get_addr(ctx, src[0], 4);
1517 for (int i = 0; i < intr->num_components; i++) {
1518 unsigned n = idx * 4 + i + comp;
1519 dst[i] = create_indirect_load(ctx, ctx->ninputs,
1520 n, addr, collect);
1521 }
1522 }
1523 break;
1524 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1525 * pass and replaced by an ir3-specifc version that adds the
1526 * dword-offset in the last source.
1527 */
1528 case nir_intrinsic_load_ssbo_ir3:
1529 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1530 break;
1531 case nir_intrinsic_store_ssbo_ir3:
1532 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1533 !ctx->s->info.fs.early_fragment_tests)
1534 ctx->so->no_earlyz = true;
1535 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1536 break;
1537 case nir_intrinsic_get_buffer_size:
1538 emit_intrinsic_ssbo_size(ctx, intr, dst);
1539 break;
1540 case nir_intrinsic_ssbo_atomic_add_ir3:
1541 case nir_intrinsic_ssbo_atomic_imin_ir3:
1542 case nir_intrinsic_ssbo_atomic_umin_ir3:
1543 case nir_intrinsic_ssbo_atomic_imax_ir3:
1544 case nir_intrinsic_ssbo_atomic_umax_ir3:
1545 case nir_intrinsic_ssbo_atomic_and_ir3:
1546 case nir_intrinsic_ssbo_atomic_or_ir3:
1547 case nir_intrinsic_ssbo_atomic_xor_ir3:
1548 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1549 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1550 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1551 !ctx->s->info.fs.early_fragment_tests)
1552 ctx->so->no_earlyz = true;
1553 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1554 break;
1555 case nir_intrinsic_load_shared:
1556 emit_intrinsic_load_shared(ctx, intr, dst);
1557 break;
1558 case nir_intrinsic_store_shared:
1559 emit_intrinsic_store_shared(ctx, intr);
1560 break;
1561 case nir_intrinsic_shared_atomic_add:
1562 case nir_intrinsic_shared_atomic_imin:
1563 case nir_intrinsic_shared_atomic_umin:
1564 case nir_intrinsic_shared_atomic_imax:
1565 case nir_intrinsic_shared_atomic_umax:
1566 case nir_intrinsic_shared_atomic_and:
1567 case nir_intrinsic_shared_atomic_or:
1568 case nir_intrinsic_shared_atomic_xor:
1569 case nir_intrinsic_shared_atomic_exchange:
1570 case nir_intrinsic_shared_atomic_comp_swap:
1571 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1572 break;
1573 case nir_intrinsic_image_deref_load:
1574 emit_intrinsic_load_image(ctx, intr, dst);
1575 break;
1576 case nir_intrinsic_image_deref_store:
1577 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1578 !ctx->s->info.fs.early_fragment_tests)
1579 ctx->so->no_earlyz = true;
1580 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1581 break;
1582 case nir_intrinsic_image_deref_size:
1583 emit_intrinsic_image_size(ctx, intr, dst);
1584 break;
1585 case nir_intrinsic_image_deref_atomic_add:
1586 case nir_intrinsic_image_deref_atomic_imin:
1587 case nir_intrinsic_image_deref_atomic_umin:
1588 case nir_intrinsic_image_deref_atomic_imax:
1589 case nir_intrinsic_image_deref_atomic_umax:
1590 case nir_intrinsic_image_deref_atomic_and:
1591 case nir_intrinsic_image_deref_atomic_or:
1592 case nir_intrinsic_image_deref_atomic_xor:
1593 case nir_intrinsic_image_deref_atomic_exchange:
1594 case nir_intrinsic_image_deref_atomic_comp_swap:
1595 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1596 !ctx->s->info.fs.early_fragment_tests)
1597 ctx->so->no_earlyz = true;
1598 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1599 break;
1600 case nir_intrinsic_barrier:
1601 case nir_intrinsic_memory_barrier:
1602 case nir_intrinsic_group_memory_barrier:
1603 case nir_intrinsic_memory_barrier_atomic_counter:
1604 case nir_intrinsic_memory_barrier_buffer:
1605 case nir_intrinsic_memory_barrier_image:
1606 case nir_intrinsic_memory_barrier_shared:
1607 emit_intrinsic_barrier(ctx, intr);
1608 /* note that blk ptr no longer valid, make that obvious: */
1609 b = NULL;
1610 break;
1611 case nir_intrinsic_store_output:
1612 idx = nir_intrinsic_base(intr);
1613 comp = nir_intrinsic_component(intr);
1614 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1615 idx += nir_src_as_uint(intr->src[1]);
1616
1617 src = ir3_get_src(ctx, &intr->src[0]);
1618 for (int i = 0; i < intr->num_components; i++) {
1619 unsigned n = idx * 4 + i + comp;
1620 ctx->outputs[n] = src[i];
1621 }
1622 break;
1623 case nir_intrinsic_load_base_vertex:
1624 case nir_intrinsic_load_first_vertex:
1625 if (!ctx->basevertex) {
1626 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1627 }
1628 dst[0] = ctx->basevertex;
1629 break;
1630 case nir_intrinsic_load_vertex_id_zero_base:
1631 case nir_intrinsic_load_vertex_id:
1632 if (!ctx->vertex_id) {
1633 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1634 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1635 ctx->vertex_id = create_sysval_input(ctx, sv, 0x1);
1636 }
1637 dst[0] = ctx->vertex_id;
1638 break;
1639 case nir_intrinsic_load_instance_id:
1640 if (!ctx->instance_id) {
1641 ctx->instance_id = create_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID, 0x1);
1642 }
1643 dst[0] = ctx->instance_id;
1644 break;
1645 case nir_intrinsic_load_sample_id:
1646 ctx->so->per_samp = true;
1647 /* fall-thru */
1648 case nir_intrinsic_load_sample_id_no_per_sample:
1649 if (!ctx->samp_id) {
1650 ctx->samp_id = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID, 0x1);
1651 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1652 }
1653 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1654 break;
1655 case nir_intrinsic_load_sample_mask_in:
1656 if (!ctx->samp_mask_in) {
1657 ctx->samp_mask_in = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN, 0x1);
1658 }
1659 dst[0] = ctx->samp_mask_in;
1660 break;
1661 case nir_intrinsic_load_user_clip_plane:
1662 idx = nir_intrinsic_ucp_id(intr);
1663 for (int i = 0; i < intr->num_components; i++) {
1664 unsigned n = idx * 4 + i;
1665 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1666 }
1667 break;
1668 case nir_intrinsic_load_front_face:
1669 if (!ctx->frag_face) {
1670 ctx->so->frag_face = true;
1671 ctx->frag_face = create_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, 0x1);
1672 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1673 }
1674 /* for fragface, we get -1 for back and 0 for front. However this is
1675 * the inverse of what nir expects (where ~0 is true).
1676 */
1677 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1678 dst[0] = ir3_NOT_B(b, dst[0], 0);
1679 break;
1680 case nir_intrinsic_load_local_invocation_id:
1681 if (!ctx->local_invocation_id) {
1682 ctx->local_invocation_id =
1683 create_sysval_input(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID, 0x7);
1684 }
1685 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1686 break;
1687 case nir_intrinsic_load_work_group_id:
1688 if (!ctx->work_group_id) {
1689 ctx->work_group_id =
1690 create_sysval_input(ctx, SYSTEM_VALUE_WORK_GROUP_ID, 0x7);
1691 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1692 }
1693 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1694 break;
1695 case nir_intrinsic_load_num_work_groups:
1696 for (int i = 0; i < intr->num_components; i++) {
1697 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1698 }
1699 break;
1700 case nir_intrinsic_load_local_group_size:
1701 for (int i = 0; i < intr->num_components; i++) {
1702 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1703 }
1704 break;
1705 case nir_intrinsic_discard_if:
1706 case nir_intrinsic_discard: {
1707 struct ir3_instruction *cond, *kill;
1708
1709 if (intr->intrinsic == nir_intrinsic_discard_if) {
1710 /* conditional discard: */
1711 src = ir3_get_src(ctx, &intr->src[0]);
1712 cond = ir3_b2n(b, src[0]);
1713 } else {
1714 /* unconditional discard: */
1715 cond = create_immed(b, 1);
1716 }
1717
1718 /* NOTE: only cmps.*.* can write p0.x: */
1719 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1720 cond->cat2.condition = IR3_COND_NE;
1721
1722 /* condition always goes in predicate register: */
1723 cond->regs[0]->num = regid(REG_P0, 0);
1724 cond->regs[0]->flags &= ~IR3_REG_SSA;
1725
1726 kill = ir3_KILL(b, cond, 0);
1727 array_insert(ctx->ir, ctx->ir->predicates, kill);
1728
1729 array_insert(b, b->keeps, kill);
1730 ctx->so->no_earlyz = true;
1731
1732 break;
1733 }
1734
1735 case nir_intrinsic_cond_end_ir3: {
1736 struct ir3_instruction *cond, *kill;
1737
1738 src = ir3_get_src(ctx, &intr->src[0]);
1739 cond = ir3_b2n(b, src[0]);
1740
1741 /* NOTE: only cmps.*.* can write p0.x: */
1742 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1743 cond->cat2.condition = IR3_COND_NE;
1744
1745 /* condition always goes in predicate register: */
1746 cond->regs[0]->num = regid(REG_P0, 0);
1747
1748 kill = ir3_CONDEND(b, cond, 0);
1749
1750 kill->barrier_class = IR3_BARRIER_EVERYTHING;
1751 kill->barrier_conflict = IR3_BARRIER_EVERYTHING;
1752
1753 array_insert(ctx->ir, ctx->ir->predicates, kill);
1754 array_insert(b, b->keeps, kill);
1755 break;
1756 }
1757
1758 case nir_intrinsic_load_shared_ir3:
1759 emit_intrinsic_load_shared_ir3(ctx, intr, dst);
1760 break;
1761 case nir_intrinsic_store_shared_ir3:
1762 emit_intrinsic_store_shared_ir3(ctx, intr);
1763 break;
1764 default:
1765 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1766 nir_intrinsic_infos[intr->intrinsic].name);
1767 break;
1768 }
1769
1770 if (info->has_dest)
1771 ir3_put_dst(ctx, &intr->dest);
1772 }
1773
1774 static void
1775 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1776 {
1777 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1778 instr->def.num_components);
1779
1780 if (instr->def.bit_size < 32) {
1781 for (int i = 0; i < instr->def.num_components; i++)
1782 dst[i] = create_immed_typed(ctx->block,
1783 instr->value[i].u16,
1784 TYPE_U16);
1785 } else {
1786 for (int i = 0; i < instr->def.num_components; i++)
1787 dst[i] = create_immed_typed(ctx->block,
1788 instr->value[i].u32,
1789 TYPE_U32);
1790 }
1791
1792 }
1793
1794 static void
1795 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1796 {
1797 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1798 undef->def.num_components);
1799 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1800
1801 /* backend doesn't want undefined instructions, so just plug
1802 * in 0.0..
1803 */
1804 for (int i = 0; i < undef->def.num_components; i++)
1805 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1806 }
1807
1808 /*
1809 * texture fetch/sample instructions:
1810 */
1811
1812 static void
1813 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1814 {
1815 unsigned coords, flags = 0;
1816
1817 /* note: would use tex->coord_components.. except txs.. also,
1818 * since array index goes after shadow ref, we don't want to
1819 * count it:
1820 */
1821 switch (tex->sampler_dim) {
1822 case GLSL_SAMPLER_DIM_1D:
1823 case GLSL_SAMPLER_DIM_BUF:
1824 coords = 1;
1825 break;
1826 case GLSL_SAMPLER_DIM_2D:
1827 case GLSL_SAMPLER_DIM_RECT:
1828 case GLSL_SAMPLER_DIM_EXTERNAL:
1829 case GLSL_SAMPLER_DIM_MS:
1830 coords = 2;
1831 break;
1832 case GLSL_SAMPLER_DIM_3D:
1833 case GLSL_SAMPLER_DIM_CUBE:
1834 coords = 3;
1835 flags |= IR3_INSTR_3D;
1836 break;
1837 default:
1838 unreachable("bad sampler_dim");
1839 }
1840
1841 if (tex->is_shadow && tex->op != nir_texop_lod)
1842 flags |= IR3_INSTR_S;
1843
1844 if (tex->is_array && tex->op != nir_texop_lod)
1845 flags |= IR3_INSTR_A;
1846
1847 *flagsp = flags;
1848 *coordsp = coords;
1849 }
1850
1851 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
1852 * or immediate (in which case it will get lowered later to a non .s2en
1853 * version of the tex instruction which encode tex/samp as immediates:
1854 */
1855 static struct ir3_instruction *
1856 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
1857 {
1858 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
1859 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
1860 struct ir3_instruction *texture, *sampler;
1861
1862 if (texture_idx >= 0) {
1863 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
1864 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
1865 } else {
1866 /* TODO what to do for dynamic case? I guess we only need the
1867 * max index for astc srgb workaround so maybe not a problem
1868 * to worry about if we don't enable indirect samplers for
1869 * a4xx?
1870 */
1871 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
1872 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
1873 }
1874
1875 if (sampler_idx >= 0) {
1876 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
1877 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
1878 } else {
1879 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
1880 }
1881
1882 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1883 sampler,
1884 texture,
1885 }, 2);
1886 }
1887
1888 static void
1889 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
1890 {
1891 struct ir3_block *b = ctx->block;
1892 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1893 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
1894 struct ir3_instruction *lod, *compare, *proj, *sample_index;
1895 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1896 unsigned i, coords, flags, ncomp;
1897 unsigned nsrc0 = 0, nsrc1 = 0;
1898 type_t type;
1899 opc_t opc = 0;
1900
1901 ncomp = nir_dest_num_components(tex->dest);
1902
1903 coord = off = ddx = ddy = NULL;
1904 lod = proj = compare = sample_index = NULL;
1905
1906 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
1907
1908 for (unsigned i = 0; i < tex->num_srcs; i++) {
1909 switch (tex->src[i].src_type) {
1910 case nir_tex_src_coord:
1911 coord = ir3_get_src(ctx, &tex->src[i].src);
1912 break;
1913 case nir_tex_src_bias:
1914 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1915 has_bias = true;
1916 break;
1917 case nir_tex_src_lod:
1918 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1919 has_lod = true;
1920 break;
1921 case nir_tex_src_comparator: /* shadow comparator */
1922 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
1923 break;
1924 case nir_tex_src_projector:
1925 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
1926 has_proj = true;
1927 break;
1928 case nir_tex_src_offset:
1929 off = ir3_get_src(ctx, &tex->src[i].src);
1930 has_off = true;
1931 break;
1932 case nir_tex_src_ddx:
1933 ddx = ir3_get_src(ctx, &tex->src[i].src);
1934 break;
1935 case nir_tex_src_ddy:
1936 ddy = ir3_get_src(ctx, &tex->src[i].src);
1937 break;
1938 case nir_tex_src_ms_index:
1939 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
1940 break;
1941 case nir_tex_src_texture_offset:
1942 case nir_tex_src_sampler_offset:
1943 /* handled in get_tex_samp_src() */
1944 break;
1945 default:
1946 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
1947 tex->src[i].src_type);
1948 return;
1949 }
1950 }
1951
1952 switch (tex->op) {
1953 case nir_texop_tex_prefetch:
1954 compile_assert(ctx, !has_bias);
1955 compile_assert(ctx, !has_lod);
1956 compile_assert(ctx, !compare);
1957 compile_assert(ctx, !has_proj);
1958 compile_assert(ctx, !has_off);
1959 compile_assert(ctx, !ddx);
1960 compile_assert(ctx, !ddy);
1961 compile_assert(ctx, !sample_index);
1962 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_texture_offset) < 0);
1963 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset) < 0);
1964
1965 if (ctx->so->num_sampler_prefetch < IR3_MAX_SAMPLER_PREFETCH) {
1966 opc = OPC_META_TEX_PREFETCH;
1967 ctx->so->num_sampler_prefetch++;
1968 break;
1969 }
1970 /* fallthru */
1971 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
1972 case nir_texop_txb: opc = OPC_SAMB; break;
1973 case nir_texop_txl: opc = OPC_SAML; break;
1974 case nir_texop_txd: opc = OPC_SAMGQ; break;
1975 case nir_texop_txf: opc = OPC_ISAML; break;
1976 case nir_texop_lod: opc = OPC_GETLOD; break;
1977 case nir_texop_tg4:
1978 /* NOTE: a4xx might need to emulate gather w/ txf (this is
1979 * what blob does, seems gather is broken?), and a3xx did
1980 * not support it (but probably could also emulate).
1981 */
1982 switch (tex->component) {
1983 case 0: opc = OPC_GATHER4R; break;
1984 case 1: opc = OPC_GATHER4G; break;
1985 case 2: opc = OPC_GATHER4B; break;
1986 case 3: opc = OPC_GATHER4A; break;
1987 }
1988 break;
1989 case nir_texop_txf_ms_fb:
1990 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
1991 default:
1992 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
1993 return;
1994 }
1995
1996 tex_info(tex, &flags, &coords);
1997
1998 /*
1999 * lay out the first argument in the proper order:
2000 * - actual coordinates first
2001 * - shadow reference
2002 * - array index
2003 * - projection w
2004 * - starting at offset 4, dpdx.xy, dpdy.xy
2005 *
2006 * bias/lod go into the second arg
2007 */
2008
2009 /* insert tex coords: */
2010 for (i = 0; i < coords; i++)
2011 src0[i] = coord[i];
2012
2013 nsrc0 = i;
2014
2015 /* scale up integer coords for TXF based on the LOD */
2016 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
2017 assert(has_lod);
2018 for (i = 0; i < coords; i++)
2019 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
2020 }
2021
2022 if (coords == 1) {
2023 /* hw doesn't do 1d, so we treat it as 2d with
2024 * height of 1, and patch up the y coord.
2025 */
2026 if (is_isam(opc)) {
2027 src0[nsrc0++] = create_immed(b, 0);
2028 } else {
2029 src0[nsrc0++] = create_immed(b, fui(0.5));
2030 }
2031 }
2032
2033 if (tex->is_shadow && tex->op != nir_texop_lod)
2034 src0[nsrc0++] = compare;
2035
2036 if (tex->is_array && tex->op != nir_texop_lod) {
2037 struct ir3_instruction *idx = coord[coords];
2038
2039 /* the array coord for cube arrays needs 0.5 added to it */
2040 if (ctx->compiler->array_index_add_half && !is_isam(opc))
2041 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
2042
2043 src0[nsrc0++] = idx;
2044 }
2045
2046 if (has_proj) {
2047 src0[nsrc0++] = proj;
2048 flags |= IR3_INSTR_P;
2049 }
2050
2051 /* pad to 4, then ddx/ddy: */
2052 if (tex->op == nir_texop_txd) {
2053 while (nsrc0 < 4)
2054 src0[nsrc0++] = create_immed(b, fui(0.0));
2055 for (i = 0; i < coords; i++)
2056 src0[nsrc0++] = ddx[i];
2057 if (coords < 2)
2058 src0[nsrc0++] = create_immed(b, fui(0.0));
2059 for (i = 0; i < coords; i++)
2060 src0[nsrc0++] = ddy[i];
2061 if (coords < 2)
2062 src0[nsrc0++] = create_immed(b, fui(0.0));
2063 }
2064
2065 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2066 * with scaled x coord according to requested sample:
2067 */
2068 if (opc == OPC_ISAMM) {
2069 if (ctx->compiler->txf_ms_with_isaml) {
2070 /* the samples are laid out in x dimension as
2071 * 0 1 2 3
2072 * x_ms = (x << ms) + sample_index;
2073 */
2074 struct ir3_instruction *ms;
2075 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
2076
2077 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
2078 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
2079
2080 opc = OPC_ISAML;
2081 } else {
2082 src0[nsrc0++] = sample_index;
2083 }
2084 }
2085
2086 /*
2087 * second argument (if applicable):
2088 * - offsets
2089 * - lod
2090 * - bias
2091 */
2092 if (has_off | has_lod | has_bias) {
2093 if (has_off) {
2094 unsigned off_coords = coords;
2095 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2096 off_coords--;
2097 for (i = 0; i < off_coords; i++)
2098 src1[nsrc1++] = off[i];
2099 if (off_coords < 2)
2100 src1[nsrc1++] = create_immed(b, fui(0.0));
2101 flags |= IR3_INSTR_O;
2102 }
2103
2104 if (has_lod | has_bias)
2105 src1[nsrc1++] = lod;
2106 }
2107
2108 switch (tex->dest_type) {
2109 case nir_type_invalid:
2110 case nir_type_float:
2111 type = TYPE_F32;
2112 break;
2113 case nir_type_int:
2114 type = TYPE_S32;
2115 break;
2116 case nir_type_uint:
2117 case nir_type_bool:
2118 type = TYPE_U32;
2119 break;
2120 default:
2121 unreachable("bad dest_type");
2122 }
2123
2124 if (opc == OPC_GETLOD)
2125 type = TYPE_S32;
2126
2127 struct ir3_instruction *samp_tex;
2128
2129 if (tex->op == nir_texop_txf_ms_fb) {
2130 /* only expect a single txf_ms_fb per shader: */
2131 compile_assert(ctx, !ctx->so->fb_read);
2132 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
2133
2134 ctx->so->fb_read = true;
2135 samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2136 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2137 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2138 }, 2);
2139
2140 ctx->so->num_samp++;
2141 } else {
2142 samp_tex = get_tex_samp_tex_src(ctx, tex);
2143 }
2144
2145 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
2146 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
2147
2148 if (opc == OPC_META_TEX_PREFETCH) {
2149 int idx = nir_tex_instr_src_index(tex, nir_tex_src_coord);
2150
2151 compile_assert(ctx, tex->src[idx].src.is_ssa);
2152
2153 sam = ir3_META_TEX_PREFETCH(b);
2154 __ssa_dst(sam)->wrmask = MASK(ncomp); /* dst */
2155 sam->prefetch.input_offset =
2156 ir3_nir_coord_offset(tex->src[idx].src.ssa);
2157 sam->prefetch.tex = tex->texture_index;
2158 sam->prefetch.samp = tex->sampler_index;
2159 } else {
2160 sam = ir3_SAM(b, opc, type, MASK(ncomp), flags,
2161 samp_tex, col0, col1);
2162 }
2163
2164 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
2165 assert(opc != OPC_META_TEX_PREFETCH);
2166
2167 /* only need first 3 components: */
2168 sam->regs[0]->wrmask = 0x7;
2169 ir3_split_dest(b, dst, sam, 0, 3);
2170
2171 /* we need to sample the alpha separately with a non-ASTC
2172 * texture state:
2173 */
2174 sam = ir3_SAM(b, opc, type, 0b1000, flags,
2175 samp_tex, col0, col1);
2176
2177 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
2178
2179 /* fixup .w component: */
2180 ir3_split_dest(b, &dst[3], sam, 3, 1);
2181 } else {
2182 /* normal (non-workaround) case: */
2183 ir3_split_dest(b, dst, sam, 0, ncomp);
2184 }
2185
2186 /* GETLOD returns results in 4.8 fixed point */
2187 if (opc == OPC_GETLOD) {
2188 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
2189
2190 compile_assert(ctx, tex->dest_type == nir_type_float);
2191 for (i = 0; i < 2; i++) {
2192 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_S32, TYPE_F32), 0,
2193 factor, 0);
2194 }
2195 }
2196
2197 ir3_put_dst(ctx, &tex->dest);
2198 }
2199
2200 static void
2201 emit_tex_info(struct ir3_context *ctx, nir_tex_instr *tex, unsigned idx)
2202 {
2203 struct ir3_block *b = ctx->block;
2204 struct ir3_instruction **dst, *sam;
2205
2206 dst = ir3_get_dst(ctx, &tex->dest, 1);
2207
2208 sam = ir3_SAM(b, OPC_GETINFO, TYPE_U32, 1 << idx, 0,
2209 get_tex_samp_tex_src(ctx, tex), NULL, NULL);
2210
2211 /* even though there is only one component, since it ends
2212 * up in .y/.z/.w rather than .x, we need a split_dest()
2213 */
2214 if (idx)
2215 ir3_split_dest(b, dst, sam, 0, idx + 1);
2216
2217 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2218 * the value in TEX_CONST_0 is zero-based.
2219 */
2220 if (ctx->compiler->levels_add_one)
2221 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2222
2223 ir3_put_dst(ctx, &tex->dest);
2224 }
2225
2226 static void
2227 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2228 {
2229 struct ir3_block *b = ctx->block;
2230 struct ir3_instruction **dst, *sam;
2231 struct ir3_instruction *lod;
2232 unsigned flags, coords;
2233
2234 tex_info(tex, &flags, &coords);
2235
2236 /* Actually we want the number of dimensions, not coordinates. This
2237 * distinction only matters for cubes.
2238 */
2239 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2240 coords = 2;
2241
2242 dst = ir3_get_dst(ctx, &tex->dest, 4);
2243
2244 compile_assert(ctx, tex->num_srcs == 1);
2245 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
2246
2247 lod = ir3_get_src(ctx, &tex->src[0].src)[0];
2248
2249 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
2250 get_tex_samp_tex_src(ctx, tex), lod, NULL);
2251
2252 ir3_split_dest(b, dst, sam, 0, 4);
2253
2254 /* Array size actually ends up in .w rather than .z. This doesn't
2255 * matter for miplevel 0, but for higher mips the value in z is
2256 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2257 * returned, which means that we have to add 1 to it for arrays.
2258 */
2259 if (tex->is_array) {
2260 if (ctx->compiler->levels_add_one) {
2261 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2262 } else {
2263 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2264 }
2265 }
2266
2267 ir3_put_dst(ctx, &tex->dest);
2268 }
2269
2270 static void
2271 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2272 {
2273 switch (jump->type) {
2274 case nir_jump_break:
2275 case nir_jump_continue:
2276 case nir_jump_return:
2277 /* I *think* we can simply just ignore this, and use the
2278 * successor block link to figure out where we need to
2279 * jump to for break/continue
2280 */
2281 break;
2282 default:
2283 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2284 break;
2285 }
2286 }
2287
2288 static void
2289 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2290 {
2291 switch (instr->type) {
2292 case nir_instr_type_alu:
2293 emit_alu(ctx, nir_instr_as_alu(instr));
2294 break;
2295 case nir_instr_type_deref:
2296 /* ignored, handled as part of the intrinsic they are src to */
2297 break;
2298 case nir_instr_type_intrinsic:
2299 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2300 break;
2301 case nir_instr_type_load_const:
2302 emit_load_const(ctx, nir_instr_as_load_const(instr));
2303 break;
2304 case nir_instr_type_ssa_undef:
2305 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2306 break;
2307 case nir_instr_type_tex: {
2308 nir_tex_instr *tex = nir_instr_as_tex(instr);
2309 /* couple tex instructions get special-cased:
2310 */
2311 switch (tex->op) {
2312 case nir_texop_txs:
2313 emit_tex_txs(ctx, tex);
2314 break;
2315 case nir_texop_query_levels:
2316 emit_tex_info(ctx, tex, 2);
2317 break;
2318 case nir_texop_texture_samples:
2319 emit_tex_info(ctx, tex, 3);
2320 break;
2321 default:
2322 emit_tex(ctx, tex);
2323 break;
2324 }
2325 break;
2326 }
2327 case nir_instr_type_jump:
2328 emit_jump(ctx, nir_instr_as_jump(instr));
2329 break;
2330 case nir_instr_type_phi:
2331 /* we have converted phi webs to regs in NIR by now */
2332 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2333 break;
2334 case nir_instr_type_call:
2335 case nir_instr_type_parallel_copy:
2336 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2337 break;
2338 }
2339 }
2340
2341 static struct ir3_block *
2342 get_block(struct ir3_context *ctx, const nir_block *nblock)
2343 {
2344 struct ir3_block *block;
2345 struct hash_entry *hentry;
2346
2347 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2348 if (hentry)
2349 return hentry->data;
2350
2351 block = ir3_block_create(ctx->ir);
2352 block->nblock = nblock;
2353 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2354
2355 block->predecessors = _mesa_pointer_set_create(block);
2356 set_foreach(nblock->predecessors, sentry) {
2357 _mesa_set_add(block->predecessors, get_block(ctx, sentry->key));
2358 }
2359
2360 return block;
2361 }
2362
2363 static void
2364 emit_block(struct ir3_context *ctx, nir_block *nblock)
2365 {
2366 struct ir3_block *block = get_block(ctx, nblock);
2367
2368 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2369 if (nblock->successors[i]) {
2370 block->successors[i] =
2371 get_block(ctx, nblock->successors[i]);
2372 }
2373 }
2374
2375 ctx->block = block;
2376 list_addtail(&block->node, &ctx->ir->block_list);
2377
2378 /* re-emit addr register in each block if needed: */
2379 for (int i = 0; i < ARRAY_SIZE(ctx->addr_ht); i++) {
2380 _mesa_hash_table_destroy(ctx->addr_ht[i], NULL);
2381 ctx->addr_ht[i] = NULL;
2382 }
2383
2384 nir_foreach_instr(instr, nblock) {
2385 ctx->cur_instr = instr;
2386 emit_instr(ctx, instr);
2387 ctx->cur_instr = NULL;
2388 if (ctx->error)
2389 return;
2390 }
2391 }
2392
2393 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2394
2395 static void
2396 emit_if(struct ir3_context *ctx, nir_if *nif)
2397 {
2398 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2399
2400 ctx->block->condition =
2401 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
2402
2403 emit_cf_list(ctx, &nif->then_list);
2404 emit_cf_list(ctx, &nif->else_list);
2405 }
2406
2407 static void
2408 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2409 {
2410 emit_cf_list(ctx, &nloop->body);
2411 ctx->so->loops++;
2412 }
2413
2414 static void
2415 stack_push(struct ir3_context *ctx)
2416 {
2417 ctx->stack++;
2418 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2419 }
2420
2421 static void
2422 stack_pop(struct ir3_context *ctx)
2423 {
2424 compile_assert(ctx, ctx->stack > 0);
2425 ctx->stack--;
2426 }
2427
2428 static void
2429 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2430 {
2431 foreach_list_typed(nir_cf_node, node, node, list) {
2432 switch (node->type) {
2433 case nir_cf_node_block:
2434 emit_block(ctx, nir_cf_node_as_block(node));
2435 break;
2436 case nir_cf_node_if:
2437 stack_push(ctx);
2438 emit_if(ctx, nir_cf_node_as_if(node));
2439 stack_pop(ctx);
2440 break;
2441 case nir_cf_node_loop:
2442 stack_push(ctx);
2443 emit_loop(ctx, nir_cf_node_as_loop(node));
2444 stack_pop(ctx);
2445 break;
2446 case nir_cf_node_function:
2447 ir3_context_error(ctx, "TODO\n");
2448 break;
2449 }
2450 }
2451 }
2452
2453 /* emit stream-out code. At this point, the current block is the original
2454 * (nir) end block, and nir ensures that all flow control paths terminate
2455 * into the end block. We re-purpose the original end block to generate
2456 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2457 * block holding stream-out write instructions, followed by the new end
2458 * block:
2459 *
2460 * blockOrigEnd {
2461 * p0.x = (vtxcnt < maxvtxcnt)
2462 * // succs: blockStreamOut, blockNewEnd
2463 * }
2464 * blockStreamOut {
2465 * ... stream-out instructions ...
2466 * // succs: blockNewEnd
2467 * }
2468 * blockNewEnd {
2469 * }
2470 */
2471 static void
2472 emit_stream_out(struct ir3_context *ctx)
2473 {
2474 struct ir3 *ir = ctx->ir;
2475 struct ir3_stream_output_info *strmout =
2476 &ctx->so->shader->stream_output;
2477 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2478 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2479 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2480
2481 /* create vtxcnt input in input block at top of shader,
2482 * so that it is seen as live over the entire duration
2483 * of the shader:
2484 */
2485 vtxcnt = create_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, 0x1);
2486 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2487
2488 /* at this point, we are at the original 'end' block,
2489 * re-purpose this block to stream-out condition, then
2490 * append stream-out block and new-end block
2491 */
2492 orig_end_block = ctx->block;
2493
2494 // TODO these blocks need to update predecessors..
2495 // maybe w/ store_global intrinsic, we could do this
2496 // stuff in nir->nir pass
2497
2498 stream_out_block = ir3_block_create(ir);
2499 list_addtail(&stream_out_block->node, &ir->block_list);
2500
2501 new_end_block = ir3_block_create(ir);
2502 list_addtail(&new_end_block->node, &ir->block_list);
2503
2504 orig_end_block->successors[0] = stream_out_block;
2505 orig_end_block->successors[1] = new_end_block;
2506 stream_out_block->successors[0] = new_end_block;
2507
2508 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2509 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2510 cond->regs[0]->num = regid(REG_P0, 0);
2511 cond->regs[0]->flags &= ~IR3_REG_SSA;
2512 cond->cat2.condition = IR3_COND_LT;
2513
2514 /* condition goes on previous block to the conditional,
2515 * since it is used to pick which of the two successor
2516 * paths to take:
2517 */
2518 orig_end_block->condition = cond;
2519
2520 /* switch to stream_out_block to generate the stream-out
2521 * instructions:
2522 */
2523 ctx->block = stream_out_block;
2524
2525 /* Calculate base addresses based on vtxcnt. Instructions
2526 * generated for bases not used in following loop will be
2527 * stripped out in the backend.
2528 */
2529 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2530 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
2531 unsigned stride = strmout->stride[i];
2532 struct ir3_instruction *base, *off;
2533
2534 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
2535
2536 /* 24-bit should be enough: */
2537 off = ir3_MUL_U24(ctx->block, vtxcnt, 0,
2538 create_immed(ctx->block, stride * 4), 0);
2539
2540 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2541 }
2542
2543 /* Generate the per-output store instructions: */
2544 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2545 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2546 unsigned c = j + strmout->output[i].start_component;
2547 struct ir3_instruction *base, *out, *stg;
2548
2549 base = bases[strmout->output[i].output_buffer];
2550 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2551
2552 stg = ir3_STG(ctx->block, base, 0, out, 0,
2553 create_immed(ctx->block, 1), 0);
2554 stg->cat6.type = TYPE_U32;
2555 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2556
2557 array_insert(ctx->block, ctx->block->keeps, stg);
2558 }
2559 }
2560
2561 /* and finally switch to the new_end_block: */
2562 ctx->block = new_end_block;
2563 }
2564
2565 static void
2566 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2567 {
2568 nir_metadata_require(impl, nir_metadata_block_index);
2569
2570 compile_assert(ctx, ctx->stack == 0);
2571
2572 emit_cf_list(ctx, &impl->body);
2573 emit_block(ctx, impl->end_block);
2574
2575 compile_assert(ctx, ctx->stack == 0);
2576
2577 /* at this point, we should have a single empty block,
2578 * into which we emit the 'end' instruction.
2579 */
2580 compile_assert(ctx, list_is_empty(&ctx->block->instr_list));
2581
2582 /* If stream-out (aka transform-feedback) enabled, emit the
2583 * stream-out instructions, followed by a new empty block (into
2584 * which the 'end' instruction lands).
2585 *
2586 * NOTE: it is done in this order, rather than inserting before
2587 * we emit end_block, because NIR guarantees that all blocks
2588 * flow into end_block, and that end_block has no successors.
2589 * So by re-purposing end_block as the first block of stream-
2590 * out, we guarantee that all exit paths flow into the stream-
2591 * out instructions.
2592 */
2593 if ((ctx->compiler->gpu_id < 500) &&
2594 (ctx->so->shader->stream_output.num_outputs > 0) &&
2595 !ctx->so->binning_pass) {
2596 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2597 emit_stream_out(ctx);
2598 }
2599
2600 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2601 * NOP and has an epilogue that writes the VS outputs to local storage, to
2602 * be read by the HS. Then it resets execution mask (chmask) and chains
2603 * to the next shader (chsh).
2604 */
2605 if ((ctx->so->type == MESA_SHADER_VERTEX &&
2606 (ctx->so->key.has_gs || ctx->so->key.tessellation)) ||
2607 (ctx->so->type == MESA_SHADER_TESS_EVAL && ctx->so->key.has_gs)) {
2608 struct ir3_instruction *chmask =
2609 ir3_CHMASK(ctx->block);
2610 chmask->barrier_class = IR3_BARRIER_EVERYTHING;
2611 chmask->barrier_conflict = IR3_BARRIER_EVERYTHING;
2612
2613 struct ir3_instruction *chsh =
2614 ir3_CHSH(ctx->block);
2615 chsh->barrier_class = IR3_BARRIER_EVERYTHING;
2616 chsh->barrier_conflict = IR3_BARRIER_EVERYTHING;
2617 } else {
2618 ir3_END(ctx->block);
2619 }
2620 }
2621
2622 static void
2623 setup_input(struct ir3_context *ctx, nir_variable *in)
2624 {
2625 struct ir3_shader_variant *so = ctx->so;
2626 unsigned ncomp = glsl_get_components(in->type);
2627 unsigned n = in->data.driver_location;
2628 unsigned frac = in->data.location_frac;
2629 unsigned slot = in->data.location;
2630
2631 /* Inputs are loaded using ldlw or ldg for these stages. */
2632 if (ctx->so->type == MESA_SHADER_TESS_CTRL ||
2633 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2634 ctx->so->type == MESA_SHADER_GEOMETRY)
2635 return;
2636
2637 /* skip unread inputs, we could end up with (for example), unsplit
2638 * matrix/etc inputs in the case they are not read, so just silently
2639 * skip these.
2640 */
2641 if (ncomp > 4)
2642 return;
2643
2644 so->inputs[n].slot = slot;
2645 so->inputs[n].compmask = (1 << (ncomp + frac)) - 1;
2646 so->inputs_count = MAX2(so->inputs_count, n + 1);
2647 so->inputs[n].interpolate = in->data.interpolation;
2648
2649 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2650
2651 /* if any varyings have 'sample' qualifer, that triggers us
2652 * to run in per-sample mode:
2653 */
2654 so->per_samp |= in->data.sample;
2655
2656 for (int i = 0; i < ncomp; i++) {
2657 struct ir3_instruction *instr = NULL;
2658 unsigned idx = (n * 4) + i + frac;
2659
2660 if (slot == VARYING_SLOT_POS) {
2661 ir3_context_error(ctx, "fragcoord should be a sysval!\n");
2662 } else if (slot == VARYING_SLOT_PNTC) {
2663 /* see for example st_nir_fixup_varying_slots().. this is
2664 * maybe a bit mesa/st specific. But we need things to line
2665 * up for this in fdN_program:
2666 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2667 * if (emit->sprite_coord_enable & texmask) {
2668 * ...
2669 * }
2670 */
2671 so->inputs[n].slot = VARYING_SLOT_VAR8;
2672 so->inputs[n].bary = true;
2673 instr = create_frag_input(ctx, false, idx);
2674 } else {
2675 /* detect the special case for front/back colors where
2676 * we need to do flat vs smooth shading depending on
2677 * rast state:
2678 */
2679 if (in->data.interpolation == INTERP_MODE_NONE) {
2680 switch (slot) {
2681 case VARYING_SLOT_COL0:
2682 case VARYING_SLOT_COL1:
2683 case VARYING_SLOT_BFC0:
2684 case VARYING_SLOT_BFC1:
2685 so->inputs[n].rasterflat = true;
2686 break;
2687 default:
2688 break;
2689 }
2690 }
2691
2692 if (ctx->compiler->flat_bypass) {
2693 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2694 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2695 so->inputs[n].use_ldlv = true;
2696 }
2697
2698 so->inputs[n].bary = true;
2699
2700 instr = create_frag_input(ctx, so->inputs[n].use_ldlv, idx);
2701 }
2702
2703 compile_assert(ctx, idx < ctx->ninputs);
2704
2705 ctx->inputs[idx] = instr;
2706 }
2707 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2708 /* We shouldn't have fractional input for VS input.. that only shows
2709 * up with varying packing
2710 */
2711 assert(frac == 0);
2712
2713 struct ir3_instruction *input = create_input(ctx, (1 << ncomp) - 1);
2714 struct ir3_instruction *components[ncomp];
2715
2716 input->input.inidx = n;
2717
2718 ir3_split_dest(ctx->block, components, input, 0, ncomp);
2719
2720 for (int i = 0; i < ncomp; i++) {
2721 unsigned idx = (n * 4) + i + frac;
2722 compile_assert(ctx, idx < ctx->ninputs);
2723 ctx->inputs[idx] = components[i];
2724 }
2725 } else {
2726 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2727 }
2728
2729 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
2730 so->total_in += ncomp;
2731 }
2732 }
2733
2734 /* Initially we assign non-packed inloc's for varyings, as we don't really
2735 * know up-front which components will be unused. After all the compilation
2736 * stages we scan the shader to see which components are actually used, and
2737 * re-pack the inlocs to eliminate unneeded varyings.
2738 */
2739 static void
2740 pack_inlocs(struct ir3_context *ctx)
2741 {
2742 struct ir3_shader_variant *so = ctx->so;
2743 uint8_t used_components[so->inputs_count];
2744
2745 memset(used_components, 0, sizeof(used_components));
2746
2747 /*
2748 * First Step: scan shader to find which bary.f/ldlv remain:
2749 */
2750
2751 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) {
2752 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
2753 if (is_input(instr)) {
2754 unsigned inloc = instr->regs[1]->iim_val;
2755 unsigned i = inloc / 4;
2756 unsigned j = inloc % 4;
2757
2758 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
2759 compile_assert(ctx, i < so->inputs_count);
2760
2761 used_components[i] |= 1 << j;
2762 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
2763 for (int n = 0; n < 2; n++) {
2764 unsigned inloc = instr->prefetch.input_offset + n;
2765 unsigned i = inloc / 4;
2766 unsigned j = inloc % 4;
2767
2768 compile_assert(ctx, i < so->inputs_count);
2769
2770 used_components[i] |= 1 << j;
2771 }
2772 }
2773 }
2774 }
2775
2776 /*
2777 * Second Step: reassign varying inloc/slots:
2778 */
2779
2780 unsigned actual_in = 0;
2781 unsigned inloc = 0;
2782
2783 for (unsigned i = 0; i < so->inputs_count; i++) {
2784 unsigned compmask = 0, maxcomp = 0;
2785
2786 so->inputs[i].inloc = inloc;
2787 so->inputs[i].bary = false;
2788
2789 for (unsigned j = 0; j < 4; j++) {
2790 if (!(used_components[i] & (1 << j)))
2791 continue;
2792
2793 compmask |= (1 << j);
2794 actual_in++;
2795 maxcomp = j + 1;
2796
2797 /* at this point, since used_components[i] mask is only
2798 * considering varyings (ie. not sysvals) we know this
2799 * is a varying:
2800 */
2801 so->inputs[i].bary = true;
2802 }
2803
2804 if (so->inputs[i].bary) {
2805 so->varying_in++;
2806 so->inputs[i].compmask = (1 << maxcomp) - 1;
2807 inloc += maxcomp;
2808 }
2809 }
2810
2811 /*
2812 * Third Step: reassign packed inloc's:
2813 */
2814
2815 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) {
2816 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
2817 if (is_input(instr)) {
2818 unsigned inloc = instr->regs[1]->iim_val;
2819 unsigned i = inloc / 4;
2820 unsigned j = inloc % 4;
2821
2822 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
2823 }
2824 }
2825 }
2826 }
2827
2828 static void
2829 setup_output(struct ir3_context *ctx, nir_variable *out)
2830 {
2831 struct ir3_shader_variant *so = ctx->so;
2832 unsigned ncomp = glsl_get_components(out->type);
2833 unsigned n = out->data.driver_location;
2834 unsigned frac = out->data.location_frac;
2835 unsigned slot = out->data.location;
2836 unsigned comp = 0;
2837
2838 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2839 switch (slot) {
2840 case FRAG_RESULT_DEPTH:
2841 comp = 2; /* tgsi will write to .z component */
2842 so->writes_pos = true;
2843 break;
2844 case FRAG_RESULT_COLOR:
2845 so->color0_mrt = 1;
2846 break;
2847 case FRAG_RESULT_SAMPLE_MASK:
2848 so->writes_smask = true;
2849 break;
2850 default:
2851 if (slot >= FRAG_RESULT_DATA0)
2852 break;
2853 ir3_context_error(ctx, "unknown FS output name: %s\n",
2854 gl_frag_result_name(slot));
2855 }
2856 } else if (ctx->so->type == MESA_SHADER_VERTEX ||
2857 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2858 ctx->so->type == MESA_SHADER_GEOMETRY) {
2859 switch (slot) {
2860 case VARYING_SLOT_POS:
2861 so->writes_pos = true;
2862 break;
2863 case VARYING_SLOT_PSIZ:
2864 so->writes_psize = true;
2865 break;
2866 case VARYING_SLOT_PRIMITIVE_ID:
2867 case VARYING_SLOT_LAYER:
2868 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
2869 debug_assert(ctx->so->type == MESA_SHADER_GEOMETRY);
2870 /* fall through */
2871 case VARYING_SLOT_COL0:
2872 case VARYING_SLOT_COL1:
2873 case VARYING_SLOT_BFC0:
2874 case VARYING_SLOT_BFC1:
2875 case VARYING_SLOT_FOGC:
2876 case VARYING_SLOT_CLIP_DIST0:
2877 case VARYING_SLOT_CLIP_DIST1:
2878 case VARYING_SLOT_CLIP_VERTEX:
2879 break;
2880 default:
2881 if (slot >= VARYING_SLOT_VAR0)
2882 break;
2883 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
2884 break;
2885 ir3_context_error(ctx, "unknown %s shader output name: %s\n",
2886 _mesa_shader_stage_to_string(ctx->so->type),
2887 gl_varying_slot_name(slot));
2888 }
2889 } else if (ctx->so->type == MESA_SHADER_TESS_CTRL) {
2890 /* output lowered to buffer writes. */
2891 return;
2892 } else {
2893 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2894 }
2895
2896 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
2897
2898 so->outputs[n].slot = slot;
2899 so->outputs[n].regid = regid(n, comp);
2900 so->outputs_count = MAX2(so->outputs_count, n + 1);
2901
2902 for (int i = 0; i < ncomp; i++) {
2903 unsigned idx = (n * 4) + i + frac;
2904 compile_assert(ctx, idx < ctx->noutputs);
2905 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
2906 }
2907
2908 /* if varying packing doesn't happen, we could end up in a situation
2909 * with "holes" in the output, and since the per-generation code that
2910 * sets up varying linkage registers doesn't expect to have more than
2911 * one varying per vec4 slot, pad the holes.
2912 *
2913 * Note that this should probably generate a performance warning of
2914 * some sort.
2915 */
2916 for (int i = 0; i < frac; i++) {
2917 unsigned idx = (n * 4) + i;
2918 if (!ctx->outputs[idx]) {
2919 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
2920 }
2921 }
2922 }
2923
2924 static int
2925 max_drvloc(struct exec_list *vars)
2926 {
2927 int drvloc = -1;
2928 nir_foreach_variable(var, vars) {
2929 drvloc = MAX2(drvloc, (int)var->data.driver_location);
2930 }
2931 return drvloc;
2932 }
2933
2934 static void
2935 emit_instructions(struct ir3_context *ctx)
2936 {
2937 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
2938
2939 ctx->ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4;
2940 ctx->noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4;
2941
2942 ctx->inputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->ninputs);
2943 ctx->outputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->noutputs);
2944
2945 ctx->ir = ir3_create(ctx->compiler, ctx->so->type);
2946
2947 /* Create inputs in first block: */
2948 ctx->block = get_block(ctx, nir_start_block(fxn));
2949 ctx->in_block = ctx->block;
2950 list_addtail(&ctx->block->node, &ctx->ir->block_list);
2951
2952 /* for fragment shader, the vcoord input register is used as the
2953 * base for bary.f varying fetch instrs:
2954 *
2955 * TODO defer creating ctx->ij_pixel and corresponding sysvals
2956 * until emit_intrinsic when we know they are actually needed.
2957 * For now, we defer creating ctx->ij_centroid, etc, since we
2958 * only need ij_pixel for "old style" varying inputs (ie.
2959 * tgsi_to_nir)
2960 */
2961 struct ir3_instruction *vcoord = NULL;
2962 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2963 struct ir3_instruction *xy[2];
2964
2965 vcoord = create_input(ctx, 0x3);
2966 ir3_split_dest(ctx->block, xy, vcoord, 0, 2);
2967
2968 ctx->ij_pixel = ir3_create_collect(ctx, xy, 2);
2969 }
2970
2971 /* Setup inputs: */
2972 nir_foreach_variable(var, &ctx->s->inputs) {
2973 setup_input(ctx, var);
2974 }
2975
2976 /* Defer add_sysval_input() stuff until after setup_inputs(),
2977 * because sysvals need to be appended after varyings:
2978 */
2979 if (vcoord) {
2980 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PIXEL,
2981 0x3, vcoord);
2982 }
2983
2984
2985 /* Tesselation shaders always need primitive ID for indexing the
2986 * BO. Geometry shaders don't always need it but when they do it has be
2987 * delivered and unclobbered in the VS. To make things easy, we always
2988 * make room for it in VS/DS.
2989 */
2990 bool has_tess = ctx->so->key.tessellation != IR3_TESS_NONE;
2991 bool has_gs = ctx->so->key.has_gs;
2992 switch (ctx->so->type) {
2993 case MESA_SHADER_VERTEX:
2994 if (has_tess) {
2995 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
2996 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
2997 } else if (has_gs) {
2998 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
2999 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3000 }
3001 break;
3002 case MESA_SHADER_TESS_CTRL:
3003 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3004 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3005 break;
3006 case MESA_SHADER_TESS_EVAL:
3007 if (has_gs)
3008 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3009 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3010 break;
3011 case MESA_SHADER_GEOMETRY:
3012 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3013 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3014 break;
3015 default:
3016 break;
3017 }
3018
3019 /* Setup outputs: */
3020 nir_foreach_variable(var, &ctx->s->outputs) {
3021 setup_output(ctx, var);
3022 }
3023
3024 /* Find # of samplers: */
3025 nir_foreach_variable(var, &ctx->s->uniforms) {
3026 ctx->so->num_samp += glsl_type_get_sampler_count(var->type);
3027 /* just assume that we'll be reading from images.. if it
3028 * is write-only we don't have to count it, but not sure
3029 * if there is a good way to know?
3030 */
3031 ctx->so->num_samp += glsl_type_get_image_count(var->type);
3032 }
3033
3034 /* NOTE: need to do something more clever when we support >1 fxn */
3035 nir_foreach_register(reg, &fxn->registers) {
3036 ir3_declare_array(ctx, reg);
3037 }
3038 /* And emit the body: */
3039 ctx->impl = fxn;
3040 emit_function(ctx, fxn);
3041 }
3042
3043 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3044 * need to assign the tex state indexes for these after we know the
3045 * max tex index.
3046 */
3047 static void
3048 fixup_astc_srgb(struct ir3_context *ctx)
3049 {
3050 struct ir3_shader_variant *so = ctx->so;
3051 /* indexed by original tex idx, value is newly assigned alpha sampler
3052 * state tex idx. Zero is invalid since there is at least one sampler
3053 * if we get here.
3054 */
3055 unsigned alt_tex_state[16] = {0};
3056 unsigned tex_idx = ctx->max_texture_index + 1;
3057 unsigned idx = 0;
3058
3059 so->astc_srgb.base = tex_idx;
3060
3061 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
3062 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
3063
3064 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
3065
3066 if (alt_tex_state[sam->cat5.tex] == 0) {
3067 /* assign new alternate/alpha tex state slot: */
3068 alt_tex_state[sam->cat5.tex] = tex_idx++;
3069 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
3070 so->astc_srgb.count++;
3071 }
3072
3073 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
3074 }
3075 }
3076
3077 static void
3078 fixup_binning_pass(struct ir3_context *ctx)
3079 {
3080 struct ir3_shader_variant *so = ctx->so;
3081 struct ir3 *ir = ctx->ir;
3082 unsigned i, j;
3083
3084 /* first pass, remove unused outputs from the IR level outputs: */
3085 for (i = 0, j = 0; i < ir->outputs_count; i++) {
3086 struct ir3_instruction *out = ir->outputs[i];
3087 assert(out->opc == OPC_META_COLLECT);
3088 unsigned outidx = out->collect.outidx;
3089 unsigned slot = so->outputs[outidx].slot;
3090
3091 /* throw away everything but first position/psize */
3092 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3093 ir->outputs[j] = ir->outputs[i];
3094 j++;
3095 }
3096 }
3097 ir->outputs_count = j;
3098
3099 /* second pass, cleanup the unused slots in ir3_shader_variant::outputs
3100 * table:
3101 */
3102 for (i = 0, j = 0; i < so->outputs_count; i++) {
3103 unsigned slot = so->outputs[i].slot;
3104
3105 /* throw away everything but first position/psize */
3106 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3107 so->outputs[j] = so->outputs[i];
3108
3109 /* fixup outidx to point to new output table entry: */
3110 struct ir3_instruction *out;
3111 foreach_output(out, ir) {
3112 if (out->collect.outidx == i) {
3113 out->collect.outidx = j;
3114 break;
3115 }
3116 }
3117
3118 j++;
3119 }
3120 }
3121 so->outputs_count = j;
3122 }
3123
3124 static void
3125 collect_tex_prefetches(struct ir3_context *ctx, struct ir3 *ir)
3126 {
3127 unsigned idx = 0;
3128
3129 /* Collect sampling instructions eligible for pre-dispatch. */
3130 list_for_each_entry(struct ir3_block, block, &ir->block_list, node) {
3131 list_for_each_entry_safe(struct ir3_instruction, instr,
3132 &block->instr_list, node) {
3133 if (instr->opc == OPC_META_TEX_PREFETCH) {
3134 assert(idx < ARRAY_SIZE(ctx->so->sampler_prefetch));
3135 struct ir3_sampler_prefetch *fetch =
3136 &ctx->so->sampler_prefetch[idx];
3137 idx++;
3138
3139 fetch->cmd = IR3_SAMPLER_PREFETCH_CMD;
3140 fetch->wrmask = instr->regs[0]->wrmask;
3141 fetch->tex_id = instr->prefetch.tex;
3142 fetch->samp_id = instr->prefetch.samp;
3143 fetch->dst = instr->regs[0]->num;
3144 fetch->src = instr->prefetch.input_offset;
3145
3146 ctx->so->total_in =
3147 MAX2(ctx->so->total_in, instr->prefetch.input_offset + 2);
3148
3149 /* Disable half precision until supported. */
3150 fetch->half_precision = 0x0;
3151
3152 /* Remove the prefetch placeholder instruction: */
3153 list_delinit(&instr->node);
3154 }
3155 }
3156 }
3157 }
3158
3159 int
3160 ir3_compile_shader_nir(struct ir3_compiler *compiler,
3161 struct ir3_shader_variant *so)
3162 {
3163 struct ir3_context *ctx;
3164 struct ir3 *ir;
3165 int ret = 0, max_bary;
3166
3167 assert(!so->ir);
3168
3169 ctx = ir3_context_init(compiler, so);
3170 if (!ctx) {
3171 DBG("INIT failed!");
3172 ret = -1;
3173 goto out;
3174 }
3175
3176 emit_instructions(ctx);
3177
3178 if (ctx->error) {
3179 DBG("EMIT failed!");
3180 ret = -1;
3181 goto out;
3182 }
3183
3184 ir = so->ir = ctx->ir;
3185
3186 assert((ctx->noutputs % 4) == 0);
3187
3188 /* Setup IR level outputs, which are "collects" that gather
3189 * the scalar components of outputs.
3190 */
3191 for (unsigned i = 0; i < ctx->noutputs; i += 4) {
3192 unsigned ncomp = 0;
3193 /* figure out the # of components written:
3194 *
3195 * TODO do we need to handle holes, ie. if .x and .z
3196 * components written, but .y component not written?
3197 */
3198 for (unsigned j = 0; j < 4; j++) {
3199 if (!ctx->outputs[i + j])
3200 break;
3201 ncomp++;
3202 }
3203
3204 /* Note that in some stages, like TCS, store_output is
3205 * lowered to memory writes, so no components of the
3206 * are "written" from the PoV of traditional store-
3207 * output instructions:
3208 */
3209 if (!ncomp)
3210 continue;
3211
3212 struct ir3_instruction *out =
3213 ir3_create_collect(ctx, &ctx->outputs[i], ncomp);
3214
3215 int outidx = i / 4;
3216 assert(outidx < so->outputs_count);
3217
3218 /* stash index into so->outputs[] so we can map the
3219 * output back to slot/etc later:
3220 */
3221 out->collect.outidx = outidx;
3222
3223 array_insert(ir, ir->outputs, out);
3224 }
3225
3226 /* Set up the gs header as an output for the vertex shader so it won't
3227 * clobber it for the tess ctrl shader.
3228 *
3229 * TODO this could probably be done more cleanly in a nir pass.
3230 */
3231 if (ctx->so->type == MESA_SHADER_VERTEX ||
3232 (ctx->so->key.has_gs && ctx->so->type == MESA_SHADER_TESS_EVAL)) {
3233 if (ctx->primitive_id) {
3234 unsigned n = so->outputs_count++;
3235 so->outputs[n].slot = VARYING_SLOT_PRIMITIVE_ID;
3236
3237 struct ir3_instruction *out =
3238 ir3_create_collect(ctx, &ctx->primitive_id, 1);
3239 out->collect.outidx = n;
3240 array_insert(ir, ir->outputs, out);
3241 }
3242
3243 if (ctx->gs_header) {
3244 unsigned n = so->outputs_count++;
3245 so->outputs[n].slot = VARYING_SLOT_GS_HEADER_IR3;
3246 struct ir3_instruction *out =
3247 ir3_create_collect(ctx, &ctx->gs_header, 1);
3248 out->collect.outidx = n;
3249 array_insert(ir, ir->outputs, out);
3250 }
3251
3252 if (ctx->tcs_header) {
3253 unsigned n = so->outputs_count++;
3254 so->outputs[n].slot = VARYING_SLOT_TCS_HEADER_IR3;
3255 struct ir3_instruction *out =
3256 ir3_create_collect(ctx, &ctx->tcs_header, 1);
3257 out->collect.outidx = n;
3258 array_insert(ir, ir->outputs, out);
3259 }
3260 }
3261
3262 /* at this point, for binning pass, throw away unneeded outputs: */
3263 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
3264 fixup_binning_pass(ctx);
3265
3266 ir3_debug_print(ir, "BEFORE CP");
3267
3268 ir3_cp(ir, so);
3269
3270 /* at this point, for binning pass, throw away unneeded outputs:
3271 * Note that for a6xx and later, we do this after ir3_cp to ensure
3272 * that the uniform/constant layout for BS and VS matches, so that
3273 * we can re-use same VS_CONST state group.
3274 */
3275 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
3276 fixup_binning_pass(ctx);
3277
3278 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3279 * need to make sure not to remove any inputs that are used by
3280 * the nonbinning VS.
3281 */
3282 if (ctx->compiler->gpu_id >= 600 && so->binning_pass &&
3283 so->type == MESA_SHADER_VERTEX) {
3284 for (int i = 0; i < ctx->ninputs; i++) {
3285 struct ir3_instruction *in = ctx->inputs[i];
3286
3287 if (!in)
3288 continue;
3289
3290 unsigned n = i / 4;
3291 unsigned c = i % 4;
3292
3293 debug_assert(n < so->nonbinning->inputs_count);
3294
3295 if (so->nonbinning->inputs[n].sysval)
3296 continue;
3297
3298 /* be sure to keep inputs, even if only used in VS */
3299 if (so->nonbinning->inputs[n].compmask & (1 << c))
3300 array_insert(in->block, in->block->keeps, in);
3301 }
3302 }
3303
3304 ir3_debug_print(ir, "BEFORE GROUPING");
3305
3306 ir3_sched_add_deps(ir);
3307
3308 /* Group left/right neighbors, inserting mov's where needed to
3309 * solve conflicts:
3310 */
3311 ir3_group(ir);
3312
3313 ir3_debug_print(ir, "AFTER GROUPING");
3314
3315 ir3_depth(ir, so);
3316
3317 ir3_debug_print(ir, "AFTER DEPTH");
3318
3319 /* do Sethi–Ullman numbering before scheduling: */
3320 ir3_sun(ir);
3321
3322 ret = ir3_sched(ir);
3323 if (ret) {
3324 DBG("SCHED failed!");
3325 goto out;
3326 }
3327
3328 if (compiler->gpu_id >= 600) {
3329 ir3_a6xx_fixup_atomic_dests(ir, so);
3330 }
3331
3332 ir3_debug_print(ir, "AFTER SCHED");
3333
3334 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3335 * with draw pass VS, so binning and draw pass can both use the
3336 * same VBO state.
3337 *
3338 * Note that VS inputs are expected to be full precision.
3339 */
3340 bool pre_assign_inputs = (ir->compiler->gpu_id >= 600) &&
3341 (ir->type == MESA_SHADER_VERTEX) &&
3342 so->binning_pass;
3343
3344 if (pre_assign_inputs) {
3345 for (unsigned i = 0; i < ctx->ninputs; i++) {
3346 struct ir3_instruction *instr = ctx->inputs[i];
3347
3348 if (!instr)
3349 continue;
3350
3351 unsigned n = i / 4;
3352 unsigned c = i % 4;
3353 unsigned regid = so->nonbinning->inputs[n].regid + c;
3354
3355 instr->regs[0]->num = regid;
3356 }
3357
3358 ret = ir3_ra(so, ctx->inputs, ctx->ninputs);
3359 } else if (ctx->tcs_header) {
3360 /* We need to have these values in the same registers between VS and TCS
3361 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3362 */
3363
3364 ctx->tcs_header->regs[0]->num = regid(0, 0);
3365 ctx->primitive_id->regs[0]->num = regid(0, 1);
3366 struct ir3_instruction *precolor[] = { ctx->tcs_header, ctx->primitive_id };
3367 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3368 } else if (ctx->gs_header) {
3369 /* We need to have these values in the same registers between producer
3370 * (VS or DS) and GS since the producer chains to GS and doesn't get
3371 * the sysvals redelivered.
3372 */
3373
3374 ctx->gs_header->regs[0]->num = regid(0, 0);
3375 ctx->primitive_id->regs[0]->num = regid(0, 1);
3376 struct ir3_instruction *precolor[] = { ctx->gs_header, ctx->primitive_id };
3377 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3378 } else if (so->num_sampler_prefetch) {
3379 assert(so->type == MESA_SHADER_FRAGMENT);
3380 struct ir3_instruction *instr, *precolor[2];
3381 int idx = 0;
3382
3383 foreach_input(instr, ir) {
3384 if (instr->input.sysval != SYSTEM_VALUE_BARYCENTRIC_PIXEL)
3385 continue;
3386
3387 assert(idx < ARRAY_SIZE(precolor));
3388
3389 precolor[idx] = instr;
3390 instr->regs[0]->num = idx;
3391
3392 idx++;
3393 }
3394 ret = ir3_ra(so, precolor, idx);
3395 } else {
3396 ret = ir3_ra(so, NULL, 0);
3397 }
3398
3399 if (ret) {
3400 DBG("RA failed!");
3401 goto out;
3402 }
3403
3404 ir3_debug_print(ir, "AFTER RA");
3405
3406 if (so->type == MESA_SHADER_FRAGMENT)
3407 pack_inlocs(ctx);
3408
3409 /*
3410 * Fixup inputs/outputs to point to the actual registers assigned:
3411 *
3412 * 1) initialize to r63.x (invalid/unused)
3413 * 2) iterate IR level inputs/outputs and update the variants
3414 * inputs/outputs table based on the assigned registers for
3415 * the remaining inputs/outputs.
3416 */
3417
3418 for (unsigned i = 0; i < so->inputs_count; i++)
3419 so->inputs[i].regid = regid(63, 0);
3420 for (unsigned i = 0; i < so->outputs_count; i++)
3421 so->outputs[i].regid = regid(63, 0);
3422
3423 struct ir3_instruction *out;
3424 foreach_output(out, ir) {
3425 assert(out->opc == OPC_META_COLLECT);
3426 unsigned outidx = out->collect.outidx;
3427
3428 so->outputs[outidx].regid = out->regs[0]->num;
3429 so->outputs[outidx].half = !!(out->regs[0]->flags & IR3_REG_HALF);
3430 }
3431
3432 struct ir3_instruction *in;
3433 foreach_input(in, ir) {
3434 assert(in->opc == OPC_META_INPUT);
3435 unsigned inidx = in->input.inidx;
3436
3437 so->inputs[inidx].regid = in->regs[0]->num;
3438 so->inputs[inidx].half = !!(in->regs[0]->flags & IR3_REG_HALF);
3439 }
3440
3441 if (ctx->astc_srgb)
3442 fixup_astc_srgb(ctx);
3443
3444 /* We need to do legalize after (for frag shader's) the "bary.f"
3445 * offsets (inloc) have been assigned.
3446 */
3447 ir3_legalize(ir, &so->has_ssbo, &so->need_pixlod, &max_bary);
3448
3449 ir3_debug_print(ir, "AFTER LEGALIZE");
3450
3451 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3452 * know what we might have to wait on when coming in from VS chsh.
3453 */
3454 if (so->type == MESA_SHADER_TESS_CTRL ||
3455 so->type == MESA_SHADER_GEOMETRY ) {
3456 list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
3457 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
3458 instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
3459 break;
3460 }
3461 }
3462 }
3463
3464 so->branchstack = ctx->max_stack;
3465
3466 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3467 if (so->type == MESA_SHADER_FRAGMENT)
3468 so->total_in = max_bary + 1;
3469
3470 so->max_sun = ir->max_sun;
3471
3472 /* Collect sampling instructions eligible for pre-dispatch. */
3473 collect_tex_prefetches(ctx, ir);
3474
3475 out:
3476 if (ret) {
3477 if (so->ir)
3478 ir3_destroy(so->ir);
3479 so->ir = NULL;
3480 }
3481 ir3_context_free(ctx);
3482
3483 return ret;
3484 }