2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
38 #include "instr-a3xx.h"
40 #include "ir3_context.h"
43 ir3_handle_bindless_cat6(struct ir3_instruction
*instr
, nir_src rsrc
)
45 nir_intrinsic_instr
*intrin
= ir3_bindless_resource(rsrc
);
49 instr
->flags
|= IR3_INSTR_B
;
50 instr
->cat6
.base
= nir_intrinsic_desc_set(intrin
);
53 static struct ir3_instruction
*
54 create_indirect_load(struct ir3_context
*ctx
, unsigned arrsz
, int n
,
55 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
57 struct ir3_block
*block
= ctx
->block
;
58 struct ir3_instruction
*mov
;
59 struct ir3_register
*src
;
61 mov
= ir3_instr_create(block
, OPC_MOV
);
62 mov
->cat1
.src_type
= TYPE_U32
;
63 mov
->cat1
.dst_type
= TYPE_U32
;
65 src
= __ssa_src(mov
, collect
, IR3_REG_RELATIV
);
67 src
->array
.offset
= n
;
69 ir3_instr_set_address(mov
, address
);
74 static struct ir3_instruction
*
75 create_input(struct ir3_context
*ctx
, unsigned compmask
)
77 struct ir3_instruction
*in
;
79 in
= ir3_instr_create(ctx
->in_block
, OPC_META_INPUT
);
80 in
->input
.sysval
= ~0;
81 __ssa_dst(in
)->wrmask
= compmask
;
83 array_insert(ctx
->ir
, ctx
->ir
->inputs
, in
);
88 static struct ir3_instruction
*
89 create_frag_input(struct ir3_context
*ctx
, bool use_ldlv
, unsigned n
)
91 struct ir3_block
*block
= ctx
->block
;
92 struct ir3_instruction
*instr
;
93 /* packed inloc is fixed up later: */
94 struct ir3_instruction
*inloc
= create_immed(block
, n
);
97 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
98 instr
->cat6
.type
= TYPE_U32
;
99 instr
->cat6
.iim_val
= 1;
101 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->ij_pixel
, 0);
102 instr
->regs
[2]->wrmask
= 0x3;
108 static struct ir3_instruction
*
109 create_driver_param(struct ir3_context
*ctx
, enum ir3_driver_param dp
)
111 /* first four vec4 sysval's reserved for UBOs: */
112 /* NOTE: dp is in scalar, but there can be >4 dp components: */
113 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
114 unsigned n
= const_state
->offsets
.driver_param
;
115 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
116 return create_uniform(ctx
->block
, r
);
120 * Adreno's comparisons produce a 1 for true and 0 for false, in either 16 or
121 * 32-bit registers. We use NIR's 1-bit integers to represent bools, and
122 * trust that we will only see and/or/xor on those 1-bit values, so we can
123 * safely store NIR i1s in a 32-bit reg while always containing either a 1 or
128 * alu/sfu instructions:
131 static struct ir3_instruction
*
132 create_cov(struct ir3_context
*ctx
, struct ir3_instruction
*src
,
133 unsigned src_bitsize
, nir_op op
)
135 type_t src_type
, dst_type
;
139 case nir_op_f2f16_rtne
:
140 case nir_op_f2f16_rtz
:
148 switch (src_bitsize
) {
156 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
165 switch (src_bitsize
) {
176 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
185 switch (src_bitsize
) {
196 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
209 ir3_context_error(ctx
, "invalid conversion op: %u", op
);
220 case nir_op_f2f16_rtne
:
221 case nir_op_f2f16_rtz
:
263 ir3_context_error(ctx
, "invalid conversion op: %u", op
);
266 if (src_type
== dst_type
)
269 struct ir3_instruction
*cov
=
270 ir3_COV(ctx
->block
, src
, src_type
, dst_type
);
272 if (op
== nir_op_f2f16_rtne
)
273 cov
->regs
[0]->flags
|= IR3_REG_EVEN
;
279 emit_alu(struct ir3_context
*ctx
, nir_alu_instr
*alu
)
281 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
282 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
283 unsigned bs
[info
->num_inputs
]; /* bit size */
284 struct ir3_block
*b
= ctx
->block
;
285 unsigned dst_sz
, wrmask
;
286 type_t dst_type
= nir_dest_bit_size(alu
->dest
.dest
) == 16 ?
289 if (alu
->dest
.dest
.is_ssa
) {
290 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
291 wrmask
= (1 << dst_sz
) - 1;
293 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
294 wrmask
= alu
->dest
.write_mask
;
297 dst
= ir3_get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
299 /* Vectors are special in that they have non-scalarized writemasks,
300 * and just take the first swizzle channel for each argument in
301 * order into each writemask channel.
303 if ((alu
->op
== nir_op_vec2
) ||
304 (alu
->op
== nir_op_vec3
) ||
305 (alu
->op
== nir_op_vec4
)) {
307 for (int i
= 0; i
< info
->num_inputs
; i
++) {
308 nir_alu_src
*asrc
= &alu
->src
[i
];
310 compile_assert(ctx
, !asrc
->abs
);
311 compile_assert(ctx
, !asrc
->negate
);
313 src
[i
] = ir3_get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
315 src
[i
] = create_immed_typed(ctx
->block
, 0, dst_type
);
316 dst
[i
] = ir3_MOV(b
, src
[i
], dst_type
);
319 ir3_put_dst(ctx
, &alu
->dest
.dest
);
323 /* We also get mov's with more than one component for mov's so
324 * handle those specially:
326 if (alu
->op
== nir_op_mov
) {
327 nir_alu_src
*asrc
= &alu
->src
[0];
328 struct ir3_instruction
*const *src0
= ir3_get_src(ctx
, &asrc
->src
);
330 for (unsigned i
= 0; i
< dst_sz
; i
++) {
331 if (wrmask
& (1 << i
)) {
332 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], dst_type
);
338 ir3_put_dst(ctx
, &alu
->dest
.dest
);
342 /* General case: We can just grab the one used channel per src. */
343 for (int i
= 0; i
< info
->num_inputs
; i
++) {
344 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
345 nir_alu_src
*asrc
= &alu
->src
[i
];
347 compile_assert(ctx
, !asrc
->abs
);
348 compile_assert(ctx
, !asrc
->negate
);
350 src
[i
] = ir3_get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
351 bs
[i
] = nir_src_bit_size(asrc
->src
);
353 compile_assert(ctx
, src
[i
]);
358 case nir_op_f2f16_rtne
:
359 case nir_op_f2f16_rtz
:
382 dst
[0] = create_cov(ctx
, src
[0], bs
[0], alu
->op
);
385 case nir_op_fquantize2f16
:
386 dst
[0] = create_cov(ctx
,
387 create_cov(ctx
, src
[0], 32, nir_op_f2f16
),
391 dst
[0] = ir3_CMPS_F(b
,
393 create_immed_typed(b
, 0, bs
[0] == 16 ? TYPE_F16
: TYPE_F32
), 0);
394 dst
[0]->cat2
.condition
= IR3_COND_NE
;
398 /* i2b1 will appear when translating from nir_load_ubo or
399 * nir_intrinsic_load_ssbo, where any non-zero value is true.
401 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
402 dst
[0]->cat2
.condition
= IR3_COND_NE
;
406 /* b2b1 will appear when translating from
408 * - nir_intrinsic_load_shared of a 32-bit 0/~0 value.
409 * - nir_intrinsic_load_constant of a 32-bit 0/~0 value
411 * A negate can turn those into a 1 or 0 for us.
413 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
417 /* b2b32 will appear when converting our 1-bit bools to a store_shared
420 * A negate can turn those into a ~0 for us.
422 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
426 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
429 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
432 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
435 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
438 /* if there is just a single use of the src, and it supports
439 * (sat) bit, we can just fold the (sat) flag back to the
440 * src instruction and create a mov. This is easier for cp
443 * NOTE: a3xx definitely seen not working with flat bary.f. Same test
444 * uses ldlv on a4xx+, so not definitive. Seems rare enough to apply
447 * TODO probably opc_cat==4 is ok too
449 if (alu
->src
[0].src
.is_ssa
&&
450 src
[0]->opc
!= OPC_BARY_F
&&
451 (list_length(&alu
->src
[0].src
.ssa
->uses
) == 1) &&
452 ((opc_cat(src
[0]->opc
) == 2) || (opc_cat(src
[0]->opc
) == 3))) {
453 src
[0]->flags
|= IR3_INSTR_SAT
;
454 dst
[0] = ir3_MOV(b
, src
[0], dst_type
);
456 /* otherwise generate a max.f that saturates.. blob does
457 * similar (generating a cat2 mov using max.f)
459 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[0], 0);
460 dst
[0]->flags
|= IR3_INSTR_SAT
;
464 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
467 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
470 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
473 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
476 case nir_op_fddx_coarse
:
477 dst
[0] = ir3_DSX(b
, src
[0], 0);
478 dst
[0]->cat5
.type
= TYPE_F32
;
480 case nir_op_fddx_fine
:
481 dst
[0] = ir3_DSXPP_1(b
, src
[0], 0);
482 dst
[0]->cat5
.type
= TYPE_F32
;
485 case nir_op_fddy_coarse
:
486 dst
[0] = ir3_DSY(b
, src
[0], 0);
487 dst
[0]->cat5
.type
= TYPE_F32
;
490 case nir_op_fddy_fine
:
491 dst
[0] = ir3_DSYPP_1(b
, src
[0], 0);
492 dst
[0]->cat5
.type
= TYPE_F32
;
495 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
496 dst
[0]->cat2
.condition
= IR3_COND_LT
;
499 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
500 dst
[0]->cat2
.condition
= IR3_COND_GE
;
503 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
504 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
507 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
508 dst
[0]->cat2
.condition
= IR3_COND_NE
;
511 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
514 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
517 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
519 case nir_op_fround_even
:
520 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
523 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
527 dst
[0] = ir3_SIN(b
, src
[0], 0);
530 dst
[0] = ir3_COS(b
, src
[0], 0);
533 dst
[0] = ir3_RSQ(b
, src
[0], 0);
536 dst
[0] = ir3_RCP(b
, src
[0], 0);
539 dst
[0] = ir3_LOG2(b
, src
[0], 0);
542 dst
[0] = ir3_EXP2(b
, src
[0], 0);
545 dst
[0] = ir3_SQRT(b
, src
[0], 0);
549 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
552 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
555 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
558 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
561 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
564 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
567 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
569 case nir_op_umul_low
:
570 dst
[0] = ir3_MULL_U(b
, src
[0], 0, src
[1], 0);
572 case nir_op_imadsh_mix16
:
573 dst
[0] = ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0, src
[2], 0);
575 case nir_op_imad24_ir3
:
576 dst
[0] = ir3_MAD_S24(b
, src
[0], 0, src
[1], 0, src
[2], 0);
579 dst
[0] = ir3_MUL_S24(b
, src
[0], 0, src
[1], 0);
582 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
586 dst
[0] = ir3_SUB_U(b
, create_immed(ctx
->block
, 1), 0, src
[0], 0);
588 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
592 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
595 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
598 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
601 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
604 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
607 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
610 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
611 dst
[0]->cat2
.condition
= IR3_COND_LT
;
614 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
615 dst
[0]->cat2
.condition
= IR3_COND_GE
;
618 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
619 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
622 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
623 dst
[0]->cat2
.condition
= IR3_COND_NE
;
626 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
627 dst
[0]->cat2
.condition
= IR3_COND_LT
;
630 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
631 dst
[0]->cat2
.condition
= IR3_COND_GE
;
635 struct ir3_instruction
*cond
= src
[0];
637 /* If src[0] is a negation (likely as a result of an ir3_b2n(cond)),
638 * we can ignore that and use original cond, since the nonzero-ness of
639 * cond stays the same.
641 if (cond
->opc
== OPC_ABSNEG_S
&&
643 (cond
->regs
[1]->flags
& (IR3_REG_SNEG
| IR3_REG_SABS
)) == IR3_REG_SNEG
) {
644 cond
= cond
->regs
[1]->instr
;
647 compile_assert(ctx
, bs
[1] == bs
[2]);
648 /* The condition's size has to match the other two arguments' size, so
649 * convert down if necessary.
652 struct hash_entry
*prev_entry
=
653 _mesa_hash_table_search(ctx
->sel_cond_conversions
, src
[0]);
655 cond
= prev_entry
->data
;
657 cond
= ir3_COV(b
, cond
, TYPE_U32
, TYPE_U16
);
658 _mesa_hash_table_insert(ctx
->sel_cond_conversions
, src
[0], cond
);
663 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, cond
, 0, src
[2], 0);
665 dst
[0] = ir3_SEL_B16(b
, src
[1], 0, cond
, 0, src
[2], 0);
668 case nir_op_bit_count
: {
669 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
670 // double check on earlier gen's. Once half-precision support is
671 // in place, this should probably move to a NIR lowering pass:
672 struct ir3_instruction
*hi
, *lo
;
674 hi
= ir3_COV(b
, ir3_SHR_B(b
, src
[0], 0, create_immed(b
, 16), 0),
676 lo
= ir3_COV(b
, src
[0], TYPE_U32
, TYPE_U16
);
678 hi
= ir3_CBITS_B(b
, hi
, 0);
679 lo
= ir3_CBITS_B(b
, lo
, 0);
681 // TODO maybe the builders should default to making dst half-precision
682 // if the src's were half precision, to make this less awkward.. otoh
683 // we should probably just do this lowering in NIR.
684 hi
->regs
[0]->flags
|= IR3_REG_HALF
;
685 lo
->regs
[0]->flags
|= IR3_REG_HALF
;
687 dst
[0] = ir3_ADD_S(b
, hi
, 0, lo
, 0);
688 dst
[0]->regs
[0]->flags
|= IR3_REG_HALF
;
689 dst
[0] = ir3_COV(b
, dst
[0], TYPE_U16
, TYPE_U32
);
692 case nir_op_ifind_msb
: {
693 struct ir3_instruction
*cmp
;
694 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
695 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
696 cmp
->cat2
.condition
= IR3_COND_GE
;
697 dst
[0] = ir3_SEL_B32(b
,
698 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
702 case nir_op_ufind_msb
:
703 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
704 dst
[0] = ir3_SEL_B32(b
,
705 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
706 src
[0], 0, dst
[0], 0);
708 case nir_op_find_lsb
:
709 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
710 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
712 case nir_op_bitfield_reverse
:
713 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
717 ir3_context_error(ctx
, "Unhandled ALU op: %s\n",
718 nir_op_infos
[alu
->op
].name
);
722 if (nir_alu_type_get_base_type(info
->output_type
) == nir_type_bool
) {
723 assert(nir_dest_bit_size(alu
->dest
.dest
) == 1 ||
724 alu
->op
== nir_op_b2b32
);
727 /* 1-bit values stored in 32-bit registers are only valid for certain
738 compile_assert(ctx
, nir_dest_bit_size(alu
->dest
.dest
) != 1);
742 ir3_put_dst(ctx
, &alu
->dest
.dest
);
746 emit_intrinsic_load_ubo_ldc(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
747 struct ir3_instruction
**dst
)
749 struct ir3_block
*b
= ctx
->block
;
751 unsigned ncomp
= intr
->num_components
;
752 struct ir3_instruction
*offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
753 struct ir3_instruction
*idx
= ir3_get_src(ctx
, &intr
->src
[0])[0];
754 struct ir3_instruction
*ldc
= ir3_LDC(b
, idx
, 0, offset
, 0);
755 ldc
->regs
[0]->wrmask
= MASK(ncomp
);
756 ldc
->cat6
.iim_val
= ncomp
;
757 ldc
->cat6
.d
= nir_intrinsic_base(intr
);
758 ldc
->cat6
.type
= TYPE_U32
;
760 ir3_handle_bindless_cat6(ldc
, intr
->src
[0]);
761 if (ldc
->flags
& IR3_INSTR_B
)
762 ctx
->so
->bindless_ubo
= true;
764 ir3_split_dest(b
, dst
, ldc
, 0, ncomp
);
768 /* handles direct/indirect UBO reads: */
770 emit_intrinsic_load_ubo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
771 struct ir3_instruction
**dst
)
773 struct ir3_block
*b
= ctx
->block
;
774 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
775 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
776 unsigned ubo
= regid(const_state
->offsets
.ubo
, 0);
777 const unsigned ptrsz
= ir3_pointer_size(ctx
->compiler
);
781 /* First src is ubo index, which could either be an immed or not: */
782 src0
= ir3_get_src(ctx
, &intr
->src
[0])[0];
783 if (is_same_type_mov(src0
) &&
784 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
785 base_lo
= create_uniform(b
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
786 base_hi
= create_uniform(b
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
788 base_lo
= create_uniform_indirect(b
, ubo
, ir3_get_addr0(ctx
, src0
, ptrsz
));
789 base_hi
= create_uniform_indirect(b
, ubo
+ 1, ir3_get_addr0(ctx
, src0
, ptrsz
));
791 /* NOTE: since relative addressing is used, make sure constlen is
792 * at least big enough to cover all the UBO addresses, since the
793 * assembler won't know what the max address reg is.
795 ctx
->so
->constlen
= MAX2(ctx
->so
->constlen
,
796 const_state
->offsets
.ubo
+ (ctx
->s
->info
.num_ubos
* ptrsz
));
799 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
802 if (nir_src_is_const(intr
->src
[1])) {
803 off
+= nir_src_as_uint(intr
->src
[1]);
805 /* For load_ubo_indirect, second src is indirect offset: */
806 src1
= ir3_get_src(ctx
, &intr
->src
[1])[0];
808 /* and add offset to addr: */
809 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
812 /* if offset is to large to encode in the ldg, split it out: */
813 if ((off
+ (intr
->num_components
* 4)) > 1024) {
814 /* split out the minimal amount to improve the odds that
815 * cp can fit the immediate in the add.s instruction:
817 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
818 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
823 struct ir3_instruction
*carry
;
825 /* handle 32b rollover, ie:
826 * if (addr < base_lo)
829 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
830 carry
->cat2
.condition
= IR3_COND_LT
;
831 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
833 addr
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
836 for (int i
= 0; i
< intr
->num_components
; i
++) {
837 struct ir3_instruction
*load
=
838 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0, /* num components */
839 create_immed(b
, off
+ i
* 4), 0);
840 load
->cat6
.type
= TYPE_U32
;
845 /* src[] = { block_index } */
847 emit_intrinsic_ssbo_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
848 struct ir3_instruction
**dst
)
850 /* SSBO size stored as a const starting at ssbo_sizes: */
851 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
852 unsigned blk_idx
= nir_src_as_uint(intr
->src
[0]);
853 unsigned idx
= regid(const_state
->offsets
.ssbo_sizes
, 0) +
854 const_state
->ssbo_size
.off
[blk_idx
];
856 debug_assert(const_state
->ssbo_size
.mask
& (1 << blk_idx
));
858 dst
[0] = create_uniform(ctx
->block
, idx
);
861 /* src[] = { offset }. const_index[] = { base } */
863 emit_intrinsic_load_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
864 struct ir3_instruction
**dst
)
866 struct ir3_block
*b
= ctx
->block
;
867 struct ir3_instruction
*ldl
, *offset
;
870 offset
= ir3_get_src(ctx
, &intr
->src
[0])[0];
871 base
= nir_intrinsic_base(intr
);
873 ldl
= ir3_LDL(b
, offset
, 0,
874 create_immed(b
, intr
->num_components
), 0,
875 create_immed(b
, base
), 0);
877 ldl
->cat6
.type
= utype_dst(intr
->dest
);
878 ldl
->regs
[0]->wrmask
= MASK(intr
->num_components
);
880 ldl
->barrier_class
= IR3_BARRIER_SHARED_R
;
881 ldl
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
883 ir3_split_dest(b
, dst
, ldl
, 0, intr
->num_components
);
886 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
888 emit_intrinsic_store_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
890 struct ir3_block
*b
= ctx
->block
;
891 struct ir3_instruction
*stl
, *offset
;
892 struct ir3_instruction
* const *value
;
893 unsigned base
, wrmask
, ncomp
;
895 value
= ir3_get_src(ctx
, &intr
->src
[0]);
896 offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
898 base
= nir_intrinsic_base(intr
);
899 wrmask
= nir_intrinsic_write_mask(intr
);
900 ncomp
= ffs(~wrmask
) - 1;
902 assert(wrmask
== BITFIELD_MASK(intr
->num_components
));
904 stl
= ir3_STL(b
, offset
, 0,
905 ir3_create_collect(ctx
, value
, ncomp
), 0,
906 create_immed(b
, ncomp
), 0);
907 stl
->cat6
.dst_offset
= base
;
908 stl
->cat6
.type
= utype_src(intr
->src
[0]);
909 stl
->barrier_class
= IR3_BARRIER_SHARED_W
;
910 stl
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
912 array_insert(b
, b
->keeps
, stl
);
915 /* src[] = { offset }. const_index[] = { base } */
917 emit_intrinsic_load_shared_ir3(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
918 struct ir3_instruction
**dst
)
920 struct ir3_block
*b
= ctx
->block
;
921 struct ir3_instruction
*load
, *offset
;
924 offset
= ir3_get_src(ctx
, &intr
->src
[0])[0];
925 base
= nir_intrinsic_base(intr
);
927 load
= ir3_LDLW(b
, offset
, 0,
928 create_immed(b
, intr
->num_components
), 0,
929 create_immed(b
, base
), 0);
931 load
->cat6
.type
= utype_dst(intr
->dest
);
932 load
->regs
[0]->wrmask
= MASK(intr
->num_components
);
934 load
->barrier_class
= IR3_BARRIER_SHARED_R
;
935 load
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
937 ir3_split_dest(b
, dst
, load
, 0, intr
->num_components
);
940 /* src[] = { value, offset }. const_index[] = { base } */
942 emit_intrinsic_store_shared_ir3(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
944 struct ir3_block
*b
= ctx
->block
;
945 struct ir3_instruction
*store
, *offset
;
946 struct ir3_instruction
* const *value
;
948 value
= ir3_get_src(ctx
, &intr
->src
[0]);
949 offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
951 store
= ir3_STLW(b
, offset
, 0,
952 ir3_create_collect(ctx
, value
, intr
->num_components
), 0,
953 create_immed(b
, intr
->num_components
), 0);
955 store
->cat6
.dst_offset
= nir_intrinsic_base(intr
);
956 store
->cat6
.type
= utype_src(intr
->src
[0]);
957 store
->barrier_class
= IR3_BARRIER_SHARED_W
;
958 store
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
960 array_insert(b
, b
->keeps
, store
);
964 * CS shared variable atomic intrinsics
966 * All of the shared variable atomic memory operations read a value from
967 * memory, compute a new value using one of the operations below, write the
968 * new value to memory, and return the original value read.
970 * All operations take 2 sources except CompSwap that takes 3. These
973 * 0: The offset into the shared variable storage region that the atomic
974 * operation will operate on.
975 * 1: The data parameter to the atomic function (i.e. the value to add
976 * in shared_atomic_add, etc).
977 * 2: For CompSwap only: the second data parameter.
979 static struct ir3_instruction
*
980 emit_intrinsic_atomic_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
982 struct ir3_block
*b
= ctx
->block
;
983 struct ir3_instruction
*atomic
, *src0
, *src1
;
984 type_t type
= TYPE_U32
;
986 src0
= ir3_get_src(ctx
, &intr
->src
[0])[0]; /* offset */
987 src1
= ir3_get_src(ctx
, &intr
->src
[1])[0]; /* value */
989 switch (intr
->intrinsic
) {
990 case nir_intrinsic_shared_atomic_add
:
991 atomic
= ir3_ATOMIC_ADD(b
, src0
, 0, src1
, 0);
993 case nir_intrinsic_shared_atomic_imin
:
994 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
997 case nir_intrinsic_shared_atomic_umin
:
998 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1000 case nir_intrinsic_shared_atomic_imax
:
1001 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1004 case nir_intrinsic_shared_atomic_umax
:
1005 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1007 case nir_intrinsic_shared_atomic_and
:
1008 atomic
= ir3_ATOMIC_AND(b
, src0
, 0, src1
, 0);
1010 case nir_intrinsic_shared_atomic_or
:
1011 atomic
= ir3_ATOMIC_OR(b
, src0
, 0, src1
, 0);
1013 case nir_intrinsic_shared_atomic_xor
:
1014 atomic
= ir3_ATOMIC_XOR(b
, src0
, 0, src1
, 0);
1016 case nir_intrinsic_shared_atomic_exchange
:
1017 atomic
= ir3_ATOMIC_XCHG(b
, src0
, 0, src1
, 0);
1019 case nir_intrinsic_shared_atomic_comp_swap
:
1020 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1021 src1
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1022 ir3_get_src(ctx
, &intr
->src
[2])[0],
1025 atomic
= ir3_ATOMIC_CMPXCHG(b
, src0
, 0, src1
, 0);
1031 atomic
->cat6
.iim_val
= 1;
1033 atomic
->cat6
.type
= type
;
1034 atomic
->barrier_class
= IR3_BARRIER_SHARED_W
;
1035 atomic
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1037 /* even if nothing consume the result, we can't DCE the instruction: */
1038 array_insert(b
, b
->keeps
, atomic
);
1043 struct tex_src_info
{
1045 unsigned tex_base
, samp_base
, tex_idx
, samp_idx
;
1046 /* For normal tex instructions */
1047 unsigned base
, combined_idx
, a1_val
, flags
;
1048 struct ir3_instruction
*samp_tex
;
1051 /* TODO handle actual indirect/dynamic case.. which is going to be weird
1052 * to handle with the image_mapping table..
1054 static struct tex_src_info
1055 get_image_samp_tex_src(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1057 struct ir3_block
*b
= ctx
->block
;
1058 struct tex_src_info info
= { 0 };
1059 nir_intrinsic_instr
*bindless_tex
= ir3_bindless_resource(intr
->src
[0]);
1060 ctx
->so
->bindless_tex
= true;
1064 info
.flags
|= IR3_INSTR_B
;
1066 /* Gather information required to determine which encoding to
1067 * choose as well as for prefetch.
1069 info
.tex_base
= nir_intrinsic_desc_set(bindless_tex
);
1070 bool tex_const
= nir_src_is_const(bindless_tex
->src
[0]);
1072 info
.tex_idx
= nir_src_as_uint(bindless_tex
->src
[0]);
1075 /* Choose encoding. */
1076 if (tex_const
&& info
.tex_idx
< 256) {
1077 if (info
.tex_idx
< 16) {
1078 /* Everything fits within the instruction */
1079 info
.base
= info
.tex_base
;
1080 info
.combined_idx
= info
.samp_idx
| (info
.tex_idx
<< 4);
1082 info
.base
= info
.tex_base
;
1083 info
.a1_val
= info
.tex_idx
<< 3;
1084 info
.combined_idx
= 0;
1085 info
.flags
|= IR3_INSTR_A1EN
;
1087 info
.samp_tex
= NULL
;
1089 info
.flags
|= IR3_INSTR_S2EN
;
1090 info
.base
= info
.tex_base
;
1092 /* Note: the indirect source is now a vec2 instead of hvec2 */
1093 struct ir3_instruction
*texture
, *sampler
;
1095 texture
= ir3_get_src(ctx
, &intr
->src
[0])[0];
1096 sampler
= create_immed(b
, 0);
1097 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1103 info
.flags
|= IR3_INSTR_S2EN
;
1104 unsigned slot
= nir_src_as_uint(intr
->src
[0]);
1105 unsigned tex_idx
= ir3_image_to_tex(&ctx
->so
->image_mapping
, slot
);
1106 struct ir3_instruction
*texture
, *sampler
;
1108 texture
= create_immed_typed(ctx
->block
, tex_idx
, TYPE_U16
);
1109 sampler
= create_immed_typed(ctx
->block
, tex_idx
, TYPE_U16
);
1111 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1120 static struct ir3_instruction
*
1121 emit_sam(struct ir3_context
*ctx
, opc_t opc
, struct tex_src_info info
,
1122 type_t type
, unsigned wrmask
, struct ir3_instruction
*src0
,
1123 struct ir3_instruction
*src1
)
1125 struct ir3_instruction
*sam
, *addr
;
1126 if (info
.flags
& IR3_INSTR_A1EN
) {
1127 addr
= ir3_get_addr1(ctx
, info
.a1_val
);
1129 sam
= ir3_SAM(ctx
->block
, opc
, type
, 0b1111, info
.flags
,
1130 info
.samp_tex
, src0
, src1
);
1131 if (info
.flags
& IR3_INSTR_A1EN
) {
1132 ir3_instr_set_address(sam
, addr
);
1134 if (info
.flags
& IR3_INSTR_B
) {
1135 sam
->cat5
.tex_base
= info
.base
;
1136 sam
->cat5
.samp
= info
.combined_idx
;
1141 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1143 emit_intrinsic_load_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1144 struct ir3_instruction
**dst
)
1146 struct ir3_block
*b
= ctx
->block
;
1147 struct tex_src_info info
= get_image_samp_tex_src(ctx
, intr
);
1148 struct ir3_instruction
*sam
;
1149 struct ir3_instruction
* const *src0
= ir3_get_src(ctx
, &intr
->src
[1]);
1150 struct ir3_instruction
*coords
[4];
1151 unsigned flags
, ncoords
= ir3_get_image_coords(intr
, &flags
);
1152 type_t type
= ir3_get_type_for_image_intrinsic(intr
);
1154 /* hmm, this seems a bit odd, but it is what blob does and (at least
1155 * a5xx) just faults on bogus addresses otherwise:
1157 if (flags
& IR3_INSTR_3D
) {
1158 flags
&= ~IR3_INSTR_3D
;
1159 flags
|= IR3_INSTR_A
;
1161 info
.flags
|= flags
;
1163 for (unsigned i
= 0; i
< ncoords
; i
++)
1164 coords
[i
] = src0
[i
];
1167 coords
[ncoords
++] = create_immed(b
, 0);
1169 sam
= emit_sam(ctx
, OPC_ISAM
, info
, type
, 0b1111,
1170 ir3_create_collect(ctx
, coords
, ncoords
), NULL
);
1172 sam
->barrier_class
= IR3_BARRIER_IMAGE_R
;
1173 sam
->barrier_conflict
= IR3_BARRIER_IMAGE_W
;
1175 ir3_split_dest(b
, dst
, sam
, 0, 4);
1178 /* A4xx version of image_size, see ir3_a6xx.c for newer resinfo version. */
1180 emit_intrinsic_image_size_tex(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1181 struct ir3_instruction
**dst
)
1183 struct ir3_block
*b
= ctx
->block
;
1184 struct tex_src_info info
= get_image_samp_tex_src(ctx
, intr
);
1185 struct ir3_instruction
*sam
, *lod
;
1186 unsigned flags
, ncoords
= ir3_get_image_coords(intr
, &flags
);
1187 type_t dst_type
= nir_dest_bit_size(intr
->dest
) == 16 ?
1188 TYPE_U16
: TYPE_U32
;
1190 info
.flags
|= flags
;
1191 lod
= create_immed(b
, 0);
1192 sam
= emit_sam(ctx
, OPC_GETSIZE
, info
, dst_type
, 0b1111, lod
, NULL
);
1194 /* Array size actually ends up in .w rather than .z. This doesn't
1195 * matter for miplevel 0, but for higher mips the value in z is
1196 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1197 * returned, which means that we have to add 1 to it for arrays for
1200 * Note use a temporary dst and then copy, since the size of the dst
1201 * array that is passed in is based on nir's understanding of the
1202 * result size, not the hardware's
1204 struct ir3_instruction
*tmp
[4];
1206 ir3_split_dest(b
, tmp
, sam
, 0, 4);
1208 /* get_size instruction returns size in bytes instead of texels
1209 * for imageBuffer, so we need to divide it by the pixel size
1210 * of the image format.
1212 * TODO: This is at least true on a5xx. Check other gens.
1214 if (nir_intrinsic_image_dim(intr
) == GLSL_SAMPLER_DIM_BUF
) {
1215 /* Since all the possible values the divisor can take are
1216 * power-of-two (4, 8, or 16), the division is implemented
1218 * During shader setup, the log2 of the image format's
1219 * bytes-per-pixel should have been emitted in 2nd slot of
1220 * image_dims. See ir3_shader::emit_image_dims().
1222 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
1223 unsigned cb
= regid(const_state
->offsets
.image_dims
, 0) +
1224 const_state
->image_dims
.off
[nir_src_as_uint(intr
->src
[0])];
1225 struct ir3_instruction
*aux
= create_uniform(b
, cb
+ 1);
1227 tmp
[0] = ir3_SHR_B(b
, tmp
[0], 0, aux
, 0);
1230 for (unsigned i
= 0; i
< ncoords
; i
++)
1233 if (flags
& IR3_INSTR_A
) {
1234 if (ctx
->compiler
->levels_add_one
) {
1235 dst
[ncoords
-1] = ir3_ADD_U(b
, tmp
[3], 0, create_immed(b
, 1), 0);
1237 dst
[ncoords
-1] = ir3_MOV(b
, tmp
[3], TYPE_U32
);
1243 emit_intrinsic_barrier(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1245 struct ir3_block
*b
= ctx
->block
;
1246 struct ir3_instruction
*barrier
;
1248 switch (intr
->intrinsic
) {
1249 case nir_intrinsic_control_barrier
:
1250 barrier
= ir3_BAR(b
);
1251 barrier
->cat7
.g
= true;
1252 barrier
->cat7
.l
= true;
1253 barrier
->flags
= IR3_INSTR_SS
| IR3_INSTR_SY
;
1254 barrier
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1256 case nir_intrinsic_memory_barrier
:
1257 barrier
= ir3_FENCE(b
);
1258 barrier
->cat7
.g
= true;
1259 barrier
->cat7
.r
= true;
1260 barrier
->cat7
.w
= true;
1261 barrier
->cat7
.l
= true;
1262 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
|
1263 IR3_BARRIER_BUFFER_W
;
1264 barrier
->barrier_conflict
=
1265 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1266 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1268 case nir_intrinsic_memory_barrier_buffer
:
1269 barrier
= ir3_FENCE(b
);
1270 barrier
->cat7
.g
= true;
1271 barrier
->cat7
.r
= true;
1272 barrier
->cat7
.w
= true;
1273 barrier
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1274 barrier
->barrier_conflict
= IR3_BARRIER_BUFFER_R
|
1275 IR3_BARRIER_BUFFER_W
;
1277 case nir_intrinsic_memory_barrier_image
:
1278 // TODO double check if this should have .g set
1279 barrier
= ir3_FENCE(b
);
1280 barrier
->cat7
.g
= true;
1281 barrier
->cat7
.r
= true;
1282 barrier
->cat7
.w
= true;
1283 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1284 barrier
->barrier_conflict
= IR3_BARRIER_IMAGE_R
|
1285 IR3_BARRIER_IMAGE_W
;
1287 case nir_intrinsic_memory_barrier_shared
:
1288 barrier
= ir3_FENCE(b
);
1289 barrier
->cat7
.g
= true;
1290 barrier
->cat7
.l
= true;
1291 barrier
->cat7
.r
= true;
1292 barrier
->cat7
.w
= true;
1293 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
;
1294 barrier
->barrier_conflict
= IR3_BARRIER_SHARED_R
|
1295 IR3_BARRIER_SHARED_W
;
1297 case nir_intrinsic_group_memory_barrier
:
1298 barrier
= ir3_FENCE(b
);
1299 barrier
->cat7
.g
= true;
1300 barrier
->cat7
.l
= true;
1301 barrier
->cat7
.r
= true;
1302 barrier
->cat7
.w
= true;
1303 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
|
1304 IR3_BARRIER_IMAGE_W
|
1305 IR3_BARRIER_BUFFER_W
;
1306 barrier
->barrier_conflict
=
1307 IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
|
1308 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1309 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1315 /* make sure barrier doesn't get DCE'd */
1316 array_insert(b
, b
->keeps
, barrier
);
1319 static void add_sysval_input_compmask(struct ir3_context
*ctx
,
1320 gl_system_value slot
, unsigned compmask
,
1321 struct ir3_instruction
*instr
)
1323 struct ir3_shader_variant
*so
= ctx
->so
;
1324 unsigned n
= so
->inputs_count
++;
1326 assert(instr
->opc
== OPC_META_INPUT
);
1327 instr
->input
.inidx
= n
;
1328 instr
->input
.sysval
= slot
;
1330 so
->inputs
[n
].sysval
= true;
1331 so
->inputs
[n
].slot
= slot
;
1332 so
->inputs
[n
].compmask
= compmask
;
1333 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
1337 static struct ir3_instruction
*
1338 create_sysval_input(struct ir3_context
*ctx
, gl_system_value slot
,
1342 struct ir3_instruction
*sysval
= create_input(ctx
, compmask
);
1343 add_sysval_input_compmask(ctx
, slot
, compmask
, sysval
);
1347 static struct ir3_instruction
*
1348 get_barycentric_centroid(struct ir3_context
*ctx
)
1350 if (!ctx
->ij_centroid
) {
1351 struct ir3_instruction
*xy
[2];
1352 struct ir3_instruction
*ij
;
1354 ij
= create_sysval_input(ctx
, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID
, 0x3);
1355 ir3_split_dest(ctx
->block
, xy
, ij
, 0, 2);
1357 ctx
->ij_centroid
= ir3_create_collect(ctx
, xy
, 2);
1360 return ctx
->ij_centroid
;
1363 static struct ir3_instruction
*
1364 get_barycentric_sample(struct ir3_context
*ctx
)
1366 if (!ctx
->ij_sample
) {
1367 struct ir3_instruction
*xy
[2];
1368 struct ir3_instruction
*ij
;
1370 ij
= create_sysval_input(ctx
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE
, 0x3);
1371 ir3_split_dest(ctx
->block
, xy
, ij
, 0, 2);
1373 ctx
->ij_sample
= ir3_create_collect(ctx
, xy
, 2);
1376 return ctx
->ij_sample
;
1379 static struct ir3_instruction
*
1380 get_barycentric_pixel(struct ir3_context
*ctx
)
1382 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1383 * this to create ij_pixel only on demand:
1385 return ctx
->ij_pixel
;
1388 static struct ir3_instruction
*
1389 get_frag_coord(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1391 if (!ctx
->frag_coord
) {
1392 struct ir3_block
*b
= ctx
->in_block
;
1393 struct ir3_instruction
*xyzw
[4];
1394 struct ir3_instruction
*hw_frag_coord
;
1396 hw_frag_coord
= create_sysval_input(ctx
, SYSTEM_VALUE_FRAG_COORD
, 0xf);
1397 ir3_split_dest(b
, xyzw
, hw_frag_coord
, 0, 4);
1399 /* for frag_coord.xy, we get unsigned values.. we need
1400 * to subtract (integer) 8 and divide by 16 (right-
1401 * shift by 4) then convert to float:
1405 * mov.u32f32 dst, tmp
1408 for (int i
= 0; i
< 2; i
++) {
1409 xyzw
[i
] = ir3_COV(b
, xyzw
[i
], TYPE_U32
, TYPE_F32
);
1410 xyzw
[i
] = ir3_MUL_F(b
, xyzw
[i
], 0, create_immed(b
, fui(1.0 / 16.0)), 0);
1413 ctx
->frag_coord
= ir3_create_collect(ctx
, xyzw
, 4);
1416 ctx
->so
->fragcoord_compmask
|=
1417 nir_ssa_def_components_read(&intr
->dest
.ssa
);
1419 return ctx
->frag_coord
;
1423 emit_intrinsic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1425 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1426 struct ir3_instruction
**dst
;
1427 struct ir3_instruction
* const *src
;
1428 struct ir3_block
*b
= ctx
->block
;
1429 unsigned dest_components
= nir_intrinsic_dest_components(intr
);
1432 if (info
->has_dest
) {
1433 dst
= ir3_get_dst(ctx
, &intr
->dest
, dest_components
);
1438 const unsigned primitive_param
= ctx
->so
->shader
->const_state
.offsets
.primitive_param
* 4;
1439 const unsigned primitive_map
= ctx
->so
->shader
->const_state
.offsets
.primitive_map
* 4;
1441 switch (intr
->intrinsic
) {
1442 case nir_intrinsic_load_uniform
:
1443 idx
= nir_intrinsic_base(intr
);
1444 if (nir_src_is_const(intr
->src
[0])) {
1445 idx
+= nir_src_as_uint(intr
->src
[0]);
1446 for (int i
= 0; i
< dest_components
; i
++) {
1447 dst
[i
] = create_uniform_typed(b
, idx
+ i
,
1448 nir_dest_bit_size(intr
->dest
) == 16 ? TYPE_F16
: TYPE_F32
);
1451 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1452 for (int i
= 0; i
< dest_components
; i
++) {
1453 dst
[i
] = create_uniform_indirect(b
, idx
+ i
,
1454 ir3_get_addr0(ctx
, src
[0], 1));
1456 /* NOTE: if relative addressing is used, we set
1457 * constlen in the compiler (to worst-case value)
1458 * since we don't know in the assembler what the max
1459 * addr reg value can be:
1461 ctx
->so
->constlen
= MAX2(ctx
->so
->constlen
,
1462 ctx
->so
->shader
->ubo_state
.size
/ 16);
1466 case nir_intrinsic_load_vs_primitive_stride_ir3
:
1467 dst
[0] = create_uniform(b
, primitive_param
+ 0);
1469 case nir_intrinsic_load_vs_vertex_stride_ir3
:
1470 dst
[0] = create_uniform(b
, primitive_param
+ 1);
1472 case nir_intrinsic_load_hs_patch_stride_ir3
:
1473 dst
[0] = create_uniform(b
, primitive_param
+ 2);
1475 case nir_intrinsic_load_patch_vertices_in
:
1476 dst
[0] = create_uniform(b
, primitive_param
+ 3);
1478 case nir_intrinsic_load_tess_param_base_ir3
:
1479 dst
[0] = create_uniform(b
, primitive_param
+ 4);
1480 dst
[1] = create_uniform(b
, primitive_param
+ 5);
1482 case nir_intrinsic_load_tess_factor_base_ir3
:
1483 dst
[0] = create_uniform(b
, primitive_param
+ 6);
1484 dst
[1] = create_uniform(b
, primitive_param
+ 7);
1487 case nir_intrinsic_load_primitive_location_ir3
:
1488 idx
= nir_intrinsic_driver_location(intr
);
1489 dst
[0] = create_uniform(b
, primitive_map
+ idx
);
1492 case nir_intrinsic_load_gs_header_ir3
:
1493 dst
[0] = ctx
->gs_header
;
1495 case nir_intrinsic_load_tcs_header_ir3
:
1496 dst
[0] = ctx
->tcs_header
;
1499 case nir_intrinsic_load_primitive_id
:
1500 dst
[0] = ctx
->primitive_id
;
1503 case nir_intrinsic_load_tess_coord
:
1504 if (!ctx
->tess_coord
) {
1506 create_sysval_input(ctx
, SYSTEM_VALUE_TESS_COORD
, 0x3);
1508 ir3_split_dest(b
, dst
, ctx
->tess_coord
, 0, 2);
1510 /* Unused, but ir3_put_dst() below wants to free something */
1511 dst
[2] = create_immed(b
, 0);
1514 case nir_intrinsic_end_patch_ir3
:
1515 assert(ctx
->so
->type
== MESA_SHADER_TESS_CTRL
);
1516 struct ir3_instruction
*end
= ir3_PREDE(b
);
1517 array_insert(b
, b
->keeps
, end
);
1519 end
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1520 end
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
1523 case nir_intrinsic_store_global_ir3
: {
1524 struct ir3_instruction
*value
, *addr
, *offset
;
1525 unsigned ncomp
= nir_intrinsic_src_components(intr
, 0);
1527 addr
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1528 ir3_get_src(ctx
, &intr
->src
[1])[0],
1529 ir3_get_src(ctx
, &intr
->src
[1])[1]
1532 offset
= ir3_get_src(ctx
, &intr
->src
[2])[0];
1534 value
= ir3_create_collect(ctx
, ir3_get_src(ctx
, &intr
->src
[0]), ncomp
);
1536 struct ir3_instruction
*stg
=
1537 ir3_STG_G(ctx
->block
, addr
, 0, value
, 0,
1538 create_immed(ctx
->block
, ncomp
), 0, offset
, 0);
1539 stg
->cat6
.type
= TYPE_U32
;
1540 stg
->cat6
.iim_val
= 1;
1542 array_insert(b
, b
->keeps
, stg
);
1544 stg
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1545 stg
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1549 case nir_intrinsic_load_global_ir3
: {
1550 struct ir3_instruction
*addr
, *offset
;
1552 addr
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1553 ir3_get_src(ctx
, &intr
->src
[0])[0],
1554 ir3_get_src(ctx
, &intr
->src
[0])[1]
1557 offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
1559 struct ir3_instruction
*load
=
1560 ir3_LDG(b
, addr
, 0, create_immed(ctx
->block
, dest_components
),
1562 load
->cat6
.type
= TYPE_U32
;
1563 load
->regs
[0]->wrmask
= MASK(dest_components
);
1565 load
->barrier_class
= IR3_BARRIER_BUFFER_R
;
1566 load
->barrier_conflict
= IR3_BARRIER_BUFFER_W
;
1568 ir3_split_dest(b
, dst
, load
, 0, dest_components
);
1572 case nir_intrinsic_load_ubo
:
1573 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1575 case nir_intrinsic_load_ubo_ir3
:
1576 emit_intrinsic_load_ubo_ldc(ctx
, intr
, dst
);
1578 case nir_intrinsic_load_frag_coord
:
1579 ir3_split_dest(b
, dst
, get_frag_coord(ctx
, intr
), 0, 4);
1581 case nir_intrinsic_load_sample_pos_from_id
: {
1582 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1583 * but that doesn't seem necessary.
1585 struct ir3_instruction
*offset
=
1586 ir3_RGETPOS(b
, ir3_get_src(ctx
, &intr
->src
[0])[0], 0);
1587 offset
->regs
[0]->wrmask
= 0x3;
1588 offset
->cat5
.type
= TYPE_F32
;
1590 ir3_split_dest(b
, dst
, offset
, 0, 2);
1594 case nir_intrinsic_load_size_ir3
:
1595 if (!ctx
->ij_size
) {
1597 create_sysval_input(ctx
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE
, 0x1);
1599 dst
[0] = ctx
->ij_size
;
1601 case nir_intrinsic_load_barycentric_centroid
:
1602 ir3_split_dest(b
, dst
, get_barycentric_centroid(ctx
), 0, 2);
1604 case nir_intrinsic_load_barycentric_sample
:
1605 if (ctx
->so
->key
.msaa
) {
1606 ir3_split_dest(b
, dst
, get_barycentric_sample(ctx
), 0, 2);
1608 ir3_split_dest(b
, dst
, get_barycentric_pixel(ctx
), 0, 2);
1611 case nir_intrinsic_load_barycentric_pixel
:
1612 ir3_split_dest(b
, dst
, get_barycentric_pixel(ctx
), 0, 2);
1614 case nir_intrinsic_load_interpolated_input
:
1615 idx
= nir_intrinsic_base(intr
);
1616 comp
= nir_intrinsic_component(intr
);
1617 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1618 if (nir_src_is_const(intr
->src
[1])) {
1619 struct ir3_instruction
*coord
= ir3_create_collect(ctx
, src
, 2);
1620 idx
+= nir_src_as_uint(intr
->src
[1]);
1621 for (int i
= 0; i
< dest_components
; i
++) {
1622 unsigned inloc
= idx
* 4 + i
+ comp
;
1623 if (ctx
->so
->inputs
[idx
].bary
&&
1624 !ctx
->so
->inputs
[idx
].use_ldlv
) {
1625 dst
[i
] = ir3_BARY_F(b
, create_immed(b
, inloc
), 0, coord
, 0);
1627 /* for non-varyings use the pre-setup input, since
1628 * that is easier than mapping things back to a
1629 * nir_variable to figure out what it is.
1631 dst
[i
] = ctx
->inputs
[inloc
];
1632 compile_assert(ctx
, dst
[i
]);
1636 ir3_context_error(ctx
, "unhandled");
1639 case nir_intrinsic_load_input
:
1640 idx
= nir_intrinsic_base(intr
);
1641 comp
= nir_intrinsic_component(intr
);
1642 if (nir_src_is_const(intr
->src
[0])) {
1643 idx
+= nir_src_as_uint(intr
->src
[0]);
1644 for (int i
= 0; i
< dest_components
; i
++) {
1645 unsigned n
= idx
* 4 + i
+ comp
;
1646 dst
[i
] = ctx
->inputs
[n
];
1647 compile_assert(ctx
, ctx
->inputs
[n
]);
1650 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1651 struct ir3_instruction
*collect
=
1652 ir3_create_collect(ctx
, ctx
->ir
->inputs
, ctx
->ninputs
);
1653 struct ir3_instruction
*addr
= ir3_get_addr0(ctx
, src
[0], 4);
1654 for (int i
= 0; i
< dest_components
; i
++) {
1655 unsigned n
= idx
* 4 + i
+ comp
;
1656 dst
[i
] = create_indirect_load(ctx
, ctx
->ninputs
,
1661 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1662 * pass and replaced by an ir3-specifc version that adds the
1663 * dword-offset in the last source.
1665 case nir_intrinsic_load_ssbo_ir3
:
1666 ctx
->funcs
->emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
1668 case nir_intrinsic_store_ssbo_ir3
:
1669 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1670 !ctx
->s
->info
.fs
.early_fragment_tests
)
1671 ctx
->so
->no_earlyz
= true;
1672 ctx
->funcs
->emit_intrinsic_store_ssbo(ctx
, intr
);
1674 case nir_intrinsic_get_buffer_size
:
1675 emit_intrinsic_ssbo_size(ctx
, intr
, dst
);
1677 case nir_intrinsic_ssbo_atomic_add_ir3
:
1678 case nir_intrinsic_ssbo_atomic_imin_ir3
:
1679 case nir_intrinsic_ssbo_atomic_umin_ir3
:
1680 case nir_intrinsic_ssbo_atomic_imax_ir3
:
1681 case nir_intrinsic_ssbo_atomic_umax_ir3
:
1682 case nir_intrinsic_ssbo_atomic_and_ir3
:
1683 case nir_intrinsic_ssbo_atomic_or_ir3
:
1684 case nir_intrinsic_ssbo_atomic_xor_ir3
:
1685 case nir_intrinsic_ssbo_atomic_exchange_ir3
:
1686 case nir_intrinsic_ssbo_atomic_comp_swap_ir3
:
1687 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1688 !ctx
->s
->info
.fs
.early_fragment_tests
)
1689 ctx
->so
->no_earlyz
= true;
1690 dst
[0] = ctx
->funcs
->emit_intrinsic_atomic_ssbo(ctx
, intr
);
1692 case nir_intrinsic_load_shared
:
1693 emit_intrinsic_load_shared(ctx
, intr
, dst
);
1695 case nir_intrinsic_store_shared
:
1696 emit_intrinsic_store_shared(ctx
, intr
);
1698 case nir_intrinsic_shared_atomic_add
:
1699 case nir_intrinsic_shared_atomic_imin
:
1700 case nir_intrinsic_shared_atomic_umin
:
1701 case nir_intrinsic_shared_atomic_imax
:
1702 case nir_intrinsic_shared_atomic_umax
:
1703 case nir_intrinsic_shared_atomic_and
:
1704 case nir_intrinsic_shared_atomic_or
:
1705 case nir_intrinsic_shared_atomic_xor
:
1706 case nir_intrinsic_shared_atomic_exchange
:
1707 case nir_intrinsic_shared_atomic_comp_swap
:
1708 dst
[0] = emit_intrinsic_atomic_shared(ctx
, intr
);
1710 case nir_intrinsic_image_load
:
1711 emit_intrinsic_load_image(ctx
, intr
, dst
);
1713 case nir_intrinsic_bindless_image_load
:
1714 /* Bindless uses the IBO state, which doesn't have swizzle filled out,
1715 * so using isam doesn't work.
1717 * TODO: can we use isam if we fill out more fields?
1719 ctx
->funcs
->emit_intrinsic_load_image(ctx
, intr
, dst
);
1721 case nir_intrinsic_image_store
:
1722 case nir_intrinsic_bindless_image_store
:
1723 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1724 !ctx
->s
->info
.fs
.early_fragment_tests
)
1725 ctx
->so
->no_earlyz
= true;
1726 ctx
->funcs
->emit_intrinsic_store_image(ctx
, intr
);
1728 case nir_intrinsic_image_size
:
1729 case nir_intrinsic_bindless_image_size
:
1730 ctx
->funcs
->emit_intrinsic_image_size(ctx
, intr
, dst
);
1732 case nir_intrinsic_image_atomic_add
:
1733 case nir_intrinsic_bindless_image_atomic_add
:
1734 case nir_intrinsic_image_atomic_imin
:
1735 case nir_intrinsic_bindless_image_atomic_imin
:
1736 case nir_intrinsic_image_atomic_umin
:
1737 case nir_intrinsic_bindless_image_atomic_umin
:
1738 case nir_intrinsic_image_atomic_imax
:
1739 case nir_intrinsic_bindless_image_atomic_imax
:
1740 case nir_intrinsic_image_atomic_umax
:
1741 case nir_intrinsic_bindless_image_atomic_umax
:
1742 case nir_intrinsic_image_atomic_and
:
1743 case nir_intrinsic_bindless_image_atomic_and
:
1744 case nir_intrinsic_image_atomic_or
:
1745 case nir_intrinsic_bindless_image_atomic_or
:
1746 case nir_intrinsic_image_atomic_xor
:
1747 case nir_intrinsic_bindless_image_atomic_xor
:
1748 case nir_intrinsic_image_atomic_exchange
:
1749 case nir_intrinsic_bindless_image_atomic_exchange
:
1750 case nir_intrinsic_image_atomic_comp_swap
:
1751 case nir_intrinsic_bindless_image_atomic_comp_swap
:
1752 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1753 !ctx
->s
->info
.fs
.early_fragment_tests
)
1754 ctx
->so
->no_earlyz
= true;
1755 dst
[0] = ctx
->funcs
->emit_intrinsic_atomic_image(ctx
, intr
);
1757 case nir_intrinsic_control_barrier
:
1758 case nir_intrinsic_memory_barrier
:
1759 case nir_intrinsic_group_memory_barrier
:
1760 case nir_intrinsic_memory_barrier_buffer
:
1761 case nir_intrinsic_memory_barrier_image
:
1762 case nir_intrinsic_memory_barrier_shared
:
1763 emit_intrinsic_barrier(ctx
, intr
);
1764 /* note that blk ptr no longer valid, make that obvious: */
1767 case nir_intrinsic_store_output
:
1768 idx
= nir_intrinsic_base(intr
);
1769 comp
= nir_intrinsic_component(intr
);
1770 compile_assert(ctx
, nir_src_is_const(intr
->src
[1]));
1771 idx
+= nir_src_as_uint(intr
->src
[1]);
1773 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1774 for (int i
= 0; i
< nir_intrinsic_src_components(intr
, 0); i
++) {
1775 unsigned n
= idx
* 4 + i
+ comp
;
1776 ctx
->outputs
[n
] = src
[i
];
1779 case nir_intrinsic_load_base_vertex
:
1780 case nir_intrinsic_load_first_vertex
:
1781 if (!ctx
->basevertex
) {
1782 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
1784 dst
[0] = ctx
->basevertex
;
1786 case nir_intrinsic_load_base_instance
:
1787 if (!ctx
->base_instance
) {
1788 ctx
->base_instance
= create_driver_param(ctx
, IR3_DP_INSTID_BASE
);
1790 dst
[0] = ctx
->base_instance
;
1792 case nir_intrinsic_load_vertex_id_zero_base
:
1793 case nir_intrinsic_load_vertex_id
:
1794 if (!ctx
->vertex_id
) {
1795 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
1796 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
1797 ctx
->vertex_id
= create_sysval_input(ctx
, sv
, 0x1);
1799 dst
[0] = ctx
->vertex_id
;
1801 case nir_intrinsic_load_instance_id
:
1802 if (!ctx
->instance_id
) {
1803 ctx
->instance_id
= create_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
, 0x1);
1805 dst
[0] = ctx
->instance_id
;
1807 case nir_intrinsic_load_sample_id
:
1808 ctx
->so
->per_samp
= true;
1810 case nir_intrinsic_load_sample_id_no_per_sample
:
1811 if (!ctx
->samp_id
) {
1812 ctx
->samp_id
= create_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_ID
, 0x1);
1813 ctx
->samp_id
->regs
[0]->flags
|= IR3_REG_HALF
;
1815 dst
[0] = ir3_COV(b
, ctx
->samp_id
, TYPE_U16
, TYPE_U32
);
1817 case nir_intrinsic_load_sample_mask_in
:
1818 if (!ctx
->samp_mask_in
) {
1819 ctx
->samp_mask_in
= create_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_MASK_IN
, 0x1);
1821 dst
[0] = ctx
->samp_mask_in
;
1823 case nir_intrinsic_load_user_clip_plane
:
1824 idx
= nir_intrinsic_ucp_id(intr
);
1825 for (int i
= 0; i
< dest_components
; i
++) {
1826 unsigned n
= idx
* 4 + i
;
1827 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
1830 case nir_intrinsic_load_front_face
:
1831 if (!ctx
->frag_face
) {
1832 ctx
->so
->frag_face
= true;
1833 ctx
->frag_face
= create_sysval_input(ctx
, SYSTEM_VALUE_FRONT_FACE
, 0x1);
1834 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
1836 /* for fragface, we get -1 for back and 0 for front. However this is
1837 * the inverse of what nir expects (where ~0 is true).
1839 dst
[0] = ir3_CMPS_S(b
,
1841 create_immed_typed(b
, 0, TYPE_U16
), 0);
1842 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
1844 case nir_intrinsic_load_local_invocation_id
:
1845 if (!ctx
->local_invocation_id
) {
1846 ctx
->local_invocation_id
=
1847 create_sysval_input(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
, 0x7);
1849 ir3_split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
1851 case nir_intrinsic_load_work_group_id
:
1852 if (!ctx
->work_group_id
) {
1853 ctx
->work_group_id
=
1854 create_sysval_input(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
, 0x7);
1855 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
1857 ir3_split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
1859 case nir_intrinsic_load_num_work_groups
:
1860 for (int i
= 0; i
< dest_components
; i
++) {
1861 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
1864 case nir_intrinsic_load_local_group_size
:
1865 for (int i
= 0; i
< dest_components
; i
++) {
1866 dst
[i
] = create_driver_param(ctx
, IR3_DP_LOCAL_GROUP_SIZE_X
+ i
);
1869 case nir_intrinsic_discard_if
:
1870 case nir_intrinsic_discard
: {
1871 struct ir3_instruction
*cond
, *kill
;
1873 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1874 /* conditional discard: */
1875 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1878 /* unconditional discard: */
1879 cond
= create_immed(b
, 1);
1882 /* NOTE: only cmps.*.* can write p0.x: */
1883 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1884 cond
->cat2
.condition
= IR3_COND_NE
;
1886 /* condition always goes in predicate register: */
1887 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1888 cond
->regs
[0]->flags
&= ~IR3_REG_SSA
;
1890 kill
= ir3_KILL(b
, cond
, 0);
1891 kill
->regs
[1]->num
= regid(REG_P0
, 0);
1892 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
1894 array_insert(b
, b
->keeps
, kill
);
1895 ctx
->so
->has_kill
= true;
1900 case nir_intrinsic_cond_end_ir3
: {
1901 struct ir3_instruction
*cond
, *kill
;
1903 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1906 /* NOTE: only cmps.*.* can write p0.x: */
1907 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1908 cond
->cat2
.condition
= IR3_COND_NE
;
1910 /* condition always goes in predicate register: */
1911 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1913 kill
= ir3_PREDT(b
, cond
, 0);
1915 kill
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1916 kill
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
1918 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
1919 array_insert(b
, b
->keeps
, kill
);
1923 case nir_intrinsic_load_shared_ir3
:
1924 emit_intrinsic_load_shared_ir3(ctx
, intr
, dst
);
1926 case nir_intrinsic_store_shared_ir3
:
1927 emit_intrinsic_store_shared_ir3(ctx
, intr
);
1929 case nir_intrinsic_bindless_resource_ir3
:
1930 dst
[0] = ir3_get_src(ctx
, &intr
->src
[0])[0];
1933 ir3_context_error(ctx
, "Unhandled intrinsic type: %s\n",
1934 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1939 ir3_put_dst(ctx
, &intr
->dest
);
1943 emit_load_const(struct ir3_context
*ctx
, nir_load_const_instr
*instr
)
1945 struct ir3_instruction
**dst
= ir3_get_dst_ssa(ctx
, &instr
->def
,
1946 instr
->def
.num_components
);
1948 if (instr
->def
.bit_size
== 16) {
1949 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1950 dst
[i
] = create_immed_typed(ctx
->block
,
1951 instr
->value
[i
].u16
,
1954 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1955 dst
[i
] = create_immed_typed(ctx
->block
,
1956 instr
->value
[i
].u32
,
1963 emit_undef(struct ir3_context
*ctx
, nir_ssa_undef_instr
*undef
)
1965 struct ir3_instruction
**dst
= ir3_get_dst_ssa(ctx
, &undef
->def
,
1966 undef
->def
.num_components
);
1967 type_t type
= (undef
->def
.bit_size
== 16) ? TYPE_U16
: TYPE_U32
;
1969 /* backend doesn't want undefined instructions, so just plug
1972 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
1973 dst
[i
] = create_immed_typed(ctx
->block
, fui(0.0), type
);
1977 * texture fetch/sample instructions:
1981 get_tex_dest_type(nir_tex_instr
*tex
)
1985 switch (nir_alu_type_get_base_type(tex
->dest_type
)) {
1986 case nir_type_invalid
:
1987 case nir_type_float
:
1988 type
= nir_dest_bit_size(tex
->dest
) == 16 ? TYPE_F16
: TYPE_F32
;
1991 type
= nir_dest_bit_size(tex
->dest
) == 16 ? TYPE_S16
: TYPE_S32
;
1995 type
= nir_dest_bit_size(tex
->dest
) == 16 ? TYPE_U16
: TYPE_U32
;
1998 unreachable("bad dest_type");
2005 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
2007 unsigned coords
= glsl_get_sampler_dim_coordinate_components(tex
->sampler_dim
);
2010 /* note: would use tex->coord_components.. except txs.. also,
2011 * since array index goes after shadow ref, we don't want to
2015 flags
|= IR3_INSTR_3D
;
2017 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2018 flags
|= IR3_INSTR_S
;
2020 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
2021 flags
|= IR3_INSTR_A
;
2027 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
2028 * or immediate (in which case it will get lowered later to a non .s2en
2029 * version of the tex instruction which encode tex/samp as immediates:
2031 static struct tex_src_info
2032 get_tex_samp_tex_src(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2034 struct ir3_block
*b
= ctx
->block
;
2035 struct tex_src_info info
= { 0 };
2036 int texture_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_texture_handle
);
2037 int sampler_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_sampler_handle
);
2038 struct ir3_instruction
*texture
, *sampler
;
2040 if (texture_idx
>= 0 || sampler_idx
>= 0) {
2042 info
.flags
|= IR3_INSTR_B
;
2044 /* Gather information required to determine which encoding to
2045 * choose as well as for prefetch.
2047 nir_intrinsic_instr
*bindless_tex
= NULL
;
2049 if (texture_idx
>= 0) {
2050 ctx
->so
->bindless_tex
= true;
2051 bindless_tex
= ir3_bindless_resource(tex
->src
[texture_idx
].src
);
2052 assert(bindless_tex
);
2053 info
.tex_base
= nir_intrinsic_desc_set(bindless_tex
);
2054 tex_const
= nir_src_is_const(bindless_tex
->src
[0]);
2056 info
.tex_idx
= nir_src_as_uint(bindless_tex
->src
[0]);
2058 /* To simplify some of the logic below, assume the index is
2059 * constant 0 when it's not enabled.
2064 nir_intrinsic_instr
*bindless_samp
= NULL
;
2066 if (sampler_idx
>= 0) {
2067 ctx
->so
->bindless_samp
= true;
2068 bindless_samp
= ir3_bindless_resource(tex
->src
[sampler_idx
].src
);
2069 assert(bindless_samp
);
2070 info
.samp_base
= nir_intrinsic_desc_set(bindless_samp
);
2071 samp_const
= nir_src_is_const(bindless_samp
->src
[0]);
2073 info
.samp_idx
= nir_src_as_uint(bindless_samp
->src
[0]);
2079 /* Choose encoding. */
2080 if (tex_const
&& samp_const
&& info
.tex_idx
< 256 && info
.samp_idx
< 256) {
2081 if (info
.tex_idx
< 16 && info
.samp_idx
< 16 &&
2082 (!bindless_tex
|| !bindless_samp
|| info
.tex_base
== info
.samp_base
)) {
2083 /* Everything fits within the instruction */
2084 info
.base
= info
.tex_base
;
2085 info
.combined_idx
= info
.samp_idx
| (info
.tex_idx
<< 4);
2087 info
.base
= info
.tex_base
;
2088 info
.a1_val
= info
.tex_idx
<< 3 | info
.samp_base
;
2089 info
.combined_idx
= info
.samp_idx
;
2090 info
.flags
|= IR3_INSTR_A1EN
;
2092 info
.samp_tex
= NULL
;
2094 info
.flags
|= IR3_INSTR_S2EN
;
2095 /* In the indirect case, we only use a1.x to store the sampler
2096 * base if it differs from the texture base.
2098 if (!bindless_tex
|| !bindless_samp
|| info
.tex_base
== info
.samp_base
) {
2099 info
.base
= info
.tex_base
;
2101 info
.base
= info
.tex_base
;
2102 info
.a1_val
= info
.samp_base
;
2103 info
.flags
|= IR3_INSTR_A1EN
;
2106 /* Note: the indirect source is now a vec2 instead of hvec2, and
2107 * for some reason the texture and sampler are swapped.
2109 struct ir3_instruction
*texture
, *sampler
;
2112 texture
= ir3_get_src(ctx
, &tex
->src
[texture_idx
].src
)[0];
2114 texture
= create_immed(b
, 0);
2117 if (bindless_samp
) {
2118 sampler
= ir3_get_src(ctx
, &tex
->src
[sampler_idx
].src
)[0];
2120 sampler
= create_immed(b
, 0);
2122 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
2128 info
.flags
|= IR3_INSTR_S2EN
;
2129 texture_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_texture_offset
);
2130 sampler_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_sampler_offset
);
2131 if (texture_idx
>= 0) {
2132 texture
= ir3_get_src(ctx
, &tex
->src
[texture_idx
].src
)[0];
2133 texture
= ir3_COV(ctx
->block
, texture
, TYPE_U32
, TYPE_U16
);
2135 /* TODO what to do for dynamic case? I guess we only need the
2136 * max index for astc srgb workaround so maybe not a problem
2137 * to worry about if we don't enable indirect samplers for
2140 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex
->texture_index
);
2141 texture
= create_immed_typed(ctx
->block
, tex
->texture_index
, TYPE_U16
);
2142 info
.tex_idx
= tex
->texture_index
;
2145 if (sampler_idx
>= 0) {
2146 sampler
= ir3_get_src(ctx
, &tex
->src
[sampler_idx
].src
)[0];
2147 sampler
= ir3_COV(ctx
->block
, sampler
, TYPE_U32
, TYPE_U16
);
2149 sampler
= create_immed_typed(ctx
->block
, tex
->sampler_index
, TYPE_U16
);
2150 info
.samp_idx
= tex
->texture_index
;
2153 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
2163 emit_tex(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2165 struct ir3_block
*b
= ctx
->block
;
2166 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
2167 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
2168 struct ir3_instruction
*lod
, *compare
, *proj
, *sample_index
;
2169 struct tex_src_info info
= { 0 };
2170 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
2171 unsigned i
, coords
, flags
, ncomp
;
2172 unsigned nsrc0
= 0, nsrc1
= 0;
2176 ncomp
= nir_dest_num_components(tex
->dest
);
2178 coord
= off
= ddx
= ddy
= NULL
;
2179 lod
= proj
= compare
= sample_index
= NULL
;
2181 dst
= ir3_get_dst(ctx
, &tex
->dest
, ncomp
);
2183 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
2184 switch (tex
->src
[i
].src_type
) {
2185 case nir_tex_src_coord
:
2186 coord
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
2188 case nir_tex_src_bias
:
2189 lod
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2192 case nir_tex_src_lod
:
2193 lod
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2196 case nir_tex_src_comparator
: /* shadow comparator */
2197 compare
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2199 case nir_tex_src_projector
:
2200 proj
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2203 case nir_tex_src_offset
:
2204 off
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
2207 case nir_tex_src_ddx
:
2208 ddx
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
2210 case nir_tex_src_ddy
:
2211 ddy
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
2213 case nir_tex_src_ms_index
:
2214 sample_index
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2216 case nir_tex_src_texture_offset
:
2217 case nir_tex_src_sampler_offset
:
2218 case nir_tex_src_texture_handle
:
2219 case nir_tex_src_sampler_handle
:
2220 /* handled in get_tex_samp_src() */
2223 ir3_context_error(ctx
, "Unhandled NIR tex src type: %d\n",
2224 tex
->src
[i
].src_type
);
2230 case nir_texop_tex_prefetch
:
2231 compile_assert(ctx
, !has_bias
);
2232 compile_assert(ctx
, !has_lod
);
2233 compile_assert(ctx
, !compare
);
2234 compile_assert(ctx
, !has_proj
);
2235 compile_assert(ctx
, !has_off
);
2236 compile_assert(ctx
, !ddx
);
2237 compile_assert(ctx
, !ddy
);
2238 compile_assert(ctx
, !sample_index
);
2239 compile_assert(ctx
, nir_tex_instr_src_index(tex
, nir_tex_src_texture_offset
) < 0);
2240 compile_assert(ctx
, nir_tex_instr_src_index(tex
, nir_tex_src_sampler_offset
) < 0);
2242 if (ctx
->so
->num_sampler_prefetch
< ctx
->prefetch_limit
) {
2243 opc
= OPC_META_TEX_PREFETCH
;
2244 ctx
->so
->num_sampler_prefetch
++;
2248 case nir_texop_tex
: opc
= has_lod
? OPC_SAML
: OPC_SAM
; break;
2249 case nir_texop_txb
: opc
= OPC_SAMB
; break;
2250 case nir_texop_txl
: opc
= OPC_SAML
; break;
2251 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
2252 case nir_texop_txf
: opc
= OPC_ISAML
; break;
2253 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
2255 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2256 * what blob does, seems gather is broken?), and a3xx did
2257 * not support it (but probably could also emulate).
2259 switch (tex
->component
) {
2260 case 0: opc
= OPC_GATHER4R
; break;
2261 case 1: opc
= OPC_GATHER4G
; break;
2262 case 2: opc
= OPC_GATHER4B
; break;
2263 case 3: opc
= OPC_GATHER4A
; break;
2266 case nir_texop_txf_ms_fb
:
2267 case nir_texop_txf_ms
: opc
= OPC_ISAMM
; break;
2269 ir3_context_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
2273 tex_info(tex
, &flags
, &coords
);
2276 * lay out the first argument in the proper order:
2277 * - actual coordinates first
2278 * - shadow reference
2281 * - starting at offset 4, dpdx.xy, dpdy.xy
2283 * bias/lod go into the second arg
2286 /* insert tex coords: */
2287 for (i
= 0; i
< coords
; i
++)
2292 /* scale up integer coords for TXF based on the LOD */
2293 if (ctx
->compiler
->unminify_coords
&& (opc
== OPC_ISAML
)) {
2295 for (i
= 0; i
< coords
; i
++)
2296 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
2300 /* hw doesn't do 1d, so we treat it as 2d with
2301 * height of 1, and patch up the y coord.
2304 src0
[nsrc0
++] = create_immed(b
, 0);
2306 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
2310 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2311 src0
[nsrc0
++] = compare
;
2313 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
2314 struct ir3_instruction
*idx
= coord
[coords
];
2316 /* the array coord for cube arrays needs 0.5 added to it */
2317 if (ctx
->compiler
->array_index_add_half
&& !is_isam(opc
))
2318 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
2320 src0
[nsrc0
++] = idx
;
2324 src0
[nsrc0
++] = proj
;
2325 flags
|= IR3_INSTR_P
;
2328 /* pad to 4, then ddx/ddy: */
2329 if (tex
->op
== nir_texop_txd
) {
2331 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2332 for (i
= 0; i
< coords
; i
++)
2333 src0
[nsrc0
++] = ddx
[i
];
2335 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2336 for (i
= 0; i
< coords
; i
++)
2337 src0
[nsrc0
++] = ddy
[i
];
2339 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2342 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2343 * with scaled x coord according to requested sample:
2345 if (opc
== OPC_ISAMM
) {
2346 if (ctx
->compiler
->txf_ms_with_isaml
) {
2347 /* the samples are laid out in x dimension as
2349 * x_ms = (x << ms) + sample_index;
2351 struct ir3_instruction
*ms
;
2352 ms
= create_immed(b
, (ctx
->samples
>> (2 * tex
->texture_index
)) & 3);
2354 src0
[0] = ir3_SHL_B(b
, src0
[0], 0, ms
, 0);
2355 src0
[0] = ir3_ADD_U(b
, src0
[0], 0, sample_index
, 0);
2359 src0
[nsrc0
++] = sample_index
;
2364 * second argument (if applicable):
2369 if (has_off
| has_lod
| has_bias
) {
2371 unsigned off_coords
= coords
;
2372 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2374 for (i
= 0; i
< off_coords
; i
++)
2375 src1
[nsrc1
++] = off
[i
];
2377 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
2378 flags
|= IR3_INSTR_O
;
2381 if (has_lod
| has_bias
)
2382 src1
[nsrc1
++] = lod
;
2385 type
= get_tex_dest_type(tex
);
2387 if (opc
== OPC_GETLOD
)
2391 if (tex
->op
== nir_texop_txf_ms_fb
) {
2392 /* only expect a single txf_ms_fb per shader: */
2393 compile_assert(ctx
, !ctx
->so
->fb_read
);
2394 compile_assert(ctx
, ctx
->so
->type
== MESA_SHADER_FRAGMENT
);
2396 ctx
->so
->fb_read
= true;
2397 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
2398 create_immed_typed(ctx
->block
, ctx
->so
->num_samp
, TYPE_U16
),
2399 create_immed_typed(ctx
->block
, ctx
->so
->num_samp
, TYPE_U16
),
2401 info
.flags
= IR3_INSTR_S2EN
;
2403 ctx
->so
->num_samp
++;
2405 info
= get_tex_samp_tex_src(ctx
, tex
);
2408 struct ir3_instruction
*col0
= ir3_create_collect(ctx
, src0
, nsrc0
);
2409 struct ir3_instruction
*col1
= ir3_create_collect(ctx
, src1
, nsrc1
);
2411 if (opc
== OPC_META_TEX_PREFETCH
) {
2412 int idx
= nir_tex_instr_src_index(tex
, nir_tex_src_coord
);
2414 compile_assert(ctx
, tex
->src
[idx
].src
.is_ssa
);
2416 sam
= ir3_META_TEX_PREFETCH(b
);
2417 __ssa_dst(sam
)->wrmask
= MASK(ncomp
); /* dst */
2418 __ssa_src(sam
, get_barycentric_pixel(ctx
), 0);
2419 sam
->prefetch
.input_offset
=
2420 ir3_nir_coord_offset(tex
->src
[idx
].src
.ssa
);
2421 /* make sure not to add irrelevant flags like S2EN */
2422 sam
->flags
= flags
| (info
.flags
& IR3_INSTR_B
);
2423 sam
->prefetch
.tex
= info
.tex_idx
;
2424 sam
->prefetch
.samp
= info
.samp_idx
;
2425 sam
->prefetch
.tex_base
= info
.tex_base
;
2426 sam
->prefetch
.samp_base
= info
.samp_base
;
2428 info
.flags
|= flags
;
2429 sam
= emit_sam(ctx
, opc
, info
, type
, MASK(ncomp
), col0
, col1
);
2432 if ((ctx
->astc_srgb
& (1 << tex
->texture_index
)) && !nir_tex_instr_is_query(tex
)) {
2433 assert(opc
!= OPC_META_TEX_PREFETCH
);
2435 /* only need first 3 components: */
2436 sam
->regs
[0]->wrmask
= 0x7;
2437 ir3_split_dest(b
, dst
, sam
, 0, 3);
2439 /* we need to sample the alpha separately with a non-ASTC
2442 sam
= ir3_SAM(b
, opc
, type
, 0b1000, flags
| info
.flags
,
2443 info
.samp_tex
, col0
, col1
);
2445 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
2447 /* fixup .w component: */
2448 ir3_split_dest(b
, &dst
[3], sam
, 3, 1);
2450 /* normal (non-workaround) case: */
2451 ir3_split_dest(b
, dst
, sam
, 0, ncomp
);
2454 /* GETLOD returns results in 4.8 fixed point */
2455 if (opc
== OPC_GETLOD
) {
2456 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
2458 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
2459 for (i
= 0; i
< 2; i
++) {
2460 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_S32
, TYPE_F32
), 0,
2465 ir3_put_dst(ctx
, &tex
->dest
);
2469 emit_tex_info(struct ir3_context
*ctx
, nir_tex_instr
*tex
, unsigned idx
)
2471 struct ir3_block
*b
= ctx
->block
;
2472 struct ir3_instruction
**dst
, *sam
;
2473 type_t dst_type
= get_tex_dest_type(tex
);
2474 struct tex_src_info info
= get_tex_samp_tex_src(ctx
, tex
);
2476 dst
= ir3_get_dst(ctx
, &tex
->dest
, 1);
2478 sam
= emit_sam(ctx
, OPC_GETINFO
, info
, dst_type
, 1 << idx
, NULL
, NULL
);
2480 /* even though there is only one component, since it ends
2481 * up in .y/.z/.w rather than .x, we need a split_dest()
2483 ir3_split_dest(b
, dst
, sam
, idx
, 1);
2485 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2486 * the value in TEX_CONST_0 is zero-based.
2488 if (ctx
->compiler
->levels_add_one
)
2489 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
2491 ir3_put_dst(ctx
, &tex
->dest
);
2495 emit_tex_txs(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2497 struct ir3_block
*b
= ctx
->block
;
2498 struct ir3_instruction
**dst
, *sam
;
2499 struct ir3_instruction
*lod
;
2500 unsigned flags
, coords
;
2501 type_t dst_type
= get_tex_dest_type(tex
);
2502 struct tex_src_info info
= get_tex_samp_tex_src(ctx
, tex
);
2504 tex_info(tex
, &flags
, &coords
);
2505 info
.flags
|= flags
;
2507 /* Actually we want the number of dimensions, not coordinates. This
2508 * distinction only matters for cubes.
2510 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2513 dst
= ir3_get_dst(ctx
, &tex
->dest
, 4);
2515 int lod_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_lod
);
2516 compile_assert(ctx
, lod_idx
>= 0);
2518 lod
= ir3_get_src(ctx
, &tex
->src
[lod_idx
].src
)[0];
2520 sam
= emit_sam(ctx
, OPC_GETSIZE
, info
, dst_type
, 0b1111, lod
, NULL
);
2521 ir3_split_dest(b
, dst
, sam
, 0, 4);
2523 /* Array size actually ends up in .w rather than .z. This doesn't
2524 * matter for miplevel 0, but for higher mips the value in z is
2525 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2526 * returned, which means that we have to add 1 to it for arrays.
2528 if (tex
->is_array
) {
2529 if (ctx
->compiler
->levels_add_one
) {
2530 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
2532 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
2536 ir3_put_dst(ctx
, &tex
->dest
);
2540 emit_jump(struct ir3_context
*ctx
, nir_jump_instr
*jump
)
2542 switch (jump
->type
) {
2543 case nir_jump_break
:
2544 case nir_jump_continue
:
2545 case nir_jump_return
:
2546 /* I *think* we can simply just ignore this, and use the
2547 * successor block link to figure out where we need to
2548 * jump to for break/continue
2552 ir3_context_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
2558 emit_instr(struct ir3_context
*ctx
, nir_instr
*instr
)
2560 switch (instr
->type
) {
2561 case nir_instr_type_alu
:
2562 emit_alu(ctx
, nir_instr_as_alu(instr
));
2564 case nir_instr_type_deref
:
2565 /* ignored, handled as part of the intrinsic they are src to */
2567 case nir_instr_type_intrinsic
:
2568 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2570 case nir_instr_type_load_const
:
2571 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2573 case nir_instr_type_ssa_undef
:
2574 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
2576 case nir_instr_type_tex
: {
2577 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2578 /* couple tex instructions get special-cased:
2582 emit_tex_txs(ctx
, tex
);
2584 case nir_texop_query_levels
:
2585 emit_tex_info(ctx
, tex
, 2);
2587 case nir_texop_texture_samples
:
2588 emit_tex_info(ctx
, tex
, 3);
2596 case nir_instr_type_jump
:
2597 emit_jump(ctx
, nir_instr_as_jump(instr
));
2599 case nir_instr_type_phi
:
2600 /* we have converted phi webs to regs in NIR by now */
2601 ir3_context_error(ctx
, "Unexpected NIR instruction type: %d\n", instr
->type
);
2603 case nir_instr_type_call
:
2604 case nir_instr_type_parallel_copy
:
2605 ir3_context_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
2610 static struct ir3_block
*
2611 get_block(struct ir3_context
*ctx
, const nir_block
*nblock
)
2613 struct ir3_block
*block
;
2614 struct hash_entry
*hentry
;
2616 hentry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
2618 return hentry
->data
;
2620 block
= ir3_block_create(ctx
->ir
);
2621 block
->nblock
= nblock
;
2622 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
2624 set_foreach(nblock
->predecessors
, sentry
) {
2625 _mesa_set_add(block
->predecessors
, get_block(ctx
, sentry
->key
));
2632 emit_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2634 struct ir3_block
*block
= get_block(ctx
, nblock
);
2636 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
2637 if (nblock
->successors
[i
]) {
2638 block
->successors
[i
] =
2639 get_block(ctx
, nblock
->successors
[i
]);
2644 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
2646 /* re-emit addr register in each block if needed: */
2647 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr0_ht
); i
++) {
2648 _mesa_hash_table_destroy(ctx
->addr0_ht
[i
], NULL
);
2649 ctx
->addr0_ht
[i
] = NULL
;
2652 _mesa_hash_table_u64_destroy(ctx
->addr1_ht
, NULL
);
2653 ctx
->addr1_ht
= NULL
;
2655 nir_foreach_instr (instr
, nblock
) {
2656 ctx
->cur_instr
= instr
;
2657 emit_instr(ctx
, instr
);
2658 ctx
->cur_instr
= NULL
;
2663 _mesa_hash_table_clear(ctx
->sel_cond_conversions
, NULL
);
2666 static void emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
);
2669 emit_if(struct ir3_context
*ctx
, nir_if
*nif
)
2671 struct ir3_instruction
*condition
= ir3_get_src(ctx
, &nif
->condition
)[0];
2673 ctx
->block
->condition
= ir3_get_predicate(ctx
, condition
);
2675 emit_cf_list(ctx
, &nif
->then_list
);
2676 emit_cf_list(ctx
, &nif
->else_list
);
2680 emit_loop(struct ir3_context
*ctx
, nir_loop
*nloop
)
2682 emit_cf_list(ctx
, &nloop
->body
);
2687 stack_push(struct ir3_context
*ctx
)
2690 ctx
->max_stack
= MAX2(ctx
->max_stack
, ctx
->stack
);
2694 stack_pop(struct ir3_context
*ctx
)
2696 compile_assert(ctx
, ctx
->stack
> 0);
2701 emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
)
2703 foreach_list_typed (nir_cf_node
, node
, node
, list
) {
2704 switch (node
->type
) {
2705 case nir_cf_node_block
:
2706 emit_block(ctx
, nir_cf_node_as_block(node
));
2708 case nir_cf_node_if
:
2710 emit_if(ctx
, nir_cf_node_as_if(node
));
2713 case nir_cf_node_loop
:
2715 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2718 case nir_cf_node_function
:
2719 ir3_context_error(ctx
, "TODO\n");
2725 /* emit stream-out code. At this point, the current block is the original
2726 * (nir) end block, and nir ensures that all flow control paths terminate
2727 * into the end block. We re-purpose the original end block to generate
2728 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2729 * block holding stream-out write instructions, followed by the new end
2733 * p0.x = (vtxcnt < maxvtxcnt)
2734 * // succs: blockStreamOut, blockNewEnd
2737 * // preds: blockOrigEnd
2738 * ... stream-out instructions ...
2739 * // succs: blockNewEnd
2742 * // preds: blockOrigEnd, blockStreamOut
2746 emit_stream_out(struct ir3_context
*ctx
)
2748 struct ir3
*ir
= ctx
->ir
;
2749 struct ir3_stream_output_info
*strmout
=
2750 &ctx
->so
->shader
->stream_output
;
2751 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2752 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2753 struct ir3_instruction
*bases
[IR3_MAX_SO_BUFFERS
];
2755 /* create vtxcnt input in input block at top of shader,
2756 * so that it is seen as live over the entire duration
2759 vtxcnt
= create_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, 0x1);
2760 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2762 /* at this point, we are at the original 'end' block,
2763 * re-purpose this block to stream-out condition, then
2764 * append stream-out block and new-end block
2766 orig_end_block
= ctx
->block
;
2768 // maybe w/ store_global intrinsic, we could do this
2769 // stuff in nir->nir pass
2771 stream_out_block
= ir3_block_create(ir
);
2772 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2774 new_end_block
= ir3_block_create(ir
);
2775 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2777 orig_end_block
->successors
[0] = stream_out_block
;
2778 orig_end_block
->successors
[1] = new_end_block
;
2780 stream_out_block
->successors
[0] = new_end_block
;
2781 _mesa_set_add(stream_out_block
->predecessors
, orig_end_block
);
2783 _mesa_set_add(new_end_block
->predecessors
, orig_end_block
);
2784 _mesa_set_add(new_end_block
->predecessors
, stream_out_block
);
2786 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2787 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2788 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2789 cond
->regs
[0]->flags
&= ~IR3_REG_SSA
;
2790 cond
->cat2
.condition
= IR3_COND_LT
;
2792 /* condition goes on previous block to the conditional,
2793 * since it is used to pick which of the two successor
2796 orig_end_block
->condition
= cond
;
2798 /* switch to stream_out_block to generate the stream-out
2801 ctx
->block
= stream_out_block
;
2803 /* Calculate base addresses based on vtxcnt. Instructions
2804 * generated for bases not used in following loop will be
2805 * stripped out in the backend.
2807 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
2808 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
2809 unsigned stride
= strmout
->stride
[i
];
2810 struct ir3_instruction
*base
, *off
;
2812 base
= create_uniform(ctx
->block
, regid(const_state
->offsets
.tfbo
, i
));
2814 /* 24-bit should be enough: */
2815 off
= ir3_MUL_U24(ctx
->block
, vtxcnt
, 0,
2816 create_immed(ctx
->block
, stride
* 4), 0);
2818 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2821 /* Generate the per-output store instructions: */
2822 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2823 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2824 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2825 struct ir3_instruction
*base
, *out
, *stg
;
2827 base
= bases
[strmout
->output
[i
].output_buffer
];
2828 out
= ctx
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2830 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2831 create_immed(ctx
->block
, 1), 0);
2832 stg
->cat6
.type
= TYPE_U32
;
2833 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2835 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
2839 /* and finally switch to the new_end_block: */
2840 ctx
->block
= new_end_block
;
2844 emit_function(struct ir3_context
*ctx
, nir_function_impl
*impl
)
2846 nir_metadata_require(impl
, nir_metadata_block_index
);
2848 compile_assert(ctx
, ctx
->stack
== 0);
2850 emit_cf_list(ctx
, &impl
->body
);
2851 emit_block(ctx
, impl
->end_block
);
2853 compile_assert(ctx
, ctx
->stack
== 0);
2855 /* at this point, we should have a single empty block,
2856 * into which we emit the 'end' instruction.
2858 compile_assert(ctx
, list_is_empty(&ctx
->block
->instr_list
));
2860 /* If stream-out (aka transform-feedback) enabled, emit the
2861 * stream-out instructions, followed by a new empty block (into
2862 * which the 'end' instruction lands).
2864 * NOTE: it is done in this order, rather than inserting before
2865 * we emit end_block, because NIR guarantees that all blocks
2866 * flow into end_block, and that end_block has no successors.
2867 * So by re-purposing end_block as the first block of stream-
2868 * out, we guarantee that all exit paths flow into the stream-
2871 if ((ctx
->compiler
->gpu_id
< 500) &&
2872 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2873 !ctx
->so
->binning_pass
) {
2874 debug_assert(ctx
->so
->type
== MESA_SHADER_VERTEX
);
2875 emit_stream_out(ctx
);
2878 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2879 * NOP and has an epilogue that writes the VS outputs to local storage, to
2880 * be read by the HS. Then it resets execution mask (chmask) and chains
2881 * to the next shader (chsh).
2883 if ((ctx
->so
->type
== MESA_SHADER_VERTEX
&&
2884 (ctx
->so
->key
.has_gs
|| ctx
->so
->key
.tessellation
)) ||
2885 (ctx
->so
->type
== MESA_SHADER_TESS_EVAL
&& ctx
->so
->key
.has_gs
)) {
2886 struct ir3_instruction
*chmask
=
2887 ir3_CHMASK(ctx
->block
);
2888 chmask
->barrier_class
= IR3_BARRIER_EVERYTHING
;
2889 chmask
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
2891 struct ir3_instruction
*chsh
=
2892 ir3_CHSH(ctx
->block
);
2893 chsh
->barrier_class
= IR3_BARRIER_EVERYTHING
;
2894 chsh
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
2896 ir3_END(ctx
->block
);
2901 setup_input(struct ir3_context
*ctx
, nir_variable
*in
)
2903 struct ir3_shader_variant
*so
= ctx
->so
;
2904 unsigned ncomp
= glsl_get_components(in
->type
);
2905 unsigned n
= in
->data
.driver_location
;
2906 unsigned frac
= in
->data
.location_frac
;
2907 unsigned slot
= in
->data
.location
;
2909 /* Inputs are loaded using ldlw or ldg for these stages. */
2910 if (ctx
->so
->type
== MESA_SHADER_TESS_CTRL
||
2911 ctx
->so
->type
== MESA_SHADER_TESS_EVAL
||
2912 ctx
->so
->type
== MESA_SHADER_GEOMETRY
)
2915 /* skip unread inputs, we could end up with (for example), unsplit
2916 * matrix/etc inputs in the case they are not read, so just silently
2922 so
->inputs
[n
].slot
= slot
;
2923 so
->inputs
[n
].compmask
|= (1 << (ncomp
+ frac
)) - 1;
2924 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2925 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2927 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
2929 /* if any varyings have 'sample' qualifer, that triggers us
2930 * to run in per-sample mode:
2932 so
->per_samp
|= in
->data
.sample
;
2934 for (int i
= 0; i
< ncomp
; i
++) {
2935 struct ir3_instruction
*instr
= NULL
;
2936 unsigned idx
= (n
* 4) + i
+ frac
;
2938 if (slot
== VARYING_SLOT_POS
) {
2939 ir3_context_error(ctx
, "fragcoord should be a sysval!\n");
2941 /* detect the special case for front/back colors where
2942 * we need to do flat vs smooth shading depending on
2945 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
2947 case VARYING_SLOT_COL0
:
2948 case VARYING_SLOT_COL1
:
2949 case VARYING_SLOT_BFC0
:
2950 case VARYING_SLOT_BFC1
:
2951 so
->inputs
[n
].rasterflat
= true;
2958 if (ctx
->compiler
->flat_bypass
) {
2959 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
2960 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
2961 so
->inputs
[n
].use_ldlv
= true;
2964 so
->inputs
[n
].bary
= true;
2966 instr
= create_frag_input(ctx
, so
->inputs
[n
].use_ldlv
, idx
);
2969 compile_assert(ctx
, idx
< ctx
->ninputs
);
2971 ctx
->inputs
[idx
] = instr
;
2973 } else if (ctx
->so
->type
== MESA_SHADER_VERTEX
) {
2974 struct ir3_instruction
*input
= NULL
;
2975 struct ir3_instruction
*components
[4];
2976 unsigned mask
= (1 << (ncomp
+ frac
)) - 1;
2978 foreach_input (in
, ctx
->ir
) {
2979 if (in
->input
.inidx
== n
) {
2986 input
= create_input(ctx
, mask
);
2987 input
->input
.inidx
= n
;
2989 /* For aliased inputs, just append to the wrmask.. ie. if we
2990 * first see a vec2 index at slot N, and then later a vec4,
2991 * the wrmask of the resulting overlapped vec2 and vec4 is 0xf
2993 * If the new input that aliases a previously processed input
2994 * sets no new bits, then just bail as there is nothing to see
2997 * Note that we don't expect to get an input w/ frac!=0, if we
2998 * did we'd have to adjust ncomp and frac to cover the entire
3001 if (!(mask
& ~input
->regs
[0]->wrmask
))
3003 input
->regs
[0]->wrmask
|= mask
;
3006 ir3_split_dest(ctx
->block
, components
, input
, frac
, ncomp
);
3008 for (int i
= 0; i
< ncomp
; i
++) {
3009 unsigned idx
= (n
* 4) + i
+ frac
;
3010 compile_assert(ctx
, idx
< ctx
->ninputs
);
3012 /* With aliased inputs, since we add to the wrmask above, we
3013 * can end up with stale meta:split instructions in the inputs
3014 * table. This is basically harmless, since eventually they
3015 * will get swept away by DCE, but the mismatch wrmask (since
3016 * they would be using the previous wrmask before we OR'd in
3017 * more bits) angers ir3_validate. So just preemptively clean
3020 * dEQP-GLES2.functional.attribute_location.bind_aliasing.cond_vec2
3022 * Note however that split_dest() will return the src if it is
3023 * scalar, so the previous ctx->inputs[idx] could be the input
3024 * itself (which we don't want to remove)
3026 if (ctx
->inputs
[idx
] && (ctx
->inputs
[idx
] != input
)) {
3027 list_del(&ctx
->inputs
[idx
]->node
);
3030 ctx
->inputs
[idx
] = components
[i
];
3033 ir3_context_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3036 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== MESA_SHADER_VERTEX
)) {
3037 so
->total_in
+= ncomp
;
3041 /* Initially we assign non-packed inloc's for varyings, as we don't really
3042 * know up-front which components will be unused. After all the compilation
3043 * stages we scan the shader to see which components are actually used, and
3044 * re-pack the inlocs to eliminate unneeded varyings.
3047 pack_inlocs(struct ir3_context
*ctx
)
3049 struct ir3_shader_variant
*so
= ctx
->so
;
3050 uint8_t used_components
[so
->inputs_count
];
3052 memset(used_components
, 0, sizeof(used_components
));
3055 * First Step: scan shader to find which bary.f/ldlv remain:
3058 foreach_block (block
, &ctx
->ir
->block_list
) {
3059 foreach_instr (instr
, &block
->instr_list
) {
3060 if (is_input(instr
)) {
3061 unsigned inloc
= instr
->regs
[1]->iim_val
;
3062 unsigned i
= inloc
/ 4;
3063 unsigned j
= inloc
% 4;
3065 compile_assert(ctx
, instr
->regs
[1]->flags
& IR3_REG_IMMED
);
3066 compile_assert(ctx
, i
< so
->inputs_count
);
3068 used_components
[i
] |= 1 << j
;
3069 } else if (instr
->opc
== OPC_META_TEX_PREFETCH
) {
3070 for (int n
= 0; n
< 2; n
++) {
3071 unsigned inloc
= instr
->prefetch
.input_offset
+ n
;
3072 unsigned i
= inloc
/ 4;
3073 unsigned j
= inloc
% 4;
3075 compile_assert(ctx
, i
< so
->inputs_count
);
3077 used_components
[i
] |= 1 << j
;
3084 * Second Step: reassign varying inloc/slots:
3087 unsigned actual_in
= 0;
3090 for (unsigned i
= 0; i
< so
->inputs_count
; i
++) {
3091 unsigned compmask
= 0, maxcomp
= 0;
3093 so
->inputs
[i
].inloc
= inloc
;
3094 so
->inputs
[i
].bary
= false;
3096 for (unsigned j
= 0; j
< 4; j
++) {
3097 if (!(used_components
[i
] & (1 << j
)))
3100 compmask
|= (1 << j
);
3104 /* at this point, since used_components[i] mask is only
3105 * considering varyings (ie. not sysvals) we know this
3108 so
->inputs
[i
].bary
= true;
3111 if (so
->inputs
[i
].bary
) {
3113 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
3119 * Third Step: reassign packed inloc's:
3122 foreach_block (block
, &ctx
->ir
->block_list
) {
3123 foreach_instr (instr
, &block
->instr_list
) {
3124 if (is_input(instr
)) {
3125 unsigned inloc
= instr
->regs
[1]->iim_val
;
3126 unsigned i
= inloc
/ 4;
3127 unsigned j
= inloc
% 4;
3129 instr
->regs
[1]->iim_val
= so
->inputs
[i
].inloc
+ j
;
3130 } else if (instr
->opc
== OPC_META_TEX_PREFETCH
) {
3131 unsigned i
= instr
->prefetch
.input_offset
/ 4;
3132 unsigned j
= instr
->prefetch
.input_offset
% 4;
3133 instr
->prefetch
.input_offset
= so
->inputs
[i
].inloc
+ j
;
3140 setup_output(struct ir3_context
*ctx
, nir_variable
*out
)
3142 struct ir3_shader_variant
*so
= ctx
->so
;
3143 unsigned slots
= glsl_count_vec4_slots(out
->type
, false, false);
3144 unsigned ncomp
= glsl_get_components(glsl_without_array(out
->type
));
3145 unsigned n
= out
->data
.driver_location
;
3146 unsigned frac
= out
->data
.location_frac
;
3147 unsigned slot
= out
->data
.location
;
3149 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
3151 case FRAG_RESULT_DEPTH
:
3152 so
->writes_pos
= true;
3154 case FRAG_RESULT_COLOR
:
3157 case FRAG_RESULT_SAMPLE_MASK
:
3158 so
->writes_smask
= true;
3161 slot
+= out
->data
.index
; /* For dual-src blend */
3162 if (slot
>= FRAG_RESULT_DATA0
)
3164 ir3_context_error(ctx
, "unknown FS output name: %s\n",
3165 gl_frag_result_name(slot
));
3167 } else if (ctx
->so
->type
== MESA_SHADER_VERTEX
||
3168 ctx
->so
->type
== MESA_SHADER_TESS_EVAL
||
3169 ctx
->so
->type
== MESA_SHADER_GEOMETRY
) {
3171 case VARYING_SLOT_POS
:
3172 so
->writes_pos
= true;
3174 case VARYING_SLOT_PSIZ
:
3175 so
->writes_psize
= true;
3177 case VARYING_SLOT_PRIMITIVE_ID
:
3178 case VARYING_SLOT_LAYER
:
3179 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3
:
3180 debug_assert(ctx
->so
->type
== MESA_SHADER_GEOMETRY
);
3182 case VARYING_SLOT_COL0
:
3183 case VARYING_SLOT_COL1
:
3184 case VARYING_SLOT_BFC0
:
3185 case VARYING_SLOT_BFC1
:
3186 case VARYING_SLOT_FOGC
:
3187 case VARYING_SLOT_CLIP_DIST0
:
3188 case VARYING_SLOT_CLIP_DIST1
:
3189 case VARYING_SLOT_CLIP_VERTEX
:
3192 if (slot
>= VARYING_SLOT_VAR0
)
3194 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
3196 ir3_context_error(ctx
, "unknown %s shader output name: %s\n",
3197 _mesa_shader_stage_to_string(ctx
->so
->type
),
3198 gl_varying_slot_name(slot
));
3200 } else if (ctx
->so
->type
== MESA_SHADER_TESS_CTRL
) {
3201 /* output lowered to buffer writes. */
3204 ir3_context_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3208 so
->outputs_count
= out
->data
.driver_location
+ slots
;
3209 compile_assert(ctx
, so
->outputs_count
< ARRAY_SIZE(so
->outputs
));
3211 for (int i
= 0; i
< slots
; i
++) {
3212 int slot_base
= n
+ i
;
3213 so
->outputs
[slot_base
].slot
= slot
+ i
;
3215 for (int i
= 0; i
< ncomp
; i
++) {
3216 unsigned idx
= (slot_base
* 4) + i
+ frac
;
3217 compile_assert(ctx
, idx
< ctx
->noutputs
);
3218 ctx
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
3221 /* if varying packing doesn't happen, we could end up in a situation
3222 * with "holes" in the output, and since the per-generation code that
3223 * sets up varying linkage registers doesn't expect to have more than
3224 * one varying per vec4 slot, pad the holes.
3226 * Note that this should probably generate a performance warning of
3229 for (int i
= 0; i
< frac
; i
++) {
3230 unsigned idx
= (slot_base
* 4) + i
;
3231 if (!ctx
->outputs
[idx
]) {
3232 ctx
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
3239 emit_instructions(struct ir3_context
*ctx
)
3241 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
3243 ctx
->ninputs
= ctx
->s
->num_inputs
* 4;
3244 ctx
->noutputs
= ctx
->s
->num_outputs
* 4;
3245 ctx
->inputs
= rzalloc_array(ctx
, struct ir3_instruction
*, ctx
->ninputs
);
3246 ctx
->outputs
= rzalloc_array(ctx
, struct ir3_instruction
*, ctx
->noutputs
);
3248 ctx
->ir
= ir3_create(ctx
->compiler
, ctx
->so
->type
);
3250 /* Create inputs in first block: */
3251 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
3252 ctx
->in_block
= ctx
->block
;
3254 /* for fragment shader, the vcoord input register is used as the
3255 * base for bary.f varying fetch instrs:
3257 * TODO defer creating ctx->ij_pixel and corresponding sysvals
3258 * until emit_intrinsic when we know they are actually needed.
3259 * For now, we defer creating ctx->ij_centroid, etc, since we
3260 * only need ij_pixel for "old style" varying inputs (ie.
3263 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
3264 ctx
->ij_pixel
= create_input(ctx
, 0x3);
3268 nir_foreach_variable (var
, &ctx
->s
->inputs
) {
3269 setup_input(ctx
, var
);
3272 /* Defer add_sysval_input() stuff until after setup_inputs(),
3273 * because sysvals need to be appended after varyings:
3275 if (ctx
->ij_pixel
) {
3276 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
,
3277 0x3, ctx
->ij_pixel
);
3281 /* Tesselation shaders always need primitive ID for indexing the
3282 * BO. Geometry shaders don't always need it but when they do it has be
3283 * delivered and unclobbered in the VS. To make things easy, we always
3284 * make room for it in VS/DS.
3286 bool has_tess
= ctx
->so
->key
.tessellation
!= IR3_TESS_NONE
;
3287 bool has_gs
= ctx
->so
->key
.has_gs
;
3288 switch (ctx
->so
->type
) {
3289 case MESA_SHADER_VERTEX
:
3291 ctx
->tcs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_TCS_HEADER_IR3
, 0x1);
3292 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3293 } else if (has_gs
) {
3294 ctx
->gs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_GS_HEADER_IR3
, 0x1);
3295 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3298 case MESA_SHADER_TESS_CTRL
:
3299 ctx
->tcs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_TCS_HEADER_IR3
, 0x1);
3300 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3302 case MESA_SHADER_TESS_EVAL
:
3304 ctx
->gs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_GS_HEADER_IR3
, 0x1);
3305 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3307 case MESA_SHADER_GEOMETRY
:
3308 ctx
->gs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_GS_HEADER_IR3
, 0x1);
3309 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3315 /* Setup outputs: */
3316 nir_foreach_variable (var
, &ctx
->s
->outputs
) {
3317 setup_output(ctx
, var
);
3320 /* Find # of samplers. Just assume that we'll be reading from images.. if
3321 * it is write-only we don't have to count it, but after lowering derefs
3322 * is too late to compact indices for that.
3324 ctx
->so
->num_samp
= util_last_bit(ctx
->s
->info
.textures_used
) + ctx
->s
->info
.num_images
;
3326 /* NOTE: need to do something more clever when we support >1 fxn */
3327 nir_foreach_register (reg
, &fxn
->registers
) {
3328 ir3_declare_array(ctx
, reg
);
3330 /* And emit the body: */
3332 emit_function(ctx
, fxn
);
3335 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3336 * need to assign the tex state indexes for these after we know the
3340 fixup_astc_srgb(struct ir3_context
*ctx
)
3342 struct ir3_shader_variant
*so
= ctx
->so
;
3343 /* indexed by original tex idx, value is newly assigned alpha sampler
3344 * state tex idx. Zero is invalid since there is at least one sampler
3347 unsigned alt_tex_state
[16] = {0};
3348 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
3351 so
->astc_srgb
.base
= tex_idx
;
3353 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
3354 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
3356 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
3358 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
3359 /* assign new alternate/alpha tex state slot: */
3360 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
3361 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
3362 so
->astc_srgb
.count
++;
3365 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
3370 fixup_binning_pass(struct ir3_context
*ctx
)
3372 struct ir3_shader_variant
*so
= ctx
->so
;
3373 struct ir3
*ir
= ctx
->ir
;
3376 /* first pass, remove unused outputs from the IR level outputs: */
3377 for (i
= 0, j
= 0; i
< ir
->outputs_count
; i
++) {
3378 struct ir3_instruction
*out
= ir
->outputs
[i
];
3379 assert(out
->opc
== OPC_META_COLLECT
);
3380 unsigned outidx
= out
->collect
.outidx
;
3381 unsigned slot
= so
->outputs
[outidx
].slot
;
3383 /* throw away everything but first position/psize */
3384 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3385 ir
->outputs
[j
] = ir
->outputs
[i
];
3389 ir
->outputs_count
= j
;
3391 /* second pass, cleanup the unused slots in ir3_shader_variant::outputs
3394 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
3395 unsigned slot
= so
->outputs
[i
].slot
;
3397 /* throw away everything but first position/psize */
3398 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3399 so
->outputs
[j
] = so
->outputs
[i
];
3401 /* fixup outidx to point to new output table entry: */
3402 foreach_output (out
, ir
) {
3403 if (out
->collect
.outidx
== i
) {
3404 out
->collect
.outidx
= j
;
3412 so
->outputs_count
= j
;
3416 collect_tex_prefetches(struct ir3_context
*ctx
, struct ir3
*ir
)
3420 /* Collect sampling instructions eligible for pre-dispatch. */
3421 foreach_block (block
, &ir
->block_list
) {
3422 foreach_instr_safe (instr
, &block
->instr_list
) {
3423 if (instr
->opc
== OPC_META_TEX_PREFETCH
) {
3424 assert(idx
< ARRAY_SIZE(ctx
->so
->sampler_prefetch
));
3425 struct ir3_sampler_prefetch
*fetch
=
3426 &ctx
->so
->sampler_prefetch
[idx
];
3429 if (instr
->flags
& IR3_INSTR_B
) {
3430 fetch
->cmd
= IR3_SAMPLER_BINDLESS_PREFETCH_CMD
;
3431 /* In bindless mode, the index is actually the base */
3432 fetch
->tex_id
= instr
->prefetch
.tex_base
;
3433 fetch
->samp_id
= instr
->prefetch
.samp_base
;
3434 fetch
->tex_bindless_id
= instr
->prefetch
.tex
;
3435 fetch
->samp_bindless_id
= instr
->prefetch
.samp
;
3437 fetch
->cmd
= IR3_SAMPLER_PREFETCH_CMD
;
3438 fetch
->tex_id
= instr
->prefetch
.tex
;
3439 fetch
->samp_id
= instr
->prefetch
.samp
;
3441 fetch
->wrmask
= instr
->regs
[0]->wrmask
;
3442 fetch
->dst
= instr
->regs
[0]->num
;
3443 fetch
->src
= instr
->prefetch
.input_offset
;
3445 /* These are the limits on a5xx/a6xx, we might need to
3446 * revisit if SP_FS_PREFETCH[n] changes on later gens:
3448 assert(fetch
->dst
<= 0x3f);
3449 assert(fetch
->tex_id
<= 0x1f);
3450 assert(fetch
->samp_id
< 0xf);
3453 MAX2(ctx
->so
->total_in
, instr
->prefetch
.input_offset
+ 2);
3455 fetch
->half_precision
= !!(instr
->regs
[0]->flags
& IR3_REG_HALF
);
3457 /* Remove the prefetch placeholder instruction: */
3458 list_delinit(&instr
->node
);
3465 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
3466 struct ir3_shader_variant
*so
)
3468 struct ir3_context
*ctx
;
3470 int ret
= 0, max_bary
;
3475 ctx
= ir3_context_init(compiler
, so
);
3477 DBG("INIT failed!");
3482 emit_instructions(ctx
);
3485 DBG("EMIT failed!");
3490 ir
= so
->ir
= ctx
->ir
;
3492 assert((ctx
->noutputs
% 4) == 0);
3494 /* Setup IR level outputs, which are "collects" that gather
3495 * the scalar components of outputs.
3497 for (unsigned i
= 0; i
< ctx
->noutputs
; i
+= 4) {
3499 /* figure out the # of components written:
3501 * TODO do we need to handle holes, ie. if .x and .z
3502 * components written, but .y component not written?
3504 for (unsigned j
= 0; j
< 4; j
++) {
3505 if (!ctx
->outputs
[i
+ j
])
3510 /* Note that in some stages, like TCS, store_output is
3511 * lowered to memory writes, so no components of the
3512 * are "written" from the PoV of traditional store-
3513 * output instructions:
3518 struct ir3_instruction
*out
=
3519 ir3_create_collect(ctx
, &ctx
->outputs
[i
], ncomp
);
3522 assert(outidx
< so
->outputs_count
);
3524 /* stash index into so->outputs[] so we can map the
3525 * output back to slot/etc later:
3527 out
->collect
.outidx
= outidx
;
3529 array_insert(ir
, ir
->outputs
, out
);
3532 /* Set up the gs header as an output for the vertex shader so it won't
3533 * clobber it for the tess ctrl shader.
3535 * TODO this could probably be done more cleanly in a nir pass.
3537 if (ctx
->so
->type
== MESA_SHADER_VERTEX
||
3538 (ctx
->so
->key
.has_gs
&& ctx
->so
->type
== MESA_SHADER_TESS_EVAL
)) {
3539 if (ctx
->primitive_id
) {
3540 unsigned n
= so
->outputs_count
++;
3541 so
->outputs
[n
].slot
= VARYING_SLOT_PRIMITIVE_ID
;
3543 struct ir3_instruction
*out
=
3544 ir3_create_collect(ctx
, &ctx
->primitive_id
, 1);
3545 out
->collect
.outidx
= n
;
3546 array_insert(ir
, ir
->outputs
, out
);
3549 if (ctx
->gs_header
) {
3550 unsigned n
= so
->outputs_count
++;
3551 so
->outputs
[n
].slot
= VARYING_SLOT_GS_HEADER_IR3
;
3552 struct ir3_instruction
*out
=
3553 ir3_create_collect(ctx
, &ctx
->gs_header
, 1);
3554 out
->collect
.outidx
= n
;
3555 array_insert(ir
, ir
->outputs
, out
);
3558 if (ctx
->tcs_header
) {
3559 unsigned n
= so
->outputs_count
++;
3560 so
->outputs
[n
].slot
= VARYING_SLOT_TCS_HEADER_IR3
;
3561 struct ir3_instruction
*out
=
3562 ir3_create_collect(ctx
, &ctx
->tcs_header
, 1);
3563 out
->collect
.outidx
= n
;
3564 array_insert(ir
, ir
->outputs
, out
);
3568 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3569 * need to make sure not to remove any inputs that are used by
3570 * the nonbinning VS.
3572 if (ctx
->compiler
->gpu_id
>= 600 && so
->binning_pass
&&
3573 so
->type
== MESA_SHADER_VERTEX
) {
3574 for (int i
= 0; i
< ctx
->ninputs
; i
++) {
3575 struct ir3_instruction
*in
= ctx
->inputs
[i
];
3583 debug_assert(n
< so
->nonbinning
->inputs_count
);
3585 if (so
->nonbinning
->inputs
[n
].sysval
)
3588 /* be sure to keep inputs, even if only used in VS */
3589 if (so
->nonbinning
->inputs
[n
].compmask
& (1 << c
))
3590 array_insert(in
->block
, in
->block
->keeps
, in
);
3594 /* at this point, for binning pass, throw away unneeded outputs: */
3595 if (so
->binning_pass
&& (ctx
->compiler
->gpu_id
< 600))
3596 fixup_binning_pass(ctx
);
3598 ir3_debug_print(ir
, "AFTER: nir->ir3");
3604 progress
|= IR3_PASS(ir
, ir3_cf
);
3605 progress
|= IR3_PASS(ir
, ir3_cp
, so
);
3606 progress
|= IR3_PASS(ir
, ir3_dce
, so
);
3609 /* at this point, for binning pass, throw away unneeded outputs:
3610 * Note that for a6xx and later, we do this after ir3_cp to ensure
3611 * that the uniform/constant layout for BS and VS matches, so that
3612 * we can re-use same VS_CONST state group.
3614 if (so
->binning_pass
&& (ctx
->compiler
->gpu_id
>= 600)) {
3615 fixup_binning_pass(ctx
);
3616 /* cleanup the result of removing unneeded outputs: */
3617 while (IR3_PASS(ir
, ir3_dce
, so
)) {}
3620 IR3_PASS(ir
, ir3_sched_add_deps
);
3622 /* Group left/right neighbors, inserting mov's where needed to
3625 IR3_PASS(ir
, ir3_group
);
3627 /* At this point, all the dead code should be long gone: */
3628 assert(!IR3_PASS(ir
, ir3_dce
, so
));
3630 ret
= ir3_sched(ir
);
3632 DBG("SCHED failed!");
3636 ir3_debug_print(ir
, "AFTER: ir3_sched");
3638 if (IR3_PASS(ir
, ir3_cp_postsched
)) {
3639 /* cleanup the result of removing unneeded mov's: */
3640 while (IR3_PASS(ir
, ir3_dce
, so
)) {}
3643 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3644 * with draw pass VS, so binning and draw pass can both use the
3647 * Note that VS inputs are expected to be full precision.
3649 bool pre_assign_inputs
= (ir
->compiler
->gpu_id
>= 600) &&
3650 (ir
->type
== MESA_SHADER_VERTEX
) &&
3653 if (pre_assign_inputs
) {
3654 for (unsigned i
= 0; i
< ctx
->ninputs
; i
++) {
3655 struct ir3_instruction
*instr
= ctx
->inputs
[i
];
3662 unsigned regid
= so
->nonbinning
->inputs
[n
].regid
+ c
;
3664 instr
->regs
[0]->num
= regid
;
3667 ret
= ir3_ra(so
, ctx
->inputs
, ctx
->ninputs
);
3668 } else if (ctx
->tcs_header
) {
3669 /* We need to have these values in the same registers between VS and TCS
3670 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3673 ctx
->tcs_header
->regs
[0]->num
= regid(0, 0);
3674 ctx
->primitive_id
->regs
[0]->num
= regid(0, 1);
3675 struct ir3_instruction
*precolor
[] = { ctx
->tcs_header
, ctx
->primitive_id
};
3676 ret
= ir3_ra(so
, precolor
, ARRAY_SIZE(precolor
));
3677 } else if (ctx
->gs_header
) {
3678 /* We need to have these values in the same registers between producer
3679 * (VS or DS) and GS since the producer chains to GS and doesn't get
3680 * the sysvals redelivered.
3683 ctx
->gs_header
->regs
[0]->num
= regid(0, 0);
3684 ctx
->primitive_id
->regs
[0]->num
= regid(0, 1);
3685 struct ir3_instruction
*precolor
[] = { ctx
->gs_header
, ctx
->primitive_id
};
3686 ret
= ir3_ra(so
, precolor
, ARRAY_SIZE(precolor
));
3687 } else if (so
->num_sampler_prefetch
) {
3688 assert(so
->type
== MESA_SHADER_FRAGMENT
);
3689 struct ir3_instruction
*precolor
[2];
3692 foreach_input (instr
, ir
) {
3693 if (instr
->input
.sysval
!= SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
)
3696 assert(idx
< ARRAY_SIZE(precolor
));
3698 precolor
[idx
] = instr
;
3699 instr
->regs
[0]->num
= idx
;
3703 ret
= ir3_ra(so
, precolor
, idx
);
3705 ret
= ir3_ra(so
, NULL
, 0);
3713 IR3_PASS(ir
, ir3_postsched
);
3715 if (compiler
->gpu_id
>= 600) {
3716 IR3_PASS(ir
, ir3_a6xx_fixup_atomic_dests
, so
);
3719 if (so
->type
== MESA_SHADER_FRAGMENT
)
3723 * Fixup inputs/outputs to point to the actual registers assigned:
3725 * 1) initialize to r63.x (invalid/unused)
3726 * 2) iterate IR level inputs/outputs and update the variants
3727 * inputs/outputs table based on the assigned registers for
3728 * the remaining inputs/outputs.
3731 for (unsigned i
= 0; i
< so
->inputs_count
; i
++)
3732 so
->inputs
[i
].regid
= INVALID_REG
;
3733 for (unsigned i
= 0; i
< so
->outputs_count
; i
++)
3734 so
->outputs
[i
].regid
= INVALID_REG
;
3736 foreach_output (out
, ir
) {
3737 assert(out
->opc
== OPC_META_COLLECT
);
3738 unsigned outidx
= out
->collect
.outidx
;
3740 so
->outputs
[outidx
].regid
= out
->regs
[0]->num
;
3741 so
->outputs
[outidx
].half
= !!(out
->regs
[0]->flags
& IR3_REG_HALF
);
3744 foreach_input (in
, ir
) {
3745 assert(in
->opc
== OPC_META_INPUT
);
3746 unsigned inidx
= in
->input
.inidx
;
3748 if (pre_assign_inputs
&& !so
->inputs
[inidx
].sysval
) {
3749 if (VALIDREG(so
->nonbinning
->inputs
[inidx
].regid
)) {
3750 compile_assert(ctx
, in
->regs
[0]->num
==
3751 so
->nonbinning
->inputs
[inidx
].regid
);
3752 compile_assert(ctx
, !!(in
->regs
[0]->flags
& IR3_REG_HALF
) ==
3753 so
->nonbinning
->inputs
[inidx
].half
);
3755 so
->inputs
[inidx
].regid
= so
->nonbinning
->inputs
[inidx
].regid
;
3756 so
->inputs
[inidx
].half
= so
->nonbinning
->inputs
[inidx
].half
;
3758 so
->inputs
[inidx
].regid
= in
->regs
[0]->num
;
3759 so
->inputs
[inidx
].half
= !!(in
->regs
[0]->flags
& IR3_REG_HALF
);
3764 fixup_astc_srgb(ctx
);
3766 /* We need to do legalize after (for frag shader's) the "bary.f"
3767 * offsets (inloc) have been assigned.
3769 IR3_PASS(ir
, ir3_legalize
, so
, &max_bary
);
3771 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3772 * know what we might have to wait on when coming in from VS chsh.
3774 if (so
->type
== MESA_SHADER_TESS_CTRL
||
3775 so
->type
== MESA_SHADER_GEOMETRY
) {
3776 foreach_block (block
, &ir
->block_list
) {
3777 foreach_instr (instr
, &block
->instr_list
) {
3778 instr
->flags
|= IR3_INSTR_SS
| IR3_INSTR_SY
;
3784 so
->branchstack
= ctx
->max_stack
;
3786 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3787 if (so
->type
== MESA_SHADER_FRAGMENT
)
3788 so
->total_in
= max_bary
+ 1;
3790 /* Collect sampling instructions eligible for pre-dispatch. */
3791 collect_tex_prefetches(ctx
, ir
);
3793 if (so
->type
== MESA_SHADER_FRAGMENT
&&
3794 ctx
->s
->info
.fs
.needs_helper_invocations
)
3795 so
->need_pixlod
= true;
3800 ir3_destroy(so
->ir
);
3803 ir3_context_free(ctx
);