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ir3: Remove VARYING_SLOT_PNTC remapping hack
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 __ssa_dst(mov);
55 src = __ssa_src(mov, collect, IR3_REG_RELATIV);
56 src->size = arrsz;
57 src->array.offset = n;
58
59 ir3_instr_set_address(mov, address);
60
61 return mov;
62 }
63
64 static struct ir3_instruction *
65 create_input(struct ir3_context *ctx, unsigned compmask)
66 {
67 struct ir3_instruction *in;
68
69 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
70 in->input.sysval = ~0;
71 __ssa_dst(in)->wrmask = compmask;
72
73 array_insert(ctx->ir, ctx->ir->inputs, in);
74
75 return in;
76 }
77
78 static struct ir3_instruction *
79 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
80 {
81 struct ir3_block *block = ctx->block;
82 struct ir3_instruction *instr;
83 /* packed inloc is fixed up later: */
84 struct ir3_instruction *inloc = create_immed(block, n);
85
86 if (use_ldlv) {
87 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
88 instr->cat6.type = TYPE_U32;
89 instr->cat6.iim_val = 1;
90 } else {
91 instr = ir3_BARY_F(block, inloc, 0, ctx->ij_pixel, 0);
92 instr->regs[2]->wrmask = 0x3;
93 }
94
95 return instr;
96 }
97
98 static struct ir3_instruction *
99 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
100 {
101 /* first four vec4 sysval's reserved for UBOs: */
102 /* NOTE: dp is in scalar, but there can be >4 dp components: */
103 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
104 unsigned n = const_state->offsets.driver_param;
105 unsigned r = regid(n + dp / 4, dp % 4);
106 return create_uniform(ctx->block, r);
107 }
108
109 /*
110 * Adreno uses uint rather than having dedicated bool type,
111 * which (potentially) requires some conversion, in particular
112 * when using output of an bool instr to int input, or visa
113 * versa.
114 *
115 * | Adreno | NIR |
116 * -------+---------+-------+-
117 * true | 1 | ~0 |
118 * false | 0 | 0 |
119 *
120 * To convert from an adreno bool (uint) to nir, use:
121 *
122 * absneg.s dst, (neg)src
123 *
124 * To convert back in the other direction:
125 *
126 * absneg.s dst, (abs)arc
127 *
128 * The CP step can clean up the absneg.s that cancel each other
129 * out, and with a slight bit of extra cleverness (to recognize
130 * the instructions which produce either a 0 or 1) can eliminate
131 * the absneg.s's completely when an instruction that wants
132 * 0/1 consumes the result. For example, when a nir 'bcsel'
133 * consumes the result of 'feq'. So we should be able to get by
134 * without a boolean resolve step, and without incuring any
135 * extra penalty in instruction count.
136 */
137
138 /* NIR bool -> native (adreno): */
139 static struct ir3_instruction *
140 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
141 {
142 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
143 }
144
145 /* native (adreno) -> NIR bool: */
146 static struct ir3_instruction *
147 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
148 {
149 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
150 }
151
152 /*
153 * alu/sfu instructions:
154 */
155
156 static struct ir3_instruction *
157 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
158 unsigned src_bitsize, nir_op op)
159 {
160 type_t src_type, dst_type;
161
162 switch (op) {
163 case nir_op_f2f32:
164 case nir_op_f2f16_rtne:
165 case nir_op_f2f16_rtz:
166 case nir_op_f2f16:
167 case nir_op_f2i32:
168 case nir_op_f2i16:
169 case nir_op_f2i8:
170 case nir_op_f2u32:
171 case nir_op_f2u16:
172 case nir_op_f2u8:
173 switch (src_bitsize) {
174 case 32:
175 src_type = TYPE_F32;
176 break;
177 case 16:
178 src_type = TYPE_F16;
179 break;
180 default:
181 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
182 }
183 break;
184
185 case nir_op_i2f32:
186 case nir_op_i2f16:
187 case nir_op_i2i32:
188 case nir_op_i2i16:
189 case nir_op_i2i8:
190 switch (src_bitsize) {
191 case 32:
192 src_type = TYPE_S32;
193 break;
194 case 16:
195 src_type = TYPE_S16;
196 break;
197 case 8:
198 src_type = TYPE_S8;
199 break;
200 default:
201 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
202 }
203 break;
204
205 case nir_op_u2f32:
206 case nir_op_u2f16:
207 case nir_op_u2u32:
208 case nir_op_u2u16:
209 case nir_op_u2u8:
210 switch (src_bitsize) {
211 case 32:
212 src_type = TYPE_U32;
213 break;
214 case 16:
215 src_type = TYPE_U16;
216 break;
217 case 8:
218 src_type = TYPE_U8;
219 break;
220 default:
221 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
222 }
223 break;
224
225 default:
226 ir3_context_error(ctx, "invalid conversion op: %u", op);
227 }
228
229 switch (op) {
230 case nir_op_f2f32:
231 case nir_op_i2f32:
232 case nir_op_u2f32:
233 dst_type = TYPE_F32;
234 break;
235
236 case nir_op_f2f16_rtne:
237 case nir_op_f2f16_rtz:
238 case nir_op_f2f16:
239 case nir_op_i2f16:
240 case nir_op_u2f16:
241 dst_type = TYPE_F16;
242 break;
243
244 case nir_op_f2i32:
245 case nir_op_i2i32:
246 dst_type = TYPE_S32;
247 break;
248
249 case nir_op_f2i16:
250 case nir_op_i2i16:
251 dst_type = TYPE_S16;
252 break;
253
254 case nir_op_f2i8:
255 case nir_op_i2i8:
256 dst_type = TYPE_S8;
257 break;
258
259 case nir_op_f2u32:
260 case nir_op_u2u32:
261 dst_type = TYPE_U32;
262 break;
263
264 case nir_op_f2u16:
265 case nir_op_u2u16:
266 dst_type = TYPE_U16;
267 break;
268
269 case nir_op_f2u8:
270 case nir_op_u2u8:
271 dst_type = TYPE_U8;
272 break;
273
274 default:
275 ir3_context_error(ctx, "invalid conversion op: %u", op);
276 }
277
278 struct ir3_instruction *cov =
279 ir3_COV(ctx->block, src, src_type, dst_type);
280
281 if (op == nir_op_f2f16_rtne)
282 cov->regs[0]->flags |= IR3_REG_EVEN;
283
284 return cov;
285 }
286
287 static void
288 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
289 {
290 const nir_op_info *info = &nir_op_infos[alu->op];
291 struct ir3_instruction **dst, *src[info->num_inputs];
292 unsigned bs[info->num_inputs]; /* bit size */
293 struct ir3_block *b = ctx->block;
294 unsigned dst_sz, wrmask;
295 type_t dst_type = nir_dest_bit_size(alu->dest.dest) < 32 ?
296 TYPE_U16 : TYPE_U32;
297
298 if (alu->dest.dest.is_ssa) {
299 dst_sz = alu->dest.dest.ssa.num_components;
300 wrmask = (1 << dst_sz) - 1;
301 } else {
302 dst_sz = alu->dest.dest.reg.reg->num_components;
303 wrmask = alu->dest.write_mask;
304 }
305
306 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
307
308 /* Vectors are special in that they have non-scalarized writemasks,
309 * and just take the first swizzle channel for each argument in
310 * order into each writemask channel.
311 */
312 if ((alu->op == nir_op_vec2) ||
313 (alu->op == nir_op_vec3) ||
314 (alu->op == nir_op_vec4)) {
315
316 for (int i = 0; i < info->num_inputs; i++) {
317 nir_alu_src *asrc = &alu->src[i];
318
319 compile_assert(ctx, !asrc->abs);
320 compile_assert(ctx, !asrc->negate);
321
322 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
323 if (!src[i])
324 src[i] = create_immed_typed(ctx->block, 0, dst_type);
325 dst[i] = ir3_MOV(b, src[i], dst_type);
326 }
327
328 ir3_put_dst(ctx, &alu->dest.dest);
329 return;
330 }
331
332 /* We also get mov's with more than one component for mov's so
333 * handle those specially:
334 */
335 if (alu->op == nir_op_mov) {
336 nir_alu_src *asrc = &alu->src[0];
337 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
338
339 for (unsigned i = 0; i < dst_sz; i++) {
340 if (wrmask & (1 << i)) {
341 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
342 } else {
343 dst[i] = NULL;
344 }
345 }
346
347 ir3_put_dst(ctx, &alu->dest.dest);
348 return;
349 }
350
351 /* General case: We can just grab the one used channel per src. */
352 for (int i = 0; i < info->num_inputs; i++) {
353 unsigned chan = ffs(alu->dest.write_mask) - 1;
354 nir_alu_src *asrc = &alu->src[i];
355
356 compile_assert(ctx, !asrc->abs);
357 compile_assert(ctx, !asrc->negate);
358
359 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
360 bs[i] = nir_src_bit_size(asrc->src);
361
362 compile_assert(ctx, src[i]);
363 }
364
365 switch (alu->op) {
366 case nir_op_f2f32:
367 case nir_op_f2f16_rtne:
368 case nir_op_f2f16_rtz:
369 case nir_op_f2f16:
370 case nir_op_f2i32:
371 case nir_op_f2i16:
372 case nir_op_f2i8:
373 case nir_op_f2u32:
374 case nir_op_f2u16:
375 case nir_op_f2u8:
376 case nir_op_i2f32:
377 case nir_op_i2f16:
378 case nir_op_i2i32:
379 case nir_op_i2i16:
380 case nir_op_i2i8:
381 case nir_op_u2f32:
382 case nir_op_u2f16:
383 case nir_op_u2u32:
384 case nir_op_u2u16:
385 case nir_op_u2u8:
386 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
387 break;
388 case nir_op_fquantize2f16:
389 dst[0] = create_cov(ctx,
390 create_cov(ctx, src[0], 32, nir_op_f2f16),
391 16, nir_op_f2f32);
392 break;
393 case nir_op_f2b16: {
394 struct ir3_instruction *zero = create_immed_typed(b, 0, TYPE_F16);
395 dst[0] = ir3_CMPS_F(b, src[0], 0, zero, 0);
396 dst[0]->cat2.condition = IR3_COND_NE;
397 break;
398 }
399 case nir_op_f2b32:
400 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
401 dst[0]->cat2.condition = IR3_COND_NE;
402 break;
403 case nir_op_b2f16:
404 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F16);
405 break;
406 case nir_op_b2f32:
407 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
408 break;
409 case nir_op_b2i8:
410 case nir_op_b2i16:
411 case nir_op_b2i32:
412 dst[0] = ir3_b2n(b, src[0]);
413 break;
414 case nir_op_i2b16: {
415 struct ir3_instruction *zero = create_immed_typed(b, 0, TYPE_S16);
416 dst[0] = ir3_CMPS_S(b, src[0], 0, zero, 0);
417 dst[0]->cat2.condition = IR3_COND_NE;
418 break;
419 }
420 case nir_op_i2b32:
421 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
422 dst[0]->cat2.condition = IR3_COND_NE;
423 break;
424
425 case nir_op_fneg:
426 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
427 break;
428 case nir_op_fabs:
429 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
430 break;
431 case nir_op_fmax:
432 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
433 break;
434 case nir_op_fmin:
435 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
436 break;
437 case nir_op_fsat:
438 /* if there is just a single use of the src, and it supports
439 * (sat) bit, we can just fold the (sat) flag back to the
440 * src instruction and create a mov. This is easier for cp
441 * to eliminate.
442 *
443 * TODO probably opc_cat==4 is ok too
444 */
445 if (alu->src[0].src.is_ssa &&
446 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
447 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
448 src[0]->flags |= IR3_INSTR_SAT;
449 dst[0] = ir3_MOV(b, src[0], dst_type);
450 } else {
451 /* otherwise generate a max.f that saturates.. blob does
452 * similar (generating a cat2 mov using max.f)
453 */
454 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
455 dst[0]->flags |= IR3_INSTR_SAT;
456 }
457 break;
458 case nir_op_fmul:
459 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
460 break;
461 case nir_op_fadd:
462 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
463 break;
464 case nir_op_fsub:
465 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
466 break;
467 case nir_op_ffma:
468 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
469 break;
470 case nir_op_fddx:
471 case nir_op_fddx_coarse:
472 dst[0] = ir3_DSX(b, src[0], 0);
473 dst[0]->cat5.type = TYPE_F32;
474 break;
475 case nir_op_fddx_fine:
476 dst[0] = ir3_DSXPP_1(b, src[0], 0);
477 dst[0]->cat5.type = TYPE_F32;
478 break;
479 case nir_op_fddy:
480 case nir_op_fddy_coarse:
481 dst[0] = ir3_DSY(b, src[0], 0);
482 dst[0]->cat5.type = TYPE_F32;
483 break;
484 break;
485 case nir_op_fddy_fine:
486 dst[0] = ir3_DSYPP_1(b, src[0], 0);
487 dst[0]->cat5.type = TYPE_F32;
488 break;
489 case nir_op_flt16:
490 case nir_op_flt32:
491 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
492 dst[0]->cat2.condition = IR3_COND_LT;
493 break;
494 case nir_op_fge16:
495 case nir_op_fge32:
496 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
497 dst[0]->cat2.condition = IR3_COND_GE;
498 break;
499 case nir_op_feq16:
500 case nir_op_feq32:
501 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
502 dst[0]->cat2.condition = IR3_COND_EQ;
503 break;
504 case nir_op_fne16:
505 case nir_op_fne32:
506 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
507 dst[0]->cat2.condition = IR3_COND_NE;
508 break;
509 case nir_op_fceil:
510 dst[0] = ir3_CEIL_F(b, src[0], 0);
511 break;
512 case nir_op_ffloor:
513 dst[0] = ir3_FLOOR_F(b, src[0], 0);
514 break;
515 case nir_op_ftrunc:
516 dst[0] = ir3_TRUNC_F(b, src[0], 0);
517 break;
518 case nir_op_fround_even:
519 dst[0] = ir3_RNDNE_F(b, src[0], 0);
520 break;
521 case nir_op_fsign:
522 dst[0] = ir3_SIGN_F(b, src[0], 0);
523 break;
524
525 case nir_op_fsin:
526 dst[0] = ir3_SIN(b, src[0], 0);
527 break;
528 case nir_op_fcos:
529 dst[0] = ir3_COS(b, src[0], 0);
530 break;
531 case nir_op_frsq:
532 dst[0] = ir3_RSQ(b, src[0], 0);
533 break;
534 case nir_op_frcp:
535 dst[0] = ir3_RCP(b, src[0], 0);
536 break;
537 case nir_op_flog2:
538 dst[0] = ir3_LOG2(b, src[0], 0);
539 break;
540 case nir_op_fexp2:
541 dst[0] = ir3_EXP2(b, src[0], 0);
542 break;
543 case nir_op_fsqrt:
544 dst[0] = ir3_SQRT(b, src[0], 0);
545 break;
546
547 case nir_op_iabs:
548 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
549 break;
550 case nir_op_iadd:
551 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
552 break;
553 case nir_op_iand:
554 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
555 break;
556 case nir_op_imax:
557 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
558 break;
559 case nir_op_umax:
560 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
561 break;
562 case nir_op_imin:
563 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
564 break;
565 case nir_op_umin:
566 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
567 break;
568 case nir_op_umul_low:
569 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
570 break;
571 case nir_op_imadsh_mix16:
572 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
573 break;
574 case nir_op_imad24_ir3:
575 dst[0] = ir3_MAD_S24(b, src[0], 0, src[1], 0, src[2], 0);
576 break;
577 case nir_op_imul24:
578 dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
579 break;
580 case nir_op_ineg:
581 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
582 break;
583 case nir_op_inot:
584 dst[0] = ir3_NOT_B(b, src[0], 0);
585 break;
586 case nir_op_ior:
587 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
588 break;
589 case nir_op_ishl:
590 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
591 break;
592 case nir_op_ishr:
593 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
594 break;
595 case nir_op_isub:
596 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
597 break;
598 case nir_op_ixor:
599 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
600 break;
601 case nir_op_ushr:
602 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
603 break;
604 case nir_op_ilt16:
605 case nir_op_ilt32:
606 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
607 dst[0]->cat2.condition = IR3_COND_LT;
608 break;
609 case nir_op_ige16:
610 case nir_op_ige32:
611 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
612 dst[0]->cat2.condition = IR3_COND_GE;
613 break;
614 case nir_op_ieq16:
615 case nir_op_ieq32:
616 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
617 dst[0]->cat2.condition = IR3_COND_EQ;
618 break;
619 case nir_op_ine16:
620 case nir_op_ine32:
621 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
622 dst[0]->cat2.condition = IR3_COND_NE;
623 break;
624 case nir_op_ult16:
625 case nir_op_ult32:
626 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
627 dst[0]->cat2.condition = IR3_COND_LT;
628 break;
629 case nir_op_uge16:
630 case nir_op_uge32:
631 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
632 dst[0]->cat2.condition = IR3_COND_GE;
633 break;
634
635 case nir_op_b16csel:
636 case nir_op_b32csel: {
637 struct ir3_instruction *cond = src[0];
638
639 /* If src[0] is a negation (likely as a result of an ir3_b2n(cond)),
640 * we can ignore that and use original cond, since the nonzero-ness of
641 * cond stays the same.
642 */
643 if (cond->opc == OPC_ABSNEG_S &&
644 cond->flags == 0 &&
645 (cond->regs[1]->flags & (IR3_REG_SNEG | IR3_REG_SABS)) == IR3_REG_SNEG) {
646 cond = cond->regs[1]->instr;
647 }
648
649 compile_assert(ctx, bs[1] == bs[2]);
650 if (bs[1] != bs[0]) {
651 struct hash_entry *prev_entry =
652 _mesa_hash_table_search(ctx->sel_cond_conversions, src[0]);
653 if (prev_entry) {
654 cond = prev_entry->data;
655 } else {
656 /* Make sure the boolean condition has the same bit size as the other
657 * two arguments, adding a conversion if necessary.
658 */
659 if (bs[1] < bs[0])
660 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
661 else if (bs[1] > bs[0])
662 cond = ir3_COV(b, cond, TYPE_U16, TYPE_U32);
663 _mesa_hash_table_insert(ctx->sel_cond_conversions, src[0], cond);
664 }
665 }
666
667 if (bs[1] > 16)
668 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
669 else
670 dst[0] = ir3_SEL_B16(b, src[1], 0, cond, 0, src[2], 0);
671 break;
672 }
673 case nir_op_bit_count: {
674 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
675 // double check on earlier gen's. Once half-precision support is
676 // in place, this should probably move to a NIR lowering pass:
677 struct ir3_instruction *hi, *lo;
678
679 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
680 TYPE_U32, TYPE_U16);
681 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
682
683 hi = ir3_CBITS_B(b, hi, 0);
684 lo = ir3_CBITS_B(b, lo, 0);
685
686 // TODO maybe the builders should default to making dst half-precision
687 // if the src's were half precision, to make this less awkward.. otoh
688 // we should probably just do this lowering in NIR.
689 hi->regs[0]->flags |= IR3_REG_HALF;
690 lo->regs[0]->flags |= IR3_REG_HALF;
691
692 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
693 dst[0]->regs[0]->flags |= IR3_REG_HALF;
694 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
695 break;
696 }
697 case nir_op_ifind_msb: {
698 struct ir3_instruction *cmp;
699 dst[0] = ir3_CLZ_S(b, src[0], 0);
700 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
701 cmp->cat2.condition = IR3_COND_GE;
702 dst[0] = ir3_SEL_B32(b,
703 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
704 cmp, 0, dst[0], 0);
705 break;
706 }
707 case nir_op_ufind_msb:
708 dst[0] = ir3_CLZ_B(b, src[0], 0);
709 dst[0] = ir3_SEL_B32(b,
710 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
711 src[0], 0, dst[0], 0);
712 break;
713 case nir_op_find_lsb:
714 dst[0] = ir3_BFREV_B(b, src[0], 0);
715 dst[0] = ir3_CLZ_B(b, dst[0], 0);
716 break;
717 case nir_op_bitfield_reverse:
718 dst[0] = ir3_BFREV_B(b, src[0], 0);
719 break;
720
721 default:
722 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
723 nir_op_infos[alu->op].name);
724 break;
725 }
726
727 if (nir_alu_type_get_base_type(info->output_type) == nir_type_bool) {
728 assert(dst_sz == 1);
729
730 if (nir_dest_bit_size(alu->dest.dest) < 32)
731 dst[0]->regs[0]->flags |= IR3_REG_HALF;
732
733 dst[0] = ir3_n2b(b, dst[0]);
734 }
735
736 if (nir_dest_bit_size(alu->dest.dest) < 32) {
737 for (unsigned i = 0; i < dst_sz; i++) {
738 dst[i]->regs[0]->flags |= IR3_REG_HALF;
739 }
740 }
741
742 ir3_put_dst(ctx, &alu->dest.dest);
743 }
744
745 static void
746 emit_intrinsic_load_ubo_ldc(struct ir3_context *ctx, nir_intrinsic_instr *intr,
747 struct ir3_instruction **dst)
748 {
749 struct ir3_block *b = ctx->block;
750
751 unsigned ncomp = intr->num_components;
752 struct ir3_instruction *offset = ir3_get_src(ctx, &intr->src[1])[0];
753 struct ir3_instruction *idx = ir3_get_src(ctx, &intr->src[0])[0];
754 struct ir3_instruction *ldc = ir3_LDC(b, idx, 0, offset, 0);
755 ldc->regs[0]->wrmask = MASK(ncomp);
756 ldc->cat6.iim_val = ncomp;
757 ldc->cat6.d = nir_intrinsic_base(intr);
758 ldc->cat6.type = TYPE_U32;
759
760 nir_intrinsic_instr *bindless = ir3_bindless_resource(intr->src[0]);
761 if (bindless) {
762 ldc->flags |= IR3_INSTR_B;
763 ldc->cat6.base = nir_intrinsic_desc_set(bindless);
764 ctx->so->bindless_ubo = true;
765 }
766
767 ir3_split_dest(b, dst, ldc, 0, ncomp);
768 }
769
770
771 /* handles direct/indirect UBO reads: */
772 static void
773 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
774 struct ir3_instruction **dst)
775 {
776 struct ir3_block *b = ctx->block;
777 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
778 /* UBO addresses are the first driver params, but subtract 2 here to
779 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
780 * is the uniforms: */
781 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
782 unsigned ubo = regid(const_state->offsets.ubo, 0) - 2;
783 const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
784
785 int off = 0;
786
787 /* First src is ubo index, which could either be an immed or not: */
788 src0 = ir3_get_src(ctx, &intr->src[0])[0];
789 if (is_same_type_mov(src0) &&
790 (src0->regs[1]->flags & IR3_REG_IMMED)) {
791 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
792 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
793 } else {
794 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr0(ctx, src0, ptrsz));
795 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr0(ctx, src0, ptrsz));
796
797 /* NOTE: since relative addressing is used, make sure constlen is
798 * at least big enough to cover all the UBO addresses, since the
799 * assembler won't know what the max address reg is.
800 */
801 ctx->so->constlen = MAX2(ctx->so->constlen,
802 const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
803 }
804
805 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
806 addr = base_lo;
807
808 if (nir_src_is_const(intr->src[1])) {
809 off += nir_src_as_uint(intr->src[1]);
810 } else {
811 /* For load_ubo_indirect, second src is indirect offset: */
812 src1 = ir3_get_src(ctx, &intr->src[1])[0];
813
814 /* and add offset to addr: */
815 addr = ir3_ADD_S(b, addr, 0, src1, 0);
816 }
817
818 /* if offset is to large to encode in the ldg, split it out: */
819 if ((off + (intr->num_components * 4)) > 1024) {
820 /* split out the minimal amount to improve the odds that
821 * cp can fit the immediate in the add.s instruction:
822 */
823 unsigned off2 = off + (intr->num_components * 4) - 1024;
824 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
825 off -= off2;
826 }
827
828 if (ptrsz == 2) {
829 struct ir3_instruction *carry;
830
831 /* handle 32b rollover, ie:
832 * if (addr < base_lo)
833 * base_hi++
834 */
835 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
836 carry->cat2.condition = IR3_COND_LT;
837 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
838
839 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
840 }
841
842 for (int i = 0; i < intr->num_components; i++) {
843 struct ir3_instruction *load =
844 ir3_LDG(b, addr, 0, create_immed(b, 1), 0, /* num components */
845 create_immed(b, off + i * 4), 0);
846 load->cat6.type = TYPE_U32;
847 dst[i] = load;
848 }
849 }
850
851 /* src[] = { block_index } */
852 static void
853 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
854 struct ir3_instruction **dst)
855 {
856 /* SSBO size stored as a const starting at ssbo_sizes: */
857 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
858 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
859 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
860 const_state->ssbo_size.off[blk_idx];
861
862 debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
863
864 dst[0] = create_uniform(ctx->block, idx);
865 }
866
867 /* src[] = { offset }. const_index[] = { base } */
868 static void
869 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
870 struct ir3_instruction **dst)
871 {
872 struct ir3_block *b = ctx->block;
873 struct ir3_instruction *ldl, *offset;
874 unsigned base;
875
876 offset = ir3_get_src(ctx, &intr->src[0])[0];
877 base = nir_intrinsic_base(intr);
878
879 ldl = ir3_LDL(b, offset, 0,
880 create_immed(b, intr->num_components), 0,
881 create_immed(b, base), 0);
882
883 ldl->cat6.type = utype_dst(intr->dest);
884 ldl->regs[0]->wrmask = MASK(intr->num_components);
885
886 ldl->barrier_class = IR3_BARRIER_SHARED_R;
887 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
888
889 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
890 }
891
892 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
893 static void
894 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
895 {
896 struct ir3_block *b = ctx->block;
897 struct ir3_instruction *stl, *offset;
898 struct ir3_instruction * const *value;
899 unsigned base, wrmask;
900
901 value = ir3_get_src(ctx, &intr->src[0]);
902 offset = ir3_get_src(ctx, &intr->src[1])[0];
903
904 base = nir_intrinsic_base(intr);
905 wrmask = nir_intrinsic_write_mask(intr);
906
907 /* Combine groups of consecutive enabled channels in one write
908 * message. We use ffs to find the first enabled channel and then ffs on
909 * the bit-inverse, down-shifted writemask to determine the length of
910 * the block of enabled bits.
911 *
912 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
913 */
914 while (wrmask) {
915 unsigned first_component = ffs(wrmask) - 1;
916 unsigned length = ffs(~(wrmask >> first_component)) - 1;
917
918 stl = ir3_STL(b, offset, 0,
919 ir3_create_collect(ctx, &value[first_component], length), 0,
920 create_immed(b, length), 0);
921 stl->cat6.dst_offset = first_component + base;
922 stl->cat6.type = utype_src(intr->src[0]);
923 stl->barrier_class = IR3_BARRIER_SHARED_W;
924 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
925
926 array_insert(b, b->keeps, stl);
927
928 /* Clear the bits in the writemask that we just wrote, then try
929 * again to see if more channels are left.
930 */
931 wrmask &= (15 << (first_component + length));
932 }
933 }
934
935 /* src[] = { offset }. const_index[] = { base } */
936 static void
937 emit_intrinsic_load_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr,
938 struct ir3_instruction **dst)
939 {
940 struct ir3_block *b = ctx->block;
941 struct ir3_instruction *load, *offset;
942 unsigned base;
943
944 offset = ir3_get_src(ctx, &intr->src[0])[0];
945 base = nir_intrinsic_base(intr);
946
947 load = ir3_LDLW(b, offset, 0,
948 create_immed(b, intr->num_components), 0,
949 create_immed(b, base), 0);
950
951 load->cat6.type = utype_dst(intr->dest);
952 load->regs[0]->wrmask = MASK(intr->num_components);
953
954 load->barrier_class = IR3_BARRIER_SHARED_R;
955 load->barrier_conflict = IR3_BARRIER_SHARED_W;
956
957 ir3_split_dest(b, dst, load, 0, intr->num_components);
958 }
959
960 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
961 static void
962 emit_intrinsic_store_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr)
963 {
964 struct ir3_block *b = ctx->block;
965 struct ir3_instruction *store, *offset;
966 struct ir3_instruction * const *value;
967 unsigned base, wrmask;
968
969 value = ir3_get_src(ctx, &intr->src[0]);
970 offset = ir3_get_src(ctx, &intr->src[1])[0];
971
972 base = nir_intrinsic_base(intr);
973 wrmask = nir_intrinsic_write_mask(intr);
974
975 /* Combine groups of consecutive enabled channels in one write
976 * message. We use ffs to find the first enabled channel and then ffs on
977 * the bit-inverse, down-shifted writemask to determine the length of
978 * the block of enabled bits.
979 *
980 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
981 */
982 while (wrmask) {
983 unsigned first_component = ffs(wrmask) - 1;
984 unsigned length = ffs(~(wrmask >> first_component)) - 1;
985
986 store = ir3_STLW(b, offset, 0,
987 ir3_create_collect(ctx, &value[first_component], length), 0,
988 create_immed(b, length), 0);
989
990 store->cat6.dst_offset = first_component + base;
991 store->cat6.type = utype_src(intr->src[0]);
992 store->barrier_class = IR3_BARRIER_SHARED_W;
993 store->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
994
995 array_insert(b, b->keeps, store);
996
997 /* Clear the bits in the writemask that we just wrote, then try
998 * again to see if more channels are left.
999 */
1000 wrmask &= (15 << (first_component + length));
1001 }
1002 }
1003
1004 /*
1005 * CS shared variable atomic intrinsics
1006 *
1007 * All of the shared variable atomic memory operations read a value from
1008 * memory, compute a new value using one of the operations below, write the
1009 * new value to memory, and return the original value read.
1010 *
1011 * All operations take 2 sources except CompSwap that takes 3. These
1012 * sources represent:
1013 *
1014 * 0: The offset into the shared variable storage region that the atomic
1015 * operation will operate on.
1016 * 1: The data parameter to the atomic function (i.e. the value to add
1017 * in shared_atomic_add, etc).
1018 * 2: For CompSwap only: the second data parameter.
1019 */
1020 static struct ir3_instruction *
1021 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1022 {
1023 struct ir3_block *b = ctx->block;
1024 struct ir3_instruction *atomic, *src0, *src1;
1025 type_t type = TYPE_U32;
1026
1027 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
1028 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
1029
1030 switch (intr->intrinsic) {
1031 case nir_intrinsic_shared_atomic_add:
1032 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
1033 break;
1034 case nir_intrinsic_shared_atomic_imin:
1035 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
1036 type = TYPE_S32;
1037 break;
1038 case nir_intrinsic_shared_atomic_umin:
1039 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
1040 break;
1041 case nir_intrinsic_shared_atomic_imax:
1042 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1043 type = TYPE_S32;
1044 break;
1045 case nir_intrinsic_shared_atomic_umax:
1046 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1047 break;
1048 case nir_intrinsic_shared_atomic_and:
1049 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
1050 break;
1051 case nir_intrinsic_shared_atomic_or:
1052 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
1053 break;
1054 case nir_intrinsic_shared_atomic_xor:
1055 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
1056 break;
1057 case nir_intrinsic_shared_atomic_exchange:
1058 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
1059 break;
1060 case nir_intrinsic_shared_atomic_comp_swap:
1061 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1062 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1063 ir3_get_src(ctx, &intr->src[2])[0],
1064 src1,
1065 }, 2);
1066 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
1067 break;
1068 default:
1069 unreachable("boo");
1070 }
1071
1072 atomic->cat6.iim_val = 1;
1073 atomic->cat6.d = 1;
1074 atomic->cat6.type = type;
1075 atomic->barrier_class = IR3_BARRIER_SHARED_W;
1076 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
1077
1078 /* even if nothing consume the result, we can't DCE the instruction: */
1079 array_insert(b, b->keeps, atomic);
1080
1081 return atomic;
1082 }
1083
1084 struct tex_src_info {
1085 /* For prefetch */
1086 unsigned tex_base, samp_base, tex_idx, samp_idx;
1087 /* For normal tex instructions */
1088 unsigned base, combined_idx, a1_val, flags;
1089 struct ir3_instruction *samp_tex;
1090 };
1091
1092 /* TODO handle actual indirect/dynamic case.. which is going to be weird
1093 * to handle with the image_mapping table..
1094 */
1095 static struct tex_src_info
1096 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1097 {
1098 struct ir3_block *b = ctx->block;
1099 struct tex_src_info info = { 0 };
1100 nir_intrinsic_instr *bindless_tex = ir3_bindless_resource(intr->src[0]);
1101 ctx->so->bindless_tex = true;
1102
1103 if (bindless_tex) {
1104 /* Bindless case */
1105 info.flags |= IR3_INSTR_B;
1106
1107 /* Gather information required to determine which encoding to
1108 * choose as well as for prefetch.
1109 */
1110 info.tex_base = nir_intrinsic_desc_set(bindless_tex);
1111 bool tex_const = nir_src_is_const(bindless_tex->src[0]);
1112 if (tex_const)
1113 info.tex_idx = nir_src_as_uint(bindless_tex->src[0]);
1114 info.samp_idx = 0;
1115
1116 /* Choose encoding. */
1117 if (tex_const && info.tex_idx < 256) {
1118 if (info.tex_idx < 16) {
1119 /* Everything fits within the instruction */
1120 info.base = info.tex_base;
1121 info.combined_idx = info.samp_idx | (info.tex_idx << 4);
1122 } else {
1123 info.base = info.tex_base;
1124 info.a1_val = info.tex_idx << 3;
1125 info.combined_idx = 0;
1126 info.flags |= IR3_INSTR_A1EN;
1127 }
1128 info.samp_tex = NULL;
1129 } else {
1130 info.flags |= IR3_INSTR_S2EN;
1131 info.base = info.tex_base;
1132
1133 /* Note: the indirect source is now a vec2 instead of hvec2 */
1134 struct ir3_instruction *texture, *sampler;
1135
1136 texture = ir3_get_src(ctx, &intr->src[0])[0];
1137 sampler = create_immed(b, 0);
1138 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1139 texture,
1140 sampler,
1141 }, 2);
1142 }
1143 } else {
1144 info.flags |= IR3_INSTR_S2EN;
1145 unsigned slot = nir_src_as_uint(intr->src[0]);
1146 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
1147 struct ir3_instruction *texture, *sampler;
1148
1149 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1150 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1151
1152 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1153 sampler,
1154 texture,
1155 }, 2);
1156 }
1157
1158 return info;
1159 }
1160
1161 static struct ir3_instruction *
1162 emit_sam(struct ir3_context *ctx, opc_t opc, struct tex_src_info info,
1163 type_t type, unsigned wrmask, struct ir3_instruction *src0,
1164 struct ir3_instruction *src1)
1165 {
1166 struct ir3_instruction *sam, *addr;
1167 if (info.flags & IR3_INSTR_A1EN) {
1168 addr = ir3_get_addr1(ctx, info.a1_val);
1169 }
1170 sam = ir3_SAM(ctx->block, opc, type, 0b1111, info.flags,
1171 info.samp_tex, src0, src1);
1172 if (info.flags & IR3_INSTR_A1EN) {
1173 ir3_instr_set_address(sam, addr);
1174 }
1175 if (info.flags & IR3_INSTR_B) {
1176 sam->cat5.tex_base = info.base;
1177 sam->cat5.samp = info.combined_idx;
1178 }
1179 return sam;
1180 }
1181
1182 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1183 static void
1184 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1185 struct ir3_instruction **dst)
1186 {
1187 struct ir3_block *b = ctx->block;
1188 struct tex_src_info info = get_image_samp_tex_src(ctx, intr);
1189 struct ir3_instruction *sam;
1190 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
1191 struct ir3_instruction *coords[4];
1192 unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
1193 type_t type = ir3_get_type_for_image_intrinsic(intr);
1194
1195 /* hmm, this seems a bit odd, but it is what blob does and (at least
1196 * a5xx) just faults on bogus addresses otherwise:
1197 */
1198 if (flags & IR3_INSTR_3D) {
1199 flags &= ~IR3_INSTR_3D;
1200 flags |= IR3_INSTR_A;
1201 }
1202 info.flags |= flags;
1203
1204 for (unsigned i = 0; i < ncoords; i++)
1205 coords[i] = src0[i];
1206
1207 if (ncoords == 1)
1208 coords[ncoords++] = create_immed(b, 0);
1209
1210 sam = emit_sam(ctx, OPC_ISAM, info, type, 0b1111,
1211 ir3_create_collect(ctx, coords, ncoords), NULL);
1212
1213 sam->barrier_class = IR3_BARRIER_IMAGE_R;
1214 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
1215
1216 ir3_split_dest(b, dst, sam, 0, 4);
1217 }
1218
1219 static void
1220 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1221 struct ir3_instruction **dst)
1222 {
1223 struct ir3_block *b = ctx->block;
1224 struct tex_src_info info = get_image_samp_tex_src(ctx, intr);
1225 struct ir3_instruction *sam, *lod;
1226 unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
1227 type_t dst_type = nir_dest_bit_size(intr->dest) < 32 ?
1228 TYPE_U16 : TYPE_U32;
1229
1230 info.flags |= flags;
1231 lod = create_immed(b, 0);
1232 sam = emit_sam(ctx, OPC_GETSIZE, info, dst_type, 0b1111, lod, NULL);
1233
1234 /* Array size actually ends up in .w rather than .z. This doesn't
1235 * matter for miplevel 0, but for higher mips the value in z is
1236 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1237 * returned, which means that we have to add 1 to it for arrays for
1238 * a3xx.
1239 *
1240 * Note use a temporary dst and then copy, since the size of the dst
1241 * array that is passed in is based on nir's understanding of the
1242 * result size, not the hardware's
1243 */
1244 struct ir3_instruction *tmp[4];
1245
1246 ir3_split_dest(b, tmp, sam, 0, 4);
1247
1248 /* get_size instruction returns size in bytes instead of texels
1249 * for imageBuffer, so we need to divide it by the pixel size
1250 * of the image format.
1251 *
1252 * TODO: This is at least true on a5xx. Check other gens.
1253 */
1254 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF) {
1255 /* Since all the possible values the divisor can take are
1256 * power-of-two (4, 8, or 16), the division is implemented
1257 * as a shift-right.
1258 * During shader setup, the log2 of the image format's
1259 * bytes-per-pixel should have been emitted in 2nd slot of
1260 * image_dims. See ir3_shader::emit_image_dims().
1261 */
1262 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
1263 unsigned cb = regid(const_state->offsets.image_dims, 0) +
1264 const_state->image_dims.off[nir_src_as_uint(intr->src[0])];
1265 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1266
1267 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1268 }
1269
1270 for (unsigned i = 0; i < ncoords; i++)
1271 dst[i] = tmp[i];
1272
1273 if (flags & IR3_INSTR_A) {
1274 if (ctx->compiler->levels_add_one) {
1275 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1276 } else {
1277 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1278 }
1279 }
1280 }
1281
1282 static void
1283 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1284 {
1285 struct ir3_block *b = ctx->block;
1286 struct ir3_instruction *barrier;
1287
1288 switch (intr->intrinsic) {
1289 case nir_intrinsic_control_barrier:
1290 barrier = ir3_BAR(b);
1291 barrier->cat7.g = true;
1292 barrier->cat7.l = true;
1293 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1294 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1295 break;
1296 case nir_intrinsic_memory_barrier:
1297 barrier = ir3_FENCE(b);
1298 barrier->cat7.g = true;
1299 barrier->cat7.r = true;
1300 barrier->cat7.w = true;
1301 barrier->cat7.l = true;
1302 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1303 IR3_BARRIER_BUFFER_W;
1304 barrier->barrier_conflict =
1305 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1306 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1307 break;
1308 case nir_intrinsic_memory_barrier_buffer:
1309 barrier = ir3_FENCE(b);
1310 barrier->cat7.g = true;
1311 barrier->cat7.r = true;
1312 barrier->cat7.w = true;
1313 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1314 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1315 IR3_BARRIER_BUFFER_W;
1316 break;
1317 case nir_intrinsic_memory_barrier_image:
1318 // TODO double check if this should have .g set
1319 barrier = ir3_FENCE(b);
1320 barrier->cat7.g = true;
1321 barrier->cat7.r = true;
1322 barrier->cat7.w = true;
1323 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1324 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1325 IR3_BARRIER_IMAGE_W;
1326 break;
1327 case nir_intrinsic_memory_barrier_shared:
1328 barrier = ir3_FENCE(b);
1329 barrier->cat7.g = true;
1330 barrier->cat7.l = true;
1331 barrier->cat7.r = true;
1332 barrier->cat7.w = true;
1333 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1334 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1335 IR3_BARRIER_SHARED_W;
1336 break;
1337 case nir_intrinsic_group_memory_barrier:
1338 barrier = ir3_FENCE(b);
1339 barrier->cat7.g = true;
1340 barrier->cat7.l = true;
1341 barrier->cat7.r = true;
1342 barrier->cat7.w = true;
1343 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1344 IR3_BARRIER_IMAGE_W |
1345 IR3_BARRIER_BUFFER_W;
1346 barrier->barrier_conflict =
1347 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1348 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1349 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1350 break;
1351 default:
1352 unreachable("boo");
1353 }
1354
1355 /* make sure barrier doesn't get DCE'd */
1356 array_insert(b, b->keeps, barrier);
1357 }
1358
1359 static void add_sysval_input_compmask(struct ir3_context *ctx,
1360 gl_system_value slot, unsigned compmask,
1361 struct ir3_instruction *instr)
1362 {
1363 struct ir3_shader_variant *so = ctx->so;
1364 unsigned n = so->inputs_count++;
1365
1366 assert(instr->opc == OPC_META_INPUT);
1367 instr->input.inidx = n;
1368 instr->input.sysval = slot;
1369
1370 so->inputs[n].sysval = true;
1371 so->inputs[n].slot = slot;
1372 so->inputs[n].compmask = compmask;
1373 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1374 so->total_in++;
1375 }
1376
1377 static struct ir3_instruction *
1378 create_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1379 unsigned compmask)
1380 {
1381 assert(compmask);
1382 struct ir3_instruction *sysval = create_input(ctx, compmask);
1383 add_sysval_input_compmask(ctx, slot, compmask, sysval);
1384 return sysval;
1385 }
1386
1387 static struct ir3_instruction *
1388 get_barycentric_centroid(struct ir3_context *ctx)
1389 {
1390 if (!ctx->ij_centroid) {
1391 struct ir3_instruction *xy[2];
1392 struct ir3_instruction *ij;
1393
1394 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID, 0x3);
1395 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1396
1397 ctx->ij_centroid = ir3_create_collect(ctx, xy, 2);
1398 }
1399
1400 return ctx->ij_centroid;
1401 }
1402
1403 static struct ir3_instruction *
1404 get_barycentric_sample(struct ir3_context *ctx)
1405 {
1406 if (!ctx->ij_sample) {
1407 struct ir3_instruction *xy[2];
1408 struct ir3_instruction *ij;
1409
1410 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE, 0x3);
1411 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1412
1413 ctx->ij_sample = ir3_create_collect(ctx, xy, 2);
1414 }
1415
1416 return ctx->ij_sample;
1417 }
1418
1419 static struct ir3_instruction *
1420 get_barycentric_pixel(struct ir3_context *ctx)
1421 {
1422 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1423 * this to create ij_pixel only on demand:
1424 */
1425 return ctx->ij_pixel;
1426 }
1427
1428 static struct ir3_instruction *
1429 get_frag_coord(struct ir3_context *ctx)
1430 {
1431 if (!ctx->frag_coord) {
1432 struct ir3_block *b = ctx->in_block;
1433 struct ir3_instruction *xyzw[4];
1434 struct ir3_instruction *hw_frag_coord;
1435
1436 hw_frag_coord = create_sysval_input(ctx, SYSTEM_VALUE_FRAG_COORD, 0xf);
1437 ir3_split_dest(b, xyzw, hw_frag_coord, 0, 4);
1438
1439 /* for frag_coord.xy, we get unsigned values.. we need
1440 * to subtract (integer) 8 and divide by 16 (right-
1441 * shift by 4) then convert to float:
1442 *
1443 * sub.s tmp, src, 8
1444 * shr.b tmp, tmp, 4
1445 * mov.u32f32 dst, tmp
1446 *
1447 */
1448 for (int i = 0; i < 2; i++) {
1449 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1450 xyzw[i] = ir3_MUL_F(b, xyzw[i], 0, create_immed(b, fui(1.0 / 16.0)), 0);
1451 }
1452
1453 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1454 ctx->so->frag_coord = true;
1455 }
1456
1457 return ctx->frag_coord;
1458 }
1459
1460 static void
1461 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1462 {
1463 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1464 struct ir3_instruction **dst;
1465 struct ir3_instruction * const *src;
1466 struct ir3_block *b = ctx->block;
1467 int idx, comp;
1468
1469 if (info->has_dest) {
1470 unsigned n = nir_intrinsic_dest_components(intr);
1471 dst = ir3_get_dst(ctx, &intr->dest, n);
1472 } else {
1473 dst = NULL;
1474 }
1475
1476 const unsigned primitive_param = ctx->so->shader->const_state.offsets.primitive_param * 4;
1477 const unsigned primitive_map = ctx->so->shader->const_state.offsets.primitive_map * 4;
1478
1479 switch (intr->intrinsic) {
1480 case nir_intrinsic_load_uniform:
1481 idx = nir_intrinsic_base(intr);
1482 if (nir_src_is_const(intr->src[0])) {
1483 idx += nir_src_as_uint(intr->src[0]);
1484 for (int i = 0; i < intr->num_components; i++) {
1485 dst[i] = create_uniform_typed(b, idx + i,
1486 nir_dest_bit_size(intr->dest) < 32 ? TYPE_F16 : TYPE_F32);
1487 }
1488 } else {
1489 src = ir3_get_src(ctx, &intr->src[0]);
1490 for (int i = 0; i < intr->num_components; i++) {
1491 dst[i] = create_uniform_indirect(b, idx + i,
1492 ir3_get_addr0(ctx, src[0], 1));
1493 }
1494 /* NOTE: if relative addressing is used, we set
1495 * constlen in the compiler (to worst-case value)
1496 * since we don't know in the assembler what the max
1497 * addr reg value can be:
1498 */
1499 ctx->so->constlen = MAX2(ctx->so->constlen,
1500 ctx->so->shader->ubo_state.size / 16);
1501 }
1502 break;
1503
1504 case nir_intrinsic_load_vs_primitive_stride_ir3:
1505 dst[0] = create_uniform(b, primitive_param + 0);
1506 break;
1507 case nir_intrinsic_load_vs_vertex_stride_ir3:
1508 dst[0] = create_uniform(b, primitive_param + 1);
1509 break;
1510 case nir_intrinsic_load_hs_patch_stride_ir3:
1511 dst[0] = create_uniform(b, primitive_param + 2);
1512 break;
1513 case nir_intrinsic_load_patch_vertices_in:
1514 dst[0] = create_uniform(b, primitive_param + 3);
1515 break;
1516 case nir_intrinsic_load_tess_param_base_ir3:
1517 dst[0] = create_uniform(b, primitive_param + 4);
1518 dst[1] = create_uniform(b, primitive_param + 5);
1519 break;
1520 case nir_intrinsic_load_tess_factor_base_ir3:
1521 dst[0] = create_uniform(b, primitive_param + 6);
1522 dst[1] = create_uniform(b, primitive_param + 7);
1523 break;
1524
1525 case nir_intrinsic_load_primitive_location_ir3:
1526 idx = nir_intrinsic_driver_location(intr);
1527 dst[0] = create_uniform(b, primitive_map + idx);
1528 break;
1529
1530 case nir_intrinsic_load_gs_header_ir3:
1531 dst[0] = ctx->gs_header;
1532 break;
1533 case nir_intrinsic_load_tcs_header_ir3:
1534 dst[0] = ctx->tcs_header;
1535 break;
1536
1537 case nir_intrinsic_load_primitive_id:
1538 dst[0] = ctx->primitive_id;
1539 break;
1540
1541 case nir_intrinsic_load_tess_coord:
1542 if (!ctx->tess_coord) {
1543 ctx->tess_coord =
1544 create_sysval_input(ctx, SYSTEM_VALUE_TESS_COORD, 0x3);
1545 }
1546 ir3_split_dest(b, dst, ctx->tess_coord, 0, 2);
1547
1548 /* Unused, but ir3_put_dst() below wants to free something */
1549 dst[2] = create_immed(b, 0);
1550 break;
1551
1552 case nir_intrinsic_end_patch_ir3:
1553 assert(ctx->so->type == MESA_SHADER_TESS_CTRL);
1554 struct ir3_instruction *end = ir3_ENDIF(b);
1555 array_insert(b, b->keeps, end);
1556
1557 end->barrier_class = IR3_BARRIER_EVERYTHING;
1558 end->barrier_conflict = IR3_BARRIER_EVERYTHING;
1559 break;
1560
1561 case nir_intrinsic_store_global_ir3: {
1562 struct ir3_instruction *value, *addr, *offset;
1563
1564 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1565 ir3_get_src(ctx, &intr->src[1])[0],
1566 ir3_get_src(ctx, &intr->src[1])[1]
1567 }, 2);
1568
1569 offset = ir3_get_src(ctx, &intr->src[2])[0];
1570
1571 value = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]),
1572 intr->num_components);
1573
1574 struct ir3_instruction *stg =
1575 ir3_STG_G(ctx->block, addr, 0, value, 0,
1576 create_immed(ctx->block, intr->num_components), 0, offset, 0);
1577 stg->cat6.type = TYPE_U32;
1578 stg->cat6.iim_val = 1;
1579
1580 array_insert(b, b->keeps, stg);
1581
1582 stg->barrier_class = IR3_BARRIER_BUFFER_W;
1583 stg->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1584 break;
1585 }
1586
1587 case nir_intrinsic_load_global_ir3: {
1588 struct ir3_instruction *addr, *offset;
1589
1590 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1591 ir3_get_src(ctx, &intr->src[0])[0],
1592 ir3_get_src(ctx, &intr->src[0])[1]
1593 }, 2);
1594
1595 offset = ir3_get_src(ctx, &intr->src[1])[0];
1596
1597 struct ir3_instruction *load =
1598 ir3_LDG(b, addr, 0, create_immed(ctx->block, intr->num_components),
1599 0, offset, 0);
1600 load->cat6.type = TYPE_U32;
1601 load->regs[0]->wrmask = MASK(intr->num_components);
1602
1603 load->barrier_class = IR3_BARRIER_BUFFER_R;
1604 load->barrier_conflict = IR3_BARRIER_BUFFER_W;
1605
1606 ir3_split_dest(b, dst, load, 0, intr->num_components);
1607 break;
1608 }
1609
1610 case nir_intrinsic_load_ubo:
1611 emit_intrinsic_load_ubo(ctx, intr, dst);
1612 break;
1613 case nir_intrinsic_load_ubo_ir3:
1614 emit_intrinsic_load_ubo_ldc(ctx, intr, dst);
1615 break;
1616 case nir_intrinsic_load_frag_coord:
1617 ir3_split_dest(b, dst, get_frag_coord(ctx), 0, 4);
1618 break;
1619 case nir_intrinsic_load_sample_pos_from_id: {
1620 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1621 * but that doesn't seem necessary.
1622 */
1623 struct ir3_instruction *offset =
1624 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1625 offset->regs[0]->wrmask = 0x3;
1626 offset->cat5.type = TYPE_F32;
1627
1628 ir3_split_dest(b, dst, offset, 0, 2);
1629
1630 break;
1631 }
1632 case nir_intrinsic_load_size_ir3:
1633 if (!ctx->ij_size) {
1634 ctx->ij_size =
1635 create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE, 0x1);
1636 }
1637 dst[0] = ctx->ij_size;
1638 break;
1639 case nir_intrinsic_load_barycentric_centroid:
1640 ir3_split_dest(b, dst, get_barycentric_centroid(ctx), 0, 2);
1641 break;
1642 case nir_intrinsic_load_barycentric_sample:
1643 if (ctx->so->key.msaa) {
1644 ir3_split_dest(b, dst, get_barycentric_sample(ctx), 0, 2);
1645 } else {
1646 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1647 }
1648 break;
1649 case nir_intrinsic_load_barycentric_pixel:
1650 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1651 break;
1652 case nir_intrinsic_load_interpolated_input:
1653 idx = nir_intrinsic_base(intr);
1654 comp = nir_intrinsic_component(intr);
1655 src = ir3_get_src(ctx, &intr->src[0]);
1656 if (nir_src_is_const(intr->src[1])) {
1657 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1658 idx += nir_src_as_uint(intr->src[1]);
1659 for (int i = 0; i < intr->num_components; i++) {
1660 unsigned inloc = idx * 4 + i + comp;
1661 if (ctx->so->inputs[idx].bary &&
1662 !ctx->so->inputs[idx].use_ldlv) {
1663 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1664 } else {
1665 /* for non-varyings use the pre-setup input, since
1666 * that is easier than mapping things back to a
1667 * nir_variable to figure out what it is.
1668 */
1669 dst[i] = ctx->inputs[inloc];
1670 compile_assert(ctx, dst[i]);
1671 }
1672 }
1673 } else {
1674 ir3_context_error(ctx, "unhandled");
1675 }
1676 break;
1677 case nir_intrinsic_load_input:
1678 idx = nir_intrinsic_base(intr);
1679 comp = nir_intrinsic_component(intr);
1680 if (nir_src_is_const(intr->src[0])) {
1681 idx += nir_src_as_uint(intr->src[0]);
1682 for (int i = 0; i < intr->num_components; i++) {
1683 unsigned n = idx * 4 + i + comp;
1684 dst[i] = ctx->inputs[n];
1685 compile_assert(ctx, ctx->inputs[n]);
1686 }
1687 } else {
1688 src = ir3_get_src(ctx, &intr->src[0]);
1689 struct ir3_instruction *collect =
1690 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ninputs);
1691 struct ir3_instruction *addr = ir3_get_addr0(ctx, src[0], 4);
1692 for (int i = 0; i < intr->num_components; i++) {
1693 unsigned n = idx * 4 + i + comp;
1694 dst[i] = create_indirect_load(ctx, ctx->ninputs,
1695 n, addr, collect);
1696 }
1697 }
1698 break;
1699 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1700 * pass and replaced by an ir3-specifc version that adds the
1701 * dword-offset in the last source.
1702 */
1703 case nir_intrinsic_load_ssbo_ir3:
1704 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1705 break;
1706 case nir_intrinsic_store_ssbo_ir3:
1707 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1708 !ctx->s->info.fs.early_fragment_tests)
1709 ctx->so->no_earlyz = true;
1710 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1711 break;
1712 case nir_intrinsic_get_buffer_size:
1713 emit_intrinsic_ssbo_size(ctx, intr, dst);
1714 break;
1715 case nir_intrinsic_ssbo_atomic_add_ir3:
1716 case nir_intrinsic_ssbo_atomic_imin_ir3:
1717 case nir_intrinsic_ssbo_atomic_umin_ir3:
1718 case nir_intrinsic_ssbo_atomic_imax_ir3:
1719 case nir_intrinsic_ssbo_atomic_umax_ir3:
1720 case nir_intrinsic_ssbo_atomic_and_ir3:
1721 case nir_intrinsic_ssbo_atomic_or_ir3:
1722 case nir_intrinsic_ssbo_atomic_xor_ir3:
1723 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1724 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1725 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1726 !ctx->s->info.fs.early_fragment_tests)
1727 ctx->so->no_earlyz = true;
1728 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1729 break;
1730 case nir_intrinsic_load_shared:
1731 emit_intrinsic_load_shared(ctx, intr, dst);
1732 break;
1733 case nir_intrinsic_store_shared:
1734 emit_intrinsic_store_shared(ctx, intr);
1735 break;
1736 case nir_intrinsic_shared_atomic_add:
1737 case nir_intrinsic_shared_atomic_imin:
1738 case nir_intrinsic_shared_atomic_umin:
1739 case nir_intrinsic_shared_atomic_imax:
1740 case nir_intrinsic_shared_atomic_umax:
1741 case nir_intrinsic_shared_atomic_and:
1742 case nir_intrinsic_shared_atomic_or:
1743 case nir_intrinsic_shared_atomic_xor:
1744 case nir_intrinsic_shared_atomic_exchange:
1745 case nir_intrinsic_shared_atomic_comp_swap:
1746 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1747 break;
1748 case nir_intrinsic_image_load:
1749 emit_intrinsic_load_image(ctx, intr, dst);
1750 break;
1751 case nir_intrinsic_bindless_image_load:
1752 /* Bindless uses the IBO state, which doesn't have swizzle filled out,
1753 * so using isam doesn't work.
1754 *
1755 * TODO: can we use isam if we fill out more fields?
1756 */
1757 ctx->funcs->emit_intrinsic_load_image(ctx, intr, dst);
1758 break;
1759 case nir_intrinsic_image_store:
1760 case nir_intrinsic_bindless_image_store:
1761 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1762 !ctx->s->info.fs.early_fragment_tests)
1763 ctx->so->no_earlyz = true;
1764 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1765 break;
1766 case nir_intrinsic_image_size:
1767 case nir_intrinsic_bindless_image_size:
1768 emit_intrinsic_image_size(ctx, intr, dst);
1769 break;
1770 case nir_intrinsic_image_atomic_add:
1771 case nir_intrinsic_bindless_image_atomic_add:
1772 case nir_intrinsic_image_atomic_imin:
1773 case nir_intrinsic_bindless_image_atomic_imin:
1774 case nir_intrinsic_image_atomic_umin:
1775 case nir_intrinsic_bindless_image_atomic_umin:
1776 case nir_intrinsic_image_atomic_imax:
1777 case nir_intrinsic_bindless_image_atomic_imax:
1778 case nir_intrinsic_image_atomic_umax:
1779 case nir_intrinsic_bindless_image_atomic_umax:
1780 case nir_intrinsic_image_atomic_and:
1781 case nir_intrinsic_bindless_image_atomic_and:
1782 case nir_intrinsic_image_atomic_or:
1783 case nir_intrinsic_bindless_image_atomic_or:
1784 case nir_intrinsic_image_atomic_xor:
1785 case nir_intrinsic_bindless_image_atomic_xor:
1786 case nir_intrinsic_image_atomic_exchange:
1787 case nir_intrinsic_bindless_image_atomic_exchange:
1788 case nir_intrinsic_image_atomic_comp_swap:
1789 case nir_intrinsic_bindless_image_atomic_comp_swap:
1790 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1791 !ctx->s->info.fs.early_fragment_tests)
1792 ctx->so->no_earlyz = true;
1793 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1794 break;
1795 case nir_intrinsic_control_barrier:
1796 case nir_intrinsic_memory_barrier:
1797 case nir_intrinsic_group_memory_barrier:
1798 case nir_intrinsic_memory_barrier_buffer:
1799 case nir_intrinsic_memory_barrier_image:
1800 case nir_intrinsic_memory_barrier_shared:
1801 emit_intrinsic_barrier(ctx, intr);
1802 /* note that blk ptr no longer valid, make that obvious: */
1803 b = NULL;
1804 break;
1805 case nir_intrinsic_store_output:
1806 idx = nir_intrinsic_base(intr);
1807 comp = nir_intrinsic_component(intr);
1808 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1809 idx += nir_src_as_uint(intr->src[1]);
1810
1811 src = ir3_get_src(ctx, &intr->src[0]);
1812 for (int i = 0; i < intr->num_components; i++) {
1813 unsigned n = idx * 4 + i + comp;
1814 ctx->outputs[n] = src[i];
1815 }
1816 break;
1817 case nir_intrinsic_load_base_vertex:
1818 case nir_intrinsic_load_first_vertex:
1819 if (!ctx->basevertex) {
1820 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1821 }
1822 dst[0] = ctx->basevertex;
1823 break;
1824 case nir_intrinsic_load_base_instance:
1825 if (!ctx->base_instance) {
1826 ctx->base_instance = create_driver_param(ctx, IR3_DP_INSTID_BASE);
1827 }
1828 dst[0] = ctx->base_instance;
1829 break;
1830 case nir_intrinsic_load_vertex_id_zero_base:
1831 case nir_intrinsic_load_vertex_id:
1832 if (!ctx->vertex_id) {
1833 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1834 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1835 ctx->vertex_id = create_sysval_input(ctx, sv, 0x1);
1836 }
1837 dst[0] = ctx->vertex_id;
1838 break;
1839 case nir_intrinsic_load_instance_id:
1840 if (!ctx->instance_id) {
1841 ctx->instance_id = create_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID, 0x1);
1842 }
1843 dst[0] = ctx->instance_id;
1844 break;
1845 case nir_intrinsic_load_sample_id:
1846 ctx->so->per_samp = true;
1847 /* fall-thru */
1848 case nir_intrinsic_load_sample_id_no_per_sample:
1849 if (!ctx->samp_id) {
1850 ctx->samp_id = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID, 0x1);
1851 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1852 }
1853 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1854 break;
1855 case nir_intrinsic_load_sample_mask_in:
1856 if (!ctx->samp_mask_in) {
1857 ctx->samp_mask_in = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN, 0x1);
1858 }
1859 dst[0] = ctx->samp_mask_in;
1860 break;
1861 case nir_intrinsic_load_user_clip_plane:
1862 idx = nir_intrinsic_ucp_id(intr);
1863 for (int i = 0; i < intr->num_components; i++) {
1864 unsigned n = idx * 4 + i;
1865 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1866 }
1867 break;
1868 case nir_intrinsic_load_front_face:
1869 if (!ctx->frag_face) {
1870 ctx->so->frag_face = true;
1871 ctx->frag_face = create_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, 0x1);
1872 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1873 }
1874 /* for fragface, we get -1 for back and 0 for front. However this is
1875 * the inverse of what nir expects (where ~0 is true).
1876 */
1877 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1878 dst[0] = ir3_NOT_B(b, dst[0], 0);
1879 break;
1880 case nir_intrinsic_load_local_invocation_id:
1881 if (!ctx->local_invocation_id) {
1882 ctx->local_invocation_id =
1883 create_sysval_input(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID, 0x7);
1884 }
1885 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1886 break;
1887 case nir_intrinsic_load_work_group_id:
1888 if (!ctx->work_group_id) {
1889 ctx->work_group_id =
1890 create_sysval_input(ctx, SYSTEM_VALUE_WORK_GROUP_ID, 0x7);
1891 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1892 }
1893 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1894 break;
1895 case nir_intrinsic_load_num_work_groups:
1896 for (int i = 0; i < intr->num_components; i++) {
1897 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1898 }
1899 break;
1900 case nir_intrinsic_load_local_group_size:
1901 for (int i = 0; i < intr->num_components; i++) {
1902 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1903 }
1904 break;
1905 case nir_intrinsic_discard_if:
1906 case nir_intrinsic_discard: {
1907 struct ir3_instruction *cond, *kill;
1908
1909 if (intr->intrinsic == nir_intrinsic_discard_if) {
1910 /* conditional discard: */
1911 src = ir3_get_src(ctx, &intr->src[0]);
1912 cond = ir3_b2n(b, src[0]);
1913 } else {
1914 /* unconditional discard: */
1915 cond = create_immed(b, 1);
1916 }
1917
1918 /* NOTE: only cmps.*.* can write p0.x: */
1919 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1920 cond->cat2.condition = IR3_COND_NE;
1921
1922 /* condition always goes in predicate register: */
1923 cond->regs[0]->num = regid(REG_P0, 0);
1924 cond->regs[0]->flags &= ~IR3_REG_SSA;
1925
1926 kill = ir3_KILL(b, cond, 0);
1927 kill->regs[1]->num = regid(REG_P0, 0);
1928 array_insert(ctx->ir, ctx->ir->predicates, kill);
1929
1930 array_insert(b, b->keeps, kill);
1931 ctx->so->no_earlyz = true;
1932
1933 break;
1934 }
1935
1936 case nir_intrinsic_cond_end_ir3: {
1937 struct ir3_instruction *cond, *kill;
1938
1939 src = ir3_get_src(ctx, &intr->src[0]);
1940 cond = ir3_b2n(b, src[0]);
1941
1942 /* NOTE: only cmps.*.* can write p0.x: */
1943 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1944 cond->cat2.condition = IR3_COND_NE;
1945
1946 /* condition always goes in predicate register: */
1947 cond->regs[0]->num = regid(REG_P0, 0);
1948
1949 kill = ir3_IF(b, cond, 0);
1950
1951 kill->barrier_class = IR3_BARRIER_EVERYTHING;
1952 kill->barrier_conflict = IR3_BARRIER_EVERYTHING;
1953
1954 array_insert(ctx->ir, ctx->ir->predicates, kill);
1955 array_insert(b, b->keeps, kill);
1956 break;
1957 }
1958
1959 case nir_intrinsic_load_shared_ir3:
1960 emit_intrinsic_load_shared_ir3(ctx, intr, dst);
1961 break;
1962 case nir_intrinsic_store_shared_ir3:
1963 emit_intrinsic_store_shared_ir3(ctx, intr);
1964 break;
1965 case nir_intrinsic_bindless_resource_ir3:
1966 dst[0] = ir3_get_src(ctx, &intr->src[0])[0];
1967 break;
1968 default:
1969 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1970 nir_intrinsic_infos[intr->intrinsic].name);
1971 break;
1972 }
1973
1974 if (info->has_dest)
1975 ir3_put_dst(ctx, &intr->dest);
1976 }
1977
1978 static void
1979 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1980 {
1981 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1982 instr->def.num_components);
1983
1984 if (instr->def.bit_size < 32) {
1985 for (int i = 0; i < instr->def.num_components; i++)
1986 dst[i] = create_immed_typed(ctx->block,
1987 instr->value[i].u16,
1988 TYPE_U16);
1989 } else {
1990 for (int i = 0; i < instr->def.num_components; i++)
1991 dst[i] = create_immed_typed(ctx->block,
1992 instr->value[i].u32,
1993 TYPE_U32);
1994 }
1995
1996 }
1997
1998 static void
1999 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
2000 {
2001 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
2002 undef->def.num_components);
2003 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
2004
2005 /* backend doesn't want undefined instructions, so just plug
2006 * in 0.0..
2007 */
2008 for (int i = 0; i < undef->def.num_components; i++)
2009 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
2010 }
2011
2012 /*
2013 * texture fetch/sample instructions:
2014 */
2015
2016 static type_t
2017 get_tex_dest_type(nir_tex_instr *tex)
2018 {
2019 type_t type;
2020
2021 switch (nir_alu_type_get_base_type(tex->dest_type)) {
2022 case nir_type_invalid:
2023 case nir_type_float:
2024 type = nir_dest_bit_size(tex->dest) < 32 ? TYPE_F16 : TYPE_F32;
2025 break;
2026 case nir_type_int:
2027 type = nir_dest_bit_size(tex->dest) < 32 ? TYPE_S16 : TYPE_S32;
2028 break;
2029 case nir_type_uint:
2030 case nir_type_bool:
2031 type = nir_dest_bit_size(tex->dest) < 32 ? TYPE_U16 : TYPE_U32;
2032 break;
2033 default:
2034 unreachable("bad dest_type");
2035 }
2036
2037 return type;
2038 }
2039
2040 static void
2041 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
2042 {
2043 unsigned coords = glsl_get_sampler_dim_coordinate_components(tex->sampler_dim);
2044 unsigned flags = 0;
2045
2046 /* note: would use tex->coord_components.. except txs.. also,
2047 * since array index goes after shadow ref, we don't want to
2048 * count it:
2049 */
2050 if (coords == 3)
2051 flags |= IR3_INSTR_3D;
2052
2053 if (tex->is_shadow && tex->op != nir_texop_lod)
2054 flags |= IR3_INSTR_S;
2055
2056 if (tex->is_array && tex->op != nir_texop_lod)
2057 flags |= IR3_INSTR_A;
2058
2059 *flagsp = flags;
2060 *coordsp = coords;
2061 }
2062
2063 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
2064 * or immediate (in which case it will get lowered later to a non .s2en
2065 * version of the tex instruction which encode tex/samp as immediates:
2066 */
2067 static struct tex_src_info
2068 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
2069 {
2070 struct ir3_block *b = ctx->block;
2071 struct tex_src_info info = { 0 };
2072 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_handle);
2073 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_handle);
2074 struct ir3_instruction *texture, *sampler;
2075
2076 if (texture_idx >= 0 || sampler_idx >= 0) {
2077 /* Bindless case */
2078 info.flags |= IR3_INSTR_B;
2079
2080 /* Gather information required to determine which encoding to
2081 * choose as well as for prefetch.
2082 */
2083 nir_intrinsic_instr *bindless_tex = NULL;
2084 bool tex_const;
2085 if (texture_idx >= 0) {
2086 ctx->so->bindless_tex = true;
2087 bindless_tex = ir3_bindless_resource(tex->src[texture_idx].src);
2088 assert(bindless_tex);
2089 info.tex_base = nir_intrinsic_desc_set(bindless_tex);
2090 tex_const = nir_src_is_const(bindless_tex->src[0]);
2091 if (tex_const)
2092 info.tex_idx = nir_src_as_uint(bindless_tex->src[0]);
2093 } else {
2094 /* To simplify some of the logic below, assume the index is
2095 * constant 0 when it's not enabled.
2096 */
2097 tex_const = true;
2098 info.tex_idx = 0;
2099 }
2100 nir_intrinsic_instr *bindless_samp = NULL;
2101 bool samp_const;
2102 if (sampler_idx >= 0) {
2103 ctx->so->bindless_samp = true;
2104 bindless_samp = ir3_bindless_resource(tex->src[sampler_idx].src);
2105 assert(bindless_samp);
2106 info.samp_base = nir_intrinsic_desc_set(bindless_samp);
2107 samp_const = nir_src_is_const(bindless_samp->src[0]);
2108 if (samp_const)
2109 info.samp_idx = nir_src_as_uint(bindless_samp->src[0]);
2110 } else {
2111 samp_const = true;
2112 info.samp_idx = 0;
2113 }
2114
2115 /* Choose encoding. */
2116 if (tex_const && samp_const && info.tex_idx < 256 && info.samp_idx < 256) {
2117 if (info.tex_idx < 16 && info.samp_idx < 16 &&
2118 (!bindless_tex || !bindless_samp || info.tex_base == info.samp_base)) {
2119 /* Everything fits within the instruction */
2120 info.base = info.tex_base;
2121 info.combined_idx = info.samp_idx | (info.tex_idx << 4);
2122 } else {
2123 info.base = info.tex_base;
2124 info.a1_val = info.tex_idx << 3 | info.samp_base;
2125 info.combined_idx = info.samp_idx;
2126 info.flags |= IR3_INSTR_A1EN;
2127 }
2128 info.samp_tex = NULL;
2129 } else {
2130 info.flags |= IR3_INSTR_S2EN;
2131 /* In the indirect case, we only use a1.x to store the sampler
2132 * base if it differs from the texture base.
2133 */
2134 if (!bindless_tex || !bindless_samp || info.tex_base == info.samp_base) {
2135 info.base = info.tex_base;
2136 } else {
2137 info.base = info.tex_base;
2138 info.a1_val = info.samp_base;
2139 info.flags |= IR3_INSTR_A1EN;
2140 }
2141
2142 /* Note: the indirect source is now a vec2 instead of hvec2, and
2143 * for some reason the texture and sampler are swapped.
2144 */
2145 struct ir3_instruction *texture, *sampler;
2146
2147 if (bindless_tex) {
2148 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
2149 } else {
2150 texture = create_immed(b, 0);
2151 }
2152
2153 if (bindless_samp) {
2154 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
2155 } else {
2156 sampler = create_immed(b, 0);
2157 }
2158 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2159 texture,
2160 sampler,
2161 }, 2);
2162 }
2163 } else {
2164 info.flags |= IR3_INSTR_S2EN;
2165 texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
2166 sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
2167 if (texture_idx >= 0) {
2168 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
2169 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
2170 } else {
2171 /* TODO what to do for dynamic case? I guess we only need the
2172 * max index for astc srgb workaround so maybe not a problem
2173 * to worry about if we don't enable indirect samplers for
2174 * a4xx?
2175 */
2176 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
2177 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
2178 info.tex_idx = tex->texture_index;
2179 }
2180
2181 if (sampler_idx >= 0) {
2182 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
2183 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
2184 } else {
2185 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
2186 info.samp_idx = tex->texture_index;
2187 }
2188
2189 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2190 sampler,
2191 texture,
2192 }, 2);
2193 }
2194
2195 return info;
2196 }
2197
2198 static void
2199 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
2200 {
2201 struct ir3_block *b = ctx->block;
2202 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
2203 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
2204 struct ir3_instruction *lod, *compare, *proj, *sample_index;
2205 struct tex_src_info info = { 0 };
2206 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
2207 unsigned i, coords, flags, ncomp;
2208 unsigned nsrc0 = 0, nsrc1 = 0;
2209 type_t type;
2210 opc_t opc = 0;
2211
2212 ncomp = nir_dest_num_components(tex->dest);
2213
2214 coord = off = ddx = ddy = NULL;
2215 lod = proj = compare = sample_index = NULL;
2216
2217 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
2218
2219 for (unsigned i = 0; i < tex->num_srcs; i++) {
2220 switch (tex->src[i].src_type) {
2221 case nir_tex_src_coord:
2222 coord = ir3_get_src(ctx, &tex->src[i].src);
2223 break;
2224 case nir_tex_src_bias:
2225 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
2226 has_bias = true;
2227 break;
2228 case nir_tex_src_lod:
2229 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
2230 has_lod = true;
2231 break;
2232 case nir_tex_src_comparator: /* shadow comparator */
2233 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
2234 break;
2235 case nir_tex_src_projector:
2236 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
2237 has_proj = true;
2238 break;
2239 case nir_tex_src_offset:
2240 off = ir3_get_src(ctx, &tex->src[i].src);
2241 has_off = true;
2242 break;
2243 case nir_tex_src_ddx:
2244 ddx = ir3_get_src(ctx, &tex->src[i].src);
2245 break;
2246 case nir_tex_src_ddy:
2247 ddy = ir3_get_src(ctx, &tex->src[i].src);
2248 break;
2249 case nir_tex_src_ms_index:
2250 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
2251 break;
2252 case nir_tex_src_texture_offset:
2253 case nir_tex_src_sampler_offset:
2254 case nir_tex_src_texture_handle:
2255 case nir_tex_src_sampler_handle:
2256 /* handled in get_tex_samp_src() */
2257 break;
2258 default:
2259 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
2260 tex->src[i].src_type);
2261 return;
2262 }
2263 }
2264
2265 switch (tex->op) {
2266 case nir_texop_tex_prefetch:
2267 compile_assert(ctx, !has_bias);
2268 compile_assert(ctx, !has_lod);
2269 compile_assert(ctx, !compare);
2270 compile_assert(ctx, !has_proj);
2271 compile_assert(ctx, !has_off);
2272 compile_assert(ctx, !ddx);
2273 compile_assert(ctx, !ddy);
2274 compile_assert(ctx, !sample_index);
2275 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_texture_offset) < 0);
2276 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset) < 0);
2277
2278 if (ctx->so->num_sampler_prefetch < IR3_MAX_SAMPLER_PREFETCH) {
2279 opc = OPC_META_TEX_PREFETCH;
2280 ctx->so->num_sampler_prefetch++;
2281 break;
2282 }
2283 /* fallthru */
2284 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
2285 case nir_texop_txb: opc = OPC_SAMB; break;
2286 case nir_texop_txl: opc = OPC_SAML; break;
2287 case nir_texop_txd: opc = OPC_SAMGQ; break;
2288 case nir_texop_txf: opc = OPC_ISAML; break;
2289 case nir_texop_lod: opc = OPC_GETLOD; break;
2290 case nir_texop_tg4:
2291 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2292 * what blob does, seems gather is broken?), and a3xx did
2293 * not support it (but probably could also emulate).
2294 */
2295 switch (tex->component) {
2296 case 0: opc = OPC_GATHER4R; break;
2297 case 1: opc = OPC_GATHER4G; break;
2298 case 2: opc = OPC_GATHER4B; break;
2299 case 3: opc = OPC_GATHER4A; break;
2300 }
2301 break;
2302 case nir_texop_txf_ms_fb:
2303 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
2304 default:
2305 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
2306 return;
2307 }
2308
2309 tex_info(tex, &flags, &coords);
2310
2311 /*
2312 * lay out the first argument in the proper order:
2313 * - actual coordinates first
2314 * - shadow reference
2315 * - array index
2316 * - projection w
2317 * - starting at offset 4, dpdx.xy, dpdy.xy
2318 *
2319 * bias/lod go into the second arg
2320 */
2321
2322 /* insert tex coords: */
2323 for (i = 0; i < coords; i++)
2324 src0[i] = coord[i];
2325
2326 nsrc0 = i;
2327
2328 /* scale up integer coords for TXF based on the LOD */
2329 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
2330 assert(has_lod);
2331 for (i = 0; i < coords; i++)
2332 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
2333 }
2334
2335 if (coords == 1) {
2336 /* hw doesn't do 1d, so we treat it as 2d with
2337 * height of 1, and patch up the y coord.
2338 */
2339 if (is_isam(opc)) {
2340 src0[nsrc0++] = create_immed(b, 0);
2341 } else {
2342 src0[nsrc0++] = create_immed(b, fui(0.5));
2343 }
2344 }
2345
2346 if (tex->is_shadow && tex->op != nir_texop_lod)
2347 src0[nsrc0++] = compare;
2348
2349 if (tex->is_array && tex->op != nir_texop_lod) {
2350 struct ir3_instruction *idx = coord[coords];
2351
2352 /* the array coord for cube arrays needs 0.5 added to it */
2353 if (ctx->compiler->array_index_add_half && !is_isam(opc))
2354 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
2355
2356 src0[nsrc0++] = idx;
2357 }
2358
2359 if (has_proj) {
2360 src0[nsrc0++] = proj;
2361 flags |= IR3_INSTR_P;
2362 }
2363
2364 /* pad to 4, then ddx/ddy: */
2365 if (tex->op == nir_texop_txd) {
2366 while (nsrc0 < 4)
2367 src0[nsrc0++] = create_immed(b, fui(0.0));
2368 for (i = 0; i < coords; i++)
2369 src0[nsrc0++] = ddx[i];
2370 if (coords < 2)
2371 src0[nsrc0++] = create_immed(b, fui(0.0));
2372 for (i = 0; i < coords; i++)
2373 src0[nsrc0++] = ddy[i];
2374 if (coords < 2)
2375 src0[nsrc0++] = create_immed(b, fui(0.0));
2376 }
2377
2378 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2379 * with scaled x coord according to requested sample:
2380 */
2381 if (opc == OPC_ISAMM) {
2382 if (ctx->compiler->txf_ms_with_isaml) {
2383 /* the samples are laid out in x dimension as
2384 * 0 1 2 3
2385 * x_ms = (x << ms) + sample_index;
2386 */
2387 struct ir3_instruction *ms;
2388 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
2389
2390 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
2391 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
2392
2393 opc = OPC_ISAML;
2394 } else {
2395 src0[nsrc0++] = sample_index;
2396 }
2397 }
2398
2399 /*
2400 * second argument (if applicable):
2401 * - offsets
2402 * - lod
2403 * - bias
2404 */
2405 if (has_off | has_lod | has_bias) {
2406 if (has_off) {
2407 unsigned off_coords = coords;
2408 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2409 off_coords--;
2410 for (i = 0; i < off_coords; i++)
2411 src1[nsrc1++] = off[i];
2412 if (off_coords < 2)
2413 src1[nsrc1++] = create_immed(b, fui(0.0));
2414 flags |= IR3_INSTR_O;
2415 }
2416
2417 if (has_lod | has_bias)
2418 src1[nsrc1++] = lod;
2419 }
2420
2421 type = get_tex_dest_type(tex);
2422
2423 if (opc == OPC_GETLOD)
2424 type = TYPE_S32;
2425
2426
2427 if (tex->op == nir_texop_txf_ms_fb) {
2428 /* only expect a single txf_ms_fb per shader: */
2429 compile_assert(ctx, !ctx->so->fb_read);
2430 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
2431
2432 ctx->so->fb_read = true;
2433 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2434 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2435 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2436 }, 2);
2437 info.flags = IR3_INSTR_S2EN;
2438
2439 ctx->so->num_samp++;
2440 } else {
2441 info = get_tex_samp_tex_src(ctx, tex);
2442 }
2443
2444 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
2445 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
2446
2447 if (opc == OPC_META_TEX_PREFETCH) {
2448 int idx = nir_tex_instr_src_index(tex, nir_tex_src_coord);
2449
2450 compile_assert(ctx, tex->src[idx].src.is_ssa);
2451
2452 sam = ir3_META_TEX_PREFETCH(b);
2453 __ssa_dst(sam)->wrmask = MASK(ncomp); /* dst */
2454 __ssa_src(sam, get_barycentric_pixel(ctx), 0);
2455 sam->prefetch.input_offset =
2456 ir3_nir_coord_offset(tex->src[idx].src.ssa);
2457 /* make sure not to add irrelevant flags like S2EN */
2458 sam->flags = flags | (info.flags & IR3_INSTR_B);
2459 sam->prefetch.tex = info.tex_idx;
2460 sam->prefetch.samp = info.samp_idx;
2461 sam->prefetch.tex_base = info.tex_base;
2462 sam->prefetch.samp_base = info.samp_base;
2463 } else {
2464 info.flags |= flags;
2465 sam = emit_sam(ctx, opc, info, type, MASK(ncomp), col0, col1);
2466 }
2467
2468 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
2469 assert(opc != OPC_META_TEX_PREFETCH);
2470
2471 /* only need first 3 components: */
2472 sam->regs[0]->wrmask = 0x7;
2473 ir3_split_dest(b, dst, sam, 0, 3);
2474
2475 /* we need to sample the alpha separately with a non-ASTC
2476 * texture state:
2477 */
2478 sam = ir3_SAM(b, opc, type, 0b1000, flags | info.flags,
2479 info.samp_tex, col0, col1);
2480
2481 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
2482
2483 /* fixup .w component: */
2484 ir3_split_dest(b, &dst[3], sam, 3, 1);
2485 } else {
2486 /* normal (non-workaround) case: */
2487 ir3_split_dest(b, dst, sam, 0, ncomp);
2488 }
2489
2490 /* GETLOD returns results in 4.8 fixed point */
2491 if (opc == OPC_GETLOD) {
2492 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
2493
2494 compile_assert(ctx, tex->dest_type == nir_type_float);
2495 for (i = 0; i < 2; i++) {
2496 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_S32, TYPE_F32), 0,
2497 factor, 0);
2498 }
2499 }
2500
2501 ir3_put_dst(ctx, &tex->dest);
2502 }
2503
2504 static void
2505 emit_tex_info(struct ir3_context *ctx, nir_tex_instr *tex, unsigned idx)
2506 {
2507 struct ir3_block *b = ctx->block;
2508 struct ir3_instruction **dst, *sam;
2509 type_t dst_type = get_tex_dest_type(tex);
2510 struct tex_src_info info = get_tex_samp_tex_src(ctx, tex);
2511
2512 dst = ir3_get_dst(ctx, &tex->dest, 1);
2513
2514 sam = emit_sam(ctx, OPC_GETINFO, info, dst_type, 1 << idx, NULL, NULL);
2515
2516 /* even though there is only one component, since it ends
2517 * up in .y/.z/.w rather than .x, we need a split_dest()
2518 */
2519 ir3_split_dest(b, dst, sam, idx, 1);
2520
2521 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2522 * the value in TEX_CONST_0 is zero-based.
2523 */
2524 if (ctx->compiler->levels_add_one)
2525 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2526
2527 ir3_put_dst(ctx, &tex->dest);
2528 }
2529
2530 static void
2531 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2532 {
2533 struct ir3_block *b = ctx->block;
2534 struct ir3_instruction **dst, *sam;
2535 struct ir3_instruction *lod;
2536 unsigned flags, coords;
2537 type_t dst_type = get_tex_dest_type(tex);
2538 struct tex_src_info info = get_tex_samp_tex_src(ctx, tex);
2539
2540 tex_info(tex, &flags, &coords);
2541 info.flags |= flags;
2542
2543 /* Actually we want the number of dimensions, not coordinates. This
2544 * distinction only matters for cubes.
2545 */
2546 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2547 coords = 2;
2548
2549 dst = ir3_get_dst(ctx, &tex->dest, 4);
2550
2551 int lod_idx = nir_tex_instr_src_index(tex, nir_tex_src_lod);
2552 compile_assert(ctx, lod_idx >= 0);
2553
2554 lod = ir3_get_src(ctx, &tex->src[lod_idx].src)[0];
2555
2556 sam = emit_sam(ctx, OPC_GETSIZE, info, dst_type, 0b1111, lod, NULL);
2557 ir3_split_dest(b, dst, sam, 0, 4);
2558
2559 /* Array size actually ends up in .w rather than .z. This doesn't
2560 * matter for miplevel 0, but for higher mips the value in z is
2561 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2562 * returned, which means that we have to add 1 to it for arrays.
2563 */
2564 if (tex->is_array) {
2565 if (ctx->compiler->levels_add_one) {
2566 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2567 } else {
2568 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2569 }
2570 }
2571
2572 ir3_put_dst(ctx, &tex->dest);
2573 }
2574
2575 static void
2576 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2577 {
2578 switch (jump->type) {
2579 case nir_jump_break:
2580 case nir_jump_continue:
2581 case nir_jump_return:
2582 /* I *think* we can simply just ignore this, and use the
2583 * successor block link to figure out where we need to
2584 * jump to for break/continue
2585 */
2586 break;
2587 default:
2588 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2589 break;
2590 }
2591 }
2592
2593 static void
2594 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2595 {
2596 switch (instr->type) {
2597 case nir_instr_type_alu:
2598 emit_alu(ctx, nir_instr_as_alu(instr));
2599 break;
2600 case nir_instr_type_deref:
2601 /* ignored, handled as part of the intrinsic they are src to */
2602 break;
2603 case nir_instr_type_intrinsic:
2604 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2605 break;
2606 case nir_instr_type_load_const:
2607 emit_load_const(ctx, nir_instr_as_load_const(instr));
2608 break;
2609 case nir_instr_type_ssa_undef:
2610 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2611 break;
2612 case nir_instr_type_tex: {
2613 nir_tex_instr *tex = nir_instr_as_tex(instr);
2614 /* couple tex instructions get special-cased:
2615 */
2616 switch (tex->op) {
2617 case nir_texop_txs:
2618 emit_tex_txs(ctx, tex);
2619 break;
2620 case nir_texop_query_levels:
2621 emit_tex_info(ctx, tex, 2);
2622 break;
2623 case nir_texop_texture_samples:
2624 emit_tex_info(ctx, tex, 3);
2625 break;
2626 default:
2627 emit_tex(ctx, tex);
2628 break;
2629 }
2630 break;
2631 }
2632 case nir_instr_type_jump:
2633 emit_jump(ctx, nir_instr_as_jump(instr));
2634 break;
2635 case nir_instr_type_phi:
2636 /* we have converted phi webs to regs in NIR by now */
2637 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2638 break;
2639 case nir_instr_type_call:
2640 case nir_instr_type_parallel_copy:
2641 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2642 break;
2643 }
2644 }
2645
2646 static struct ir3_block *
2647 get_block(struct ir3_context *ctx, const nir_block *nblock)
2648 {
2649 struct ir3_block *block;
2650 struct hash_entry *hentry;
2651
2652 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2653 if (hentry)
2654 return hentry->data;
2655
2656 block = ir3_block_create(ctx->ir);
2657 block->nblock = nblock;
2658 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2659
2660 block->predecessors = _mesa_pointer_set_create(block);
2661 set_foreach(nblock->predecessors, sentry) {
2662 _mesa_set_add(block->predecessors, get_block(ctx, sentry->key));
2663 }
2664
2665 return block;
2666 }
2667
2668 static void
2669 emit_block(struct ir3_context *ctx, nir_block *nblock)
2670 {
2671 struct ir3_block *block = get_block(ctx, nblock);
2672
2673 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2674 if (nblock->successors[i]) {
2675 block->successors[i] =
2676 get_block(ctx, nblock->successors[i]);
2677 }
2678 }
2679
2680 ctx->block = block;
2681 list_addtail(&block->node, &ctx->ir->block_list);
2682
2683 /* re-emit addr register in each block if needed: */
2684 for (int i = 0; i < ARRAY_SIZE(ctx->addr0_ht); i++) {
2685 _mesa_hash_table_destroy(ctx->addr0_ht[i], NULL);
2686 ctx->addr0_ht[i] = NULL;
2687 }
2688
2689 _mesa_hash_table_u64_destroy(ctx->addr1_ht, NULL);
2690 ctx->addr1_ht = NULL;
2691
2692 nir_foreach_instr (instr, nblock) {
2693 ctx->cur_instr = instr;
2694 emit_instr(ctx, instr);
2695 ctx->cur_instr = NULL;
2696 if (ctx->error)
2697 return;
2698 }
2699
2700 _mesa_hash_table_clear(ctx->sel_cond_conversions, NULL);
2701 }
2702
2703 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2704
2705 static void
2706 emit_if(struct ir3_context *ctx, nir_if *nif)
2707 {
2708 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2709
2710 ctx->block->condition =
2711 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
2712
2713 emit_cf_list(ctx, &nif->then_list);
2714 emit_cf_list(ctx, &nif->else_list);
2715 }
2716
2717 static void
2718 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2719 {
2720 emit_cf_list(ctx, &nloop->body);
2721 ctx->so->loops++;
2722 }
2723
2724 static void
2725 stack_push(struct ir3_context *ctx)
2726 {
2727 ctx->stack++;
2728 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2729 }
2730
2731 static void
2732 stack_pop(struct ir3_context *ctx)
2733 {
2734 compile_assert(ctx, ctx->stack > 0);
2735 ctx->stack--;
2736 }
2737
2738 static void
2739 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2740 {
2741 foreach_list_typed (nir_cf_node, node, node, list) {
2742 switch (node->type) {
2743 case nir_cf_node_block:
2744 emit_block(ctx, nir_cf_node_as_block(node));
2745 break;
2746 case nir_cf_node_if:
2747 stack_push(ctx);
2748 emit_if(ctx, nir_cf_node_as_if(node));
2749 stack_pop(ctx);
2750 break;
2751 case nir_cf_node_loop:
2752 stack_push(ctx);
2753 emit_loop(ctx, nir_cf_node_as_loop(node));
2754 stack_pop(ctx);
2755 break;
2756 case nir_cf_node_function:
2757 ir3_context_error(ctx, "TODO\n");
2758 break;
2759 }
2760 }
2761 }
2762
2763 /* emit stream-out code. At this point, the current block is the original
2764 * (nir) end block, and nir ensures that all flow control paths terminate
2765 * into the end block. We re-purpose the original end block to generate
2766 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2767 * block holding stream-out write instructions, followed by the new end
2768 * block:
2769 *
2770 * blockOrigEnd {
2771 * p0.x = (vtxcnt < maxvtxcnt)
2772 * // succs: blockStreamOut, blockNewEnd
2773 * }
2774 * blockStreamOut {
2775 * ... stream-out instructions ...
2776 * // succs: blockNewEnd
2777 * }
2778 * blockNewEnd {
2779 * }
2780 */
2781 static void
2782 emit_stream_out(struct ir3_context *ctx)
2783 {
2784 struct ir3 *ir = ctx->ir;
2785 struct ir3_stream_output_info *strmout =
2786 &ctx->so->shader->stream_output;
2787 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2788 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2789 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2790
2791 /* create vtxcnt input in input block at top of shader,
2792 * so that it is seen as live over the entire duration
2793 * of the shader:
2794 */
2795 vtxcnt = create_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, 0x1);
2796 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2797
2798 /* at this point, we are at the original 'end' block,
2799 * re-purpose this block to stream-out condition, then
2800 * append stream-out block and new-end block
2801 */
2802 orig_end_block = ctx->block;
2803
2804 // TODO these blocks need to update predecessors..
2805 // maybe w/ store_global intrinsic, we could do this
2806 // stuff in nir->nir pass
2807
2808 stream_out_block = ir3_block_create(ir);
2809 list_addtail(&stream_out_block->node, &ir->block_list);
2810
2811 new_end_block = ir3_block_create(ir);
2812 list_addtail(&new_end_block->node, &ir->block_list);
2813
2814 orig_end_block->successors[0] = stream_out_block;
2815 orig_end_block->successors[1] = new_end_block;
2816 stream_out_block->successors[0] = new_end_block;
2817
2818 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2819 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2820 cond->regs[0]->num = regid(REG_P0, 0);
2821 cond->regs[0]->flags &= ~IR3_REG_SSA;
2822 cond->cat2.condition = IR3_COND_LT;
2823
2824 /* condition goes on previous block to the conditional,
2825 * since it is used to pick which of the two successor
2826 * paths to take:
2827 */
2828 orig_end_block->condition = cond;
2829
2830 /* switch to stream_out_block to generate the stream-out
2831 * instructions:
2832 */
2833 ctx->block = stream_out_block;
2834
2835 /* Calculate base addresses based on vtxcnt. Instructions
2836 * generated for bases not used in following loop will be
2837 * stripped out in the backend.
2838 */
2839 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2840 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
2841 unsigned stride = strmout->stride[i];
2842 struct ir3_instruction *base, *off;
2843
2844 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
2845
2846 /* 24-bit should be enough: */
2847 off = ir3_MUL_U24(ctx->block, vtxcnt, 0,
2848 create_immed(ctx->block, stride * 4), 0);
2849
2850 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2851 }
2852
2853 /* Generate the per-output store instructions: */
2854 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2855 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2856 unsigned c = j + strmout->output[i].start_component;
2857 struct ir3_instruction *base, *out, *stg;
2858
2859 base = bases[strmout->output[i].output_buffer];
2860 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2861
2862 stg = ir3_STG(ctx->block, base, 0, out, 0,
2863 create_immed(ctx->block, 1), 0);
2864 stg->cat6.type = TYPE_U32;
2865 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2866
2867 array_insert(ctx->block, ctx->block->keeps, stg);
2868 }
2869 }
2870
2871 /* and finally switch to the new_end_block: */
2872 ctx->block = new_end_block;
2873 }
2874
2875 static void
2876 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2877 {
2878 nir_metadata_require(impl, nir_metadata_block_index);
2879
2880 compile_assert(ctx, ctx->stack == 0);
2881
2882 emit_cf_list(ctx, &impl->body);
2883 emit_block(ctx, impl->end_block);
2884
2885 compile_assert(ctx, ctx->stack == 0);
2886
2887 /* at this point, we should have a single empty block,
2888 * into which we emit the 'end' instruction.
2889 */
2890 compile_assert(ctx, list_is_empty(&ctx->block->instr_list));
2891
2892 /* If stream-out (aka transform-feedback) enabled, emit the
2893 * stream-out instructions, followed by a new empty block (into
2894 * which the 'end' instruction lands).
2895 *
2896 * NOTE: it is done in this order, rather than inserting before
2897 * we emit end_block, because NIR guarantees that all blocks
2898 * flow into end_block, and that end_block has no successors.
2899 * So by re-purposing end_block as the first block of stream-
2900 * out, we guarantee that all exit paths flow into the stream-
2901 * out instructions.
2902 */
2903 if ((ctx->compiler->gpu_id < 500) &&
2904 (ctx->so->shader->stream_output.num_outputs > 0) &&
2905 !ctx->so->binning_pass) {
2906 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2907 emit_stream_out(ctx);
2908 }
2909
2910 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2911 * NOP and has an epilogue that writes the VS outputs to local storage, to
2912 * be read by the HS. Then it resets execution mask (chmask) and chains
2913 * to the next shader (chsh).
2914 */
2915 if ((ctx->so->type == MESA_SHADER_VERTEX &&
2916 (ctx->so->key.has_gs || ctx->so->key.tessellation)) ||
2917 (ctx->so->type == MESA_SHADER_TESS_EVAL && ctx->so->key.has_gs)) {
2918 struct ir3_instruction *chmask =
2919 ir3_CHMASK(ctx->block);
2920 chmask->barrier_class = IR3_BARRIER_EVERYTHING;
2921 chmask->barrier_conflict = IR3_BARRIER_EVERYTHING;
2922
2923 struct ir3_instruction *chsh =
2924 ir3_CHSH(ctx->block);
2925 chsh->barrier_class = IR3_BARRIER_EVERYTHING;
2926 chsh->barrier_conflict = IR3_BARRIER_EVERYTHING;
2927 } else {
2928 ir3_END(ctx->block);
2929 }
2930 }
2931
2932 static void
2933 setup_input(struct ir3_context *ctx, nir_variable *in)
2934 {
2935 struct ir3_shader_variant *so = ctx->so;
2936 unsigned ncomp = glsl_get_components(in->type);
2937 unsigned n = in->data.driver_location;
2938 unsigned frac = in->data.location_frac;
2939 unsigned slot = in->data.location;
2940
2941 /* Inputs are loaded using ldlw or ldg for these stages. */
2942 if (ctx->so->type == MESA_SHADER_TESS_CTRL ||
2943 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2944 ctx->so->type == MESA_SHADER_GEOMETRY)
2945 return;
2946
2947 /* skip unread inputs, we could end up with (for example), unsplit
2948 * matrix/etc inputs in the case they are not read, so just silently
2949 * skip these.
2950 */
2951 if (ncomp > 4)
2952 return;
2953
2954 so->inputs[n].slot = slot;
2955 so->inputs[n].compmask |= (1 << (ncomp + frac)) - 1;
2956 so->inputs_count = MAX2(so->inputs_count, n + 1);
2957 so->inputs[n].interpolate = in->data.interpolation;
2958
2959 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2960
2961 /* if any varyings have 'sample' qualifer, that triggers us
2962 * to run in per-sample mode:
2963 */
2964 so->per_samp |= in->data.sample;
2965
2966 for (int i = 0; i < ncomp; i++) {
2967 struct ir3_instruction *instr = NULL;
2968 unsigned idx = (n * 4) + i + frac;
2969
2970 if (slot == VARYING_SLOT_POS) {
2971 ir3_context_error(ctx, "fragcoord should be a sysval!\n");
2972 } else {
2973 /* detect the special case for front/back colors where
2974 * we need to do flat vs smooth shading depending on
2975 * rast state:
2976 */
2977 if (in->data.interpolation == INTERP_MODE_NONE) {
2978 switch (slot) {
2979 case VARYING_SLOT_COL0:
2980 case VARYING_SLOT_COL1:
2981 case VARYING_SLOT_BFC0:
2982 case VARYING_SLOT_BFC1:
2983 so->inputs[n].rasterflat = true;
2984 break;
2985 default:
2986 break;
2987 }
2988 }
2989
2990 if (ctx->compiler->flat_bypass) {
2991 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2992 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2993 so->inputs[n].use_ldlv = true;
2994 }
2995
2996 so->inputs[n].bary = true;
2997
2998 instr = create_frag_input(ctx, so->inputs[n].use_ldlv, idx);
2999 }
3000
3001 compile_assert(ctx, idx < ctx->ninputs);
3002
3003 ctx->inputs[idx] = instr;
3004 }
3005 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
3006 struct ir3_instruction *input = NULL, *in;
3007 struct ir3_instruction *components[4];
3008 unsigned mask = (1 << (ncomp + frac)) - 1;
3009
3010 foreach_input (in, ctx->ir) {
3011 if (in->input.inidx == n) {
3012 input = in;
3013 break;
3014 }
3015 }
3016
3017 if (!input) {
3018 input = create_input(ctx, mask);
3019 input->input.inidx = n;
3020 } else {
3021 input->regs[0]->wrmask |= mask;
3022 }
3023
3024 ir3_split_dest(ctx->block, components, input, frac, ncomp);
3025
3026 for (int i = 0; i < ncomp; i++) {
3027 unsigned idx = (n * 4) + i + frac;
3028 compile_assert(ctx, idx < ctx->ninputs);
3029 ctx->inputs[idx] = components[i];
3030 }
3031 } else {
3032 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
3033 }
3034
3035 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
3036 so->total_in += ncomp;
3037 }
3038 }
3039
3040 /* Initially we assign non-packed inloc's for varyings, as we don't really
3041 * know up-front which components will be unused. After all the compilation
3042 * stages we scan the shader to see which components are actually used, and
3043 * re-pack the inlocs to eliminate unneeded varyings.
3044 */
3045 static void
3046 pack_inlocs(struct ir3_context *ctx)
3047 {
3048 struct ir3_shader_variant *so = ctx->so;
3049 uint8_t used_components[so->inputs_count];
3050
3051 memset(used_components, 0, sizeof(used_components));
3052
3053 /*
3054 * First Step: scan shader to find which bary.f/ldlv remain:
3055 */
3056
3057 foreach_block (block, &ctx->ir->block_list) {
3058 foreach_instr (instr, &block->instr_list) {
3059 if (is_input(instr)) {
3060 unsigned inloc = instr->regs[1]->iim_val;
3061 unsigned i = inloc / 4;
3062 unsigned j = inloc % 4;
3063
3064 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
3065 compile_assert(ctx, i < so->inputs_count);
3066
3067 used_components[i] |= 1 << j;
3068 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
3069 for (int n = 0; n < 2; n++) {
3070 unsigned inloc = instr->prefetch.input_offset + n;
3071 unsigned i = inloc / 4;
3072 unsigned j = inloc % 4;
3073
3074 compile_assert(ctx, i < so->inputs_count);
3075
3076 used_components[i] |= 1 << j;
3077 }
3078 }
3079 }
3080 }
3081
3082 /*
3083 * Second Step: reassign varying inloc/slots:
3084 */
3085
3086 unsigned actual_in = 0;
3087 unsigned inloc = 0;
3088
3089 for (unsigned i = 0; i < so->inputs_count; i++) {
3090 unsigned compmask = 0, maxcomp = 0;
3091
3092 so->inputs[i].inloc = inloc;
3093 so->inputs[i].bary = false;
3094
3095 for (unsigned j = 0; j < 4; j++) {
3096 if (!(used_components[i] & (1 << j)))
3097 continue;
3098
3099 compmask |= (1 << j);
3100 actual_in++;
3101 maxcomp = j + 1;
3102
3103 /* at this point, since used_components[i] mask is only
3104 * considering varyings (ie. not sysvals) we know this
3105 * is a varying:
3106 */
3107 so->inputs[i].bary = true;
3108 }
3109
3110 if (so->inputs[i].bary) {
3111 so->varying_in++;
3112 so->inputs[i].compmask = (1 << maxcomp) - 1;
3113 inloc += maxcomp;
3114 }
3115 }
3116
3117 /*
3118 * Third Step: reassign packed inloc's:
3119 */
3120
3121 foreach_block (block, &ctx->ir->block_list) {
3122 foreach_instr (instr, &block->instr_list) {
3123 if (is_input(instr)) {
3124 unsigned inloc = instr->regs[1]->iim_val;
3125 unsigned i = inloc / 4;
3126 unsigned j = inloc % 4;
3127
3128 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
3129 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
3130 unsigned i = instr->prefetch.input_offset / 4;
3131 unsigned j = instr->prefetch.input_offset % 4;
3132 instr->prefetch.input_offset = so->inputs[i].inloc + j;
3133 }
3134 }
3135 }
3136 }
3137
3138 static void
3139 setup_output(struct ir3_context *ctx, nir_variable *out)
3140 {
3141 struct ir3_shader_variant *so = ctx->so;
3142 unsigned ncomp = glsl_get_components(out->type);
3143 unsigned n = out->data.driver_location;
3144 unsigned frac = out->data.location_frac;
3145 unsigned slot = out->data.location;
3146
3147 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3148 switch (slot) {
3149 case FRAG_RESULT_DEPTH:
3150 so->writes_pos = true;
3151 break;
3152 case FRAG_RESULT_COLOR:
3153 so->color0_mrt = 1;
3154 break;
3155 case FRAG_RESULT_SAMPLE_MASK:
3156 so->writes_smask = true;
3157 break;
3158 default:
3159 if (slot >= FRAG_RESULT_DATA0)
3160 break;
3161 ir3_context_error(ctx, "unknown FS output name: %s\n",
3162 gl_frag_result_name(slot));
3163 }
3164 } else if (ctx->so->type == MESA_SHADER_VERTEX ||
3165 ctx->so->type == MESA_SHADER_TESS_EVAL ||
3166 ctx->so->type == MESA_SHADER_GEOMETRY) {
3167 switch (slot) {
3168 case VARYING_SLOT_POS:
3169 so->writes_pos = true;
3170 break;
3171 case VARYING_SLOT_PSIZ:
3172 so->writes_psize = true;
3173 break;
3174 case VARYING_SLOT_PRIMITIVE_ID:
3175 case VARYING_SLOT_LAYER:
3176 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
3177 debug_assert(ctx->so->type == MESA_SHADER_GEOMETRY);
3178 /* fall through */
3179 case VARYING_SLOT_COL0:
3180 case VARYING_SLOT_COL1:
3181 case VARYING_SLOT_BFC0:
3182 case VARYING_SLOT_BFC1:
3183 case VARYING_SLOT_FOGC:
3184 case VARYING_SLOT_CLIP_DIST0:
3185 case VARYING_SLOT_CLIP_DIST1:
3186 case VARYING_SLOT_CLIP_VERTEX:
3187 break;
3188 default:
3189 if (slot >= VARYING_SLOT_VAR0)
3190 break;
3191 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
3192 break;
3193 ir3_context_error(ctx, "unknown %s shader output name: %s\n",
3194 _mesa_shader_stage_to_string(ctx->so->type),
3195 gl_varying_slot_name(slot));
3196 }
3197 } else if (ctx->so->type == MESA_SHADER_TESS_CTRL) {
3198 /* output lowered to buffer writes. */
3199 return;
3200 } else {
3201 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
3202 }
3203
3204 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
3205
3206 so->outputs[n].slot = slot;
3207 so->outputs[n].regid = regid(n, 0);
3208 so->outputs_count = MAX2(so->outputs_count, n + 1);
3209
3210 for (int i = 0; i < ncomp; i++) {
3211 unsigned idx = (n * 4) + i + frac;
3212 compile_assert(ctx, idx < ctx->noutputs);
3213 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
3214 }
3215
3216 /* if varying packing doesn't happen, we could end up in a situation
3217 * with "holes" in the output, and since the per-generation code that
3218 * sets up varying linkage registers doesn't expect to have more than
3219 * one varying per vec4 slot, pad the holes.
3220 *
3221 * Note that this should probably generate a performance warning of
3222 * some sort.
3223 */
3224 for (int i = 0; i < frac; i++) {
3225 unsigned idx = (n * 4) + i;
3226 if (!ctx->outputs[idx]) {
3227 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
3228 }
3229 }
3230 }
3231
3232 static void
3233 emit_instructions(struct ir3_context *ctx)
3234 {
3235 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
3236
3237 ctx->ninputs = ctx->s->num_inputs * 4;
3238 ctx->noutputs = ctx->s->num_outputs * 4;
3239 ctx->inputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->ninputs);
3240 ctx->outputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->noutputs);
3241
3242 ctx->ir = ir3_create(ctx->compiler, ctx->so->type);
3243
3244 /* Create inputs in first block: */
3245 ctx->block = get_block(ctx, nir_start_block(fxn));
3246 ctx->in_block = ctx->block;
3247
3248 /* for fragment shader, the vcoord input register is used as the
3249 * base for bary.f varying fetch instrs:
3250 *
3251 * TODO defer creating ctx->ij_pixel and corresponding sysvals
3252 * until emit_intrinsic when we know they are actually needed.
3253 * For now, we defer creating ctx->ij_centroid, etc, since we
3254 * only need ij_pixel for "old style" varying inputs (ie.
3255 * tgsi_to_nir)
3256 */
3257 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3258 ctx->ij_pixel = create_input(ctx, 0x3);
3259 }
3260
3261 /* Setup inputs: */
3262 nir_foreach_variable (var, &ctx->s->inputs) {
3263 setup_input(ctx, var);
3264 }
3265
3266 /* Defer add_sysval_input() stuff until after setup_inputs(),
3267 * because sysvals need to be appended after varyings:
3268 */
3269 if (ctx->ij_pixel) {
3270 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL,
3271 0x3, ctx->ij_pixel);
3272 }
3273
3274
3275 /* Tesselation shaders always need primitive ID for indexing the
3276 * BO. Geometry shaders don't always need it but when they do it has be
3277 * delivered and unclobbered in the VS. To make things easy, we always
3278 * make room for it in VS/DS.
3279 */
3280 bool has_tess = ctx->so->key.tessellation != IR3_TESS_NONE;
3281 bool has_gs = ctx->so->key.has_gs;
3282 switch (ctx->so->type) {
3283 case MESA_SHADER_VERTEX:
3284 if (has_tess) {
3285 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3286 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3287 } else if (has_gs) {
3288 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3289 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3290 }
3291 break;
3292 case MESA_SHADER_TESS_CTRL:
3293 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3294 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3295 break;
3296 case MESA_SHADER_TESS_EVAL:
3297 if (has_gs)
3298 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3299 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3300 break;
3301 case MESA_SHADER_GEOMETRY:
3302 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3303 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3304 break;
3305 default:
3306 break;
3307 }
3308
3309 /* Setup outputs: */
3310 nir_foreach_variable (var, &ctx->s->outputs) {
3311 setup_output(ctx, var);
3312 }
3313
3314 /* Find # of samplers: */
3315 nir_foreach_variable (var, &ctx->s->uniforms) {
3316 ctx->so->num_samp += glsl_type_get_sampler_count(var->type);
3317 /* just assume that we'll be reading from images.. if it
3318 * is write-only we don't have to count it, but not sure
3319 * if there is a good way to know?
3320 */
3321 ctx->so->num_samp += glsl_type_get_image_count(var->type);
3322 }
3323
3324 /* NOTE: need to do something more clever when we support >1 fxn */
3325 nir_foreach_register (reg, &fxn->registers) {
3326 ir3_declare_array(ctx, reg);
3327 }
3328 /* And emit the body: */
3329 ctx->impl = fxn;
3330 emit_function(ctx, fxn);
3331 }
3332
3333 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3334 * need to assign the tex state indexes for these after we know the
3335 * max tex index.
3336 */
3337 static void
3338 fixup_astc_srgb(struct ir3_context *ctx)
3339 {
3340 struct ir3_shader_variant *so = ctx->so;
3341 /* indexed by original tex idx, value is newly assigned alpha sampler
3342 * state tex idx. Zero is invalid since there is at least one sampler
3343 * if we get here.
3344 */
3345 unsigned alt_tex_state[16] = {0};
3346 unsigned tex_idx = ctx->max_texture_index + 1;
3347 unsigned idx = 0;
3348
3349 so->astc_srgb.base = tex_idx;
3350
3351 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
3352 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
3353
3354 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
3355
3356 if (alt_tex_state[sam->cat5.tex] == 0) {
3357 /* assign new alternate/alpha tex state slot: */
3358 alt_tex_state[sam->cat5.tex] = tex_idx++;
3359 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
3360 so->astc_srgb.count++;
3361 }
3362
3363 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
3364 }
3365 }
3366
3367 static void
3368 fixup_binning_pass(struct ir3_context *ctx)
3369 {
3370 struct ir3_shader_variant *so = ctx->so;
3371 struct ir3 *ir = ctx->ir;
3372 unsigned i, j;
3373
3374 /* first pass, remove unused outputs from the IR level outputs: */
3375 for (i = 0, j = 0; i < ir->outputs_count; i++) {
3376 struct ir3_instruction *out = ir->outputs[i];
3377 assert(out->opc == OPC_META_COLLECT);
3378 unsigned outidx = out->collect.outidx;
3379 unsigned slot = so->outputs[outidx].slot;
3380
3381 /* throw away everything but first position/psize */
3382 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3383 ir->outputs[j] = ir->outputs[i];
3384 j++;
3385 }
3386 }
3387 ir->outputs_count = j;
3388
3389 /* second pass, cleanup the unused slots in ir3_shader_variant::outputs
3390 * table:
3391 */
3392 for (i = 0, j = 0; i < so->outputs_count; i++) {
3393 unsigned slot = so->outputs[i].slot;
3394
3395 /* throw away everything but first position/psize */
3396 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3397 so->outputs[j] = so->outputs[i];
3398
3399 /* fixup outidx to point to new output table entry: */
3400 struct ir3_instruction *out;
3401 foreach_output (out, ir) {
3402 if (out->collect.outidx == i) {
3403 out->collect.outidx = j;
3404 break;
3405 }
3406 }
3407
3408 j++;
3409 }
3410 }
3411 so->outputs_count = j;
3412 }
3413
3414 static void
3415 collect_tex_prefetches(struct ir3_context *ctx, struct ir3 *ir)
3416 {
3417 unsigned idx = 0;
3418
3419 /* Collect sampling instructions eligible for pre-dispatch. */
3420 foreach_block (block, &ir->block_list) {
3421 foreach_instr_safe (instr, &block->instr_list) {
3422 if (instr->opc == OPC_META_TEX_PREFETCH) {
3423 assert(idx < ARRAY_SIZE(ctx->so->sampler_prefetch));
3424 struct ir3_sampler_prefetch *fetch =
3425 &ctx->so->sampler_prefetch[idx];
3426 idx++;
3427
3428 if (instr->flags & IR3_INSTR_B) {
3429 fetch->cmd = IR3_SAMPLER_BINDLESS_PREFETCH_CMD;
3430 /* In bindless mode, the index is actually the base */
3431 fetch->tex_id = instr->prefetch.tex_base;
3432 fetch->samp_id = instr->prefetch.samp_base;
3433 fetch->tex_bindless_id = instr->prefetch.tex;
3434 fetch->samp_bindless_id = instr->prefetch.samp;
3435 } else {
3436 fetch->cmd = IR3_SAMPLER_PREFETCH_CMD;
3437 fetch->tex_id = instr->prefetch.tex;
3438 fetch->samp_id = instr->prefetch.samp;
3439 }
3440 fetch->wrmask = instr->regs[0]->wrmask;
3441 fetch->dst = instr->regs[0]->num;
3442 fetch->src = instr->prefetch.input_offset;
3443
3444 ctx->so->total_in =
3445 MAX2(ctx->so->total_in, instr->prefetch.input_offset + 2);
3446
3447 /* Disable half precision until supported. */
3448 fetch->half_precision = !!(instr->regs[0]->flags & IR3_REG_HALF);
3449
3450 /* Remove the prefetch placeholder instruction: */
3451 list_delinit(&instr->node);
3452 }
3453 }
3454 }
3455 }
3456
3457 int
3458 ir3_compile_shader_nir(struct ir3_compiler *compiler,
3459 struct ir3_shader_variant *so)
3460 {
3461 struct ir3_context *ctx;
3462 struct ir3 *ir;
3463 int ret = 0, max_bary;
3464
3465 assert(!so->ir);
3466
3467 ctx = ir3_context_init(compiler, so);
3468 if (!ctx) {
3469 DBG("INIT failed!");
3470 ret = -1;
3471 goto out;
3472 }
3473
3474 emit_instructions(ctx);
3475
3476 if (ctx->error) {
3477 DBG("EMIT failed!");
3478 ret = -1;
3479 goto out;
3480 }
3481
3482 ir = so->ir = ctx->ir;
3483
3484 assert((ctx->noutputs % 4) == 0);
3485
3486 /* Setup IR level outputs, which are "collects" that gather
3487 * the scalar components of outputs.
3488 */
3489 for (unsigned i = 0; i < ctx->noutputs; i += 4) {
3490 unsigned ncomp = 0;
3491 /* figure out the # of components written:
3492 *
3493 * TODO do we need to handle holes, ie. if .x and .z
3494 * components written, but .y component not written?
3495 */
3496 for (unsigned j = 0; j < 4; j++) {
3497 if (!ctx->outputs[i + j])
3498 break;
3499 ncomp++;
3500 }
3501
3502 /* Note that in some stages, like TCS, store_output is
3503 * lowered to memory writes, so no components of the
3504 * are "written" from the PoV of traditional store-
3505 * output instructions:
3506 */
3507 if (!ncomp)
3508 continue;
3509
3510 struct ir3_instruction *out =
3511 ir3_create_collect(ctx, &ctx->outputs[i], ncomp);
3512
3513 int outidx = i / 4;
3514 assert(outidx < so->outputs_count);
3515
3516 /* stash index into so->outputs[] so we can map the
3517 * output back to slot/etc later:
3518 */
3519 out->collect.outidx = outidx;
3520
3521 array_insert(ir, ir->outputs, out);
3522 }
3523
3524 /* Set up the gs header as an output for the vertex shader so it won't
3525 * clobber it for the tess ctrl shader.
3526 *
3527 * TODO this could probably be done more cleanly in a nir pass.
3528 */
3529 if (ctx->so->type == MESA_SHADER_VERTEX ||
3530 (ctx->so->key.has_gs && ctx->so->type == MESA_SHADER_TESS_EVAL)) {
3531 if (ctx->primitive_id) {
3532 unsigned n = so->outputs_count++;
3533 so->outputs[n].slot = VARYING_SLOT_PRIMITIVE_ID;
3534
3535 struct ir3_instruction *out =
3536 ir3_create_collect(ctx, &ctx->primitive_id, 1);
3537 out->collect.outidx = n;
3538 array_insert(ir, ir->outputs, out);
3539 }
3540
3541 if (ctx->gs_header) {
3542 unsigned n = so->outputs_count++;
3543 so->outputs[n].slot = VARYING_SLOT_GS_HEADER_IR3;
3544 struct ir3_instruction *out =
3545 ir3_create_collect(ctx, &ctx->gs_header, 1);
3546 out->collect.outidx = n;
3547 array_insert(ir, ir->outputs, out);
3548 }
3549
3550 if (ctx->tcs_header) {
3551 unsigned n = so->outputs_count++;
3552 so->outputs[n].slot = VARYING_SLOT_TCS_HEADER_IR3;
3553 struct ir3_instruction *out =
3554 ir3_create_collect(ctx, &ctx->tcs_header, 1);
3555 out->collect.outidx = n;
3556 array_insert(ir, ir->outputs, out);
3557 }
3558 }
3559
3560 /* at this point, for binning pass, throw away unneeded outputs: */
3561 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
3562 fixup_binning_pass(ctx);
3563
3564 ir3_debug_print(ir, "BEFORE CF");
3565
3566 ir3_cf(ir);
3567
3568 ir3_debug_print(ir, "BEFORE CP");
3569
3570 ir3_cp(ir, so);
3571
3572 /* at this point, for binning pass, throw away unneeded outputs:
3573 * Note that for a6xx and later, we do this after ir3_cp to ensure
3574 * that the uniform/constant layout for BS and VS matches, so that
3575 * we can re-use same VS_CONST state group.
3576 */
3577 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
3578 fixup_binning_pass(ctx);
3579
3580 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3581 * need to make sure not to remove any inputs that are used by
3582 * the nonbinning VS.
3583 */
3584 if (ctx->compiler->gpu_id >= 600 && so->binning_pass &&
3585 so->type == MESA_SHADER_VERTEX) {
3586 for (int i = 0; i < ctx->ninputs; i++) {
3587 struct ir3_instruction *in = ctx->inputs[i];
3588
3589 if (!in)
3590 continue;
3591
3592 unsigned n = i / 4;
3593 unsigned c = i % 4;
3594
3595 debug_assert(n < so->nonbinning->inputs_count);
3596
3597 if (so->nonbinning->inputs[n].sysval)
3598 continue;
3599
3600 /* be sure to keep inputs, even if only used in VS */
3601 if (so->nonbinning->inputs[n].compmask & (1 << c))
3602 array_insert(in->block, in->block->keeps, in);
3603 }
3604 }
3605
3606 ir3_debug_print(ir, "BEFORE GROUPING");
3607
3608 ir3_sched_add_deps(ir);
3609
3610 /* Group left/right neighbors, inserting mov's where needed to
3611 * solve conflicts:
3612 */
3613 ir3_group(ir);
3614
3615 ir3_debug_print(ir, "AFTER GROUPING");
3616
3617 ir3_dce(ir, so);
3618
3619 ir3_debug_print(ir, "AFTER DCE");
3620
3621 /* do Sethi–Ullman numbering before scheduling: */
3622 ir3_sun(ir);
3623
3624 ret = ir3_sched(ir);
3625 if (ret) {
3626 DBG("SCHED failed!");
3627 goto out;
3628 }
3629
3630 ir3_debug_print(ir, "AFTER SCHED");
3631
3632 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3633 * with draw pass VS, so binning and draw pass can both use the
3634 * same VBO state.
3635 *
3636 * Note that VS inputs are expected to be full precision.
3637 */
3638 bool pre_assign_inputs = (ir->compiler->gpu_id >= 600) &&
3639 (ir->type == MESA_SHADER_VERTEX) &&
3640 so->binning_pass;
3641
3642 if (pre_assign_inputs) {
3643 for (unsigned i = 0; i < ctx->ninputs; i++) {
3644 struct ir3_instruction *instr = ctx->inputs[i];
3645
3646 if (!instr)
3647 continue;
3648
3649 unsigned n = i / 4;
3650 unsigned c = i % 4;
3651 unsigned regid = so->nonbinning->inputs[n].regid + c;
3652
3653 instr->regs[0]->num = regid;
3654 }
3655
3656 ret = ir3_ra(so, ctx->inputs, ctx->ninputs);
3657 } else if (ctx->tcs_header) {
3658 /* We need to have these values in the same registers between VS and TCS
3659 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3660 */
3661
3662 ctx->tcs_header->regs[0]->num = regid(0, 0);
3663 ctx->primitive_id->regs[0]->num = regid(0, 1);
3664 struct ir3_instruction *precolor[] = { ctx->tcs_header, ctx->primitive_id };
3665 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3666 } else if (ctx->gs_header) {
3667 /* We need to have these values in the same registers between producer
3668 * (VS or DS) and GS since the producer chains to GS and doesn't get
3669 * the sysvals redelivered.
3670 */
3671
3672 ctx->gs_header->regs[0]->num = regid(0, 0);
3673 ctx->primitive_id->regs[0]->num = regid(0, 1);
3674 struct ir3_instruction *precolor[] = { ctx->gs_header, ctx->primitive_id };
3675 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3676 } else if (so->num_sampler_prefetch) {
3677 assert(so->type == MESA_SHADER_FRAGMENT);
3678 struct ir3_instruction *instr, *precolor[2];
3679 int idx = 0;
3680
3681 foreach_input (instr, ir) {
3682 if (instr->input.sysval != SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL)
3683 continue;
3684
3685 assert(idx < ARRAY_SIZE(precolor));
3686
3687 precolor[idx] = instr;
3688 instr->regs[0]->num = idx;
3689
3690 idx++;
3691 }
3692 ret = ir3_ra(so, precolor, idx);
3693 } else {
3694 ret = ir3_ra(so, NULL, 0);
3695 }
3696
3697 if (ret) {
3698 DBG("RA failed!");
3699 goto out;
3700 }
3701
3702 ir3_postsched(ctx);
3703 ir3_debug_print(ir, "AFTER POSTSCHED");
3704
3705 if (compiler->gpu_id >= 600) {
3706 if (ir3_a6xx_fixup_atomic_dests(ir, so)) {
3707 ir3_debug_print(ir, "AFTER ATOMIC FIXUP");
3708 }
3709 }
3710
3711 if (so->type == MESA_SHADER_FRAGMENT)
3712 pack_inlocs(ctx);
3713
3714 /*
3715 * Fixup inputs/outputs to point to the actual registers assigned:
3716 *
3717 * 1) initialize to r63.x (invalid/unused)
3718 * 2) iterate IR level inputs/outputs and update the variants
3719 * inputs/outputs table based on the assigned registers for
3720 * the remaining inputs/outputs.
3721 */
3722
3723 for (unsigned i = 0; i < so->inputs_count; i++)
3724 so->inputs[i].regid = INVALID_REG;
3725 for (unsigned i = 0; i < so->outputs_count; i++)
3726 so->outputs[i].regid = INVALID_REG;
3727
3728 struct ir3_instruction *out;
3729 foreach_output (out, ir) {
3730 assert(out->opc == OPC_META_COLLECT);
3731 unsigned outidx = out->collect.outidx;
3732
3733 so->outputs[outidx].regid = out->regs[0]->num;
3734 so->outputs[outidx].half = !!(out->regs[0]->flags & IR3_REG_HALF);
3735 }
3736
3737 struct ir3_instruction *in;
3738 foreach_input (in, ir) {
3739 assert(in->opc == OPC_META_INPUT);
3740 unsigned inidx = in->input.inidx;
3741
3742 if (pre_assign_inputs && !so->inputs[inidx].sysval) {
3743 if (VALIDREG(so->nonbinning->inputs[inidx].regid)) {
3744 compile_assert(ctx, in->regs[0]->num ==
3745 so->nonbinning->inputs[inidx].regid);
3746 compile_assert(ctx, !!(in->regs[0]->flags & IR3_REG_HALF) ==
3747 so->nonbinning->inputs[inidx].half);
3748 }
3749 so->inputs[inidx].regid = so->nonbinning->inputs[inidx].regid;
3750 so->inputs[inidx].half = so->nonbinning->inputs[inidx].half;
3751 } else {
3752 so->inputs[inidx].regid = in->regs[0]->num;
3753 so->inputs[inidx].half = !!(in->regs[0]->flags & IR3_REG_HALF);
3754 }
3755 }
3756
3757 if (ctx->astc_srgb)
3758 fixup_astc_srgb(ctx);
3759
3760 /* We need to do legalize after (for frag shader's) the "bary.f"
3761 * offsets (inloc) have been assigned.
3762 */
3763 ir3_legalize(ir, so, &max_bary);
3764
3765 ir3_debug_print(ir, "AFTER LEGALIZE");
3766
3767 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3768 * know what we might have to wait on when coming in from VS chsh.
3769 */
3770 if (so->type == MESA_SHADER_TESS_CTRL ||
3771 so->type == MESA_SHADER_GEOMETRY ) {
3772 foreach_block (block, &ir->block_list) {
3773 foreach_instr (instr, &block->instr_list) {
3774 instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
3775 break;
3776 }
3777 }
3778 }
3779
3780 so->branchstack = ctx->max_stack;
3781
3782 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3783 if (so->type == MESA_SHADER_FRAGMENT)
3784 so->total_in = max_bary + 1;
3785
3786 so->max_sun = ir->max_sun;
3787
3788 /* Collect sampling instructions eligible for pre-dispatch. */
3789 collect_tex_prefetches(ctx, ir);
3790
3791 if (so->type == MESA_SHADER_FRAGMENT &&
3792 ctx->s->info.fs.needs_helper_invocations)
3793 so->need_pixlod = true;
3794
3795 out:
3796 if (ret) {
3797 if (so->ir)
3798 ir3_destroy(so->ir);
3799 so->ir = NULL;
3800 }
3801 ir3_context_free(ctx);
3802
3803 return ret;
3804 }