2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
38 #include "instr-a3xx.h"
40 #include "ir3_context.h"
43 static struct ir3_instruction
*
44 create_indirect_load(struct ir3_context
*ctx
, unsigned arrsz
, int n
,
45 struct ir3_instruction
*address
, struct ir3_instruction
*collect
)
47 struct ir3_block
*block
= ctx
->block
;
48 struct ir3_instruction
*mov
;
49 struct ir3_register
*src
;
51 mov
= ir3_instr_create(block
, OPC_MOV
);
52 mov
->cat1
.src_type
= TYPE_U32
;
53 mov
->cat1
.dst_type
= TYPE_U32
;
55 src
= __ssa_src(mov
, collect
, IR3_REG_RELATIV
);
57 src
->array
.offset
= n
;
59 ir3_instr_set_address(mov
, address
);
64 static struct ir3_instruction
*
65 create_input(struct ir3_context
*ctx
, unsigned compmask
)
67 struct ir3_instruction
*in
;
69 in
= ir3_instr_create(ctx
->in_block
, OPC_META_INPUT
);
70 in
->input
.sysval
= ~0;
71 __ssa_dst(in
)->wrmask
= compmask
;
73 array_insert(ctx
->ir
, ctx
->ir
->inputs
, in
);
78 static struct ir3_instruction
*
79 create_frag_input(struct ir3_context
*ctx
, bool use_ldlv
, unsigned n
)
81 struct ir3_block
*block
= ctx
->block
;
82 struct ir3_instruction
*instr
;
83 /* packed inloc is fixed up later: */
84 struct ir3_instruction
*inloc
= create_immed(block
, n
);
87 instr
= ir3_LDLV(block
, inloc
, 0, create_immed(block
, 1), 0);
88 instr
->cat6
.type
= TYPE_U32
;
89 instr
->cat6
.iim_val
= 1;
91 instr
= ir3_BARY_F(block
, inloc
, 0, ctx
->ij_pixel
, 0);
92 instr
->regs
[2]->wrmask
= 0x3;
98 static struct ir3_instruction
*
99 create_driver_param(struct ir3_context
*ctx
, enum ir3_driver_param dp
)
101 /* first four vec4 sysval's reserved for UBOs: */
102 /* NOTE: dp is in scalar, but there can be >4 dp components: */
103 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
104 unsigned n
= const_state
->offsets
.driver_param
;
105 unsigned r
= regid(n
+ dp
/ 4, dp
% 4);
106 return create_uniform(ctx
->block
, r
);
110 * Adreno uses uint rather than having dedicated bool type,
111 * which (potentially) requires some conversion, in particular
112 * when using output of an bool instr to int input, or visa
116 * -------+---------+-------+-
120 * To convert from an adreno bool (uint) to nir, use:
122 * absneg.s dst, (neg)src
124 * To convert back in the other direction:
126 * absneg.s dst, (abs)arc
128 * The CP step can clean up the absneg.s that cancel each other
129 * out, and with a slight bit of extra cleverness (to recognize
130 * the instructions which produce either a 0 or 1) can eliminate
131 * the absneg.s's completely when an instruction that wants
132 * 0/1 consumes the result. For example, when a nir 'bcsel'
133 * consumes the result of 'feq'. So we should be able to get by
134 * without a boolean resolve step, and without incuring any
135 * extra penalty in instruction count.
138 /* NIR bool -> native (adreno): */
139 static struct ir3_instruction
*
140 ir3_b2n(struct ir3_block
*block
, struct ir3_instruction
*instr
)
142 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SABS
);
145 /* native (adreno) -> NIR bool: */
146 static struct ir3_instruction
*
147 ir3_n2b(struct ir3_block
*block
, struct ir3_instruction
*instr
)
149 return ir3_ABSNEG_S(block
, instr
, IR3_REG_SNEG
);
153 * alu/sfu instructions:
156 static struct ir3_instruction
*
157 create_cov(struct ir3_context
*ctx
, struct ir3_instruction
*src
,
158 unsigned src_bitsize
, nir_op op
)
160 type_t src_type
, dst_type
;
164 case nir_op_f2f16_rtne
:
165 case nir_op_f2f16_rtz
:
173 switch (src_bitsize
) {
181 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
190 switch (src_bitsize
) {
201 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
210 switch (src_bitsize
) {
221 ir3_context_error(ctx
, "invalid src bit size: %u", src_bitsize
);
226 ir3_context_error(ctx
, "invalid conversion op: %u", op
);
236 case nir_op_f2f16_rtne
:
237 case nir_op_f2f16_rtz
:
239 /* TODO how to handle rounding mode? */
276 ir3_context_error(ctx
, "invalid conversion op: %u", op
);
279 return ir3_COV(ctx
->block
, src
, src_type
, dst_type
);
283 emit_alu(struct ir3_context
*ctx
, nir_alu_instr
*alu
)
285 const nir_op_info
*info
= &nir_op_infos
[alu
->op
];
286 struct ir3_instruction
**dst
, *src
[info
->num_inputs
];
287 unsigned bs
[info
->num_inputs
]; /* bit size */
288 struct ir3_block
*b
= ctx
->block
;
289 unsigned dst_sz
, wrmask
;
290 type_t dst_type
= nir_dest_bit_size(alu
->dest
.dest
) < 32 ?
293 if (alu
->dest
.dest
.is_ssa
) {
294 dst_sz
= alu
->dest
.dest
.ssa
.num_components
;
295 wrmask
= (1 << dst_sz
) - 1;
297 dst_sz
= alu
->dest
.dest
.reg
.reg
->num_components
;
298 wrmask
= alu
->dest
.write_mask
;
301 dst
= ir3_get_dst(ctx
, &alu
->dest
.dest
, dst_sz
);
303 /* Vectors are special in that they have non-scalarized writemasks,
304 * and just take the first swizzle channel for each argument in
305 * order into each writemask channel.
307 if ((alu
->op
== nir_op_vec2
) ||
308 (alu
->op
== nir_op_vec3
) ||
309 (alu
->op
== nir_op_vec4
)) {
311 for (int i
= 0; i
< info
->num_inputs
; i
++) {
312 nir_alu_src
*asrc
= &alu
->src
[i
];
314 compile_assert(ctx
, !asrc
->abs
);
315 compile_assert(ctx
, !asrc
->negate
);
317 src
[i
] = ir3_get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[0]];
319 src
[i
] = create_immed_typed(ctx
->block
, 0, dst_type
);
320 dst
[i
] = ir3_MOV(b
, src
[i
], dst_type
);
323 ir3_put_dst(ctx
, &alu
->dest
.dest
);
327 /* We also get mov's with more than one component for mov's so
328 * handle those specially:
330 if (alu
->op
== nir_op_mov
) {
331 nir_alu_src
*asrc
= &alu
->src
[0];
332 struct ir3_instruction
*const *src0
= ir3_get_src(ctx
, &asrc
->src
);
334 for (unsigned i
= 0; i
< dst_sz
; i
++) {
335 if (wrmask
& (1 << i
)) {
336 dst
[i
] = ir3_MOV(b
, src0
[asrc
->swizzle
[i
]], dst_type
);
342 ir3_put_dst(ctx
, &alu
->dest
.dest
);
346 /* General case: We can just grab the one used channel per src. */
347 for (int i
= 0; i
< info
->num_inputs
; i
++) {
348 unsigned chan
= ffs(alu
->dest
.write_mask
) - 1;
349 nir_alu_src
*asrc
= &alu
->src
[i
];
351 compile_assert(ctx
, !asrc
->abs
);
352 compile_assert(ctx
, !asrc
->negate
);
354 src
[i
] = ir3_get_src(ctx
, &asrc
->src
)[asrc
->swizzle
[chan
]];
355 bs
[i
] = nir_src_bit_size(asrc
->src
);
357 compile_assert(ctx
, src
[i
]);
362 case nir_op_f2f16_rtne
:
363 case nir_op_f2f16_rtz
:
381 dst
[0] = create_cov(ctx
, src
[0], bs
[0], alu
->op
);
383 case nir_op_fquantize2f16
:
384 dst
[0] = create_cov(ctx
,
385 create_cov(ctx
, src
[0], 32, nir_op_f2f16
),
389 struct ir3_instruction
*zero
= create_immed_typed(b
, 0, TYPE_F16
);
390 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, zero
, 0);
391 dst
[0]->cat2
.condition
= IR3_COND_NE
;
395 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, create_immed(b
, fui(0.0)), 0);
396 dst
[0]->cat2
.condition
= IR3_COND_NE
;
399 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F16
);
402 dst
[0] = ir3_COV(b
, ir3_b2n(b
, src
[0]), TYPE_U32
, TYPE_F32
);
407 dst
[0] = ir3_b2n(b
, src
[0]);
410 struct ir3_instruction
*zero
= create_immed_typed(b
, 0, TYPE_S16
);
411 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, zero
, 0);
412 dst
[0]->cat2
.condition
= IR3_COND_NE
;
416 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, create_immed(b
, 0), 0);
417 dst
[0]->cat2
.condition
= IR3_COND_NE
;
421 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FNEG
);
424 dst
[0] = ir3_ABSNEG_F(b
, src
[0], IR3_REG_FABS
);
427 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[1], 0);
430 dst
[0] = ir3_MIN_F(b
, src
[0], 0, src
[1], 0);
433 /* if there is just a single use of the src, and it supports
434 * (sat) bit, we can just fold the (sat) flag back to the
435 * src instruction and create a mov. This is easier for cp
438 * TODO probably opc_cat==4 is ok too
440 if (alu
->src
[0].src
.is_ssa
&&
441 (list_length(&alu
->src
[0].src
.ssa
->uses
) == 1) &&
442 ((opc_cat(src
[0]->opc
) == 2) || (opc_cat(src
[0]->opc
) == 3))) {
443 src
[0]->flags
|= IR3_INSTR_SAT
;
444 dst
[0] = ir3_MOV(b
, src
[0], dst_type
);
446 /* otherwise generate a max.f that saturates.. blob does
447 * similar (generating a cat2 mov using max.f)
449 dst
[0] = ir3_MAX_F(b
, src
[0], 0, src
[0], 0);
450 dst
[0]->flags
|= IR3_INSTR_SAT
;
454 dst
[0] = ir3_MUL_F(b
, src
[0], 0, src
[1], 0);
457 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], 0);
460 dst
[0] = ir3_ADD_F(b
, src
[0], 0, src
[1], IR3_REG_FNEG
);
463 dst
[0] = ir3_MAD_F32(b
, src
[0], 0, src
[1], 0, src
[2], 0);
466 case nir_op_fddx_coarse
:
467 dst
[0] = ir3_DSX(b
, src
[0], 0);
468 dst
[0]->cat5
.type
= TYPE_F32
;
470 case nir_op_fddx_fine
:
471 dst
[0] = ir3_DSXPP_1(b
, src
[0], 0);
472 dst
[0]->cat5
.type
= TYPE_F32
;
475 case nir_op_fddy_coarse
:
476 dst
[0] = ir3_DSY(b
, src
[0], 0);
477 dst
[0]->cat5
.type
= TYPE_F32
;
480 case nir_op_fddy_fine
:
481 dst
[0] = ir3_DSYPP_1(b
, src
[0], 0);
482 dst
[0]->cat5
.type
= TYPE_F32
;
486 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
487 dst
[0]->cat2
.condition
= IR3_COND_LT
;
491 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
492 dst
[0]->cat2
.condition
= IR3_COND_GE
;
496 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
497 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
501 dst
[0] = ir3_CMPS_F(b
, src
[0], 0, src
[1], 0);
502 dst
[0]->cat2
.condition
= IR3_COND_NE
;
505 dst
[0] = ir3_CEIL_F(b
, src
[0], 0);
508 dst
[0] = ir3_FLOOR_F(b
, src
[0], 0);
511 dst
[0] = ir3_TRUNC_F(b
, src
[0], 0);
513 case nir_op_fround_even
:
514 dst
[0] = ir3_RNDNE_F(b
, src
[0], 0);
517 dst
[0] = ir3_SIGN_F(b
, src
[0], 0);
521 dst
[0] = ir3_SIN(b
, src
[0], 0);
524 dst
[0] = ir3_COS(b
, src
[0], 0);
527 dst
[0] = ir3_RSQ(b
, src
[0], 0);
530 dst
[0] = ir3_RCP(b
, src
[0], 0);
533 dst
[0] = ir3_LOG2(b
, src
[0], 0);
536 dst
[0] = ir3_EXP2(b
, src
[0], 0);
539 dst
[0] = ir3_SQRT(b
, src
[0], 0);
543 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SABS
);
546 dst
[0] = ir3_ADD_U(b
, src
[0], 0, src
[1], 0);
549 dst
[0] = ir3_AND_B(b
, src
[0], 0, src
[1], 0);
552 dst
[0] = ir3_MAX_S(b
, src
[0], 0, src
[1], 0);
555 dst
[0] = ir3_MAX_U(b
, src
[0], 0, src
[1], 0);
558 dst
[0] = ir3_MIN_S(b
, src
[0], 0, src
[1], 0);
561 dst
[0] = ir3_MIN_U(b
, src
[0], 0, src
[1], 0);
563 case nir_op_umul_low
:
564 dst
[0] = ir3_MULL_U(b
, src
[0], 0, src
[1], 0);
566 case nir_op_imadsh_mix16
:
567 dst
[0] = ir3_MADSH_M16(b
, src
[0], 0, src
[1], 0, src
[2], 0);
569 case nir_op_imad24_ir3
:
570 dst
[0] = ir3_MAD_S24(b
, src
[0], 0, src
[1], 0, src
[2], 0);
573 dst
[0] = ir3_MUL_S24(b
, src
[0], 0, src
[1], 0);
576 dst
[0] = ir3_ABSNEG_S(b
, src
[0], IR3_REG_SNEG
);
579 dst
[0] = ir3_NOT_B(b
, src
[0], 0);
582 dst
[0] = ir3_OR_B(b
, src
[0], 0, src
[1], 0);
585 dst
[0] = ir3_SHL_B(b
, src
[0], 0, src
[1], 0);
588 dst
[0] = ir3_ASHR_B(b
, src
[0], 0, src
[1], 0);
591 dst
[0] = ir3_SUB_U(b
, src
[0], 0, src
[1], 0);
594 dst
[0] = ir3_XOR_B(b
, src
[0], 0, src
[1], 0);
597 dst
[0] = ir3_SHR_B(b
, src
[0], 0, src
[1], 0);
601 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
602 dst
[0]->cat2
.condition
= IR3_COND_LT
;
606 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
607 dst
[0]->cat2
.condition
= IR3_COND_GE
;
611 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
612 dst
[0]->cat2
.condition
= IR3_COND_EQ
;
616 dst
[0] = ir3_CMPS_S(b
, src
[0], 0, src
[1], 0);
617 dst
[0]->cat2
.condition
= IR3_COND_NE
;
621 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
622 dst
[0]->cat2
.condition
= IR3_COND_LT
;
626 dst
[0] = ir3_CMPS_U(b
, src
[0], 0, src
[1], 0);
627 dst
[0]->cat2
.condition
= IR3_COND_GE
;
631 case nir_op_b32csel
: {
632 struct ir3_instruction
*cond
= ir3_b2n(b
, src
[0]);
634 if ((src
[0]->regs
[0]->flags
& IR3_REG_HALF
))
635 cond
->regs
[0]->flags
|= IR3_REG_HALF
;
637 compile_assert(ctx
, bs
[1] == bs
[2]);
638 /* Make sure the boolean condition has the same bit size as the other
639 * two arguments, adding a conversion if necessary.
642 cond
= ir3_COV(b
, cond
, TYPE_U32
, TYPE_U16
);
643 else if (bs
[1] > bs
[0])
644 cond
= ir3_COV(b
, cond
, TYPE_U16
, TYPE_U32
);
647 dst
[0] = ir3_SEL_B32(b
, src
[1], 0, cond
, 0, src
[2], 0);
649 dst
[0] = ir3_SEL_B16(b
, src
[1], 0, cond
, 0, src
[2], 0);
652 case nir_op_bit_count
: {
653 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
654 // double check on earlier gen's. Once half-precision support is
655 // in place, this should probably move to a NIR lowering pass:
656 struct ir3_instruction
*hi
, *lo
;
658 hi
= ir3_COV(b
, ir3_SHR_B(b
, src
[0], 0, create_immed(b
, 16), 0),
660 lo
= ir3_COV(b
, src
[0], TYPE_U32
, TYPE_U16
);
662 hi
= ir3_CBITS_B(b
, hi
, 0);
663 lo
= ir3_CBITS_B(b
, lo
, 0);
665 // TODO maybe the builders should default to making dst half-precision
666 // if the src's were half precision, to make this less awkward.. otoh
667 // we should probably just do this lowering in NIR.
668 hi
->regs
[0]->flags
|= IR3_REG_HALF
;
669 lo
->regs
[0]->flags
|= IR3_REG_HALF
;
671 dst
[0] = ir3_ADD_S(b
, hi
, 0, lo
, 0);
672 dst
[0]->regs
[0]->flags
|= IR3_REG_HALF
;
673 dst
[0] = ir3_COV(b
, dst
[0], TYPE_U16
, TYPE_U32
);
676 case nir_op_ifind_msb
: {
677 struct ir3_instruction
*cmp
;
678 dst
[0] = ir3_CLZ_S(b
, src
[0], 0);
679 cmp
= ir3_CMPS_S(b
, dst
[0], 0, create_immed(b
, 0), 0);
680 cmp
->cat2
.condition
= IR3_COND_GE
;
681 dst
[0] = ir3_SEL_B32(b
,
682 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
686 case nir_op_ufind_msb
:
687 dst
[0] = ir3_CLZ_B(b
, src
[0], 0);
688 dst
[0] = ir3_SEL_B32(b
,
689 ir3_SUB_U(b
, create_immed(b
, 31), 0, dst
[0], 0), 0,
690 src
[0], 0, dst
[0], 0);
692 case nir_op_find_lsb
:
693 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
694 dst
[0] = ir3_CLZ_B(b
, dst
[0], 0);
696 case nir_op_bitfield_reverse
:
697 dst
[0] = ir3_BFREV_B(b
, src
[0], 0);
701 ir3_context_error(ctx
, "Unhandled ALU op: %s\n",
702 nir_op_infos
[alu
->op
].name
);
706 if (nir_alu_type_get_base_type(info
->output_type
) == nir_type_bool
) {
709 if (nir_dest_bit_size(alu
->dest
.dest
) < 32)
710 dst
[0]->regs
[0]->flags
|= IR3_REG_HALF
;
712 dst
[0] = ir3_n2b(b
, dst
[0]);
715 if (nir_dest_bit_size(alu
->dest
.dest
) < 32) {
716 for (unsigned i
= 0; i
< dst_sz
; i
++) {
717 dst
[i
]->regs
[0]->flags
|= IR3_REG_HALF
;
721 ir3_put_dst(ctx
, &alu
->dest
.dest
);
725 emit_intrinsic_load_ubo_ldc(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
726 struct ir3_instruction
**dst
)
728 struct ir3_block
*b
= ctx
->block
;
730 unsigned ncomp
= intr
->num_components
;
731 struct ir3_instruction
*offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
732 struct ir3_instruction
*idx
= ir3_get_src(ctx
, &intr
->src
[0])[0];
733 struct ir3_instruction
*ldc
= ir3_LDC(b
, idx
, 0, offset
, 0);
734 ldc
->regs
[0]->wrmask
= MASK(ncomp
);
735 ldc
->cat6
.iim_val
= intr
->num_components
;
737 ldc
->cat6
.type
= TYPE_U32
;
739 nir_intrinsic_instr
*bindless
= ir3_bindless_resource(intr
->src
[0]);
741 ldc
->flags
|= IR3_INSTR_B
;
742 ldc
->cat6
.base
= nir_intrinsic_desc_set(bindless
);
743 ctx
->so
->bindless_ubo
= true;
746 ir3_split_dest(b
, dst
, ldc
, 0, ncomp
);
750 /* handles direct/indirect UBO reads: */
752 emit_intrinsic_load_ubo(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
753 struct ir3_instruction
**dst
)
755 if (ir3_bindless_resource(intr
->src
[0])) {
756 /* TODO: We should be using ldc for non-bindless things on a6xx as
759 emit_intrinsic_load_ubo_ldc(ctx
, intr
, dst
);
762 struct ir3_block
*b
= ctx
->block
;
763 struct ir3_instruction
*base_lo
, *base_hi
, *addr
, *src0
, *src1
;
764 /* UBO addresses are the first driver params, but subtract 2 here to
765 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
766 * is the uniforms: */
767 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
768 unsigned ubo
= regid(const_state
->offsets
.ubo
, 0) - 2;
769 const unsigned ptrsz
= ir3_pointer_size(ctx
->compiler
);
773 /* First src is ubo index, which could either be an immed or not: */
774 src0
= ir3_get_src(ctx
, &intr
->src
[0])[0];
775 if (is_same_type_mov(src0
) &&
776 (src0
->regs
[1]->flags
& IR3_REG_IMMED
)) {
777 base_lo
= create_uniform(b
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
));
778 base_hi
= create_uniform(b
, ubo
+ (src0
->regs
[1]->iim_val
* ptrsz
) + 1);
780 base_lo
= create_uniform_indirect(b
, ubo
, ir3_get_addr0(ctx
, src0
, ptrsz
));
781 base_hi
= create_uniform_indirect(b
, ubo
+ 1, ir3_get_addr0(ctx
, src0
, ptrsz
));
783 /* NOTE: since relative addressing is used, make sure constlen is
784 * at least big enough to cover all the UBO addresses, since the
785 * assembler won't know what the max address reg is.
787 ctx
->so
->constlen
= MAX2(ctx
->so
->constlen
,
788 const_state
->offsets
.ubo
+ (ctx
->s
->info
.num_ubos
* ptrsz
));
791 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
794 if (nir_src_is_const(intr
->src
[1])) {
795 off
+= nir_src_as_uint(intr
->src
[1]);
797 /* For load_ubo_indirect, second src is indirect offset: */
798 src1
= ir3_get_src(ctx
, &intr
->src
[1])[0];
800 /* and add offset to addr: */
801 addr
= ir3_ADD_S(b
, addr
, 0, src1
, 0);
804 /* if offset is to large to encode in the ldg, split it out: */
805 if ((off
+ (intr
->num_components
* 4)) > 1024) {
806 /* split out the minimal amount to improve the odds that
807 * cp can fit the immediate in the add.s instruction:
809 unsigned off2
= off
+ (intr
->num_components
* 4) - 1024;
810 addr
= ir3_ADD_S(b
, addr
, 0, create_immed(b
, off2
), 0);
815 struct ir3_instruction
*carry
;
817 /* handle 32b rollover, ie:
818 * if (addr < base_lo)
821 carry
= ir3_CMPS_U(b
, addr
, 0, base_lo
, 0);
822 carry
->cat2
.condition
= IR3_COND_LT
;
823 base_hi
= ir3_ADD_S(b
, base_hi
, 0, carry
, 0);
825 addr
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){ addr
, base_hi
}, 2);
828 for (int i
= 0; i
< intr
->num_components
; i
++) {
829 struct ir3_instruction
*load
=
830 ir3_LDG(b
, addr
, 0, create_immed(b
, 1), 0, /* num components */
831 create_immed(b
, off
+ i
* 4), 0);
832 load
->cat6
.type
= TYPE_U32
;
837 /* src[] = { block_index } */
839 emit_intrinsic_ssbo_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
840 struct ir3_instruction
**dst
)
842 /* SSBO size stored as a const starting at ssbo_sizes: */
843 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
844 unsigned blk_idx
= nir_src_as_uint(intr
->src
[0]);
845 unsigned idx
= regid(const_state
->offsets
.ssbo_sizes
, 0) +
846 const_state
->ssbo_size
.off
[blk_idx
];
848 debug_assert(const_state
->ssbo_size
.mask
& (1 << blk_idx
));
850 dst
[0] = create_uniform(ctx
->block
, idx
);
853 /* src[] = { offset }. const_index[] = { base } */
855 emit_intrinsic_load_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
856 struct ir3_instruction
**dst
)
858 struct ir3_block
*b
= ctx
->block
;
859 struct ir3_instruction
*ldl
, *offset
;
862 offset
= ir3_get_src(ctx
, &intr
->src
[0])[0];
863 base
= nir_intrinsic_base(intr
);
865 ldl
= ir3_LDL(b
, offset
, 0,
866 create_immed(b
, intr
->num_components
), 0,
867 create_immed(b
, base
), 0);
869 ldl
->cat6
.type
= utype_dst(intr
->dest
);
870 ldl
->regs
[0]->wrmask
= MASK(intr
->num_components
);
872 ldl
->barrier_class
= IR3_BARRIER_SHARED_R
;
873 ldl
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
875 ir3_split_dest(b
, dst
, ldl
, 0, intr
->num_components
);
878 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
880 emit_intrinsic_store_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
882 struct ir3_block
*b
= ctx
->block
;
883 struct ir3_instruction
*stl
, *offset
;
884 struct ir3_instruction
* const *value
;
885 unsigned base
, wrmask
;
887 value
= ir3_get_src(ctx
, &intr
->src
[0]);
888 offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
890 base
= nir_intrinsic_base(intr
);
891 wrmask
= nir_intrinsic_write_mask(intr
);
893 /* Combine groups of consecutive enabled channels in one write
894 * message. We use ffs to find the first enabled channel and then ffs on
895 * the bit-inverse, down-shifted writemask to determine the length of
896 * the block of enabled bits.
898 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
901 unsigned first_component
= ffs(wrmask
) - 1;
902 unsigned length
= ffs(~(wrmask
>> first_component
)) - 1;
904 stl
= ir3_STL(b
, offset
, 0,
905 ir3_create_collect(ctx
, &value
[first_component
], length
), 0,
906 create_immed(b
, length
), 0);
907 stl
->cat6
.dst_offset
= first_component
+ base
;
908 stl
->cat6
.type
= utype_src(intr
->src
[0]);
909 stl
->barrier_class
= IR3_BARRIER_SHARED_W
;
910 stl
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
912 array_insert(b
, b
->keeps
, stl
);
914 /* Clear the bits in the writemask that we just wrote, then try
915 * again to see if more channels are left.
917 wrmask
&= (15 << (first_component
+ length
));
921 /* src[] = { offset }. const_index[] = { base } */
923 emit_intrinsic_load_shared_ir3(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
924 struct ir3_instruction
**dst
)
926 struct ir3_block
*b
= ctx
->block
;
927 struct ir3_instruction
*load
, *offset
;
930 offset
= ir3_get_src(ctx
, &intr
->src
[0])[0];
931 base
= nir_intrinsic_base(intr
);
933 load
= ir3_LDLW(b
, offset
, 0,
934 create_immed(b
, intr
->num_components
), 0,
935 create_immed(b
, base
), 0);
937 load
->cat6
.type
= utype_dst(intr
->dest
);
938 load
->regs
[0]->wrmask
= MASK(intr
->num_components
);
940 load
->barrier_class
= IR3_BARRIER_SHARED_R
;
941 load
->barrier_conflict
= IR3_BARRIER_SHARED_W
;
943 ir3_split_dest(b
, dst
, load
, 0, intr
->num_components
);
946 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
948 emit_intrinsic_store_shared_ir3(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
950 struct ir3_block
*b
= ctx
->block
;
951 struct ir3_instruction
*store
, *offset
;
952 struct ir3_instruction
* const *value
;
953 unsigned base
, wrmask
;
955 value
= ir3_get_src(ctx
, &intr
->src
[0]);
956 offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
958 base
= nir_intrinsic_base(intr
);
959 wrmask
= nir_intrinsic_write_mask(intr
);
961 /* Combine groups of consecutive enabled channels in one write
962 * message. We use ffs to find the first enabled channel and then ffs on
963 * the bit-inverse, down-shifted writemask to determine the length of
964 * the block of enabled bits.
966 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
969 unsigned first_component
= ffs(wrmask
) - 1;
970 unsigned length
= ffs(~(wrmask
>> first_component
)) - 1;
972 store
= ir3_STLW(b
, offset
, 0,
973 ir3_create_collect(ctx
, &value
[first_component
], length
), 0,
974 create_immed(b
, length
), 0);
976 store
->cat6
.dst_offset
= first_component
+ base
;
977 store
->cat6
.type
= utype_src(intr
->src
[0]);
978 store
->barrier_class
= IR3_BARRIER_SHARED_W
;
979 store
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
981 array_insert(b
, b
->keeps
, store
);
983 /* Clear the bits in the writemask that we just wrote, then try
984 * again to see if more channels are left.
986 wrmask
&= (15 << (first_component
+ length
));
991 * CS shared variable atomic intrinsics
993 * All of the shared variable atomic memory operations read a value from
994 * memory, compute a new value using one of the operations below, write the
995 * new value to memory, and return the original value read.
997 * All operations take 2 sources except CompSwap that takes 3. These
1000 * 0: The offset into the shared variable storage region that the atomic
1001 * operation will operate on.
1002 * 1: The data parameter to the atomic function (i.e. the value to add
1003 * in shared_atomic_add, etc).
1004 * 2: For CompSwap only: the second data parameter.
1006 static struct ir3_instruction
*
1007 emit_intrinsic_atomic_shared(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1009 struct ir3_block
*b
= ctx
->block
;
1010 struct ir3_instruction
*atomic
, *src0
, *src1
;
1011 type_t type
= TYPE_U32
;
1013 src0
= ir3_get_src(ctx
, &intr
->src
[0])[0]; /* offset */
1014 src1
= ir3_get_src(ctx
, &intr
->src
[1])[0]; /* value */
1016 switch (intr
->intrinsic
) {
1017 case nir_intrinsic_shared_atomic_add
:
1018 atomic
= ir3_ATOMIC_ADD(b
, src0
, 0, src1
, 0);
1020 case nir_intrinsic_shared_atomic_imin
:
1021 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1024 case nir_intrinsic_shared_atomic_umin
:
1025 atomic
= ir3_ATOMIC_MIN(b
, src0
, 0, src1
, 0);
1027 case nir_intrinsic_shared_atomic_imax
:
1028 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1031 case nir_intrinsic_shared_atomic_umax
:
1032 atomic
= ir3_ATOMIC_MAX(b
, src0
, 0, src1
, 0);
1034 case nir_intrinsic_shared_atomic_and
:
1035 atomic
= ir3_ATOMIC_AND(b
, src0
, 0, src1
, 0);
1037 case nir_intrinsic_shared_atomic_or
:
1038 atomic
= ir3_ATOMIC_OR(b
, src0
, 0, src1
, 0);
1040 case nir_intrinsic_shared_atomic_xor
:
1041 atomic
= ir3_ATOMIC_XOR(b
, src0
, 0, src1
, 0);
1043 case nir_intrinsic_shared_atomic_exchange
:
1044 atomic
= ir3_ATOMIC_XCHG(b
, src0
, 0, src1
, 0);
1046 case nir_intrinsic_shared_atomic_comp_swap
:
1047 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1048 src1
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1049 ir3_get_src(ctx
, &intr
->src
[2])[0],
1052 atomic
= ir3_ATOMIC_CMPXCHG(b
, src0
, 0, src1
, 0);
1058 atomic
->cat6
.iim_val
= 1;
1060 atomic
->cat6
.type
= type
;
1061 atomic
->barrier_class
= IR3_BARRIER_SHARED_W
;
1062 atomic
->barrier_conflict
= IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
;
1064 /* even if nothing consume the result, we can't DCE the instruction: */
1065 array_insert(b
, b
->keeps
, atomic
);
1070 struct tex_src_info
{
1072 unsigned tex_base
, samp_base
, tex_idx
, samp_idx
;
1073 /* For normal tex instructions */
1074 unsigned base
, combined_idx
, a1_val
, flags
;
1075 struct ir3_instruction
*samp_tex
;
1078 /* TODO handle actual indirect/dynamic case.. which is going to be weird
1079 * to handle with the image_mapping table..
1081 static struct tex_src_info
1082 get_image_samp_tex_src(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1084 struct ir3_block
*b
= ctx
->block
;
1085 struct tex_src_info info
= { 0 };
1086 nir_intrinsic_instr
*bindless_tex
= ir3_bindless_resource(intr
->src
[0]);
1087 ctx
->so
->bindless_tex
= true;
1091 info
.flags
|= IR3_INSTR_B
;
1093 /* Gather information required to determine which encoding to
1094 * choose as well as for prefetch.
1096 info
.tex_base
= nir_intrinsic_desc_set(bindless_tex
);
1097 bool tex_const
= nir_src_is_const(bindless_tex
->src
[0]);
1099 info
.tex_idx
= nir_src_as_uint(bindless_tex
->src
[0]);
1102 /* Choose encoding. */
1103 if (tex_const
&& info
.tex_idx
< 256) {
1104 if (info
.tex_idx
< 16) {
1105 /* Everything fits within the instruction */
1106 info
.base
= info
.tex_base
;
1107 info
.combined_idx
= info
.samp_idx
| (info
.tex_idx
<< 4);
1109 info
.base
= info
.tex_base
;
1110 info
.a1_val
= info
.tex_idx
<< 3;
1111 info
.combined_idx
= 0;
1112 info
.flags
|= IR3_INSTR_A1EN
;
1114 info
.samp_tex
= NULL
;
1116 info
.flags
|= IR3_INSTR_S2EN
;
1117 info
.base
= info
.tex_base
;
1119 /* Note: the indirect source is now a vec2 instead of hvec2 */
1120 struct ir3_instruction
*texture
, *sampler
;
1122 texture
= ir3_get_src(ctx
, &intr
->src
[0])[0];
1123 sampler
= create_immed(b
, 0);
1124 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1130 info
.flags
|= IR3_INSTR_S2EN
;
1131 unsigned slot
= nir_src_as_uint(intr
->src
[0]);
1132 unsigned tex_idx
= ir3_image_to_tex(&ctx
->so
->image_mapping
, slot
);
1133 struct ir3_instruction
*texture
, *sampler
;
1135 texture
= create_immed_typed(ctx
->block
, tex_idx
, TYPE_U16
);
1136 sampler
= create_immed_typed(ctx
->block
, tex_idx
, TYPE_U16
);
1138 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1147 static struct ir3_instruction
*
1148 emit_sam(struct ir3_context
*ctx
, opc_t opc
, struct tex_src_info info
,
1149 type_t type
, unsigned wrmask
, struct ir3_instruction
*src0
,
1150 struct ir3_instruction
*src1
)
1152 struct ir3_instruction
*sam
, *addr
;
1153 if (info
.flags
& IR3_INSTR_A1EN
) {
1154 addr
= ir3_get_addr1(ctx
, info
.a1_val
);
1156 sam
= ir3_SAM(ctx
->block
, opc
, type
, 0b1111, info
.flags
,
1157 info
.samp_tex
, src0
, src1
);
1158 if (info
.flags
& IR3_INSTR_A1EN
) {
1159 ir3_instr_set_address(sam
, addr
);
1161 if (info
.flags
& IR3_INSTR_B
) {
1162 sam
->cat5
.tex_base
= info
.base
;
1163 sam
->cat5
.samp
= info
.combined_idx
;
1168 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1170 emit_intrinsic_load_image(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1171 struct ir3_instruction
**dst
)
1173 struct ir3_block
*b
= ctx
->block
;
1174 struct tex_src_info info
= get_image_samp_tex_src(ctx
, intr
);
1175 struct ir3_instruction
*sam
;
1176 struct ir3_instruction
* const *src0
= ir3_get_src(ctx
, &intr
->src
[1]);
1177 struct ir3_instruction
*coords
[4];
1178 unsigned flags
, ncoords
= ir3_get_image_coords(intr
, &flags
);
1179 type_t type
= ir3_get_type_for_image_intrinsic(intr
);
1181 /* hmm, this seems a bit odd, but it is what blob does and (at least
1182 * a5xx) just faults on bogus addresses otherwise:
1184 if (flags
& IR3_INSTR_3D
) {
1185 flags
&= ~IR3_INSTR_3D
;
1186 flags
|= IR3_INSTR_A
;
1188 info
.flags
|= flags
;
1190 for (unsigned i
= 0; i
< ncoords
; i
++)
1191 coords
[i
] = src0
[i
];
1194 coords
[ncoords
++] = create_immed(b
, 0);
1196 sam
= emit_sam(ctx
, OPC_ISAM
, info
, type
, 0b1111,
1197 ir3_create_collect(ctx
, coords
, ncoords
), NULL
);
1199 sam
->barrier_class
= IR3_BARRIER_IMAGE_R
;
1200 sam
->barrier_conflict
= IR3_BARRIER_IMAGE_W
;
1202 ir3_split_dest(b
, dst
, sam
, 0, 4);
1206 emit_intrinsic_image_size(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
,
1207 struct ir3_instruction
**dst
)
1209 struct ir3_block
*b
= ctx
->block
;
1210 struct tex_src_info info
= get_image_samp_tex_src(ctx
, intr
);
1211 struct ir3_instruction
*sam
, *lod
;
1212 unsigned flags
, ncoords
= ir3_get_image_coords(intr
, &flags
);
1213 type_t dst_type
= nir_dest_bit_size(intr
->dest
) < 32 ?
1214 TYPE_U16
: TYPE_U32
;
1216 info
.flags
|= flags
;
1217 lod
= create_immed(b
, 0);
1218 sam
= emit_sam(ctx
, OPC_GETSIZE
, info
, dst_type
, 0b1111, lod
, NULL
);
1220 /* Array size actually ends up in .w rather than .z. This doesn't
1221 * matter for miplevel 0, but for higher mips the value in z is
1222 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1223 * returned, which means that we have to add 1 to it for arrays for
1226 * Note use a temporary dst and then copy, since the size of the dst
1227 * array that is passed in is based on nir's understanding of the
1228 * result size, not the hardware's
1230 struct ir3_instruction
*tmp
[4];
1232 ir3_split_dest(b
, tmp
, sam
, 0, 4);
1234 /* get_size instruction returns size in bytes instead of texels
1235 * for imageBuffer, so we need to divide it by the pixel size
1236 * of the image format.
1238 * TODO: This is at least true on a5xx. Check other gens.
1240 if (nir_intrinsic_image_dim(intr
) == GLSL_SAMPLER_DIM_BUF
) {
1241 /* Since all the possible values the divisor can take are
1242 * power-of-two (4, 8, or 16), the division is implemented
1244 * During shader setup, the log2 of the image format's
1245 * bytes-per-pixel should have been emitted in 2nd slot of
1246 * image_dims. See ir3_shader::emit_image_dims().
1248 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
1249 unsigned cb
= regid(const_state
->offsets
.image_dims
, 0) +
1250 const_state
->image_dims
.off
[nir_src_as_uint(intr
->src
[0])];
1251 struct ir3_instruction
*aux
= create_uniform(b
, cb
+ 1);
1253 tmp
[0] = ir3_SHR_B(b
, tmp
[0], 0, aux
, 0);
1256 for (unsigned i
= 0; i
< ncoords
; i
++)
1259 if (flags
& IR3_INSTR_A
) {
1260 if (ctx
->compiler
->levels_add_one
) {
1261 dst
[ncoords
-1] = ir3_ADD_U(b
, tmp
[3], 0, create_immed(b
, 1), 0);
1263 dst
[ncoords
-1] = ir3_MOV(b
, tmp
[3], TYPE_U32
);
1269 emit_intrinsic_barrier(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1271 struct ir3_block
*b
= ctx
->block
;
1272 struct ir3_instruction
*barrier
;
1274 switch (intr
->intrinsic
) {
1275 case nir_intrinsic_control_barrier
:
1276 barrier
= ir3_BAR(b
);
1277 barrier
->cat7
.g
= true;
1278 barrier
->cat7
.l
= true;
1279 barrier
->flags
= IR3_INSTR_SS
| IR3_INSTR_SY
;
1280 barrier
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1282 case nir_intrinsic_memory_barrier
:
1283 barrier
= ir3_FENCE(b
);
1284 barrier
->cat7
.g
= true;
1285 barrier
->cat7
.r
= true;
1286 barrier
->cat7
.w
= true;
1287 barrier
->cat7
.l
= true;
1288 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
|
1289 IR3_BARRIER_BUFFER_W
;
1290 barrier
->barrier_conflict
=
1291 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1292 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1294 case nir_intrinsic_memory_barrier_buffer
:
1295 barrier
= ir3_FENCE(b
);
1296 barrier
->cat7
.g
= true;
1297 barrier
->cat7
.r
= true;
1298 barrier
->cat7
.w
= true;
1299 barrier
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1300 barrier
->barrier_conflict
= IR3_BARRIER_BUFFER_R
|
1301 IR3_BARRIER_BUFFER_W
;
1303 case nir_intrinsic_memory_barrier_image
:
1304 // TODO double check if this should have .g set
1305 barrier
= ir3_FENCE(b
);
1306 barrier
->cat7
.g
= true;
1307 barrier
->cat7
.r
= true;
1308 barrier
->cat7
.w
= true;
1309 barrier
->barrier_class
= IR3_BARRIER_IMAGE_W
;
1310 barrier
->barrier_conflict
= IR3_BARRIER_IMAGE_R
|
1311 IR3_BARRIER_IMAGE_W
;
1313 case nir_intrinsic_memory_barrier_shared
:
1314 barrier
= ir3_FENCE(b
);
1315 barrier
->cat7
.g
= true;
1316 barrier
->cat7
.l
= true;
1317 barrier
->cat7
.r
= true;
1318 barrier
->cat7
.w
= true;
1319 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
;
1320 barrier
->barrier_conflict
= IR3_BARRIER_SHARED_R
|
1321 IR3_BARRIER_SHARED_W
;
1323 case nir_intrinsic_group_memory_barrier
:
1324 barrier
= ir3_FENCE(b
);
1325 barrier
->cat7
.g
= true;
1326 barrier
->cat7
.l
= true;
1327 barrier
->cat7
.r
= true;
1328 barrier
->cat7
.w
= true;
1329 barrier
->barrier_class
= IR3_BARRIER_SHARED_W
|
1330 IR3_BARRIER_IMAGE_W
|
1331 IR3_BARRIER_BUFFER_W
;
1332 barrier
->barrier_conflict
=
1333 IR3_BARRIER_SHARED_R
| IR3_BARRIER_SHARED_W
|
1334 IR3_BARRIER_IMAGE_R
| IR3_BARRIER_IMAGE_W
|
1335 IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1341 /* make sure barrier doesn't get DCE'd */
1342 array_insert(b
, b
->keeps
, barrier
);
1345 static void add_sysval_input_compmask(struct ir3_context
*ctx
,
1346 gl_system_value slot
, unsigned compmask
,
1347 struct ir3_instruction
*instr
)
1349 struct ir3_shader_variant
*so
= ctx
->so
;
1350 unsigned n
= so
->inputs_count
++;
1352 assert(instr
->opc
== OPC_META_INPUT
);
1353 instr
->input
.inidx
= n
;
1354 instr
->input
.sysval
= slot
;
1356 so
->inputs
[n
].sysval
= true;
1357 so
->inputs
[n
].slot
= slot
;
1358 so
->inputs
[n
].compmask
= compmask
;
1359 so
->inputs
[n
].interpolate
= INTERP_MODE_FLAT
;
1363 static struct ir3_instruction
*
1364 create_sysval_input(struct ir3_context
*ctx
, gl_system_value slot
,
1368 struct ir3_instruction
*sysval
= create_input(ctx
, compmask
);
1369 add_sysval_input_compmask(ctx
, slot
, compmask
, sysval
);
1373 static struct ir3_instruction
*
1374 get_barycentric_centroid(struct ir3_context
*ctx
)
1376 if (!ctx
->ij_centroid
) {
1377 struct ir3_instruction
*xy
[2];
1378 struct ir3_instruction
*ij
;
1380 ij
= create_sysval_input(ctx
, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID
, 0x3);
1381 ir3_split_dest(ctx
->block
, xy
, ij
, 0, 2);
1383 ctx
->ij_centroid
= ir3_create_collect(ctx
, xy
, 2);
1386 return ctx
->ij_centroid
;
1389 static struct ir3_instruction
*
1390 get_barycentric_sample(struct ir3_context
*ctx
)
1392 if (!ctx
->ij_sample
) {
1393 struct ir3_instruction
*xy
[2];
1394 struct ir3_instruction
*ij
;
1396 ij
= create_sysval_input(ctx
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE
, 0x3);
1397 ir3_split_dest(ctx
->block
, xy
, ij
, 0, 2);
1399 ctx
->ij_sample
= ir3_create_collect(ctx
, xy
, 2);
1402 return ctx
->ij_sample
;
1405 static struct ir3_instruction
*
1406 get_barycentric_pixel(struct ir3_context
*ctx
)
1408 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1409 * this to create ij_pixel only on demand:
1411 return ctx
->ij_pixel
;
1414 static struct ir3_instruction
*
1415 get_frag_coord(struct ir3_context
*ctx
)
1417 if (!ctx
->frag_coord
) {
1418 struct ir3_block
*b
= ctx
->in_block
;
1419 struct ir3_instruction
*xyzw
[4];
1420 struct ir3_instruction
*hw_frag_coord
;
1422 hw_frag_coord
= create_sysval_input(ctx
, SYSTEM_VALUE_FRAG_COORD
, 0xf);
1423 ir3_split_dest(b
, xyzw
, hw_frag_coord
, 0, 4);
1425 /* for frag_coord.xy, we get unsigned values.. we need
1426 * to subtract (integer) 8 and divide by 16 (right-
1427 * shift by 4) then convert to float:
1431 * mov.u32f32 dst, tmp
1434 for (int i
= 0; i
< 2; i
++) {
1435 xyzw
[i
] = ir3_COV(b
, xyzw
[i
], TYPE_U32
, TYPE_F32
);
1436 xyzw
[i
] = ir3_MUL_F(b
, xyzw
[i
], 0, create_immed(b
, fui(1.0 / 16.0)), 0);
1439 ctx
->frag_coord
= ir3_create_collect(ctx
, xyzw
, 4);
1440 ctx
->so
->frag_coord
= true;
1443 return ctx
->frag_coord
;
1447 emit_intrinsic(struct ir3_context
*ctx
, nir_intrinsic_instr
*intr
)
1449 const nir_intrinsic_info
*info
= &nir_intrinsic_infos
[intr
->intrinsic
];
1450 struct ir3_instruction
**dst
;
1451 struct ir3_instruction
* const *src
;
1452 struct ir3_block
*b
= ctx
->block
;
1455 if (info
->has_dest
) {
1456 unsigned n
= nir_intrinsic_dest_components(intr
);
1457 dst
= ir3_get_dst(ctx
, &intr
->dest
, n
);
1462 const unsigned primitive_param
= ctx
->so
->shader
->const_state
.offsets
.primitive_param
* 4;
1463 const unsigned primitive_map
= ctx
->so
->shader
->const_state
.offsets
.primitive_map
* 4;
1465 switch (intr
->intrinsic
) {
1466 case nir_intrinsic_load_uniform
:
1467 idx
= nir_intrinsic_base(intr
);
1468 if (nir_src_is_const(intr
->src
[0])) {
1469 idx
+= nir_src_as_uint(intr
->src
[0]);
1470 for (int i
= 0; i
< intr
->num_components
; i
++) {
1471 dst
[i
] = create_uniform_typed(b
, idx
+ i
,
1472 nir_dest_bit_size(intr
->dest
) < 32 ? TYPE_F16
: TYPE_F32
);
1475 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1476 for (int i
= 0; i
< intr
->num_components
; i
++) {
1477 dst
[i
] = create_uniform_indirect(b
, idx
+ i
,
1478 ir3_get_addr0(ctx
, src
[0], 1));
1480 /* NOTE: if relative addressing is used, we set
1481 * constlen in the compiler (to worst-case value)
1482 * since we don't know in the assembler what the max
1483 * addr reg value can be:
1485 ctx
->so
->constlen
= MAX2(ctx
->so
->constlen
,
1486 ctx
->so
->shader
->ubo_state
.size
/ 16);
1490 case nir_intrinsic_load_vs_primitive_stride_ir3
:
1491 dst
[0] = create_uniform(b
, primitive_param
+ 0);
1493 case nir_intrinsic_load_vs_vertex_stride_ir3
:
1494 dst
[0] = create_uniform(b
, primitive_param
+ 1);
1496 case nir_intrinsic_load_hs_patch_stride_ir3
:
1497 dst
[0] = create_uniform(b
, primitive_param
+ 2);
1499 case nir_intrinsic_load_patch_vertices_in
:
1500 dst
[0] = create_uniform(b
, primitive_param
+ 3);
1502 case nir_intrinsic_load_tess_param_base_ir3
:
1503 dst
[0] = create_uniform(b
, primitive_param
+ 4);
1504 dst
[1] = create_uniform(b
, primitive_param
+ 5);
1506 case nir_intrinsic_load_tess_factor_base_ir3
:
1507 dst
[0] = create_uniform(b
, primitive_param
+ 6);
1508 dst
[1] = create_uniform(b
, primitive_param
+ 7);
1511 case nir_intrinsic_load_primitive_location_ir3
:
1512 idx
= nir_intrinsic_driver_location(intr
);
1513 dst
[0] = create_uniform(b
, primitive_map
+ idx
);
1516 case nir_intrinsic_load_gs_header_ir3
:
1517 dst
[0] = ctx
->gs_header
;
1519 case nir_intrinsic_load_tcs_header_ir3
:
1520 dst
[0] = ctx
->tcs_header
;
1523 case nir_intrinsic_load_primitive_id
:
1524 dst
[0] = ctx
->primitive_id
;
1527 case nir_intrinsic_load_tess_coord
:
1528 if (!ctx
->tess_coord
) {
1530 create_sysval_input(ctx
, SYSTEM_VALUE_TESS_COORD
, 0x3);
1532 ir3_split_dest(b
, dst
, ctx
->tess_coord
, 0, 2);
1534 /* Unused, but ir3_put_dst() below wants to free something */
1535 dst
[2] = create_immed(b
, 0);
1538 case nir_intrinsic_end_patch_ir3
:
1539 assert(ctx
->so
->type
== MESA_SHADER_TESS_CTRL
);
1540 struct ir3_instruction
*end
= ir3_ENDIF(b
);
1541 array_insert(b
, b
->keeps
, end
);
1543 end
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1544 end
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
1547 case nir_intrinsic_store_global_ir3
: {
1548 struct ir3_instruction
*value
, *addr
, *offset
;
1550 addr
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1551 ir3_get_src(ctx
, &intr
->src
[1])[0],
1552 ir3_get_src(ctx
, &intr
->src
[1])[1]
1555 offset
= ir3_get_src(ctx
, &intr
->src
[2])[0];
1557 value
= ir3_create_collect(ctx
, ir3_get_src(ctx
, &intr
->src
[0]),
1558 intr
->num_components
);
1560 struct ir3_instruction
*stg
=
1561 ir3_STG_G(ctx
->block
, addr
, 0, value
, 0,
1562 create_immed(ctx
->block
, intr
->num_components
), 0, offset
, 0);
1563 stg
->cat6
.type
= TYPE_U32
;
1564 stg
->cat6
.iim_val
= 1;
1566 array_insert(b
, b
->keeps
, stg
);
1568 stg
->barrier_class
= IR3_BARRIER_BUFFER_W
;
1569 stg
->barrier_conflict
= IR3_BARRIER_BUFFER_R
| IR3_BARRIER_BUFFER_W
;
1573 case nir_intrinsic_load_global_ir3
: {
1574 struct ir3_instruction
*addr
, *offset
;
1576 addr
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
1577 ir3_get_src(ctx
, &intr
->src
[0])[0],
1578 ir3_get_src(ctx
, &intr
->src
[0])[1]
1581 offset
= ir3_get_src(ctx
, &intr
->src
[1])[0];
1583 struct ir3_instruction
*load
=
1584 ir3_LDG(b
, addr
, 0, create_immed(ctx
->block
, intr
->num_components
),
1586 load
->cat6
.type
= TYPE_U32
;
1587 load
->regs
[0]->wrmask
= MASK(intr
->num_components
);
1589 load
->barrier_class
= IR3_BARRIER_BUFFER_R
;
1590 load
->barrier_conflict
= IR3_BARRIER_BUFFER_W
;
1592 ir3_split_dest(b
, dst
, load
, 0, intr
->num_components
);
1596 case nir_intrinsic_load_ubo
:
1597 emit_intrinsic_load_ubo(ctx
, intr
, dst
);
1599 case nir_intrinsic_load_frag_coord
:
1600 ir3_split_dest(b
, dst
, get_frag_coord(ctx
), 0, 4);
1602 case nir_intrinsic_load_sample_pos_from_id
: {
1603 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1604 * but that doesn't seem necessary.
1606 struct ir3_instruction
*offset
=
1607 ir3_RGETPOS(b
, ir3_get_src(ctx
, &intr
->src
[0])[0], 0);
1608 offset
->regs
[0]->wrmask
= 0x3;
1609 offset
->cat5
.type
= TYPE_F32
;
1611 ir3_split_dest(b
, dst
, offset
, 0, 2);
1615 case nir_intrinsic_load_size_ir3
:
1616 if (!ctx
->ij_size
) {
1618 create_sysval_input(ctx
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE
, 0x1);
1620 dst
[0] = ctx
->ij_size
;
1622 case nir_intrinsic_load_barycentric_centroid
:
1623 ir3_split_dest(b
, dst
, get_barycentric_centroid(ctx
), 0, 2);
1625 case nir_intrinsic_load_barycentric_sample
:
1626 if (ctx
->so
->key
.msaa
) {
1627 ir3_split_dest(b
, dst
, get_barycentric_sample(ctx
), 0, 2);
1629 ir3_split_dest(b
, dst
, get_barycentric_pixel(ctx
), 0, 2);
1632 case nir_intrinsic_load_barycentric_pixel
:
1633 ir3_split_dest(b
, dst
, get_barycentric_pixel(ctx
), 0, 2);
1635 case nir_intrinsic_load_interpolated_input
:
1636 idx
= nir_intrinsic_base(intr
);
1637 comp
= nir_intrinsic_component(intr
);
1638 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1639 if (nir_src_is_const(intr
->src
[1])) {
1640 struct ir3_instruction
*coord
= ir3_create_collect(ctx
, src
, 2);
1641 idx
+= nir_src_as_uint(intr
->src
[1]);
1642 for (int i
= 0; i
< intr
->num_components
; i
++) {
1643 unsigned inloc
= idx
* 4 + i
+ comp
;
1644 if (ctx
->so
->inputs
[idx
].bary
&&
1645 !ctx
->so
->inputs
[idx
].use_ldlv
) {
1646 dst
[i
] = ir3_BARY_F(b
, create_immed(b
, inloc
), 0, coord
, 0);
1648 /* for non-varyings use the pre-setup input, since
1649 * that is easier than mapping things back to a
1650 * nir_variable to figure out what it is.
1652 dst
[i
] = ctx
->inputs
[inloc
];
1653 compile_assert(ctx
, dst
[i
]);
1657 ir3_context_error(ctx
, "unhandled");
1660 case nir_intrinsic_load_input
:
1661 idx
= nir_intrinsic_base(intr
);
1662 comp
= nir_intrinsic_component(intr
);
1663 if (nir_src_is_const(intr
->src
[0])) {
1664 idx
+= nir_src_as_uint(intr
->src
[0]);
1665 for (int i
= 0; i
< intr
->num_components
; i
++) {
1666 unsigned n
= idx
* 4 + i
+ comp
;
1667 dst
[i
] = ctx
->inputs
[n
];
1668 compile_assert(ctx
, ctx
->inputs
[n
]);
1671 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1672 struct ir3_instruction
*collect
=
1673 ir3_create_collect(ctx
, ctx
->ir
->inputs
, ctx
->ninputs
);
1674 struct ir3_instruction
*addr
= ir3_get_addr0(ctx
, src
[0], 4);
1675 for (int i
= 0; i
< intr
->num_components
; i
++) {
1676 unsigned n
= idx
* 4 + i
+ comp
;
1677 dst
[i
] = create_indirect_load(ctx
, ctx
->ninputs
,
1682 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1683 * pass and replaced by an ir3-specifc version that adds the
1684 * dword-offset in the last source.
1686 case nir_intrinsic_load_ssbo_ir3
:
1687 ctx
->funcs
->emit_intrinsic_load_ssbo(ctx
, intr
, dst
);
1689 case nir_intrinsic_store_ssbo_ir3
:
1690 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1691 !ctx
->s
->info
.fs
.early_fragment_tests
)
1692 ctx
->so
->no_earlyz
= true;
1693 ctx
->funcs
->emit_intrinsic_store_ssbo(ctx
, intr
);
1695 case nir_intrinsic_get_buffer_size
:
1696 emit_intrinsic_ssbo_size(ctx
, intr
, dst
);
1698 case nir_intrinsic_ssbo_atomic_add_ir3
:
1699 case nir_intrinsic_ssbo_atomic_imin_ir3
:
1700 case nir_intrinsic_ssbo_atomic_umin_ir3
:
1701 case nir_intrinsic_ssbo_atomic_imax_ir3
:
1702 case nir_intrinsic_ssbo_atomic_umax_ir3
:
1703 case nir_intrinsic_ssbo_atomic_and_ir3
:
1704 case nir_intrinsic_ssbo_atomic_or_ir3
:
1705 case nir_intrinsic_ssbo_atomic_xor_ir3
:
1706 case nir_intrinsic_ssbo_atomic_exchange_ir3
:
1707 case nir_intrinsic_ssbo_atomic_comp_swap_ir3
:
1708 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1709 !ctx
->s
->info
.fs
.early_fragment_tests
)
1710 ctx
->so
->no_earlyz
= true;
1711 dst
[0] = ctx
->funcs
->emit_intrinsic_atomic_ssbo(ctx
, intr
);
1713 case nir_intrinsic_load_shared
:
1714 emit_intrinsic_load_shared(ctx
, intr
, dst
);
1716 case nir_intrinsic_store_shared
:
1717 emit_intrinsic_store_shared(ctx
, intr
);
1719 case nir_intrinsic_shared_atomic_add
:
1720 case nir_intrinsic_shared_atomic_imin
:
1721 case nir_intrinsic_shared_atomic_umin
:
1722 case nir_intrinsic_shared_atomic_imax
:
1723 case nir_intrinsic_shared_atomic_umax
:
1724 case nir_intrinsic_shared_atomic_and
:
1725 case nir_intrinsic_shared_atomic_or
:
1726 case nir_intrinsic_shared_atomic_xor
:
1727 case nir_intrinsic_shared_atomic_exchange
:
1728 case nir_intrinsic_shared_atomic_comp_swap
:
1729 dst
[0] = emit_intrinsic_atomic_shared(ctx
, intr
);
1731 case nir_intrinsic_image_load
:
1732 emit_intrinsic_load_image(ctx
, intr
, dst
);
1734 case nir_intrinsic_bindless_image_load
:
1735 /* Bindless uses the IBO state, which doesn't have swizzle filled out,
1736 * so using isam doesn't work.
1738 * TODO: can we use isam if we fill out more fields?
1740 ctx
->funcs
->emit_intrinsic_load_image(ctx
, intr
, dst
);
1742 case nir_intrinsic_image_store
:
1743 case nir_intrinsic_bindless_image_store
:
1744 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1745 !ctx
->s
->info
.fs
.early_fragment_tests
)
1746 ctx
->so
->no_earlyz
= true;
1747 ctx
->funcs
->emit_intrinsic_store_image(ctx
, intr
);
1749 case nir_intrinsic_image_size
:
1750 case nir_intrinsic_bindless_image_size
:
1751 emit_intrinsic_image_size(ctx
, intr
, dst
);
1753 case nir_intrinsic_image_atomic_add
:
1754 case nir_intrinsic_bindless_image_atomic_add
:
1755 case nir_intrinsic_image_atomic_imin
:
1756 case nir_intrinsic_bindless_image_atomic_imin
:
1757 case nir_intrinsic_image_atomic_umin
:
1758 case nir_intrinsic_bindless_image_atomic_umin
:
1759 case nir_intrinsic_image_atomic_imax
:
1760 case nir_intrinsic_bindless_image_atomic_imax
:
1761 case nir_intrinsic_image_atomic_umax
:
1762 case nir_intrinsic_bindless_image_atomic_umax
:
1763 case nir_intrinsic_image_atomic_and
:
1764 case nir_intrinsic_bindless_image_atomic_and
:
1765 case nir_intrinsic_image_atomic_or
:
1766 case nir_intrinsic_bindless_image_atomic_or
:
1767 case nir_intrinsic_image_atomic_xor
:
1768 case nir_intrinsic_bindless_image_atomic_xor
:
1769 case nir_intrinsic_image_atomic_exchange
:
1770 case nir_intrinsic_bindless_image_atomic_exchange
:
1771 case nir_intrinsic_image_atomic_comp_swap
:
1772 case nir_intrinsic_bindless_image_atomic_comp_swap
:
1773 if ((ctx
->so
->type
== MESA_SHADER_FRAGMENT
) &&
1774 !ctx
->s
->info
.fs
.early_fragment_tests
)
1775 ctx
->so
->no_earlyz
= true;
1776 dst
[0] = ctx
->funcs
->emit_intrinsic_atomic_image(ctx
, intr
);
1778 case nir_intrinsic_control_barrier
:
1779 case nir_intrinsic_memory_barrier
:
1780 case nir_intrinsic_group_memory_barrier
:
1781 case nir_intrinsic_memory_barrier_buffer
:
1782 case nir_intrinsic_memory_barrier_image
:
1783 case nir_intrinsic_memory_barrier_shared
:
1784 emit_intrinsic_barrier(ctx
, intr
);
1785 /* note that blk ptr no longer valid, make that obvious: */
1788 case nir_intrinsic_store_output
:
1789 idx
= nir_intrinsic_base(intr
);
1790 comp
= nir_intrinsic_component(intr
);
1791 compile_assert(ctx
, nir_src_is_const(intr
->src
[1]));
1792 idx
+= nir_src_as_uint(intr
->src
[1]);
1794 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1795 for (int i
= 0; i
< intr
->num_components
; i
++) {
1796 unsigned n
= idx
* 4 + i
+ comp
;
1797 ctx
->outputs
[n
] = src
[i
];
1800 case nir_intrinsic_load_base_vertex
:
1801 case nir_intrinsic_load_first_vertex
:
1802 if (!ctx
->basevertex
) {
1803 ctx
->basevertex
= create_driver_param(ctx
, IR3_DP_VTXID_BASE
);
1805 dst
[0] = ctx
->basevertex
;
1807 case nir_intrinsic_load_base_instance
:
1808 if (!ctx
->base_instance
) {
1809 ctx
->base_instance
= create_driver_param(ctx
, IR3_DP_INSTID_BASE
);
1811 dst
[0] = ctx
->base_instance
;
1813 case nir_intrinsic_load_vertex_id_zero_base
:
1814 case nir_intrinsic_load_vertex_id
:
1815 if (!ctx
->vertex_id
) {
1816 gl_system_value sv
= (intr
->intrinsic
== nir_intrinsic_load_vertex_id
) ?
1817 SYSTEM_VALUE_VERTEX_ID
: SYSTEM_VALUE_VERTEX_ID_ZERO_BASE
;
1818 ctx
->vertex_id
= create_sysval_input(ctx
, sv
, 0x1);
1820 dst
[0] = ctx
->vertex_id
;
1822 case nir_intrinsic_load_instance_id
:
1823 if (!ctx
->instance_id
) {
1824 ctx
->instance_id
= create_sysval_input(ctx
, SYSTEM_VALUE_INSTANCE_ID
, 0x1);
1826 dst
[0] = ctx
->instance_id
;
1828 case nir_intrinsic_load_sample_id
:
1829 ctx
->so
->per_samp
= true;
1831 case nir_intrinsic_load_sample_id_no_per_sample
:
1832 if (!ctx
->samp_id
) {
1833 ctx
->samp_id
= create_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_ID
, 0x1);
1834 ctx
->samp_id
->regs
[0]->flags
|= IR3_REG_HALF
;
1836 dst
[0] = ir3_COV(b
, ctx
->samp_id
, TYPE_U16
, TYPE_U32
);
1838 case nir_intrinsic_load_sample_mask_in
:
1839 if (!ctx
->samp_mask_in
) {
1840 ctx
->samp_mask_in
= create_sysval_input(ctx
, SYSTEM_VALUE_SAMPLE_MASK_IN
, 0x1);
1842 dst
[0] = ctx
->samp_mask_in
;
1844 case nir_intrinsic_load_user_clip_plane
:
1845 idx
= nir_intrinsic_ucp_id(intr
);
1846 for (int i
= 0; i
< intr
->num_components
; i
++) {
1847 unsigned n
= idx
* 4 + i
;
1848 dst
[i
] = create_driver_param(ctx
, IR3_DP_UCP0_X
+ n
);
1851 case nir_intrinsic_load_front_face
:
1852 if (!ctx
->frag_face
) {
1853 ctx
->so
->frag_face
= true;
1854 ctx
->frag_face
= create_sysval_input(ctx
, SYSTEM_VALUE_FRONT_FACE
, 0x1);
1855 ctx
->frag_face
->regs
[0]->flags
|= IR3_REG_HALF
;
1857 /* for fragface, we get -1 for back and 0 for front. However this is
1858 * the inverse of what nir expects (where ~0 is true).
1860 dst
[0] = ir3_COV(b
, ctx
->frag_face
, TYPE_S16
, TYPE_S32
);
1861 dst
[0] = ir3_NOT_B(b
, dst
[0], 0);
1863 case nir_intrinsic_load_local_invocation_id
:
1864 if (!ctx
->local_invocation_id
) {
1865 ctx
->local_invocation_id
=
1866 create_sysval_input(ctx
, SYSTEM_VALUE_LOCAL_INVOCATION_ID
, 0x7);
1868 ir3_split_dest(b
, dst
, ctx
->local_invocation_id
, 0, 3);
1870 case nir_intrinsic_load_work_group_id
:
1871 if (!ctx
->work_group_id
) {
1872 ctx
->work_group_id
=
1873 create_sysval_input(ctx
, SYSTEM_VALUE_WORK_GROUP_ID
, 0x7);
1874 ctx
->work_group_id
->regs
[0]->flags
|= IR3_REG_HIGH
;
1876 ir3_split_dest(b
, dst
, ctx
->work_group_id
, 0, 3);
1878 case nir_intrinsic_load_num_work_groups
:
1879 for (int i
= 0; i
< intr
->num_components
; i
++) {
1880 dst
[i
] = create_driver_param(ctx
, IR3_DP_NUM_WORK_GROUPS_X
+ i
);
1883 case nir_intrinsic_load_local_group_size
:
1884 for (int i
= 0; i
< intr
->num_components
; i
++) {
1885 dst
[i
] = create_driver_param(ctx
, IR3_DP_LOCAL_GROUP_SIZE_X
+ i
);
1888 case nir_intrinsic_discard_if
:
1889 case nir_intrinsic_discard
: {
1890 struct ir3_instruction
*cond
, *kill
;
1892 if (intr
->intrinsic
== nir_intrinsic_discard_if
) {
1893 /* conditional discard: */
1894 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1895 cond
= ir3_b2n(b
, src
[0]);
1897 /* unconditional discard: */
1898 cond
= create_immed(b
, 1);
1901 /* NOTE: only cmps.*.* can write p0.x: */
1902 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1903 cond
->cat2
.condition
= IR3_COND_NE
;
1905 /* condition always goes in predicate register: */
1906 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1907 cond
->regs
[0]->flags
&= ~IR3_REG_SSA
;
1909 kill
= ir3_KILL(b
, cond
, 0);
1910 kill
->regs
[1]->num
= regid(REG_P0
, 0);
1911 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
1913 array_insert(b
, b
->keeps
, kill
);
1914 ctx
->so
->no_earlyz
= true;
1919 case nir_intrinsic_cond_end_ir3
: {
1920 struct ir3_instruction
*cond
, *kill
;
1922 src
= ir3_get_src(ctx
, &intr
->src
[0]);
1923 cond
= ir3_b2n(b
, src
[0]);
1925 /* NOTE: only cmps.*.* can write p0.x: */
1926 cond
= ir3_CMPS_S(b
, cond
, 0, create_immed(b
, 0), 0);
1927 cond
->cat2
.condition
= IR3_COND_NE
;
1929 /* condition always goes in predicate register: */
1930 cond
->regs
[0]->num
= regid(REG_P0
, 0);
1932 kill
= ir3_IF(b
, cond
, 0);
1934 kill
->barrier_class
= IR3_BARRIER_EVERYTHING
;
1935 kill
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
1937 array_insert(ctx
->ir
, ctx
->ir
->predicates
, kill
);
1938 array_insert(b
, b
->keeps
, kill
);
1942 case nir_intrinsic_load_shared_ir3
:
1943 emit_intrinsic_load_shared_ir3(ctx
, intr
, dst
);
1945 case nir_intrinsic_store_shared_ir3
:
1946 emit_intrinsic_store_shared_ir3(ctx
, intr
);
1948 case nir_intrinsic_bindless_resource_ir3
:
1949 dst
[0] = ir3_get_src(ctx
, &intr
->src
[0])[0];
1952 ir3_context_error(ctx
, "Unhandled intrinsic type: %s\n",
1953 nir_intrinsic_infos
[intr
->intrinsic
].name
);
1958 ir3_put_dst(ctx
, &intr
->dest
);
1962 emit_load_const(struct ir3_context
*ctx
, nir_load_const_instr
*instr
)
1964 struct ir3_instruction
**dst
= ir3_get_dst_ssa(ctx
, &instr
->def
,
1965 instr
->def
.num_components
);
1967 if (instr
->def
.bit_size
< 32) {
1968 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1969 dst
[i
] = create_immed_typed(ctx
->block
,
1970 instr
->value
[i
].u16
,
1973 for (int i
= 0; i
< instr
->def
.num_components
; i
++)
1974 dst
[i
] = create_immed_typed(ctx
->block
,
1975 instr
->value
[i
].u32
,
1982 emit_undef(struct ir3_context
*ctx
, nir_ssa_undef_instr
*undef
)
1984 struct ir3_instruction
**dst
= ir3_get_dst_ssa(ctx
, &undef
->def
,
1985 undef
->def
.num_components
);
1986 type_t type
= (undef
->def
.bit_size
< 32) ? TYPE_U16
: TYPE_U32
;
1988 /* backend doesn't want undefined instructions, so just plug
1991 for (int i
= 0; i
< undef
->def
.num_components
; i
++)
1992 dst
[i
] = create_immed_typed(ctx
->block
, fui(0.0), type
);
1996 * texture fetch/sample instructions:
2000 get_tex_dest_type(nir_tex_instr
*tex
)
2004 switch (nir_alu_type_get_base_type(tex
->dest_type
)) {
2005 case nir_type_invalid
:
2006 case nir_type_float
:
2007 type
= nir_dest_bit_size(tex
->dest
) < 32 ? TYPE_F16
: TYPE_F32
;
2010 type
= nir_dest_bit_size(tex
->dest
) < 32 ? TYPE_S16
: TYPE_S32
;
2014 type
= nir_dest_bit_size(tex
->dest
) < 32 ? TYPE_U16
: TYPE_U32
;
2017 unreachable("bad dest_type");
2024 tex_info(nir_tex_instr
*tex
, unsigned *flagsp
, unsigned *coordsp
)
2026 unsigned coords
= glsl_get_sampler_dim_coordinate_components(tex
->sampler_dim
);
2029 /* note: would use tex->coord_components.. except txs.. also,
2030 * since array index goes after shadow ref, we don't want to
2034 flags
|= IR3_INSTR_3D
;
2036 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2037 flags
|= IR3_INSTR_S
;
2039 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
)
2040 flags
|= IR3_INSTR_A
;
2046 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
2047 * or immediate (in which case it will get lowered later to a non .s2en
2048 * version of the tex instruction which encode tex/samp as immediates:
2050 static struct tex_src_info
2051 get_tex_samp_tex_src(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2053 struct ir3_block
*b
= ctx
->block
;
2054 struct tex_src_info info
= { 0 };
2055 int texture_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_texture_handle
);
2056 int sampler_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_sampler_handle
);
2057 struct ir3_instruction
*texture
, *sampler
;
2059 if (texture_idx
>= 0 || sampler_idx
>= 0) {
2061 info
.flags
|= IR3_INSTR_B
;
2063 /* Gather information required to determine which encoding to
2064 * choose as well as for prefetch.
2066 nir_intrinsic_instr
*bindless_tex
= NULL
;
2068 if (texture_idx
>= 0) {
2069 ctx
->so
->bindless_tex
= true;
2070 bindless_tex
= ir3_bindless_resource(tex
->src
[texture_idx
].src
);
2071 assert(bindless_tex
);
2072 info
.tex_base
= nir_intrinsic_desc_set(bindless_tex
);
2073 tex_const
= nir_src_is_const(bindless_tex
->src
[0]);
2075 info
.tex_idx
= nir_src_as_uint(bindless_tex
->src
[0]);
2077 /* To simplify some of the logic below, assume the index is
2078 * constant 0 when it's not enabled.
2083 nir_intrinsic_instr
*bindless_samp
= NULL
;
2085 if (sampler_idx
>= 0) {
2086 ctx
->so
->bindless_samp
= true;
2087 bindless_samp
= ir3_bindless_resource(tex
->src
[sampler_idx
].src
);
2088 assert(bindless_samp
);
2089 info
.samp_base
= nir_intrinsic_desc_set(bindless_samp
);
2090 samp_const
= nir_src_is_const(bindless_samp
->src
[0]);
2092 info
.samp_idx
= nir_src_as_uint(bindless_samp
->src
[0]);
2098 /* Choose encoding. */
2099 if (tex_const
&& samp_const
&& info
.tex_idx
< 256 && info
.samp_idx
< 256) {
2100 if (info
.tex_idx
< 16 && info
.samp_idx
< 16 &&
2101 (!bindless_tex
|| !bindless_samp
|| info
.tex_base
== info
.samp_base
)) {
2102 /* Everything fits within the instruction */
2103 info
.base
= info
.tex_base
;
2104 info
.combined_idx
= info
.samp_idx
| (info
.tex_idx
<< 4);
2106 info
.base
= info
.tex_base
;
2107 info
.a1_val
= info
.tex_idx
<< 3 | info
.samp_base
;
2108 info
.combined_idx
= info
.samp_idx
;
2109 info
.flags
|= IR3_INSTR_A1EN
;
2111 info
.samp_tex
= NULL
;
2113 info
.flags
|= IR3_INSTR_S2EN
;
2114 /* In the indirect case, we only use a1.x to store the sampler
2115 * base if it differs from the texture base.
2117 if (!bindless_tex
|| !bindless_samp
|| info
.tex_base
== info
.samp_base
) {
2118 info
.base
= info
.tex_base
;
2120 info
.base
= info
.tex_base
;
2121 info
.a1_val
= info
.samp_base
;
2122 info
.flags
|= IR3_INSTR_A1EN
;
2125 /* Note: the indirect source is now a vec2 instead of hvec2, and
2126 * for some reason the texture and sampler are swapped.
2128 struct ir3_instruction
*texture
, *sampler
;
2131 texture
= ir3_get_src(ctx
, &tex
->src
[texture_idx
].src
)[0];
2133 texture
= create_immed(b
, 0);
2136 if (bindless_samp
) {
2137 sampler
= ir3_get_src(ctx
, &tex
->src
[sampler_idx
].src
)[0];
2139 sampler
= create_immed(b
, 0);
2141 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
2147 info
.flags
|= IR3_INSTR_S2EN
;
2148 texture_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_texture_offset
);
2149 sampler_idx
= nir_tex_instr_src_index(tex
, nir_tex_src_sampler_offset
);
2150 if (texture_idx
>= 0) {
2151 texture
= ir3_get_src(ctx
, &tex
->src
[texture_idx
].src
)[0];
2152 texture
= ir3_COV(ctx
->block
, texture
, TYPE_U32
, TYPE_U16
);
2154 /* TODO what to do for dynamic case? I guess we only need the
2155 * max index for astc srgb workaround so maybe not a problem
2156 * to worry about if we don't enable indirect samplers for
2159 ctx
->max_texture_index
= MAX2(ctx
->max_texture_index
, tex
->texture_index
);
2160 texture
= create_immed_typed(ctx
->block
, tex
->texture_index
, TYPE_U16
);
2161 info
.tex_idx
= tex
->texture_index
;
2164 if (sampler_idx
>= 0) {
2165 sampler
= ir3_get_src(ctx
, &tex
->src
[sampler_idx
].src
)[0];
2166 sampler
= ir3_COV(ctx
->block
, sampler
, TYPE_U32
, TYPE_U16
);
2168 sampler
= create_immed_typed(ctx
->block
, tex
->sampler_index
, TYPE_U16
);
2169 info
.samp_idx
= tex
->texture_index
;
2172 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
2182 emit_tex(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2184 struct ir3_block
*b
= ctx
->block
;
2185 struct ir3_instruction
**dst
, *sam
, *src0
[12], *src1
[4];
2186 struct ir3_instruction
* const *coord
, * const *off
, * const *ddx
, * const *ddy
;
2187 struct ir3_instruction
*lod
, *compare
, *proj
, *sample_index
;
2188 struct tex_src_info info
= { 0 };
2189 bool has_bias
= false, has_lod
= false, has_proj
= false, has_off
= false;
2190 unsigned i
, coords
, flags
, ncomp
;
2191 unsigned nsrc0
= 0, nsrc1
= 0;
2195 ncomp
= nir_dest_num_components(tex
->dest
);
2197 coord
= off
= ddx
= ddy
= NULL
;
2198 lod
= proj
= compare
= sample_index
= NULL
;
2200 dst
= ir3_get_dst(ctx
, &tex
->dest
, ncomp
);
2202 for (unsigned i
= 0; i
< tex
->num_srcs
; i
++) {
2203 switch (tex
->src
[i
].src_type
) {
2204 case nir_tex_src_coord
:
2205 coord
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
2207 case nir_tex_src_bias
:
2208 lod
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2211 case nir_tex_src_lod
:
2212 lod
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2215 case nir_tex_src_comparator
: /* shadow comparator */
2216 compare
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2218 case nir_tex_src_projector
:
2219 proj
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2222 case nir_tex_src_offset
:
2223 off
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
2226 case nir_tex_src_ddx
:
2227 ddx
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
2229 case nir_tex_src_ddy
:
2230 ddy
= ir3_get_src(ctx
, &tex
->src
[i
].src
);
2232 case nir_tex_src_ms_index
:
2233 sample_index
= ir3_get_src(ctx
, &tex
->src
[i
].src
)[0];
2235 case nir_tex_src_texture_offset
:
2236 case nir_tex_src_sampler_offset
:
2237 case nir_tex_src_texture_handle
:
2238 case nir_tex_src_sampler_handle
:
2239 /* handled in get_tex_samp_src() */
2242 ir3_context_error(ctx
, "Unhandled NIR tex src type: %d\n",
2243 tex
->src
[i
].src_type
);
2249 case nir_texop_tex_prefetch
:
2250 compile_assert(ctx
, !has_bias
);
2251 compile_assert(ctx
, !has_lod
);
2252 compile_assert(ctx
, !compare
);
2253 compile_assert(ctx
, !has_proj
);
2254 compile_assert(ctx
, !has_off
);
2255 compile_assert(ctx
, !ddx
);
2256 compile_assert(ctx
, !ddy
);
2257 compile_assert(ctx
, !sample_index
);
2258 compile_assert(ctx
, nir_tex_instr_src_index(tex
, nir_tex_src_texture_offset
) < 0);
2259 compile_assert(ctx
, nir_tex_instr_src_index(tex
, nir_tex_src_sampler_offset
) < 0);
2261 if (ctx
->so
->num_sampler_prefetch
< IR3_MAX_SAMPLER_PREFETCH
) {
2262 opc
= OPC_META_TEX_PREFETCH
;
2263 ctx
->so
->num_sampler_prefetch
++;
2267 case nir_texop_tex
: opc
= has_lod
? OPC_SAML
: OPC_SAM
; break;
2268 case nir_texop_txb
: opc
= OPC_SAMB
; break;
2269 case nir_texop_txl
: opc
= OPC_SAML
; break;
2270 case nir_texop_txd
: opc
= OPC_SAMGQ
; break;
2271 case nir_texop_txf
: opc
= OPC_ISAML
; break;
2272 case nir_texop_lod
: opc
= OPC_GETLOD
; break;
2274 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2275 * what blob does, seems gather is broken?), and a3xx did
2276 * not support it (but probably could also emulate).
2278 switch (tex
->component
) {
2279 case 0: opc
= OPC_GATHER4R
; break;
2280 case 1: opc
= OPC_GATHER4G
; break;
2281 case 2: opc
= OPC_GATHER4B
; break;
2282 case 3: opc
= OPC_GATHER4A
; break;
2285 case nir_texop_txf_ms_fb
:
2286 case nir_texop_txf_ms
: opc
= OPC_ISAMM
; break;
2288 ir3_context_error(ctx
, "Unhandled NIR tex type: %d\n", tex
->op
);
2292 tex_info(tex
, &flags
, &coords
);
2295 * lay out the first argument in the proper order:
2296 * - actual coordinates first
2297 * - shadow reference
2300 * - starting at offset 4, dpdx.xy, dpdy.xy
2302 * bias/lod go into the second arg
2305 /* insert tex coords: */
2306 for (i
= 0; i
< coords
; i
++)
2311 /* scale up integer coords for TXF based on the LOD */
2312 if (ctx
->compiler
->unminify_coords
&& (opc
== OPC_ISAML
)) {
2314 for (i
= 0; i
< coords
; i
++)
2315 src0
[i
] = ir3_SHL_B(b
, src0
[i
], 0, lod
, 0);
2319 /* hw doesn't do 1d, so we treat it as 2d with
2320 * height of 1, and patch up the y coord.
2323 src0
[nsrc0
++] = create_immed(b
, 0);
2325 src0
[nsrc0
++] = create_immed(b
, fui(0.5));
2329 if (tex
->is_shadow
&& tex
->op
!= nir_texop_lod
)
2330 src0
[nsrc0
++] = compare
;
2332 if (tex
->is_array
&& tex
->op
!= nir_texop_lod
) {
2333 struct ir3_instruction
*idx
= coord
[coords
];
2335 /* the array coord for cube arrays needs 0.5 added to it */
2336 if (ctx
->compiler
->array_index_add_half
&& !is_isam(opc
))
2337 idx
= ir3_ADD_F(b
, idx
, 0, create_immed(b
, fui(0.5)), 0);
2339 src0
[nsrc0
++] = idx
;
2343 src0
[nsrc0
++] = proj
;
2344 flags
|= IR3_INSTR_P
;
2347 /* pad to 4, then ddx/ddy: */
2348 if (tex
->op
== nir_texop_txd
) {
2350 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2351 for (i
= 0; i
< coords
; i
++)
2352 src0
[nsrc0
++] = ddx
[i
];
2354 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2355 for (i
= 0; i
< coords
; i
++)
2356 src0
[nsrc0
++] = ddy
[i
];
2358 src0
[nsrc0
++] = create_immed(b
, fui(0.0));
2361 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2362 * with scaled x coord according to requested sample:
2364 if (opc
== OPC_ISAMM
) {
2365 if (ctx
->compiler
->txf_ms_with_isaml
) {
2366 /* the samples are laid out in x dimension as
2368 * x_ms = (x << ms) + sample_index;
2370 struct ir3_instruction
*ms
;
2371 ms
= create_immed(b
, (ctx
->samples
>> (2 * tex
->texture_index
)) & 3);
2373 src0
[0] = ir3_SHL_B(b
, src0
[0], 0, ms
, 0);
2374 src0
[0] = ir3_ADD_U(b
, src0
[0], 0, sample_index
, 0);
2378 src0
[nsrc0
++] = sample_index
;
2383 * second argument (if applicable):
2388 if (has_off
| has_lod
| has_bias
) {
2390 unsigned off_coords
= coords
;
2391 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2393 for (i
= 0; i
< off_coords
; i
++)
2394 src1
[nsrc1
++] = off
[i
];
2396 src1
[nsrc1
++] = create_immed(b
, fui(0.0));
2397 flags
|= IR3_INSTR_O
;
2400 if (has_lod
| has_bias
)
2401 src1
[nsrc1
++] = lod
;
2404 type
= get_tex_dest_type(tex
);
2406 if (opc
== OPC_GETLOD
)
2410 if (tex
->op
== nir_texop_txf_ms_fb
) {
2411 /* only expect a single txf_ms_fb per shader: */
2412 compile_assert(ctx
, !ctx
->so
->fb_read
);
2413 compile_assert(ctx
, ctx
->so
->type
== MESA_SHADER_FRAGMENT
);
2415 ctx
->so
->fb_read
= true;
2416 info
.samp_tex
= ir3_create_collect(ctx
, (struct ir3_instruction
*[]){
2417 create_immed_typed(ctx
->block
, ctx
->so
->num_samp
, TYPE_U16
),
2418 create_immed_typed(ctx
->block
, ctx
->so
->num_samp
, TYPE_U16
),
2420 info
.flags
= IR3_INSTR_S2EN
;
2422 ctx
->so
->num_samp
++;
2424 info
= get_tex_samp_tex_src(ctx
, tex
);
2427 struct ir3_instruction
*col0
= ir3_create_collect(ctx
, src0
, nsrc0
);
2428 struct ir3_instruction
*col1
= ir3_create_collect(ctx
, src1
, nsrc1
);
2430 if (opc
== OPC_META_TEX_PREFETCH
) {
2431 int idx
= nir_tex_instr_src_index(tex
, nir_tex_src_coord
);
2433 compile_assert(ctx
, tex
->src
[idx
].src
.is_ssa
);
2435 sam
= ir3_META_TEX_PREFETCH(b
);
2436 __ssa_dst(sam
)->wrmask
= MASK(ncomp
); /* dst */
2437 __ssa_src(sam
, get_barycentric_pixel(ctx
), 0);
2438 sam
->prefetch
.input_offset
=
2439 ir3_nir_coord_offset(tex
->src
[idx
].src
.ssa
);
2440 /* make sure not to add irrelevant flags like S2EN */
2441 sam
->flags
= flags
| (info
.flags
& IR3_INSTR_B
);
2442 sam
->prefetch
.tex
= info
.tex_idx
;
2443 sam
->prefetch
.samp
= info
.samp_idx
;
2444 sam
->prefetch
.tex_base
= info
.tex_base
;
2445 sam
->prefetch
.samp_base
= info
.samp_base
;
2447 info
.flags
|= flags
;
2448 sam
= emit_sam(ctx
, opc
, info
, type
, MASK(ncomp
), col0
, col1
);
2451 if ((ctx
->astc_srgb
& (1 << tex
->texture_index
)) && !nir_tex_instr_is_query(tex
)) {
2452 assert(opc
!= OPC_META_TEX_PREFETCH
);
2454 /* only need first 3 components: */
2455 sam
->regs
[0]->wrmask
= 0x7;
2456 ir3_split_dest(b
, dst
, sam
, 0, 3);
2458 /* we need to sample the alpha separately with a non-ASTC
2461 sam
= ir3_SAM(b
, opc
, type
, 0b1000, flags
| info
.flags
,
2462 info
.samp_tex
, col0
, col1
);
2464 array_insert(ctx
->ir
, ctx
->ir
->astc_srgb
, sam
);
2466 /* fixup .w component: */
2467 ir3_split_dest(b
, &dst
[3], sam
, 3, 1);
2469 /* normal (non-workaround) case: */
2470 ir3_split_dest(b
, dst
, sam
, 0, ncomp
);
2473 /* GETLOD returns results in 4.8 fixed point */
2474 if (opc
== OPC_GETLOD
) {
2475 struct ir3_instruction
*factor
= create_immed(b
, fui(1.0 / 256));
2477 compile_assert(ctx
, tex
->dest_type
== nir_type_float
);
2478 for (i
= 0; i
< 2; i
++) {
2479 dst
[i
] = ir3_MUL_F(b
, ir3_COV(b
, dst
[i
], TYPE_S32
, TYPE_F32
), 0,
2484 ir3_put_dst(ctx
, &tex
->dest
);
2488 emit_tex_info(struct ir3_context
*ctx
, nir_tex_instr
*tex
, unsigned idx
)
2490 struct ir3_block
*b
= ctx
->block
;
2491 struct ir3_instruction
**dst
, *sam
;
2492 type_t dst_type
= get_tex_dest_type(tex
);
2493 struct tex_src_info info
= get_tex_samp_tex_src(ctx
, tex
);
2495 dst
= ir3_get_dst(ctx
, &tex
->dest
, 1);
2497 sam
= emit_sam(ctx
, OPC_GETINFO
, info
, dst_type
, 1 << idx
, NULL
, NULL
);
2499 /* even though there is only one component, since it ends
2500 * up in .y/.z/.w rather than .x, we need a split_dest()
2503 ir3_split_dest(b
, dst
, sam
, 0, idx
+ 1);
2505 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2506 * the value in TEX_CONST_0 is zero-based.
2508 if (ctx
->compiler
->levels_add_one
)
2509 dst
[0] = ir3_ADD_U(b
, dst
[0], 0, create_immed(b
, 1), 0);
2511 ir3_put_dst(ctx
, &tex
->dest
);
2515 emit_tex_txs(struct ir3_context
*ctx
, nir_tex_instr
*tex
)
2517 struct ir3_block
*b
= ctx
->block
;
2518 struct ir3_instruction
**dst
, *sam
;
2519 struct ir3_instruction
*lod
;
2520 unsigned flags
, coords
;
2521 type_t dst_type
= get_tex_dest_type(tex
);
2522 struct tex_src_info info
= get_tex_samp_tex_src(ctx
, tex
);
2524 tex_info(tex
, &flags
, &coords
);
2525 info
.flags
|= flags
;
2527 /* Actually we want the number of dimensions, not coordinates. This
2528 * distinction only matters for cubes.
2530 if (tex
->sampler_dim
== GLSL_SAMPLER_DIM_CUBE
)
2533 dst
= ir3_get_dst(ctx
, &tex
->dest
, 4);
2535 compile_assert(ctx
, tex
->num_srcs
== 1);
2536 compile_assert(ctx
, tex
->src
[0].src_type
== nir_tex_src_lod
);
2538 lod
= ir3_get_src(ctx
, &tex
->src
[0].src
)[0];
2540 sam
= emit_sam(ctx
, OPC_GETSIZE
, info
, dst_type
, 0b1111, lod
, NULL
);
2541 ir3_split_dest(b
, dst
, sam
, 0, 4);
2543 /* Array size actually ends up in .w rather than .z. This doesn't
2544 * matter for miplevel 0, but for higher mips the value in z is
2545 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2546 * returned, which means that we have to add 1 to it for arrays.
2548 if (tex
->is_array
) {
2549 if (ctx
->compiler
->levels_add_one
) {
2550 dst
[coords
] = ir3_ADD_U(b
, dst
[3], 0, create_immed(b
, 1), 0);
2552 dst
[coords
] = ir3_MOV(b
, dst
[3], TYPE_U32
);
2556 ir3_put_dst(ctx
, &tex
->dest
);
2560 emit_jump(struct ir3_context
*ctx
, nir_jump_instr
*jump
)
2562 switch (jump
->type
) {
2563 case nir_jump_break
:
2564 case nir_jump_continue
:
2565 case nir_jump_return
:
2566 /* I *think* we can simply just ignore this, and use the
2567 * successor block link to figure out where we need to
2568 * jump to for break/continue
2572 ir3_context_error(ctx
, "Unhandled NIR jump type: %d\n", jump
->type
);
2578 emit_instr(struct ir3_context
*ctx
, nir_instr
*instr
)
2580 switch (instr
->type
) {
2581 case nir_instr_type_alu
:
2582 emit_alu(ctx
, nir_instr_as_alu(instr
));
2584 case nir_instr_type_deref
:
2585 /* ignored, handled as part of the intrinsic they are src to */
2587 case nir_instr_type_intrinsic
:
2588 emit_intrinsic(ctx
, nir_instr_as_intrinsic(instr
));
2590 case nir_instr_type_load_const
:
2591 emit_load_const(ctx
, nir_instr_as_load_const(instr
));
2593 case nir_instr_type_ssa_undef
:
2594 emit_undef(ctx
, nir_instr_as_ssa_undef(instr
));
2596 case nir_instr_type_tex
: {
2597 nir_tex_instr
*tex
= nir_instr_as_tex(instr
);
2598 /* couple tex instructions get special-cased:
2602 emit_tex_txs(ctx
, tex
);
2604 case nir_texop_query_levels
:
2605 emit_tex_info(ctx
, tex
, 2);
2607 case nir_texop_texture_samples
:
2608 emit_tex_info(ctx
, tex
, 3);
2616 case nir_instr_type_jump
:
2617 emit_jump(ctx
, nir_instr_as_jump(instr
));
2619 case nir_instr_type_phi
:
2620 /* we have converted phi webs to regs in NIR by now */
2621 ir3_context_error(ctx
, "Unexpected NIR instruction type: %d\n", instr
->type
);
2623 case nir_instr_type_call
:
2624 case nir_instr_type_parallel_copy
:
2625 ir3_context_error(ctx
, "Unhandled NIR instruction type: %d\n", instr
->type
);
2630 static struct ir3_block
*
2631 get_block(struct ir3_context
*ctx
, const nir_block
*nblock
)
2633 struct ir3_block
*block
;
2634 struct hash_entry
*hentry
;
2636 hentry
= _mesa_hash_table_search(ctx
->block_ht
, nblock
);
2638 return hentry
->data
;
2640 block
= ir3_block_create(ctx
->ir
);
2641 block
->nblock
= nblock
;
2642 _mesa_hash_table_insert(ctx
->block_ht
, nblock
, block
);
2644 block
->predecessors
= _mesa_pointer_set_create(block
);
2645 set_foreach(nblock
->predecessors
, sentry
) {
2646 _mesa_set_add(block
->predecessors
, get_block(ctx
, sentry
->key
));
2653 emit_block(struct ir3_context
*ctx
, nir_block
*nblock
)
2655 struct ir3_block
*block
= get_block(ctx
, nblock
);
2657 for (int i
= 0; i
< ARRAY_SIZE(block
->successors
); i
++) {
2658 if (nblock
->successors
[i
]) {
2659 block
->successors
[i
] =
2660 get_block(ctx
, nblock
->successors
[i
]);
2665 list_addtail(&block
->node
, &ctx
->ir
->block_list
);
2667 /* re-emit addr register in each block if needed: */
2668 for (int i
= 0; i
< ARRAY_SIZE(ctx
->addr0_ht
); i
++) {
2669 _mesa_hash_table_destroy(ctx
->addr0_ht
[i
], NULL
);
2670 ctx
->addr0_ht
[i
] = NULL
;
2673 _mesa_hash_table_u64_destroy(ctx
->addr1_ht
, NULL
);
2674 ctx
->addr1_ht
= NULL
;
2676 nir_foreach_instr (instr
, nblock
) {
2677 ctx
->cur_instr
= instr
;
2678 emit_instr(ctx
, instr
);
2679 ctx
->cur_instr
= NULL
;
2685 static void emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
);
2688 emit_if(struct ir3_context
*ctx
, nir_if
*nif
)
2690 struct ir3_instruction
*condition
= ir3_get_src(ctx
, &nif
->condition
)[0];
2692 ctx
->block
->condition
=
2693 ir3_get_predicate(ctx
, ir3_b2n(condition
->block
, condition
));
2695 emit_cf_list(ctx
, &nif
->then_list
);
2696 emit_cf_list(ctx
, &nif
->else_list
);
2700 emit_loop(struct ir3_context
*ctx
, nir_loop
*nloop
)
2702 emit_cf_list(ctx
, &nloop
->body
);
2707 stack_push(struct ir3_context
*ctx
)
2710 ctx
->max_stack
= MAX2(ctx
->max_stack
, ctx
->stack
);
2714 stack_pop(struct ir3_context
*ctx
)
2716 compile_assert(ctx
, ctx
->stack
> 0);
2721 emit_cf_list(struct ir3_context
*ctx
, struct exec_list
*list
)
2723 foreach_list_typed (nir_cf_node
, node
, node
, list
) {
2724 switch (node
->type
) {
2725 case nir_cf_node_block
:
2726 emit_block(ctx
, nir_cf_node_as_block(node
));
2728 case nir_cf_node_if
:
2730 emit_if(ctx
, nir_cf_node_as_if(node
));
2733 case nir_cf_node_loop
:
2735 emit_loop(ctx
, nir_cf_node_as_loop(node
));
2738 case nir_cf_node_function
:
2739 ir3_context_error(ctx
, "TODO\n");
2745 /* emit stream-out code. At this point, the current block is the original
2746 * (nir) end block, and nir ensures that all flow control paths terminate
2747 * into the end block. We re-purpose the original end block to generate
2748 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2749 * block holding stream-out write instructions, followed by the new end
2753 * p0.x = (vtxcnt < maxvtxcnt)
2754 * // succs: blockStreamOut, blockNewEnd
2757 * ... stream-out instructions ...
2758 * // succs: blockNewEnd
2764 emit_stream_out(struct ir3_context
*ctx
)
2766 struct ir3
*ir
= ctx
->ir
;
2767 struct ir3_stream_output_info
*strmout
=
2768 &ctx
->so
->shader
->stream_output
;
2769 struct ir3_block
*orig_end_block
, *stream_out_block
, *new_end_block
;
2770 struct ir3_instruction
*vtxcnt
, *maxvtxcnt
, *cond
;
2771 struct ir3_instruction
*bases
[IR3_MAX_SO_BUFFERS
];
2773 /* create vtxcnt input in input block at top of shader,
2774 * so that it is seen as live over the entire duration
2777 vtxcnt
= create_sysval_input(ctx
, SYSTEM_VALUE_VERTEX_CNT
, 0x1);
2778 maxvtxcnt
= create_driver_param(ctx
, IR3_DP_VTXCNT_MAX
);
2780 /* at this point, we are at the original 'end' block,
2781 * re-purpose this block to stream-out condition, then
2782 * append stream-out block and new-end block
2784 orig_end_block
= ctx
->block
;
2786 // TODO these blocks need to update predecessors..
2787 // maybe w/ store_global intrinsic, we could do this
2788 // stuff in nir->nir pass
2790 stream_out_block
= ir3_block_create(ir
);
2791 list_addtail(&stream_out_block
->node
, &ir
->block_list
);
2793 new_end_block
= ir3_block_create(ir
);
2794 list_addtail(&new_end_block
->node
, &ir
->block_list
);
2796 orig_end_block
->successors
[0] = stream_out_block
;
2797 orig_end_block
->successors
[1] = new_end_block
;
2798 stream_out_block
->successors
[0] = new_end_block
;
2800 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2801 cond
= ir3_CMPS_S(ctx
->block
, vtxcnt
, 0, maxvtxcnt
, 0);
2802 cond
->regs
[0]->num
= regid(REG_P0
, 0);
2803 cond
->regs
[0]->flags
&= ~IR3_REG_SSA
;
2804 cond
->cat2
.condition
= IR3_COND_LT
;
2806 /* condition goes on previous block to the conditional,
2807 * since it is used to pick which of the two successor
2810 orig_end_block
->condition
= cond
;
2812 /* switch to stream_out_block to generate the stream-out
2815 ctx
->block
= stream_out_block
;
2817 /* Calculate base addresses based on vtxcnt. Instructions
2818 * generated for bases not used in following loop will be
2819 * stripped out in the backend.
2821 for (unsigned i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
2822 struct ir3_const_state
*const_state
= &ctx
->so
->shader
->const_state
;
2823 unsigned stride
= strmout
->stride
[i
];
2824 struct ir3_instruction
*base
, *off
;
2826 base
= create_uniform(ctx
->block
, regid(const_state
->offsets
.tfbo
, i
));
2828 /* 24-bit should be enough: */
2829 off
= ir3_MUL_U24(ctx
->block
, vtxcnt
, 0,
2830 create_immed(ctx
->block
, stride
* 4), 0);
2832 bases
[i
] = ir3_ADD_S(ctx
->block
, off
, 0, base
, 0);
2835 /* Generate the per-output store instructions: */
2836 for (unsigned i
= 0; i
< strmout
->num_outputs
; i
++) {
2837 for (unsigned j
= 0; j
< strmout
->output
[i
].num_components
; j
++) {
2838 unsigned c
= j
+ strmout
->output
[i
].start_component
;
2839 struct ir3_instruction
*base
, *out
, *stg
;
2841 base
= bases
[strmout
->output
[i
].output_buffer
];
2842 out
= ctx
->ir
->outputs
[regid(strmout
->output
[i
].register_index
, c
)];
2844 stg
= ir3_STG(ctx
->block
, base
, 0, out
, 0,
2845 create_immed(ctx
->block
, 1), 0);
2846 stg
->cat6
.type
= TYPE_U32
;
2847 stg
->cat6
.dst_offset
= (strmout
->output
[i
].dst_offset
+ j
) * 4;
2849 array_insert(ctx
->block
, ctx
->block
->keeps
, stg
);
2853 /* and finally switch to the new_end_block: */
2854 ctx
->block
= new_end_block
;
2858 emit_function(struct ir3_context
*ctx
, nir_function_impl
*impl
)
2860 nir_metadata_require(impl
, nir_metadata_block_index
);
2862 compile_assert(ctx
, ctx
->stack
== 0);
2864 emit_cf_list(ctx
, &impl
->body
);
2865 emit_block(ctx
, impl
->end_block
);
2867 compile_assert(ctx
, ctx
->stack
== 0);
2869 /* at this point, we should have a single empty block,
2870 * into which we emit the 'end' instruction.
2872 compile_assert(ctx
, list_is_empty(&ctx
->block
->instr_list
));
2874 /* If stream-out (aka transform-feedback) enabled, emit the
2875 * stream-out instructions, followed by a new empty block (into
2876 * which the 'end' instruction lands).
2878 * NOTE: it is done in this order, rather than inserting before
2879 * we emit end_block, because NIR guarantees that all blocks
2880 * flow into end_block, and that end_block has no successors.
2881 * So by re-purposing end_block as the first block of stream-
2882 * out, we guarantee that all exit paths flow into the stream-
2885 if ((ctx
->compiler
->gpu_id
< 500) &&
2886 (ctx
->so
->shader
->stream_output
.num_outputs
> 0) &&
2887 !ctx
->so
->binning_pass
) {
2888 debug_assert(ctx
->so
->type
== MESA_SHADER_VERTEX
);
2889 emit_stream_out(ctx
);
2892 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2893 * NOP and has an epilogue that writes the VS outputs to local storage, to
2894 * be read by the HS. Then it resets execution mask (chmask) and chains
2895 * to the next shader (chsh).
2897 if ((ctx
->so
->type
== MESA_SHADER_VERTEX
&&
2898 (ctx
->so
->key
.has_gs
|| ctx
->so
->key
.tessellation
)) ||
2899 (ctx
->so
->type
== MESA_SHADER_TESS_EVAL
&& ctx
->so
->key
.has_gs
)) {
2900 struct ir3_instruction
*chmask
=
2901 ir3_CHMASK(ctx
->block
);
2902 chmask
->barrier_class
= IR3_BARRIER_EVERYTHING
;
2903 chmask
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
2905 struct ir3_instruction
*chsh
=
2906 ir3_CHSH(ctx
->block
);
2907 chsh
->barrier_class
= IR3_BARRIER_EVERYTHING
;
2908 chsh
->barrier_conflict
= IR3_BARRIER_EVERYTHING
;
2910 ir3_END(ctx
->block
);
2915 setup_input(struct ir3_context
*ctx
, nir_variable
*in
)
2917 struct ir3_shader_variant
*so
= ctx
->so
;
2918 unsigned ncomp
= glsl_get_components(in
->type
);
2919 unsigned n
= in
->data
.driver_location
;
2920 unsigned frac
= in
->data
.location_frac
;
2921 unsigned slot
= in
->data
.location
;
2923 /* Inputs are loaded using ldlw or ldg for these stages. */
2924 if (ctx
->so
->type
== MESA_SHADER_TESS_CTRL
||
2925 ctx
->so
->type
== MESA_SHADER_TESS_EVAL
||
2926 ctx
->so
->type
== MESA_SHADER_GEOMETRY
)
2929 /* skip unread inputs, we could end up with (for example), unsplit
2930 * matrix/etc inputs in the case they are not read, so just silently
2936 so
->inputs
[n
].slot
= slot
;
2937 so
->inputs
[n
].compmask
|= (1 << (ncomp
+ frac
)) - 1;
2938 so
->inputs_count
= MAX2(so
->inputs_count
, n
+ 1);
2939 so
->inputs
[n
].interpolate
= in
->data
.interpolation
;
2941 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
2943 /* if any varyings have 'sample' qualifer, that triggers us
2944 * to run in per-sample mode:
2946 so
->per_samp
|= in
->data
.sample
;
2948 for (int i
= 0; i
< ncomp
; i
++) {
2949 struct ir3_instruction
*instr
= NULL
;
2950 unsigned idx
= (n
* 4) + i
+ frac
;
2952 if (slot
== VARYING_SLOT_POS
) {
2953 ir3_context_error(ctx
, "fragcoord should be a sysval!\n");
2954 } else if (slot
== VARYING_SLOT_PNTC
) {
2955 /* see for example st_nir_fixup_varying_slots().. this is
2956 * maybe a bit mesa/st specific. But we need things to line
2957 * up for this in fdN_program:
2958 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2959 * if (emit->sprite_coord_enable & texmask) {
2963 so
->inputs
[n
].slot
= VARYING_SLOT_VAR8
;
2964 so
->inputs
[n
].bary
= true;
2965 instr
= create_frag_input(ctx
, false, idx
);
2967 /* detect the special case for front/back colors where
2968 * we need to do flat vs smooth shading depending on
2971 if (in
->data
.interpolation
== INTERP_MODE_NONE
) {
2973 case VARYING_SLOT_COL0
:
2974 case VARYING_SLOT_COL1
:
2975 case VARYING_SLOT_BFC0
:
2976 case VARYING_SLOT_BFC1
:
2977 so
->inputs
[n
].rasterflat
= true;
2984 if (ctx
->compiler
->flat_bypass
) {
2985 if ((so
->inputs
[n
].interpolate
== INTERP_MODE_FLAT
) ||
2986 (so
->inputs
[n
].rasterflat
&& ctx
->so
->key
.rasterflat
))
2987 so
->inputs
[n
].use_ldlv
= true;
2990 so
->inputs
[n
].bary
= true;
2992 instr
= create_frag_input(ctx
, so
->inputs
[n
].use_ldlv
, idx
);
2995 compile_assert(ctx
, idx
< ctx
->ninputs
);
2997 ctx
->inputs
[idx
] = instr
;
2999 } else if (ctx
->so
->type
== MESA_SHADER_VERTEX
) {
3000 struct ir3_instruction
*input
= NULL
, *in
;
3001 struct ir3_instruction
*components
[4];
3002 unsigned mask
= (1 << (ncomp
+ frac
)) - 1;
3004 foreach_input (in
, ctx
->ir
) {
3005 if (in
->input
.inidx
== n
) {
3012 input
= create_input(ctx
, mask
);
3013 input
->input
.inidx
= n
;
3015 input
->regs
[0]->wrmask
|= mask
;
3018 ir3_split_dest(ctx
->block
, components
, input
, frac
, ncomp
);
3020 for (int i
= 0; i
< ncomp
; i
++) {
3021 unsigned idx
= (n
* 4) + i
+ frac
;
3022 compile_assert(ctx
, idx
< ctx
->ninputs
);
3023 ctx
->inputs
[idx
] = components
[i
];
3026 ir3_context_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3029 if (so
->inputs
[n
].bary
|| (ctx
->so
->type
== MESA_SHADER_VERTEX
)) {
3030 so
->total_in
+= ncomp
;
3034 /* Initially we assign non-packed inloc's for varyings, as we don't really
3035 * know up-front which components will be unused. After all the compilation
3036 * stages we scan the shader to see which components are actually used, and
3037 * re-pack the inlocs to eliminate unneeded varyings.
3040 pack_inlocs(struct ir3_context
*ctx
)
3042 struct ir3_shader_variant
*so
= ctx
->so
;
3043 uint8_t used_components
[so
->inputs_count
];
3045 memset(used_components
, 0, sizeof(used_components
));
3048 * First Step: scan shader to find which bary.f/ldlv remain:
3051 foreach_block (block
, &ctx
->ir
->block_list
) {
3052 foreach_instr (instr
, &block
->instr_list
) {
3053 if (is_input(instr
)) {
3054 unsigned inloc
= instr
->regs
[1]->iim_val
;
3055 unsigned i
= inloc
/ 4;
3056 unsigned j
= inloc
% 4;
3058 compile_assert(ctx
, instr
->regs
[1]->flags
& IR3_REG_IMMED
);
3059 compile_assert(ctx
, i
< so
->inputs_count
);
3061 used_components
[i
] |= 1 << j
;
3062 } else if (instr
->opc
== OPC_META_TEX_PREFETCH
) {
3063 for (int n
= 0; n
< 2; n
++) {
3064 unsigned inloc
= instr
->prefetch
.input_offset
+ n
;
3065 unsigned i
= inloc
/ 4;
3066 unsigned j
= inloc
% 4;
3068 compile_assert(ctx
, i
< so
->inputs_count
);
3070 used_components
[i
] |= 1 << j
;
3077 * Second Step: reassign varying inloc/slots:
3080 unsigned actual_in
= 0;
3083 for (unsigned i
= 0; i
< so
->inputs_count
; i
++) {
3084 unsigned compmask
= 0, maxcomp
= 0;
3086 so
->inputs
[i
].inloc
= inloc
;
3087 so
->inputs
[i
].bary
= false;
3089 for (unsigned j
= 0; j
< 4; j
++) {
3090 if (!(used_components
[i
] & (1 << j
)))
3093 compmask
|= (1 << j
);
3097 /* at this point, since used_components[i] mask is only
3098 * considering varyings (ie. not sysvals) we know this
3101 so
->inputs
[i
].bary
= true;
3104 if (so
->inputs
[i
].bary
) {
3106 so
->inputs
[i
].compmask
= (1 << maxcomp
) - 1;
3112 * Third Step: reassign packed inloc's:
3115 foreach_block (block
, &ctx
->ir
->block_list
) {
3116 foreach_instr (instr
, &block
->instr_list
) {
3117 if (is_input(instr
)) {
3118 unsigned inloc
= instr
->regs
[1]->iim_val
;
3119 unsigned i
= inloc
/ 4;
3120 unsigned j
= inloc
% 4;
3122 instr
->regs
[1]->iim_val
= so
->inputs
[i
].inloc
+ j
;
3123 } else if (instr
->opc
== OPC_META_TEX_PREFETCH
) {
3124 unsigned i
= instr
->prefetch
.input_offset
/ 4;
3125 unsigned j
= instr
->prefetch
.input_offset
% 4;
3126 instr
->prefetch
.input_offset
= so
->inputs
[i
].inloc
+ j
;
3133 setup_output(struct ir3_context
*ctx
, nir_variable
*out
)
3135 struct ir3_shader_variant
*so
= ctx
->so
;
3136 unsigned ncomp
= glsl_get_components(out
->type
);
3137 unsigned n
= out
->data
.driver_location
;
3138 unsigned frac
= out
->data
.location_frac
;
3139 unsigned slot
= out
->data
.location
;
3142 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
3144 case FRAG_RESULT_DEPTH
:
3145 comp
= 2; /* tgsi will write to .z component */
3146 so
->writes_pos
= true;
3148 case FRAG_RESULT_COLOR
:
3151 case FRAG_RESULT_SAMPLE_MASK
:
3152 so
->writes_smask
= true;
3155 if (slot
>= FRAG_RESULT_DATA0
)
3157 ir3_context_error(ctx
, "unknown FS output name: %s\n",
3158 gl_frag_result_name(slot
));
3160 } else if (ctx
->so
->type
== MESA_SHADER_VERTEX
||
3161 ctx
->so
->type
== MESA_SHADER_TESS_EVAL
||
3162 ctx
->so
->type
== MESA_SHADER_GEOMETRY
) {
3164 case VARYING_SLOT_POS
:
3165 so
->writes_pos
= true;
3167 case VARYING_SLOT_PSIZ
:
3168 so
->writes_psize
= true;
3170 case VARYING_SLOT_PRIMITIVE_ID
:
3171 case VARYING_SLOT_LAYER
:
3172 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3
:
3173 debug_assert(ctx
->so
->type
== MESA_SHADER_GEOMETRY
);
3175 case VARYING_SLOT_COL0
:
3176 case VARYING_SLOT_COL1
:
3177 case VARYING_SLOT_BFC0
:
3178 case VARYING_SLOT_BFC1
:
3179 case VARYING_SLOT_FOGC
:
3180 case VARYING_SLOT_CLIP_DIST0
:
3181 case VARYING_SLOT_CLIP_DIST1
:
3182 case VARYING_SLOT_CLIP_VERTEX
:
3185 if (slot
>= VARYING_SLOT_VAR0
)
3187 if ((VARYING_SLOT_TEX0
<= slot
) && (slot
<= VARYING_SLOT_TEX7
))
3189 ir3_context_error(ctx
, "unknown %s shader output name: %s\n",
3190 _mesa_shader_stage_to_string(ctx
->so
->type
),
3191 gl_varying_slot_name(slot
));
3193 } else if (ctx
->so
->type
== MESA_SHADER_TESS_CTRL
) {
3194 /* output lowered to buffer writes. */
3197 ir3_context_error(ctx
, "unknown shader type: %d\n", ctx
->so
->type
);
3200 compile_assert(ctx
, n
< ARRAY_SIZE(so
->outputs
));
3202 so
->outputs
[n
].slot
= slot
;
3203 so
->outputs
[n
].regid
= regid(n
, comp
);
3204 so
->outputs_count
= MAX2(so
->outputs_count
, n
+ 1);
3206 for (int i
= 0; i
< ncomp
; i
++) {
3207 unsigned idx
= (n
* 4) + i
+ frac
;
3208 compile_assert(ctx
, idx
< ctx
->noutputs
);
3209 ctx
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
3212 /* if varying packing doesn't happen, we could end up in a situation
3213 * with "holes" in the output, and since the per-generation code that
3214 * sets up varying linkage registers doesn't expect to have more than
3215 * one varying per vec4 slot, pad the holes.
3217 * Note that this should probably generate a performance warning of
3220 for (int i
= 0; i
< frac
; i
++) {
3221 unsigned idx
= (n
* 4) + i
;
3222 if (!ctx
->outputs
[idx
]) {
3223 ctx
->outputs
[idx
] = create_immed(ctx
->block
, fui(0.0));
3229 max_drvloc(struct exec_list
*vars
)
3232 nir_foreach_variable (var
, vars
) {
3233 drvloc
= MAX2(drvloc
, (int)var
->data
.driver_location
);
3239 emit_instructions(struct ir3_context
*ctx
)
3241 nir_function_impl
*fxn
= nir_shader_get_entrypoint(ctx
->s
);
3243 ctx
->ninputs
= (max_drvloc(&ctx
->s
->inputs
) + 1) * 4;
3244 ctx
->noutputs
= (max_drvloc(&ctx
->s
->outputs
) + 1) * 4;
3246 ctx
->inputs
= rzalloc_array(ctx
, struct ir3_instruction
*, ctx
->ninputs
);
3247 ctx
->outputs
= rzalloc_array(ctx
, struct ir3_instruction
*, ctx
->noutputs
);
3249 ctx
->ir
= ir3_create(ctx
->compiler
, ctx
->so
->type
);
3251 /* Create inputs in first block: */
3252 ctx
->block
= get_block(ctx
, nir_start_block(fxn
));
3253 ctx
->in_block
= ctx
->block
;
3254 list_addtail(&ctx
->block
->node
, &ctx
->ir
->block_list
);
3256 /* for fragment shader, the vcoord input register is used as the
3257 * base for bary.f varying fetch instrs:
3259 * TODO defer creating ctx->ij_pixel and corresponding sysvals
3260 * until emit_intrinsic when we know they are actually needed.
3261 * For now, we defer creating ctx->ij_centroid, etc, since we
3262 * only need ij_pixel for "old style" varying inputs (ie.
3265 if (ctx
->so
->type
== MESA_SHADER_FRAGMENT
) {
3266 ctx
->ij_pixel
= create_input(ctx
, 0x3);
3270 nir_foreach_variable (var
, &ctx
->s
->inputs
) {
3271 setup_input(ctx
, var
);
3274 /* Defer add_sysval_input() stuff until after setup_inputs(),
3275 * because sysvals need to be appended after varyings:
3277 if (ctx
->ij_pixel
) {
3278 add_sysval_input_compmask(ctx
, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
,
3279 0x3, ctx
->ij_pixel
);
3283 /* Tesselation shaders always need primitive ID for indexing the
3284 * BO. Geometry shaders don't always need it but when they do it has be
3285 * delivered and unclobbered in the VS. To make things easy, we always
3286 * make room for it in VS/DS.
3288 bool has_tess
= ctx
->so
->key
.tessellation
!= IR3_TESS_NONE
;
3289 bool has_gs
= ctx
->so
->key
.has_gs
;
3290 switch (ctx
->so
->type
) {
3291 case MESA_SHADER_VERTEX
:
3293 ctx
->tcs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_TCS_HEADER_IR3
, 0x1);
3294 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3295 } else if (has_gs
) {
3296 ctx
->gs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_GS_HEADER_IR3
, 0x1);
3297 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3300 case MESA_SHADER_TESS_CTRL
:
3301 ctx
->tcs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_TCS_HEADER_IR3
, 0x1);
3302 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3304 case MESA_SHADER_TESS_EVAL
:
3306 ctx
->gs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_GS_HEADER_IR3
, 0x1);
3307 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3309 case MESA_SHADER_GEOMETRY
:
3310 ctx
->gs_header
= create_sysval_input(ctx
, SYSTEM_VALUE_GS_HEADER_IR3
, 0x1);
3311 ctx
->primitive_id
= create_sysval_input(ctx
, SYSTEM_VALUE_PRIMITIVE_ID
, 0x1);
3317 /* Setup outputs: */
3318 nir_foreach_variable (var
, &ctx
->s
->outputs
) {
3319 setup_output(ctx
, var
);
3322 /* Find # of samplers: */
3323 nir_foreach_variable (var
, &ctx
->s
->uniforms
) {
3324 ctx
->so
->num_samp
+= glsl_type_get_sampler_count(var
->type
);
3325 /* just assume that we'll be reading from images.. if it
3326 * is write-only we don't have to count it, but not sure
3327 * if there is a good way to know?
3329 ctx
->so
->num_samp
+= glsl_type_get_image_count(var
->type
);
3332 /* NOTE: need to do something more clever when we support >1 fxn */
3333 nir_foreach_register (reg
, &fxn
->registers
) {
3334 ir3_declare_array(ctx
, reg
);
3336 /* And emit the body: */
3338 emit_function(ctx
, fxn
);
3341 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3342 * need to assign the tex state indexes for these after we know the
3346 fixup_astc_srgb(struct ir3_context
*ctx
)
3348 struct ir3_shader_variant
*so
= ctx
->so
;
3349 /* indexed by original tex idx, value is newly assigned alpha sampler
3350 * state tex idx. Zero is invalid since there is at least one sampler
3353 unsigned alt_tex_state
[16] = {0};
3354 unsigned tex_idx
= ctx
->max_texture_index
+ 1;
3357 so
->astc_srgb
.base
= tex_idx
;
3359 for (unsigned i
= 0; i
< ctx
->ir
->astc_srgb_count
; i
++) {
3360 struct ir3_instruction
*sam
= ctx
->ir
->astc_srgb
[i
];
3362 compile_assert(ctx
, sam
->cat5
.tex
< ARRAY_SIZE(alt_tex_state
));
3364 if (alt_tex_state
[sam
->cat5
.tex
] == 0) {
3365 /* assign new alternate/alpha tex state slot: */
3366 alt_tex_state
[sam
->cat5
.tex
] = tex_idx
++;
3367 so
->astc_srgb
.orig_idx
[idx
++] = sam
->cat5
.tex
;
3368 so
->astc_srgb
.count
++;
3371 sam
->cat5
.tex
= alt_tex_state
[sam
->cat5
.tex
];
3376 fixup_binning_pass(struct ir3_context
*ctx
)
3378 struct ir3_shader_variant
*so
= ctx
->so
;
3379 struct ir3
*ir
= ctx
->ir
;
3382 /* first pass, remove unused outputs from the IR level outputs: */
3383 for (i
= 0, j
= 0; i
< ir
->outputs_count
; i
++) {
3384 struct ir3_instruction
*out
= ir
->outputs
[i
];
3385 assert(out
->opc
== OPC_META_COLLECT
);
3386 unsigned outidx
= out
->collect
.outidx
;
3387 unsigned slot
= so
->outputs
[outidx
].slot
;
3389 /* throw away everything but first position/psize */
3390 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3391 ir
->outputs
[j
] = ir
->outputs
[i
];
3395 ir
->outputs_count
= j
;
3397 /* second pass, cleanup the unused slots in ir3_shader_variant::outputs
3400 for (i
= 0, j
= 0; i
< so
->outputs_count
; i
++) {
3401 unsigned slot
= so
->outputs
[i
].slot
;
3403 /* throw away everything but first position/psize */
3404 if ((slot
== VARYING_SLOT_POS
) || (slot
== VARYING_SLOT_PSIZ
)) {
3405 so
->outputs
[j
] = so
->outputs
[i
];
3407 /* fixup outidx to point to new output table entry: */
3408 struct ir3_instruction
*out
;
3409 foreach_output (out
, ir
) {
3410 if (out
->collect
.outidx
== i
) {
3411 out
->collect
.outidx
= j
;
3419 so
->outputs_count
= j
;
3423 collect_tex_prefetches(struct ir3_context
*ctx
, struct ir3
*ir
)
3427 /* Collect sampling instructions eligible for pre-dispatch. */
3428 foreach_block (block
, &ir
->block_list
) {
3429 foreach_instr_safe (instr
, &block
->instr_list
) {
3430 if (instr
->opc
== OPC_META_TEX_PREFETCH
) {
3431 assert(idx
< ARRAY_SIZE(ctx
->so
->sampler_prefetch
));
3432 struct ir3_sampler_prefetch
*fetch
=
3433 &ctx
->so
->sampler_prefetch
[idx
];
3436 if (instr
->flags
& IR3_INSTR_B
) {
3437 fetch
->cmd
= IR3_SAMPLER_BINDLESS_PREFETCH_CMD
;
3438 /* In bindless mode, the index is actually the base */
3439 fetch
->tex_id
= instr
->prefetch
.tex_base
;
3440 fetch
->samp_id
= instr
->prefetch
.samp_base
;
3441 fetch
->tex_bindless_id
= instr
->prefetch
.tex
;
3442 fetch
->samp_bindless_id
= instr
->prefetch
.samp
;
3444 fetch
->cmd
= IR3_SAMPLER_PREFETCH_CMD
;
3445 fetch
->tex_id
= instr
->prefetch
.tex
;
3446 fetch
->samp_id
= instr
->prefetch
.samp
;
3448 fetch
->wrmask
= instr
->regs
[0]->wrmask
;
3449 fetch
->dst
= instr
->regs
[0]->num
;
3450 fetch
->src
= instr
->prefetch
.input_offset
;
3453 MAX2(ctx
->so
->total_in
, instr
->prefetch
.input_offset
+ 2);
3455 /* Disable half precision until supported. */
3456 fetch
->half_precision
= !!(instr
->regs
[0]->flags
& IR3_REG_HALF
);
3458 /* Remove the prefetch placeholder instruction: */
3459 list_delinit(&instr
->node
);
3466 ir3_compile_shader_nir(struct ir3_compiler
*compiler
,
3467 struct ir3_shader_variant
*so
)
3469 struct ir3_context
*ctx
;
3471 int ret
= 0, max_bary
;
3475 ctx
= ir3_context_init(compiler
, so
);
3477 DBG("INIT failed!");
3482 emit_instructions(ctx
);
3485 DBG("EMIT failed!");
3490 ir
= so
->ir
= ctx
->ir
;
3492 assert((ctx
->noutputs
% 4) == 0);
3494 /* Setup IR level outputs, which are "collects" that gather
3495 * the scalar components of outputs.
3497 for (unsigned i
= 0; i
< ctx
->noutputs
; i
+= 4) {
3499 /* figure out the # of components written:
3501 * TODO do we need to handle holes, ie. if .x and .z
3502 * components written, but .y component not written?
3504 for (unsigned j
= 0; j
< 4; j
++) {
3505 if (!ctx
->outputs
[i
+ j
])
3510 /* Note that in some stages, like TCS, store_output is
3511 * lowered to memory writes, so no components of the
3512 * are "written" from the PoV of traditional store-
3513 * output instructions:
3518 struct ir3_instruction
*out
=
3519 ir3_create_collect(ctx
, &ctx
->outputs
[i
], ncomp
);
3522 assert(outidx
< so
->outputs_count
);
3524 /* stash index into so->outputs[] so we can map the
3525 * output back to slot/etc later:
3527 out
->collect
.outidx
= outidx
;
3529 array_insert(ir
, ir
->outputs
, out
);
3532 /* Set up the gs header as an output for the vertex shader so it won't
3533 * clobber it for the tess ctrl shader.
3535 * TODO this could probably be done more cleanly in a nir pass.
3537 if (ctx
->so
->type
== MESA_SHADER_VERTEX
||
3538 (ctx
->so
->key
.has_gs
&& ctx
->so
->type
== MESA_SHADER_TESS_EVAL
)) {
3539 if (ctx
->primitive_id
) {
3540 unsigned n
= so
->outputs_count
++;
3541 so
->outputs
[n
].slot
= VARYING_SLOT_PRIMITIVE_ID
;
3543 struct ir3_instruction
*out
=
3544 ir3_create_collect(ctx
, &ctx
->primitive_id
, 1);
3545 out
->collect
.outidx
= n
;
3546 array_insert(ir
, ir
->outputs
, out
);
3549 if (ctx
->gs_header
) {
3550 unsigned n
= so
->outputs_count
++;
3551 so
->outputs
[n
].slot
= VARYING_SLOT_GS_HEADER_IR3
;
3552 struct ir3_instruction
*out
=
3553 ir3_create_collect(ctx
, &ctx
->gs_header
, 1);
3554 out
->collect
.outidx
= n
;
3555 array_insert(ir
, ir
->outputs
, out
);
3558 if (ctx
->tcs_header
) {
3559 unsigned n
= so
->outputs_count
++;
3560 so
->outputs
[n
].slot
= VARYING_SLOT_TCS_HEADER_IR3
;
3561 struct ir3_instruction
*out
=
3562 ir3_create_collect(ctx
, &ctx
->tcs_header
, 1);
3563 out
->collect
.outidx
= n
;
3564 array_insert(ir
, ir
->outputs
, out
);
3568 /* at this point, for binning pass, throw away unneeded outputs: */
3569 if (so
->binning_pass
&& (ctx
->compiler
->gpu_id
< 600))
3570 fixup_binning_pass(ctx
);
3572 ir3_debug_print(ir
, "BEFORE CF");
3576 ir3_debug_print(ir
, "BEFORE CP");
3580 /* at this point, for binning pass, throw away unneeded outputs:
3581 * Note that for a6xx and later, we do this after ir3_cp to ensure
3582 * that the uniform/constant layout for BS and VS matches, so that
3583 * we can re-use same VS_CONST state group.
3585 if (so
->binning_pass
&& (ctx
->compiler
->gpu_id
>= 600))
3586 fixup_binning_pass(ctx
);
3588 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3589 * need to make sure not to remove any inputs that are used by
3590 * the nonbinning VS.
3592 if (ctx
->compiler
->gpu_id
>= 600 && so
->binning_pass
&&
3593 so
->type
== MESA_SHADER_VERTEX
) {
3594 for (int i
= 0; i
< ctx
->ninputs
; i
++) {
3595 struct ir3_instruction
*in
= ctx
->inputs
[i
];
3603 debug_assert(n
< so
->nonbinning
->inputs_count
);
3605 if (so
->nonbinning
->inputs
[n
].sysval
)
3608 /* be sure to keep inputs, even if only used in VS */
3609 if (so
->nonbinning
->inputs
[n
].compmask
& (1 << c
))
3610 array_insert(in
->block
, in
->block
->keeps
, in
);
3614 ir3_debug_print(ir
, "BEFORE GROUPING");
3616 ir3_sched_add_deps(ir
);
3618 /* Group left/right neighbors, inserting mov's where needed to
3623 ir3_debug_print(ir
, "AFTER GROUPING");
3627 ir3_debug_print(ir
, "AFTER DEPTH");
3629 /* do Sethi–Ullman numbering before scheduling: */
3632 ret
= ir3_sched(ir
);
3634 DBG("SCHED failed!");
3638 ir3_debug_print(ir
, "AFTER SCHED");
3640 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3641 * with draw pass VS, so binning and draw pass can both use the
3644 * Note that VS inputs are expected to be full precision.
3646 bool pre_assign_inputs
= (ir
->compiler
->gpu_id
>= 600) &&
3647 (ir
->type
== MESA_SHADER_VERTEX
) &&
3650 if (pre_assign_inputs
) {
3651 for (unsigned i
= 0; i
< ctx
->ninputs
; i
++) {
3652 struct ir3_instruction
*instr
= ctx
->inputs
[i
];
3659 unsigned regid
= so
->nonbinning
->inputs
[n
].regid
+ c
;
3661 instr
->regs
[0]->num
= regid
;
3664 ret
= ir3_ra(so
, ctx
->inputs
, ctx
->ninputs
);
3665 } else if (ctx
->tcs_header
) {
3666 /* We need to have these values in the same registers between VS and TCS
3667 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3670 ctx
->tcs_header
->regs
[0]->num
= regid(0, 0);
3671 ctx
->primitive_id
->regs
[0]->num
= regid(0, 1);
3672 struct ir3_instruction
*precolor
[] = { ctx
->tcs_header
, ctx
->primitive_id
};
3673 ret
= ir3_ra(so
, precolor
, ARRAY_SIZE(precolor
));
3674 } else if (ctx
->gs_header
) {
3675 /* We need to have these values in the same registers between producer
3676 * (VS or DS) and GS since the producer chains to GS and doesn't get
3677 * the sysvals redelivered.
3680 ctx
->gs_header
->regs
[0]->num
= regid(0, 0);
3681 ctx
->primitive_id
->regs
[0]->num
= regid(0, 1);
3682 struct ir3_instruction
*precolor
[] = { ctx
->gs_header
, ctx
->primitive_id
};
3683 ret
= ir3_ra(so
, precolor
, ARRAY_SIZE(precolor
));
3684 } else if (so
->num_sampler_prefetch
) {
3685 assert(so
->type
== MESA_SHADER_FRAGMENT
);
3686 struct ir3_instruction
*instr
, *precolor
[2];
3689 foreach_input (instr
, ir
) {
3690 if (instr
->input
.sysval
!= SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
)
3693 assert(idx
< ARRAY_SIZE(precolor
));
3695 precolor
[idx
] = instr
;
3696 instr
->regs
[0]->num
= idx
;
3700 ret
= ir3_ra(so
, precolor
, idx
);
3702 ret
= ir3_ra(so
, NULL
, 0);
3711 ir3_debug_print(ir
, "AFTER POSTSCHED");
3713 if (compiler
->gpu_id
>= 600) {
3714 if (ir3_a6xx_fixup_atomic_dests(ir
, so
)) {
3715 ir3_debug_print(ir
, "AFTER ATOMIC FIXUP");
3719 if (so
->type
== MESA_SHADER_FRAGMENT
)
3723 * Fixup inputs/outputs to point to the actual registers assigned:
3725 * 1) initialize to r63.x (invalid/unused)
3726 * 2) iterate IR level inputs/outputs and update the variants
3727 * inputs/outputs table based on the assigned registers for
3728 * the remaining inputs/outputs.
3731 for (unsigned i
= 0; i
< so
->inputs_count
; i
++)
3732 so
->inputs
[i
].regid
= INVALID_REG
;
3733 for (unsigned i
= 0; i
< so
->outputs_count
; i
++)
3734 so
->outputs
[i
].regid
= INVALID_REG
;
3736 struct ir3_instruction
*out
;
3737 foreach_output (out
, ir
) {
3738 assert(out
->opc
== OPC_META_COLLECT
);
3739 unsigned outidx
= out
->collect
.outidx
;
3741 so
->outputs
[outidx
].regid
= out
->regs
[0]->num
;
3742 so
->outputs
[outidx
].half
= !!(out
->regs
[0]->flags
& IR3_REG_HALF
);
3745 struct ir3_instruction
*in
;
3746 foreach_input (in
, ir
) {
3747 assert(in
->opc
== OPC_META_INPUT
);
3748 unsigned inidx
= in
->input
.inidx
;
3750 if (pre_assign_inputs
&& !so
->inputs
[inidx
].sysval
) {
3751 if (VALIDREG(so
->nonbinning
->inputs
[inidx
].regid
)) {
3752 compile_assert(ctx
, in
->regs
[0]->num
==
3753 so
->nonbinning
->inputs
[inidx
].regid
);
3754 compile_assert(ctx
, !!(in
->regs
[0]->flags
& IR3_REG_HALF
) ==
3755 so
->nonbinning
->inputs
[inidx
].half
);
3757 so
->inputs
[inidx
].regid
= so
->nonbinning
->inputs
[inidx
].regid
;
3758 so
->inputs
[inidx
].half
= so
->nonbinning
->inputs
[inidx
].half
;
3760 so
->inputs
[inidx
].regid
= in
->regs
[0]->num
;
3761 so
->inputs
[inidx
].half
= !!(in
->regs
[0]->flags
& IR3_REG_HALF
);
3766 fixup_astc_srgb(ctx
);
3768 /* We need to do legalize after (for frag shader's) the "bary.f"
3769 * offsets (inloc) have been assigned.
3771 ir3_legalize(ir
, so
, &max_bary
);
3773 ir3_debug_print(ir
, "AFTER LEGALIZE");
3775 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3776 * know what we might have to wait on when coming in from VS chsh.
3778 if (so
->type
== MESA_SHADER_TESS_CTRL
||
3779 so
->type
== MESA_SHADER_GEOMETRY
) {
3780 foreach_block (block
, &ir
->block_list
) {
3781 foreach_instr (instr
, &block
->instr_list
) {
3782 instr
->flags
|= IR3_INSTR_SS
| IR3_INSTR_SY
;
3788 so
->branchstack
= ctx
->max_stack
;
3790 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3791 if (so
->type
== MESA_SHADER_FRAGMENT
)
3792 so
->total_in
= max_bary
+ 1;
3794 so
->max_sun
= ir
->max_sun
;
3796 /* Collect sampling instructions eligible for pre-dispatch. */
3797 collect_tex_prefetches(ctx
, ir
);
3799 if (so
->type
== MESA_SHADER_FRAGMENT
&&
3800 ctx
->s
->info
.fs
.needs_helper_invocations
)
3801 so
->need_pixlod
= true;
3806 ir3_destroy(so
->ir
);
3809 ir3_context_free(ctx
);