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freedreno/ir3: move atomic fixup after RA
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 __ssa_dst(mov);
55 src = __ssa_src(mov, collect, IR3_REG_RELATIV);
56 src->size = arrsz;
57 src->array.offset = n;
58
59 ir3_instr_set_address(mov, address);
60
61 return mov;
62 }
63
64 static struct ir3_instruction *
65 create_input(struct ir3_context *ctx, unsigned compmask)
66 {
67 struct ir3_instruction *in;
68
69 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
70 in->input.sysval = ~0;
71 __ssa_dst(in)->wrmask = compmask;
72
73 array_insert(ctx->ir, ctx->ir->inputs, in);
74
75 return in;
76 }
77
78 static struct ir3_instruction *
79 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
80 {
81 struct ir3_block *block = ctx->block;
82 struct ir3_instruction *instr;
83 /* packed inloc is fixed up later: */
84 struct ir3_instruction *inloc = create_immed(block, n);
85
86 if (use_ldlv) {
87 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
88 instr->cat6.type = TYPE_U32;
89 instr->cat6.iim_val = 1;
90 } else {
91 instr = ir3_BARY_F(block, inloc, 0, ctx->ij_pixel, 0);
92 instr->regs[2]->wrmask = 0x3;
93 }
94
95 return instr;
96 }
97
98 static struct ir3_instruction *
99 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
100 {
101 /* first four vec4 sysval's reserved for UBOs: */
102 /* NOTE: dp is in scalar, but there can be >4 dp components: */
103 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
104 unsigned n = const_state->offsets.driver_param;
105 unsigned r = regid(n + dp / 4, dp % 4);
106 return create_uniform(ctx->block, r);
107 }
108
109 /*
110 * Adreno uses uint rather than having dedicated bool type,
111 * which (potentially) requires some conversion, in particular
112 * when using output of an bool instr to int input, or visa
113 * versa.
114 *
115 * | Adreno | NIR |
116 * -------+---------+-------+-
117 * true | 1 | ~0 |
118 * false | 0 | 0 |
119 *
120 * To convert from an adreno bool (uint) to nir, use:
121 *
122 * absneg.s dst, (neg)src
123 *
124 * To convert back in the other direction:
125 *
126 * absneg.s dst, (abs)arc
127 *
128 * The CP step can clean up the absneg.s that cancel each other
129 * out, and with a slight bit of extra cleverness (to recognize
130 * the instructions which produce either a 0 or 1) can eliminate
131 * the absneg.s's completely when an instruction that wants
132 * 0/1 consumes the result. For example, when a nir 'bcsel'
133 * consumes the result of 'feq'. So we should be able to get by
134 * without a boolean resolve step, and without incuring any
135 * extra penalty in instruction count.
136 */
137
138 /* NIR bool -> native (adreno): */
139 static struct ir3_instruction *
140 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
141 {
142 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
143 }
144
145 /* native (adreno) -> NIR bool: */
146 static struct ir3_instruction *
147 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
148 {
149 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
150 }
151
152 /*
153 * alu/sfu instructions:
154 */
155
156 static struct ir3_instruction *
157 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
158 unsigned src_bitsize, nir_op op)
159 {
160 type_t src_type, dst_type;
161
162 switch (op) {
163 case nir_op_f2f32:
164 case nir_op_f2f16_rtne:
165 case nir_op_f2f16_rtz:
166 case nir_op_f2f16:
167 case nir_op_f2i32:
168 case nir_op_f2i16:
169 case nir_op_f2i8:
170 case nir_op_f2u32:
171 case nir_op_f2u16:
172 case nir_op_f2u8:
173 switch (src_bitsize) {
174 case 32:
175 src_type = TYPE_F32;
176 break;
177 case 16:
178 src_type = TYPE_F16;
179 break;
180 default:
181 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
182 }
183 break;
184
185 case nir_op_i2f32:
186 case nir_op_i2f16:
187 case nir_op_i2i32:
188 case nir_op_i2i16:
189 case nir_op_i2i8:
190 switch (src_bitsize) {
191 case 32:
192 src_type = TYPE_S32;
193 break;
194 case 16:
195 src_type = TYPE_S16;
196 break;
197 case 8:
198 src_type = TYPE_S8;
199 break;
200 default:
201 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
202 }
203 break;
204
205 case nir_op_u2f32:
206 case nir_op_u2f16:
207 case nir_op_u2u32:
208 case nir_op_u2u16:
209 case nir_op_u2u8:
210 switch (src_bitsize) {
211 case 32:
212 src_type = TYPE_U32;
213 break;
214 case 16:
215 src_type = TYPE_U16;
216 break;
217 case 8:
218 src_type = TYPE_U8;
219 break;
220 default:
221 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
222 }
223 break;
224
225 default:
226 ir3_context_error(ctx, "invalid conversion op: %u", op);
227 }
228
229 switch (op) {
230 case nir_op_f2f32:
231 case nir_op_i2f32:
232 case nir_op_u2f32:
233 dst_type = TYPE_F32;
234 break;
235
236 case nir_op_f2f16_rtne:
237 case nir_op_f2f16_rtz:
238 case nir_op_f2f16:
239 /* TODO how to handle rounding mode? */
240 case nir_op_i2f16:
241 case nir_op_u2f16:
242 dst_type = TYPE_F16;
243 break;
244
245 case nir_op_f2i32:
246 case nir_op_i2i32:
247 dst_type = TYPE_S32;
248 break;
249
250 case nir_op_f2i16:
251 case nir_op_i2i16:
252 dst_type = TYPE_S16;
253 break;
254
255 case nir_op_f2i8:
256 case nir_op_i2i8:
257 dst_type = TYPE_S8;
258 break;
259
260 case nir_op_f2u32:
261 case nir_op_u2u32:
262 dst_type = TYPE_U32;
263 break;
264
265 case nir_op_f2u16:
266 case nir_op_u2u16:
267 dst_type = TYPE_U16;
268 break;
269
270 case nir_op_f2u8:
271 case nir_op_u2u8:
272 dst_type = TYPE_U8;
273 break;
274
275 default:
276 ir3_context_error(ctx, "invalid conversion op: %u", op);
277 }
278
279 return ir3_COV(ctx->block, src, src_type, dst_type);
280 }
281
282 static void
283 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
284 {
285 const nir_op_info *info = &nir_op_infos[alu->op];
286 struct ir3_instruction **dst, *src[info->num_inputs];
287 unsigned bs[info->num_inputs]; /* bit size */
288 struct ir3_block *b = ctx->block;
289 unsigned dst_sz, wrmask;
290 type_t dst_type = nir_dest_bit_size(alu->dest.dest) < 32 ?
291 TYPE_U16 : TYPE_U32;
292
293 if (alu->dest.dest.is_ssa) {
294 dst_sz = alu->dest.dest.ssa.num_components;
295 wrmask = (1 << dst_sz) - 1;
296 } else {
297 dst_sz = alu->dest.dest.reg.reg->num_components;
298 wrmask = alu->dest.write_mask;
299 }
300
301 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
302
303 /* Vectors are special in that they have non-scalarized writemasks,
304 * and just take the first swizzle channel for each argument in
305 * order into each writemask channel.
306 */
307 if ((alu->op == nir_op_vec2) ||
308 (alu->op == nir_op_vec3) ||
309 (alu->op == nir_op_vec4)) {
310
311 for (int i = 0; i < info->num_inputs; i++) {
312 nir_alu_src *asrc = &alu->src[i];
313
314 compile_assert(ctx, !asrc->abs);
315 compile_assert(ctx, !asrc->negate);
316
317 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
318 if (!src[i])
319 src[i] = create_immed_typed(ctx->block, 0, dst_type);
320 dst[i] = ir3_MOV(b, src[i], dst_type);
321 }
322
323 ir3_put_dst(ctx, &alu->dest.dest);
324 return;
325 }
326
327 /* We also get mov's with more than one component for mov's so
328 * handle those specially:
329 */
330 if (alu->op == nir_op_mov) {
331 nir_alu_src *asrc = &alu->src[0];
332 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
333
334 for (unsigned i = 0; i < dst_sz; i++) {
335 if (wrmask & (1 << i)) {
336 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
337 } else {
338 dst[i] = NULL;
339 }
340 }
341
342 ir3_put_dst(ctx, &alu->dest.dest);
343 return;
344 }
345
346 /* General case: We can just grab the one used channel per src. */
347 for (int i = 0; i < info->num_inputs; i++) {
348 unsigned chan = ffs(alu->dest.write_mask) - 1;
349 nir_alu_src *asrc = &alu->src[i];
350
351 compile_assert(ctx, !asrc->abs);
352 compile_assert(ctx, !asrc->negate);
353
354 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
355 bs[i] = nir_src_bit_size(asrc->src);
356
357 compile_assert(ctx, src[i]);
358 }
359
360 switch (alu->op) {
361 case nir_op_f2f32:
362 case nir_op_f2f16_rtne:
363 case nir_op_f2f16_rtz:
364 case nir_op_f2f16:
365 case nir_op_f2i32:
366 case nir_op_f2i16:
367 case nir_op_f2i8:
368 case nir_op_f2u32:
369 case nir_op_f2u16:
370 case nir_op_f2u8:
371 case nir_op_i2f32:
372 case nir_op_i2f16:
373 case nir_op_i2i32:
374 case nir_op_i2i16:
375 case nir_op_i2i8:
376 case nir_op_u2f32:
377 case nir_op_u2f16:
378 case nir_op_u2u32:
379 case nir_op_u2u16:
380 case nir_op_u2u8:
381 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
382 break;
383 case nir_op_fquantize2f16:
384 dst[0] = create_cov(ctx,
385 create_cov(ctx, src[0], 32, nir_op_f2f16),
386 16, nir_op_f2f32);
387 break;
388 case nir_op_f2b16: {
389 struct ir3_instruction *zero = create_immed_typed(b, 0, TYPE_F16);
390 dst[0] = ir3_CMPS_F(b, src[0], 0, zero, 0);
391 dst[0]->cat2.condition = IR3_COND_NE;
392 break;
393 }
394 case nir_op_f2b32:
395 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
396 dst[0]->cat2.condition = IR3_COND_NE;
397 break;
398 case nir_op_b2f16:
399 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F16);
400 break;
401 case nir_op_b2f32:
402 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
403 break;
404 case nir_op_b2i8:
405 case nir_op_b2i16:
406 case nir_op_b2i32:
407 dst[0] = ir3_b2n(b, src[0]);
408 break;
409 case nir_op_i2b16: {
410 struct ir3_instruction *zero = create_immed_typed(b, 0, TYPE_S16);
411 dst[0] = ir3_CMPS_S(b, src[0], 0, zero, 0);
412 dst[0]->cat2.condition = IR3_COND_NE;
413 break;
414 }
415 case nir_op_i2b32:
416 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
417 dst[0]->cat2.condition = IR3_COND_NE;
418 break;
419
420 case nir_op_fneg:
421 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
422 break;
423 case nir_op_fabs:
424 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
425 break;
426 case nir_op_fmax:
427 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
428 break;
429 case nir_op_fmin:
430 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
431 break;
432 case nir_op_fsat:
433 /* if there is just a single use of the src, and it supports
434 * (sat) bit, we can just fold the (sat) flag back to the
435 * src instruction and create a mov. This is easier for cp
436 * to eliminate.
437 *
438 * TODO probably opc_cat==4 is ok too
439 */
440 if (alu->src[0].src.is_ssa &&
441 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
442 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
443 src[0]->flags |= IR3_INSTR_SAT;
444 dst[0] = ir3_MOV(b, src[0], dst_type);
445 } else {
446 /* otherwise generate a max.f that saturates.. blob does
447 * similar (generating a cat2 mov using max.f)
448 */
449 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
450 dst[0]->flags |= IR3_INSTR_SAT;
451 }
452 break;
453 case nir_op_fmul:
454 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
455 break;
456 case nir_op_fadd:
457 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
458 break;
459 case nir_op_fsub:
460 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
461 break;
462 case nir_op_ffma:
463 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
464 break;
465 case nir_op_fddx:
466 case nir_op_fddx_coarse:
467 dst[0] = ir3_DSX(b, src[0], 0);
468 dst[0]->cat5.type = TYPE_F32;
469 break;
470 case nir_op_fddx_fine:
471 dst[0] = ir3_DSXPP_1(b, src[0], 0);
472 dst[0]->cat5.type = TYPE_F32;
473 break;
474 case nir_op_fddy:
475 case nir_op_fddy_coarse:
476 dst[0] = ir3_DSY(b, src[0], 0);
477 dst[0]->cat5.type = TYPE_F32;
478 break;
479 break;
480 case nir_op_fddy_fine:
481 dst[0] = ir3_DSYPP_1(b, src[0], 0);
482 dst[0]->cat5.type = TYPE_F32;
483 break;
484 case nir_op_flt16:
485 case nir_op_flt32:
486 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
487 dst[0]->cat2.condition = IR3_COND_LT;
488 break;
489 case nir_op_fge16:
490 case nir_op_fge32:
491 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
492 dst[0]->cat2.condition = IR3_COND_GE;
493 break;
494 case nir_op_feq16:
495 case nir_op_feq32:
496 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
497 dst[0]->cat2.condition = IR3_COND_EQ;
498 break;
499 case nir_op_fne16:
500 case nir_op_fne32:
501 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
502 dst[0]->cat2.condition = IR3_COND_NE;
503 break;
504 case nir_op_fceil:
505 dst[0] = ir3_CEIL_F(b, src[0], 0);
506 break;
507 case nir_op_ffloor:
508 dst[0] = ir3_FLOOR_F(b, src[0], 0);
509 break;
510 case nir_op_ftrunc:
511 dst[0] = ir3_TRUNC_F(b, src[0], 0);
512 break;
513 case nir_op_fround_even:
514 dst[0] = ir3_RNDNE_F(b, src[0], 0);
515 break;
516 case nir_op_fsign:
517 dst[0] = ir3_SIGN_F(b, src[0], 0);
518 break;
519
520 case nir_op_fsin:
521 dst[0] = ir3_SIN(b, src[0], 0);
522 break;
523 case nir_op_fcos:
524 dst[0] = ir3_COS(b, src[0], 0);
525 break;
526 case nir_op_frsq:
527 dst[0] = ir3_RSQ(b, src[0], 0);
528 break;
529 case nir_op_frcp:
530 dst[0] = ir3_RCP(b, src[0], 0);
531 break;
532 case nir_op_flog2:
533 dst[0] = ir3_LOG2(b, src[0], 0);
534 break;
535 case nir_op_fexp2:
536 dst[0] = ir3_EXP2(b, src[0], 0);
537 break;
538 case nir_op_fsqrt:
539 dst[0] = ir3_SQRT(b, src[0], 0);
540 break;
541
542 case nir_op_iabs:
543 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
544 break;
545 case nir_op_iadd:
546 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
547 break;
548 case nir_op_iand:
549 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
550 break;
551 case nir_op_imax:
552 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
553 break;
554 case nir_op_umax:
555 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
556 break;
557 case nir_op_imin:
558 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
559 break;
560 case nir_op_umin:
561 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
562 break;
563 case nir_op_umul_low:
564 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
565 break;
566 case nir_op_imadsh_mix16:
567 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
568 break;
569 case nir_op_imad24_ir3:
570 dst[0] = ir3_MAD_S24(b, src[0], 0, src[1], 0, src[2], 0);
571 break;
572 case nir_op_imul24:
573 dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
574 break;
575 case nir_op_ineg:
576 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
577 break;
578 case nir_op_inot:
579 dst[0] = ir3_NOT_B(b, src[0], 0);
580 break;
581 case nir_op_ior:
582 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
583 break;
584 case nir_op_ishl:
585 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
586 break;
587 case nir_op_ishr:
588 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
589 break;
590 case nir_op_isub:
591 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
592 break;
593 case nir_op_ixor:
594 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
595 break;
596 case nir_op_ushr:
597 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
598 break;
599 case nir_op_ilt16:
600 case nir_op_ilt32:
601 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
602 dst[0]->cat2.condition = IR3_COND_LT;
603 break;
604 case nir_op_ige16:
605 case nir_op_ige32:
606 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
607 dst[0]->cat2.condition = IR3_COND_GE;
608 break;
609 case nir_op_ieq16:
610 case nir_op_ieq32:
611 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
612 dst[0]->cat2.condition = IR3_COND_EQ;
613 break;
614 case nir_op_ine16:
615 case nir_op_ine32:
616 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
617 dst[0]->cat2.condition = IR3_COND_NE;
618 break;
619 case nir_op_ult16:
620 case nir_op_ult32:
621 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
622 dst[0]->cat2.condition = IR3_COND_LT;
623 break;
624 case nir_op_uge16:
625 case nir_op_uge32:
626 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
627 dst[0]->cat2.condition = IR3_COND_GE;
628 break;
629
630 case nir_op_b16csel:
631 case nir_op_b32csel: {
632 struct ir3_instruction *cond = ir3_b2n(b, src[0]);
633
634 if ((src[0]->regs[0]->flags & IR3_REG_HALF))
635 cond->regs[0]->flags |= IR3_REG_HALF;
636
637 compile_assert(ctx, bs[1] == bs[2]);
638 /* Make sure the boolean condition has the same bit size as the other
639 * two arguments, adding a conversion if necessary.
640 */
641 if (bs[1] < bs[0])
642 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
643 else if (bs[1] > bs[0])
644 cond = ir3_COV(b, cond, TYPE_U16, TYPE_U32);
645
646 if (bs[1] > 16)
647 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
648 else
649 dst[0] = ir3_SEL_B16(b, src[1], 0, cond, 0, src[2], 0);
650 break;
651 }
652 case nir_op_bit_count: {
653 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
654 // double check on earlier gen's. Once half-precision support is
655 // in place, this should probably move to a NIR lowering pass:
656 struct ir3_instruction *hi, *lo;
657
658 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
659 TYPE_U32, TYPE_U16);
660 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
661
662 hi = ir3_CBITS_B(b, hi, 0);
663 lo = ir3_CBITS_B(b, lo, 0);
664
665 // TODO maybe the builders should default to making dst half-precision
666 // if the src's were half precision, to make this less awkward.. otoh
667 // we should probably just do this lowering in NIR.
668 hi->regs[0]->flags |= IR3_REG_HALF;
669 lo->regs[0]->flags |= IR3_REG_HALF;
670
671 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
672 dst[0]->regs[0]->flags |= IR3_REG_HALF;
673 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
674 break;
675 }
676 case nir_op_ifind_msb: {
677 struct ir3_instruction *cmp;
678 dst[0] = ir3_CLZ_S(b, src[0], 0);
679 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
680 cmp->cat2.condition = IR3_COND_GE;
681 dst[0] = ir3_SEL_B32(b,
682 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
683 cmp, 0, dst[0], 0);
684 break;
685 }
686 case nir_op_ufind_msb:
687 dst[0] = ir3_CLZ_B(b, src[0], 0);
688 dst[0] = ir3_SEL_B32(b,
689 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
690 src[0], 0, dst[0], 0);
691 break;
692 case nir_op_find_lsb:
693 dst[0] = ir3_BFREV_B(b, src[0], 0);
694 dst[0] = ir3_CLZ_B(b, dst[0], 0);
695 break;
696 case nir_op_bitfield_reverse:
697 dst[0] = ir3_BFREV_B(b, src[0], 0);
698 break;
699
700 default:
701 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
702 nir_op_infos[alu->op].name);
703 break;
704 }
705
706 if (nir_alu_type_get_base_type(info->output_type) == nir_type_bool) {
707 assert(dst_sz == 1);
708
709 if (nir_dest_bit_size(alu->dest.dest) < 32)
710 dst[0]->regs[0]->flags |= IR3_REG_HALF;
711
712 dst[0] = ir3_n2b(b, dst[0]);
713 }
714
715 if (nir_dest_bit_size(alu->dest.dest) < 32) {
716 for (unsigned i = 0; i < dst_sz; i++) {
717 dst[i]->regs[0]->flags |= IR3_REG_HALF;
718 }
719 }
720
721 ir3_put_dst(ctx, &alu->dest.dest);
722 }
723
724 /* handles direct/indirect UBO reads: */
725 static void
726 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
727 struct ir3_instruction **dst)
728 {
729 struct ir3_block *b = ctx->block;
730 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
731 /* UBO addresses are the first driver params, but subtract 2 here to
732 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
733 * is the uniforms: */
734 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
735 unsigned ubo = regid(const_state->offsets.ubo, 0) - 2;
736 const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
737
738 int off = 0;
739
740 /* First src is ubo index, which could either be an immed or not: */
741 src0 = ir3_get_src(ctx, &intr->src[0])[0];
742 if (is_same_type_mov(src0) &&
743 (src0->regs[1]->flags & IR3_REG_IMMED)) {
744 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
745 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
746 } else {
747 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, ptrsz));
748 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, ptrsz));
749
750 /* NOTE: since relative addressing is used, make sure constlen is
751 * at least big enough to cover all the UBO addresses, since the
752 * assembler won't know what the max address reg is.
753 */
754 ctx->so->constlen = MAX2(ctx->so->constlen,
755 const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
756 }
757
758 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
759 addr = base_lo;
760
761 if (nir_src_is_const(intr->src[1])) {
762 off += nir_src_as_uint(intr->src[1]);
763 } else {
764 /* For load_ubo_indirect, second src is indirect offset: */
765 src1 = ir3_get_src(ctx, &intr->src[1])[0];
766
767 /* and add offset to addr: */
768 addr = ir3_ADD_S(b, addr, 0, src1, 0);
769 }
770
771 /* if offset is to large to encode in the ldg, split it out: */
772 if ((off + (intr->num_components * 4)) > 1024) {
773 /* split out the minimal amount to improve the odds that
774 * cp can fit the immediate in the add.s instruction:
775 */
776 unsigned off2 = off + (intr->num_components * 4) - 1024;
777 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
778 off -= off2;
779 }
780
781 if (ptrsz == 2) {
782 struct ir3_instruction *carry;
783
784 /* handle 32b rollover, ie:
785 * if (addr < base_lo)
786 * base_hi++
787 */
788 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
789 carry->cat2.condition = IR3_COND_LT;
790 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
791
792 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
793 }
794
795 for (int i = 0; i < intr->num_components; i++) {
796 struct ir3_instruction *load =
797 ir3_LDG(b, addr, 0, create_immed(b, 1), 0, /* num components */
798 create_immed(b, off + i * 4), 0);
799 load->cat6.type = TYPE_U32;
800 dst[i] = load;
801 }
802 }
803
804 /* src[] = { block_index } */
805 static void
806 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
807 struct ir3_instruction **dst)
808 {
809 /* SSBO size stored as a const starting at ssbo_sizes: */
810 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
811 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
812 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
813 const_state->ssbo_size.off[blk_idx];
814
815 debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
816
817 dst[0] = create_uniform(ctx->block, idx);
818 }
819
820 /* src[] = { offset }. const_index[] = { base } */
821 static void
822 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
823 struct ir3_instruction **dst)
824 {
825 struct ir3_block *b = ctx->block;
826 struct ir3_instruction *ldl, *offset;
827 unsigned base;
828
829 offset = ir3_get_src(ctx, &intr->src[0])[0];
830 base = nir_intrinsic_base(intr);
831
832 ldl = ir3_LDL(b, offset, 0,
833 create_immed(b, intr->num_components), 0,
834 create_immed(b, base), 0);
835
836 ldl->cat6.type = utype_dst(intr->dest);
837 ldl->regs[0]->wrmask = MASK(intr->num_components);
838
839 ldl->barrier_class = IR3_BARRIER_SHARED_R;
840 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
841
842 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
843 }
844
845 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
846 static void
847 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
848 {
849 struct ir3_block *b = ctx->block;
850 struct ir3_instruction *stl, *offset;
851 struct ir3_instruction * const *value;
852 unsigned base, wrmask;
853
854 value = ir3_get_src(ctx, &intr->src[0]);
855 offset = ir3_get_src(ctx, &intr->src[1])[0];
856
857 base = nir_intrinsic_base(intr);
858 wrmask = nir_intrinsic_write_mask(intr);
859
860 /* Combine groups of consecutive enabled channels in one write
861 * message. We use ffs to find the first enabled channel and then ffs on
862 * the bit-inverse, down-shifted writemask to determine the length of
863 * the block of enabled bits.
864 *
865 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
866 */
867 while (wrmask) {
868 unsigned first_component = ffs(wrmask) - 1;
869 unsigned length = ffs(~(wrmask >> first_component)) - 1;
870
871 stl = ir3_STL(b, offset, 0,
872 ir3_create_collect(ctx, &value[first_component], length), 0,
873 create_immed(b, length), 0);
874 stl->cat6.dst_offset = first_component + base;
875 stl->cat6.type = utype_src(intr->src[0]);
876 stl->barrier_class = IR3_BARRIER_SHARED_W;
877 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
878
879 array_insert(b, b->keeps, stl);
880
881 /* Clear the bits in the writemask that we just wrote, then try
882 * again to see if more channels are left.
883 */
884 wrmask &= (15 << (first_component + length));
885 }
886 }
887
888 /* src[] = { offset }. const_index[] = { base } */
889 static void
890 emit_intrinsic_load_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr,
891 struct ir3_instruction **dst)
892 {
893 struct ir3_block *b = ctx->block;
894 struct ir3_instruction *load, *offset;
895 unsigned base;
896
897 offset = ir3_get_src(ctx, &intr->src[0])[0];
898 base = nir_intrinsic_base(intr);
899
900 load = ir3_LDLW(b, offset, 0,
901 create_immed(b, intr->num_components), 0,
902 create_immed(b, base), 0);
903
904 load->cat6.type = utype_dst(intr->dest);
905 load->regs[0]->wrmask = MASK(intr->num_components);
906
907 load->barrier_class = IR3_BARRIER_SHARED_R;
908 load->barrier_conflict = IR3_BARRIER_SHARED_W;
909
910 ir3_split_dest(b, dst, load, 0, intr->num_components);
911 }
912
913 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
914 static void
915 emit_intrinsic_store_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr)
916 {
917 struct ir3_block *b = ctx->block;
918 struct ir3_instruction *store, *offset;
919 struct ir3_instruction * const *value;
920 unsigned base, wrmask;
921
922 value = ir3_get_src(ctx, &intr->src[0]);
923 offset = ir3_get_src(ctx, &intr->src[1])[0];
924
925 base = nir_intrinsic_base(intr);
926 wrmask = nir_intrinsic_write_mask(intr);
927
928 /* Combine groups of consecutive enabled channels in one write
929 * message. We use ffs to find the first enabled channel and then ffs on
930 * the bit-inverse, down-shifted writemask to determine the length of
931 * the block of enabled bits.
932 *
933 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
934 */
935 while (wrmask) {
936 unsigned first_component = ffs(wrmask) - 1;
937 unsigned length = ffs(~(wrmask >> first_component)) - 1;
938
939 store = ir3_STLW(b, offset, 0,
940 ir3_create_collect(ctx, &value[first_component], length), 0,
941 create_immed(b, length), 0);
942
943 store->cat6.dst_offset = first_component + base;
944 store->cat6.type = utype_src(intr->src[0]);
945 store->barrier_class = IR3_BARRIER_SHARED_W;
946 store->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
947
948 array_insert(b, b->keeps, store);
949
950 /* Clear the bits in the writemask that we just wrote, then try
951 * again to see if more channels are left.
952 */
953 wrmask &= (15 << (first_component + length));
954 }
955 }
956
957 /*
958 * CS shared variable atomic intrinsics
959 *
960 * All of the shared variable atomic memory operations read a value from
961 * memory, compute a new value using one of the operations below, write the
962 * new value to memory, and return the original value read.
963 *
964 * All operations take 2 sources except CompSwap that takes 3. These
965 * sources represent:
966 *
967 * 0: The offset into the shared variable storage region that the atomic
968 * operation will operate on.
969 * 1: The data parameter to the atomic function (i.e. the value to add
970 * in shared_atomic_add, etc).
971 * 2: For CompSwap only: the second data parameter.
972 */
973 static struct ir3_instruction *
974 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
975 {
976 struct ir3_block *b = ctx->block;
977 struct ir3_instruction *atomic, *src0, *src1;
978 type_t type = TYPE_U32;
979
980 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
981 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
982
983 switch (intr->intrinsic) {
984 case nir_intrinsic_shared_atomic_add:
985 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
986 break;
987 case nir_intrinsic_shared_atomic_imin:
988 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
989 type = TYPE_S32;
990 break;
991 case nir_intrinsic_shared_atomic_umin:
992 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
993 break;
994 case nir_intrinsic_shared_atomic_imax:
995 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
996 type = TYPE_S32;
997 break;
998 case nir_intrinsic_shared_atomic_umax:
999 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1000 break;
1001 case nir_intrinsic_shared_atomic_and:
1002 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
1003 break;
1004 case nir_intrinsic_shared_atomic_or:
1005 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
1006 break;
1007 case nir_intrinsic_shared_atomic_xor:
1008 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
1009 break;
1010 case nir_intrinsic_shared_atomic_exchange:
1011 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
1012 break;
1013 case nir_intrinsic_shared_atomic_comp_swap:
1014 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1015 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1016 ir3_get_src(ctx, &intr->src[2])[0],
1017 src1,
1018 }, 2);
1019 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
1020 break;
1021 default:
1022 unreachable("boo");
1023 }
1024
1025 atomic->cat6.iim_val = 1;
1026 atomic->cat6.d = 1;
1027 atomic->cat6.type = type;
1028 atomic->barrier_class = IR3_BARRIER_SHARED_W;
1029 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
1030
1031 /* even if nothing consume the result, we can't DCE the instruction: */
1032 array_insert(b, b->keeps, atomic);
1033
1034 return atomic;
1035 }
1036
1037 /* TODO handle actual indirect/dynamic case.. which is going to be weird
1038 * to handle with the image_mapping table..
1039 */
1040 static struct ir3_instruction *
1041 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1042 {
1043 unsigned slot = ir3_get_image_slot(nir_src_as_deref(intr->src[0]));
1044 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
1045 struct ir3_instruction *texture, *sampler;
1046
1047 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1048 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1049
1050 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1051 sampler,
1052 texture,
1053 }, 2);
1054 }
1055
1056 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1057 static void
1058 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1059 struct ir3_instruction **dst)
1060 {
1061 struct ir3_block *b = ctx->block;
1062 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1063 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
1064 struct ir3_instruction *sam;
1065 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
1066 struct ir3_instruction *coords[4];
1067 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
1068 type_t type = ir3_get_image_type(var);
1069
1070 /* hmm, this seems a bit odd, but it is what blob does and (at least
1071 * a5xx) just faults on bogus addresses otherwise:
1072 */
1073 if (flags & IR3_INSTR_3D) {
1074 flags &= ~IR3_INSTR_3D;
1075 flags |= IR3_INSTR_A;
1076 }
1077
1078 for (unsigned i = 0; i < ncoords; i++)
1079 coords[i] = src0[i];
1080
1081 if (ncoords == 1)
1082 coords[ncoords++] = create_immed(b, 0);
1083
1084 sam = ir3_SAM(b, OPC_ISAM, type, 0b1111, flags,
1085 samp_tex, ir3_create_collect(ctx, coords, ncoords), NULL);
1086
1087 sam->barrier_class = IR3_BARRIER_IMAGE_R;
1088 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
1089
1090 ir3_split_dest(b, dst, sam, 0, 4);
1091 }
1092
1093 static void
1094 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1095 struct ir3_instruction **dst)
1096 {
1097 struct ir3_block *b = ctx->block;
1098 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1099 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
1100 struct ir3_instruction *sam, *lod;
1101 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
1102 type_t dst_type = nir_dest_bit_size(intr->dest) < 32 ?
1103 TYPE_U16 : TYPE_U32;
1104
1105 lod = create_immed(b, 0);
1106 sam = ir3_SAM(b, OPC_GETSIZE, dst_type, 0b1111, flags,
1107 samp_tex, lod, NULL);
1108
1109 /* Array size actually ends up in .w rather than .z. This doesn't
1110 * matter for miplevel 0, but for higher mips the value in z is
1111 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1112 * returned, which means that we have to add 1 to it for arrays for
1113 * a3xx.
1114 *
1115 * Note use a temporary dst and then copy, since the size of the dst
1116 * array that is passed in is based on nir's understanding of the
1117 * result size, not the hardware's
1118 */
1119 struct ir3_instruction *tmp[4];
1120
1121 ir3_split_dest(b, tmp, sam, 0, 4);
1122
1123 /* get_size instruction returns size in bytes instead of texels
1124 * for imageBuffer, so we need to divide it by the pixel size
1125 * of the image format.
1126 *
1127 * TODO: This is at least true on a5xx. Check other gens.
1128 */
1129 enum glsl_sampler_dim dim =
1130 glsl_get_sampler_dim(glsl_without_array(var->type));
1131 if (dim == GLSL_SAMPLER_DIM_BUF) {
1132 /* Since all the possible values the divisor can take are
1133 * power-of-two (4, 8, or 16), the division is implemented
1134 * as a shift-right.
1135 * During shader setup, the log2 of the image format's
1136 * bytes-per-pixel should have been emitted in 2nd slot of
1137 * image_dims. See ir3_shader::emit_image_dims().
1138 */
1139 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
1140 unsigned cb = regid(const_state->offsets.image_dims, 0) +
1141 const_state->image_dims.off[var->data.driver_location];
1142 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1143
1144 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1145 }
1146
1147 for (unsigned i = 0; i < ncoords; i++)
1148 dst[i] = tmp[i];
1149
1150 if (flags & IR3_INSTR_A) {
1151 if (ctx->compiler->levels_add_one) {
1152 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1153 } else {
1154 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1155 }
1156 }
1157 }
1158
1159 static void
1160 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1161 {
1162 struct ir3_block *b = ctx->block;
1163 struct ir3_instruction *barrier;
1164
1165 switch (intr->intrinsic) {
1166 case nir_intrinsic_control_barrier:
1167 barrier = ir3_BAR(b);
1168 barrier->cat7.g = true;
1169 barrier->cat7.l = true;
1170 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1171 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1172 break;
1173 case nir_intrinsic_memory_barrier:
1174 barrier = ir3_FENCE(b);
1175 barrier->cat7.g = true;
1176 barrier->cat7.r = true;
1177 barrier->cat7.w = true;
1178 barrier->cat7.l = true;
1179 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1180 IR3_BARRIER_BUFFER_W;
1181 barrier->barrier_conflict =
1182 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1183 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1184 break;
1185 case nir_intrinsic_memory_barrier_buffer:
1186 barrier = ir3_FENCE(b);
1187 barrier->cat7.g = true;
1188 barrier->cat7.r = true;
1189 barrier->cat7.w = true;
1190 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1191 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1192 IR3_BARRIER_BUFFER_W;
1193 break;
1194 case nir_intrinsic_memory_barrier_image:
1195 // TODO double check if this should have .g set
1196 barrier = ir3_FENCE(b);
1197 barrier->cat7.g = true;
1198 barrier->cat7.r = true;
1199 barrier->cat7.w = true;
1200 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1201 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1202 IR3_BARRIER_IMAGE_W;
1203 break;
1204 case nir_intrinsic_memory_barrier_shared:
1205 barrier = ir3_FENCE(b);
1206 barrier->cat7.g = true;
1207 barrier->cat7.l = true;
1208 barrier->cat7.r = true;
1209 barrier->cat7.w = true;
1210 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1211 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1212 IR3_BARRIER_SHARED_W;
1213 break;
1214 case nir_intrinsic_group_memory_barrier:
1215 barrier = ir3_FENCE(b);
1216 barrier->cat7.g = true;
1217 barrier->cat7.l = true;
1218 barrier->cat7.r = true;
1219 barrier->cat7.w = true;
1220 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1221 IR3_BARRIER_IMAGE_W |
1222 IR3_BARRIER_BUFFER_W;
1223 barrier->barrier_conflict =
1224 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1225 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1226 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1227 break;
1228 default:
1229 unreachable("boo");
1230 }
1231
1232 /* make sure barrier doesn't get DCE'd */
1233 array_insert(b, b->keeps, barrier);
1234 }
1235
1236 static void add_sysval_input_compmask(struct ir3_context *ctx,
1237 gl_system_value slot, unsigned compmask,
1238 struct ir3_instruction *instr)
1239 {
1240 struct ir3_shader_variant *so = ctx->so;
1241 unsigned n = so->inputs_count++;
1242
1243 assert(instr->opc == OPC_META_INPUT);
1244 instr->input.inidx = n;
1245 instr->input.sysval = slot;
1246
1247 so->inputs[n].sysval = true;
1248 so->inputs[n].slot = slot;
1249 so->inputs[n].compmask = compmask;
1250 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1251 so->total_in++;
1252 }
1253
1254 static struct ir3_instruction *
1255 create_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1256 unsigned compmask)
1257 {
1258 assert(compmask);
1259 struct ir3_instruction *sysval = create_input(ctx, compmask);
1260 add_sysval_input_compmask(ctx, slot, compmask, sysval);
1261 return sysval;
1262 }
1263
1264 static struct ir3_instruction *
1265 get_barycentric_centroid(struct ir3_context *ctx)
1266 {
1267 if (!ctx->ij_centroid) {
1268 struct ir3_instruction *xy[2];
1269 struct ir3_instruction *ij;
1270
1271 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID, 0x3);
1272 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1273
1274 ctx->ij_centroid = ir3_create_collect(ctx, xy, 2);
1275 }
1276
1277 return ctx->ij_centroid;
1278 }
1279
1280 static struct ir3_instruction *
1281 get_barycentric_sample(struct ir3_context *ctx)
1282 {
1283 if (!ctx->ij_sample) {
1284 struct ir3_instruction *xy[2];
1285 struct ir3_instruction *ij;
1286
1287 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE, 0x3);
1288 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1289
1290 ctx->ij_sample = ir3_create_collect(ctx, xy, 2);
1291 }
1292
1293 return ctx->ij_sample;
1294 }
1295
1296 static struct ir3_instruction *
1297 get_barycentric_pixel(struct ir3_context *ctx)
1298 {
1299 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1300 * this to create ij_pixel only on demand:
1301 */
1302 return ctx->ij_pixel;
1303 }
1304
1305 static struct ir3_instruction *
1306 get_frag_coord(struct ir3_context *ctx)
1307 {
1308 if (!ctx->frag_coord) {
1309 struct ir3_block *b = ctx->block;
1310 struct ir3_instruction *xyzw[4];
1311 struct ir3_instruction *hw_frag_coord;
1312
1313 hw_frag_coord = create_sysval_input(ctx, SYSTEM_VALUE_FRAG_COORD, 0xf);
1314 ir3_split_dest(ctx->block, xyzw, hw_frag_coord, 0, 4);
1315
1316 /* for frag_coord.xy, we get unsigned values.. we need
1317 * to subtract (integer) 8 and divide by 16 (right-
1318 * shift by 4) then convert to float:
1319 *
1320 * sub.s tmp, src, 8
1321 * shr.b tmp, tmp, 4
1322 * mov.u32f32 dst, tmp
1323 *
1324 */
1325 for (int i = 0; i < 2; i++) {
1326 xyzw[i] = ir3_SUB_S(b, xyzw[i], 0,
1327 create_immed(b, 8), 0);
1328 xyzw[i] = ir3_SHR_B(b, xyzw[i], 0,
1329 create_immed(b, 4), 0);
1330 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1331 }
1332
1333 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1334 ctx->so->frag_coord = true;
1335 }
1336
1337 return ctx->frag_coord;
1338 }
1339
1340 static void
1341 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1342 {
1343 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1344 struct ir3_instruction **dst;
1345 struct ir3_instruction * const *src;
1346 struct ir3_block *b = ctx->block;
1347 int idx, comp;
1348
1349 if (info->has_dest) {
1350 unsigned n = nir_intrinsic_dest_components(intr);
1351 dst = ir3_get_dst(ctx, &intr->dest, n);
1352 } else {
1353 dst = NULL;
1354 }
1355
1356 const unsigned primitive_param = ctx->so->shader->const_state.offsets.primitive_param * 4;
1357 const unsigned primitive_map = ctx->so->shader->const_state.offsets.primitive_map * 4;
1358
1359 switch (intr->intrinsic) {
1360 case nir_intrinsic_load_uniform:
1361 idx = nir_intrinsic_base(intr);
1362 if (nir_src_is_const(intr->src[0])) {
1363 idx += nir_src_as_uint(intr->src[0]);
1364 for (int i = 0; i < intr->num_components; i++) {
1365 dst[i] = create_uniform_typed(b, idx + i,
1366 nir_dest_bit_size(intr->dest) < 32 ? TYPE_F16 : TYPE_F32);
1367 }
1368 } else {
1369 src = ir3_get_src(ctx, &intr->src[0]);
1370 for (int i = 0; i < intr->num_components; i++) {
1371 dst[i] = create_uniform_indirect(b, idx + i,
1372 ir3_get_addr(ctx, src[0], 1));
1373 }
1374 /* NOTE: if relative addressing is used, we set
1375 * constlen in the compiler (to worst-case value)
1376 * since we don't know in the assembler what the max
1377 * addr reg value can be:
1378 */
1379 ctx->so->constlen = MAX2(ctx->so->constlen,
1380 ctx->so->shader->ubo_state.size / 16);
1381 }
1382 break;
1383
1384 case nir_intrinsic_load_vs_primitive_stride_ir3:
1385 dst[0] = create_uniform(b, primitive_param + 0);
1386 break;
1387 case nir_intrinsic_load_vs_vertex_stride_ir3:
1388 dst[0] = create_uniform(b, primitive_param + 1);
1389 break;
1390 case nir_intrinsic_load_hs_patch_stride_ir3:
1391 dst[0] = create_uniform(b, primitive_param + 2);
1392 break;
1393 case nir_intrinsic_load_patch_vertices_in:
1394 dst[0] = create_uniform(b, primitive_param + 3);
1395 break;
1396 case nir_intrinsic_load_tess_param_base_ir3:
1397 dst[0] = create_uniform(b, primitive_param + 4);
1398 dst[1] = create_uniform(b, primitive_param + 5);
1399 break;
1400 case nir_intrinsic_load_tess_factor_base_ir3:
1401 dst[0] = create_uniform(b, primitive_param + 6);
1402 dst[1] = create_uniform(b, primitive_param + 7);
1403 break;
1404
1405 case nir_intrinsic_load_primitive_location_ir3:
1406 idx = nir_intrinsic_driver_location(intr);
1407 dst[0] = create_uniform(b, primitive_map + idx);
1408 break;
1409
1410 case nir_intrinsic_load_gs_header_ir3:
1411 dst[0] = ctx->gs_header;
1412 break;
1413 case nir_intrinsic_load_tcs_header_ir3:
1414 dst[0] = ctx->tcs_header;
1415 break;
1416
1417 case nir_intrinsic_load_primitive_id:
1418 dst[0] = ctx->primitive_id;
1419 break;
1420
1421 case nir_intrinsic_load_tess_coord:
1422 if (!ctx->tess_coord) {
1423 ctx->tess_coord =
1424 create_sysval_input(ctx, SYSTEM_VALUE_TESS_COORD, 0x3);
1425 }
1426 ir3_split_dest(b, dst, ctx->tess_coord, 0, 2);
1427
1428 /* Unused, but ir3_put_dst() below wants to free something */
1429 dst[2] = create_immed(b, 0);
1430 break;
1431
1432 case nir_intrinsic_end_patch_ir3:
1433 assert(ctx->so->type == MESA_SHADER_TESS_CTRL);
1434 struct ir3_instruction *end = ir3_ENDIF(b);
1435 array_insert(b, b->keeps, end);
1436
1437 end->barrier_class = IR3_BARRIER_EVERYTHING;
1438 end->barrier_conflict = IR3_BARRIER_EVERYTHING;
1439 break;
1440
1441 case nir_intrinsic_store_global_ir3: {
1442 struct ir3_instruction *value, *addr, *offset;
1443
1444 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1445 ir3_get_src(ctx, &intr->src[1])[0],
1446 ir3_get_src(ctx, &intr->src[1])[1]
1447 }, 2);
1448
1449 offset = ir3_get_src(ctx, &intr->src[2])[0];
1450
1451 value = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]),
1452 intr->num_components);
1453
1454 struct ir3_instruction *stg =
1455 ir3_STG_G(ctx->block, addr, 0, value, 0,
1456 create_immed(ctx->block, intr->num_components), 0, offset, 0);
1457 stg->cat6.type = TYPE_U32;
1458 stg->cat6.iim_val = 1;
1459
1460 array_insert(b, b->keeps, stg);
1461
1462 stg->barrier_class = IR3_BARRIER_BUFFER_W;
1463 stg->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1464 break;
1465 }
1466
1467 case nir_intrinsic_load_global_ir3: {
1468 struct ir3_instruction *addr, *offset;
1469
1470 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1471 ir3_get_src(ctx, &intr->src[0])[0],
1472 ir3_get_src(ctx, &intr->src[0])[1]
1473 }, 2);
1474
1475 offset = ir3_get_src(ctx, &intr->src[1])[0];
1476
1477 struct ir3_instruction *load =
1478 ir3_LDG(b, addr, 0, create_immed(ctx->block, intr->num_components),
1479 0, offset, 0);
1480 load->cat6.type = TYPE_U32;
1481 load->regs[0]->wrmask = MASK(intr->num_components);
1482
1483 load->barrier_class = IR3_BARRIER_BUFFER_R;
1484 load->barrier_conflict = IR3_BARRIER_BUFFER_W;
1485
1486 ir3_split_dest(b, dst, load, 0, intr->num_components);
1487 break;
1488 }
1489
1490 case nir_intrinsic_load_ubo:
1491 emit_intrinsic_load_ubo(ctx, intr, dst);
1492 break;
1493 case nir_intrinsic_load_frag_coord:
1494 ir3_split_dest(b, dst, get_frag_coord(ctx), 0, 4);
1495 break;
1496 case nir_intrinsic_load_sample_pos_from_id: {
1497 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1498 * but that doesn't seem necessary.
1499 */
1500 struct ir3_instruction *offset =
1501 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1502 offset->regs[0]->wrmask = 0x3;
1503 offset->cat5.type = TYPE_F32;
1504
1505 ir3_split_dest(b, dst, offset, 0, 2);
1506
1507 break;
1508 }
1509 case nir_intrinsic_load_size_ir3:
1510 if (!ctx->ij_size) {
1511 ctx->ij_size =
1512 create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE, 0x1);
1513 }
1514 dst[0] = ctx->ij_size;
1515 break;
1516 case nir_intrinsic_load_barycentric_centroid:
1517 ir3_split_dest(b, dst, get_barycentric_centroid(ctx), 0, 2);
1518 break;
1519 case nir_intrinsic_load_barycentric_sample:
1520 if (ctx->so->key.msaa) {
1521 ir3_split_dest(b, dst, get_barycentric_sample(ctx), 0, 2);
1522 } else {
1523 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1524 }
1525 break;
1526 case nir_intrinsic_load_barycentric_pixel:
1527 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1528 break;
1529 case nir_intrinsic_load_interpolated_input:
1530 idx = nir_intrinsic_base(intr);
1531 comp = nir_intrinsic_component(intr);
1532 src = ir3_get_src(ctx, &intr->src[0]);
1533 if (nir_src_is_const(intr->src[1])) {
1534 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1535 idx += nir_src_as_uint(intr->src[1]);
1536 for (int i = 0; i < intr->num_components; i++) {
1537 unsigned inloc = idx * 4 + i + comp;
1538 if (ctx->so->inputs[idx].bary &&
1539 !ctx->so->inputs[idx].use_ldlv) {
1540 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1541 } else {
1542 /* for non-varyings use the pre-setup input, since
1543 * that is easier than mapping things back to a
1544 * nir_variable to figure out what it is.
1545 */
1546 dst[i] = ctx->inputs[inloc];
1547 }
1548 }
1549 } else {
1550 ir3_context_error(ctx, "unhandled");
1551 }
1552 break;
1553 case nir_intrinsic_load_input:
1554 idx = nir_intrinsic_base(intr);
1555 comp = nir_intrinsic_component(intr);
1556 if (nir_src_is_const(intr->src[0])) {
1557 idx += nir_src_as_uint(intr->src[0]);
1558 for (int i = 0; i < intr->num_components; i++) {
1559 unsigned n = idx * 4 + i + comp;
1560 dst[i] = ctx->inputs[n];
1561 compile_assert(ctx, ctx->inputs[n]);
1562 }
1563 } else {
1564 src = ir3_get_src(ctx, &intr->src[0]);
1565 struct ir3_instruction *collect =
1566 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ninputs);
1567 struct ir3_instruction *addr = ir3_get_addr(ctx, src[0], 4);
1568 for (int i = 0; i < intr->num_components; i++) {
1569 unsigned n = idx * 4 + i + comp;
1570 dst[i] = create_indirect_load(ctx, ctx->ninputs,
1571 n, addr, collect);
1572 }
1573 }
1574 break;
1575 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1576 * pass and replaced by an ir3-specifc version that adds the
1577 * dword-offset in the last source.
1578 */
1579 case nir_intrinsic_load_ssbo_ir3:
1580 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1581 break;
1582 case nir_intrinsic_store_ssbo_ir3:
1583 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1584 !ctx->s->info.fs.early_fragment_tests)
1585 ctx->so->no_earlyz = true;
1586 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1587 break;
1588 case nir_intrinsic_get_buffer_size:
1589 emit_intrinsic_ssbo_size(ctx, intr, dst);
1590 break;
1591 case nir_intrinsic_ssbo_atomic_add_ir3:
1592 case nir_intrinsic_ssbo_atomic_imin_ir3:
1593 case nir_intrinsic_ssbo_atomic_umin_ir3:
1594 case nir_intrinsic_ssbo_atomic_imax_ir3:
1595 case nir_intrinsic_ssbo_atomic_umax_ir3:
1596 case nir_intrinsic_ssbo_atomic_and_ir3:
1597 case nir_intrinsic_ssbo_atomic_or_ir3:
1598 case nir_intrinsic_ssbo_atomic_xor_ir3:
1599 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1600 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1601 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1602 !ctx->s->info.fs.early_fragment_tests)
1603 ctx->so->no_earlyz = true;
1604 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1605 break;
1606 case nir_intrinsic_load_shared:
1607 emit_intrinsic_load_shared(ctx, intr, dst);
1608 break;
1609 case nir_intrinsic_store_shared:
1610 emit_intrinsic_store_shared(ctx, intr);
1611 break;
1612 case nir_intrinsic_shared_atomic_add:
1613 case nir_intrinsic_shared_atomic_imin:
1614 case nir_intrinsic_shared_atomic_umin:
1615 case nir_intrinsic_shared_atomic_imax:
1616 case nir_intrinsic_shared_atomic_umax:
1617 case nir_intrinsic_shared_atomic_and:
1618 case nir_intrinsic_shared_atomic_or:
1619 case nir_intrinsic_shared_atomic_xor:
1620 case nir_intrinsic_shared_atomic_exchange:
1621 case nir_intrinsic_shared_atomic_comp_swap:
1622 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1623 break;
1624 case nir_intrinsic_image_deref_load:
1625 emit_intrinsic_load_image(ctx, intr, dst);
1626 break;
1627 case nir_intrinsic_image_deref_store:
1628 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1629 !ctx->s->info.fs.early_fragment_tests)
1630 ctx->so->no_earlyz = true;
1631 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1632 break;
1633 case nir_intrinsic_image_deref_size:
1634 emit_intrinsic_image_size(ctx, intr, dst);
1635 break;
1636 case nir_intrinsic_image_deref_atomic_add:
1637 case nir_intrinsic_image_deref_atomic_imin:
1638 case nir_intrinsic_image_deref_atomic_umin:
1639 case nir_intrinsic_image_deref_atomic_imax:
1640 case nir_intrinsic_image_deref_atomic_umax:
1641 case nir_intrinsic_image_deref_atomic_and:
1642 case nir_intrinsic_image_deref_atomic_or:
1643 case nir_intrinsic_image_deref_atomic_xor:
1644 case nir_intrinsic_image_deref_atomic_exchange:
1645 case nir_intrinsic_image_deref_atomic_comp_swap:
1646 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1647 !ctx->s->info.fs.early_fragment_tests)
1648 ctx->so->no_earlyz = true;
1649 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1650 break;
1651 case nir_intrinsic_control_barrier:
1652 case nir_intrinsic_memory_barrier:
1653 case nir_intrinsic_group_memory_barrier:
1654 case nir_intrinsic_memory_barrier_buffer:
1655 case nir_intrinsic_memory_barrier_image:
1656 case nir_intrinsic_memory_barrier_shared:
1657 emit_intrinsic_barrier(ctx, intr);
1658 /* note that blk ptr no longer valid, make that obvious: */
1659 b = NULL;
1660 break;
1661 case nir_intrinsic_store_output:
1662 idx = nir_intrinsic_base(intr);
1663 comp = nir_intrinsic_component(intr);
1664 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1665 idx += nir_src_as_uint(intr->src[1]);
1666
1667 src = ir3_get_src(ctx, &intr->src[0]);
1668 for (int i = 0; i < intr->num_components; i++) {
1669 unsigned n = idx * 4 + i + comp;
1670 ctx->outputs[n] = src[i];
1671 }
1672 break;
1673 case nir_intrinsic_load_base_vertex:
1674 case nir_intrinsic_load_first_vertex:
1675 if (!ctx->basevertex) {
1676 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1677 }
1678 dst[0] = ctx->basevertex;
1679 break;
1680 case nir_intrinsic_load_base_instance:
1681 if (!ctx->base_instance) {
1682 ctx->base_instance = create_driver_param(ctx, IR3_DP_INSTID_BASE);
1683 }
1684 dst[0] = ctx->base_instance;
1685 break;
1686 case nir_intrinsic_load_vertex_id_zero_base:
1687 case nir_intrinsic_load_vertex_id:
1688 if (!ctx->vertex_id) {
1689 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1690 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1691 ctx->vertex_id = create_sysval_input(ctx, sv, 0x1);
1692 }
1693 dst[0] = ctx->vertex_id;
1694 break;
1695 case nir_intrinsic_load_instance_id:
1696 if (!ctx->instance_id) {
1697 ctx->instance_id = create_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID, 0x1);
1698 }
1699 dst[0] = ctx->instance_id;
1700 break;
1701 case nir_intrinsic_load_sample_id:
1702 ctx->so->per_samp = true;
1703 /* fall-thru */
1704 case nir_intrinsic_load_sample_id_no_per_sample:
1705 if (!ctx->samp_id) {
1706 ctx->samp_id = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID, 0x1);
1707 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1708 }
1709 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1710 break;
1711 case nir_intrinsic_load_sample_mask_in:
1712 if (!ctx->samp_mask_in) {
1713 ctx->samp_mask_in = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN, 0x1);
1714 }
1715 dst[0] = ctx->samp_mask_in;
1716 break;
1717 case nir_intrinsic_load_user_clip_plane:
1718 idx = nir_intrinsic_ucp_id(intr);
1719 for (int i = 0; i < intr->num_components; i++) {
1720 unsigned n = idx * 4 + i;
1721 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1722 }
1723 break;
1724 case nir_intrinsic_load_front_face:
1725 if (!ctx->frag_face) {
1726 ctx->so->frag_face = true;
1727 ctx->frag_face = create_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, 0x1);
1728 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1729 }
1730 /* for fragface, we get -1 for back and 0 for front. However this is
1731 * the inverse of what nir expects (where ~0 is true).
1732 */
1733 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1734 dst[0] = ir3_NOT_B(b, dst[0], 0);
1735 break;
1736 case nir_intrinsic_load_local_invocation_id:
1737 if (!ctx->local_invocation_id) {
1738 ctx->local_invocation_id =
1739 create_sysval_input(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID, 0x7);
1740 }
1741 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1742 break;
1743 case nir_intrinsic_load_work_group_id:
1744 if (!ctx->work_group_id) {
1745 ctx->work_group_id =
1746 create_sysval_input(ctx, SYSTEM_VALUE_WORK_GROUP_ID, 0x7);
1747 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1748 }
1749 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1750 break;
1751 case nir_intrinsic_load_num_work_groups:
1752 for (int i = 0; i < intr->num_components; i++) {
1753 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1754 }
1755 break;
1756 case nir_intrinsic_load_local_group_size:
1757 for (int i = 0; i < intr->num_components; i++) {
1758 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1759 }
1760 break;
1761 case nir_intrinsic_discard_if:
1762 case nir_intrinsic_discard: {
1763 struct ir3_instruction *cond, *kill;
1764
1765 if (intr->intrinsic == nir_intrinsic_discard_if) {
1766 /* conditional discard: */
1767 src = ir3_get_src(ctx, &intr->src[0]);
1768 cond = ir3_b2n(b, src[0]);
1769 } else {
1770 /* unconditional discard: */
1771 cond = create_immed(b, 1);
1772 }
1773
1774 /* NOTE: only cmps.*.* can write p0.x: */
1775 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1776 cond->cat2.condition = IR3_COND_NE;
1777
1778 /* condition always goes in predicate register: */
1779 cond->regs[0]->num = regid(REG_P0, 0);
1780 cond->regs[0]->flags &= ~IR3_REG_SSA;
1781
1782 kill = ir3_KILL(b, cond, 0);
1783 array_insert(ctx->ir, ctx->ir->predicates, kill);
1784
1785 array_insert(b, b->keeps, kill);
1786 ctx->so->no_earlyz = true;
1787
1788 break;
1789 }
1790
1791 case nir_intrinsic_cond_end_ir3: {
1792 struct ir3_instruction *cond, *kill;
1793
1794 src = ir3_get_src(ctx, &intr->src[0]);
1795 cond = ir3_b2n(b, src[0]);
1796
1797 /* NOTE: only cmps.*.* can write p0.x: */
1798 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1799 cond->cat2.condition = IR3_COND_NE;
1800
1801 /* condition always goes in predicate register: */
1802 cond->regs[0]->num = regid(REG_P0, 0);
1803
1804 kill = ir3_IF(b, cond, 0);
1805
1806 kill->barrier_class = IR3_BARRIER_EVERYTHING;
1807 kill->barrier_conflict = IR3_BARRIER_EVERYTHING;
1808
1809 array_insert(ctx->ir, ctx->ir->predicates, kill);
1810 array_insert(b, b->keeps, kill);
1811 break;
1812 }
1813
1814 case nir_intrinsic_load_shared_ir3:
1815 emit_intrinsic_load_shared_ir3(ctx, intr, dst);
1816 break;
1817 case nir_intrinsic_store_shared_ir3:
1818 emit_intrinsic_store_shared_ir3(ctx, intr);
1819 break;
1820 default:
1821 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1822 nir_intrinsic_infos[intr->intrinsic].name);
1823 break;
1824 }
1825
1826 if (info->has_dest)
1827 ir3_put_dst(ctx, &intr->dest);
1828 }
1829
1830 static void
1831 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1832 {
1833 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1834 instr->def.num_components);
1835
1836 if (instr->def.bit_size < 32) {
1837 for (int i = 0; i < instr->def.num_components; i++)
1838 dst[i] = create_immed_typed(ctx->block,
1839 instr->value[i].u16,
1840 TYPE_U16);
1841 } else {
1842 for (int i = 0; i < instr->def.num_components; i++)
1843 dst[i] = create_immed_typed(ctx->block,
1844 instr->value[i].u32,
1845 TYPE_U32);
1846 }
1847
1848 }
1849
1850 static void
1851 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1852 {
1853 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1854 undef->def.num_components);
1855 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1856
1857 /* backend doesn't want undefined instructions, so just plug
1858 * in 0.0..
1859 */
1860 for (int i = 0; i < undef->def.num_components; i++)
1861 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1862 }
1863
1864 /*
1865 * texture fetch/sample instructions:
1866 */
1867
1868 static type_t
1869 get_tex_dest_type(nir_tex_instr *tex)
1870 {
1871 type_t type;
1872
1873 switch (nir_alu_type_get_base_type(tex->dest_type)) {
1874 case nir_type_invalid:
1875 case nir_type_float:
1876 type = nir_dest_bit_size(tex->dest) < 32 ? TYPE_F16 : TYPE_F32;
1877 break;
1878 case nir_type_int:
1879 type = nir_dest_bit_size(tex->dest) < 32 ? TYPE_S16 : TYPE_S32;
1880 break;
1881 case nir_type_uint:
1882 case nir_type_bool:
1883 type = nir_dest_bit_size(tex->dest) < 32 ? TYPE_U16 : TYPE_U32;
1884 break;
1885 default:
1886 unreachable("bad dest_type");
1887 }
1888
1889 return type;
1890 }
1891
1892 static void
1893 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1894 {
1895 unsigned coords, flags = 0;
1896
1897 /* note: would use tex->coord_components.. except txs.. also,
1898 * since array index goes after shadow ref, we don't want to
1899 * count it:
1900 */
1901 switch (tex->sampler_dim) {
1902 case GLSL_SAMPLER_DIM_1D:
1903 case GLSL_SAMPLER_DIM_BUF:
1904 coords = 1;
1905 break;
1906 case GLSL_SAMPLER_DIM_2D:
1907 case GLSL_SAMPLER_DIM_RECT:
1908 case GLSL_SAMPLER_DIM_EXTERNAL:
1909 case GLSL_SAMPLER_DIM_MS:
1910 case GLSL_SAMPLER_DIM_SUBPASS:
1911 case GLSL_SAMPLER_DIM_SUBPASS_MS:
1912 coords = 2;
1913 break;
1914 case GLSL_SAMPLER_DIM_3D:
1915 case GLSL_SAMPLER_DIM_CUBE:
1916 coords = 3;
1917 flags |= IR3_INSTR_3D;
1918 break;
1919 default:
1920 unreachable("bad sampler_dim");
1921 }
1922
1923 if (tex->is_shadow && tex->op != nir_texop_lod)
1924 flags |= IR3_INSTR_S;
1925
1926 if (tex->is_array && tex->op != nir_texop_lod)
1927 flags |= IR3_INSTR_A;
1928
1929 *flagsp = flags;
1930 *coordsp = coords;
1931 }
1932
1933 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
1934 * or immediate (in which case it will get lowered later to a non .s2en
1935 * version of the tex instruction which encode tex/samp as immediates:
1936 */
1937 static struct ir3_instruction *
1938 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
1939 {
1940 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
1941 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
1942 struct ir3_instruction *texture, *sampler;
1943
1944 if (texture_idx >= 0) {
1945 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
1946 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
1947 } else {
1948 /* TODO what to do for dynamic case? I guess we only need the
1949 * max index for astc srgb workaround so maybe not a problem
1950 * to worry about if we don't enable indirect samplers for
1951 * a4xx?
1952 */
1953 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
1954 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
1955 }
1956
1957 if (sampler_idx >= 0) {
1958 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
1959 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
1960 } else {
1961 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
1962 }
1963
1964 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1965 sampler,
1966 texture,
1967 }, 2);
1968 }
1969
1970 static void
1971 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
1972 {
1973 struct ir3_block *b = ctx->block;
1974 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1975 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
1976 struct ir3_instruction *lod, *compare, *proj, *sample_index;
1977 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1978 unsigned i, coords, flags, ncomp;
1979 unsigned nsrc0 = 0, nsrc1 = 0;
1980 type_t type;
1981 opc_t opc = 0;
1982
1983 ncomp = nir_dest_num_components(tex->dest);
1984
1985 coord = off = ddx = ddy = NULL;
1986 lod = proj = compare = sample_index = NULL;
1987
1988 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
1989
1990 for (unsigned i = 0; i < tex->num_srcs; i++) {
1991 switch (tex->src[i].src_type) {
1992 case nir_tex_src_coord:
1993 coord = ir3_get_src(ctx, &tex->src[i].src);
1994 break;
1995 case nir_tex_src_bias:
1996 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1997 has_bias = true;
1998 break;
1999 case nir_tex_src_lod:
2000 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
2001 has_lod = true;
2002 break;
2003 case nir_tex_src_comparator: /* shadow comparator */
2004 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
2005 break;
2006 case nir_tex_src_projector:
2007 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
2008 has_proj = true;
2009 break;
2010 case nir_tex_src_offset:
2011 off = ir3_get_src(ctx, &tex->src[i].src);
2012 has_off = true;
2013 break;
2014 case nir_tex_src_ddx:
2015 ddx = ir3_get_src(ctx, &tex->src[i].src);
2016 break;
2017 case nir_tex_src_ddy:
2018 ddy = ir3_get_src(ctx, &tex->src[i].src);
2019 break;
2020 case nir_tex_src_ms_index:
2021 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
2022 break;
2023 case nir_tex_src_texture_offset:
2024 case nir_tex_src_sampler_offset:
2025 /* handled in get_tex_samp_src() */
2026 break;
2027 default:
2028 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
2029 tex->src[i].src_type);
2030 return;
2031 }
2032 }
2033
2034 switch (tex->op) {
2035 case nir_texop_tex_prefetch:
2036 compile_assert(ctx, !has_bias);
2037 compile_assert(ctx, !has_lod);
2038 compile_assert(ctx, !compare);
2039 compile_assert(ctx, !has_proj);
2040 compile_assert(ctx, !has_off);
2041 compile_assert(ctx, !ddx);
2042 compile_assert(ctx, !ddy);
2043 compile_assert(ctx, !sample_index);
2044 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_texture_offset) < 0);
2045 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset) < 0);
2046
2047 if (ctx->so->num_sampler_prefetch < IR3_MAX_SAMPLER_PREFETCH) {
2048 opc = OPC_META_TEX_PREFETCH;
2049 ctx->so->num_sampler_prefetch++;
2050 break;
2051 }
2052 /* fallthru */
2053 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
2054 case nir_texop_txb: opc = OPC_SAMB; break;
2055 case nir_texop_txl: opc = OPC_SAML; break;
2056 case nir_texop_txd: opc = OPC_SAMGQ; break;
2057 case nir_texop_txf: opc = OPC_ISAML; break;
2058 case nir_texop_lod: opc = OPC_GETLOD; break;
2059 case nir_texop_tg4:
2060 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2061 * what blob does, seems gather is broken?), and a3xx did
2062 * not support it (but probably could also emulate).
2063 */
2064 switch (tex->component) {
2065 case 0: opc = OPC_GATHER4R; break;
2066 case 1: opc = OPC_GATHER4G; break;
2067 case 2: opc = OPC_GATHER4B; break;
2068 case 3: opc = OPC_GATHER4A; break;
2069 }
2070 break;
2071 case nir_texop_txf_ms_fb:
2072 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
2073 default:
2074 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
2075 return;
2076 }
2077
2078 tex_info(tex, &flags, &coords);
2079
2080 /*
2081 * lay out the first argument in the proper order:
2082 * - actual coordinates first
2083 * - shadow reference
2084 * - array index
2085 * - projection w
2086 * - starting at offset 4, dpdx.xy, dpdy.xy
2087 *
2088 * bias/lod go into the second arg
2089 */
2090
2091 /* insert tex coords: */
2092 for (i = 0; i < coords; i++)
2093 src0[i] = coord[i];
2094
2095 nsrc0 = i;
2096
2097 /* scale up integer coords for TXF based on the LOD */
2098 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
2099 assert(has_lod);
2100 for (i = 0; i < coords; i++)
2101 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
2102 }
2103
2104 if (coords == 1) {
2105 /* hw doesn't do 1d, so we treat it as 2d with
2106 * height of 1, and patch up the y coord.
2107 */
2108 if (is_isam(opc)) {
2109 src0[nsrc0++] = create_immed(b, 0);
2110 } else {
2111 src0[nsrc0++] = create_immed(b, fui(0.5));
2112 }
2113 }
2114
2115 if (tex->is_shadow && tex->op != nir_texop_lod)
2116 src0[nsrc0++] = compare;
2117
2118 if (tex->is_array && tex->op != nir_texop_lod) {
2119 struct ir3_instruction *idx = coord[coords];
2120
2121 /* the array coord for cube arrays needs 0.5 added to it */
2122 if (ctx->compiler->array_index_add_half && !is_isam(opc))
2123 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
2124
2125 src0[nsrc0++] = idx;
2126 }
2127
2128 if (has_proj) {
2129 src0[nsrc0++] = proj;
2130 flags |= IR3_INSTR_P;
2131 }
2132
2133 /* pad to 4, then ddx/ddy: */
2134 if (tex->op == nir_texop_txd) {
2135 while (nsrc0 < 4)
2136 src0[nsrc0++] = create_immed(b, fui(0.0));
2137 for (i = 0; i < coords; i++)
2138 src0[nsrc0++] = ddx[i];
2139 if (coords < 2)
2140 src0[nsrc0++] = create_immed(b, fui(0.0));
2141 for (i = 0; i < coords; i++)
2142 src0[nsrc0++] = ddy[i];
2143 if (coords < 2)
2144 src0[nsrc0++] = create_immed(b, fui(0.0));
2145 }
2146
2147 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2148 * with scaled x coord according to requested sample:
2149 */
2150 if (opc == OPC_ISAMM) {
2151 if (ctx->compiler->txf_ms_with_isaml) {
2152 /* the samples are laid out in x dimension as
2153 * 0 1 2 3
2154 * x_ms = (x << ms) + sample_index;
2155 */
2156 struct ir3_instruction *ms;
2157 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
2158
2159 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
2160 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
2161
2162 opc = OPC_ISAML;
2163 } else {
2164 src0[nsrc0++] = sample_index;
2165 }
2166 }
2167
2168 /*
2169 * second argument (if applicable):
2170 * - offsets
2171 * - lod
2172 * - bias
2173 */
2174 if (has_off | has_lod | has_bias) {
2175 if (has_off) {
2176 unsigned off_coords = coords;
2177 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2178 off_coords--;
2179 for (i = 0; i < off_coords; i++)
2180 src1[nsrc1++] = off[i];
2181 if (off_coords < 2)
2182 src1[nsrc1++] = create_immed(b, fui(0.0));
2183 flags |= IR3_INSTR_O;
2184 }
2185
2186 if (has_lod | has_bias)
2187 src1[nsrc1++] = lod;
2188 }
2189
2190 type = get_tex_dest_type(tex);
2191
2192 if (opc == OPC_GETLOD)
2193 type = TYPE_S32;
2194
2195 struct ir3_instruction *samp_tex;
2196
2197 if (tex->op == nir_texop_txf_ms_fb) {
2198 /* only expect a single txf_ms_fb per shader: */
2199 compile_assert(ctx, !ctx->so->fb_read);
2200 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
2201
2202 ctx->so->fb_read = true;
2203 samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2204 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2205 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2206 }, 2);
2207
2208 ctx->so->num_samp++;
2209 } else {
2210 samp_tex = get_tex_samp_tex_src(ctx, tex);
2211 }
2212
2213 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
2214 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
2215
2216 if (opc == OPC_META_TEX_PREFETCH) {
2217 int idx = nir_tex_instr_src_index(tex, nir_tex_src_coord);
2218
2219 compile_assert(ctx, tex->src[idx].src.is_ssa);
2220
2221 sam = ir3_META_TEX_PREFETCH(b);
2222 __ssa_dst(sam)->wrmask = MASK(ncomp); /* dst */
2223 sam->prefetch.input_offset =
2224 ir3_nir_coord_offset(tex->src[idx].src.ssa);
2225 sam->prefetch.tex = tex->texture_index;
2226 sam->prefetch.samp = tex->sampler_index;
2227 } else {
2228 sam = ir3_SAM(b, opc, type, MASK(ncomp), flags,
2229 samp_tex, col0, col1);
2230 }
2231
2232 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
2233 assert(opc != OPC_META_TEX_PREFETCH);
2234
2235 /* only need first 3 components: */
2236 sam->regs[0]->wrmask = 0x7;
2237 ir3_split_dest(b, dst, sam, 0, 3);
2238
2239 /* we need to sample the alpha separately with a non-ASTC
2240 * texture state:
2241 */
2242 sam = ir3_SAM(b, opc, type, 0b1000, flags,
2243 samp_tex, col0, col1);
2244
2245 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
2246
2247 /* fixup .w component: */
2248 ir3_split_dest(b, &dst[3], sam, 3, 1);
2249 } else {
2250 /* normal (non-workaround) case: */
2251 ir3_split_dest(b, dst, sam, 0, ncomp);
2252 }
2253
2254 /* GETLOD returns results in 4.8 fixed point */
2255 if (opc == OPC_GETLOD) {
2256 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
2257
2258 compile_assert(ctx, tex->dest_type == nir_type_float);
2259 for (i = 0; i < 2; i++) {
2260 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_S32, TYPE_F32), 0,
2261 factor, 0);
2262 }
2263 }
2264
2265 ir3_put_dst(ctx, &tex->dest);
2266 }
2267
2268 static void
2269 emit_tex_info(struct ir3_context *ctx, nir_tex_instr *tex, unsigned idx)
2270 {
2271 struct ir3_block *b = ctx->block;
2272 struct ir3_instruction **dst, *sam;
2273 type_t dst_type = get_tex_dest_type(tex);
2274
2275 dst = ir3_get_dst(ctx, &tex->dest, 1);
2276
2277 sam = ir3_SAM(b, OPC_GETINFO, dst_type, 1 << idx, 0,
2278 get_tex_samp_tex_src(ctx, tex), NULL, NULL);
2279
2280 /* even though there is only one component, since it ends
2281 * up in .y/.z/.w rather than .x, we need a split_dest()
2282 */
2283 if (idx)
2284 ir3_split_dest(b, dst, sam, 0, idx + 1);
2285
2286 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2287 * the value in TEX_CONST_0 is zero-based.
2288 */
2289 if (ctx->compiler->levels_add_one)
2290 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2291
2292 ir3_put_dst(ctx, &tex->dest);
2293 }
2294
2295 static void
2296 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2297 {
2298 struct ir3_block *b = ctx->block;
2299 struct ir3_instruction **dst, *sam;
2300 struct ir3_instruction *lod;
2301 unsigned flags, coords;
2302 type_t dst_type = get_tex_dest_type(tex);
2303
2304 tex_info(tex, &flags, &coords);
2305
2306 /* Actually we want the number of dimensions, not coordinates. This
2307 * distinction only matters for cubes.
2308 */
2309 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2310 coords = 2;
2311
2312 dst = ir3_get_dst(ctx, &tex->dest, 4);
2313
2314 compile_assert(ctx, tex->num_srcs == 1);
2315 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
2316
2317 lod = ir3_get_src(ctx, &tex->src[0].src)[0];
2318
2319 sam = ir3_SAM(b, OPC_GETSIZE, dst_type, 0b1111, flags,
2320 get_tex_samp_tex_src(ctx, tex), lod, NULL);
2321
2322 ir3_split_dest(b, dst, sam, 0, 4);
2323
2324 /* Array size actually ends up in .w rather than .z. This doesn't
2325 * matter for miplevel 0, but for higher mips the value in z is
2326 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2327 * returned, which means that we have to add 1 to it for arrays.
2328 */
2329 if (tex->is_array) {
2330 if (ctx->compiler->levels_add_one) {
2331 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2332 } else {
2333 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2334 }
2335 }
2336
2337 ir3_put_dst(ctx, &tex->dest);
2338 }
2339
2340 static void
2341 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2342 {
2343 switch (jump->type) {
2344 case nir_jump_break:
2345 case nir_jump_continue:
2346 case nir_jump_return:
2347 /* I *think* we can simply just ignore this, and use the
2348 * successor block link to figure out where we need to
2349 * jump to for break/continue
2350 */
2351 break;
2352 default:
2353 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2354 break;
2355 }
2356 }
2357
2358 static void
2359 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2360 {
2361 switch (instr->type) {
2362 case nir_instr_type_alu:
2363 emit_alu(ctx, nir_instr_as_alu(instr));
2364 break;
2365 case nir_instr_type_deref:
2366 /* ignored, handled as part of the intrinsic they are src to */
2367 break;
2368 case nir_instr_type_intrinsic:
2369 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2370 break;
2371 case nir_instr_type_load_const:
2372 emit_load_const(ctx, nir_instr_as_load_const(instr));
2373 break;
2374 case nir_instr_type_ssa_undef:
2375 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2376 break;
2377 case nir_instr_type_tex: {
2378 nir_tex_instr *tex = nir_instr_as_tex(instr);
2379 /* couple tex instructions get special-cased:
2380 */
2381 switch (tex->op) {
2382 case nir_texop_txs:
2383 emit_tex_txs(ctx, tex);
2384 break;
2385 case nir_texop_query_levels:
2386 emit_tex_info(ctx, tex, 2);
2387 break;
2388 case nir_texop_texture_samples:
2389 emit_tex_info(ctx, tex, 3);
2390 break;
2391 default:
2392 emit_tex(ctx, tex);
2393 break;
2394 }
2395 break;
2396 }
2397 case nir_instr_type_jump:
2398 emit_jump(ctx, nir_instr_as_jump(instr));
2399 break;
2400 case nir_instr_type_phi:
2401 /* we have converted phi webs to regs in NIR by now */
2402 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2403 break;
2404 case nir_instr_type_call:
2405 case nir_instr_type_parallel_copy:
2406 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2407 break;
2408 }
2409 }
2410
2411 static struct ir3_block *
2412 get_block(struct ir3_context *ctx, const nir_block *nblock)
2413 {
2414 struct ir3_block *block;
2415 struct hash_entry *hentry;
2416
2417 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2418 if (hentry)
2419 return hentry->data;
2420
2421 block = ir3_block_create(ctx->ir);
2422 block->nblock = nblock;
2423 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2424
2425 block->predecessors = _mesa_pointer_set_create(block);
2426 set_foreach(nblock->predecessors, sentry) {
2427 _mesa_set_add(block->predecessors, get_block(ctx, sentry->key));
2428 }
2429
2430 return block;
2431 }
2432
2433 static void
2434 emit_block(struct ir3_context *ctx, nir_block *nblock)
2435 {
2436 struct ir3_block *block = get_block(ctx, nblock);
2437
2438 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2439 if (nblock->successors[i]) {
2440 block->successors[i] =
2441 get_block(ctx, nblock->successors[i]);
2442 }
2443 }
2444
2445 ctx->block = block;
2446 list_addtail(&block->node, &ctx->ir->block_list);
2447
2448 /* re-emit addr register in each block if needed: */
2449 for (int i = 0; i < ARRAY_SIZE(ctx->addr_ht); i++) {
2450 _mesa_hash_table_destroy(ctx->addr_ht[i], NULL);
2451 ctx->addr_ht[i] = NULL;
2452 }
2453
2454 nir_foreach_instr(instr, nblock) {
2455 ctx->cur_instr = instr;
2456 emit_instr(ctx, instr);
2457 ctx->cur_instr = NULL;
2458 if (ctx->error)
2459 return;
2460 }
2461 }
2462
2463 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2464
2465 static void
2466 emit_if(struct ir3_context *ctx, nir_if *nif)
2467 {
2468 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2469
2470 ctx->block->condition =
2471 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
2472
2473 emit_cf_list(ctx, &nif->then_list);
2474 emit_cf_list(ctx, &nif->else_list);
2475 }
2476
2477 static void
2478 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2479 {
2480 emit_cf_list(ctx, &nloop->body);
2481 ctx->so->loops++;
2482 }
2483
2484 static void
2485 stack_push(struct ir3_context *ctx)
2486 {
2487 ctx->stack++;
2488 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2489 }
2490
2491 static void
2492 stack_pop(struct ir3_context *ctx)
2493 {
2494 compile_assert(ctx, ctx->stack > 0);
2495 ctx->stack--;
2496 }
2497
2498 static void
2499 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2500 {
2501 foreach_list_typed(nir_cf_node, node, node, list) {
2502 switch (node->type) {
2503 case nir_cf_node_block:
2504 emit_block(ctx, nir_cf_node_as_block(node));
2505 break;
2506 case nir_cf_node_if:
2507 stack_push(ctx);
2508 emit_if(ctx, nir_cf_node_as_if(node));
2509 stack_pop(ctx);
2510 break;
2511 case nir_cf_node_loop:
2512 stack_push(ctx);
2513 emit_loop(ctx, nir_cf_node_as_loop(node));
2514 stack_pop(ctx);
2515 break;
2516 case nir_cf_node_function:
2517 ir3_context_error(ctx, "TODO\n");
2518 break;
2519 }
2520 }
2521 }
2522
2523 /* emit stream-out code. At this point, the current block is the original
2524 * (nir) end block, and nir ensures that all flow control paths terminate
2525 * into the end block. We re-purpose the original end block to generate
2526 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2527 * block holding stream-out write instructions, followed by the new end
2528 * block:
2529 *
2530 * blockOrigEnd {
2531 * p0.x = (vtxcnt < maxvtxcnt)
2532 * // succs: blockStreamOut, blockNewEnd
2533 * }
2534 * blockStreamOut {
2535 * ... stream-out instructions ...
2536 * // succs: blockNewEnd
2537 * }
2538 * blockNewEnd {
2539 * }
2540 */
2541 static void
2542 emit_stream_out(struct ir3_context *ctx)
2543 {
2544 struct ir3 *ir = ctx->ir;
2545 struct ir3_stream_output_info *strmout =
2546 &ctx->so->shader->stream_output;
2547 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2548 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2549 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2550
2551 /* create vtxcnt input in input block at top of shader,
2552 * so that it is seen as live over the entire duration
2553 * of the shader:
2554 */
2555 vtxcnt = create_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, 0x1);
2556 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2557
2558 /* at this point, we are at the original 'end' block,
2559 * re-purpose this block to stream-out condition, then
2560 * append stream-out block and new-end block
2561 */
2562 orig_end_block = ctx->block;
2563
2564 // TODO these blocks need to update predecessors..
2565 // maybe w/ store_global intrinsic, we could do this
2566 // stuff in nir->nir pass
2567
2568 stream_out_block = ir3_block_create(ir);
2569 list_addtail(&stream_out_block->node, &ir->block_list);
2570
2571 new_end_block = ir3_block_create(ir);
2572 list_addtail(&new_end_block->node, &ir->block_list);
2573
2574 orig_end_block->successors[0] = stream_out_block;
2575 orig_end_block->successors[1] = new_end_block;
2576 stream_out_block->successors[0] = new_end_block;
2577
2578 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2579 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2580 cond->regs[0]->num = regid(REG_P0, 0);
2581 cond->regs[0]->flags &= ~IR3_REG_SSA;
2582 cond->cat2.condition = IR3_COND_LT;
2583
2584 /* condition goes on previous block to the conditional,
2585 * since it is used to pick which of the two successor
2586 * paths to take:
2587 */
2588 orig_end_block->condition = cond;
2589
2590 /* switch to stream_out_block to generate the stream-out
2591 * instructions:
2592 */
2593 ctx->block = stream_out_block;
2594
2595 /* Calculate base addresses based on vtxcnt. Instructions
2596 * generated for bases not used in following loop will be
2597 * stripped out in the backend.
2598 */
2599 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2600 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
2601 unsigned stride = strmout->stride[i];
2602 struct ir3_instruction *base, *off;
2603
2604 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
2605
2606 /* 24-bit should be enough: */
2607 off = ir3_MUL_U24(ctx->block, vtxcnt, 0,
2608 create_immed(ctx->block, stride * 4), 0);
2609
2610 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2611 }
2612
2613 /* Generate the per-output store instructions: */
2614 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2615 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2616 unsigned c = j + strmout->output[i].start_component;
2617 struct ir3_instruction *base, *out, *stg;
2618
2619 base = bases[strmout->output[i].output_buffer];
2620 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2621
2622 stg = ir3_STG(ctx->block, base, 0, out, 0,
2623 create_immed(ctx->block, 1), 0);
2624 stg->cat6.type = TYPE_U32;
2625 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2626
2627 array_insert(ctx->block, ctx->block->keeps, stg);
2628 }
2629 }
2630
2631 /* and finally switch to the new_end_block: */
2632 ctx->block = new_end_block;
2633 }
2634
2635 static void
2636 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2637 {
2638 nir_metadata_require(impl, nir_metadata_block_index);
2639
2640 compile_assert(ctx, ctx->stack == 0);
2641
2642 emit_cf_list(ctx, &impl->body);
2643 emit_block(ctx, impl->end_block);
2644
2645 compile_assert(ctx, ctx->stack == 0);
2646
2647 /* at this point, we should have a single empty block,
2648 * into which we emit the 'end' instruction.
2649 */
2650 compile_assert(ctx, list_is_empty(&ctx->block->instr_list));
2651
2652 /* If stream-out (aka transform-feedback) enabled, emit the
2653 * stream-out instructions, followed by a new empty block (into
2654 * which the 'end' instruction lands).
2655 *
2656 * NOTE: it is done in this order, rather than inserting before
2657 * we emit end_block, because NIR guarantees that all blocks
2658 * flow into end_block, and that end_block has no successors.
2659 * So by re-purposing end_block as the first block of stream-
2660 * out, we guarantee that all exit paths flow into the stream-
2661 * out instructions.
2662 */
2663 if ((ctx->compiler->gpu_id < 500) &&
2664 (ctx->so->shader->stream_output.num_outputs > 0) &&
2665 !ctx->so->binning_pass) {
2666 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2667 emit_stream_out(ctx);
2668 }
2669
2670 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2671 * NOP and has an epilogue that writes the VS outputs to local storage, to
2672 * be read by the HS. Then it resets execution mask (chmask) and chains
2673 * to the next shader (chsh).
2674 */
2675 if ((ctx->so->type == MESA_SHADER_VERTEX &&
2676 (ctx->so->key.has_gs || ctx->so->key.tessellation)) ||
2677 (ctx->so->type == MESA_SHADER_TESS_EVAL && ctx->so->key.has_gs)) {
2678 struct ir3_instruction *chmask =
2679 ir3_CHMASK(ctx->block);
2680 chmask->barrier_class = IR3_BARRIER_EVERYTHING;
2681 chmask->barrier_conflict = IR3_BARRIER_EVERYTHING;
2682
2683 struct ir3_instruction *chsh =
2684 ir3_CHSH(ctx->block);
2685 chsh->barrier_class = IR3_BARRIER_EVERYTHING;
2686 chsh->barrier_conflict = IR3_BARRIER_EVERYTHING;
2687 } else {
2688 ir3_END(ctx->block);
2689 }
2690 }
2691
2692 static void
2693 setup_input(struct ir3_context *ctx, nir_variable *in)
2694 {
2695 struct ir3_shader_variant *so = ctx->so;
2696 unsigned ncomp = glsl_get_components(in->type);
2697 unsigned n = in->data.driver_location;
2698 unsigned frac = in->data.location_frac;
2699 unsigned slot = in->data.location;
2700
2701 /* Inputs are loaded using ldlw or ldg for these stages. */
2702 if (ctx->so->type == MESA_SHADER_TESS_CTRL ||
2703 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2704 ctx->so->type == MESA_SHADER_GEOMETRY)
2705 return;
2706
2707 /* skip unread inputs, we could end up with (for example), unsplit
2708 * matrix/etc inputs in the case they are not read, so just silently
2709 * skip these.
2710 */
2711 if (ncomp > 4)
2712 return;
2713
2714 so->inputs[n].slot = slot;
2715 so->inputs[n].compmask |= (1 << (ncomp + frac)) - 1;
2716 so->inputs_count = MAX2(so->inputs_count, n + 1);
2717 so->inputs[n].interpolate = in->data.interpolation;
2718
2719 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2720
2721 /* if any varyings have 'sample' qualifer, that triggers us
2722 * to run in per-sample mode:
2723 */
2724 so->per_samp |= in->data.sample;
2725
2726 for (int i = 0; i < ncomp; i++) {
2727 struct ir3_instruction *instr = NULL;
2728 unsigned idx = (n * 4) + i + frac;
2729
2730 if (slot == VARYING_SLOT_POS) {
2731 ir3_context_error(ctx, "fragcoord should be a sysval!\n");
2732 } else if (slot == VARYING_SLOT_PNTC) {
2733 /* see for example st_nir_fixup_varying_slots().. this is
2734 * maybe a bit mesa/st specific. But we need things to line
2735 * up for this in fdN_program:
2736 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2737 * if (emit->sprite_coord_enable & texmask) {
2738 * ...
2739 * }
2740 */
2741 so->inputs[n].slot = VARYING_SLOT_VAR8;
2742 so->inputs[n].bary = true;
2743 instr = create_frag_input(ctx, false, idx);
2744 } else {
2745 /* detect the special case for front/back colors where
2746 * we need to do flat vs smooth shading depending on
2747 * rast state:
2748 */
2749 if (in->data.interpolation == INTERP_MODE_NONE) {
2750 switch (slot) {
2751 case VARYING_SLOT_COL0:
2752 case VARYING_SLOT_COL1:
2753 case VARYING_SLOT_BFC0:
2754 case VARYING_SLOT_BFC1:
2755 so->inputs[n].rasterflat = true;
2756 break;
2757 default:
2758 break;
2759 }
2760 }
2761
2762 if (ctx->compiler->flat_bypass) {
2763 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2764 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2765 so->inputs[n].use_ldlv = true;
2766 }
2767
2768 so->inputs[n].bary = true;
2769
2770 instr = create_frag_input(ctx, so->inputs[n].use_ldlv, idx);
2771 }
2772
2773 compile_assert(ctx, idx < ctx->ninputs);
2774
2775 ctx->inputs[idx] = instr;
2776 }
2777 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2778 struct ir3_instruction *input = NULL, *in;
2779 struct ir3_instruction *components[4];
2780 unsigned mask = (1 << (ncomp + frac)) - 1;
2781
2782 foreach_input(in, ctx->ir) {
2783 if (in->input.inidx == n) {
2784 input = in;
2785 break;
2786 }
2787 }
2788
2789 if (!input) {
2790 input = create_input(ctx, mask);
2791 input->input.inidx = n;
2792 } else {
2793 input->regs[0]->wrmask |= mask;
2794 }
2795
2796 ir3_split_dest(ctx->block, components, input, frac, ncomp);
2797
2798 for (int i = 0; i < ncomp; i++) {
2799 unsigned idx = (n * 4) + i + frac;
2800 compile_assert(ctx, idx < ctx->ninputs);
2801 ctx->inputs[idx] = components[i];
2802 }
2803 } else {
2804 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2805 }
2806
2807 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
2808 so->total_in += ncomp;
2809 }
2810 }
2811
2812 /* Initially we assign non-packed inloc's for varyings, as we don't really
2813 * know up-front which components will be unused. After all the compilation
2814 * stages we scan the shader to see which components are actually used, and
2815 * re-pack the inlocs to eliminate unneeded varyings.
2816 */
2817 static void
2818 pack_inlocs(struct ir3_context *ctx)
2819 {
2820 struct ir3_shader_variant *so = ctx->so;
2821 uint8_t used_components[so->inputs_count];
2822
2823 memset(used_components, 0, sizeof(used_components));
2824
2825 /*
2826 * First Step: scan shader to find which bary.f/ldlv remain:
2827 */
2828
2829 foreach_block (block, &ctx->ir->block_list) {
2830 foreach_instr (instr, &block->instr_list) {
2831 if (is_input(instr)) {
2832 unsigned inloc = instr->regs[1]->iim_val;
2833 unsigned i = inloc / 4;
2834 unsigned j = inloc % 4;
2835
2836 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
2837 compile_assert(ctx, i < so->inputs_count);
2838
2839 used_components[i] |= 1 << j;
2840 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
2841 for (int n = 0; n < 2; n++) {
2842 unsigned inloc = instr->prefetch.input_offset + n;
2843 unsigned i = inloc / 4;
2844 unsigned j = inloc % 4;
2845
2846 compile_assert(ctx, i < so->inputs_count);
2847
2848 used_components[i] |= 1 << j;
2849 }
2850 }
2851 }
2852 }
2853
2854 /*
2855 * Second Step: reassign varying inloc/slots:
2856 */
2857
2858 unsigned actual_in = 0;
2859 unsigned inloc = 0;
2860
2861 for (unsigned i = 0; i < so->inputs_count; i++) {
2862 unsigned compmask = 0, maxcomp = 0;
2863
2864 so->inputs[i].inloc = inloc;
2865 so->inputs[i].bary = false;
2866
2867 for (unsigned j = 0; j < 4; j++) {
2868 if (!(used_components[i] & (1 << j)))
2869 continue;
2870
2871 compmask |= (1 << j);
2872 actual_in++;
2873 maxcomp = j + 1;
2874
2875 /* at this point, since used_components[i] mask is only
2876 * considering varyings (ie. not sysvals) we know this
2877 * is a varying:
2878 */
2879 so->inputs[i].bary = true;
2880 }
2881
2882 if (so->inputs[i].bary) {
2883 so->varying_in++;
2884 so->inputs[i].compmask = (1 << maxcomp) - 1;
2885 inloc += maxcomp;
2886 }
2887 }
2888
2889 /*
2890 * Third Step: reassign packed inloc's:
2891 */
2892
2893 foreach_block (block, &ctx->ir->block_list) {
2894 foreach_instr (instr, &block->instr_list) {
2895 if (is_input(instr)) {
2896 unsigned inloc = instr->regs[1]->iim_val;
2897 unsigned i = inloc / 4;
2898 unsigned j = inloc % 4;
2899
2900 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
2901 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
2902 unsigned i = instr->prefetch.input_offset / 4;
2903 unsigned j = instr->prefetch.input_offset % 4;
2904 instr->prefetch.input_offset = so->inputs[i].inloc + j;
2905 }
2906 }
2907 }
2908 }
2909
2910 static void
2911 setup_output(struct ir3_context *ctx, nir_variable *out)
2912 {
2913 struct ir3_shader_variant *so = ctx->so;
2914 unsigned ncomp = glsl_get_components(out->type);
2915 unsigned n = out->data.driver_location;
2916 unsigned frac = out->data.location_frac;
2917 unsigned slot = out->data.location;
2918 unsigned comp = 0;
2919
2920 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2921 switch (slot) {
2922 case FRAG_RESULT_DEPTH:
2923 comp = 2; /* tgsi will write to .z component */
2924 so->writes_pos = true;
2925 break;
2926 case FRAG_RESULT_COLOR:
2927 so->color0_mrt = 1;
2928 break;
2929 case FRAG_RESULT_SAMPLE_MASK:
2930 so->writes_smask = true;
2931 break;
2932 default:
2933 if (slot >= FRAG_RESULT_DATA0)
2934 break;
2935 ir3_context_error(ctx, "unknown FS output name: %s\n",
2936 gl_frag_result_name(slot));
2937 }
2938 } else if (ctx->so->type == MESA_SHADER_VERTEX ||
2939 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2940 ctx->so->type == MESA_SHADER_GEOMETRY) {
2941 switch (slot) {
2942 case VARYING_SLOT_POS:
2943 so->writes_pos = true;
2944 break;
2945 case VARYING_SLOT_PSIZ:
2946 so->writes_psize = true;
2947 break;
2948 case VARYING_SLOT_PRIMITIVE_ID:
2949 case VARYING_SLOT_LAYER:
2950 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
2951 debug_assert(ctx->so->type == MESA_SHADER_GEOMETRY);
2952 /* fall through */
2953 case VARYING_SLOT_COL0:
2954 case VARYING_SLOT_COL1:
2955 case VARYING_SLOT_BFC0:
2956 case VARYING_SLOT_BFC1:
2957 case VARYING_SLOT_FOGC:
2958 case VARYING_SLOT_CLIP_DIST0:
2959 case VARYING_SLOT_CLIP_DIST1:
2960 case VARYING_SLOT_CLIP_VERTEX:
2961 break;
2962 default:
2963 if (slot >= VARYING_SLOT_VAR0)
2964 break;
2965 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
2966 break;
2967 ir3_context_error(ctx, "unknown %s shader output name: %s\n",
2968 _mesa_shader_stage_to_string(ctx->so->type),
2969 gl_varying_slot_name(slot));
2970 }
2971 } else if (ctx->so->type == MESA_SHADER_TESS_CTRL) {
2972 /* output lowered to buffer writes. */
2973 return;
2974 } else {
2975 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2976 }
2977
2978 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
2979
2980 so->outputs[n].slot = slot;
2981 so->outputs[n].regid = regid(n, comp);
2982 so->outputs_count = MAX2(so->outputs_count, n + 1);
2983
2984 for (int i = 0; i < ncomp; i++) {
2985 unsigned idx = (n * 4) + i + frac;
2986 compile_assert(ctx, idx < ctx->noutputs);
2987 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
2988 }
2989
2990 /* if varying packing doesn't happen, we could end up in a situation
2991 * with "holes" in the output, and since the per-generation code that
2992 * sets up varying linkage registers doesn't expect to have more than
2993 * one varying per vec4 slot, pad the holes.
2994 *
2995 * Note that this should probably generate a performance warning of
2996 * some sort.
2997 */
2998 for (int i = 0; i < frac; i++) {
2999 unsigned idx = (n * 4) + i;
3000 if (!ctx->outputs[idx]) {
3001 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
3002 }
3003 }
3004 }
3005
3006 static int
3007 max_drvloc(struct exec_list *vars)
3008 {
3009 int drvloc = -1;
3010 nir_foreach_variable(var, vars) {
3011 drvloc = MAX2(drvloc, (int)var->data.driver_location);
3012 }
3013 return drvloc;
3014 }
3015
3016 static void
3017 emit_instructions(struct ir3_context *ctx)
3018 {
3019 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
3020
3021 ctx->ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4;
3022 ctx->noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4;
3023
3024 ctx->inputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->ninputs);
3025 ctx->outputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->noutputs);
3026
3027 ctx->ir = ir3_create(ctx->compiler, ctx->so->type);
3028
3029 /* Create inputs in first block: */
3030 ctx->block = get_block(ctx, nir_start_block(fxn));
3031 ctx->in_block = ctx->block;
3032 list_addtail(&ctx->block->node, &ctx->ir->block_list);
3033
3034 /* for fragment shader, the vcoord input register is used as the
3035 * base for bary.f varying fetch instrs:
3036 *
3037 * TODO defer creating ctx->ij_pixel and corresponding sysvals
3038 * until emit_intrinsic when we know they are actually needed.
3039 * For now, we defer creating ctx->ij_centroid, etc, since we
3040 * only need ij_pixel for "old style" varying inputs (ie.
3041 * tgsi_to_nir)
3042 */
3043 struct ir3_instruction *vcoord = NULL;
3044 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3045 struct ir3_instruction *xy[2];
3046
3047 vcoord = create_input(ctx, 0x3);
3048 ir3_split_dest(ctx->block, xy, vcoord, 0, 2);
3049
3050 ctx->ij_pixel = ir3_create_collect(ctx, xy, 2);
3051 }
3052
3053 /* Setup inputs: */
3054 nir_foreach_variable(var, &ctx->s->inputs) {
3055 setup_input(ctx, var);
3056 }
3057
3058 /* Defer add_sysval_input() stuff until after setup_inputs(),
3059 * because sysvals need to be appended after varyings:
3060 */
3061 if (vcoord) {
3062 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL,
3063 0x3, vcoord);
3064 }
3065
3066
3067 /* Tesselation shaders always need primitive ID for indexing the
3068 * BO. Geometry shaders don't always need it but when they do it has be
3069 * delivered and unclobbered in the VS. To make things easy, we always
3070 * make room for it in VS/DS.
3071 */
3072 bool has_tess = ctx->so->key.tessellation != IR3_TESS_NONE;
3073 bool has_gs = ctx->so->key.has_gs;
3074 switch (ctx->so->type) {
3075 case MESA_SHADER_VERTEX:
3076 if (has_tess) {
3077 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3078 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3079 } else if (has_gs) {
3080 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3081 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3082 }
3083 break;
3084 case MESA_SHADER_TESS_CTRL:
3085 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3086 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3087 break;
3088 case MESA_SHADER_TESS_EVAL:
3089 if (has_gs)
3090 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3091 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3092 break;
3093 case MESA_SHADER_GEOMETRY:
3094 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3095 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3096 break;
3097 default:
3098 break;
3099 }
3100
3101 /* Setup outputs: */
3102 nir_foreach_variable(var, &ctx->s->outputs) {
3103 setup_output(ctx, var);
3104 }
3105
3106 /* Find # of samplers: */
3107 nir_foreach_variable(var, &ctx->s->uniforms) {
3108 ctx->so->num_samp += glsl_type_get_sampler_count(var->type);
3109 /* just assume that we'll be reading from images.. if it
3110 * is write-only we don't have to count it, but not sure
3111 * if there is a good way to know?
3112 */
3113 ctx->so->num_samp += glsl_type_get_image_count(var->type);
3114 }
3115
3116 /* NOTE: need to do something more clever when we support >1 fxn */
3117 nir_foreach_register(reg, &fxn->registers) {
3118 ir3_declare_array(ctx, reg);
3119 }
3120 /* And emit the body: */
3121 ctx->impl = fxn;
3122 emit_function(ctx, fxn);
3123 }
3124
3125 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3126 * need to assign the tex state indexes for these after we know the
3127 * max tex index.
3128 */
3129 static void
3130 fixup_astc_srgb(struct ir3_context *ctx)
3131 {
3132 struct ir3_shader_variant *so = ctx->so;
3133 /* indexed by original tex idx, value is newly assigned alpha sampler
3134 * state tex idx. Zero is invalid since there is at least one sampler
3135 * if we get here.
3136 */
3137 unsigned alt_tex_state[16] = {0};
3138 unsigned tex_idx = ctx->max_texture_index + 1;
3139 unsigned idx = 0;
3140
3141 so->astc_srgb.base = tex_idx;
3142
3143 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
3144 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
3145
3146 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
3147
3148 if (alt_tex_state[sam->cat5.tex] == 0) {
3149 /* assign new alternate/alpha tex state slot: */
3150 alt_tex_state[sam->cat5.tex] = tex_idx++;
3151 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
3152 so->astc_srgb.count++;
3153 }
3154
3155 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
3156 }
3157 }
3158
3159 static void
3160 fixup_binning_pass(struct ir3_context *ctx)
3161 {
3162 struct ir3_shader_variant *so = ctx->so;
3163 struct ir3 *ir = ctx->ir;
3164 unsigned i, j;
3165
3166 /* first pass, remove unused outputs from the IR level outputs: */
3167 for (i = 0, j = 0; i < ir->outputs_count; i++) {
3168 struct ir3_instruction *out = ir->outputs[i];
3169 assert(out->opc == OPC_META_COLLECT);
3170 unsigned outidx = out->collect.outidx;
3171 unsigned slot = so->outputs[outidx].slot;
3172
3173 /* throw away everything but first position/psize */
3174 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3175 ir->outputs[j] = ir->outputs[i];
3176 j++;
3177 }
3178 }
3179 ir->outputs_count = j;
3180
3181 /* second pass, cleanup the unused slots in ir3_shader_variant::outputs
3182 * table:
3183 */
3184 for (i = 0, j = 0; i < so->outputs_count; i++) {
3185 unsigned slot = so->outputs[i].slot;
3186
3187 /* throw away everything but first position/psize */
3188 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3189 so->outputs[j] = so->outputs[i];
3190
3191 /* fixup outidx to point to new output table entry: */
3192 struct ir3_instruction *out;
3193 foreach_output(out, ir) {
3194 if (out->collect.outidx == i) {
3195 out->collect.outidx = j;
3196 break;
3197 }
3198 }
3199
3200 j++;
3201 }
3202 }
3203 so->outputs_count = j;
3204 }
3205
3206 static void
3207 collect_tex_prefetches(struct ir3_context *ctx, struct ir3 *ir)
3208 {
3209 unsigned idx = 0;
3210
3211 /* Collect sampling instructions eligible for pre-dispatch. */
3212 foreach_block (block, &ir->block_list) {
3213 foreach_instr_safe (instr, &block->instr_list) {
3214 if (instr->opc == OPC_META_TEX_PREFETCH) {
3215 assert(idx < ARRAY_SIZE(ctx->so->sampler_prefetch));
3216 struct ir3_sampler_prefetch *fetch =
3217 &ctx->so->sampler_prefetch[idx];
3218 idx++;
3219
3220 fetch->cmd = IR3_SAMPLER_PREFETCH_CMD;
3221 fetch->wrmask = instr->regs[0]->wrmask;
3222 fetch->tex_id = instr->prefetch.tex;
3223 fetch->samp_id = instr->prefetch.samp;
3224 fetch->dst = instr->regs[0]->num;
3225 fetch->src = instr->prefetch.input_offset;
3226
3227 ctx->so->total_in =
3228 MAX2(ctx->so->total_in, instr->prefetch.input_offset + 2);
3229
3230 /* Disable half precision until supported. */
3231 fetch->half_precision = !!(instr->regs[0]->flags & IR3_REG_HALF);
3232
3233 /* Remove the prefetch placeholder instruction: */
3234 list_delinit(&instr->node);
3235 }
3236 }
3237 }
3238 }
3239
3240 int
3241 ir3_compile_shader_nir(struct ir3_compiler *compiler,
3242 struct ir3_shader_variant *so)
3243 {
3244 struct ir3_context *ctx;
3245 struct ir3 *ir;
3246 int ret = 0, max_bary;
3247
3248 assert(!so->ir);
3249
3250 ctx = ir3_context_init(compiler, so);
3251 if (!ctx) {
3252 DBG("INIT failed!");
3253 ret = -1;
3254 goto out;
3255 }
3256
3257 emit_instructions(ctx);
3258
3259 if (ctx->error) {
3260 DBG("EMIT failed!");
3261 ret = -1;
3262 goto out;
3263 }
3264
3265 ir = so->ir = ctx->ir;
3266
3267 assert((ctx->noutputs % 4) == 0);
3268
3269 /* Setup IR level outputs, which are "collects" that gather
3270 * the scalar components of outputs.
3271 */
3272 for (unsigned i = 0; i < ctx->noutputs; i += 4) {
3273 unsigned ncomp = 0;
3274 /* figure out the # of components written:
3275 *
3276 * TODO do we need to handle holes, ie. if .x and .z
3277 * components written, but .y component not written?
3278 */
3279 for (unsigned j = 0; j < 4; j++) {
3280 if (!ctx->outputs[i + j])
3281 break;
3282 ncomp++;
3283 }
3284
3285 /* Note that in some stages, like TCS, store_output is
3286 * lowered to memory writes, so no components of the
3287 * are "written" from the PoV of traditional store-
3288 * output instructions:
3289 */
3290 if (!ncomp)
3291 continue;
3292
3293 struct ir3_instruction *out =
3294 ir3_create_collect(ctx, &ctx->outputs[i], ncomp);
3295
3296 int outidx = i / 4;
3297 assert(outidx < so->outputs_count);
3298
3299 /* stash index into so->outputs[] so we can map the
3300 * output back to slot/etc later:
3301 */
3302 out->collect.outidx = outidx;
3303
3304 array_insert(ir, ir->outputs, out);
3305 }
3306
3307 /* Set up the gs header as an output for the vertex shader so it won't
3308 * clobber it for the tess ctrl shader.
3309 *
3310 * TODO this could probably be done more cleanly in a nir pass.
3311 */
3312 if (ctx->so->type == MESA_SHADER_VERTEX ||
3313 (ctx->so->key.has_gs && ctx->so->type == MESA_SHADER_TESS_EVAL)) {
3314 if (ctx->primitive_id) {
3315 unsigned n = so->outputs_count++;
3316 so->outputs[n].slot = VARYING_SLOT_PRIMITIVE_ID;
3317
3318 struct ir3_instruction *out =
3319 ir3_create_collect(ctx, &ctx->primitive_id, 1);
3320 out->collect.outidx = n;
3321 array_insert(ir, ir->outputs, out);
3322 }
3323
3324 if (ctx->gs_header) {
3325 unsigned n = so->outputs_count++;
3326 so->outputs[n].slot = VARYING_SLOT_GS_HEADER_IR3;
3327 struct ir3_instruction *out =
3328 ir3_create_collect(ctx, &ctx->gs_header, 1);
3329 out->collect.outidx = n;
3330 array_insert(ir, ir->outputs, out);
3331 }
3332
3333 if (ctx->tcs_header) {
3334 unsigned n = so->outputs_count++;
3335 so->outputs[n].slot = VARYING_SLOT_TCS_HEADER_IR3;
3336 struct ir3_instruction *out =
3337 ir3_create_collect(ctx, &ctx->tcs_header, 1);
3338 out->collect.outidx = n;
3339 array_insert(ir, ir->outputs, out);
3340 }
3341 }
3342
3343 /* at this point, for binning pass, throw away unneeded outputs: */
3344 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
3345 fixup_binning_pass(ctx);
3346
3347 ir3_debug_print(ir, "BEFORE CP");
3348
3349 ir3_cp(ir, so);
3350
3351 /* at this point, for binning pass, throw away unneeded outputs:
3352 * Note that for a6xx and later, we do this after ir3_cp to ensure
3353 * that the uniform/constant layout for BS and VS matches, so that
3354 * we can re-use same VS_CONST state group.
3355 */
3356 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
3357 fixup_binning_pass(ctx);
3358
3359 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3360 * need to make sure not to remove any inputs that are used by
3361 * the nonbinning VS.
3362 */
3363 if (ctx->compiler->gpu_id >= 600 && so->binning_pass &&
3364 so->type == MESA_SHADER_VERTEX) {
3365 for (int i = 0; i < ctx->ninputs; i++) {
3366 struct ir3_instruction *in = ctx->inputs[i];
3367
3368 if (!in)
3369 continue;
3370
3371 unsigned n = i / 4;
3372 unsigned c = i % 4;
3373
3374 debug_assert(n < so->nonbinning->inputs_count);
3375
3376 if (so->nonbinning->inputs[n].sysval)
3377 continue;
3378
3379 /* be sure to keep inputs, even if only used in VS */
3380 if (so->nonbinning->inputs[n].compmask & (1 << c))
3381 array_insert(in->block, in->block->keeps, in);
3382 }
3383 }
3384
3385 ir3_debug_print(ir, "BEFORE GROUPING");
3386
3387 ir3_sched_add_deps(ir);
3388
3389 /* Group left/right neighbors, inserting mov's where needed to
3390 * solve conflicts:
3391 */
3392 ir3_group(ir);
3393
3394 ir3_debug_print(ir, "AFTER GROUPING");
3395
3396 ir3_depth(ir, so);
3397
3398 ir3_debug_print(ir, "AFTER DEPTH");
3399
3400 /* do Sethi–Ullman numbering before scheduling: */
3401 ir3_sun(ir);
3402
3403 ret = ir3_sched(ir);
3404 if (ret) {
3405 DBG("SCHED failed!");
3406 goto out;
3407 }
3408
3409 ir3_debug_print(ir, "AFTER SCHED");
3410
3411 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3412 * with draw pass VS, so binning and draw pass can both use the
3413 * same VBO state.
3414 *
3415 * Note that VS inputs are expected to be full precision.
3416 */
3417 bool pre_assign_inputs = (ir->compiler->gpu_id >= 600) &&
3418 (ir->type == MESA_SHADER_VERTEX) &&
3419 so->binning_pass;
3420
3421 if (pre_assign_inputs) {
3422 for (unsigned i = 0; i < ctx->ninputs; i++) {
3423 struct ir3_instruction *instr = ctx->inputs[i];
3424
3425 if (!instr)
3426 continue;
3427
3428 unsigned n = i / 4;
3429 unsigned c = i % 4;
3430 unsigned regid = so->nonbinning->inputs[n].regid + c;
3431
3432 instr->regs[0]->num = regid;
3433 }
3434
3435 ret = ir3_ra(so, ctx->inputs, ctx->ninputs);
3436 } else if (ctx->tcs_header) {
3437 /* We need to have these values in the same registers between VS and TCS
3438 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3439 */
3440
3441 ctx->tcs_header->regs[0]->num = regid(0, 0);
3442 ctx->primitive_id->regs[0]->num = regid(0, 1);
3443 struct ir3_instruction *precolor[] = { ctx->tcs_header, ctx->primitive_id };
3444 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3445 } else if (ctx->gs_header) {
3446 /* We need to have these values in the same registers between producer
3447 * (VS or DS) and GS since the producer chains to GS and doesn't get
3448 * the sysvals redelivered.
3449 */
3450
3451 ctx->gs_header->regs[0]->num = regid(0, 0);
3452 ctx->primitive_id->regs[0]->num = regid(0, 1);
3453 struct ir3_instruction *precolor[] = { ctx->gs_header, ctx->primitive_id };
3454 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3455 } else if (so->num_sampler_prefetch) {
3456 assert(so->type == MESA_SHADER_FRAGMENT);
3457 struct ir3_instruction *instr, *precolor[2];
3458 int idx = 0;
3459
3460 foreach_input(instr, ir) {
3461 if (instr->input.sysval != SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL)
3462 continue;
3463
3464 assert(idx < ARRAY_SIZE(precolor));
3465
3466 precolor[idx] = instr;
3467 instr->regs[0]->num = idx;
3468
3469 idx++;
3470 }
3471 ret = ir3_ra(so, precolor, idx);
3472 } else {
3473 ret = ir3_ra(so, NULL, 0);
3474 }
3475
3476 if (ret) {
3477 DBG("RA failed!");
3478 goto out;
3479 }
3480
3481 ir3_debug_print(ir, "AFTER RA");
3482
3483 if (compiler->gpu_id >= 600) {
3484 if (ir3_a6xx_fixup_atomic_dests(ir, so)) {
3485 ir3_debug_print(ir, "AFTER ATOMIC FIXUP");
3486 }
3487 }
3488
3489 if (so->type == MESA_SHADER_FRAGMENT)
3490 pack_inlocs(ctx);
3491
3492 /*
3493 * Fixup inputs/outputs to point to the actual registers assigned:
3494 *
3495 * 1) initialize to r63.x (invalid/unused)
3496 * 2) iterate IR level inputs/outputs and update the variants
3497 * inputs/outputs table based on the assigned registers for
3498 * the remaining inputs/outputs.
3499 */
3500
3501 for (unsigned i = 0; i < so->inputs_count; i++)
3502 so->inputs[i].regid = INVALID_REG;
3503 for (unsigned i = 0; i < so->outputs_count; i++)
3504 so->outputs[i].regid = INVALID_REG;
3505
3506 struct ir3_instruction *out;
3507 foreach_output(out, ir) {
3508 assert(out->opc == OPC_META_COLLECT);
3509 unsigned outidx = out->collect.outidx;
3510
3511 so->outputs[outidx].regid = out->regs[0]->num;
3512 so->outputs[outidx].half = !!(out->regs[0]->flags & IR3_REG_HALF);
3513 }
3514
3515 struct ir3_instruction *in;
3516 foreach_input(in, ir) {
3517 assert(in->opc == OPC_META_INPUT);
3518 unsigned inidx = in->input.inidx;
3519
3520 if (pre_assign_inputs && !so->inputs[inidx].sysval) {
3521 if (VALIDREG(so->nonbinning->inputs[inidx].regid)) {
3522 compile_assert(ctx, in->regs[0]->num ==
3523 so->nonbinning->inputs[inidx].regid);
3524 compile_assert(ctx, !!(in->regs[0]->flags & IR3_REG_HALF) ==
3525 so->nonbinning->inputs[inidx].half);
3526 }
3527 so->inputs[inidx].regid = so->nonbinning->inputs[inidx].regid;
3528 so->inputs[inidx].half = so->nonbinning->inputs[inidx].half;
3529 } else {
3530 so->inputs[inidx].regid = in->regs[0]->num;
3531 so->inputs[inidx].half = !!(in->regs[0]->flags & IR3_REG_HALF);
3532 }
3533 }
3534
3535 if (ctx->astc_srgb)
3536 fixup_astc_srgb(ctx);
3537
3538 /* We need to do legalize after (for frag shader's) the "bary.f"
3539 * offsets (inloc) have been assigned.
3540 */
3541 ir3_legalize(ir, so, &max_bary);
3542
3543 ir3_debug_print(ir, "AFTER LEGALIZE");
3544
3545 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3546 * know what we might have to wait on when coming in from VS chsh.
3547 */
3548 if (so->type == MESA_SHADER_TESS_CTRL ||
3549 so->type == MESA_SHADER_GEOMETRY ) {
3550 foreach_block (block, &ir->block_list) {
3551 foreach_instr (instr, &block->instr_list) {
3552 instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
3553 break;
3554 }
3555 }
3556 }
3557
3558 so->branchstack = ctx->max_stack;
3559
3560 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3561 if (so->type == MESA_SHADER_FRAGMENT)
3562 so->total_in = max_bary + 1;
3563
3564 so->max_sun = ir->max_sun;
3565
3566 /* Collect sampling instructions eligible for pre-dispatch. */
3567 collect_tex_prefetches(ctx, ir);
3568
3569 out:
3570 if (ret) {
3571 if (so->ir)
3572 ir3_destroy(so->ir);
3573 so->ir = NULL;
3574 }
3575 ir3_context_free(ctx);
3576
3577 return ret;
3578 }