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ir3: Fix txs with bindless
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 __ssa_dst(mov);
55 src = __ssa_src(mov, collect, IR3_REG_RELATIV);
56 src->size = arrsz;
57 src->array.offset = n;
58
59 ir3_instr_set_address(mov, address);
60
61 return mov;
62 }
63
64 static struct ir3_instruction *
65 create_input(struct ir3_context *ctx, unsigned compmask)
66 {
67 struct ir3_instruction *in;
68
69 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
70 in->input.sysval = ~0;
71 __ssa_dst(in)->wrmask = compmask;
72
73 array_insert(ctx->ir, ctx->ir->inputs, in);
74
75 return in;
76 }
77
78 static struct ir3_instruction *
79 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
80 {
81 struct ir3_block *block = ctx->block;
82 struct ir3_instruction *instr;
83 /* packed inloc is fixed up later: */
84 struct ir3_instruction *inloc = create_immed(block, n);
85
86 if (use_ldlv) {
87 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
88 instr->cat6.type = TYPE_U32;
89 instr->cat6.iim_val = 1;
90 } else {
91 instr = ir3_BARY_F(block, inloc, 0, ctx->ij_pixel, 0);
92 instr->regs[2]->wrmask = 0x3;
93 }
94
95 return instr;
96 }
97
98 static struct ir3_instruction *
99 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
100 {
101 /* first four vec4 sysval's reserved for UBOs: */
102 /* NOTE: dp is in scalar, but there can be >4 dp components: */
103 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
104 unsigned n = const_state->offsets.driver_param;
105 unsigned r = regid(n + dp / 4, dp % 4);
106 return create_uniform(ctx->block, r);
107 }
108
109 /*
110 * Adreno uses uint rather than having dedicated bool type,
111 * which (potentially) requires some conversion, in particular
112 * when using output of an bool instr to int input, or visa
113 * versa.
114 *
115 * | Adreno | NIR |
116 * -------+---------+-------+-
117 * true | 1 | ~0 |
118 * false | 0 | 0 |
119 *
120 * To convert from an adreno bool (uint) to nir, use:
121 *
122 * absneg.s dst, (neg)src
123 *
124 * To convert back in the other direction:
125 *
126 * absneg.s dst, (abs)arc
127 *
128 * The CP step can clean up the absneg.s that cancel each other
129 * out, and with a slight bit of extra cleverness (to recognize
130 * the instructions which produce either a 0 or 1) can eliminate
131 * the absneg.s's completely when an instruction that wants
132 * 0/1 consumes the result. For example, when a nir 'bcsel'
133 * consumes the result of 'feq'. So we should be able to get by
134 * without a boolean resolve step, and without incuring any
135 * extra penalty in instruction count.
136 */
137
138 /* NIR bool -> native (adreno): */
139 static struct ir3_instruction *
140 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
141 {
142 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
143 }
144
145 /* native (adreno) -> NIR bool: */
146 static struct ir3_instruction *
147 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
148 {
149 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
150 }
151
152 /*
153 * alu/sfu instructions:
154 */
155
156 static struct ir3_instruction *
157 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
158 unsigned src_bitsize, nir_op op)
159 {
160 type_t src_type, dst_type;
161
162 switch (op) {
163 case nir_op_f2f32:
164 case nir_op_f2f16_rtne:
165 case nir_op_f2f16_rtz:
166 case nir_op_f2f16:
167 case nir_op_f2i32:
168 case nir_op_f2i16:
169 case nir_op_f2i8:
170 case nir_op_f2u32:
171 case nir_op_f2u16:
172 case nir_op_f2u8:
173 switch (src_bitsize) {
174 case 32:
175 src_type = TYPE_F32;
176 break;
177 case 16:
178 src_type = TYPE_F16;
179 break;
180 default:
181 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
182 }
183 break;
184
185 case nir_op_i2f32:
186 case nir_op_i2f16:
187 case nir_op_i2i32:
188 case nir_op_i2i16:
189 case nir_op_i2i8:
190 switch (src_bitsize) {
191 case 32:
192 src_type = TYPE_S32;
193 break;
194 case 16:
195 src_type = TYPE_S16;
196 break;
197 case 8:
198 src_type = TYPE_S8;
199 break;
200 default:
201 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
202 }
203 break;
204
205 case nir_op_u2f32:
206 case nir_op_u2f16:
207 case nir_op_u2u32:
208 case nir_op_u2u16:
209 case nir_op_u2u8:
210 switch (src_bitsize) {
211 case 32:
212 src_type = TYPE_U32;
213 break;
214 case 16:
215 src_type = TYPE_U16;
216 break;
217 case 8:
218 src_type = TYPE_U8;
219 break;
220 default:
221 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
222 }
223 break;
224
225 default:
226 ir3_context_error(ctx, "invalid conversion op: %u", op);
227 }
228
229 switch (op) {
230 case nir_op_f2f32:
231 case nir_op_i2f32:
232 case nir_op_u2f32:
233 dst_type = TYPE_F32;
234 break;
235
236 case nir_op_f2f16_rtne:
237 case nir_op_f2f16_rtz:
238 case nir_op_f2f16:
239 /* TODO how to handle rounding mode? */
240 case nir_op_i2f16:
241 case nir_op_u2f16:
242 dst_type = TYPE_F16;
243 break;
244
245 case nir_op_f2i32:
246 case nir_op_i2i32:
247 dst_type = TYPE_S32;
248 break;
249
250 case nir_op_f2i16:
251 case nir_op_i2i16:
252 dst_type = TYPE_S16;
253 break;
254
255 case nir_op_f2i8:
256 case nir_op_i2i8:
257 dst_type = TYPE_S8;
258 break;
259
260 case nir_op_f2u32:
261 case nir_op_u2u32:
262 dst_type = TYPE_U32;
263 break;
264
265 case nir_op_f2u16:
266 case nir_op_u2u16:
267 dst_type = TYPE_U16;
268 break;
269
270 case nir_op_f2u8:
271 case nir_op_u2u8:
272 dst_type = TYPE_U8;
273 break;
274
275 default:
276 ir3_context_error(ctx, "invalid conversion op: %u", op);
277 }
278
279 return ir3_COV(ctx->block, src, src_type, dst_type);
280 }
281
282 static void
283 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
284 {
285 const nir_op_info *info = &nir_op_infos[alu->op];
286 struct ir3_instruction **dst, *src[info->num_inputs];
287 unsigned bs[info->num_inputs]; /* bit size */
288 struct ir3_block *b = ctx->block;
289 unsigned dst_sz, wrmask;
290 type_t dst_type = nir_dest_bit_size(alu->dest.dest) < 32 ?
291 TYPE_U16 : TYPE_U32;
292
293 if (alu->dest.dest.is_ssa) {
294 dst_sz = alu->dest.dest.ssa.num_components;
295 wrmask = (1 << dst_sz) - 1;
296 } else {
297 dst_sz = alu->dest.dest.reg.reg->num_components;
298 wrmask = alu->dest.write_mask;
299 }
300
301 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
302
303 /* Vectors are special in that they have non-scalarized writemasks,
304 * and just take the first swizzle channel for each argument in
305 * order into each writemask channel.
306 */
307 if ((alu->op == nir_op_vec2) ||
308 (alu->op == nir_op_vec3) ||
309 (alu->op == nir_op_vec4)) {
310
311 for (int i = 0; i < info->num_inputs; i++) {
312 nir_alu_src *asrc = &alu->src[i];
313
314 compile_assert(ctx, !asrc->abs);
315 compile_assert(ctx, !asrc->negate);
316
317 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
318 if (!src[i])
319 src[i] = create_immed_typed(ctx->block, 0, dst_type);
320 dst[i] = ir3_MOV(b, src[i], dst_type);
321 }
322
323 ir3_put_dst(ctx, &alu->dest.dest);
324 return;
325 }
326
327 /* We also get mov's with more than one component for mov's so
328 * handle those specially:
329 */
330 if (alu->op == nir_op_mov) {
331 nir_alu_src *asrc = &alu->src[0];
332 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
333
334 for (unsigned i = 0; i < dst_sz; i++) {
335 if (wrmask & (1 << i)) {
336 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
337 } else {
338 dst[i] = NULL;
339 }
340 }
341
342 ir3_put_dst(ctx, &alu->dest.dest);
343 return;
344 }
345
346 /* General case: We can just grab the one used channel per src. */
347 for (int i = 0; i < info->num_inputs; i++) {
348 unsigned chan = ffs(alu->dest.write_mask) - 1;
349 nir_alu_src *asrc = &alu->src[i];
350
351 compile_assert(ctx, !asrc->abs);
352 compile_assert(ctx, !asrc->negate);
353
354 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
355 bs[i] = nir_src_bit_size(asrc->src);
356
357 compile_assert(ctx, src[i]);
358 }
359
360 switch (alu->op) {
361 case nir_op_f2f32:
362 case nir_op_f2f16_rtne:
363 case nir_op_f2f16_rtz:
364 case nir_op_f2f16:
365 case nir_op_f2i32:
366 case nir_op_f2i16:
367 case nir_op_f2i8:
368 case nir_op_f2u32:
369 case nir_op_f2u16:
370 case nir_op_f2u8:
371 case nir_op_i2f32:
372 case nir_op_i2f16:
373 case nir_op_i2i32:
374 case nir_op_i2i16:
375 case nir_op_i2i8:
376 case nir_op_u2f32:
377 case nir_op_u2f16:
378 case nir_op_u2u32:
379 case nir_op_u2u16:
380 case nir_op_u2u8:
381 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
382 break;
383 case nir_op_fquantize2f16:
384 dst[0] = create_cov(ctx,
385 create_cov(ctx, src[0], 32, nir_op_f2f16),
386 16, nir_op_f2f32);
387 break;
388 case nir_op_f2b16: {
389 struct ir3_instruction *zero = create_immed_typed(b, 0, TYPE_F16);
390 dst[0] = ir3_CMPS_F(b, src[0], 0, zero, 0);
391 dst[0]->cat2.condition = IR3_COND_NE;
392 break;
393 }
394 case nir_op_f2b32:
395 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
396 dst[0]->cat2.condition = IR3_COND_NE;
397 break;
398 case nir_op_b2f16:
399 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F16);
400 break;
401 case nir_op_b2f32:
402 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
403 break;
404 case nir_op_b2i8:
405 case nir_op_b2i16:
406 case nir_op_b2i32:
407 dst[0] = ir3_b2n(b, src[0]);
408 break;
409 case nir_op_i2b16: {
410 struct ir3_instruction *zero = create_immed_typed(b, 0, TYPE_S16);
411 dst[0] = ir3_CMPS_S(b, src[0], 0, zero, 0);
412 dst[0]->cat2.condition = IR3_COND_NE;
413 break;
414 }
415 case nir_op_i2b32:
416 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
417 dst[0]->cat2.condition = IR3_COND_NE;
418 break;
419
420 case nir_op_fneg:
421 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
422 break;
423 case nir_op_fabs:
424 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
425 break;
426 case nir_op_fmax:
427 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
428 break;
429 case nir_op_fmin:
430 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
431 break;
432 case nir_op_fsat:
433 /* if there is just a single use of the src, and it supports
434 * (sat) bit, we can just fold the (sat) flag back to the
435 * src instruction and create a mov. This is easier for cp
436 * to eliminate.
437 *
438 * TODO probably opc_cat==4 is ok too
439 */
440 if (alu->src[0].src.is_ssa &&
441 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
442 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
443 src[0]->flags |= IR3_INSTR_SAT;
444 dst[0] = ir3_MOV(b, src[0], dst_type);
445 } else {
446 /* otherwise generate a max.f that saturates.. blob does
447 * similar (generating a cat2 mov using max.f)
448 */
449 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
450 dst[0]->flags |= IR3_INSTR_SAT;
451 }
452 break;
453 case nir_op_fmul:
454 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
455 break;
456 case nir_op_fadd:
457 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
458 break;
459 case nir_op_fsub:
460 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
461 break;
462 case nir_op_ffma:
463 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
464 break;
465 case nir_op_fddx:
466 case nir_op_fddx_coarse:
467 dst[0] = ir3_DSX(b, src[0], 0);
468 dst[0]->cat5.type = TYPE_F32;
469 break;
470 case nir_op_fddx_fine:
471 dst[0] = ir3_DSXPP_1(b, src[0], 0);
472 dst[0]->cat5.type = TYPE_F32;
473 break;
474 case nir_op_fddy:
475 case nir_op_fddy_coarse:
476 dst[0] = ir3_DSY(b, src[0], 0);
477 dst[0]->cat5.type = TYPE_F32;
478 break;
479 break;
480 case nir_op_fddy_fine:
481 dst[0] = ir3_DSYPP_1(b, src[0], 0);
482 dst[0]->cat5.type = TYPE_F32;
483 break;
484 case nir_op_flt16:
485 case nir_op_flt32:
486 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
487 dst[0]->cat2.condition = IR3_COND_LT;
488 break;
489 case nir_op_fge16:
490 case nir_op_fge32:
491 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
492 dst[0]->cat2.condition = IR3_COND_GE;
493 break;
494 case nir_op_feq16:
495 case nir_op_feq32:
496 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
497 dst[0]->cat2.condition = IR3_COND_EQ;
498 break;
499 case nir_op_fne16:
500 case nir_op_fne32:
501 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
502 dst[0]->cat2.condition = IR3_COND_NE;
503 break;
504 case nir_op_fceil:
505 dst[0] = ir3_CEIL_F(b, src[0], 0);
506 break;
507 case nir_op_ffloor:
508 dst[0] = ir3_FLOOR_F(b, src[0], 0);
509 break;
510 case nir_op_ftrunc:
511 dst[0] = ir3_TRUNC_F(b, src[0], 0);
512 break;
513 case nir_op_fround_even:
514 dst[0] = ir3_RNDNE_F(b, src[0], 0);
515 break;
516 case nir_op_fsign:
517 dst[0] = ir3_SIGN_F(b, src[0], 0);
518 break;
519
520 case nir_op_fsin:
521 dst[0] = ir3_SIN(b, src[0], 0);
522 break;
523 case nir_op_fcos:
524 dst[0] = ir3_COS(b, src[0], 0);
525 break;
526 case nir_op_frsq:
527 dst[0] = ir3_RSQ(b, src[0], 0);
528 break;
529 case nir_op_frcp:
530 dst[0] = ir3_RCP(b, src[0], 0);
531 break;
532 case nir_op_flog2:
533 dst[0] = ir3_LOG2(b, src[0], 0);
534 break;
535 case nir_op_fexp2:
536 dst[0] = ir3_EXP2(b, src[0], 0);
537 break;
538 case nir_op_fsqrt:
539 dst[0] = ir3_SQRT(b, src[0], 0);
540 break;
541
542 case nir_op_iabs:
543 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
544 break;
545 case nir_op_iadd:
546 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
547 break;
548 case nir_op_iand:
549 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
550 break;
551 case nir_op_imax:
552 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
553 break;
554 case nir_op_umax:
555 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
556 break;
557 case nir_op_imin:
558 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
559 break;
560 case nir_op_umin:
561 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
562 break;
563 case nir_op_umul_low:
564 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
565 break;
566 case nir_op_imadsh_mix16:
567 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
568 break;
569 case nir_op_imad24_ir3:
570 dst[0] = ir3_MAD_S24(b, src[0], 0, src[1], 0, src[2], 0);
571 break;
572 case nir_op_imul24:
573 dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
574 break;
575 case nir_op_ineg:
576 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
577 break;
578 case nir_op_inot:
579 dst[0] = ir3_NOT_B(b, src[0], 0);
580 break;
581 case nir_op_ior:
582 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
583 break;
584 case nir_op_ishl:
585 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
586 break;
587 case nir_op_ishr:
588 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
589 break;
590 case nir_op_isub:
591 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
592 break;
593 case nir_op_ixor:
594 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
595 break;
596 case nir_op_ushr:
597 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
598 break;
599 case nir_op_ilt16:
600 case nir_op_ilt32:
601 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
602 dst[0]->cat2.condition = IR3_COND_LT;
603 break;
604 case nir_op_ige16:
605 case nir_op_ige32:
606 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
607 dst[0]->cat2.condition = IR3_COND_GE;
608 break;
609 case nir_op_ieq16:
610 case nir_op_ieq32:
611 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
612 dst[0]->cat2.condition = IR3_COND_EQ;
613 break;
614 case nir_op_ine16:
615 case nir_op_ine32:
616 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
617 dst[0]->cat2.condition = IR3_COND_NE;
618 break;
619 case nir_op_ult16:
620 case nir_op_ult32:
621 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
622 dst[0]->cat2.condition = IR3_COND_LT;
623 break;
624 case nir_op_uge16:
625 case nir_op_uge32:
626 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
627 dst[0]->cat2.condition = IR3_COND_GE;
628 break;
629
630 case nir_op_b16csel:
631 case nir_op_b32csel: {
632 struct ir3_instruction *cond = src[0];
633
634 /* If src[0] is a negation (likely as a result of an ir3_b2n(cond)),
635 * we can ignore that and use original cond, since the nonzero-ness of
636 * cond stays the same.
637 */
638 if (cond->opc == OPC_ABSNEG_S &&
639 cond->flags == 0 &&
640 (cond->regs[1]->flags & (IR3_REG_SNEG | IR3_REG_SABS)) == IR3_REG_SNEG) {
641 cond = cond->regs[1]->instr;
642 }
643
644 compile_assert(ctx, bs[1] == bs[2]);
645 if (bs[1] != bs[0]) {
646 struct hash_entry *prev_entry =
647 _mesa_hash_table_search(ctx->sel_cond_conversions, src[0]);
648 if (prev_entry) {
649 cond = prev_entry->data;
650 } else {
651 /* Make sure the boolean condition has the same bit size as the other
652 * two arguments, adding a conversion if necessary.
653 */
654 if (bs[1] < bs[0])
655 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
656 else if (bs[1] > bs[0])
657 cond = ir3_COV(b, cond, TYPE_U16, TYPE_U32);
658 _mesa_hash_table_insert(ctx->sel_cond_conversions, src[0], cond);
659 }
660 }
661
662 if (bs[1] > 16)
663 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
664 else
665 dst[0] = ir3_SEL_B16(b, src[1], 0, cond, 0, src[2], 0);
666 break;
667 }
668 case nir_op_bit_count: {
669 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
670 // double check on earlier gen's. Once half-precision support is
671 // in place, this should probably move to a NIR lowering pass:
672 struct ir3_instruction *hi, *lo;
673
674 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
675 TYPE_U32, TYPE_U16);
676 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
677
678 hi = ir3_CBITS_B(b, hi, 0);
679 lo = ir3_CBITS_B(b, lo, 0);
680
681 // TODO maybe the builders should default to making dst half-precision
682 // if the src's were half precision, to make this less awkward.. otoh
683 // we should probably just do this lowering in NIR.
684 hi->regs[0]->flags |= IR3_REG_HALF;
685 lo->regs[0]->flags |= IR3_REG_HALF;
686
687 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
688 dst[0]->regs[0]->flags |= IR3_REG_HALF;
689 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
690 break;
691 }
692 case nir_op_ifind_msb: {
693 struct ir3_instruction *cmp;
694 dst[0] = ir3_CLZ_S(b, src[0], 0);
695 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
696 cmp->cat2.condition = IR3_COND_GE;
697 dst[0] = ir3_SEL_B32(b,
698 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
699 cmp, 0, dst[0], 0);
700 break;
701 }
702 case nir_op_ufind_msb:
703 dst[0] = ir3_CLZ_B(b, src[0], 0);
704 dst[0] = ir3_SEL_B32(b,
705 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
706 src[0], 0, dst[0], 0);
707 break;
708 case nir_op_find_lsb:
709 dst[0] = ir3_BFREV_B(b, src[0], 0);
710 dst[0] = ir3_CLZ_B(b, dst[0], 0);
711 break;
712 case nir_op_bitfield_reverse:
713 dst[0] = ir3_BFREV_B(b, src[0], 0);
714 break;
715
716 default:
717 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
718 nir_op_infos[alu->op].name);
719 break;
720 }
721
722 if (nir_alu_type_get_base_type(info->output_type) == nir_type_bool) {
723 assert(dst_sz == 1);
724
725 if (nir_dest_bit_size(alu->dest.dest) < 32)
726 dst[0]->regs[0]->flags |= IR3_REG_HALF;
727
728 dst[0] = ir3_n2b(b, dst[0]);
729 }
730
731 if (nir_dest_bit_size(alu->dest.dest) < 32) {
732 for (unsigned i = 0; i < dst_sz; i++) {
733 dst[i]->regs[0]->flags |= IR3_REG_HALF;
734 }
735 }
736
737 ir3_put_dst(ctx, &alu->dest.dest);
738 }
739
740 static void
741 emit_intrinsic_load_ubo_ldc(struct ir3_context *ctx, nir_intrinsic_instr *intr,
742 struct ir3_instruction **dst)
743 {
744 struct ir3_block *b = ctx->block;
745
746 unsigned ncomp = intr->num_components;
747 struct ir3_instruction *offset = ir3_get_src(ctx, &intr->src[1])[0];
748 struct ir3_instruction *idx = ir3_get_src(ctx, &intr->src[0])[0];
749 struct ir3_instruction *ldc = ir3_LDC(b, idx, 0, offset, 0);
750 ldc->regs[0]->wrmask = MASK(ncomp);
751 ldc->cat6.iim_val = intr->num_components;
752 ldc->cat6.d = 1;
753 ldc->cat6.type = TYPE_U32;
754
755 nir_intrinsic_instr *bindless = ir3_bindless_resource(intr->src[0]);
756 if (bindless) {
757 ldc->flags |= IR3_INSTR_B;
758 ldc->cat6.base = nir_intrinsic_desc_set(bindless);
759 ctx->so->bindless_ubo = true;
760 }
761
762 ir3_split_dest(b, dst, ldc, 0, ncomp);
763 }
764
765
766 /* handles direct/indirect UBO reads: */
767 static void
768 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
769 struct ir3_instruction **dst)
770 {
771 if (ir3_bindless_resource(intr->src[0])) {
772 /* TODO: We should be using ldc for non-bindless things on a6xx as
773 * well.
774 */
775 emit_intrinsic_load_ubo_ldc(ctx, intr, dst);
776 return;
777 }
778 struct ir3_block *b = ctx->block;
779 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
780 /* UBO addresses are the first driver params, but subtract 2 here to
781 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
782 * is the uniforms: */
783 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
784 unsigned ubo = regid(const_state->offsets.ubo, 0) - 2;
785 const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
786
787 int off = 0;
788
789 /* First src is ubo index, which could either be an immed or not: */
790 src0 = ir3_get_src(ctx, &intr->src[0])[0];
791 if (is_same_type_mov(src0) &&
792 (src0->regs[1]->flags & IR3_REG_IMMED)) {
793 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
794 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
795 } else {
796 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr0(ctx, src0, ptrsz));
797 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr0(ctx, src0, ptrsz));
798
799 /* NOTE: since relative addressing is used, make sure constlen is
800 * at least big enough to cover all the UBO addresses, since the
801 * assembler won't know what the max address reg is.
802 */
803 ctx->so->constlen = MAX2(ctx->so->constlen,
804 const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
805 }
806
807 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
808 addr = base_lo;
809
810 if (nir_src_is_const(intr->src[1])) {
811 off += nir_src_as_uint(intr->src[1]);
812 } else {
813 /* For load_ubo_indirect, second src is indirect offset: */
814 src1 = ir3_get_src(ctx, &intr->src[1])[0];
815
816 /* and add offset to addr: */
817 addr = ir3_ADD_S(b, addr, 0, src1, 0);
818 }
819
820 /* if offset is to large to encode in the ldg, split it out: */
821 if ((off + (intr->num_components * 4)) > 1024) {
822 /* split out the minimal amount to improve the odds that
823 * cp can fit the immediate in the add.s instruction:
824 */
825 unsigned off2 = off + (intr->num_components * 4) - 1024;
826 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
827 off -= off2;
828 }
829
830 if (ptrsz == 2) {
831 struct ir3_instruction *carry;
832
833 /* handle 32b rollover, ie:
834 * if (addr < base_lo)
835 * base_hi++
836 */
837 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
838 carry->cat2.condition = IR3_COND_LT;
839 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
840
841 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
842 }
843
844 for (int i = 0; i < intr->num_components; i++) {
845 struct ir3_instruction *load =
846 ir3_LDG(b, addr, 0, create_immed(b, 1), 0, /* num components */
847 create_immed(b, off + i * 4), 0);
848 load->cat6.type = TYPE_U32;
849 dst[i] = load;
850 }
851 }
852
853 /* src[] = { block_index } */
854 static void
855 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
856 struct ir3_instruction **dst)
857 {
858 /* SSBO size stored as a const starting at ssbo_sizes: */
859 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
860 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
861 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
862 const_state->ssbo_size.off[blk_idx];
863
864 debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
865
866 dst[0] = create_uniform(ctx->block, idx);
867 }
868
869 /* src[] = { offset }. const_index[] = { base } */
870 static void
871 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
872 struct ir3_instruction **dst)
873 {
874 struct ir3_block *b = ctx->block;
875 struct ir3_instruction *ldl, *offset;
876 unsigned base;
877
878 offset = ir3_get_src(ctx, &intr->src[0])[0];
879 base = nir_intrinsic_base(intr);
880
881 ldl = ir3_LDL(b, offset, 0,
882 create_immed(b, intr->num_components), 0,
883 create_immed(b, base), 0);
884
885 ldl->cat6.type = utype_dst(intr->dest);
886 ldl->regs[0]->wrmask = MASK(intr->num_components);
887
888 ldl->barrier_class = IR3_BARRIER_SHARED_R;
889 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
890
891 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
892 }
893
894 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
895 static void
896 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
897 {
898 struct ir3_block *b = ctx->block;
899 struct ir3_instruction *stl, *offset;
900 struct ir3_instruction * const *value;
901 unsigned base, wrmask;
902
903 value = ir3_get_src(ctx, &intr->src[0]);
904 offset = ir3_get_src(ctx, &intr->src[1])[0];
905
906 base = nir_intrinsic_base(intr);
907 wrmask = nir_intrinsic_write_mask(intr);
908
909 /* Combine groups of consecutive enabled channels in one write
910 * message. We use ffs to find the first enabled channel and then ffs on
911 * the bit-inverse, down-shifted writemask to determine the length of
912 * the block of enabled bits.
913 *
914 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
915 */
916 while (wrmask) {
917 unsigned first_component = ffs(wrmask) - 1;
918 unsigned length = ffs(~(wrmask >> first_component)) - 1;
919
920 stl = ir3_STL(b, offset, 0,
921 ir3_create_collect(ctx, &value[first_component], length), 0,
922 create_immed(b, length), 0);
923 stl->cat6.dst_offset = first_component + base;
924 stl->cat6.type = utype_src(intr->src[0]);
925 stl->barrier_class = IR3_BARRIER_SHARED_W;
926 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
927
928 array_insert(b, b->keeps, stl);
929
930 /* Clear the bits in the writemask that we just wrote, then try
931 * again to see if more channels are left.
932 */
933 wrmask &= (15 << (first_component + length));
934 }
935 }
936
937 /* src[] = { offset }. const_index[] = { base } */
938 static void
939 emit_intrinsic_load_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr,
940 struct ir3_instruction **dst)
941 {
942 struct ir3_block *b = ctx->block;
943 struct ir3_instruction *load, *offset;
944 unsigned base;
945
946 offset = ir3_get_src(ctx, &intr->src[0])[0];
947 base = nir_intrinsic_base(intr);
948
949 load = ir3_LDLW(b, offset, 0,
950 create_immed(b, intr->num_components), 0,
951 create_immed(b, base), 0);
952
953 load->cat6.type = utype_dst(intr->dest);
954 load->regs[0]->wrmask = MASK(intr->num_components);
955
956 load->barrier_class = IR3_BARRIER_SHARED_R;
957 load->barrier_conflict = IR3_BARRIER_SHARED_W;
958
959 ir3_split_dest(b, dst, load, 0, intr->num_components);
960 }
961
962 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
963 static void
964 emit_intrinsic_store_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr)
965 {
966 struct ir3_block *b = ctx->block;
967 struct ir3_instruction *store, *offset;
968 struct ir3_instruction * const *value;
969 unsigned base, wrmask;
970
971 value = ir3_get_src(ctx, &intr->src[0]);
972 offset = ir3_get_src(ctx, &intr->src[1])[0];
973
974 base = nir_intrinsic_base(intr);
975 wrmask = nir_intrinsic_write_mask(intr);
976
977 /* Combine groups of consecutive enabled channels in one write
978 * message. We use ffs to find the first enabled channel and then ffs on
979 * the bit-inverse, down-shifted writemask to determine the length of
980 * the block of enabled bits.
981 *
982 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
983 */
984 while (wrmask) {
985 unsigned first_component = ffs(wrmask) - 1;
986 unsigned length = ffs(~(wrmask >> first_component)) - 1;
987
988 store = ir3_STLW(b, offset, 0,
989 ir3_create_collect(ctx, &value[first_component], length), 0,
990 create_immed(b, length), 0);
991
992 store->cat6.dst_offset = first_component + base;
993 store->cat6.type = utype_src(intr->src[0]);
994 store->barrier_class = IR3_BARRIER_SHARED_W;
995 store->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
996
997 array_insert(b, b->keeps, store);
998
999 /* Clear the bits in the writemask that we just wrote, then try
1000 * again to see if more channels are left.
1001 */
1002 wrmask &= (15 << (first_component + length));
1003 }
1004 }
1005
1006 /*
1007 * CS shared variable atomic intrinsics
1008 *
1009 * All of the shared variable atomic memory operations read a value from
1010 * memory, compute a new value using one of the operations below, write the
1011 * new value to memory, and return the original value read.
1012 *
1013 * All operations take 2 sources except CompSwap that takes 3. These
1014 * sources represent:
1015 *
1016 * 0: The offset into the shared variable storage region that the atomic
1017 * operation will operate on.
1018 * 1: The data parameter to the atomic function (i.e. the value to add
1019 * in shared_atomic_add, etc).
1020 * 2: For CompSwap only: the second data parameter.
1021 */
1022 static struct ir3_instruction *
1023 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1024 {
1025 struct ir3_block *b = ctx->block;
1026 struct ir3_instruction *atomic, *src0, *src1;
1027 type_t type = TYPE_U32;
1028
1029 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
1030 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
1031
1032 switch (intr->intrinsic) {
1033 case nir_intrinsic_shared_atomic_add:
1034 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
1035 break;
1036 case nir_intrinsic_shared_atomic_imin:
1037 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
1038 type = TYPE_S32;
1039 break;
1040 case nir_intrinsic_shared_atomic_umin:
1041 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
1042 break;
1043 case nir_intrinsic_shared_atomic_imax:
1044 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1045 type = TYPE_S32;
1046 break;
1047 case nir_intrinsic_shared_atomic_umax:
1048 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1049 break;
1050 case nir_intrinsic_shared_atomic_and:
1051 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
1052 break;
1053 case nir_intrinsic_shared_atomic_or:
1054 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
1055 break;
1056 case nir_intrinsic_shared_atomic_xor:
1057 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
1058 break;
1059 case nir_intrinsic_shared_atomic_exchange:
1060 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
1061 break;
1062 case nir_intrinsic_shared_atomic_comp_swap:
1063 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1064 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1065 ir3_get_src(ctx, &intr->src[2])[0],
1066 src1,
1067 }, 2);
1068 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
1069 break;
1070 default:
1071 unreachable("boo");
1072 }
1073
1074 atomic->cat6.iim_val = 1;
1075 atomic->cat6.d = 1;
1076 atomic->cat6.type = type;
1077 atomic->barrier_class = IR3_BARRIER_SHARED_W;
1078 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
1079
1080 /* even if nothing consume the result, we can't DCE the instruction: */
1081 array_insert(b, b->keeps, atomic);
1082
1083 return atomic;
1084 }
1085
1086 struct tex_src_info {
1087 /* For prefetch */
1088 unsigned tex_base, samp_base, tex_idx, samp_idx;
1089 /* For normal tex instructions */
1090 unsigned base, combined_idx, a1_val, flags;
1091 struct ir3_instruction *samp_tex;
1092 };
1093
1094 /* TODO handle actual indirect/dynamic case.. which is going to be weird
1095 * to handle with the image_mapping table..
1096 */
1097 static struct tex_src_info
1098 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1099 {
1100 struct ir3_block *b = ctx->block;
1101 struct tex_src_info info = { 0 };
1102 nir_intrinsic_instr *bindless_tex = ir3_bindless_resource(intr->src[0]);
1103 ctx->so->bindless_tex = true;
1104
1105 if (bindless_tex) {
1106 /* Bindless case */
1107 info.flags |= IR3_INSTR_B;
1108
1109 /* Gather information required to determine which encoding to
1110 * choose as well as for prefetch.
1111 */
1112 info.tex_base = nir_intrinsic_desc_set(bindless_tex);
1113 bool tex_const = nir_src_is_const(bindless_tex->src[0]);
1114 if (tex_const)
1115 info.tex_idx = nir_src_as_uint(bindless_tex->src[0]);
1116 info.samp_idx = 0;
1117
1118 /* Choose encoding. */
1119 if (tex_const && info.tex_idx < 256) {
1120 if (info.tex_idx < 16) {
1121 /* Everything fits within the instruction */
1122 info.base = info.tex_base;
1123 info.combined_idx = info.samp_idx | (info.tex_idx << 4);
1124 } else {
1125 info.base = info.tex_base;
1126 info.a1_val = info.tex_idx << 3;
1127 info.combined_idx = 0;
1128 info.flags |= IR3_INSTR_A1EN;
1129 }
1130 info.samp_tex = NULL;
1131 } else {
1132 info.flags |= IR3_INSTR_S2EN;
1133 info.base = info.tex_base;
1134
1135 /* Note: the indirect source is now a vec2 instead of hvec2 */
1136 struct ir3_instruction *texture, *sampler;
1137
1138 texture = ir3_get_src(ctx, &intr->src[0])[0];
1139 sampler = create_immed(b, 0);
1140 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1141 texture,
1142 sampler,
1143 }, 2);
1144 }
1145 } else {
1146 info.flags |= IR3_INSTR_S2EN;
1147 unsigned slot = nir_src_as_uint(intr->src[0]);
1148 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
1149 struct ir3_instruction *texture, *sampler;
1150
1151 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1152 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1153
1154 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1155 sampler,
1156 texture,
1157 }, 2);
1158 }
1159
1160 return info;
1161 }
1162
1163 static struct ir3_instruction *
1164 emit_sam(struct ir3_context *ctx, opc_t opc, struct tex_src_info info,
1165 type_t type, unsigned wrmask, struct ir3_instruction *src0,
1166 struct ir3_instruction *src1)
1167 {
1168 struct ir3_instruction *sam, *addr;
1169 if (info.flags & IR3_INSTR_A1EN) {
1170 addr = ir3_get_addr1(ctx, info.a1_val);
1171 }
1172 sam = ir3_SAM(ctx->block, opc, type, 0b1111, info.flags,
1173 info.samp_tex, src0, src1);
1174 if (info.flags & IR3_INSTR_A1EN) {
1175 ir3_instr_set_address(sam, addr);
1176 }
1177 if (info.flags & IR3_INSTR_B) {
1178 sam->cat5.tex_base = info.base;
1179 sam->cat5.samp = info.combined_idx;
1180 }
1181 return sam;
1182 }
1183
1184 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1185 static void
1186 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1187 struct ir3_instruction **dst)
1188 {
1189 struct ir3_block *b = ctx->block;
1190 struct tex_src_info info = get_image_samp_tex_src(ctx, intr);
1191 struct ir3_instruction *sam;
1192 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
1193 struct ir3_instruction *coords[4];
1194 unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
1195 type_t type = ir3_get_type_for_image_intrinsic(intr);
1196
1197 /* hmm, this seems a bit odd, but it is what blob does and (at least
1198 * a5xx) just faults on bogus addresses otherwise:
1199 */
1200 if (flags & IR3_INSTR_3D) {
1201 flags &= ~IR3_INSTR_3D;
1202 flags |= IR3_INSTR_A;
1203 }
1204 info.flags |= flags;
1205
1206 for (unsigned i = 0; i < ncoords; i++)
1207 coords[i] = src0[i];
1208
1209 if (ncoords == 1)
1210 coords[ncoords++] = create_immed(b, 0);
1211
1212 sam = emit_sam(ctx, OPC_ISAM, info, type, 0b1111,
1213 ir3_create_collect(ctx, coords, ncoords), NULL);
1214
1215 sam->barrier_class = IR3_BARRIER_IMAGE_R;
1216 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
1217
1218 ir3_split_dest(b, dst, sam, 0, 4);
1219 }
1220
1221 static void
1222 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1223 struct ir3_instruction **dst)
1224 {
1225 struct ir3_block *b = ctx->block;
1226 struct tex_src_info info = get_image_samp_tex_src(ctx, intr);
1227 struct ir3_instruction *sam, *lod;
1228 unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
1229 type_t dst_type = nir_dest_bit_size(intr->dest) < 32 ?
1230 TYPE_U16 : TYPE_U32;
1231
1232 info.flags |= flags;
1233 lod = create_immed(b, 0);
1234 sam = emit_sam(ctx, OPC_GETSIZE, info, dst_type, 0b1111, lod, NULL);
1235
1236 /* Array size actually ends up in .w rather than .z. This doesn't
1237 * matter for miplevel 0, but for higher mips the value in z is
1238 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1239 * returned, which means that we have to add 1 to it for arrays for
1240 * a3xx.
1241 *
1242 * Note use a temporary dst and then copy, since the size of the dst
1243 * array that is passed in is based on nir's understanding of the
1244 * result size, not the hardware's
1245 */
1246 struct ir3_instruction *tmp[4];
1247
1248 ir3_split_dest(b, tmp, sam, 0, 4);
1249
1250 /* get_size instruction returns size in bytes instead of texels
1251 * for imageBuffer, so we need to divide it by the pixel size
1252 * of the image format.
1253 *
1254 * TODO: This is at least true on a5xx. Check other gens.
1255 */
1256 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF) {
1257 /* Since all the possible values the divisor can take are
1258 * power-of-two (4, 8, or 16), the division is implemented
1259 * as a shift-right.
1260 * During shader setup, the log2 of the image format's
1261 * bytes-per-pixel should have been emitted in 2nd slot of
1262 * image_dims. See ir3_shader::emit_image_dims().
1263 */
1264 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
1265 unsigned cb = regid(const_state->offsets.image_dims, 0) +
1266 const_state->image_dims.off[nir_src_as_uint(intr->src[0])];
1267 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1268
1269 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1270 }
1271
1272 for (unsigned i = 0; i < ncoords; i++)
1273 dst[i] = tmp[i];
1274
1275 if (flags & IR3_INSTR_A) {
1276 if (ctx->compiler->levels_add_one) {
1277 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1278 } else {
1279 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1280 }
1281 }
1282 }
1283
1284 static void
1285 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1286 {
1287 struct ir3_block *b = ctx->block;
1288 struct ir3_instruction *barrier;
1289
1290 switch (intr->intrinsic) {
1291 case nir_intrinsic_control_barrier:
1292 barrier = ir3_BAR(b);
1293 barrier->cat7.g = true;
1294 barrier->cat7.l = true;
1295 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1296 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1297 break;
1298 case nir_intrinsic_memory_barrier:
1299 barrier = ir3_FENCE(b);
1300 barrier->cat7.g = true;
1301 barrier->cat7.r = true;
1302 barrier->cat7.w = true;
1303 barrier->cat7.l = true;
1304 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1305 IR3_BARRIER_BUFFER_W;
1306 barrier->barrier_conflict =
1307 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1308 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1309 break;
1310 case nir_intrinsic_memory_barrier_buffer:
1311 barrier = ir3_FENCE(b);
1312 barrier->cat7.g = true;
1313 barrier->cat7.r = true;
1314 barrier->cat7.w = true;
1315 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1316 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1317 IR3_BARRIER_BUFFER_W;
1318 break;
1319 case nir_intrinsic_memory_barrier_image:
1320 // TODO double check if this should have .g set
1321 barrier = ir3_FENCE(b);
1322 barrier->cat7.g = true;
1323 barrier->cat7.r = true;
1324 barrier->cat7.w = true;
1325 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1326 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1327 IR3_BARRIER_IMAGE_W;
1328 break;
1329 case nir_intrinsic_memory_barrier_shared:
1330 barrier = ir3_FENCE(b);
1331 barrier->cat7.g = true;
1332 barrier->cat7.l = true;
1333 barrier->cat7.r = true;
1334 barrier->cat7.w = true;
1335 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1336 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1337 IR3_BARRIER_SHARED_W;
1338 break;
1339 case nir_intrinsic_group_memory_barrier:
1340 barrier = ir3_FENCE(b);
1341 barrier->cat7.g = true;
1342 barrier->cat7.l = true;
1343 barrier->cat7.r = true;
1344 barrier->cat7.w = true;
1345 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1346 IR3_BARRIER_IMAGE_W |
1347 IR3_BARRIER_BUFFER_W;
1348 barrier->barrier_conflict =
1349 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1350 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1351 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1352 break;
1353 default:
1354 unreachable("boo");
1355 }
1356
1357 /* make sure barrier doesn't get DCE'd */
1358 array_insert(b, b->keeps, barrier);
1359 }
1360
1361 static void add_sysval_input_compmask(struct ir3_context *ctx,
1362 gl_system_value slot, unsigned compmask,
1363 struct ir3_instruction *instr)
1364 {
1365 struct ir3_shader_variant *so = ctx->so;
1366 unsigned n = so->inputs_count++;
1367
1368 assert(instr->opc == OPC_META_INPUT);
1369 instr->input.inidx = n;
1370 instr->input.sysval = slot;
1371
1372 so->inputs[n].sysval = true;
1373 so->inputs[n].slot = slot;
1374 so->inputs[n].compmask = compmask;
1375 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1376 so->total_in++;
1377 }
1378
1379 static struct ir3_instruction *
1380 create_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1381 unsigned compmask)
1382 {
1383 assert(compmask);
1384 struct ir3_instruction *sysval = create_input(ctx, compmask);
1385 add_sysval_input_compmask(ctx, slot, compmask, sysval);
1386 return sysval;
1387 }
1388
1389 static struct ir3_instruction *
1390 get_barycentric_centroid(struct ir3_context *ctx)
1391 {
1392 if (!ctx->ij_centroid) {
1393 struct ir3_instruction *xy[2];
1394 struct ir3_instruction *ij;
1395
1396 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID, 0x3);
1397 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1398
1399 ctx->ij_centroid = ir3_create_collect(ctx, xy, 2);
1400 }
1401
1402 return ctx->ij_centroid;
1403 }
1404
1405 static struct ir3_instruction *
1406 get_barycentric_sample(struct ir3_context *ctx)
1407 {
1408 if (!ctx->ij_sample) {
1409 struct ir3_instruction *xy[2];
1410 struct ir3_instruction *ij;
1411
1412 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE, 0x3);
1413 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1414
1415 ctx->ij_sample = ir3_create_collect(ctx, xy, 2);
1416 }
1417
1418 return ctx->ij_sample;
1419 }
1420
1421 static struct ir3_instruction *
1422 get_barycentric_pixel(struct ir3_context *ctx)
1423 {
1424 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1425 * this to create ij_pixel only on demand:
1426 */
1427 return ctx->ij_pixel;
1428 }
1429
1430 static struct ir3_instruction *
1431 get_frag_coord(struct ir3_context *ctx)
1432 {
1433 if (!ctx->frag_coord) {
1434 struct ir3_block *b = ctx->in_block;
1435 struct ir3_instruction *xyzw[4];
1436 struct ir3_instruction *hw_frag_coord;
1437
1438 hw_frag_coord = create_sysval_input(ctx, SYSTEM_VALUE_FRAG_COORD, 0xf);
1439 ir3_split_dest(b, xyzw, hw_frag_coord, 0, 4);
1440
1441 /* for frag_coord.xy, we get unsigned values.. we need
1442 * to subtract (integer) 8 and divide by 16 (right-
1443 * shift by 4) then convert to float:
1444 *
1445 * sub.s tmp, src, 8
1446 * shr.b tmp, tmp, 4
1447 * mov.u32f32 dst, tmp
1448 *
1449 */
1450 for (int i = 0; i < 2; i++) {
1451 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1452 xyzw[i] = ir3_MUL_F(b, xyzw[i], 0, create_immed(b, fui(1.0 / 16.0)), 0);
1453 }
1454
1455 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1456 ctx->so->frag_coord = true;
1457 }
1458
1459 return ctx->frag_coord;
1460 }
1461
1462 static void
1463 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1464 {
1465 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1466 struct ir3_instruction **dst;
1467 struct ir3_instruction * const *src;
1468 struct ir3_block *b = ctx->block;
1469 int idx, comp;
1470
1471 if (info->has_dest) {
1472 unsigned n = nir_intrinsic_dest_components(intr);
1473 dst = ir3_get_dst(ctx, &intr->dest, n);
1474 } else {
1475 dst = NULL;
1476 }
1477
1478 const unsigned primitive_param = ctx->so->shader->const_state.offsets.primitive_param * 4;
1479 const unsigned primitive_map = ctx->so->shader->const_state.offsets.primitive_map * 4;
1480
1481 switch (intr->intrinsic) {
1482 case nir_intrinsic_load_uniform:
1483 idx = nir_intrinsic_base(intr);
1484 if (nir_src_is_const(intr->src[0])) {
1485 idx += nir_src_as_uint(intr->src[0]);
1486 for (int i = 0; i < intr->num_components; i++) {
1487 dst[i] = create_uniform_typed(b, idx + i,
1488 nir_dest_bit_size(intr->dest) < 32 ? TYPE_F16 : TYPE_F32);
1489 }
1490 } else {
1491 src = ir3_get_src(ctx, &intr->src[0]);
1492 for (int i = 0; i < intr->num_components; i++) {
1493 dst[i] = create_uniform_indirect(b, idx + i,
1494 ir3_get_addr0(ctx, src[0], 1));
1495 }
1496 /* NOTE: if relative addressing is used, we set
1497 * constlen in the compiler (to worst-case value)
1498 * since we don't know in the assembler what the max
1499 * addr reg value can be:
1500 */
1501 ctx->so->constlen = MAX2(ctx->so->constlen,
1502 ctx->so->shader->ubo_state.size / 16);
1503 }
1504 break;
1505
1506 case nir_intrinsic_load_vs_primitive_stride_ir3:
1507 dst[0] = create_uniform(b, primitive_param + 0);
1508 break;
1509 case nir_intrinsic_load_vs_vertex_stride_ir3:
1510 dst[0] = create_uniform(b, primitive_param + 1);
1511 break;
1512 case nir_intrinsic_load_hs_patch_stride_ir3:
1513 dst[0] = create_uniform(b, primitive_param + 2);
1514 break;
1515 case nir_intrinsic_load_patch_vertices_in:
1516 dst[0] = create_uniform(b, primitive_param + 3);
1517 break;
1518 case nir_intrinsic_load_tess_param_base_ir3:
1519 dst[0] = create_uniform(b, primitive_param + 4);
1520 dst[1] = create_uniform(b, primitive_param + 5);
1521 break;
1522 case nir_intrinsic_load_tess_factor_base_ir3:
1523 dst[0] = create_uniform(b, primitive_param + 6);
1524 dst[1] = create_uniform(b, primitive_param + 7);
1525 break;
1526
1527 case nir_intrinsic_load_primitive_location_ir3:
1528 idx = nir_intrinsic_driver_location(intr);
1529 dst[0] = create_uniform(b, primitive_map + idx);
1530 break;
1531
1532 case nir_intrinsic_load_gs_header_ir3:
1533 dst[0] = ctx->gs_header;
1534 break;
1535 case nir_intrinsic_load_tcs_header_ir3:
1536 dst[0] = ctx->tcs_header;
1537 break;
1538
1539 case nir_intrinsic_load_primitive_id:
1540 dst[0] = ctx->primitive_id;
1541 break;
1542
1543 case nir_intrinsic_load_tess_coord:
1544 if (!ctx->tess_coord) {
1545 ctx->tess_coord =
1546 create_sysval_input(ctx, SYSTEM_VALUE_TESS_COORD, 0x3);
1547 }
1548 ir3_split_dest(b, dst, ctx->tess_coord, 0, 2);
1549
1550 /* Unused, but ir3_put_dst() below wants to free something */
1551 dst[2] = create_immed(b, 0);
1552 break;
1553
1554 case nir_intrinsic_end_patch_ir3:
1555 assert(ctx->so->type == MESA_SHADER_TESS_CTRL);
1556 struct ir3_instruction *end = ir3_ENDIF(b);
1557 array_insert(b, b->keeps, end);
1558
1559 end->barrier_class = IR3_BARRIER_EVERYTHING;
1560 end->barrier_conflict = IR3_BARRIER_EVERYTHING;
1561 break;
1562
1563 case nir_intrinsic_store_global_ir3: {
1564 struct ir3_instruction *value, *addr, *offset;
1565
1566 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1567 ir3_get_src(ctx, &intr->src[1])[0],
1568 ir3_get_src(ctx, &intr->src[1])[1]
1569 }, 2);
1570
1571 offset = ir3_get_src(ctx, &intr->src[2])[0];
1572
1573 value = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]),
1574 intr->num_components);
1575
1576 struct ir3_instruction *stg =
1577 ir3_STG_G(ctx->block, addr, 0, value, 0,
1578 create_immed(ctx->block, intr->num_components), 0, offset, 0);
1579 stg->cat6.type = TYPE_U32;
1580 stg->cat6.iim_val = 1;
1581
1582 array_insert(b, b->keeps, stg);
1583
1584 stg->barrier_class = IR3_BARRIER_BUFFER_W;
1585 stg->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1586 break;
1587 }
1588
1589 case nir_intrinsic_load_global_ir3: {
1590 struct ir3_instruction *addr, *offset;
1591
1592 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1593 ir3_get_src(ctx, &intr->src[0])[0],
1594 ir3_get_src(ctx, &intr->src[0])[1]
1595 }, 2);
1596
1597 offset = ir3_get_src(ctx, &intr->src[1])[0];
1598
1599 struct ir3_instruction *load =
1600 ir3_LDG(b, addr, 0, create_immed(ctx->block, intr->num_components),
1601 0, offset, 0);
1602 load->cat6.type = TYPE_U32;
1603 load->regs[0]->wrmask = MASK(intr->num_components);
1604
1605 load->barrier_class = IR3_BARRIER_BUFFER_R;
1606 load->barrier_conflict = IR3_BARRIER_BUFFER_W;
1607
1608 ir3_split_dest(b, dst, load, 0, intr->num_components);
1609 break;
1610 }
1611
1612 case nir_intrinsic_load_ubo:
1613 emit_intrinsic_load_ubo(ctx, intr, dst);
1614 break;
1615 case nir_intrinsic_load_frag_coord:
1616 ir3_split_dest(b, dst, get_frag_coord(ctx), 0, 4);
1617 break;
1618 case nir_intrinsic_load_sample_pos_from_id: {
1619 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1620 * but that doesn't seem necessary.
1621 */
1622 struct ir3_instruction *offset =
1623 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1624 offset->regs[0]->wrmask = 0x3;
1625 offset->cat5.type = TYPE_F32;
1626
1627 ir3_split_dest(b, dst, offset, 0, 2);
1628
1629 break;
1630 }
1631 case nir_intrinsic_load_size_ir3:
1632 if (!ctx->ij_size) {
1633 ctx->ij_size =
1634 create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE, 0x1);
1635 }
1636 dst[0] = ctx->ij_size;
1637 break;
1638 case nir_intrinsic_load_barycentric_centroid:
1639 ir3_split_dest(b, dst, get_barycentric_centroid(ctx), 0, 2);
1640 break;
1641 case nir_intrinsic_load_barycentric_sample:
1642 if (ctx->so->key.msaa) {
1643 ir3_split_dest(b, dst, get_barycentric_sample(ctx), 0, 2);
1644 } else {
1645 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1646 }
1647 break;
1648 case nir_intrinsic_load_barycentric_pixel:
1649 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1650 break;
1651 case nir_intrinsic_load_interpolated_input:
1652 idx = nir_intrinsic_base(intr);
1653 comp = nir_intrinsic_component(intr);
1654 src = ir3_get_src(ctx, &intr->src[0]);
1655 if (nir_src_is_const(intr->src[1])) {
1656 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1657 idx += nir_src_as_uint(intr->src[1]);
1658 for (int i = 0; i < intr->num_components; i++) {
1659 unsigned inloc = idx * 4 + i + comp;
1660 if (ctx->so->inputs[idx].bary &&
1661 !ctx->so->inputs[idx].use_ldlv) {
1662 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1663 } else {
1664 /* for non-varyings use the pre-setup input, since
1665 * that is easier than mapping things back to a
1666 * nir_variable to figure out what it is.
1667 */
1668 dst[i] = ctx->inputs[inloc];
1669 compile_assert(ctx, dst[i]);
1670 }
1671 }
1672 } else {
1673 ir3_context_error(ctx, "unhandled");
1674 }
1675 break;
1676 case nir_intrinsic_load_input:
1677 idx = nir_intrinsic_base(intr);
1678 comp = nir_intrinsic_component(intr);
1679 if (nir_src_is_const(intr->src[0])) {
1680 idx += nir_src_as_uint(intr->src[0]);
1681 for (int i = 0; i < intr->num_components; i++) {
1682 unsigned n = idx * 4 + i + comp;
1683 dst[i] = ctx->inputs[n];
1684 compile_assert(ctx, ctx->inputs[n]);
1685 }
1686 } else {
1687 src = ir3_get_src(ctx, &intr->src[0]);
1688 struct ir3_instruction *collect =
1689 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ninputs);
1690 struct ir3_instruction *addr = ir3_get_addr0(ctx, src[0], 4);
1691 for (int i = 0; i < intr->num_components; i++) {
1692 unsigned n = idx * 4 + i + comp;
1693 dst[i] = create_indirect_load(ctx, ctx->ninputs,
1694 n, addr, collect);
1695 }
1696 }
1697 break;
1698 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1699 * pass and replaced by an ir3-specifc version that adds the
1700 * dword-offset in the last source.
1701 */
1702 case nir_intrinsic_load_ssbo_ir3:
1703 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1704 break;
1705 case nir_intrinsic_store_ssbo_ir3:
1706 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1707 !ctx->s->info.fs.early_fragment_tests)
1708 ctx->so->no_earlyz = true;
1709 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1710 break;
1711 case nir_intrinsic_get_buffer_size:
1712 emit_intrinsic_ssbo_size(ctx, intr, dst);
1713 break;
1714 case nir_intrinsic_ssbo_atomic_add_ir3:
1715 case nir_intrinsic_ssbo_atomic_imin_ir3:
1716 case nir_intrinsic_ssbo_atomic_umin_ir3:
1717 case nir_intrinsic_ssbo_atomic_imax_ir3:
1718 case nir_intrinsic_ssbo_atomic_umax_ir3:
1719 case nir_intrinsic_ssbo_atomic_and_ir3:
1720 case nir_intrinsic_ssbo_atomic_or_ir3:
1721 case nir_intrinsic_ssbo_atomic_xor_ir3:
1722 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1723 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1724 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1725 !ctx->s->info.fs.early_fragment_tests)
1726 ctx->so->no_earlyz = true;
1727 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1728 break;
1729 case nir_intrinsic_load_shared:
1730 emit_intrinsic_load_shared(ctx, intr, dst);
1731 break;
1732 case nir_intrinsic_store_shared:
1733 emit_intrinsic_store_shared(ctx, intr);
1734 break;
1735 case nir_intrinsic_shared_atomic_add:
1736 case nir_intrinsic_shared_atomic_imin:
1737 case nir_intrinsic_shared_atomic_umin:
1738 case nir_intrinsic_shared_atomic_imax:
1739 case nir_intrinsic_shared_atomic_umax:
1740 case nir_intrinsic_shared_atomic_and:
1741 case nir_intrinsic_shared_atomic_or:
1742 case nir_intrinsic_shared_atomic_xor:
1743 case nir_intrinsic_shared_atomic_exchange:
1744 case nir_intrinsic_shared_atomic_comp_swap:
1745 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1746 break;
1747 case nir_intrinsic_image_load:
1748 emit_intrinsic_load_image(ctx, intr, dst);
1749 break;
1750 case nir_intrinsic_bindless_image_load:
1751 /* Bindless uses the IBO state, which doesn't have swizzle filled out,
1752 * so using isam doesn't work.
1753 *
1754 * TODO: can we use isam if we fill out more fields?
1755 */
1756 ctx->funcs->emit_intrinsic_load_image(ctx, intr, dst);
1757 break;
1758 case nir_intrinsic_image_store:
1759 case nir_intrinsic_bindless_image_store:
1760 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1761 !ctx->s->info.fs.early_fragment_tests)
1762 ctx->so->no_earlyz = true;
1763 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1764 break;
1765 case nir_intrinsic_image_size:
1766 case nir_intrinsic_bindless_image_size:
1767 emit_intrinsic_image_size(ctx, intr, dst);
1768 break;
1769 case nir_intrinsic_image_atomic_add:
1770 case nir_intrinsic_bindless_image_atomic_add:
1771 case nir_intrinsic_image_atomic_imin:
1772 case nir_intrinsic_bindless_image_atomic_imin:
1773 case nir_intrinsic_image_atomic_umin:
1774 case nir_intrinsic_bindless_image_atomic_umin:
1775 case nir_intrinsic_image_atomic_imax:
1776 case nir_intrinsic_bindless_image_atomic_imax:
1777 case nir_intrinsic_image_atomic_umax:
1778 case nir_intrinsic_bindless_image_atomic_umax:
1779 case nir_intrinsic_image_atomic_and:
1780 case nir_intrinsic_bindless_image_atomic_and:
1781 case nir_intrinsic_image_atomic_or:
1782 case nir_intrinsic_bindless_image_atomic_or:
1783 case nir_intrinsic_image_atomic_xor:
1784 case nir_intrinsic_bindless_image_atomic_xor:
1785 case nir_intrinsic_image_atomic_exchange:
1786 case nir_intrinsic_bindless_image_atomic_exchange:
1787 case nir_intrinsic_image_atomic_comp_swap:
1788 case nir_intrinsic_bindless_image_atomic_comp_swap:
1789 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1790 !ctx->s->info.fs.early_fragment_tests)
1791 ctx->so->no_earlyz = true;
1792 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1793 break;
1794 case nir_intrinsic_control_barrier:
1795 case nir_intrinsic_memory_barrier:
1796 case nir_intrinsic_group_memory_barrier:
1797 case nir_intrinsic_memory_barrier_buffer:
1798 case nir_intrinsic_memory_barrier_image:
1799 case nir_intrinsic_memory_barrier_shared:
1800 emit_intrinsic_barrier(ctx, intr);
1801 /* note that blk ptr no longer valid, make that obvious: */
1802 b = NULL;
1803 break;
1804 case nir_intrinsic_store_output:
1805 idx = nir_intrinsic_base(intr);
1806 comp = nir_intrinsic_component(intr);
1807 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1808 idx += nir_src_as_uint(intr->src[1]);
1809
1810 src = ir3_get_src(ctx, &intr->src[0]);
1811 for (int i = 0; i < intr->num_components; i++) {
1812 unsigned n = idx * 4 + i + comp;
1813 ctx->outputs[n] = src[i];
1814 }
1815 break;
1816 case nir_intrinsic_load_base_vertex:
1817 case nir_intrinsic_load_first_vertex:
1818 if (!ctx->basevertex) {
1819 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1820 }
1821 dst[0] = ctx->basevertex;
1822 break;
1823 case nir_intrinsic_load_base_instance:
1824 if (!ctx->base_instance) {
1825 ctx->base_instance = create_driver_param(ctx, IR3_DP_INSTID_BASE);
1826 }
1827 dst[0] = ctx->base_instance;
1828 break;
1829 case nir_intrinsic_load_vertex_id_zero_base:
1830 case nir_intrinsic_load_vertex_id:
1831 if (!ctx->vertex_id) {
1832 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1833 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1834 ctx->vertex_id = create_sysval_input(ctx, sv, 0x1);
1835 }
1836 dst[0] = ctx->vertex_id;
1837 break;
1838 case nir_intrinsic_load_instance_id:
1839 if (!ctx->instance_id) {
1840 ctx->instance_id = create_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID, 0x1);
1841 }
1842 dst[0] = ctx->instance_id;
1843 break;
1844 case nir_intrinsic_load_sample_id:
1845 ctx->so->per_samp = true;
1846 /* fall-thru */
1847 case nir_intrinsic_load_sample_id_no_per_sample:
1848 if (!ctx->samp_id) {
1849 ctx->samp_id = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID, 0x1);
1850 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1851 }
1852 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1853 break;
1854 case nir_intrinsic_load_sample_mask_in:
1855 if (!ctx->samp_mask_in) {
1856 ctx->samp_mask_in = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN, 0x1);
1857 }
1858 dst[0] = ctx->samp_mask_in;
1859 break;
1860 case nir_intrinsic_load_user_clip_plane:
1861 idx = nir_intrinsic_ucp_id(intr);
1862 for (int i = 0; i < intr->num_components; i++) {
1863 unsigned n = idx * 4 + i;
1864 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1865 }
1866 break;
1867 case nir_intrinsic_load_front_face:
1868 if (!ctx->frag_face) {
1869 ctx->so->frag_face = true;
1870 ctx->frag_face = create_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, 0x1);
1871 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1872 }
1873 /* for fragface, we get -1 for back and 0 for front. However this is
1874 * the inverse of what nir expects (where ~0 is true).
1875 */
1876 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1877 dst[0] = ir3_NOT_B(b, dst[0], 0);
1878 break;
1879 case nir_intrinsic_load_local_invocation_id:
1880 if (!ctx->local_invocation_id) {
1881 ctx->local_invocation_id =
1882 create_sysval_input(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID, 0x7);
1883 }
1884 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1885 break;
1886 case nir_intrinsic_load_work_group_id:
1887 if (!ctx->work_group_id) {
1888 ctx->work_group_id =
1889 create_sysval_input(ctx, SYSTEM_VALUE_WORK_GROUP_ID, 0x7);
1890 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1891 }
1892 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1893 break;
1894 case nir_intrinsic_load_num_work_groups:
1895 for (int i = 0; i < intr->num_components; i++) {
1896 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1897 }
1898 break;
1899 case nir_intrinsic_load_local_group_size:
1900 for (int i = 0; i < intr->num_components; i++) {
1901 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1902 }
1903 break;
1904 case nir_intrinsic_discard_if:
1905 case nir_intrinsic_discard: {
1906 struct ir3_instruction *cond, *kill;
1907
1908 if (intr->intrinsic == nir_intrinsic_discard_if) {
1909 /* conditional discard: */
1910 src = ir3_get_src(ctx, &intr->src[0]);
1911 cond = ir3_b2n(b, src[0]);
1912 } else {
1913 /* unconditional discard: */
1914 cond = create_immed(b, 1);
1915 }
1916
1917 /* NOTE: only cmps.*.* can write p0.x: */
1918 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1919 cond->cat2.condition = IR3_COND_NE;
1920
1921 /* condition always goes in predicate register: */
1922 cond->regs[0]->num = regid(REG_P0, 0);
1923 cond->regs[0]->flags &= ~IR3_REG_SSA;
1924
1925 kill = ir3_KILL(b, cond, 0);
1926 kill->regs[1]->num = regid(REG_P0, 0);
1927 array_insert(ctx->ir, ctx->ir->predicates, kill);
1928
1929 array_insert(b, b->keeps, kill);
1930 ctx->so->no_earlyz = true;
1931
1932 break;
1933 }
1934
1935 case nir_intrinsic_cond_end_ir3: {
1936 struct ir3_instruction *cond, *kill;
1937
1938 src = ir3_get_src(ctx, &intr->src[0]);
1939 cond = ir3_b2n(b, src[0]);
1940
1941 /* NOTE: only cmps.*.* can write p0.x: */
1942 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1943 cond->cat2.condition = IR3_COND_NE;
1944
1945 /* condition always goes in predicate register: */
1946 cond->regs[0]->num = regid(REG_P0, 0);
1947
1948 kill = ir3_IF(b, cond, 0);
1949
1950 kill->barrier_class = IR3_BARRIER_EVERYTHING;
1951 kill->barrier_conflict = IR3_BARRIER_EVERYTHING;
1952
1953 array_insert(ctx->ir, ctx->ir->predicates, kill);
1954 array_insert(b, b->keeps, kill);
1955 break;
1956 }
1957
1958 case nir_intrinsic_load_shared_ir3:
1959 emit_intrinsic_load_shared_ir3(ctx, intr, dst);
1960 break;
1961 case nir_intrinsic_store_shared_ir3:
1962 emit_intrinsic_store_shared_ir3(ctx, intr);
1963 break;
1964 case nir_intrinsic_bindless_resource_ir3:
1965 dst[0] = ir3_get_src(ctx, &intr->src[0])[0];
1966 break;
1967 default:
1968 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1969 nir_intrinsic_infos[intr->intrinsic].name);
1970 break;
1971 }
1972
1973 if (info->has_dest)
1974 ir3_put_dst(ctx, &intr->dest);
1975 }
1976
1977 static void
1978 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1979 {
1980 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1981 instr->def.num_components);
1982
1983 if (instr->def.bit_size < 32) {
1984 for (int i = 0; i < instr->def.num_components; i++)
1985 dst[i] = create_immed_typed(ctx->block,
1986 instr->value[i].u16,
1987 TYPE_U16);
1988 } else {
1989 for (int i = 0; i < instr->def.num_components; i++)
1990 dst[i] = create_immed_typed(ctx->block,
1991 instr->value[i].u32,
1992 TYPE_U32);
1993 }
1994
1995 }
1996
1997 static void
1998 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1999 {
2000 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
2001 undef->def.num_components);
2002 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
2003
2004 /* backend doesn't want undefined instructions, so just plug
2005 * in 0.0..
2006 */
2007 for (int i = 0; i < undef->def.num_components; i++)
2008 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
2009 }
2010
2011 /*
2012 * texture fetch/sample instructions:
2013 */
2014
2015 static type_t
2016 get_tex_dest_type(nir_tex_instr *tex)
2017 {
2018 type_t type;
2019
2020 switch (nir_alu_type_get_base_type(tex->dest_type)) {
2021 case nir_type_invalid:
2022 case nir_type_float:
2023 type = nir_dest_bit_size(tex->dest) < 32 ? TYPE_F16 : TYPE_F32;
2024 break;
2025 case nir_type_int:
2026 type = nir_dest_bit_size(tex->dest) < 32 ? TYPE_S16 : TYPE_S32;
2027 break;
2028 case nir_type_uint:
2029 case nir_type_bool:
2030 type = nir_dest_bit_size(tex->dest) < 32 ? TYPE_U16 : TYPE_U32;
2031 break;
2032 default:
2033 unreachable("bad dest_type");
2034 }
2035
2036 return type;
2037 }
2038
2039 static void
2040 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
2041 {
2042 unsigned coords = glsl_get_sampler_dim_coordinate_components(tex->sampler_dim);
2043 unsigned flags = 0;
2044
2045 /* note: would use tex->coord_components.. except txs.. also,
2046 * since array index goes after shadow ref, we don't want to
2047 * count it:
2048 */
2049 if (coords == 3)
2050 flags |= IR3_INSTR_3D;
2051
2052 if (tex->is_shadow && tex->op != nir_texop_lod)
2053 flags |= IR3_INSTR_S;
2054
2055 if (tex->is_array && tex->op != nir_texop_lod)
2056 flags |= IR3_INSTR_A;
2057
2058 *flagsp = flags;
2059 *coordsp = coords;
2060 }
2061
2062 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
2063 * or immediate (in which case it will get lowered later to a non .s2en
2064 * version of the tex instruction which encode tex/samp as immediates:
2065 */
2066 static struct tex_src_info
2067 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
2068 {
2069 struct ir3_block *b = ctx->block;
2070 struct tex_src_info info = { 0 };
2071 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_handle);
2072 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_handle);
2073 struct ir3_instruction *texture, *sampler;
2074
2075 if (texture_idx >= 0 || sampler_idx >= 0) {
2076 /* Bindless case */
2077 info.flags |= IR3_INSTR_B;
2078
2079 /* Gather information required to determine which encoding to
2080 * choose as well as for prefetch.
2081 */
2082 nir_intrinsic_instr *bindless_tex = NULL;
2083 bool tex_const;
2084 if (texture_idx >= 0) {
2085 ctx->so->bindless_tex = true;
2086 bindless_tex = ir3_bindless_resource(tex->src[texture_idx].src);
2087 assert(bindless_tex);
2088 info.tex_base = nir_intrinsic_desc_set(bindless_tex);
2089 tex_const = nir_src_is_const(bindless_tex->src[0]);
2090 if (tex_const)
2091 info.tex_idx = nir_src_as_uint(bindless_tex->src[0]);
2092 } else {
2093 /* To simplify some of the logic below, assume the index is
2094 * constant 0 when it's not enabled.
2095 */
2096 tex_const = true;
2097 info.tex_idx = 0;
2098 }
2099 nir_intrinsic_instr *bindless_samp = NULL;
2100 bool samp_const;
2101 if (sampler_idx >= 0) {
2102 ctx->so->bindless_samp = true;
2103 bindless_samp = ir3_bindless_resource(tex->src[sampler_idx].src);
2104 assert(bindless_samp);
2105 info.samp_base = nir_intrinsic_desc_set(bindless_samp);
2106 samp_const = nir_src_is_const(bindless_samp->src[0]);
2107 if (samp_const)
2108 info.samp_idx = nir_src_as_uint(bindless_samp->src[0]);
2109 } else {
2110 samp_const = true;
2111 info.samp_idx = 0;
2112 }
2113
2114 /* Choose encoding. */
2115 if (tex_const && samp_const && info.tex_idx < 256 && info.samp_idx < 256) {
2116 if (info.tex_idx < 16 && info.samp_idx < 16 &&
2117 (!bindless_tex || !bindless_samp || info.tex_base == info.samp_base)) {
2118 /* Everything fits within the instruction */
2119 info.base = info.tex_base;
2120 info.combined_idx = info.samp_idx | (info.tex_idx << 4);
2121 } else {
2122 info.base = info.tex_base;
2123 info.a1_val = info.tex_idx << 3 | info.samp_base;
2124 info.combined_idx = info.samp_idx;
2125 info.flags |= IR3_INSTR_A1EN;
2126 }
2127 info.samp_tex = NULL;
2128 } else {
2129 info.flags |= IR3_INSTR_S2EN;
2130 /* In the indirect case, we only use a1.x to store the sampler
2131 * base if it differs from the texture base.
2132 */
2133 if (!bindless_tex || !bindless_samp || info.tex_base == info.samp_base) {
2134 info.base = info.tex_base;
2135 } else {
2136 info.base = info.tex_base;
2137 info.a1_val = info.samp_base;
2138 info.flags |= IR3_INSTR_A1EN;
2139 }
2140
2141 /* Note: the indirect source is now a vec2 instead of hvec2, and
2142 * for some reason the texture and sampler are swapped.
2143 */
2144 struct ir3_instruction *texture, *sampler;
2145
2146 if (bindless_tex) {
2147 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
2148 } else {
2149 texture = create_immed(b, 0);
2150 }
2151
2152 if (bindless_samp) {
2153 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
2154 } else {
2155 sampler = create_immed(b, 0);
2156 }
2157 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2158 texture,
2159 sampler,
2160 }, 2);
2161 }
2162 } else {
2163 info.flags |= IR3_INSTR_S2EN;
2164 texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
2165 sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
2166 if (texture_idx >= 0) {
2167 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
2168 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
2169 } else {
2170 /* TODO what to do for dynamic case? I guess we only need the
2171 * max index for astc srgb workaround so maybe not a problem
2172 * to worry about if we don't enable indirect samplers for
2173 * a4xx?
2174 */
2175 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
2176 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
2177 info.tex_idx = tex->texture_index;
2178 }
2179
2180 if (sampler_idx >= 0) {
2181 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
2182 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
2183 } else {
2184 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
2185 info.samp_idx = tex->texture_index;
2186 }
2187
2188 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2189 sampler,
2190 texture,
2191 }, 2);
2192 }
2193
2194 return info;
2195 }
2196
2197 static void
2198 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
2199 {
2200 struct ir3_block *b = ctx->block;
2201 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
2202 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
2203 struct ir3_instruction *lod, *compare, *proj, *sample_index;
2204 struct tex_src_info info = { 0 };
2205 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
2206 unsigned i, coords, flags, ncomp;
2207 unsigned nsrc0 = 0, nsrc1 = 0;
2208 type_t type;
2209 opc_t opc = 0;
2210
2211 ncomp = nir_dest_num_components(tex->dest);
2212
2213 coord = off = ddx = ddy = NULL;
2214 lod = proj = compare = sample_index = NULL;
2215
2216 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
2217
2218 for (unsigned i = 0; i < tex->num_srcs; i++) {
2219 switch (tex->src[i].src_type) {
2220 case nir_tex_src_coord:
2221 coord = ir3_get_src(ctx, &tex->src[i].src);
2222 break;
2223 case nir_tex_src_bias:
2224 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
2225 has_bias = true;
2226 break;
2227 case nir_tex_src_lod:
2228 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
2229 has_lod = true;
2230 break;
2231 case nir_tex_src_comparator: /* shadow comparator */
2232 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
2233 break;
2234 case nir_tex_src_projector:
2235 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
2236 has_proj = true;
2237 break;
2238 case nir_tex_src_offset:
2239 off = ir3_get_src(ctx, &tex->src[i].src);
2240 has_off = true;
2241 break;
2242 case nir_tex_src_ddx:
2243 ddx = ir3_get_src(ctx, &tex->src[i].src);
2244 break;
2245 case nir_tex_src_ddy:
2246 ddy = ir3_get_src(ctx, &tex->src[i].src);
2247 break;
2248 case nir_tex_src_ms_index:
2249 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
2250 break;
2251 case nir_tex_src_texture_offset:
2252 case nir_tex_src_sampler_offset:
2253 case nir_tex_src_texture_handle:
2254 case nir_tex_src_sampler_handle:
2255 /* handled in get_tex_samp_src() */
2256 break;
2257 default:
2258 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
2259 tex->src[i].src_type);
2260 return;
2261 }
2262 }
2263
2264 switch (tex->op) {
2265 case nir_texop_tex_prefetch:
2266 compile_assert(ctx, !has_bias);
2267 compile_assert(ctx, !has_lod);
2268 compile_assert(ctx, !compare);
2269 compile_assert(ctx, !has_proj);
2270 compile_assert(ctx, !has_off);
2271 compile_assert(ctx, !ddx);
2272 compile_assert(ctx, !ddy);
2273 compile_assert(ctx, !sample_index);
2274 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_texture_offset) < 0);
2275 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset) < 0);
2276
2277 if (ctx->so->num_sampler_prefetch < IR3_MAX_SAMPLER_PREFETCH) {
2278 opc = OPC_META_TEX_PREFETCH;
2279 ctx->so->num_sampler_prefetch++;
2280 break;
2281 }
2282 /* fallthru */
2283 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
2284 case nir_texop_txb: opc = OPC_SAMB; break;
2285 case nir_texop_txl: opc = OPC_SAML; break;
2286 case nir_texop_txd: opc = OPC_SAMGQ; break;
2287 case nir_texop_txf: opc = OPC_ISAML; break;
2288 case nir_texop_lod: opc = OPC_GETLOD; break;
2289 case nir_texop_tg4:
2290 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2291 * what blob does, seems gather is broken?), and a3xx did
2292 * not support it (but probably could also emulate).
2293 */
2294 switch (tex->component) {
2295 case 0: opc = OPC_GATHER4R; break;
2296 case 1: opc = OPC_GATHER4G; break;
2297 case 2: opc = OPC_GATHER4B; break;
2298 case 3: opc = OPC_GATHER4A; break;
2299 }
2300 break;
2301 case nir_texop_txf_ms_fb:
2302 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
2303 default:
2304 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
2305 return;
2306 }
2307
2308 tex_info(tex, &flags, &coords);
2309
2310 /*
2311 * lay out the first argument in the proper order:
2312 * - actual coordinates first
2313 * - shadow reference
2314 * - array index
2315 * - projection w
2316 * - starting at offset 4, dpdx.xy, dpdy.xy
2317 *
2318 * bias/lod go into the second arg
2319 */
2320
2321 /* insert tex coords: */
2322 for (i = 0; i < coords; i++)
2323 src0[i] = coord[i];
2324
2325 nsrc0 = i;
2326
2327 /* scale up integer coords for TXF based on the LOD */
2328 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
2329 assert(has_lod);
2330 for (i = 0; i < coords; i++)
2331 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
2332 }
2333
2334 if (coords == 1) {
2335 /* hw doesn't do 1d, so we treat it as 2d with
2336 * height of 1, and patch up the y coord.
2337 */
2338 if (is_isam(opc)) {
2339 src0[nsrc0++] = create_immed(b, 0);
2340 } else {
2341 src0[nsrc0++] = create_immed(b, fui(0.5));
2342 }
2343 }
2344
2345 if (tex->is_shadow && tex->op != nir_texop_lod)
2346 src0[nsrc0++] = compare;
2347
2348 if (tex->is_array && tex->op != nir_texop_lod) {
2349 struct ir3_instruction *idx = coord[coords];
2350
2351 /* the array coord for cube arrays needs 0.5 added to it */
2352 if (ctx->compiler->array_index_add_half && !is_isam(opc))
2353 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
2354
2355 src0[nsrc0++] = idx;
2356 }
2357
2358 if (has_proj) {
2359 src0[nsrc0++] = proj;
2360 flags |= IR3_INSTR_P;
2361 }
2362
2363 /* pad to 4, then ddx/ddy: */
2364 if (tex->op == nir_texop_txd) {
2365 while (nsrc0 < 4)
2366 src0[nsrc0++] = create_immed(b, fui(0.0));
2367 for (i = 0; i < coords; i++)
2368 src0[nsrc0++] = ddx[i];
2369 if (coords < 2)
2370 src0[nsrc0++] = create_immed(b, fui(0.0));
2371 for (i = 0; i < coords; i++)
2372 src0[nsrc0++] = ddy[i];
2373 if (coords < 2)
2374 src0[nsrc0++] = create_immed(b, fui(0.0));
2375 }
2376
2377 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2378 * with scaled x coord according to requested sample:
2379 */
2380 if (opc == OPC_ISAMM) {
2381 if (ctx->compiler->txf_ms_with_isaml) {
2382 /* the samples are laid out in x dimension as
2383 * 0 1 2 3
2384 * x_ms = (x << ms) + sample_index;
2385 */
2386 struct ir3_instruction *ms;
2387 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
2388
2389 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
2390 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
2391
2392 opc = OPC_ISAML;
2393 } else {
2394 src0[nsrc0++] = sample_index;
2395 }
2396 }
2397
2398 /*
2399 * second argument (if applicable):
2400 * - offsets
2401 * - lod
2402 * - bias
2403 */
2404 if (has_off | has_lod | has_bias) {
2405 if (has_off) {
2406 unsigned off_coords = coords;
2407 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2408 off_coords--;
2409 for (i = 0; i < off_coords; i++)
2410 src1[nsrc1++] = off[i];
2411 if (off_coords < 2)
2412 src1[nsrc1++] = create_immed(b, fui(0.0));
2413 flags |= IR3_INSTR_O;
2414 }
2415
2416 if (has_lod | has_bias)
2417 src1[nsrc1++] = lod;
2418 }
2419
2420 type = get_tex_dest_type(tex);
2421
2422 if (opc == OPC_GETLOD)
2423 type = TYPE_S32;
2424
2425
2426 if (tex->op == nir_texop_txf_ms_fb) {
2427 /* only expect a single txf_ms_fb per shader: */
2428 compile_assert(ctx, !ctx->so->fb_read);
2429 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
2430
2431 ctx->so->fb_read = true;
2432 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2433 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2434 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2435 }, 2);
2436 info.flags = IR3_INSTR_S2EN;
2437
2438 ctx->so->num_samp++;
2439 } else {
2440 info = get_tex_samp_tex_src(ctx, tex);
2441 }
2442
2443 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
2444 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
2445
2446 if (opc == OPC_META_TEX_PREFETCH) {
2447 int idx = nir_tex_instr_src_index(tex, nir_tex_src_coord);
2448
2449 compile_assert(ctx, tex->src[idx].src.is_ssa);
2450
2451 sam = ir3_META_TEX_PREFETCH(b);
2452 __ssa_dst(sam)->wrmask = MASK(ncomp); /* dst */
2453 __ssa_src(sam, get_barycentric_pixel(ctx), 0);
2454 sam->prefetch.input_offset =
2455 ir3_nir_coord_offset(tex->src[idx].src.ssa);
2456 /* make sure not to add irrelevant flags like S2EN */
2457 sam->flags = flags | (info.flags & IR3_INSTR_B);
2458 sam->prefetch.tex = info.tex_idx;
2459 sam->prefetch.samp = info.samp_idx;
2460 sam->prefetch.tex_base = info.tex_base;
2461 sam->prefetch.samp_base = info.samp_base;
2462 } else {
2463 info.flags |= flags;
2464 sam = emit_sam(ctx, opc, info, type, MASK(ncomp), col0, col1);
2465 }
2466
2467 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
2468 assert(opc != OPC_META_TEX_PREFETCH);
2469
2470 /* only need first 3 components: */
2471 sam->regs[0]->wrmask = 0x7;
2472 ir3_split_dest(b, dst, sam, 0, 3);
2473
2474 /* we need to sample the alpha separately with a non-ASTC
2475 * texture state:
2476 */
2477 sam = ir3_SAM(b, opc, type, 0b1000, flags | info.flags,
2478 info.samp_tex, col0, col1);
2479
2480 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
2481
2482 /* fixup .w component: */
2483 ir3_split_dest(b, &dst[3], sam, 3, 1);
2484 } else {
2485 /* normal (non-workaround) case: */
2486 ir3_split_dest(b, dst, sam, 0, ncomp);
2487 }
2488
2489 /* GETLOD returns results in 4.8 fixed point */
2490 if (opc == OPC_GETLOD) {
2491 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
2492
2493 compile_assert(ctx, tex->dest_type == nir_type_float);
2494 for (i = 0; i < 2; i++) {
2495 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_S32, TYPE_F32), 0,
2496 factor, 0);
2497 }
2498 }
2499
2500 ir3_put_dst(ctx, &tex->dest);
2501 }
2502
2503 static void
2504 emit_tex_info(struct ir3_context *ctx, nir_tex_instr *tex, unsigned idx)
2505 {
2506 struct ir3_block *b = ctx->block;
2507 struct ir3_instruction **dst, *sam;
2508 type_t dst_type = get_tex_dest_type(tex);
2509 struct tex_src_info info = get_tex_samp_tex_src(ctx, tex);
2510
2511 dst = ir3_get_dst(ctx, &tex->dest, 1);
2512
2513 sam = emit_sam(ctx, OPC_GETINFO, info, dst_type, 1 << idx, NULL, NULL);
2514
2515 /* even though there is only one component, since it ends
2516 * up in .y/.z/.w rather than .x, we need a split_dest()
2517 */
2518 if (idx)
2519 ir3_split_dest(b, dst, sam, 0, idx + 1);
2520
2521 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2522 * the value in TEX_CONST_0 is zero-based.
2523 */
2524 if (ctx->compiler->levels_add_one)
2525 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2526
2527 ir3_put_dst(ctx, &tex->dest);
2528 }
2529
2530 static void
2531 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2532 {
2533 struct ir3_block *b = ctx->block;
2534 struct ir3_instruction **dst, *sam;
2535 struct ir3_instruction *lod;
2536 unsigned flags, coords;
2537 type_t dst_type = get_tex_dest_type(tex);
2538 struct tex_src_info info = get_tex_samp_tex_src(ctx, tex);
2539
2540 tex_info(tex, &flags, &coords);
2541 info.flags |= flags;
2542
2543 /* Actually we want the number of dimensions, not coordinates. This
2544 * distinction only matters for cubes.
2545 */
2546 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2547 coords = 2;
2548
2549 dst = ir3_get_dst(ctx, &tex->dest, 4);
2550
2551 int lod_idx = nir_tex_instr_src_index(tex, nir_tex_src_lod);
2552 compile_assert(ctx, lod_idx >= 0);
2553
2554 lod = ir3_get_src(ctx, &tex->src[lod_idx].src)[0];
2555
2556 sam = emit_sam(ctx, OPC_GETSIZE, info, dst_type, 0b1111, lod, NULL);
2557 ir3_split_dest(b, dst, sam, 0, 4);
2558
2559 /* Array size actually ends up in .w rather than .z. This doesn't
2560 * matter for miplevel 0, but for higher mips the value in z is
2561 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2562 * returned, which means that we have to add 1 to it for arrays.
2563 */
2564 if (tex->is_array) {
2565 if (ctx->compiler->levels_add_one) {
2566 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2567 } else {
2568 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2569 }
2570 }
2571
2572 ir3_put_dst(ctx, &tex->dest);
2573 }
2574
2575 static void
2576 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2577 {
2578 switch (jump->type) {
2579 case nir_jump_break:
2580 case nir_jump_continue:
2581 case nir_jump_return:
2582 /* I *think* we can simply just ignore this, and use the
2583 * successor block link to figure out where we need to
2584 * jump to for break/continue
2585 */
2586 break;
2587 default:
2588 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2589 break;
2590 }
2591 }
2592
2593 static void
2594 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2595 {
2596 switch (instr->type) {
2597 case nir_instr_type_alu:
2598 emit_alu(ctx, nir_instr_as_alu(instr));
2599 break;
2600 case nir_instr_type_deref:
2601 /* ignored, handled as part of the intrinsic they are src to */
2602 break;
2603 case nir_instr_type_intrinsic:
2604 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2605 break;
2606 case nir_instr_type_load_const:
2607 emit_load_const(ctx, nir_instr_as_load_const(instr));
2608 break;
2609 case nir_instr_type_ssa_undef:
2610 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2611 break;
2612 case nir_instr_type_tex: {
2613 nir_tex_instr *tex = nir_instr_as_tex(instr);
2614 /* couple tex instructions get special-cased:
2615 */
2616 switch (tex->op) {
2617 case nir_texop_txs:
2618 emit_tex_txs(ctx, tex);
2619 break;
2620 case nir_texop_query_levels:
2621 emit_tex_info(ctx, tex, 2);
2622 break;
2623 case nir_texop_texture_samples:
2624 emit_tex_info(ctx, tex, 3);
2625 break;
2626 default:
2627 emit_tex(ctx, tex);
2628 break;
2629 }
2630 break;
2631 }
2632 case nir_instr_type_jump:
2633 emit_jump(ctx, nir_instr_as_jump(instr));
2634 break;
2635 case nir_instr_type_phi:
2636 /* we have converted phi webs to regs in NIR by now */
2637 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2638 break;
2639 case nir_instr_type_call:
2640 case nir_instr_type_parallel_copy:
2641 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2642 break;
2643 }
2644 }
2645
2646 static struct ir3_block *
2647 get_block(struct ir3_context *ctx, const nir_block *nblock)
2648 {
2649 struct ir3_block *block;
2650 struct hash_entry *hentry;
2651
2652 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2653 if (hentry)
2654 return hentry->data;
2655
2656 block = ir3_block_create(ctx->ir);
2657 block->nblock = nblock;
2658 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2659
2660 block->predecessors = _mesa_pointer_set_create(block);
2661 set_foreach(nblock->predecessors, sentry) {
2662 _mesa_set_add(block->predecessors, get_block(ctx, sentry->key));
2663 }
2664
2665 return block;
2666 }
2667
2668 static void
2669 emit_block(struct ir3_context *ctx, nir_block *nblock)
2670 {
2671 struct ir3_block *block = get_block(ctx, nblock);
2672
2673 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2674 if (nblock->successors[i]) {
2675 block->successors[i] =
2676 get_block(ctx, nblock->successors[i]);
2677 }
2678 }
2679
2680 ctx->block = block;
2681 list_addtail(&block->node, &ctx->ir->block_list);
2682
2683 /* re-emit addr register in each block if needed: */
2684 for (int i = 0; i < ARRAY_SIZE(ctx->addr0_ht); i++) {
2685 _mesa_hash_table_destroy(ctx->addr0_ht[i], NULL);
2686 ctx->addr0_ht[i] = NULL;
2687 }
2688
2689 _mesa_hash_table_u64_destroy(ctx->addr1_ht, NULL);
2690 ctx->addr1_ht = NULL;
2691
2692 nir_foreach_instr (instr, nblock) {
2693 ctx->cur_instr = instr;
2694 emit_instr(ctx, instr);
2695 ctx->cur_instr = NULL;
2696 if (ctx->error)
2697 return;
2698 }
2699
2700 _mesa_hash_table_clear(ctx->sel_cond_conversions, NULL);
2701 }
2702
2703 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2704
2705 static void
2706 emit_if(struct ir3_context *ctx, nir_if *nif)
2707 {
2708 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2709
2710 ctx->block->condition =
2711 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
2712
2713 emit_cf_list(ctx, &nif->then_list);
2714 emit_cf_list(ctx, &nif->else_list);
2715 }
2716
2717 static void
2718 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2719 {
2720 emit_cf_list(ctx, &nloop->body);
2721 ctx->so->loops++;
2722 }
2723
2724 static void
2725 stack_push(struct ir3_context *ctx)
2726 {
2727 ctx->stack++;
2728 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2729 }
2730
2731 static void
2732 stack_pop(struct ir3_context *ctx)
2733 {
2734 compile_assert(ctx, ctx->stack > 0);
2735 ctx->stack--;
2736 }
2737
2738 static void
2739 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2740 {
2741 foreach_list_typed (nir_cf_node, node, node, list) {
2742 switch (node->type) {
2743 case nir_cf_node_block:
2744 emit_block(ctx, nir_cf_node_as_block(node));
2745 break;
2746 case nir_cf_node_if:
2747 stack_push(ctx);
2748 emit_if(ctx, nir_cf_node_as_if(node));
2749 stack_pop(ctx);
2750 break;
2751 case nir_cf_node_loop:
2752 stack_push(ctx);
2753 emit_loop(ctx, nir_cf_node_as_loop(node));
2754 stack_pop(ctx);
2755 break;
2756 case nir_cf_node_function:
2757 ir3_context_error(ctx, "TODO\n");
2758 break;
2759 }
2760 }
2761 }
2762
2763 /* emit stream-out code. At this point, the current block is the original
2764 * (nir) end block, and nir ensures that all flow control paths terminate
2765 * into the end block. We re-purpose the original end block to generate
2766 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2767 * block holding stream-out write instructions, followed by the new end
2768 * block:
2769 *
2770 * blockOrigEnd {
2771 * p0.x = (vtxcnt < maxvtxcnt)
2772 * // succs: blockStreamOut, blockNewEnd
2773 * }
2774 * blockStreamOut {
2775 * ... stream-out instructions ...
2776 * // succs: blockNewEnd
2777 * }
2778 * blockNewEnd {
2779 * }
2780 */
2781 static void
2782 emit_stream_out(struct ir3_context *ctx)
2783 {
2784 struct ir3 *ir = ctx->ir;
2785 struct ir3_stream_output_info *strmout =
2786 &ctx->so->shader->stream_output;
2787 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2788 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2789 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2790
2791 /* create vtxcnt input in input block at top of shader,
2792 * so that it is seen as live over the entire duration
2793 * of the shader:
2794 */
2795 vtxcnt = create_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, 0x1);
2796 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2797
2798 /* at this point, we are at the original 'end' block,
2799 * re-purpose this block to stream-out condition, then
2800 * append stream-out block and new-end block
2801 */
2802 orig_end_block = ctx->block;
2803
2804 // TODO these blocks need to update predecessors..
2805 // maybe w/ store_global intrinsic, we could do this
2806 // stuff in nir->nir pass
2807
2808 stream_out_block = ir3_block_create(ir);
2809 list_addtail(&stream_out_block->node, &ir->block_list);
2810
2811 new_end_block = ir3_block_create(ir);
2812 list_addtail(&new_end_block->node, &ir->block_list);
2813
2814 orig_end_block->successors[0] = stream_out_block;
2815 orig_end_block->successors[1] = new_end_block;
2816 stream_out_block->successors[0] = new_end_block;
2817
2818 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2819 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2820 cond->regs[0]->num = regid(REG_P0, 0);
2821 cond->regs[0]->flags &= ~IR3_REG_SSA;
2822 cond->cat2.condition = IR3_COND_LT;
2823
2824 /* condition goes on previous block to the conditional,
2825 * since it is used to pick which of the two successor
2826 * paths to take:
2827 */
2828 orig_end_block->condition = cond;
2829
2830 /* switch to stream_out_block to generate the stream-out
2831 * instructions:
2832 */
2833 ctx->block = stream_out_block;
2834
2835 /* Calculate base addresses based on vtxcnt. Instructions
2836 * generated for bases not used in following loop will be
2837 * stripped out in the backend.
2838 */
2839 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2840 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
2841 unsigned stride = strmout->stride[i];
2842 struct ir3_instruction *base, *off;
2843
2844 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
2845
2846 /* 24-bit should be enough: */
2847 off = ir3_MUL_U24(ctx->block, vtxcnt, 0,
2848 create_immed(ctx->block, stride * 4), 0);
2849
2850 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2851 }
2852
2853 /* Generate the per-output store instructions: */
2854 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2855 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2856 unsigned c = j + strmout->output[i].start_component;
2857 struct ir3_instruction *base, *out, *stg;
2858
2859 base = bases[strmout->output[i].output_buffer];
2860 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2861
2862 stg = ir3_STG(ctx->block, base, 0, out, 0,
2863 create_immed(ctx->block, 1), 0);
2864 stg->cat6.type = TYPE_U32;
2865 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2866
2867 array_insert(ctx->block, ctx->block->keeps, stg);
2868 }
2869 }
2870
2871 /* and finally switch to the new_end_block: */
2872 ctx->block = new_end_block;
2873 }
2874
2875 static void
2876 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2877 {
2878 nir_metadata_require(impl, nir_metadata_block_index);
2879
2880 compile_assert(ctx, ctx->stack == 0);
2881
2882 emit_cf_list(ctx, &impl->body);
2883 emit_block(ctx, impl->end_block);
2884
2885 compile_assert(ctx, ctx->stack == 0);
2886
2887 /* at this point, we should have a single empty block,
2888 * into which we emit the 'end' instruction.
2889 */
2890 compile_assert(ctx, list_is_empty(&ctx->block->instr_list));
2891
2892 /* If stream-out (aka transform-feedback) enabled, emit the
2893 * stream-out instructions, followed by a new empty block (into
2894 * which the 'end' instruction lands).
2895 *
2896 * NOTE: it is done in this order, rather than inserting before
2897 * we emit end_block, because NIR guarantees that all blocks
2898 * flow into end_block, and that end_block has no successors.
2899 * So by re-purposing end_block as the first block of stream-
2900 * out, we guarantee that all exit paths flow into the stream-
2901 * out instructions.
2902 */
2903 if ((ctx->compiler->gpu_id < 500) &&
2904 (ctx->so->shader->stream_output.num_outputs > 0) &&
2905 !ctx->so->binning_pass) {
2906 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2907 emit_stream_out(ctx);
2908 }
2909
2910 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2911 * NOP and has an epilogue that writes the VS outputs to local storage, to
2912 * be read by the HS. Then it resets execution mask (chmask) and chains
2913 * to the next shader (chsh).
2914 */
2915 if ((ctx->so->type == MESA_SHADER_VERTEX &&
2916 (ctx->so->key.has_gs || ctx->so->key.tessellation)) ||
2917 (ctx->so->type == MESA_SHADER_TESS_EVAL && ctx->so->key.has_gs)) {
2918 struct ir3_instruction *chmask =
2919 ir3_CHMASK(ctx->block);
2920 chmask->barrier_class = IR3_BARRIER_EVERYTHING;
2921 chmask->barrier_conflict = IR3_BARRIER_EVERYTHING;
2922
2923 struct ir3_instruction *chsh =
2924 ir3_CHSH(ctx->block);
2925 chsh->barrier_class = IR3_BARRIER_EVERYTHING;
2926 chsh->barrier_conflict = IR3_BARRIER_EVERYTHING;
2927 } else {
2928 ir3_END(ctx->block);
2929 }
2930 }
2931
2932 static void
2933 setup_input(struct ir3_context *ctx, nir_variable *in)
2934 {
2935 struct ir3_shader_variant *so = ctx->so;
2936 unsigned ncomp = glsl_get_components(in->type);
2937 unsigned n = in->data.driver_location;
2938 unsigned frac = in->data.location_frac;
2939 unsigned slot = in->data.location;
2940
2941 /* Inputs are loaded using ldlw or ldg for these stages. */
2942 if (ctx->so->type == MESA_SHADER_TESS_CTRL ||
2943 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2944 ctx->so->type == MESA_SHADER_GEOMETRY)
2945 return;
2946
2947 /* skip unread inputs, we could end up with (for example), unsplit
2948 * matrix/etc inputs in the case they are not read, so just silently
2949 * skip these.
2950 */
2951 if (ncomp > 4)
2952 return;
2953
2954 so->inputs[n].slot = slot;
2955 so->inputs[n].compmask |= (1 << (ncomp + frac)) - 1;
2956 so->inputs_count = MAX2(so->inputs_count, n + 1);
2957 so->inputs[n].interpolate = in->data.interpolation;
2958
2959 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2960
2961 /* if any varyings have 'sample' qualifer, that triggers us
2962 * to run in per-sample mode:
2963 */
2964 so->per_samp |= in->data.sample;
2965
2966 for (int i = 0; i < ncomp; i++) {
2967 struct ir3_instruction *instr = NULL;
2968 unsigned idx = (n * 4) + i + frac;
2969
2970 if (slot == VARYING_SLOT_POS) {
2971 ir3_context_error(ctx, "fragcoord should be a sysval!\n");
2972 } else if (slot == VARYING_SLOT_PNTC) {
2973 /* see for example st_nir_fixup_varying_slots().. this is
2974 * maybe a bit mesa/st specific. But we need things to line
2975 * up for this in fdN_program:
2976 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2977 * if (emit->sprite_coord_enable & texmask) {
2978 * ...
2979 * }
2980 */
2981 so->inputs[n].slot = VARYING_SLOT_VAR8;
2982 so->inputs[n].bary = true;
2983 instr = create_frag_input(ctx, false, idx);
2984 } else {
2985 /* detect the special case for front/back colors where
2986 * we need to do flat vs smooth shading depending on
2987 * rast state:
2988 */
2989 if (in->data.interpolation == INTERP_MODE_NONE) {
2990 switch (slot) {
2991 case VARYING_SLOT_COL0:
2992 case VARYING_SLOT_COL1:
2993 case VARYING_SLOT_BFC0:
2994 case VARYING_SLOT_BFC1:
2995 so->inputs[n].rasterflat = true;
2996 break;
2997 default:
2998 break;
2999 }
3000 }
3001
3002 if (ctx->compiler->flat_bypass) {
3003 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
3004 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
3005 so->inputs[n].use_ldlv = true;
3006 }
3007
3008 so->inputs[n].bary = true;
3009
3010 instr = create_frag_input(ctx, so->inputs[n].use_ldlv, idx);
3011 }
3012
3013 compile_assert(ctx, idx < ctx->ninputs);
3014
3015 ctx->inputs[idx] = instr;
3016 }
3017 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
3018 struct ir3_instruction *input = NULL, *in;
3019 struct ir3_instruction *components[4];
3020 unsigned mask = (1 << (ncomp + frac)) - 1;
3021
3022 foreach_input (in, ctx->ir) {
3023 if (in->input.inidx == n) {
3024 input = in;
3025 break;
3026 }
3027 }
3028
3029 if (!input) {
3030 input = create_input(ctx, mask);
3031 input->input.inidx = n;
3032 } else {
3033 input->regs[0]->wrmask |= mask;
3034 }
3035
3036 ir3_split_dest(ctx->block, components, input, frac, ncomp);
3037
3038 for (int i = 0; i < ncomp; i++) {
3039 unsigned idx = (n * 4) + i + frac;
3040 compile_assert(ctx, idx < ctx->ninputs);
3041 ctx->inputs[idx] = components[i];
3042 }
3043 } else {
3044 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
3045 }
3046
3047 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
3048 so->total_in += ncomp;
3049 }
3050 }
3051
3052 /* Initially we assign non-packed inloc's for varyings, as we don't really
3053 * know up-front which components will be unused. After all the compilation
3054 * stages we scan the shader to see which components are actually used, and
3055 * re-pack the inlocs to eliminate unneeded varyings.
3056 */
3057 static void
3058 pack_inlocs(struct ir3_context *ctx)
3059 {
3060 struct ir3_shader_variant *so = ctx->so;
3061 uint8_t used_components[so->inputs_count];
3062
3063 memset(used_components, 0, sizeof(used_components));
3064
3065 /*
3066 * First Step: scan shader to find which bary.f/ldlv remain:
3067 */
3068
3069 foreach_block (block, &ctx->ir->block_list) {
3070 foreach_instr (instr, &block->instr_list) {
3071 if (is_input(instr)) {
3072 unsigned inloc = instr->regs[1]->iim_val;
3073 unsigned i = inloc / 4;
3074 unsigned j = inloc % 4;
3075
3076 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
3077 compile_assert(ctx, i < so->inputs_count);
3078
3079 used_components[i] |= 1 << j;
3080 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
3081 for (int n = 0; n < 2; n++) {
3082 unsigned inloc = instr->prefetch.input_offset + n;
3083 unsigned i = inloc / 4;
3084 unsigned j = inloc % 4;
3085
3086 compile_assert(ctx, i < so->inputs_count);
3087
3088 used_components[i] |= 1 << j;
3089 }
3090 }
3091 }
3092 }
3093
3094 /*
3095 * Second Step: reassign varying inloc/slots:
3096 */
3097
3098 unsigned actual_in = 0;
3099 unsigned inloc = 0;
3100
3101 for (unsigned i = 0; i < so->inputs_count; i++) {
3102 unsigned compmask = 0, maxcomp = 0;
3103
3104 so->inputs[i].inloc = inloc;
3105 so->inputs[i].bary = false;
3106
3107 for (unsigned j = 0; j < 4; j++) {
3108 if (!(used_components[i] & (1 << j)))
3109 continue;
3110
3111 compmask |= (1 << j);
3112 actual_in++;
3113 maxcomp = j + 1;
3114
3115 /* at this point, since used_components[i] mask is only
3116 * considering varyings (ie. not sysvals) we know this
3117 * is a varying:
3118 */
3119 so->inputs[i].bary = true;
3120 }
3121
3122 if (so->inputs[i].bary) {
3123 so->varying_in++;
3124 so->inputs[i].compmask = (1 << maxcomp) - 1;
3125 inloc += maxcomp;
3126 }
3127 }
3128
3129 /*
3130 * Third Step: reassign packed inloc's:
3131 */
3132
3133 foreach_block (block, &ctx->ir->block_list) {
3134 foreach_instr (instr, &block->instr_list) {
3135 if (is_input(instr)) {
3136 unsigned inloc = instr->regs[1]->iim_val;
3137 unsigned i = inloc / 4;
3138 unsigned j = inloc % 4;
3139
3140 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
3141 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
3142 unsigned i = instr->prefetch.input_offset / 4;
3143 unsigned j = instr->prefetch.input_offset % 4;
3144 instr->prefetch.input_offset = so->inputs[i].inloc + j;
3145 }
3146 }
3147 }
3148 }
3149
3150 static void
3151 setup_output(struct ir3_context *ctx, nir_variable *out)
3152 {
3153 struct ir3_shader_variant *so = ctx->so;
3154 unsigned ncomp = glsl_get_components(out->type);
3155 unsigned n = out->data.driver_location;
3156 unsigned frac = out->data.location_frac;
3157 unsigned slot = out->data.location;
3158 unsigned comp = 0;
3159
3160 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3161 switch (slot) {
3162 case FRAG_RESULT_DEPTH:
3163 comp = 2; /* tgsi will write to .z component */
3164 so->writes_pos = true;
3165 break;
3166 case FRAG_RESULT_COLOR:
3167 so->color0_mrt = 1;
3168 break;
3169 case FRAG_RESULT_SAMPLE_MASK:
3170 so->writes_smask = true;
3171 break;
3172 default:
3173 if (slot >= FRAG_RESULT_DATA0)
3174 break;
3175 ir3_context_error(ctx, "unknown FS output name: %s\n",
3176 gl_frag_result_name(slot));
3177 }
3178 } else if (ctx->so->type == MESA_SHADER_VERTEX ||
3179 ctx->so->type == MESA_SHADER_TESS_EVAL ||
3180 ctx->so->type == MESA_SHADER_GEOMETRY) {
3181 switch (slot) {
3182 case VARYING_SLOT_POS:
3183 so->writes_pos = true;
3184 break;
3185 case VARYING_SLOT_PSIZ:
3186 so->writes_psize = true;
3187 break;
3188 case VARYING_SLOT_PRIMITIVE_ID:
3189 case VARYING_SLOT_LAYER:
3190 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
3191 debug_assert(ctx->so->type == MESA_SHADER_GEOMETRY);
3192 /* fall through */
3193 case VARYING_SLOT_COL0:
3194 case VARYING_SLOT_COL1:
3195 case VARYING_SLOT_BFC0:
3196 case VARYING_SLOT_BFC1:
3197 case VARYING_SLOT_FOGC:
3198 case VARYING_SLOT_CLIP_DIST0:
3199 case VARYING_SLOT_CLIP_DIST1:
3200 case VARYING_SLOT_CLIP_VERTEX:
3201 break;
3202 default:
3203 if (slot >= VARYING_SLOT_VAR0)
3204 break;
3205 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
3206 break;
3207 ir3_context_error(ctx, "unknown %s shader output name: %s\n",
3208 _mesa_shader_stage_to_string(ctx->so->type),
3209 gl_varying_slot_name(slot));
3210 }
3211 } else if (ctx->so->type == MESA_SHADER_TESS_CTRL) {
3212 /* output lowered to buffer writes. */
3213 return;
3214 } else {
3215 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
3216 }
3217
3218 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
3219
3220 so->outputs[n].slot = slot;
3221 so->outputs[n].regid = regid(n, comp);
3222 so->outputs_count = MAX2(so->outputs_count, n + 1);
3223
3224 for (int i = 0; i < ncomp; i++) {
3225 unsigned idx = (n * 4) + i + frac;
3226 compile_assert(ctx, idx < ctx->noutputs);
3227 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
3228 }
3229
3230 /* if varying packing doesn't happen, we could end up in a situation
3231 * with "holes" in the output, and since the per-generation code that
3232 * sets up varying linkage registers doesn't expect to have more than
3233 * one varying per vec4 slot, pad the holes.
3234 *
3235 * Note that this should probably generate a performance warning of
3236 * some sort.
3237 */
3238 for (int i = 0; i < frac; i++) {
3239 unsigned idx = (n * 4) + i;
3240 if (!ctx->outputs[idx]) {
3241 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
3242 }
3243 }
3244 }
3245
3246 static int
3247 max_drvloc(struct exec_list *vars)
3248 {
3249 int drvloc = -1;
3250 nir_foreach_variable (var, vars) {
3251 drvloc = MAX2(drvloc, (int)var->data.driver_location);
3252 }
3253 return drvloc;
3254 }
3255
3256 static void
3257 emit_instructions(struct ir3_context *ctx)
3258 {
3259 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
3260
3261 ctx->ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4;
3262 ctx->noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4;
3263
3264 ctx->inputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->ninputs);
3265 ctx->outputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->noutputs);
3266
3267 ctx->ir = ir3_create(ctx->compiler, ctx->so->type);
3268
3269 /* Create inputs in first block: */
3270 ctx->block = get_block(ctx, nir_start_block(fxn));
3271 ctx->in_block = ctx->block;
3272 list_addtail(&ctx->block->node, &ctx->ir->block_list);
3273
3274 /* for fragment shader, the vcoord input register is used as the
3275 * base for bary.f varying fetch instrs:
3276 *
3277 * TODO defer creating ctx->ij_pixel and corresponding sysvals
3278 * until emit_intrinsic when we know they are actually needed.
3279 * For now, we defer creating ctx->ij_centroid, etc, since we
3280 * only need ij_pixel for "old style" varying inputs (ie.
3281 * tgsi_to_nir)
3282 */
3283 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3284 ctx->ij_pixel = create_input(ctx, 0x3);
3285 }
3286
3287 /* Setup inputs: */
3288 nir_foreach_variable (var, &ctx->s->inputs) {
3289 setup_input(ctx, var);
3290 }
3291
3292 /* Defer add_sysval_input() stuff until after setup_inputs(),
3293 * because sysvals need to be appended after varyings:
3294 */
3295 if (ctx->ij_pixel) {
3296 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL,
3297 0x3, ctx->ij_pixel);
3298 }
3299
3300
3301 /* Tesselation shaders always need primitive ID for indexing the
3302 * BO. Geometry shaders don't always need it but when they do it has be
3303 * delivered and unclobbered in the VS. To make things easy, we always
3304 * make room for it in VS/DS.
3305 */
3306 bool has_tess = ctx->so->key.tessellation != IR3_TESS_NONE;
3307 bool has_gs = ctx->so->key.has_gs;
3308 switch (ctx->so->type) {
3309 case MESA_SHADER_VERTEX:
3310 if (has_tess) {
3311 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3312 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3313 } else if (has_gs) {
3314 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3315 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3316 }
3317 break;
3318 case MESA_SHADER_TESS_CTRL:
3319 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3320 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3321 break;
3322 case MESA_SHADER_TESS_EVAL:
3323 if (has_gs)
3324 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3325 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3326 break;
3327 case MESA_SHADER_GEOMETRY:
3328 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3329 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3330 break;
3331 default:
3332 break;
3333 }
3334
3335 /* Setup outputs: */
3336 nir_foreach_variable (var, &ctx->s->outputs) {
3337 setup_output(ctx, var);
3338 }
3339
3340 /* Find # of samplers: */
3341 nir_foreach_variable (var, &ctx->s->uniforms) {
3342 ctx->so->num_samp += glsl_type_get_sampler_count(var->type);
3343 /* just assume that we'll be reading from images.. if it
3344 * is write-only we don't have to count it, but not sure
3345 * if there is a good way to know?
3346 */
3347 ctx->so->num_samp += glsl_type_get_image_count(var->type);
3348 }
3349
3350 /* NOTE: need to do something more clever when we support >1 fxn */
3351 nir_foreach_register (reg, &fxn->registers) {
3352 ir3_declare_array(ctx, reg);
3353 }
3354 /* And emit the body: */
3355 ctx->impl = fxn;
3356 emit_function(ctx, fxn);
3357 }
3358
3359 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3360 * need to assign the tex state indexes for these after we know the
3361 * max tex index.
3362 */
3363 static void
3364 fixup_astc_srgb(struct ir3_context *ctx)
3365 {
3366 struct ir3_shader_variant *so = ctx->so;
3367 /* indexed by original tex idx, value is newly assigned alpha sampler
3368 * state tex idx. Zero is invalid since there is at least one sampler
3369 * if we get here.
3370 */
3371 unsigned alt_tex_state[16] = {0};
3372 unsigned tex_idx = ctx->max_texture_index + 1;
3373 unsigned idx = 0;
3374
3375 so->astc_srgb.base = tex_idx;
3376
3377 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
3378 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
3379
3380 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
3381
3382 if (alt_tex_state[sam->cat5.tex] == 0) {
3383 /* assign new alternate/alpha tex state slot: */
3384 alt_tex_state[sam->cat5.tex] = tex_idx++;
3385 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
3386 so->astc_srgb.count++;
3387 }
3388
3389 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
3390 }
3391 }
3392
3393 static void
3394 fixup_binning_pass(struct ir3_context *ctx)
3395 {
3396 struct ir3_shader_variant *so = ctx->so;
3397 struct ir3 *ir = ctx->ir;
3398 unsigned i, j;
3399
3400 /* first pass, remove unused outputs from the IR level outputs: */
3401 for (i = 0, j = 0; i < ir->outputs_count; i++) {
3402 struct ir3_instruction *out = ir->outputs[i];
3403 assert(out->opc == OPC_META_COLLECT);
3404 unsigned outidx = out->collect.outidx;
3405 unsigned slot = so->outputs[outidx].slot;
3406
3407 /* throw away everything but first position/psize */
3408 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3409 ir->outputs[j] = ir->outputs[i];
3410 j++;
3411 }
3412 }
3413 ir->outputs_count = j;
3414
3415 /* second pass, cleanup the unused slots in ir3_shader_variant::outputs
3416 * table:
3417 */
3418 for (i = 0, j = 0; i < so->outputs_count; i++) {
3419 unsigned slot = so->outputs[i].slot;
3420
3421 /* throw away everything but first position/psize */
3422 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3423 so->outputs[j] = so->outputs[i];
3424
3425 /* fixup outidx to point to new output table entry: */
3426 struct ir3_instruction *out;
3427 foreach_output (out, ir) {
3428 if (out->collect.outidx == i) {
3429 out->collect.outidx = j;
3430 break;
3431 }
3432 }
3433
3434 j++;
3435 }
3436 }
3437 so->outputs_count = j;
3438 }
3439
3440 static void
3441 collect_tex_prefetches(struct ir3_context *ctx, struct ir3 *ir)
3442 {
3443 unsigned idx = 0;
3444
3445 /* Collect sampling instructions eligible for pre-dispatch. */
3446 foreach_block (block, &ir->block_list) {
3447 foreach_instr_safe (instr, &block->instr_list) {
3448 if (instr->opc == OPC_META_TEX_PREFETCH) {
3449 assert(idx < ARRAY_SIZE(ctx->so->sampler_prefetch));
3450 struct ir3_sampler_prefetch *fetch =
3451 &ctx->so->sampler_prefetch[idx];
3452 idx++;
3453
3454 if (instr->flags & IR3_INSTR_B) {
3455 fetch->cmd = IR3_SAMPLER_BINDLESS_PREFETCH_CMD;
3456 /* In bindless mode, the index is actually the base */
3457 fetch->tex_id = instr->prefetch.tex_base;
3458 fetch->samp_id = instr->prefetch.samp_base;
3459 fetch->tex_bindless_id = instr->prefetch.tex;
3460 fetch->samp_bindless_id = instr->prefetch.samp;
3461 } else {
3462 fetch->cmd = IR3_SAMPLER_PREFETCH_CMD;
3463 fetch->tex_id = instr->prefetch.tex;
3464 fetch->samp_id = instr->prefetch.samp;
3465 }
3466 fetch->wrmask = instr->regs[0]->wrmask;
3467 fetch->dst = instr->regs[0]->num;
3468 fetch->src = instr->prefetch.input_offset;
3469
3470 ctx->so->total_in =
3471 MAX2(ctx->so->total_in, instr->prefetch.input_offset + 2);
3472
3473 /* Disable half precision until supported. */
3474 fetch->half_precision = !!(instr->regs[0]->flags & IR3_REG_HALF);
3475
3476 /* Remove the prefetch placeholder instruction: */
3477 list_delinit(&instr->node);
3478 }
3479 }
3480 }
3481 }
3482
3483 int
3484 ir3_compile_shader_nir(struct ir3_compiler *compiler,
3485 struct ir3_shader_variant *so)
3486 {
3487 struct ir3_context *ctx;
3488 struct ir3 *ir;
3489 int ret = 0, max_bary;
3490
3491 assert(!so->ir);
3492
3493 ctx = ir3_context_init(compiler, so);
3494 if (!ctx) {
3495 DBG("INIT failed!");
3496 ret = -1;
3497 goto out;
3498 }
3499
3500 emit_instructions(ctx);
3501
3502 if (ctx->error) {
3503 DBG("EMIT failed!");
3504 ret = -1;
3505 goto out;
3506 }
3507
3508 ir = so->ir = ctx->ir;
3509
3510 assert((ctx->noutputs % 4) == 0);
3511
3512 /* Setup IR level outputs, which are "collects" that gather
3513 * the scalar components of outputs.
3514 */
3515 for (unsigned i = 0; i < ctx->noutputs; i += 4) {
3516 unsigned ncomp = 0;
3517 /* figure out the # of components written:
3518 *
3519 * TODO do we need to handle holes, ie. if .x and .z
3520 * components written, but .y component not written?
3521 */
3522 for (unsigned j = 0; j < 4; j++) {
3523 if (!ctx->outputs[i + j])
3524 break;
3525 ncomp++;
3526 }
3527
3528 /* Note that in some stages, like TCS, store_output is
3529 * lowered to memory writes, so no components of the
3530 * are "written" from the PoV of traditional store-
3531 * output instructions:
3532 */
3533 if (!ncomp)
3534 continue;
3535
3536 struct ir3_instruction *out =
3537 ir3_create_collect(ctx, &ctx->outputs[i], ncomp);
3538
3539 int outidx = i / 4;
3540 assert(outidx < so->outputs_count);
3541
3542 /* stash index into so->outputs[] so we can map the
3543 * output back to slot/etc later:
3544 */
3545 out->collect.outidx = outidx;
3546
3547 array_insert(ir, ir->outputs, out);
3548 }
3549
3550 /* Set up the gs header as an output for the vertex shader so it won't
3551 * clobber it for the tess ctrl shader.
3552 *
3553 * TODO this could probably be done more cleanly in a nir pass.
3554 */
3555 if (ctx->so->type == MESA_SHADER_VERTEX ||
3556 (ctx->so->key.has_gs && ctx->so->type == MESA_SHADER_TESS_EVAL)) {
3557 if (ctx->primitive_id) {
3558 unsigned n = so->outputs_count++;
3559 so->outputs[n].slot = VARYING_SLOT_PRIMITIVE_ID;
3560
3561 struct ir3_instruction *out =
3562 ir3_create_collect(ctx, &ctx->primitive_id, 1);
3563 out->collect.outidx = n;
3564 array_insert(ir, ir->outputs, out);
3565 }
3566
3567 if (ctx->gs_header) {
3568 unsigned n = so->outputs_count++;
3569 so->outputs[n].slot = VARYING_SLOT_GS_HEADER_IR3;
3570 struct ir3_instruction *out =
3571 ir3_create_collect(ctx, &ctx->gs_header, 1);
3572 out->collect.outidx = n;
3573 array_insert(ir, ir->outputs, out);
3574 }
3575
3576 if (ctx->tcs_header) {
3577 unsigned n = so->outputs_count++;
3578 so->outputs[n].slot = VARYING_SLOT_TCS_HEADER_IR3;
3579 struct ir3_instruction *out =
3580 ir3_create_collect(ctx, &ctx->tcs_header, 1);
3581 out->collect.outidx = n;
3582 array_insert(ir, ir->outputs, out);
3583 }
3584 }
3585
3586 /* at this point, for binning pass, throw away unneeded outputs: */
3587 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
3588 fixup_binning_pass(ctx);
3589
3590 ir3_debug_print(ir, "BEFORE CF");
3591
3592 ir3_cf(ir);
3593
3594 ir3_debug_print(ir, "BEFORE CP");
3595
3596 ir3_cp(ir, so);
3597
3598 /* at this point, for binning pass, throw away unneeded outputs:
3599 * Note that for a6xx and later, we do this after ir3_cp to ensure
3600 * that the uniform/constant layout for BS and VS matches, so that
3601 * we can re-use same VS_CONST state group.
3602 */
3603 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
3604 fixup_binning_pass(ctx);
3605
3606 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3607 * need to make sure not to remove any inputs that are used by
3608 * the nonbinning VS.
3609 */
3610 if (ctx->compiler->gpu_id >= 600 && so->binning_pass &&
3611 so->type == MESA_SHADER_VERTEX) {
3612 for (int i = 0; i < ctx->ninputs; i++) {
3613 struct ir3_instruction *in = ctx->inputs[i];
3614
3615 if (!in)
3616 continue;
3617
3618 unsigned n = i / 4;
3619 unsigned c = i % 4;
3620
3621 debug_assert(n < so->nonbinning->inputs_count);
3622
3623 if (so->nonbinning->inputs[n].sysval)
3624 continue;
3625
3626 /* be sure to keep inputs, even if only used in VS */
3627 if (so->nonbinning->inputs[n].compmask & (1 << c))
3628 array_insert(in->block, in->block->keeps, in);
3629 }
3630 }
3631
3632 ir3_debug_print(ir, "BEFORE GROUPING");
3633
3634 ir3_sched_add_deps(ir);
3635
3636 /* Group left/right neighbors, inserting mov's where needed to
3637 * solve conflicts:
3638 */
3639 ir3_group(ir);
3640
3641 ir3_debug_print(ir, "AFTER GROUPING");
3642
3643 ir3_dce(ir, so);
3644
3645 ir3_debug_print(ir, "AFTER DCE");
3646
3647 /* do Sethi–Ullman numbering before scheduling: */
3648 ir3_sun(ir);
3649
3650 ret = ir3_sched(ir);
3651 if (ret) {
3652 DBG("SCHED failed!");
3653 goto out;
3654 }
3655
3656 ir3_debug_print(ir, "AFTER SCHED");
3657
3658 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3659 * with draw pass VS, so binning and draw pass can both use the
3660 * same VBO state.
3661 *
3662 * Note that VS inputs are expected to be full precision.
3663 */
3664 bool pre_assign_inputs = (ir->compiler->gpu_id >= 600) &&
3665 (ir->type == MESA_SHADER_VERTEX) &&
3666 so->binning_pass;
3667
3668 if (pre_assign_inputs) {
3669 for (unsigned i = 0; i < ctx->ninputs; i++) {
3670 struct ir3_instruction *instr = ctx->inputs[i];
3671
3672 if (!instr)
3673 continue;
3674
3675 unsigned n = i / 4;
3676 unsigned c = i % 4;
3677 unsigned regid = so->nonbinning->inputs[n].regid + c;
3678
3679 instr->regs[0]->num = regid;
3680 }
3681
3682 ret = ir3_ra(so, ctx->inputs, ctx->ninputs);
3683 } else if (ctx->tcs_header) {
3684 /* We need to have these values in the same registers between VS and TCS
3685 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3686 */
3687
3688 ctx->tcs_header->regs[0]->num = regid(0, 0);
3689 ctx->primitive_id->regs[0]->num = regid(0, 1);
3690 struct ir3_instruction *precolor[] = { ctx->tcs_header, ctx->primitive_id };
3691 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3692 } else if (ctx->gs_header) {
3693 /* We need to have these values in the same registers between producer
3694 * (VS or DS) and GS since the producer chains to GS and doesn't get
3695 * the sysvals redelivered.
3696 */
3697
3698 ctx->gs_header->regs[0]->num = regid(0, 0);
3699 ctx->primitive_id->regs[0]->num = regid(0, 1);
3700 struct ir3_instruction *precolor[] = { ctx->gs_header, ctx->primitive_id };
3701 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3702 } else if (so->num_sampler_prefetch) {
3703 assert(so->type == MESA_SHADER_FRAGMENT);
3704 struct ir3_instruction *instr, *precolor[2];
3705 int idx = 0;
3706
3707 foreach_input (instr, ir) {
3708 if (instr->input.sysval != SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL)
3709 continue;
3710
3711 assert(idx < ARRAY_SIZE(precolor));
3712
3713 precolor[idx] = instr;
3714 instr->regs[0]->num = idx;
3715
3716 idx++;
3717 }
3718 ret = ir3_ra(so, precolor, idx);
3719 } else {
3720 ret = ir3_ra(so, NULL, 0);
3721 }
3722
3723 if (ret) {
3724 DBG("RA failed!");
3725 goto out;
3726 }
3727
3728 ir3_postsched(ctx);
3729 ir3_debug_print(ir, "AFTER POSTSCHED");
3730
3731 if (compiler->gpu_id >= 600) {
3732 if (ir3_a6xx_fixup_atomic_dests(ir, so)) {
3733 ir3_debug_print(ir, "AFTER ATOMIC FIXUP");
3734 }
3735 }
3736
3737 if (so->type == MESA_SHADER_FRAGMENT)
3738 pack_inlocs(ctx);
3739
3740 /*
3741 * Fixup inputs/outputs to point to the actual registers assigned:
3742 *
3743 * 1) initialize to r63.x (invalid/unused)
3744 * 2) iterate IR level inputs/outputs and update the variants
3745 * inputs/outputs table based on the assigned registers for
3746 * the remaining inputs/outputs.
3747 */
3748
3749 for (unsigned i = 0; i < so->inputs_count; i++)
3750 so->inputs[i].regid = INVALID_REG;
3751 for (unsigned i = 0; i < so->outputs_count; i++)
3752 so->outputs[i].regid = INVALID_REG;
3753
3754 struct ir3_instruction *out;
3755 foreach_output (out, ir) {
3756 assert(out->opc == OPC_META_COLLECT);
3757 unsigned outidx = out->collect.outidx;
3758
3759 so->outputs[outidx].regid = out->regs[0]->num;
3760 so->outputs[outidx].half = !!(out->regs[0]->flags & IR3_REG_HALF);
3761 }
3762
3763 struct ir3_instruction *in;
3764 foreach_input (in, ir) {
3765 assert(in->opc == OPC_META_INPUT);
3766 unsigned inidx = in->input.inidx;
3767
3768 if (pre_assign_inputs && !so->inputs[inidx].sysval) {
3769 if (VALIDREG(so->nonbinning->inputs[inidx].regid)) {
3770 compile_assert(ctx, in->regs[0]->num ==
3771 so->nonbinning->inputs[inidx].regid);
3772 compile_assert(ctx, !!(in->regs[0]->flags & IR3_REG_HALF) ==
3773 so->nonbinning->inputs[inidx].half);
3774 }
3775 so->inputs[inidx].regid = so->nonbinning->inputs[inidx].regid;
3776 so->inputs[inidx].half = so->nonbinning->inputs[inidx].half;
3777 } else {
3778 so->inputs[inidx].regid = in->regs[0]->num;
3779 so->inputs[inidx].half = !!(in->regs[0]->flags & IR3_REG_HALF);
3780 }
3781 }
3782
3783 if (ctx->astc_srgb)
3784 fixup_astc_srgb(ctx);
3785
3786 /* We need to do legalize after (for frag shader's) the "bary.f"
3787 * offsets (inloc) have been assigned.
3788 */
3789 ir3_legalize(ir, so, &max_bary);
3790
3791 ir3_debug_print(ir, "AFTER LEGALIZE");
3792
3793 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3794 * know what we might have to wait on when coming in from VS chsh.
3795 */
3796 if (so->type == MESA_SHADER_TESS_CTRL ||
3797 so->type == MESA_SHADER_GEOMETRY ) {
3798 foreach_block (block, &ir->block_list) {
3799 foreach_instr (instr, &block->instr_list) {
3800 instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
3801 break;
3802 }
3803 }
3804 }
3805
3806 so->branchstack = ctx->max_stack;
3807
3808 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3809 if (so->type == MESA_SHADER_FRAGMENT)
3810 so->total_in = max_bary + 1;
3811
3812 so->max_sun = ir->max_sun;
3813
3814 /* Collect sampling instructions eligible for pre-dispatch. */
3815 collect_tex_prefetches(ctx, ir);
3816
3817 if (so->type == MESA_SHADER_FRAGMENT &&
3818 ctx->s->info.fs.needs_helper_invocations)
3819 so->need_pixlod = true;
3820
3821 out:
3822 if (ret) {
3823 if (so->ir)
3824 ir3_destroy(so->ir);
3825 so->ir = NULL;
3826 }
3827 ir3_context_free(ctx);
3828
3829 return ret;
3830 }