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freedreno/ir3: two pass register allocation
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 __ssa_dst(mov);
55 src = __ssa_src(mov, collect, IR3_REG_RELATIV);
56 src->size = arrsz;
57 src->array.offset = n;
58
59 ir3_instr_set_address(mov, address);
60
61 return mov;
62 }
63
64 static struct ir3_instruction *
65 create_input(struct ir3_context *ctx, unsigned compmask)
66 {
67 struct ir3_instruction *in;
68
69 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
70 in->input.sysval = ~0;
71 __ssa_dst(in)->wrmask = compmask;
72
73 array_insert(ctx->ir, ctx->ir->inputs, in);
74
75 return in;
76 }
77
78 static struct ir3_instruction *
79 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
80 {
81 struct ir3_block *block = ctx->block;
82 struct ir3_instruction *instr;
83 /* packed inloc is fixed up later: */
84 struct ir3_instruction *inloc = create_immed(block, n);
85
86 if (use_ldlv) {
87 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
88 instr->cat6.type = TYPE_U32;
89 instr->cat6.iim_val = 1;
90 } else {
91 instr = ir3_BARY_F(block, inloc, 0, ctx->ij_pixel, 0);
92 instr->regs[2]->wrmask = 0x3;
93 }
94
95 return instr;
96 }
97
98 static struct ir3_instruction *
99 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
100 {
101 /* first four vec4 sysval's reserved for UBOs: */
102 /* NOTE: dp is in scalar, but there can be >4 dp components: */
103 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
104 unsigned n = const_state->offsets.driver_param;
105 unsigned r = regid(n + dp / 4, dp % 4);
106 return create_uniform(ctx->block, r);
107 }
108
109 /*
110 * Adreno uses uint rather than having dedicated bool type,
111 * which (potentially) requires some conversion, in particular
112 * when using output of an bool instr to int input, or visa
113 * versa.
114 *
115 * | Adreno | NIR |
116 * -------+---------+-------+-
117 * true | 1 | ~0 |
118 * false | 0 | 0 |
119 *
120 * To convert from an adreno bool (uint) to nir, use:
121 *
122 * absneg.s dst, (neg)src
123 *
124 * To convert back in the other direction:
125 *
126 * absneg.s dst, (abs)arc
127 *
128 * The CP step can clean up the absneg.s that cancel each other
129 * out, and with a slight bit of extra cleverness (to recognize
130 * the instructions which produce either a 0 or 1) can eliminate
131 * the absneg.s's completely when an instruction that wants
132 * 0/1 consumes the result. For example, when a nir 'bcsel'
133 * consumes the result of 'feq'. So we should be able to get by
134 * without a boolean resolve step, and without incuring any
135 * extra penalty in instruction count.
136 */
137
138 /* NIR bool -> native (adreno): */
139 static struct ir3_instruction *
140 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
141 {
142 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
143 }
144
145 /* native (adreno) -> NIR bool: */
146 static struct ir3_instruction *
147 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
148 {
149 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
150 }
151
152 /*
153 * alu/sfu instructions:
154 */
155
156 static struct ir3_instruction *
157 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
158 unsigned src_bitsize, nir_op op)
159 {
160 type_t src_type, dst_type;
161
162 switch (op) {
163 case nir_op_f2f32:
164 case nir_op_f2f16_rtne:
165 case nir_op_f2f16_rtz:
166 case nir_op_f2f16:
167 case nir_op_f2i32:
168 case nir_op_f2i16:
169 case nir_op_f2i8:
170 case nir_op_f2u32:
171 case nir_op_f2u16:
172 case nir_op_f2u8:
173 switch (src_bitsize) {
174 case 32:
175 src_type = TYPE_F32;
176 break;
177 case 16:
178 src_type = TYPE_F16;
179 break;
180 default:
181 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
182 }
183 break;
184
185 case nir_op_i2f32:
186 case nir_op_i2f16:
187 case nir_op_i2i32:
188 case nir_op_i2i16:
189 case nir_op_i2i8:
190 switch (src_bitsize) {
191 case 32:
192 src_type = TYPE_S32;
193 break;
194 case 16:
195 src_type = TYPE_S16;
196 break;
197 case 8:
198 src_type = TYPE_S8;
199 break;
200 default:
201 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
202 }
203 break;
204
205 case nir_op_u2f32:
206 case nir_op_u2f16:
207 case nir_op_u2u32:
208 case nir_op_u2u16:
209 case nir_op_u2u8:
210 switch (src_bitsize) {
211 case 32:
212 src_type = TYPE_U32;
213 break;
214 case 16:
215 src_type = TYPE_U16;
216 break;
217 case 8:
218 src_type = TYPE_U8;
219 break;
220 default:
221 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
222 }
223 break;
224
225 default:
226 ir3_context_error(ctx, "invalid conversion op: %u", op);
227 }
228
229 switch (op) {
230 case nir_op_f2f32:
231 case nir_op_i2f32:
232 case nir_op_u2f32:
233 dst_type = TYPE_F32;
234 break;
235
236 case nir_op_f2f16_rtne:
237 case nir_op_f2f16_rtz:
238 case nir_op_f2f16:
239 /* TODO how to handle rounding mode? */
240 case nir_op_i2f16:
241 case nir_op_u2f16:
242 dst_type = TYPE_F16;
243 break;
244
245 case nir_op_f2i32:
246 case nir_op_i2i32:
247 dst_type = TYPE_S32;
248 break;
249
250 case nir_op_f2i16:
251 case nir_op_i2i16:
252 dst_type = TYPE_S16;
253 break;
254
255 case nir_op_f2i8:
256 case nir_op_i2i8:
257 dst_type = TYPE_S8;
258 break;
259
260 case nir_op_f2u32:
261 case nir_op_u2u32:
262 dst_type = TYPE_U32;
263 break;
264
265 case nir_op_f2u16:
266 case nir_op_u2u16:
267 dst_type = TYPE_U16;
268 break;
269
270 case nir_op_f2u8:
271 case nir_op_u2u8:
272 dst_type = TYPE_U8;
273 break;
274
275 default:
276 ir3_context_error(ctx, "invalid conversion op: %u", op);
277 }
278
279 return ir3_COV(ctx->block, src, src_type, dst_type);
280 }
281
282 static void
283 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
284 {
285 const nir_op_info *info = &nir_op_infos[alu->op];
286 struct ir3_instruction **dst, *src[info->num_inputs];
287 unsigned bs[info->num_inputs]; /* bit size */
288 struct ir3_block *b = ctx->block;
289 unsigned dst_sz, wrmask;
290 type_t dst_type = nir_dest_bit_size(alu->dest.dest) < 32 ?
291 TYPE_U16 : TYPE_U32;
292
293 if (alu->dest.dest.is_ssa) {
294 dst_sz = alu->dest.dest.ssa.num_components;
295 wrmask = (1 << dst_sz) - 1;
296 } else {
297 dst_sz = alu->dest.dest.reg.reg->num_components;
298 wrmask = alu->dest.write_mask;
299 }
300
301 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
302
303 /* Vectors are special in that they have non-scalarized writemasks,
304 * and just take the first swizzle channel for each argument in
305 * order into each writemask channel.
306 */
307 if ((alu->op == nir_op_vec2) ||
308 (alu->op == nir_op_vec3) ||
309 (alu->op == nir_op_vec4)) {
310
311 for (int i = 0; i < info->num_inputs; i++) {
312 nir_alu_src *asrc = &alu->src[i];
313
314 compile_assert(ctx, !asrc->abs);
315 compile_assert(ctx, !asrc->negate);
316
317 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
318 if (!src[i])
319 src[i] = create_immed_typed(ctx->block, 0, dst_type);
320 dst[i] = ir3_MOV(b, src[i], dst_type);
321 }
322
323 ir3_put_dst(ctx, &alu->dest.dest);
324 return;
325 }
326
327 /* We also get mov's with more than one component for mov's so
328 * handle those specially:
329 */
330 if (alu->op == nir_op_mov) {
331 nir_alu_src *asrc = &alu->src[0];
332 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
333
334 for (unsigned i = 0; i < dst_sz; i++) {
335 if (wrmask & (1 << i)) {
336 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
337 } else {
338 dst[i] = NULL;
339 }
340 }
341
342 ir3_put_dst(ctx, &alu->dest.dest);
343 return;
344 }
345
346 /* General case: We can just grab the one used channel per src. */
347 for (int i = 0; i < info->num_inputs; i++) {
348 unsigned chan = ffs(alu->dest.write_mask) - 1;
349 nir_alu_src *asrc = &alu->src[i];
350
351 compile_assert(ctx, !asrc->abs);
352 compile_assert(ctx, !asrc->negate);
353
354 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
355 bs[i] = nir_src_bit_size(asrc->src);
356
357 compile_assert(ctx, src[i]);
358 }
359
360 switch (alu->op) {
361 case nir_op_f2f32:
362 case nir_op_f2f16_rtne:
363 case nir_op_f2f16_rtz:
364 case nir_op_f2f16:
365 case nir_op_f2i32:
366 case nir_op_f2i16:
367 case nir_op_f2i8:
368 case nir_op_f2u32:
369 case nir_op_f2u16:
370 case nir_op_f2u8:
371 case nir_op_i2f32:
372 case nir_op_i2f16:
373 case nir_op_i2i32:
374 case nir_op_i2i16:
375 case nir_op_i2i8:
376 case nir_op_u2f32:
377 case nir_op_u2f16:
378 case nir_op_u2u32:
379 case nir_op_u2u16:
380 case nir_op_u2u8:
381 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
382 break;
383 case nir_op_fquantize2f16:
384 dst[0] = create_cov(ctx,
385 create_cov(ctx, src[0], 32, nir_op_f2f16),
386 16, nir_op_f2f32);
387 break;
388 case nir_op_f2b16: {
389 struct ir3_instruction *zero = create_immed_typed(b, 0, TYPE_F16);
390 dst[0] = ir3_CMPS_F(b, src[0], 0, zero, 0);
391 dst[0]->cat2.condition = IR3_COND_NE;
392 break;
393 }
394 case nir_op_f2b32:
395 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
396 dst[0]->cat2.condition = IR3_COND_NE;
397 break;
398 case nir_op_b2f16:
399 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F16);
400 break;
401 case nir_op_b2f32:
402 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
403 break;
404 case nir_op_b2i8:
405 case nir_op_b2i16:
406 case nir_op_b2i32:
407 dst[0] = ir3_b2n(b, src[0]);
408 break;
409 case nir_op_i2b16: {
410 struct ir3_instruction *zero = create_immed_typed(b, 0, TYPE_S16);
411 dst[0] = ir3_CMPS_S(b, src[0], 0, zero, 0);
412 dst[0]->cat2.condition = IR3_COND_NE;
413 break;
414 }
415 case nir_op_i2b32:
416 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
417 dst[0]->cat2.condition = IR3_COND_NE;
418 break;
419
420 case nir_op_fneg:
421 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
422 break;
423 case nir_op_fabs:
424 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
425 break;
426 case nir_op_fmax:
427 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
428 break;
429 case nir_op_fmin:
430 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
431 break;
432 case nir_op_fsat:
433 /* if there is just a single use of the src, and it supports
434 * (sat) bit, we can just fold the (sat) flag back to the
435 * src instruction and create a mov. This is easier for cp
436 * to eliminate.
437 *
438 * TODO probably opc_cat==4 is ok too
439 */
440 if (alu->src[0].src.is_ssa &&
441 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
442 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
443 src[0]->flags |= IR3_INSTR_SAT;
444 dst[0] = ir3_MOV(b, src[0], dst_type);
445 } else {
446 /* otherwise generate a max.f that saturates.. blob does
447 * similar (generating a cat2 mov using max.f)
448 */
449 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
450 dst[0]->flags |= IR3_INSTR_SAT;
451 }
452 break;
453 case nir_op_fmul:
454 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
455 break;
456 case nir_op_fadd:
457 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
458 break;
459 case nir_op_fsub:
460 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
461 break;
462 case nir_op_ffma:
463 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
464 break;
465 case nir_op_fddx:
466 case nir_op_fddx_coarse:
467 dst[0] = ir3_DSX(b, src[0], 0);
468 dst[0]->cat5.type = TYPE_F32;
469 break;
470 case nir_op_fddx_fine:
471 dst[0] = ir3_DSXPP_1(b, src[0], 0);
472 dst[0]->cat5.type = TYPE_F32;
473 break;
474 case nir_op_fddy:
475 case nir_op_fddy_coarse:
476 dst[0] = ir3_DSY(b, src[0], 0);
477 dst[0]->cat5.type = TYPE_F32;
478 break;
479 break;
480 case nir_op_fddy_fine:
481 dst[0] = ir3_DSYPP_1(b, src[0], 0);
482 dst[0]->cat5.type = TYPE_F32;
483 break;
484 case nir_op_flt16:
485 case nir_op_flt32:
486 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
487 dst[0]->cat2.condition = IR3_COND_LT;
488 break;
489 case nir_op_fge16:
490 case nir_op_fge32:
491 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
492 dst[0]->cat2.condition = IR3_COND_GE;
493 break;
494 case nir_op_feq16:
495 case nir_op_feq32:
496 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
497 dst[0]->cat2.condition = IR3_COND_EQ;
498 break;
499 case nir_op_fne16:
500 case nir_op_fne32:
501 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
502 dst[0]->cat2.condition = IR3_COND_NE;
503 break;
504 case nir_op_fceil:
505 dst[0] = ir3_CEIL_F(b, src[0], 0);
506 break;
507 case nir_op_ffloor:
508 dst[0] = ir3_FLOOR_F(b, src[0], 0);
509 break;
510 case nir_op_ftrunc:
511 dst[0] = ir3_TRUNC_F(b, src[0], 0);
512 break;
513 case nir_op_fround_even:
514 dst[0] = ir3_RNDNE_F(b, src[0], 0);
515 break;
516 case nir_op_fsign:
517 dst[0] = ir3_SIGN_F(b, src[0], 0);
518 break;
519
520 case nir_op_fsin:
521 dst[0] = ir3_SIN(b, src[0], 0);
522 break;
523 case nir_op_fcos:
524 dst[0] = ir3_COS(b, src[0], 0);
525 break;
526 case nir_op_frsq:
527 dst[0] = ir3_RSQ(b, src[0], 0);
528 break;
529 case nir_op_frcp:
530 dst[0] = ir3_RCP(b, src[0], 0);
531 break;
532 case nir_op_flog2:
533 dst[0] = ir3_LOG2(b, src[0], 0);
534 break;
535 case nir_op_fexp2:
536 dst[0] = ir3_EXP2(b, src[0], 0);
537 break;
538 case nir_op_fsqrt:
539 dst[0] = ir3_SQRT(b, src[0], 0);
540 break;
541
542 case nir_op_iabs:
543 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
544 break;
545 case nir_op_iadd:
546 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
547 break;
548 case nir_op_iand:
549 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
550 break;
551 case nir_op_imax:
552 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
553 break;
554 case nir_op_umax:
555 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
556 break;
557 case nir_op_imin:
558 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
559 break;
560 case nir_op_umin:
561 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
562 break;
563 case nir_op_umul_low:
564 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
565 break;
566 case nir_op_imadsh_mix16:
567 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
568 break;
569 case nir_op_imad24_ir3:
570 dst[0] = ir3_MAD_S24(b, src[0], 0, src[1], 0, src[2], 0);
571 break;
572 case nir_op_imul24:
573 dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
574 break;
575 case nir_op_ineg:
576 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
577 break;
578 case nir_op_inot:
579 dst[0] = ir3_NOT_B(b, src[0], 0);
580 break;
581 case nir_op_ior:
582 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
583 break;
584 case nir_op_ishl:
585 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
586 break;
587 case nir_op_ishr:
588 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
589 break;
590 case nir_op_isub:
591 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
592 break;
593 case nir_op_ixor:
594 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
595 break;
596 case nir_op_ushr:
597 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
598 break;
599 case nir_op_ilt16:
600 case nir_op_ilt32:
601 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
602 dst[0]->cat2.condition = IR3_COND_LT;
603 break;
604 case nir_op_ige16:
605 case nir_op_ige32:
606 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
607 dst[0]->cat2.condition = IR3_COND_GE;
608 break;
609 case nir_op_ieq16:
610 case nir_op_ieq32:
611 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
612 dst[0]->cat2.condition = IR3_COND_EQ;
613 break;
614 case nir_op_ine16:
615 case nir_op_ine32:
616 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
617 dst[0]->cat2.condition = IR3_COND_NE;
618 break;
619 case nir_op_ult16:
620 case nir_op_ult32:
621 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
622 dst[0]->cat2.condition = IR3_COND_LT;
623 break;
624 case nir_op_uge16:
625 case nir_op_uge32:
626 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
627 dst[0]->cat2.condition = IR3_COND_GE;
628 break;
629
630 case nir_op_b16csel:
631 case nir_op_b32csel: {
632 struct ir3_instruction *cond = ir3_b2n(b, src[0]);
633
634 if ((src[0]->regs[0]->flags & IR3_REG_HALF))
635 cond->regs[0]->flags |= IR3_REG_HALF;
636
637 compile_assert(ctx, bs[1] == bs[2]);
638 /* Make sure the boolean condition has the same bit size as the other
639 * two arguments, adding a conversion if necessary.
640 */
641 if (bs[1] < bs[0])
642 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
643 else if (bs[1] > bs[0])
644 cond = ir3_COV(b, cond, TYPE_U16, TYPE_U32);
645
646 if (bs[1] > 16)
647 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
648 else
649 dst[0] = ir3_SEL_B16(b, src[1], 0, cond, 0, src[2], 0);
650 break;
651 }
652 case nir_op_bit_count: {
653 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
654 // double check on earlier gen's. Once half-precision support is
655 // in place, this should probably move to a NIR lowering pass:
656 struct ir3_instruction *hi, *lo;
657
658 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
659 TYPE_U32, TYPE_U16);
660 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
661
662 hi = ir3_CBITS_B(b, hi, 0);
663 lo = ir3_CBITS_B(b, lo, 0);
664
665 // TODO maybe the builders should default to making dst half-precision
666 // if the src's were half precision, to make this less awkward.. otoh
667 // we should probably just do this lowering in NIR.
668 hi->regs[0]->flags |= IR3_REG_HALF;
669 lo->regs[0]->flags |= IR3_REG_HALF;
670
671 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
672 dst[0]->regs[0]->flags |= IR3_REG_HALF;
673 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
674 break;
675 }
676 case nir_op_ifind_msb: {
677 struct ir3_instruction *cmp;
678 dst[0] = ir3_CLZ_S(b, src[0], 0);
679 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
680 cmp->cat2.condition = IR3_COND_GE;
681 dst[0] = ir3_SEL_B32(b,
682 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
683 cmp, 0, dst[0], 0);
684 break;
685 }
686 case nir_op_ufind_msb:
687 dst[0] = ir3_CLZ_B(b, src[0], 0);
688 dst[0] = ir3_SEL_B32(b,
689 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
690 src[0], 0, dst[0], 0);
691 break;
692 case nir_op_find_lsb:
693 dst[0] = ir3_BFREV_B(b, src[0], 0);
694 dst[0] = ir3_CLZ_B(b, dst[0], 0);
695 break;
696 case nir_op_bitfield_reverse:
697 dst[0] = ir3_BFREV_B(b, src[0], 0);
698 break;
699
700 default:
701 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
702 nir_op_infos[alu->op].name);
703 break;
704 }
705
706 if (nir_alu_type_get_base_type(info->output_type) == nir_type_bool) {
707 assert(dst_sz == 1);
708
709 if (nir_dest_bit_size(alu->dest.dest) < 32)
710 dst[0]->regs[0]->flags |= IR3_REG_HALF;
711
712 dst[0] = ir3_n2b(b, dst[0]);
713 }
714
715 if (nir_dest_bit_size(alu->dest.dest) < 32) {
716 for (unsigned i = 0; i < dst_sz; i++) {
717 dst[i]->regs[0]->flags |= IR3_REG_HALF;
718 }
719 }
720
721 ir3_put_dst(ctx, &alu->dest.dest);
722 }
723
724 /* handles direct/indirect UBO reads: */
725 static void
726 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
727 struct ir3_instruction **dst)
728 {
729 struct ir3_block *b = ctx->block;
730 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
731 /* UBO addresses are the first driver params, but subtract 2 here to
732 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
733 * is the uniforms: */
734 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
735 unsigned ubo = regid(const_state->offsets.ubo, 0) - 2;
736 const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
737
738 int off = 0;
739
740 /* First src is ubo index, which could either be an immed or not: */
741 src0 = ir3_get_src(ctx, &intr->src[0])[0];
742 if (is_same_type_mov(src0) &&
743 (src0->regs[1]->flags & IR3_REG_IMMED)) {
744 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
745 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
746 } else {
747 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, ptrsz));
748 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, ptrsz));
749
750 /* NOTE: since relative addressing is used, make sure constlen is
751 * at least big enough to cover all the UBO addresses, since the
752 * assembler won't know what the max address reg is.
753 */
754 ctx->so->constlen = MAX2(ctx->so->constlen,
755 const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
756 }
757
758 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
759 addr = base_lo;
760
761 if (nir_src_is_const(intr->src[1])) {
762 off += nir_src_as_uint(intr->src[1]);
763 } else {
764 /* For load_ubo_indirect, second src is indirect offset: */
765 src1 = ir3_get_src(ctx, &intr->src[1])[0];
766
767 /* and add offset to addr: */
768 addr = ir3_ADD_S(b, addr, 0, src1, 0);
769 }
770
771 /* if offset is to large to encode in the ldg, split it out: */
772 if ((off + (intr->num_components * 4)) > 1024) {
773 /* split out the minimal amount to improve the odds that
774 * cp can fit the immediate in the add.s instruction:
775 */
776 unsigned off2 = off + (intr->num_components * 4) - 1024;
777 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
778 off -= off2;
779 }
780
781 if (ptrsz == 2) {
782 struct ir3_instruction *carry;
783
784 /* handle 32b rollover, ie:
785 * if (addr < base_lo)
786 * base_hi++
787 */
788 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
789 carry->cat2.condition = IR3_COND_LT;
790 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
791
792 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
793 }
794
795 for (int i = 0; i < intr->num_components; i++) {
796 struct ir3_instruction *load =
797 ir3_LDG(b, addr, 0, create_immed(b, 1), 0, /* num components */
798 create_immed(b, off + i * 4), 0);
799 load->cat6.type = TYPE_U32;
800 dst[i] = load;
801 }
802 }
803
804 /* src[] = { block_index } */
805 static void
806 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
807 struct ir3_instruction **dst)
808 {
809 /* SSBO size stored as a const starting at ssbo_sizes: */
810 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
811 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
812 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
813 const_state->ssbo_size.off[blk_idx];
814
815 debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
816
817 dst[0] = create_uniform(ctx->block, idx);
818 }
819
820 /* src[] = { offset }. const_index[] = { base } */
821 static void
822 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
823 struct ir3_instruction **dst)
824 {
825 struct ir3_block *b = ctx->block;
826 struct ir3_instruction *ldl, *offset;
827 unsigned base;
828
829 offset = ir3_get_src(ctx, &intr->src[0])[0];
830 base = nir_intrinsic_base(intr);
831
832 ldl = ir3_LDL(b, offset, 0,
833 create_immed(b, intr->num_components), 0,
834 create_immed(b, base), 0);
835
836 ldl->cat6.type = utype_dst(intr->dest);
837 ldl->regs[0]->wrmask = MASK(intr->num_components);
838
839 ldl->barrier_class = IR3_BARRIER_SHARED_R;
840 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
841
842 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
843 }
844
845 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
846 static void
847 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
848 {
849 struct ir3_block *b = ctx->block;
850 struct ir3_instruction *stl, *offset;
851 struct ir3_instruction * const *value;
852 unsigned base, wrmask;
853
854 value = ir3_get_src(ctx, &intr->src[0]);
855 offset = ir3_get_src(ctx, &intr->src[1])[0];
856
857 base = nir_intrinsic_base(intr);
858 wrmask = nir_intrinsic_write_mask(intr);
859
860 /* Combine groups of consecutive enabled channels in one write
861 * message. We use ffs to find the first enabled channel and then ffs on
862 * the bit-inverse, down-shifted writemask to determine the length of
863 * the block of enabled bits.
864 *
865 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
866 */
867 while (wrmask) {
868 unsigned first_component = ffs(wrmask) - 1;
869 unsigned length = ffs(~(wrmask >> first_component)) - 1;
870
871 stl = ir3_STL(b, offset, 0,
872 ir3_create_collect(ctx, &value[first_component], length), 0,
873 create_immed(b, length), 0);
874 stl->cat6.dst_offset = first_component + base;
875 stl->cat6.type = utype_src(intr->src[0]);
876 stl->barrier_class = IR3_BARRIER_SHARED_W;
877 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
878
879 array_insert(b, b->keeps, stl);
880
881 /* Clear the bits in the writemask that we just wrote, then try
882 * again to see if more channels are left.
883 */
884 wrmask &= (15 << (first_component + length));
885 }
886 }
887
888 /* src[] = { offset }. const_index[] = { base } */
889 static void
890 emit_intrinsic_load_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr,
891 struct ir3_instruction **dst)
892 {
893 struct ir3_block *b = ctx->block;
894 struct ir3_instruction *load, *offset;
895 unsigned base;
896
897 offset = ir3_get_src(ctx, &intr->src[0])[0];
898 base = nir_intrinsic_base(intr);
899
900 load = ir3_LDLW(b, offset, 0,
901 create_immed(b, intr->num_components), 0,
902 create_immed(b, base), 0);
903
904 load->cat6.type = utype_dst(intr->dest);
905 load->regs[0]->wrmask = MASK(intr->num_components);
906
907 load->barrier_class = IR3_BARRIER_SHARED_R;
908 load->barrier_conflict = IR3_BARRIER_SHARED_W;
909
910 ir3_split_dest(b, dst, load, 0, intr->num_components);
911 }
912
913 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
914 static void
915 emit_intrinsic_store_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr)
916 {
917 struct ir3_block *b = ctx->block;
918 struct ir3_instruction *store, *offset;
919 struct ir3_instruction * const *value;
920 unsigned base, wrmask;
921
922 value = ir3_get_src(ctx, &intr->src[0]);
923 offset = ir3_get_src(ctx, &intr->src[1])[0];
924
925 base = nir_intrinsic_base(intr);
926 wrmask = nir_intrinsic_write_mask(intr);
927
928 /* Combine groups of consecutive enabled channels in one write
929 * message. We use ffs to find the first enabled channel and then ffs on
930 * the bit-inverse, down-shifted writemask to determine the length of
931 * the block of enabled bits.
932 *
933 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
934 */
935 while (wrmask) {
936 unsigned first_component = ffs(wrmask) - 1;
937 unsigned length = ffs(~(wrmask >> first_component)) - 1;
938
939 store = ir3_STLW(b, offset, 0,
940 ir3_create_collect(ctx, &value[first_component], length), 0,
941 create_immed(b, length), 0);
942
943 store->cat6.dst_offset = first_component + base;
944 store->cat6.type = utype_src(intr->src[0]);
945 store->barrier_class = IR3_BARRIER_SHARED_W;
946 store->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
947
948 array_insert(b, b->keeps, store);
949
950 /* Clear the bits in the writemask that we just wrote, then try
951 * again to see if more channels are left.
952 */
953 wrmask &= (15 << (first_component + length));
954 }
955 }
956
957 /*
958 * CS shared variable atomic intrinsics
959 *
960 * All of the shared variable atomic memory operations read a value from
961 * memory, compute a new value using one of the operations below, write the
962 * new value to memory, and return the original value read.
963 *
964 * All operations take 2 sources except CompSwap that takes 3. These
965 * sources represent:
966 *
967 * 0: The offset into the shared variable storage region that the atomic
968 * operation will operate on.
969 * 1: The data parameter to the atomic function (i.e. the value to add
970 * in shared_atomic_add, etc).
971 * 2: For CompSwap only: the second data parameter.
972 */
973 static struct ir3_instruction *
974 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
975 {
976 struct ir3_block *b = ctx->block;
977 struct ir3_instruction *atomic, *src0, *src1;
978 type_t type = TYPE_U32;
979
980 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
981 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
982
983 switch (intr->intrinsic) {
984 case nir_intrinsic_shared_atomic_add:
985 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
986 break;
987 case nir_intrinsic_shared_atomic_imin:
988 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
989 type = TYPE_S32;
990 break;
991 case nir_intrinsic_shared_atomic_umin:
992 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
993 break;
994 case nir_intrinsic_shared_atomic_imax:
995 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
996 type = TYPE_S32;
997 break;
998 case nir_intrinsic_shared_atomic_umax:
999 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1000 break;
1001 case nir_intrinsic_shared_atomic_and:
1002 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
1003 break;
1004 case nir_intrinsic_shared_atomic_or:
1005 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
1006 break;
1007 case nir_intrinsic_shared_atomic_xor:
1008 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
1009 break;
1010 case nir_intrinsic_shared_atomic_exchange:
1011 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
1012 break;
1013 case nir_intrinsic_shared_atomic_comp_swap:
1014 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1015 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1016 ir3_get_src(ctx, &intr->src[2])[0],
1017 src1,
1018 }, 2);
1019 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
1020 break;
1021 default:
1022 unreachable("boo");
1023 }
1024
1025 atomic->cat6.iim_val = 1;
1026 atomic->cat6.d = 1;
1027 atomic->cat6.type = type;
1028 atomic->barrier_class = IR3_BARRIER_SHARED_W;
1029 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
1030
1031 /* even if nothing consume the result, we can't DCE the instruction: */
1032 array_insert(b, b->keeps, atomic);
1033
1034 return atomic;
1035 }
1036
1037 /* TODO handle actual indirect/dynamic case.. which is going to be weird
1038 * to handle with the image_mapping table..
1039 */
1040 static struct ir3_instruction *
1041 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1042 {
1043 unsigned slot = ir3_get_image_slot(nir_src_as_deref(intr->src[0]));
1044 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
1045 struct ir3_instruction *texture, *sampler;
1046
1047 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1048 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1049
1050 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1051 sampler,
1052 texture,
1053 }, 2);
1054 }
1055
1056 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1057 static void
1058 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1059 struct ir3_instruction **dst)
1060 {
1061 struct ir3_block *b = ctx->block;
1062 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1063 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
1064 struct ir3_instruction *sam;
1065 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
1066 struct ir3_instruction *coords[4];
1067 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
1068 type_t type = ir3_get_image_type(var);
1069
1070 /* hmm, this seems a bit odd, but it is what blob does and (at least
1071 * a5xx) just faults on bogus addresses otherwise:
1072 */
1073 if (flags & IR3_INSTR_3D) {
1074 flags &= ~IR3_INSTR_3D;
1075 flags |= IR3_INSTR_A;
1076 }
1077
1078 for (unsigned i = 0; i < ncoords; i++)
1079 coords[i] = src0[i];
1080
1081 if (ncoords == 1)
1082 coords[ncoords++] = create_immed(b, 0);
1083
1084 sam = ir3_SAM(b, OPC_ISAM, type, 0b1111, flags,
1085 samp_tex, ir3_create_collect(ctx, coords, ncoords), NULL);
1086
1087 sam->barrier_class = IR3_BARRIER_IMAGE_R;
1088 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
1089
1090 ir3_split_dest(b, dst, sam, 0, 4);
1091 }
1092
1093 static void
1094 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1095 struct ir3_instruction **dst)
1096 {
1097 struct ir3_block *b = ctx->block;
1098 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1099 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
1100 struct ir3_instruction *sam, *lod;
1101 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
1102 type_t dst_type = nir_dest_bit_size(intr->dest) < 32 ?
1103 TYPE_U16 : TYPE_U32;
1104
1105 lod = create_immed(b, 0);
1106 sam = ir3_SAM(b, OPC_GETSIZE, dst_type, 0b1111, flags,
1107 samp_tex, lod, NULL);
1108
1109 /* Array size actually ends up in .w rather than .z. This doesn't
1110 * matter for miplevel 0, but for higher mips the value in z is
1111 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1112 * returned, which means that we have to add 1 to it for arrays for
1113 * a3xx.
1114 *
1115 * Note use a temporary dst and then copy, since the size of the dst
1116 * array that is passed in is based on nir's understanding of the
1117 * result size, not the hardware's
1118 */
1119 struct ir3_instruction *tmp[4];
1120
1121 ir3_split_dest(b, tmp, sam, 0, 4);
1122
1123 /* get_size instruction returns size in bytes instead of texels
1124 * for imageBuffer, so we need to divide it by the pixel size
1125 * of the image format.
1126 *
1127 * TODO: This is at least true on a5xx. Check other gens.
1128 */
1129 enum glsl_sampler_dim dim =
1130 glsl_get_sampler_dim(glsl_without_array(var->type));
1131 if (dim == GLSL_SAMPLER_DIM_BUF) {
1132 /* Since all the possible values the divisor can take are
1133 * power-of-two (4, 8, or 16), the division is implemented
1134 * as a shift-right.
1135 * During shader setup, the log2 of the image format's
1136 * bytes-per-pixel should have been emitted in 2nd slot of
1137 * image_dims. See ir3_shader::emit_image_dims().
1138 */
1139 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
1140 unsigned cb = regid(const_state->offsets.image_dims, 0) +
1141 const_state->image_dims.off[var->data.driver_location];
1142 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1143
1144 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1145 }
1146
1147 for (unsigned i = 0; i < ncoords; i++)
1148 dst[i] = tmp[i];
1149
1150 if (flags & IR3_INSTR_A) {
1151 if (ctx->compiler->levels_add_one) {
1152 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1153 } else {
1154 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1155 }
1156 }
1157 }
1158
1159 static void
1160 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1161 {
1162 struct ir3_block *b = ctx->block;
1163 struct ir3_instruction *barrier;
1164
1165 switch (intr->intrinsic) {
1166 case nir_intrinsic_control_barrier:
1167 barrier = ir3_BAR(b);
1168 barrier->cat7.g = true;
1169 barrier->cat7.l = true;
1170 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1171 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1172 break;
1173 case nir_intrinsic_memory_barrier:
1174 barrier = ir3_FENCE(b);
1175 barrier->cat7.g = true;
1176 barrier->cat7.r = true;
1177 barrier->cat7.w = true;
1178 barrier->cat7.l = true;
1179 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1180 IR3_BARRIER_BUFFER_W;
1181 barrier->barrier_conflict =
1182 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1183 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1184 break;
1185 case nir_intrinsic_memory_barrier_buffer:
1186 barrier = ir3_FENCE(b);
1187 barrier->cat7.g = true;
1188 barrier->cat7.r = true;
1189 barrier->cat7.w = true;
1190 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1191 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1192 IR3_BARRIER_BUFFER_W;
1193 break;
1194 case nir_intrinsic_memory_barrier_image:
1195 // TODO double check if this should have .g set
1196 barrier = ir3_FENCE(b);
1197 barrier->cat7.g = true;
1198 barrier->cat7.r = true;
1199 barrier->cat7.w = true;
1200 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1201 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1202 IR3_BARRIER_IMAGE_W;
1203 break;
1204 case nir_intrinsic_memory_barrier_shared:
1205 barrier = ir3_FENCE(b);
1206 barrier->cat7.g = true;
1207 barrier->cat7.l = true;
1208 barrier->cat7.r = true;
1209 barrier->cat7.w = true;
1210 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1211 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1212 IR3_BARRIER_SHARED_W;
1213 break;
1214 case nir_intrinsic_group_memory_barrier:
1215 barrier = ir3_FENCE(b);
1216 barrier->cat7.g = true;
1217 barrier->cat7.l = true;
1218 barrier->cat7.r = true;
1219 barrier->cat7.w = true;
1220 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1221 IR3_BARRIER_IMAGE_W |
1222 IR3_BARRIER_BUFFER_W;
1223 barrier->barrier_conflict =
1224 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1225 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1226 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1227 break;
1228 default:
1229 unreachable("boo");
1230 }
1231
1232 /* make sure barrier doesn't get DCE'd */
1233 array_insert(b, b->keeps, barrier);
1234 }
1235
1236 static void add_sysval_input_compmask(struct ir3_context *ctx,
1237 gl_system_value slot, unsigned compmask,
1238 struct ir3_instruction *instr)
1239 {
1240 struct ir3_shader_variant *so = ctx->so;
1241 unsigned n = so->inputs_count++;
1242
1243 assert(instr->opc == OPC_META_INPUT);
1244 instr->input.inidx = n;
1245 instr->input.sysval = slot;
1246
1247 so->inputs[n].sysval = true;
1248 so->inputs[n].slot = slot;
1249 so->inputs[n].compmask = compmask;
1250 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1251 so->total_in++;
1252 }
1253
1254 static struct ir3_instruction *
1255 create_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1256 unsigned compmask)
1257 {
1258 assert(compmask);
1259 struct ir3_instruction *sysval = create_input(ctx, compmask);
1260 add_sysval_input_compmask(ctx, slot, compmask, sysval);
1261 return sysval;
1262 }
1263
1264 static struct ir3_instruction *
1265 get_barycentric_centroid(struct ir3_context *ctx)
1266 {
1267 if (!ctx->ij_centroid) {
1268 struct ir3_instruction *xy[2];
1269 struct ir3_instruction *ij;
1270
1271 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID, 0x3);
1272 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1273
1274 ctx->ij_centroid = ir3_create_collect(ctx, xy, 2);
1275 }
1276
1277 return ctx->ij_centroid;
1278 }
1279
1280 static struct ir3_instruction *
1281 get_barycentric_sample(struct ir3_context *ctx)
1282 {
1283 if (!ctx->ij_sample) {
1284 struct ir3_instruction *xy[2];
1285 struct ir3_instruction *ij;
1286
1287 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE, 0x3);
1288 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1289
1290 ctx->ij_sample = ir3_create_collect(ctx, xy, 2);
1291 }
1292
1293 return ctx->ij_sample;
1294 }
1295
1296 static struct ir3_instruction *
1297 get_barycentric_pixel(struct ir3_context *ctx)
1298 {
1299 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1300 * this to create ij_pixel only on demand:
1301 */
1302 return ctx->ij_pixel;
1303 }
1304
1305 static struct ir3_instruction *
1306 get_frag_coord(struct ir3_context *ctx)
1307 {
1308 if (!ctx->frag_coord) {
1309 struct ir3_block *b = ctx->block;
1310 struct ir3_instruction *xyzw[4];
1311 struct ir3_instruction *hw_frag_coord;
1312
1313 hw_frag_coord = create_sysval_input(ctx, SYSTEM_VALUE_FRAG_COORD, 0xf);
1314 ir3_split_dest(ctx->block, xyzw, hw_frag_coord, 0, 4);
1315
1316 /* for frag_coord.xy, we get unsigned values.. we need
1317 * to subtract (integer) 8 and divide by 16 (right-
1318 * shift by 4) then convert to float:
1319 *
1320 * sub.s tmp, src, 8
1321 * shr.b tmp, tmp, 4
1322 * mov.u32f32 dst, tmp
1323 *
1324 */
1325 for (int i = 0; i < 2; i++) {
1326 xyzw[i] = ir3_SUB_S(b, xyzw[i], 0,
1327 create_immed(b, 8), 0);
1328 xyzw[i] = ir3_SHR_B(b, xyzw[i], 0,
1329 create_immed(b, 4), 0);
1330 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1331 }
1332
1333 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1334 ctx->so->frag_coord = true;
1335 }
1336
1337 return ctx->frag_coord;
1338 }
1339
1340 static void
1341 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1342 {
1343 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1344 struct ir3_instruction **dst;
1345 struct ir3_instruction * const *src;
1346 struct ir3_block *b = ctx->block;
1347 int idx, comp;
1348
1349 if (info->has_dest) {
1350 unsigned n = nir_intrinsic_dest_components(intr);
1351 dst = ir3_get_dst(ctx, &intr->dest, n);
1352 } else {
1353 dst = NULL;
1354 }
1355
1356 const unsigned primitive_param = ctx->so->shader->const_state.offsets.primitive_param * 4;
1357 const unsigned primitive_map = ctx->so->shader->const_state.offsets.primitive_map * 4;
1358
1359 switch (intr->intrinsic) {
1360 case nir_intrinsic_load_uniform:
1361 idx = nir_intrinsic_base(intr);
1362 if (nir_src_is_const(intr->src[0])) {
1363 idx += nir_src_as_uint(intr->src[0]);
1364 for (int i = 0; i < intr->num_components; i++) {
1365 dst[i] = create_uniform_typed(b, idx + i,
1366 nir_dest_bit_size(intr->dest) < 32 ? TYPE_F16 : TYPE_F32);
1367 }
1368 } else {
1369 src = ir3_get_src(ctx, &intr->src[0]);
1370 for (int i = 0; i < intr->num_components; i++) {
1371 dst[i] = create_uniform_indirect(b, idx + i,
1372 ir3_get_addr(ctx, src[0], 1));
1373 }
1374 /* NOTE: if relative addressing is used, we set
1375 * constlen in the compiler (to worst-case value)
1376 * since we don't know in the assembler what the max
1377 * addr reg value can be:
1378 */
1379 ctx->so->constlen = MAX2(ctx->so->constlen,
1380 ctx->so->shader->ubo_state.size / 16);
1381 }
1382 break;
1383
1384 case nir_intrinsic_load_vs_primitive_stride_ir3:
1385 dst[0] = create_uniform(b, primitive_param + 0);
1386 break;
1387 case nir_intrinsic_load_vs_vertex_stride_ir3:
1388 dst[0] = create_uniform(b, primitive_param + 1);
1389 break;
1390 case nir_intrinsic_load_hs_patch_stride_ir3:
1391 dst[0] = create_uniform(b, primitive_param + 2);
1392 break;
1393 case nir_intrinsic_load_patch_vertices_in:
1394 dst[0] = create_uniform(b, primitive_param + 3);
1395 break;
1396 case nir_intrinsic_load_tess_param_base_ir3:
1397 dst[0] = create_uniform(b, primitive_param + 4);
1398 dst[1] = create_uniform(b, primitive_param + 5);
1399 break;
1400 case nir_intrinsic_load_tess_factor_base_ir3:
1401 dst[0] = create_uniform(b, primitive_param + 6);
1402 dst[1] = create_uniform(b, primitive_param + 7);
1403 break;
1404
1405 case nir_intrinsic_load_primitive_location_ir3:
1406 idx = nir_intrinsic_driver_location(intr);
1407 dst[0] = create_uniform(b, primitive_map + idx);
1408 break;
1409
1410 case nir_intrinsic_load_gs_header_ir3:
1411 dst[0] = ctx->gs_header;
1412 break;
1413 case nir_intrinsic_load_tcs_header_ir3:
1414 dst[0] = ctx->tcs_header;
1415 break;
1416
1417 case nir_intrinsic_load_primitive_id:
1418 dst[0] = ctx->primitive_id;
1419 break;
1420
1421 case nir_intrinsic_load_tess_coord:
1422 if (!ctx->tess_coord) {
1423 ctx->tess_coord =
1424 create_sysval_input(ctx, SYSTEM_VALUE_TESS_COORD, 0x3);
1425 }
1426 ir3_split_dest(b, dst, ctx->tess_coord, 0, 2);
1427
1428 /* Unused, but ir3_put_dst() below wants to free something */
1429 dst[2] = create_immed(b, 0);
1430 break;
1431
1432 case nir_intrinsic_end_patch_ir3:
1433 assert(ctx->so->type == MESA_SHADER_TESS_CTRL);
1434 struct ir3_instruction *end = ir3_ENDIF(b);
1435 array_insert(b, b->keeps, end);
1436
1437 end->barrier_class = IR3_BARRIER_EVERYTHING;
1438 end->barrier_conflict = IR3_BARRIER_EVERYTHING;
1439 break;
1440
1441 case nir_intrinsic_store_global_ir3: {
1442 struct ir3_instruction *value, *addr, *offset;
1443
1444 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1445 ir3_get_src(ctx, &intr->src[1])[0],
1446 ir3_get_src(ctx, &intr->src[1])[1]
1447 }, 2);
1448
1449 offset = ir3_get_src(ctx, &intr->src[2])[0];
1450
1451 value = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]),
1452 intr->num_components);
1453
1454 struct ir3_instruction *stg =
1455 ir3_STG_G(ctx->block, addr, 0, value, 0,
1456 create_immed(ctx->block, intr->num_components), 0, offset, 0);
1457 stg->cat6.type = TYPE_U32;
1458 stg->cat6.iim_val = 1;
1459
1460 array_insert(b, b->keeps, stg);
1461
1462 stg->barrier_class = IR3_BARRIER_BUFFER_W;
1463 stg->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1464 break;
1465 }
1466
1467 case nir_intrinsic_load_global_ir3: {
1468 struct ir3_instruction *addr, *offset;
1469
1470 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1471 ir3_get_src(ctx, &intr->src[0])[0],
1472 ir3_get_src(ctx, &intr->src[0])[1]
1473 }, 2);
1474
1475 offset = ir3_get_src(ctx, &intr->src[1])[0];
1476
1477 struct ir3_instruction *load =
1478 ir3_LDG(b, addr, 0, create_immed(ctx->block, intr->num_components),
1479 0, offset, 0);
1480 load->cat6.type = TYPE_U32;
1481 load->regs[0]->wrmask = MASK(intr->num_components);
1482
1483 load->barrier_class = IR3_BARRIER_BUFFER_R;
1484 load->barrier_conflict = IR3_BARRIER_BUFFER_W;
1485
1486 ir3_split_dest(b, dst, load, 0, intr->num_components);
1487 break;
1488 }
1489
1490 case nir_intrinsic_load_ubo:
1491 emit_intrinsic_load_ubo(ctx, intr, dst);
1492 break;
1493 case nir_intrinsic_load_frag_coord:
1494 ir3_split_dest(b, dst, get_frag_coord(ctx), 0, 4);
1495 break;
1496 case nir_intrinsic_load_sample_pos_from_id: {
1497 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1498 * but that doesn't seem necessary.
1499 */
1500 struct ir3_instruction *offset =
1501 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1502 offset->regs[0]->wrmask = 0x3;
1503 offset->cat5.type = TYPE_F32;
1504
1505 ir3_split_dest(b, dst, offset, 0, 2);
1506
1507 break;
1508 }
1509 case nir_intrinsic_load_size_ir3:
1510 if (!ctx->ij_size) {
1511 ctx->ij_size =
1512 create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE, 0x1);
1513 }
1514 dst[0] = ctx->ij_size;
1515 break;
1516 case nir_intrinsic_load_barycentric_centroid:
1517 ir3_split_dest(b, dst, get_barycentric_centroid(ctx), 0, 2);
1518 break;
1519 case nir_intrinsic_load_barycentric_sample:
1520 if (ctx->so->key.msaa) {
1521 ir3_split_dest(b, dst, get_barycentric_sample(ctx), 0, 2);
1522 } else {
1523 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1524 }
1525 break;
1526 case nir_intrinsic_load_barycentric_pixel:
1527 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1528 break;
1529 case nir_intrinsic_load_interpolated_input:
1530 idx = nir_intrinsic_base(intr);
1531 comp = nir_intrinsic_component(intr);
1532 src = ir3_get_src(ctx, &intr->src[0]);
1533 if (nir_src_is_const(intr->src[1])) {
1534 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1535 idx += nir_src_as_uint(intr->src[1]);
1536 for (int i = 0; i < intr->num_components; i++) {
1537 unsigned inloc = idx * 4 + i + comp;
1538 if (ctx->so->inputs[idx].bary &&
1539 !ctx->so->inputs[idx].use_ldlv) {
1540 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1541 } else {
1542 /* for non-varyings use the pre-setup input, since
1543 * that is easier than mapping things back to a
1544 * nir_variable to figure out what it is.
1545 */
1546 dst[i] = ctx->inputs[inloc];
1547 }
1548 }
1549 } else {
1550 ir3_context_error(ctx, "unhandled");
1551 }
1552 break;
1553 case nir_intrinsic_load_input:
1554 idx = nir_intrinsic_base(intr);
1555 comp = nir_intrinsic_component(intr);
1556 if (nir_src_is_const(intr->src[0])) {
1557 idx += nir_src_as_uint(intr->src[0]);
1558 for (int i = 0; i < intr->num_components; i++) {
1559 unsigned n = idx * 4 + i + comp;
1560 dst[i] = ctx->inputs[n];
1561 compile_assert(ctx, ctx->inputs[n]);
1562 }
1563 } else {
1564 src = ir3_get_src(ctx, &intr->src[0]);
1565 struct ir3_instruction *collect =
1566 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ninputs);
1567 struct ir3_instruction *addr = ir3_get_addr(ctx, src[0], 4);
1568 for (int i = 0; i < intr->num_components; i++) {
1569 unsigned n = idx * 4 + i + comp;
1570 dst[i] = create_indirect_load(ctx, ctx->ninputs,
1571 n, addr, collect);
1572 }
1573 }
1574 break;
1575 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1576 * pass and replaced by an ir3-specifc version that adds the
1577 * dword-offset in the last source.
1578 */
1579 case nir_intrinsic_load_ssbo_ir3:
1580 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1581 break;
1582 case nir_intrinsic_store_ssbo_ir3:
1583 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1584 !ctx->s->info.fs.early_fragment_tests)
1585 ctx->so->no_earlyz = true;
1586 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1587 break;
1588 case nir_intrinsic_get_buffer_size:
1589 emit_intrinsic_ssbo_size(ctx, intr, dst);
1590 break;
1591 case nir_intrinsic_ssbo_atomic_add_ir3:
1592 case nir_intrinsic_ssbo_atomic_imin_ir3:
1593 case nir_intrinsic_ssbo_atomic_umin_ir3:
1594 case nir_intrinsic_ssbo_atomic_imax_ir3:
1595 case nir_intrinsic_ssbo_atomic_umax_ir3:
1596 case nir_intrinsic_ssbo_atomic_and_ir3:
1597 case nir_intrinsic_ssbo_atomic_or_ir3:
1598 case nir_intrinsic_ssbo_atomic_xor_ir3:
1599 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1600 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1601 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1602 !ctx->s->info.fs.early_fragment_tests)
1603 ctx->so->no_earlyz = true;
1604 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1605 break;
1606 case nir_intrinsic_load_shared:
1607 emit_intrinsic_load_shared(ctx, intr, dst);
1608 break;
1609 case nir_intrinsic_store_shared:
1610 emit_intrinsic_store_shared(ctx, intr);
1611 break;
1612 case nir_intrinsic_shared_atomic_add:
1613 case nir_intrinsic_shared_atomic_imin:
1614 case nir_intrinsic_shared_atomic_umin:
1615 case nir_intrinsic_shared_atomic_imax:
1616 case nir_intrinsic_shared_atomic_umax:
1617 case nir_intrinsic_shared_atomic_and:
1618 case nir_intrinsic_shared_atomic_or:
1619 case nir_intrinsic_shared_atomic_xor:
1620 case nir_intrinsic_shared_atomic_exchange:
1621 case nir_intrinsic_shared_atomic_comp_swap:
1622 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1623 break;
1624 case nir_intrinsic_image_deref_load:
1625 emit_intrinsic_load_image(ctx, intr, dst);
1626 break;
1627 case nir_intrinsic_image_deref_store:
1628 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1629 !ctx->s->info.fs.early_fragment_tests)
1630 ctx->so->no_earlyz = true;
1631 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1632 break;
1633 case nir_intrinsic_image_deref_size:
1634 emit_intrinsic_image_size(ctx, intr, dst);
1635 break;
1636 case nir_intrinsic_image_deref_atomic_add:
1637 case nir_intrinsic_image_deref_atomic_imin:
1638 case nir_intrinsic_image_deref_atomic_umin:
1639 case nir_intrinsic_image_deref_atomic_imax:
1640 case nir_intrinsic_image_deref_atomic_umax:
1641 case nir_intrinsic_image_deref_atomic_and:
1642 case nir_intrinsic_image_deref_atomic_or:
1643 case nir_intrinsic_image_deref_atomic_xor:
1644 case nir_intrinsic_image_deref_atomic_exchange:
1645 case nir_intrinsic_image_deref_atomic_comp_swap:
1646 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1647 !ctx->s->info.fs.early_fragment_tests)
1648 ctx->so->no_earlyz = true;
1649 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1650 break;
1651 case nir_intrinsic_control_barrier:
1652 case nir_intrinsic_memory_barrier:
1653 case nir_intrinsic_group_memory_barrier:
1654 case nir_intrinsic_memory_barrier_buffer:
1655 case nir_intrinsic_memory_barrier_image:
1656 case nir_intrinsic_memory_barrier_shared:
1657 emit_intrinsic_barrier(ctx, intr);
1658 /* note that blk ptr no longer valid, make that obvious: */
1659 b = NULL;
1660 break;
1661 case nir_intrinsic_store_output:
1662 idx = nir_intrinsic_base(intr);
1663 comp = nir_intrinsic_component(intr);
1664 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1665 idx += nir_src_as_uint(intr->src[1]);
1666
1667 src = ir3_get_src(ctx, &intr->src[0]);
1668 for (int i = 0; i < intr->num_components; i++) {
1669 unsigned n = idx * 4 + i + comp;
1670 ctx->outputs[n] = src[i];
1671 }
1672 break;
1673 case nir_intrinsic_load_base_vertex:
1674 case nir_intrinsic_load_first_vertex:
1675 if (!ctx->basevertex) {
1676 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1677 }
1678 dst[0] = ctx->basevertex;
1679 break;
1680 case nir_intrinsic_load_base_instance:
1681 if (!ctx->base_instance) {
1682 ctx->base_instance = create_driver_param(ctx, IR3_DP_INSTID_BASE);
1683 }
1684 dst[0] = ctx->base_instance;
1685 break;
1686 case nir_intrinsic_load_vertex_id_zero_base:
1687 case nir_intrinsic_load_vertex_id:
1688 if (!ctx->vertex_id) {
1689 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1690 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1691 ctx->vertex_id = create_sysval_input(ctx, sv, 0x1);
1692 }
1693 dst[0] = ctx->vertex_id;
1694 break;
1695 case nir_intrinsic_load_instance_id:
1696 if (!ctx->instance_id) {
1697 ctx->instance_id = create_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID, 0x1);
1698 }
1699 dst[0] = ctx->instance_id;
1700 break;
1701 case nir_intrinsic_load_sample_id:
1702 ctx->so->per_samp = true;
1703 /* fall-thru */
1704 case nir_intrinsic_load_sample_id_no_per_sample:
1705 if (!ctx->samp_id) {
1706 ctx->samp_id = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID, 0x1);
1707 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1708 }
1709 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1710 break;
1711 case nir_intrinsic_load_sample_mask_in:
1712 if (!ctx->samp_mask_in) {
1713 ctx->samp_mask_in = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN, 0x1);
1714 }
1715 dst[0] = ctx->samp_mask_in;
1716 break;
1717 case nir_intrinsic_load_user_clip_plane:
1718 idx = nir_intrinsic_ucp_id(intr);
1719 for (int i = 0; i < intr->num_components; i++) {
1720 unsigned n = idx * 4 + i;
1721 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1722 }
1723 break;
1724 case nir_intrinsic_load_front_face:
1725 if (!ctx->frag_face) {
1726 ctx->so->frag_face = true;
1727 ctx->frag_face = create_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, 0x1);
1728 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1729 }
1730 /* for fragface, we get -1 for back and 0 for front. However this is
1731 * the inverse of what nir expects (where ~0 is true).
1732 */
1733 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1734 dst[0] = ir3_NOT_B(b, dst[0], 0);
1735 break;
1736 case nir_intrinsic_load_local_invocation_id:
1737 if (!ctx->local_invocation_id) {
1738 ctx->local_invocation_id =
1739 create_sysval_input(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID, 0x7);
1740 }
1741 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1742 break;
1743 case nir_intrinsic_load_work_group_id:
1744 if (!ctx->work_group_id) {
1745 ctx->work_group_id =
1746 create_sysval_input(ctx, SYSTEM_VALUE_WORK_GROUP_ID, 0x7);
1747 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1748 }
1749 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1750 break;
1751 case nir_intrinsic_load_num_work_groups:
1752 for (int i = 0; i < intr->num_components; i++) {
1753 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1754 }
1755 break;
1756 case nir_intrinsic_load_local_group_size:
1757 for (int i = 0; i < intr->num_components; i++) {
1758 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1759 }
1760 break;
1761 case nir_intrinsic_discard_if:
1762 case nir_intrinsic_discard: {
1763 struct ir3_instruction *cond, *kill;
1764
1765 if (intr->intrinsic == nir_intrinsic_discard_if) {
1766 /* conditional discard: */
1767 src = ir3_get_src(ctx, &intr->src[0]);
1768 cond = ir3_b2n(b, src[0]);
1769 } else {
1770 /* unconditional discard: */
1771 cond = create_immed(b, 1);
1772 }
1773
1774 /* NOTE: only cmps.*.* can write p0.x: */
1775 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1776 cond->cat2.condition = IR3_COND_NE;
1777
1778 /* condition always goes in predicate register: */
1779 cond->regs[0]->num = regid(REG_P0, 0);
1780 cond->regs[0]->flags &= ~IR3_REG_SSA;
1781
1782 kill = ir3_KILL(b, cond, 0);
1783 kill->regs[1]->num = regid(REG_P0, 0);
1784 array_insert(ctx->ir, ctx->ir->predicates, kill);
1785
1786 array_insert(b, b->keeps, kill);
1787 ctx->so->no_earlyz = true;
1788
1789 break;
1790 }
1791
1792 case nir_intrinsic_cond_end_ir3: {
1793 struct ir3_instruction *cond, *kill;
1794
1795 src = ir3_get_src(ctx, &intr->src[0]);
1796 cond = ir3_b2n(b, src[0]);
1797
1798 /* NOTE: only cmps.*.* can write p0.x: */
1799 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1800 cond->cat2.condition = IR3_COND_NE;
1801
1802 /* condition always goes in predicate register: */
1803 cond->regs[0]->num = regid(REG_P0, 0);
1804
1805 kill = ir3_IF(b, cond, 0);
1806
1807 kill->barrier_class = IR3_BARRIER_EVERYTHING;
1808 kill->barrier_conflict = IR3_BARRIER_EVERYTHING;
1809
1810 array_insert(ctx->ir, ctx->ir->predicates, kill);
1811 array_insert(b, b->keeps, kill);
1812 break;
1813 }
1814
1815 case nir_intrinsic_load_shared_ir3:
1816 emit_intrinsic_load_shared_ir3(ctx, intr, dst);
1817 break;
1818 case nir_intrinsic_store_shared_ir3:
1819 emit_intrinsic_store_shared_ir3(ctx, intr);
1820 break;
1821 default:
1822 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1823 nir_intrinsic_infos[intr->intrinsic].name);
1824 break;
1825 }
1826
1827 if (info->has_dest)
1828 ir3_put_dst(ctx, &intr->dest);
1829 }
1830
1831 static void
1832 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1833 {
1834 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1835 instr->def.num_components);
1836
1837 if (instr->def.bit_size < 32) {
1838 for (int i = 0; i < instr->def.num_components; i++)
1839 dst[i] = create_immed_typed(ctx->block,
1840 instr->value[i].u16,
1841 TYPE_U16);
1842 } else {
1843 for (int i = 0; i < instr->def.num_components; i++)
1844 dst[i] = create_immed_typed(ctx->block,
1845 instr->value[i].u32,
1846 TYPE_U32);
1847 }
1848
1849 }
1850
1851 static void
1852 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1853 {
1854 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1855 undef->def.num_components);
1856 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1857
1858 /* backend doesn't want undefined instructions, so just plug
1859 * in 0.0..
1860 */
1861 for (int i = 0; i < undef->def.num_components; i++)
1862 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1863 }
1864
1865 /*
1866 * texture fetch/sample instructions:
1867 */
1868
1869 static type_t
1870 get_tex_dest_type(nir_tex_instr *tex)
1871 {
1872 type_t type;
1873
1874 switch (nir_alu_type_get_base_type(tex->dest_type)) {
1875 case nir_type_invalid:
1876 case nir_type_float:
1877 type = nir_dest_bit_size(tex->dest) < 32 ? TYPE_F16 : TYPE_F32;
1878 break;
1879 case nir_type_int:
1880 type = nir_dest_bit_size(tex->dest) < 32 ? TYPE_S16 : TYPE_S32;
1881 break;
1882 case nir_type_uint:
1883 case nir_type_bool:
1884 type = nir_dest_bit_size(tex->dest) < 32 ? TYPE_U16 : TYPE_U32;
1885 break;
1886 default:
1887 unreachable("bad dest_type");
1888 }
1889
1890 return type;
1891 }
1892
1893 static void
1894 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1895 {
1896 unsigned coords, flags = 0;
1897
1898 /* note: would use tex->coord_components.. except txs.. also,
1899 * since array index goes after shadow ref, we don't want to
1900 * count it:
1901 */
1902 switch (tex->sampler_dim) {
1903 case GLSL_SAMPLER_DIM_1D:
1904 case GLSL_SAMPLER_DIM_BUF:
1905 coords = 1;
1906 break;
1907 case GLSL_SAMPLER_DIM_2D:
1908 case GLSL_SAMPLER_DIM_RECT:
1909 case GLSL_SAMPLER_DIM_EXTERNAL:
1910 case GLSL_SAMPLER_DIM_MS:
1911 case GLSL_SAMPLER_DIM_SUBPASS:
1912 case GLSL_SAMPLER_DIM_SUBPASS_MS:
1913 coords = 2;
1914 break;
1915 case GLSL_SAMPLER_DIM_3D:
1916 case GLSL_SAMPLER_DIM_CUBE:
1917 coords = 3;
1918 flags |= IR3_INSTR_3D;
1919 break;
1920 default:
1921 unreachable("bad sampler_dim");
1922 }
1923
1924 if (tex->is_shadow && tex->op != nir_texop_lod)
1925 flags |= IR3_INSTR_S;
1926
1927 if (tex->is_array && tex->op != nir_texop_lod)
1928 flags |= IR3_INSTR_A;
1929
1930 *flagsp = flags;
1931 *coordsp = coords;
1932 }
1933
1934 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
1935 * or immediate (in which case it will get lowered later to a non .s2en
1936 * version of the tex instruction which encode tex/samp as immediates:
1937 */
1938 static struct ir3_instruction *
1939 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
1940 {
1941 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
1942 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
1943 struct ir3_instruction *texture, *sampler;
1944
1945 if (texture_idx >= 0) {
1946 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
1947 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
1948 } else {
1949 /* TODO what to do for dynamic case? I guess we only need the
1950 * max index for astc srgb workaround so maybe not a problem
1951 * to worry about if we don't enable indirect samplers for
1952 * a4xx?
1953 */
1954 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
1955 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
1956 }
1957
1958 if (sampler_idx >= 0) {
1959 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
1960 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
1961 } else {
1962 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
1963 }
1964
1965 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1966 sampler,
1967 texture,
1968 }, 2);
1969 }
1970
1971 static void
1972 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
1973 {
1974 struct ir3_block *b = ctx->block;
1975 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1976 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
1977 struct ir3_instruction *lod, *compare, *proj, *sample_index;
1978 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1979 unsigned i, coords, flags, ncomp;
1980 unsigned nsrc0 = 0, nsrc1 = 0;
1981 type_t type;
1982 opc_t opc = 0;
1983
1984 ncomp = nir_dest_num_components(tex->dest);
1985
1986 coord = off = ddx = ddy = NULL;
1987 lod = proj = compare = sample_index = NULL;
1988
1989 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
1990
1991 for (unsigned i = 0; i < tex->num_srcs; i++) {
1992 switch (tex->src[i].src_type) {
1993 case nir_tex_src_coord:
1994 coord = ir3_get_src(ctx, &tex->src[i].src);
1995 break;
1996 case nir_tex_src_bias:
1997 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1998 has_bias = true;
1999 break;
2000 case nir_tex_src_lod:
2001 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
2002 has_lod = true;
2003 break;
2004 case nir_tex_src_comparator: /* shadow comparator */
2005 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
2006 break;
2007 case nir_tex_src_projector:
2008 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
2009 has_proj = true;
2010 break;
2011 case nir_tex_src_offset:
2012 off = ir3_get_src(ctx, &tex->src[i].src);
2013 has_off = true;
2014 break;
2015 case nir_tex_src_ddx:
2016 ddx = ir3_get_src(ctx, &tex->src[i].src);
2017 break;
2018 case nir_tex_src_ddy:
2019 ddy = ir3_get_src(ctx, &tex->src[i].src);
2020 break;
2021 case nir_tex_src_ms_index:
2022 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
2023 break;
2024 case nir_tex_src_texture_offset:
2025 case nir_tex_src_sampler_offset:
2026 /* handled in get_tex_samp_src() */
2027 break;
2028 default:
2029 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
2030 tex->src[i].src_type);
2031 return;
2032 }
2033 }
2034
2035 switch (tex->op) {
2036 case nir_texop_tex_prefetch:
2037 compile_assert(ctx, !has_bias);
2038 compile_assert(ctx, !has_lod);
2039 compile_assert(ctx, !compare);
2040 compile_assert(ctx, !has_proj);
2041 compile_assert(ctx, !has_off);
2042 compile_assert(ctx, !ddx);
2043 compile_assert(ctx, !ddy);
2044 compile_assert(ctx, !sample_index);
2045 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_texture_offset) < 0);
2046 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset) < 0);
2047
2048 if (ctx->so->num_sampler_prefetch < IR3_MAX_SAMPLER_PREFETCH) {
2049 opc = OPC_META_TEX_PREFETCH;
2050 ctx->so->num_sampler_prefetch++;
2051 break;
2052 }
2053 /* fallthru */
2054 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
2055 case nir_texop_txb: opc = OPC_SAMB; break;
2056 case nir_texop_txl: opc = OPC_SAML; break;
2057 case nir_texop_txd: opc = OPC_SAMGQ; break;
2058 case nir_texop_txf: opc = OPC_ISAML; break;
2059 case nir_texop_lod: opc = OPC_GETLOD; break;
2060 case nir_texop_tg4:
2061 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2062 * what blob does, seems gather is broken?), and a3xx did
2063 * not support it (but probably could also emulate).
2064 */
2065 switch (tex->component) {
2066 case 0: opc = OPC_GATHER4R; break;
2067 case 1: opc = OPC_GATHER4G; break;
2068 case 2: opc = OPC_GATHER4B; break;
2069 case 3: opc = OPC_GATHER4A; break;
2070 }
2071 break;
2072 case nir_texop_txf_ms_fb:
2073 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
2074 default:
2075 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
2076 return;
2077 }
2078
2079 tex_info(tex, &flags, &coords);
2080
2081 /*
2082 * lay out the first argument in the proper order:
2083 * - actual coordinates first
2084 * - shadow reference
2085 * - array index
2086 * - projection w
2087 * - starting at offset 4, dpdx.xy, dpdy.xy
2088 *
2089 * bias/lod go into the second arg
2090 */
2091
2092 /* insert tex coords: */
2093 for (i = 0; i < coords; i++)
2094 src0[i] = coord[i];
2095
2096 nsrc0 = i;
2097
2098 /* scale up integer coords for TXF based on the LOD */
2099 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
2100 assert(has_lod);
2101 for (i = 0; i < coords; i++)
2102 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
2103 }
2104
2105 if (coords == 1) {
2106 /* hw doesn't do 1d, so we treat it as 2d with
2107 * height of 1, and patch up the y coord.
2108 */
2109 if (is_isam(opc)) {
2110 src0[nsrc0++] = create_immed(b, 0);
2111 } else {
2112 src0[nsrc0++] = create_immed(b, fui(0.5));
2113 }
2114 }
2115
2116 if (tex->is_shadow && tex->op != nir_texop_lod)
2117 src0[nsrc0++] = compare;
2118
2119 if (tex->is_array && tex->op != nir_texop_lod) {
2120 struct ir3_instruction *idx = coord[coords];
2121
2122 /* the array coord for cube arrays needs 0.5 added to it */
2123 if (ctx->compiler->array_index_add_half && !is_isam(opc))
2124 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
2125
2126 src0[nsrc0++] = idx;
2127 }
2128
2129 if (has_proj) {
2130 src0[nsrc0++] = proj;
2131 flags |= IR3_INSTR_P;
2132 }
2133
2134 /* pad to 4, then ddx/ddy: */
2135 if (tex->op == nir_texop_txd) {
2136 while (nsrc0 < 4)
2137 src0[nsrc0++] = create_immed(b, fui(0.0));
2138 for (i = 0; i < coords; i++)
2139 src0[nsrc0++] = ddx[i];
2140 if (coords < 2)
2141 src0[nsrc0++] = create_immed(b, fui(0.0));
2142 for (i = 0; i < coords; i++)
2143 src0[nsrc0++] = ddy[i];
2144 if (coords < 2)
2145 src0[nsrc0++] = create_immed(b, fui(0.0));
2146 }
2147
2148 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2149 * with scaled x coord according to requested sample:
2150 */
2151 if (opc == OPC_ISAMM) {
2152 if (ctx->compiler->txf_ms_with_isaml) {
2153 /* the samples are laid out in x dimension as
2154 * 0 1 2 3
2155 * x_ms = (x << ms) + sample_index;
2156 */
2157 struct ir3_instruction *ms;
2158 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
2159
2160 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
2161 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
2162
2163 opc = OPC_ISAML;
2164 } else {
2165 src0[nsrc0++] = sample_index;
2166 }
2167 }
2168
2169 /*
2170 * second argument (if applicable):
2171 * - offsets
2172 * - lod
2173 * - bias
2174 */
2175 if (has_off | has_lod | has_bias) {
2176 if (has_off) {
2177 unsigned off_coords = coords;
2178 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2179 off_coords--;
2180 for (i = 0; i < off_coords; i++)
2181 src1[nsrc1++] = off[i];
2182 if (off_coords < 2)
2183 src1[nsrc1++] = create_immed(b, fui(0.0));
2184 flags |= IR3_INSTR_O;
2185 }
2186
2187 if (has_lod | has_bias)
2188 src1[nsrc1++] = lod;
2189 }
2190
2191 type = get_tex_dest_type(tex);
2192
2193 if (opc == OPC_GETLOD)
2194 type = TYPE_S32;
2195
2196 struct ir3_instruction *samp_tex;
2197
2198 if (tex->op == nir_texop_txf_ms_fb) {
2199 /* only expect a single txf_ms_fb per shader: */
2200 compile_assert(ctx, !ctx->so->fb_read);
2201 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
2202
2203 ctx->so->fb_read = true;
2204 samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2205 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2206 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2207 }, 2);
2208
2209 ctx->so->num_samp++;
2210 } else {
2211 samp_tex = get_tex_samp_tex_src(ctx, tex);
2212 }
2213
2214 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
2215 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
2216
2217 if (opc == OPC_META_TEX_PREFETCH) {
2218 int idx = nir_tex_instr_src_index(tex, nir_tex_src_coord);
2219
2220 compile_assert(ctx, tex->src[idx].src.is_ssa);
2221
2222 sam = ir3_META_TEX_PREFETCH(b);
2223 __ssa_dst(sam)->wrmask = MASK(ncomp); /* dst */
2224 sam->prefetch.input_offset =
2225 ir3_nir_coord_offset(tex->src[idx].src.ssa);
2226 sam->prefetch.tex = tex->texture_index;
2227 sam->prefetch.samp = tex->sampler_index;
2228 } else {
2229 sam = ir3_SAM(b, opc, type, MASK(ncomp), flags,
2230 samp_tex, col0, col1);
2231 }
2232
2233 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
2234 assert(opc != OPC_META_TEX_PREFETCH);
2235
2236 /* only need first 3 components: */
2237 sam->regs[0]->wrmask = 0x7;
2238 ir3_split_dest(b, dst, sam, 0, 3);
2239
2240 /* we need to sample the alpha separately with a non-ASTC
2241 * texture state:
2242 */
2243 sam = ir3_SAM(b, opc, type, 0b1000, flags,
2244 samp_tex, col0, col1);
2245
2246 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
2247
2248 /* fixup .w component: */
2249 ir3_split_dest(b, &dst[3], sam, 3, 1);
2250 } else {
2251 /* normal (non-workaround) case: */
2252 ir3_split_dest(b, dst, sam, 0, ncomp);
2253 }
2254
2255 /* GETLOD returns results in 4.8 fixed point */
2256 if (opc == OPC_GETLOD) {
2257 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
2258
2259 compile_assert(ctx, tex->dest_type == nir_type_float);
2260 for (i = 0; i < 2; i++) {
2261 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_S32, TYPE_F32), 0,
2262 factor, 0);
2263 }
2264 }
2265
2266 ir3_put_dst(ctx, &tex->dest);
2267 }
2268
2269 static void
2270 emit_tex_info(struct ir3_context *ctx, nir_tex_instr *tex, unsigned idx)
2271 {
2272 struct ir3_block *b = ctx->block;
2273 struct ir3_instruction **dst, *sam;
2274 type_t dst_type = get_tex_dest_type(tex);
2275
2276 dst = ir3_get_dst(ctx, &tex->dest, 1);
2277
2278 sam = ir3_SAM(b, OPC_GETINFO, dst_type, 1 << idx, 0,
2279 get_tex_samp_tex_src(ctx, tex), NULL, NULL);
2280
2281 /* even though there is only one component, since it ends
2282 * up in .y/.z/.w rather than .x, we need a split_dest()
2283 */
2284 if (idx)
2285 ir3_split_dest(b, dst, sam, 0, idx + 1);
2286
2287 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2288 * the value in TEX_CONST_0 is zero-based.
2289 */
2290 if (ctx->compiler->levels_add_one)
2291 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2292
2293 ir3_put_dst(ctx, &tex->dest);
2294 }
2295
2296 static void
2297 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2298 {
2299 struct ir3_block *b = ctx->block;
2300 struct ir3_instruction **dst, *sam;
2301 struct ir3_instruction *lod;
2302 unsigned flags, coords;
2303 type_t dst_type = get_tex_dest_type(tex);
2304
2305 tex_info(tex, &flags, &coords);
2306
2307 /* Actually we want the number of dimensions, not coordinates. This
2308 * distinction only matters for cubes.
2309 */
2310 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2311 coords = 2;
2312
2313 dst = ir3_get_dst(ctx, &tex->dest, 4);
2314
2315 compile_assert(ctx, tex->num_srcs == 1);
2316 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
2317
2318 lod = ir3_get_src(ctx, &tex->src[0].src)[0];
2319
2320 sam = ir3_SAM(b, OPC_GETSIZE, dst_type, 0b1111, flags,
2321 get_tex_samp_tex_src(ctx, tex), lod, NULL);
2322
2323 ir3_split_dest(b, dst, sam, 0, 4);
2324
2325 /* Array size actually ends up in .w rather than .z. This doesn't
2326 * matter for miplevel 0, but for higher mips the value in z is
2327 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2328 * returned, which means that we have to add 1 to it for arrays.
2329 */
2330 if (tex->is_array) {
2331 if (ctx->compiler->levels_add_one) {
2332 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2333 } else {
2334 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2335 }
2336 }
2337
2338 ir3_put_dst(ctx, &tex->dest);
2339 }
2340
2341 static void
2342 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2343 {
2344 switch (jump->type) {
2345 case nir_jump_break:
2346 case nir_jump_continue:
2347 case nir_jump_return:
2348 /* I *think* we can simply just ignore this, and use the
2349 * successor block link to figure out where we need to
2350 * jump to for break/continue
2351 */
2352 break;
2353 default:
2354 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2355 break;
2356 }
2357 }
2358
2359 static void
2360 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2361 {
2362 switch (instr->type) {
2363 case nir_instr_type_alu:
2364 emit_alu(ctx, nir_instr_as_alu(instr));
2365 break;
2366 case nir_instr_type_deref:
2367 /* ignored, handled as part of the intrinsic they are src to */
2368 break;
2369 case nir_instr_type_intrinsic:
2370 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2371 break;
2372 case nir_instr_type_load_const:
2373 emit_load_const(ctx, nir_instr_as_load_const(instr));
2374 break;
2375 case nir_instr_type_ssa_undef:
2376 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2377 break;
2378 case nir_instr_type_tex: {
2379 nir_tex_instr *tex = nir_instr_as_tex(instr);
2380 /* couple tex instructions get special-cased:
2381 */
2382 switch (tex->op) {
2383 case nir_texop_txs:
2384 emit_tex_txs(ctx, tex);
2385 break;
2386 case nir_texop_query_levels:
2387 emit_tex_info(ctx, tex, 2);
2388 break;
2389 case nir_texop_texture_samples:
2390 emit_tex_info(ctx, tex, 3);
2391 break;
2392 default:
2393 emit_tex(ctx, tex);
2394 break;
2395 }
2396 break;
2397 }
2398 case nir_instr_type_jump:
2399 emit_jump(ctx, nir_instr_as_jump(instr));
2400 break;
2401 case nir_instr_type_phi:
2402 /* we have converted phi webs to regs in NIR by now */
2403 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2404 break;
2405 case nir_instr_type_call:
2406 case nir_instr_type_parallel_copy:
2407 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2408 break;
2409 }
2410 }
2411
2412 static struct ir3_block *
2413 get_block(struct ir3_context *ctx, const nir_block *nblock)
2414 {
2415 struct ir3_block *block;
2416 struct hash_entry *hentry;
2417
2418 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2419 if (hentry)
2420 return hentry->data;
2421
2422 block = ir3_block_create(ctx->ir);
2423 block->nblock = nblock;
2424 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2425
2426 block->predecessors = _mesa_pointer_set_create(block);
2427 set_foreach(nblock->predecessors, sentry) {
2428 _mesa_set_add(block->predecessors, get_block(ctx, sentry->key));
2429 }
2430
2431 return block;
2432 }
2433
2434 static void
2435 emit_block(struct ir3_context *ctx, nir_block *nblock)
2436 {
2437 struct ir3_block *block = get_block(ctx, nblock);
2438
2439 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2440 if (nblock->successors[i]) {
2441 block->successors[i] =
2442 get_block(ctx, nblock->successors[i]);
2443 }
2444 }
2445
2446 ctx->block = block;
2447 list_addtail(&block->node, &ctx->ir->block_list);
2448
2449 /* re-emit addr register in each block if needed: */
2450 for (int i = 0; i < ARRAY_SIZE(ctx->addr_ht); i++) {
2451 _mesa_hash_table_destroy(ctx->addr_ht[i], NULL);
2452 ctx->addr_ht[i] = NULL;
2453 }
2454
2455 nir_foreach_instr(instr, nblock) {
2456 ctx->cur_instr = instr;
2457 emit_instr(ctx, instr);
2458 ctx->cur_instr = NULL;
2459 if (ctx->error)
2460 return;
2461 }
2462 }
2463
2464 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2465
2466 static void
2467 emit_if(struct ir3_context *ctx, nir_if *nif)
2468 {
2469 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2470
2471 ctx->block->condition =
2472 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
2473
2474 emit_cf_list(ctx, &nif->then_list);
2475 emit_cf_list(ctx, &nif->else_list);
2476 }
2477
2478 static void
2479 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2480 {
2481 emit_cf_list(ctx, &nloop->body);
2482 ctx->so->loops++;
2483 }
2484
2485 static void
2486 stack_push(struct ir3_context *ctx)
2487 {
2488 ctx->stack++;
2489 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2490 }
2491
2492 static void
2493 stack_pop(struct ir3_context *ctx)
2494 {
2495 compile_assert(ctx, ctx->stack > 0);
2496 ctx->stack--;
2497 }
2498
2499 static void
2500 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2501 {
2502 foreach_list_typed(nir_cf_node, node, node, list) {
2503 switch (node->type) {
2504 case nir_cf_node_block:
2505 emit_block(ctx, nir_cf_node_as_block(node));
2506 break;
2507 case nir_cf_node_if:
2508 stack_push(ctx);
2509 emit_if(ctx, nir_cf_node_as_if(node));
2510 stack_pop(ctx);
2511 break;
2512 case nir_cf_node_loop:
2513 stack_push(ctx);
2514 emit_loop(ctx, nir_cf_node_as_loop(node));
2515 stack_pop(ctx);
2516 break;
2517 case nir_cf_node_function:
2518 ir3_context_error(ctx, "TODO\n");
2519 break;
2520 }
2521 }
2522 }
2523
2524 /* emit stream-out code. At this point, the current block is the original
2525 * (nir) end block, and nir ensures that all flow control paths terminate
2526 * into the end block. We re-purpose the original end block to generate
2527 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2528 * block holding stream-out write instructions, followed by the new end
2529 * block:
2530 *
2531 * blockOrigEnd {
2532 * p0.x = (vtxcnt < maxvtxcnt)
2533 * // succs: blockStreamOut, blockNewEnd
2534 * }
2535 * blockStreamOut {
2536 * ... stream-out instructions ...
2537 * // succs: blockNewEnd
2538 * }
2539 * blockNewEnd {
2540 * }
2541 */
2542 static void
2543 emit_stream_out(struct ir3_context *ctx)
2544 {
2545 struct ir3 *ir = ctx->ir;
2546 struct ir3_stream_output_info *strmout =
2547 &ctx->so->shader->stream_output;
2548 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2549 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2550 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2551
2552 /* create vtxcnt input in input block at top of shader,
2553 * so that it is seen as live over the entire duration
2554 * of the shader:
2555 */
2556 vtxcnt = create_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, 0x1);
2557 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2558
2559 /* at this point, we are at the original 'end' block,
2560 * re-purpose this block to stream-out condition, then
2561 * append stream-out block and new-end block
2562 */
2563 orig_end_block = ctx->block;
2564
2565 // TODO these blocks need to update predecessors..
2566 // maybe w/ store_global intrinsic, we could do this
2567 // stuff in nir->nir pass
2568
2569 stream_out_block = ir3_block_create(ir);
2570 list_addtail(&stream_out_block->node, &ir->block_list);
2571
2572 new_end_block = ir3_block_create(ir);
2573 list_addtail(&new_end_block->node, &ir->block_list);
2574
2575 orig_end_block->successors[0] = stream_out_block;
2576 orig_end_block->successors[1] = new_end_block;
2577 stream_out_block->successors[0] = new_end_block;
2578
2579 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2580 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2581 cond->regs[0]->num = regid(REG_P0, 0);
2582 cond->regs[0]->flags &= ~IR3_REG_SSA;
2583 cond->cat2.condition = IR3_COND_LT;
2584
2585 /* condition goes on previous block to the conditional,
2586 * since it is used to pick which of the two successor
2587 * paths to take:
2588 */
2589 orig_end_block->condition = cond;
2590
2591 /* switch to stream_out_block to generate the stream-out
2592 * instructions:
2593 */
2594 ctx->block = stream_out_block;
2595
2596 /* Calculate base addresses based on vtxcnt. Instructions
2597 * generated for bases not used in following loop will be
2598 * stripped out in the backend.
2599 */
2600 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2601 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
2602 unsigned stride = strmout->stride[i];
2603 struct ir3_instruction *base, *off;
2604
2605 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
2606
2607 /* 24-bit should be enough: */
2608 off = ir3_MUL_U24(ctx->block, vtxcnt, 0,
2609 create_immed(ctx->block, stride * 4), 0);
2610
2611 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2612 }
2613
2614 /* Generate the per-output store instructions: */
2615 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2616 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2617 unsigned c = j + strmout->output[i].start_component;
2618 struct ir3_instruction *base, *out, *stg;
2619
2620 base = bases[strmout->output[i].output_buffer];
2621 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2622
2623 stg = ir3_STG(ctx->block, base, 0, out, 0,
2624 create_immed(ctx->block, 1), 0);
2625 stg->cat6.type = TYPE_U32;
2626 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2627
2628 array_insert(ctx->block, ctx->block->keeps, stg);
2629 }
2630 }
2631
2632 /* and finally switch to the new_end_block: */
2633 ctx->block = new_end_block;
2634 }
2635
2636 static void
2637 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2638 {
2639 nir_metadata_require(impl, nir_metadata_block_index);
2640
2641 compile_assert(ctx, ctx->stack == 0);
2642
2643 emit_cf_list(ctx, &impl->body);
2644 emit_block(ctx, impl->end_block);
2645
2646 compile_assert(ctx, ctx->stack == 0);
2647
2648 /* at this point, we should have a single empty block,
2649 * into which we emit the 'end' instruction.
2650 */
2651 compile_assert(ctx, list_is_empty(&ctx->block->instr_list));
2652
2653 /* If stream-out (aka transform-feedback) enabled, emit the
2654 * stream-out instructions, followed by a new empty block (into
2655 * which the 'end' instruction lands).
2656 *
2657 * NOTE: it is done in this order, rather than inserting before
2658 * we emit end_block, because NIR guarantees that all blocks
2659 * flow into end_block, and that end_block has no successors.
2660 * So by re-purposing end_block as the first block of stream-
2661 * out, we guarantee that all exit paths flow into the stream-
2662 * out instructions.
2663 */
2664 if ((ctx->compiler->gpu_id < 500) &&
2665 (ctx->so->shader->stream_output.num_outputs > 0) &&
2666 !ctx->so->binning_pass) {
2667 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2668 emit_stream_out(ctx);
2669 }
2670
2671 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2672 * NOP and has an epilogue that writes the VS outputs to local storage, to
2673 * be read by the HS. Then it resets execution mask (chmask) and chains
2674 * to the next shader (chsh).
2675 */
2676 if ((ctx->so->type == MESA_SHADER_VERTEX &&
2677 (ctx->so->key.has_gs || ctx->so->key.tessellation)) ||
2678 (ctx->so->type == MESA_SHADER_TESS_EVAL && ctx->so->key.has_gs)) {
2679 struct ir3_instruction *chmask =
2680 ir3_CHMASK(ctx->block);
2681 chmask->barrier_class = IR3_BARRIER_EVERYTHING;
2682 chmask->barrier_conflict = IR3_BARRIER_EVERYTHING;
2683
2684 struct ir3_instruction *chsh =
2685 ir3_CHSH(ctx->block);
2686 chsh->barrier_class = IR3_BARRIER_EVERYTHING;
2687 chsh->barrier_conflict = IR3_BARRIER_EVERYTHING;
2688 } else {
2689 ir3_END(ctx->block);
2690 }
2691 }
2692
2693 static void
2694 setup_input(struct ir3_context *ctx, nir_variable *in)
2695 {
2696 struct ir3_shader_variant *so = ctx->so;
2697 unsigned ncomp = glsl_get_components(in->type);
2698 unsigned n = in->data.driver_location;
2699 unsigned frac = in->data.location_frac;
2700 unsigned slot = in->data.location;
2701
2702 /* Inputs are loaded using ldlw or ldg for these stages. */
2703 if (ctx->so->type == MESA_SHADER_TESS_CTRL ||
2704 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2705 ctx->so->type == MESA_SHADER_GEOMETRY)
2706 return;
2707
2708 /* skip unread inputs, we could end up with (for example), unsplit
2709 * matrix/etc inputs in the case they are not read, so just silently
2710 * skip these.
2711 */
2712 if (ncomp > 4)
2713 return;
2714
2715 so->inputs[n].slot = slot;
2716 so->inputs[n].compmask |= (1 << (ncomp + frac)) - 1;
2717 so->inputs_count = MAX2(so->inputs_count, n + 1);
2718 so->inputs[n].interpolate = in->data.interpolation;
2719
2720 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2721
2722 /* if any varyings have 'sample' qualifer, that triggers us
2723 * to run in per-sample mode:
2724 */
2725 so->per_samp |= in->data.sample;
2726
2727 for (int i = 0; i < ncomp; i++) {
2728 struct ir3_instruction *instr = NULL;
2729 unsigned idx = (n * 4) + i + frac;
2730
2731 if (slot == VARYING_SLOT_POS) {
2732 ir3_context_error(ctx, "fragcoord should be a sysval!\n");
2733 } else if (slot == VARYING_SLOT_PNTC) {
2734 /* see for example st_nir_fixup_varying_slots().. this is
2735 * maybe a bit mesa/st specific. But we need things to line
2736 * up for this in fdN_program:
2737 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2738 * if (emit->sprite_coord_enable & texmask) {
2739 * ...
2740 * }
2741 */
2742 so->inputs[n].slot = VARYING_SLOT_VAR8;
2743 so->inputs[n].bary = true;
2744 instr = create_frag_input(ctx, false, idx);
2745 } else {
2746 /* detect the special case for front/back colors where
2747 * we need to do flat vs smooth shading depending on
2748 * rast state:
2749 */
2750 if (in->data.interpolation == INTERP_MODE_NONE) {
2751 switch (slot) {
2752 case VARYING_SLOT_COL0:
2753 case VARYING_SLOT_COL1:
2754 case VARYING_SLOT_BFC0:
2755 case VARYING_SLOT_BFC1:
2756 so->inputs[n].rasterflat = true;
2757 break;
2758 default:
2759 break;
2760 }
2761 }
2762
2763 if (ctx->compiler->flat_bypass) {
2764 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2765 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2766 so->inputs[n].use_ldlv = true;
2767 }
2768
2769 so->inputs[n].bary = true;
2770
2771 instr = create_frag_input(ctx, so->inputs[n].use_ldlv, idx);
2772 }
2773
2774 compile_assert(ctx, idx < ctx->ninputs);
2775
2776 ctx->inputs[idx] = instr;
2777 }
2778 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2779 struct ir3_instruction *input = NULL, *in;
2780 struct ir3_instruction *components[4];
2781 unsigned mask = (1 << (ncomp + frac)) - 1;
2782
2783 foreach_input(in, ctx->ir) {
2784 if (in->input.inidx == n) {
2785 input = in;
2786 break;
2787 }
2788 }
2789
2790 if (!input) {
2791 input = create_input(ctx, mask);
2792 input->input.inidx = n;
2793 } else {
2794 input->regs[0]->wrmask |= mask;
2795 }
2796
2797 ir3_split_dest(ctx->block, components, input, frac, ncomp);
2798
2799 for (int i = 0; i < ncomp; i++) {
2800 unsigned idx = (n * 4) + i + frac;
2801 compile_assert(ctx, idx < ctx->ninputs);
2802 ctx->inputs[idx] = components[i];
2803 }
2804 } else {
2805 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2806 }
2807
2808 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
2809 so->total_in += ncomp;
2810 }
2811 }
2812
2813 /* Initially we assign non-packed inloc's for varyings, as we don't really
2814 * know up-front which components will be unused. After all the compilation
2815 * stages we scan the shader to see which components are actually used, and
2816 * re-pack the inlocs to eliminate unneeded varyings.
2817 */
2818 static void
2819 pack_inlocs(struct ir3_context *ctx)
2820 {
2821 struct ir3_shader_variant *so = ctx->so;
2822 uint8_t used_components[so->inputs_count];
2823
2824 memset(used_components, 0, sizeof(used_components));
2825
2826 /*
2827 * First Step: scan shader to find which bary.f/ldlv remain:
2828 */
2829
2830 foreach_block (block, &ctx->ir->block_list) {
2831 foreach_instr (instr, &block->instr_list) {
2832 if (is_input(instr)) {
2833 unsigned inloc = instr->regs[1]->iim_val;
2834 unsigned i = inloc / 4;
2835 unsigned j = inloc % 4;
2836
2837 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
2838 compile_assert(ctx, i < so->inputs_count);
2839
2840 used_components[i] |= 1 << j;
2841 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
2842 for (int n = 0; n < 2; n++) {
2843 unsigned inloc = instr->prefetch.input_offset + n;
2844 unsigned i = inloc / 4;
2845 unsigned j = inloc % 4;
2846
2847 compile_assert(ctx, i < so->inputs_count);
2848
2849 used_components[i] |= 1 << j;
2850 }
2851 }
2852 }
2853 }
2854
2855 /*
2856 * Second Step: reassign varying inloc/slots:
2857 */
2858
2859 unsigned actual_in = 0;
2860 unsigned inloc = 0;
2861
2862 for (unsigned i = 0; i < so->inputs_count; i++) {
2863 unsigned compmask = 0, maxcomp = 0;
2864
2865 so->inputs[i].inloc = inloc;
2866 so->inputs[i].bary = false;
2867
2868 for (unsigned j = 0; j < 4; j++) {
2869 if (!(used_components[i] & (1 << j)))
2870 continue;
2871
2872 compmask |= (1 << j);
2873 actual_in++;
2874 maxcomp = j + 1;
2875
2876 /* at this point, since used_components[i] mask is only
2877 * considering varyings (ie. not sysvals) we know this
2878 * is a varying:
2879 */
2880 so->inputs[i].bary = true;
2881 }
2882
2883 if (so->inputs[i].bary) {
2884 so->varying_in++;
2885 so->inputs[i].compmask = (1 << maxcomp) - 1;
2886 inloc += maxcomp;
2887 }
2888 }
2889
2890 /*
2891 * Third Step: reassign packed inloc's:
2892 */
2893
2894 foreach_block (block, &ctx->ir->block_list) {
2895 foreach_instr (instr, &block->instr_list) {
2896 if (is_input(instr)) {
2897 unsigned inloc = instr->regs[1]->iim_val;
2898 unsigned i = inloc / 4;
2899 unsigned j = inloc % 4;
2900
2901 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
2902 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
2903 unsigned i = instr->prefetch.input_offset / 4;
2904 unsigned j = instr->prefetch.input_offset % 4;
2905 instr->prefetch.input_offset = so->inputs[i].inloc + j;
2906 }
2907 }
2908 }
2909 }
2910
2911 static void
2912 setup_output(struct ir3_context *ctx, nir_variable *out)
2913 {
2914 struct ir3_shader_variant *so = ctx->so;
2915 unsigned ncomp = glsl_get_components(out->type);
2916 unsigned n = out->data.driver_location;
2917 unsigned frac = out->data.location_frac;
2918 unsigned slot = out->data.location;
2919 unsigned comp = 0;
2920
2921 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2922 switch (slot) {
2923 case FRAG_RESULT_DEPTH:
2924 comp = 2; /* tgsi will write to .z component */
2925 so->writes_pos = true;
2926 break;
2927 case FRAG_RESULT_COLOR:
2928 so->color0_mrt = 1;
2929 break;
2930 case FRAG_RESULT_SAMPLE_MASK:
2931 so->writes_smask = true;
2932 break;
2933 default:
2934 if (slot >= FRAG_RESULT_DATA0)
2935 break;
2936 ir3_context_error(ctx, "unknown FS output name: %s\n",
2937 gl_frag_result_name(slot));
2938 }
2939 } else if (ctx->so->type == MESA_SHADER_VERTEX ||
2940 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2941 ctx->so->type == MESA_SHADER_GEOMETRY) {
2942 switch (slot) {
2943 case VARYING_SLOT_POS:
2944 so->writes_pos = true;
2945 break;
2946 case VARYING_SLOT_PSIZ:
2947 so->writes_psize = true;
2948 break;
2949 case VARYING_SLOT_PRIMITIVE_ID:
2950 case VARYING_SLOT_LAYER:
2951 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
2952 debug_assert(ctx->so->type == MESA_SHADER_GEOMETRY);
2953 /* fall through */
2954 case VARYING_SLOT_COL0:
2955 case VARYING_SLOT_COL1:
2956 case VARYING_SLOT_BFC0:
2957 case VARYING_SLOT_BFC1:
2958 case VARYING_SLOT_FOGC:
2959 case VARYING_SLOT_CLIP_DIST0:
2960 case VARYING_SLOT_CLIP_DIST1:
2961 case VARYING_SLOT_CLIP_VERTEX:
2962 break;
2963 default:
2964 if (slot >= VARYING_SLOT_VAR0)
2965 break;
2966 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
2967 break;
2968 ir3_context_error(ctx, "unknown %s shader output name: %s\n",
2969 _mesa_shader_stage_to_string(ctx->so->type),
2970 gl_varying_slot_name(slot));
2971 }
2972 } else if (ctx->so->type == MESA_SHADER_TESS_CTRL) {
2973 /* output lowered to buffer writes. */
2974 return;
2975 } else {
2976 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2977 }
2978
2979 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
2980
2981 so->outputs[n].slot = slot;
2982 so->outputs[n].regid = regid(n, comp);
2983 so->outputs_count = MAX2(so->outputs_count, n + 1);
2984
2985 for (int i = 0; i < ncomp; i++) {
2986 unsigned idx = (n * 4) + i + frac;
2987 compile_assert(ctx, idx < ctx->noutputs);
2988 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
2989 }
2990
2991 /* if varying packing doesn't happen, we could end up in a situation
2992 * with "holes" in the output, and since the per-generation code that
2993 * sets up varying linkage registers doesn't expect to have more than
2994 * one varying per vec4 slot, pad the holes.
2995 *
2996 * Note that this should probably generate a performance warning of
2997 * some sort.
2998 */
2999 for (int i = 0; i < frac; i++) {
3000 unsigned idx = (n * 4) + i;
3001 if (!ctx->outputs[idx]) {
3002 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
3003 }
3004 }
3005 }
3006
3007 static int
3008 max_drvloc(struct exec_list *vars)
3009 {
3010 int drvloc = -1;
3011 nir_foreach_variable(var, vars) {
3012 drvloc = MAX2(drvloc, (int)var->data.driver_location);
3013 }
3014 return drvloc;
3015 }
3016
3017 static void
3018 emit_instructions(struct ir3_context *ctx)
3019 {
3020 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
3021
3022 ctx->ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4;
3023 ctx->noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4;
3024
3025 ctx->inputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->ninputs);
3026 ctx->outputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->noutputs);
3027
3028 ctx->ir = ir3_create(ctx->compiler, ctx->so->type);
3029
3030 /* Create inputs in first block: */
3031 ctx->block = get_block(ctx, nir_start_block(fxn));
3032 ctx->in_block = ctx->block;
3033 list_addtail(&ctx->block->node, &ctx->ir->block_list);
3034
3035 /* for fragment shader, the vcoord input register is used as the
3036 * base for bary.f varying fetch instrs:
3037 *
3038 * TODO defer creating ctx->ij_pixel and corresponding sysvals
3039 * until emit_intrinsic when we know they are actually needed.
3040 * For now, we defer creating ctx->ij_centroid, etc, since we
3041 * only need ij_pixel for "old style" varying inputs (ie.
3042 * tgsi_to_nir)
3043 */
3044 struct ir3_instruction *vcoord = NULL;
3045 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3046 struct ir3_instruction *xy[2];
3047
3048 vcoord = create_input(ctx, 0x3);
3049 ir3_split_dest(ctx->block, xy, vcoord, 0, 2);
3050
3051 ctx->ij_pixel = ir3_create_collect(ctx, xy, 2);
3052 }
3053
3054 /* Setup inputs: */
3055 nir_foreach_variable(var, &ctx->s->inputs) {
3056 setup_input(ctx, var);
3057 }
3058
3059 /* Defer add_sysval_input() stuff until after setup_inputs(),
3060 * because sysvals need to be appended after varyings:
3061 */
3062 if (vcoord) {
3063 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL,
3064 0x3, vcoord);
3065 }
3066
3067
3068 /* Tesselation shaders always need primitive ID for indexing the
3069 * BO. Geometry shaders don't always need it but when they do it has be
3070 * delivered and unclobbered in the VS. To make things easy, we always
3071 * make room for it in VS/DS.
3072 */
3073 bool has_tess = ctx->so->key.tessellation != IR3_TESS_NONE;
3074 bool has_gs = ctx->so->key.has_gs;
3075 switch (ctx->so->type) {
3076 case MESA_SHADER_VERTEX:
3077 if (has_tess) {
3078 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3079 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3080 } else if (has_gs) {
3081 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3082 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3083 }
3084 break;
3085 case MESA_SHADER_TESS_CTRL:
3086 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3087 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3088 break;
3089 case MESA_SHADER_TESS_EVAL:
3090 if (has_gs)
3091 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3092 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3093 break;
3094 case MESA_SHADER_GEOMETRY:
3095 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3096 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3097 break;
3098 default:
3099 break;
3100 }
3101
3102 /* Setup outputs: */
3103 nir_foreach_variable(var, &ctx->s->outputs) {
3104 setup_output(ctx, var);
3105 }
3106
3107 /* Find # of samplers: */
3108 nir_foreach_variable(var, &ctx->s->uniforms) {
3109 ctx->so->num_samp += glsl_type_get_sampler_count(var->type);
3110 /* just assume that we'll be reading from images.. if it
3111 * is write-only we don't have to count it, but not sure
3112 * if there is a good way to know?
3113 */
3114 ctx->so->num_samp += glsl_type_get_image_count(var->type);
3115 }
3116
3117 /* NOTE: need to do something more clever when we support >1 fxn */
3118 nir_foreach_register(reg, &fxn->registers) {
3119 ir3_declare_array(ctx, reg);
3120 }
3121 /* And emit the body: */
3122 ctx->impl = fxn;
3123 emit_function(ctx, fxn);
3124 }
3125
3126 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3127 * need to assign the tex state indexes for these after we know the
3128 * max tex index.
3129 */
3130 static void
3131 fixup_astc_srgb(struct ir3_context *ctx)
3132 {
3133 struct ir3_shader_variant *so = ctx->so;
3134 /* indexed by original tex idx, value is newly assigned alpha sampler
3135 * state tex idx. Zero is invalid since there is at least one sampler
3136 * if we get here.
3137 */
3138 unsigned alt_tex_state[16] = {0};
3139 unsigned tex_idx = ctx->max_texture_index + 1;
3140 unsigned idx = 0;
3141
3142 so->astc_srgb.base = tex_idx;
3143
3144 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
3145 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
3146
3147 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
3148
3149 if (alt_tex_state[sam->cat5.tex] == 0) {
3150 /* assign new alternate/alpha tex state slot: */
3151 alt_tex_state[sam->cat5.tex] = tex_idx++;
3152 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
3153 so->astc_srgb.count++;
3154 }
3155
3156 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
3157 }
3158 }
3159
3160 static void
3161 fixup_binning_pass(struct ir3_context *ctx)
3162 {
3163 struct ir3_shader_variant *so = ctx->so;
3164 struct ir3 *ir = ctx->ir;
3165 unsigned i, j;
3166
3167 /* first pass, remove unused outputs from the IR level outputs: */
3168 for (i = 0, j = 0; i < ir->outputs_count; i++) {
3169 struct ir3_instruction *out = ir->outputs[i];
3170 assert(out->opc == OPC_META_COLLECT);
3171 unsigned outidx = out->collect.outidx;
3172 unsigned slot = so->outputs[outidx].slot;
3173
3174 /* throw away everything but first position/psize */
3175 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3176 ir->outputs[j] = ir->outputs[i];
3177 j++;
3178 }
3179 }
3180 ir->outputs_count = j;
3181
3182 /* second pass, cleanup the unused slots in ir3_shader_variant::outputs
3183 * table:
3184 */
3185 for (i = 0, j = 0; i < so->outputs_count; i++) {
3186 unsigned slot = so->outputs[i].slot;
3187
3188 /* throw away everything but first position/psize */
3189 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3190 so->outputs[j] = so->outputs[i];
3191
3192 /* fixup outidx to point to new output table entry: */
3193 struct ir3_instruction *out;
3194 foreach_output(out, ir) {
3195 if (out->collect.outidx == i) {
3196 out->collect.outidx = j;
3197 break;
3198 }
3199 }
3200
3201 j++;
3202 }
3203 }
3204 so->outputs_count = j;
3205 }
3206
3207 static void
3208 collect_tex_prefetches(struct ir3_context *ctx, struct ir3 *ir)
3209 {
3210 unsigned idx = 0;
3211
3212 /* Collect sampling instructions eligible for pre-dispatch. */
3213 foreach_block (block, &ir->block_list) {
3214 foreach_instr_safe (instr, &block->instr_list) {
3215 if (instr->opc == OPC_META_TEX_PREFETCH) {
3216 assert(idx < ARRAY_SIZE(ctx->so->sampler_prefetch));
3217 struct ir3_sampler_prefetch *fetch =
3218 &ctx->so->sampler_prefetch[idx];
3219 idx++;
3220
3221 fetch->cmd = IR3_SAMPLER_PREFETCH_CMD;
3222 fetch->wrmask = instr->regs[0]->wrmask;
3223 fetch->tex_id = instr->prefetch.tex;
3224 fetch->samp_id = instr->prefetch.samp;
3225 fetch->dst = instr->regs[0]->num;
3226 fetch->src = instr->prefetch.input_offset;
3227
3228 ctx->so->total_in =
3229 MAX2(ctx->so->total_in, instr->prefetch.input_offset + 2);
3230
3231 /* Disable half precision until supported. */
3232 fetch->half_precision = !!(instr->regs[0]->flags & IR3_REG_HALF);
3233
3234 /* Remove the prefetch placeholder instruction: */
3235 list_delinit(&instr->node);
3236 }
3237 }
3238 }
3239 }
3240
3241 int
3242 ir3_compile_shader_nir(struct ir3_compiler *compiler,
3243 struct ir3_shader_variant *so)
3244 {
3245 struct ir3_context *ctx;
3246 struct ir3 *ir;
3247 int ret = 0, max_bary;
3248
3249 assert(!so->ir);
3250
3251 ctx = ir3_context_init(compiler, so);
3252 if (!ctx) {
3253 DBG("INIT failed!");
3254 ret = -1;
3255 goto out;
3256 }
3257
3258 emit_instructions(ctx);
3259
3260 if (ctx->error) {
3261 DBG("EMIT failed!");
3262 ret = -1;
3263 goto out;
3264 }
3265
3266 ir = so->ir = ctx->ir;
3267
3268 assert((ctx->noutputs % 4) == 0);
3269
3270 /* Setup IR level outputs, which are "collects" that gather
3271 * the scalar components of outputs.
3272 */
3273 for (unsigned i = 0; i < ctx->noutputs; i += 4) {
3274 unsigned ncomp = 0;
3275 /* figure out the # of components written:
3276 *
3277 * TODO do we need to handle holes, ie. if .x and .z
3278 * components written, but .y component not written?
3279 */
3280 for (unsigned j = 0; j < 4; j++) {
3281 if (!ctx->outputs[i + j])
3282 break;
3283 ncomp++;
3284 }
3285
3286 /* Note that in some stages, like TCS, store_output is
3287 * lowered to memory writes, so no components of the
3288 * are "written" from the PoV of traditional store-
3289 * output instructions:
3290 */
3291 if (!ncomp)
3292 continue;
3293
3294 struct ir3_instruction *out =
3295 ir3_create_collect(ctx, &ctx->outputs[i], ncomp);
3296
3297 int outidx = i / 4;
3298 assert(outidx < so->outputs_count);
3299
3300 /* stash index into so->outputs[] so we can map the
3301 * output back to slot/etc later:
3302 */
3303 out->collect.outidx = outidx;
3304
3305 array_insert(ir, ir->outputs, out);
3306 }
3307
3308 /* Set up the gs header as an output for the vertex shader so it won't
3309 * clobber it for the tess ctrl shader.
3310 *
3311 * TODO this could probably be done more cleanly in a nir pass.
3312 */
3313 if (ctx->so->type == MESA_SHADER_VERTEX ||
3314 (ctx->so->key.has_gs && ctx->so->type == MESA_SHADER_TESS_EVAL)) {
3315 if (ctx->primitive_id) {
3316 unsigned n = so->outputs_count++;
3317 so->outputs[n].slot = VARYING_SLOT_PRIMITIVE_ID;
3318
3319 struct ir3_instruction *out =
3320 ir3_create_collect(ctx, &ctx->primitive_id, 1);
3321 out->collect.outidx = n;
3322 array_insert(ir, ir->outputs, out);
3323 }
3324
3325 if (ctx->gs_header) {
3326 unsigned n = so->outputs_count++;
3327 so->outputs[n].slot = VARYING_SLOT_GS_HEADER_IR3;
3328 struct ir3_instruction *out =
3329 ir3_create_collect(ctx, &ctx->gs_header, 1);
3330 out->collect.outidx = n;
3331 array_insert(ir, ir->outputs, out);
3332 }
3333
3334 if (ctx->tcs_header) {
3335 unsigned n = so->outputs_count++;
3336 so->outputs[n].slot = VARYING_SLOT_TCS_HEADER_IR3;
3337 struct ir3_instruction *out =
3338 ir3_create_collect(ctx, &ctx->tcs_header, 1);
3339 out->collect.outidx = n;
3340 array_insert(ir, ir->outputs, out);
3341 }
3342 }
3343
3344 /* at this point, for binning pass, throw away unneeded outputs: */
3345 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
3346 fixup_binning_pass(ctx);
3347
3348 ir3_debug_print(ir, "BEFORE CP");
3349
3350 ir3_cp(ir, so);
3351
3352 /* at this point, for binning pass, throw away unneeded outputs:
3353 * Note that for a6xx and later, we do this after ir3_cp to ensure
3354 * that the uniform/constant layout for BS and VS matches, so that
3355 * we can re-use same VS_CONST state group.
3356 */
3357 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
3358 fixup_binning_pass(ctx);
3359
3360 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3361 * need to make sure not to remove any inputs that are used by
3362 * the nonbinning VS.
3363 */
3364 if (ctx->compiler->gpu_id >= 600 && so->binning_pass &&
3365 so->type == MESA_SHADER_VERTEX) {
3366 for (int i = 0; i < ctx->ninputs; i++) {
3367 struct ir3_instruction *in = ctx->inputs[i];
3368
3369 if (!in)
3370 continue;
3371
3372 unsigned n = i / 4;
3373 unsigned c = i % 4;
3374
3375 debug_assert(n < so->nonbinning->inputs_count);
3376
3377 if (so->nonbinning->inputs[n].sysval)
3378 continue;
3379
3380 /* be sure to keep inputs, even if only used in VS */
3381 if (so->nonbinning->inputs[n].compmask & (1 << c))
3382 array_insert(in->block, in->block->keeps, in);
3383 }
3384 }
3385
3386 ir3_debug_print(ir, "BEFORE GROUPING");
3387
3388 ir3_sched_add_deps(ir);
3389
3390 /* Group left/right neighbors, inserting mov's where needed to
3391 * solve conflicts:
3392 */
3393 ir3_group(ir);
3394
3395 ir3_debug_print(ir, "AFTER GROUPING");
3396
3397 ir3_depth(ir, so);
3398
3399 ir3_debug_print(ir, "AFTER DEPTH");
3400
3401 /* do Sethi–Ullman numbering before scheduling: */
3402 ir3_sun(ir);
3403
3404 ret = ir3_sched(ir);
3405 if (ret) {
3406 DBG("SCHED failed!");
3407 goto out;
3408 }
3409
3410 ir3_debug_print(ir, "AFTER SCHED");
3411
3412 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3413 * with draw pass VS, so binning and draw pass can both use the
3414 * same VBO state.
3415 *
3416 * Note that VS inputs are expected to be full precision.
3417 */
3418 bool pre_assign_inputs = (ir->compiler->gpu_id >= 600) &&
3419 (ir->type == MESA_SHADER_VERTEX) &&
3420 so->binning_pass;
3421
3422 if (pre_assign_inputs) {
3423 for (unsigned i = 0; i < ctx->ninputs; i++) {
3424 struct ir3_instruction *instr = ctx->inputs[i];
3425
3426 if (!instr)
3427 continue;
3428
3429 unsigned n = i / 4;
3430 unsigned c = i % 4;
3431 unsigned regid = so->nonbinning->inputs[n].regid + c;
3432
3433 instr->regs[0]->num = regid;
3434 }
3435
3436 ret = ir3_ra(so, ctx->inputs, ctx->ninputs);
3437 } else if (ctx->tcs_header) {
3438 /* We need to have these values in the same registers between VS and TCS
3439 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3440 */
3441
3442 ctx->tcs_header->regs[0]->num = regid(0, 0);
3443 ctx->primitive_id->regs[0]->num = regid(0, 1);
3444 struct ir3_instruction *precolor[] = { ctx->tcs_header, ctx->primitive_id };
3445 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3446 } else if (ctx->gs_header) {
3447 /* We need to have these values in the same registers between producer
3448 * (VS or DS) and GS since the producer chains to GS and doesn't get
3449 * the sysvals redelivered.
3450 */
3451
3452 ctx->gs_header->regs[0]->num = regid(0, 0);
3453 ctx->primitive_id->regs[0]->num = regid(0, 1);
3454 struct ir3_instruction *precolor[] = { ctx->gs_header, ctx->primitive_id };
3455 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3456 } else if (so->num_sampler_prefetch) {
3457 assert(so->type == MESA_SHADER_FRAGMENT);
3458 struct ir3_instruction *instr, *precolor[2];
3459 int idx = 0;
3460
3461 foreach_input(instr, ir) {
3462 if (instr->input.sysval != SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL)
3463 continue;
3464
3465 assert(idx < ARRAY_SIZE(precolor));
3466
3467 precolor[idx] = instr;
3468 instr->regs[0]->num = idx;
3469
3470 idx++;
3471 }
3472 ret = ir3_ra(so, precolor, idx);
3473 } else {
3474 ret = ir3_ra(so, NULL, 0);
3475 }
3476
3477 if (ret) {
3478 DBG("RA failed!");
3479 goto out;
3480 }
3481
3482 ir3_postsched(ctx);
3483 ir3_debug_print(ir, "AFTER POSTSCHED");
3484
3485 if (compiler->gpu_id >= 600) {
3486 if (ir3_a6xx_fixup_atomic_dests(ir, so)) {
3487 ir3_debug_print(ir, "AFTER ATOMIC FIXUP");
3488 }
3489 }
3490
3491 if (so->type == MESA_SHADER_FRAGMENT)
3492 pack_inlocs(ctx);
3493
3494 /*
3495 * Fixup inputs/outputs to point to the actual registers assigned:
3496 *
3497 * 1) initialize to r63.x (invalid/unused)
3498 * 2) iterate IR level inputs/outputs and update the variants
3499 * inputs/outputs table based on the assigned registers for
3500 * the remaining inputs/outputs.
3501 */
3502
3503 for (unsigned i = 0; i < so->inputs_count; i++)
3504 so->inputs[i].regid = INVALID_REG;
3505 for (unsigned i = 0; i < so->outputs_count; i++)
3506 so->outputs[i].regid = INVALID_REG;
3507
3508 struct ir3_instruction *out;
3509 foreach_output(out, ir) {
3510 assert(out->opc == OPC_META_COLLECT);
3511 unsigned outidx = out->collect.outidx;
3512
3513 so->outputs[outidx].regid = out->regs[0]->num;
3514 so->outputs[outidx].half = !!(out->regs[0]->flags & IR3_REG_HALF);
3515 }
3516
3517 struct ir3_instruction *in;
3518 foreach_input(in, ir) {
3519 assert(in->opc == OPC_META_INPUT);
3520 unsigned inidx = in->input.inidx;
3521
3522 if (pre_assign_inputs && !so->inputs[inidx].sysval) {
3523 if (VALIDREG(so->nonbinning->inputs[inidx].regid)) {
3524 compile_assert(ctx, in->regs[0]->num ==
3525 so->nonbinning->inputs[inidx].regid);
3526 compile_assert(ctx, !!(in->regs[0]->flags & IR3_REG_HALF) ==
3527 so->nonbinning->inputs[inidx].half);
3528 }
3529 so->inputs[inidx].regid = so->nonbinning->inputs[inidx].regid;
3530 so->inputs[inidx].half = so->nonbinning->inputs[inidx].half;
3531 } else {
3532 so->inputs[inidx].regid = in->regs[0]->num;
3533 so->inputs[inidx].half = !!(in->regs[0]->flags & IR3_REG_HALF);
3534 }
3535 }
3536
3537 if (ctx->astc_srgb)
3538 fixup_astc_srgb(ctx);
3539
3540 /* We need to do legalize after (for frag shader's) the "bary.f"
3541 * offsets (inloc) have been assigned.
3542 */
3543 ir3_legalize(ir, so, &max_bary);
3544
3545 ir3_debug_print(ir, "AFTER LEGALIZE");
3546
3547 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3548 * know what we might have to wait on when coming in from VS chsh.
3549 */
3550 if (so->type == MESA_SHADER_TESS_CTRL ||
3551 so->type == MESA_SHADER_GEOMETRY ) {
3552 foreach_block (block, &ir->block_list) {
3553 foreach_instr (instr, &block->instr_list) {
3554 instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
3555 break;
3556 }
3557 }
3558 }
3559
3560 so->branchstack = ctx->max_stack;
3561
3562 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3563 if (so->type == MESA_SHADER_FRAGMENT)
3564 so->total_in = max_bary + 1;
3565
3566 so->max_sun = ir->max_sun;
3567
3568 /* Collect sampling instructions eligible for pre-dispatch. */
3569 collect_tex_prefetches(ctx, ir);
3570
3571 out:
3572 if (ret) {
3573 if (so->ir)
3574 ir3_destroy(so->ir);
3575 so->ir = NULL;
3576 }
3577 ir3_context_free(ctx);
3578
3579 return ret;
3580 }