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freedreno/ir3: Implement tess coord intrinsic
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 ir3_reg_create(mov, 0, 0);
55 src = ir3_reg_create(mov, 0, IR3_REG_SSA | IR3_REG_RELATIV);
56 src->instr = collect;
57 src->size = arrsz;
58 src->array.offset = n;
59
60 ir3_instr_set_address(mov, address);
61
62 return mov;
63 }
64
65 static struct ir3_instruction *
66 create_input_compmask(struct ir3_context *ctx, unsigned n, unsigned compmask)
67 {
68 struct ir3_instruction *in;
69
70 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
71 in->input.sysval = ~0;
72 ir3_reg_create(in, n, 0);
73
74 in->regs[0]->wrmask = compmask;
75
76 return in;
77 }
78
79 static struct ir3_instruction *
80 create_input(struct ir3_context *ctx, unsigned n)
81 {
82 return create_input_compmask(ctx, n, 0x1);
83 }
84
85 static struct ir3_instruction *
86 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
87 {
88 struct ir3_block *block = ctx->block;
89 struct ir3_instruction *instr;
90 /* packed inloc is fixed up later: */
91 struct ir3_instruction *inloc = create_immed(block, n);
92
93 if (use_ldlv) {
94 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
95 instr->cat6.type = TYPE_U32;
96 instr->cat6.iim_val = 1;
97 } else {
98 instr = ir3_BARY_F(block, inloc, 0, ctx->ij_pixel, 0);
99 instr->regs[2]->wrmask = 0x3;
100 }
101
102 return instr;
103 }
104
105 static struct ir3_instruction *
106 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
107 {
108 /* first four vec4 sysval's reserved for UBOs: */
109 /* NOTE: dp is in scalar, but there can be >4 dp components: */
110 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
111 unsigned n = const_state->offsets.driver_param;
112 unsigned r = regid(n + dp / 4, dp % 4);
113 return create_uniform(ctx->block, r);
114 }
115
116 /*
117 * Adreno uses uint rather than having dedicated bool type,
118 * which (potentially) requires some conversion, in particular
119 * when using output of an bool instr to int input, or visa
120 * versa.
121 *
122 * | Adreno | NIR |
123 * -------+---------+-------+-
124 * true | 1 | ~0 |
125 * false | 0 | 0 |
126 *
127 * To convert from an adreno bool (uint) to nir, use:
128 *
129 * absneg.s dst, (neg)src
130 *
131 * To convert back in the other direction:
132 *
133 * absneg.s dst, (abs)arc
134 *
135 * The CP step can clean up the absneg.s that cancel each other
136 * out, and with a slight bit of extra cleverness (to recognize
137 * the instructions which produce either a 0 or 1) can eliminate
138 * the absneg.s's completely when an instruction that wants
139 * 0/1 consumes the result. For example, when a nir 'bcsel'
140 * consumes the result of 'feq'. So we should be able to get by
141 * without a boolean resolve step, and without incuring any
142 * extra penalty in instruction count.
143 */
144
145 /* NIR bool -> native (adreno): */
146 static struct ir3_instruction *
147 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
148 {
149 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
150 }
151
152 /* native (adreno) -> NIR bool: */
153 static struct ir3_instruction *
154 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
155 {
156 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
157 }
158
159 /*
160 * alu/sfu instructions:
161 */
162
163 static struct ir3_instruction *
164 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
165 unsigned src_bitsize, nir_op op)
166 {
167 type_t src_type, dst_type;
168
169 switch (op) {
170 case nir_op_f2f32:
171 case nir_op_f2f16_rtne:
172 case nir_op_f2f16_rtz:
173 case nir_op_f2f16:
174 case nir_op_f2i32:
175 case nir_op_f2i16:
176 case nir_op_f2i8:
177 case nir_op_f2u32:
178 case nir_op_f2u16:
179 case nir_op_f2u8:
180 switch (src_bitsize) {
181 case 32:
182 src_type = TYPE_F32;
183 break;
184 case 16:
185 src_type = TYPE_F16;
186 break;
187 default:
188 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
189 }
190 break;
191
192 case nir_op_i2f32:
193 case nir_op_i2f16:
194 case nir_op_i2i32:
195 case nir_op_i2i16:
196 case nir_op_i2i8:
197 switch (src_bitsize) {
198 case 32:
199 src_type = TYPE_S32;
200 break;
201 case 16:
202 src_type = TYPE_S16;
203 break;
204 case 8:
205 src_type = TYPE_S8;
206 break;
207 default:
208 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
209 }
210 break;
211
212 case nir_op_u2f32:
213 case nir_op_u2f16:
214 case nir_op_u2u32:
215 case nir_op_u2u16:
216 case nir_op_u2u8:
217 switch (src_bitsize) {
218 case 32:
219 src_type = TYPE_U32;
220 break;
221 case 16:
222 src_type = TYPE_U16;
223 break;
224 case 8:
225 src_type = TYPE_U8;
226 break;
227 default:
228 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
229 }
230 break;
231
232 default:
233 ir3_context_error(ctx, "invalid conversion op: %u", op);
234 }
235
236 switch (op) {
237 case nir_op_f2f32:
238 case nir_op_i2f32:
239 case nir_op_u2f32:
240 dst_type = TYPE_F32;
241 break;
242
243 case nir_op_f2f16_rtne:
244 case nir_op_f2f16_rtz:
245 case nir_op_f2f16:
246 /* TODO how to handle rounding mode? */
247 case nir_op_i2f16:
248 case nir_op_u2f16:
249 dst_type = TYPE_F16;
250 break;
251
252 case nir_op_f2i32:
253 case nir_op_i2i32:
254 dst_type = TYPE_S32;
255 break;
256
257 case nir_op_f2i16:
258 case nir_op_i2i16:
259 dst_type = TYPE_S16;
260 break;
261
262 case nir_op_f2i8:
263 case nir_op_i2i8:
264 dst_type = TYPE_S8;
265 break;
266
267 case nir_op_f2u32:
268 case nir_op_u2u32:
269 dst_type = TYPE_U32;
270 break;
271
272 case nir_op_f2u16:
273 case nir_op_u2u16:
274 dst_type = TYPE_U16;
275 break;
276
277 case nir_op_f2u8:
278 case nir_op_u2u8:
279 dst_type = TYPE_U8;
280 break;
281
282 default:
283 ir3_context_error(ctx, "invalid conversion op: %u", op);
284 }
285
286 return ir3_COV(ctx->block, src, src_type, dst_type);
287 }
288
289 static void
290 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
291 {
292 const nir_op_info *info = &nir_op_infos[alu->op];
293 struct ir3_instruction **dst, *src[info->num_inputs];
294 unsigned bs[info->num_inputs]; /* bit size */
295 struct ir3_block *b = ctx->block;
296 unsigned dst_sz, wrmask;
297 type_t dst_type = nir_dest_bit_size(alu->dest.dest) < 32 ?
298 TYPE_U16 : TYPE_U32;
299
300 if (alu->dest.dest.is_ssa) {
301 dst_sz = alu->dest.dest.ssa.num_components;
302 wrmask = (1 << dst_sz) - 1;
303 } else {
304 dst_sz = alu->dest.dest.reg.reg->num_components;
305 wrmask = alu->dest.write_mask;
306 }
307
308 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
309
310 /* Vectors are special in that they have non-scalarized writemasks,
311 * and just take the first swizzle channel for each argument in
312 * order into each writemask channel.
313 */
314 if ((alu->op == nir_op_vec2) ||
315 (alu->op == nir_op_vec3) ||
316 (alu->op == nir_op_vec4)) {
317
318 for (int i = 0; i < info->num_inputs; i++) {
319 nir_alu_src *asrc = &alu->src[i];
320
321 compile_assert(ctx, !asrc->abs);
322 compile_assert(ctx, !asrc->negate);
323
324 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
325 if (!src[i])
326 src[i] = create_immed_typed(ctx->block, 0, dst_type);
327 dst[i] = ir3_MOV(b, src[i], dst_type);
328 }
329
330 ir3_put_dst(ctx, &alu->dest.dest);
331 return;
332 }
333
334 /* We also get mov's with more than one component for mov's so
335 * handle those specially:
336 */
337 if (alu->op == nir_op_mov) {
338 nir_alu_src *asrc = &alu->src[0];
339 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
340
341 for (unsigned i = 0; i < dst_sz; i++) {
342 if (wrmask & (1 << i)) {
343 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
344 } else {
345 dst[i] = NULL;
346 }
347 }
348
349 ir3_put_dst(ctx, &alu->dest.dest);
350 return;
351 }
352
353 /* General case: We can just grab the one used channel per src. */
354 for (int i = 0; i < info->num_inputs; i++) {
355 unsigned chan = ffs(alu->dest.write_mask) - 1;
356 nir_alu_src *asrc = &alu->src[i];
357
358 compile_assert(ctx, !asrc->abs);
359 compile_assert(ctx, !asrc->negate);
360
361 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
362 bs[i] = nir_src_bit_size(asrc->src);
363
364 compile_assert(ctx, src[i]);
365 }
366
367 switch (alu->op) {
368 case nir_op_f2f32:
369 case nir_op_f2f16_rtne:
370 case nir_op_f2f16_rtz:
371 case nir_op_f2f16:
372 case nir_op_f2i32:
373 case nir_op_f2i16:
374 case nir_op_f2i8:
375 case nir_op_f2u32:
376 case nir_op_f2u16:
377 case nir_op_f2u8:
378 case nir_op_i2f32:
379 case nir_op_i2f16:
380 case nir_op_i2i32:
381 case nir_op_i2i16:
382 case nir_op_i2i8:
383 case nir_op_u2f32:
384 case nir_op_u2f16:
385 case nir_op_u2u32:
386 case nir_op_u2u16:
387 case nir_op_u2u8:
388 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
389 break;
390 case nir_op_fquantize2f16:
391 dst[0] = create_cov(ctx,
392 create_cov(ctx, src[0], 32, nir_op_f2f16),
393 16, nir_op_f2f32);
394 break;
395 case nir_op_f2b32:
396 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
397 dst[0]->cat2.condition = IR3_COND_NE;
398 dst[0] = ir3_n2b(b, dst[0]);
399 break;
400 case nir_op_b2f16:
401 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F16);
402 break;
403 case nir_op_b2f32:
404 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
405 break;
406 case nir_op_b2i8:
407 case nir_op_b2i16:
408 case nir_op_b2i32:
409 dst[0] = ir3_b2n(b, src[0]);
410 break;
411 case nir_op_i2b32:
412 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
413 dst[0]->cat2.condition = IR3_COND_NE;
414 dst[0] = ir3_n2b(b, dst[0]);
415 break;
416
417 case nir_op_fneg:
418 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
419 break;
420 case nir_op_fabs:
421 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
422 break;
423 case nir_op_fmax:
424 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
425 break;
426 case nir_op_fmin:
427 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
428 break;
429 case nir_op_fsat:
430 /* if there is just a single use of the src, and it supports
431 * (sat) bit, we can just fold the (sat) flag back to the
432 * src instruction and create a mov. This is easier for cp
433 * to eliminate.
434 *
435 * TODO probably opc_cat==4 is ok too
436 */
437 if (alu->src[0].src.is_ssa &&
438 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
439 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
440 src[0]->flags |= IR3_INSTR_SAT;
441 dst[0] = ir3_MOV(b, src[0], dst_type);
442 } else {
443 /* otherwise generate a max.f that saturates.. blob does
444 * similar (generating a cat2 mov using max.f)
445 */
446 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
447 dst[0]->flags |= IR3_INSTR_SAT;
448 }
449 break;
450 case nir_op_fmul:
451 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
452 break;
453 case nir_op_fadd:
454 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
455 break;
456 case nir_op_fsub:
457 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
458 break;
459 case nir_op_ffma:
460 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
461 break;
462 case nir_op_fddx:
463 case nir_op_fddx_coarse:
464 dst[0] = ir3_DSX(b, src[0], 0);
465 dst[0]->cat5.type = TYPE_F32;
466 break;
467 case nir_op_fddy:
468 case nir_op_fddy_coarse:
469 dst[0] = ir3_DSY(b, src[0], 0);
470 dst[0]->cat5.type = TYPE_F32;
471 break;
472 break;
473 case nir_op_flt32:
474 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
475 dst[0]->cat2.condition = IR3_COND_LT;
476 dst[0] = ir3_n2b(b, dst[0]);
477 break;
478 case nir_op_fge32:
479 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
480 dst[0]->cat2.condition = IR3_COND_GE;
481 dst[0] = ir3_n2b(b, dst[0]);
482 break;
483 case nir_op_feq32:
484 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
485 dst[0]->cat2.condition = IR3_COND_EQ;
486 dst[0] = ir3_n2b(b, dst[0]);
487 break;
488 case nir_op_fne32:
489 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
490 dst[0]->cat2.condition = IR3_COND_NE;
491 dst[0] = ir3_n2b(b, dst[0]);
492 break;
493 case nir_op_fceil:
494 dst[0] = ir3_CEIL_F(b, src[0], 0);
495 break;
496 case nir_op_ffloor:
497 dst[0] = ir3_FLOOR_F(b, src[0], 0);
498 break;
499 case nir_op_ftrunc:
500 dst[0] = ir3_TRUNC_F(b, src[0], 0);
501 break;
502 case nir_op_fround_even:
503 dst[0] = ir3_RNDNE_F(b, src[0], 0);
504 break;
505 case nir_op_fsign:
506 dst[0] = ir3_SIGN_F(b, src[0], 0);
507 break;
508
509 case nir_op_fsin:
510 dst[0] = ir3_SIN(b, src[0], 0);
511 break;
512 case nir_op_fcos:
513 dst[0] = ir3_COS(b, src[0], 0);
514 break;
515 case nir_op_frsq:
516 dst[0] = ir3_RSQ(b, src[0], 0);
517 break;
518 case nir_op_frcp:
519 dst[0] = ir3_RCP(b, src[0], 0);
520 break;
521 case nir_op_flog2:
522 dst[0] = ir3_LOG2(b, src[0], 0);
523 break;
524 case nir_op_fexp2:
525 dst[0] = ir3_EXP2(b, src[0], 0);
526 break;
527 case nir_op_fsqrt:
528 dst[0] = ir3_SQRT(b, src[0], 0);
529 break;
530
531 case nir_op_iabs:
532 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
533 break;
534 case nir_op_iadd:
535 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
536 break;
537 case nir_op_iand:
538 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
539 break;
540 case nir_op_imax:
541 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
542 break;
543 case nir_op_umax:
544 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
545 break;
546 case nir_op_imin:
547 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
548 break;
549 case nir_op_umin:
550 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
551 break;
552 case nir_op_umul_low:
553 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
554 break;
555 case nir_op_imadsh_mix16:
556 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
557 break;
558 case nir_op_imad24_ir3:
559 dst[0] = ir3_MAD_S24(b, src[0], 0, src[1], 0, src[2], 0);
560 break;
561 case nir_op_imul24:
562 dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
563 break;
564 case nir_op_ineg:
565 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
566 break;
567 case nir_op_inot:
568 dst[0] = ir3_NOT_B(b, src[0], 0);
569 break;
570 case nir_op_ior:
571 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
572 break;
573 case nir_op_ishl:
574 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
575 break;
576 case nir_op_ishr:
577 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
578 break;
579 case nir_op_isub:
580 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
581 break;
582 case nir_op_ixor:
583 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
584 break;
585 case nir_op_ushr:
586 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
587 break;
588 case nir_op_ilt32:
589 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
590 dst[0]->cat2.condition = IR3_COND_LT;
591 dst[0] = ir3_n2b(b, dst[0]);
592 break;
593 case nir_op_ige32:
594 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
595 dst[0]->cat2.condition = IR3_COND_GE;
596 dst[0] = ir3_n2b(b, dst[0]);
597 break;
598 case nir_op_ieq32:
599 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
600 dst[0]->cat2.condition = IR3_COND_EQ;
601 dst[0] = ir3_n2b(b, dst[0]);
602 break;
603 case nir_op_ine32:
604 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
605 dst[0]->cat2.condition = IR3_COND_NE;
606 dst[0] = ir3_n2b(b, dst[0]);
607 break;
608 case nir_op_ult32:
609 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
610 dst[0]->cat2.condition = IR3_COND_LT;
611 dst[0] = ir3_n2b(b, dst[0]);
612 break;
613 case nir_op_uge32:
614 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
615 dst[0]->cat2.condition = IR3_COND_GE;
616 dst[0] = ir3_n2b(b, dst[0]);
617 break;
618
619 case nir_op_b32csel: {
620 struct ir3_instruction *cond = ir3_b2n(b, src[0]);
621 compile_assert(ctx, bs[1] == bs[2]);
622 /* the boolean condition is 32b even if src[1] and src[2] are
623 * half-precision, but sel.b16 wants all three src's to be the
624 * same type.
625 */
626 if (bs[1] < 32)
627 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
628 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
629 break;
630 }
631 case nir_op_bit_count: {
632 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
633 // double check on earlier gen's. Once half-precision support is
634 // in place, this should probably move to a NIR lowering pass:
635 struct ir3_instruction *hi, *lo;
636
637 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
638 TYPE_U32, TYPE_U16);
639 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
640
641 hi = ir3_CBITS_B(b, hi, 0);
642 lo = ir3_CBITS_B(b, lo, 0);
643
644 // TODO maybe the builders should default to making dst half-precision
645 // if the src's were half precision, to make this less awkward.. otoh
646 // we should probably just do this lowering in NIR.
647 hi->regs[0]->flags |= IR3_REG_HALF;
648 lo->regs[0]->flags |= IR3_REG_HALF;
649
650 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
651 dst[0]->regs[0]->flags |= IR3_REG_HALF;
652 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
653 break;
654 }
655 case nir_op_ifind_msb: {
656 struct ir3_instruction *cmp;
657 dst[0] = ir3_CLZ_S(b, src[0], 0);
658 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
659 cmp->cat2.condition = IR3_COND_GE;
660 dst[0] = ir3_SEL_B32(b,
661 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
662 cmp, 0, dst[0], 0);
663 break;
664 }
665 case nir_op_ufind_msb:
666 dst[0] = ir3_CLZ_B(b, src[0], 0);
667 dst[0] = ir3_SEL_B32(b,
668 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
669 src[0], 0, dst[0], 0);
670 break;
671 case nir_op_find_lsb:
672 dst[0] = ir3_BFREV_B(b, src[0], 0);
673 dst[0] = ir3_CLZ_B(b, dst[0], 0);
674 break;
675 case nir_op_bitfield_reverse:
676 dst[0] = ir3_BFREV_B(b, src[0], 0);
677 break;
678
679 default:
680 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
681 nir_op_infos[alu->op].name);
682 break;
683 }
684
685 ir3_put_dst(ctx, &alu->dest.dest);
686 }
687
688 /* handles direct/indirect UBO reads: */
689 static void
690 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
691 struct ir3_instruction **dst)
692 {
693 struct ir3_block *b = ctx->block;
694 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
695 /* UBO addresses are the first driver params, but subtract 2 here to
696 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
697 * is the uniforms: */
698 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
699 unsigned ubo = regid(const_state->offsets.ubo, 0) - 2;
700 const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
701
702 int off = 0;
703
704 /* First src is ubo index, which could either be an immed or not: */
705 src0 = ir3_get_src(ctx, &intr->src[0])[0];
706 if (is_same_type_mov(src0) &&
707 (src0->regs[1]->flags & IR3_REG_IMMED)) {
708 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
709 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
710 } else {
711 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, ptrsz));
712 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, ptrsz));
713
714 /* NOTE: since relative addressing is used, make sure constlen is
715 * at least big enough to cover all the UBO addresses, since the
716 * assembler won't know what the max address reg is.
717 */
718 ctx->so->constlen = MAX2(ctx->so->constlen,
719 const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
720 }
721
722 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
723 addr = base_lo;
724
725 if (nir_src_is_const(intr->src[1])) {
726 off += nir_src_as_uint(intr->src[1]);
727 } else {
728 /* For load_ubo_indirect, second src is indirect offset: */
729 src1 = ir3_get_src(ctx, &intr->src[1])[0];
730
731 /* and add offset to addr: */
732 addr = ir3_ADD_S(b, addr, 0, src1, 0);
733 }
734
735 /* if offset is to large to encode in the ldg, split it out: */
736 if ((off + (intr->num_components * 4)) > 1024) {
737 /* split out the minimal amount to improve the odds that
738 * cp can fit the immediate in the add.s instruction:
739 */
740 unsigned off2 = off + (intr->num_components * 4) - 1024;
741 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
742 off -= off2;
743 }
744
745 if (ptrsz == 2) {
746 struct ir3_instruction *carry;
747
748 /* handle 32b rollover, ie:
749 * if (addr < base_lo)
750 * base_hi++
751 */
752 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
753 carry->cat2.condition = IR3_COND_LT;
754 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
755
756 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
757 }
758
759 for (int i = 0; i < intr->num_components; i++) {
760 struct ir3_instruction *load =
761 ir3_LDG(b, addr, 0, create_immed(b, 1), 0, /* num components */
762 create_immed(b, off + i * 4), 0);
763 load->cat6.type = TYPE_U32;
764 dst[i] = load;
765 }
766 }
767
768 /* src[] = { block_index } */
769 static void
770 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
771 struct ir3_instruction **dst)
772 {
773 /* SSBO size stored as a const starting at ssbo_sizes: */
774 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
775 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
776 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
777 const_state->ssbo_size.off[blk_idx];
778
779 debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
780
781 dst[0] = create_uniform(ctx->block, idx);
782 }
783
784 /* src[] = { offset }. const_index[] = { base } */
785 static void
786 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
787 struct ir3_instruction **dst)
788 {
789 struct ir3_block *b = ctx->block;
790 struct ir3_instruction *ldl, *offset;
791 unsigned base;
792
793 offset = ir3_get_src(ctx, &intr->src[0])[0];
794 base = nir_intrinsic_base(intr);
795
796 ldl = ir3_LDL(b, offset, 0,
797 create_immed(b, intr->num_components), 0,
798 create_immed(b, base), 0);
799
800 ldl->cat6.type = utype_dst(intr->dest);
801 ldl->regs[0]->wrmask = MASK(intr->num_components);
802
803 ldl->barrier_class = IR3_BARRIER_SHARED_R;
804 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
805
806 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
807 }
808
809 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
810 static void
811 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
812 {
813 struct ir3_block *b = ctx->block;
814 struct ir3_instruction *stl, *offset;
815 struct ir3_instruction * const *value;
816 unsigned base, wrmask;
817
818 value = ir3_get_src(ctx, &intr->src[0]);
819 offset = ir3_get_src(ctx, &intr->src[1])[0];
820
821 base = nir_intrinsic_base(intr);
822 wrmask = nir_intrinsic_write_mask(intr);
823
824 /* Combine groups of consecutive enabled channels in one write
825 * message. We use ffs to find the first enabled channel and then ffs on
826 * the bit-inverse, down-shifted writemask to determine the length of
827 * the block of enabled bits.
828 *
829 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
830 */
831 while (wrmask) {
832 unsigned first_component = ffs(wrmask) - 1;
833 unsigned length = ffs(~(wrmask >> first_component)) - 1;
834
835 stl = ir3_STL(b, offset, 0,
836 ir3_create_collect(ctx, &value[first_component], length), 0,
837 create_immed(b, length), 0);
838 stl->cat6.dst_offset = first_component + base;
839 stl->cat6.type = utype_src(intr->src[0]);
840 stl->barrier_class = IR3_BARRIER_SHARED_W;
841 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
842
843 array_insert(b, b->keeps, stl);
844
845 /* Clear the bits in the writemask that we just wrote, then try
846 * again to see if more channels are left.
847 */
848 wrmask &= (15 << (first_component + length));
849 }
850 }
851
852 /* src[] = { offset }. const_index[] = { base } */
853 static void
854 emit_intrinsic_load_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr,
855 struct ir3_instruction **dst)
856 {
857 struct ir3_block *b = ctx->block;
858 struct ir3_instruction *load, *offset;
859 unsigned base;
860
861 offset = ir3_get_src(ctx, &intr->src[0])[0];
862 base = nir_intrinsic_base(intr);
863
864 load = ir3_LDLW(b, offset, 0,
865 create_immed(b, intr->num_components), 0,
866 create_immed(b, base), 0);
867
868 load->cat6.type = utype_dst(intr->dest);
869 load->regs[0]->wrmask = MASK(intr->num_components);
870
871 load->barrier_class = IR3_BARRIER_SHARED_R;
872 load->barrier_conflict = IR3_BARRIER_SHARED_W;
873
874 ir3_split_dest(b, dst, load, 0, intr->num_components);
875 }
876
877 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
878 static void
879 emit_intrinsic_store_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr)
880 {
881 struct ir3_block *b = ctx->block;
882 struct ir3_instruction *store, *offset;
883 struct ir3_instruction * const *value;
884 unsigned base, wrmask;
885
886 value = ir3_get_src(ctx, &intr->src[0]);
887 offset = ir3_get_src(ctx, &intr->src[1])[0];
888
889 base = nir_intrinsic_base(intr);
890 wrmask = nir_intrinsic_write_mask(intr);
891
892 /* Combine groups of consecutive enabled channels in one write
893 * message. We use ffs to find the first enabled channel and then ffs on
894 * the bit-inverse, down-shifted writemask to determine the length of
895 * the block of enabled bits.
896 *
897 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
898 */
899 while (wrmask) {
900 unsigned first_component = ffs(wrmask) - 1;
901 unsigned length = ffs(~(wrmask >> first_component)) - 1;
902
903 store = ir3_STLW(b, offset, 0,
904 ir3_create_collect(ctx, &value[first_component], length), 0,
905 create_immed(b, length), 0);
906
907 store->cat6.dst_offset = first_component + base;
908 store->cat6.type = utype_src(intr->src[0]);
909 store->barrier_class = IR3_BARRIER_SHARED_W;
910 store->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
911
912 array_insert(b, b->keeps, store);
913
914 /* Clear the bits in the writemask that we just wrote, then try
915 * again to see if more channels are left.
916 */
917 wrmask &= (15 << (first_component + length));
918 }
919 }
920
921 /*
922 * CS shared variable atomic intrinsics
923 *
924 * All of the shared variable atomic memory operations read a value from
925 * memory, compute a new value using one of the operations below, write the
926 * new value to memory, and return the original value read.
927 *
928 * All operations take 2 sources except CompSwap that takes 3. These
929 * sources represent:
930 *
931 * 0: The offset into the shared variable storage region that the atomic
932 * operation will operate on.
933 * 1: The data parameter to the atomic function (i.e. the value to add
934 * in shared_atomic_add, etc).
935 * 2: For CompSwap only: the second data parameter.
936 */
937 static struct ir3_instruction *
938 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
939 {
940 struct ir3_block *b = ctx->block;
941 struct ir3_instruction *atomic, *src0, *src1;
942 type_t type = TYPE_U32;
943
944 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
945 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
946
947 switch (intr->intrinsic) {
948 case nir_intrinsic_shared_atomic_add:
949 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
950 break;
951 case nir_intrinsic_shared_atomic_imin:
952 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
953 type = TYPE_S32;
954 break;
955 case nir_intrinsic_shared_atomic_umin:
956 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
957 break;
958 case nir_intrinsic_shared_atomic_imax:
959 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
960 type = TYPE_S32;
961 break;
962 case nir_intrinsic_shared_atomic_umax:
963 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
964 break;
965 case nir_intrinsic_shared_atomic_and:
966 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
967 break;
968 case nir_intrinsic_shared_atomic_or:
969 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
970 break;
971 case nir_intrinsic_shared_atomic_xor:
972 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
973 break;
974 case nir_intrinsic_shared_atomic_exchange:
975 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
976 break;
977 case nir_intrinsic_shared_atomic_comp_swap:
978 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
979 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
980 ir3_get_src(ctx, &intr->src[2])[0],
981 src1,
982 }, 2);
983 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
984 break;
985 default:
986 unreachable("boo");
987 }
988
989 atomic->cat6.iim_val = 1;
990 atomic->cat6.d = 1;
991 atomic->cat6.type = type;
992 atomic->barrier_class = IR3_BARRIER_SHARED_W;
993 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
994
995 /* even if nothing consume the result, we can't DCE the instruction: */
996 array_insert(b, b->keeps, atomic);
997
998 return atomic;
999 }
1000
1001 /* TODO handle actual indirect/dynamic case.. which is going to be weird
1002 * to handle with the image_mapping table..
1003 */
1004 static struct ir3_instruction *
1005 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1006 {
1007 unsigned slot = ir3_get_image_slot(nir_src_as_deref(intr->src[0]));
1008 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
1009 struct ir3_instruction *texture, *sampler;
1010
1011 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1012 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1013
1014 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1015 sampler,
1016 texture,
1017 }, 2);
1018 }
1019
1020 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1021 static void
1022 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1023 struct ir3_instruction **dst)
1024 {
1025 struct ir3_block *b = ctx->block;
1026 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1027 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
1028 struct ir3_instruction *sam;
1029 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
1030 struct ir3_instruction *coords[4];
1031 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
1032 type_t type = ir3_get_image_type(var);
1033
1034 /* hmm, this seems a bit odd, but it is what blob does and (at least
1035 * a5xx) just faults on bogus addresses otherwise:
1036 */
1037 if (flags & IR3_INSTR_3D) {
1038 flags &= ~IR3_INSTR_3D;
1039 flags |= IR3_INSTR_A;
1040 }
1041
1042 for (unsigned i = 0; i < ncoords; i++)
1043 coords[i] = src0[i];
1044
1045 if (ncoords == 1)
1046 coords[ncoords++] = create_immed(b, 0);
1047
1048 sam = ir3_SAM(b, OPC_ISAM, type, 0b1111, flags,
1049 samp_tex, ir3_create_collect(ctx, coords, ncoords), NULL);
1050
1051 sam->barrier_class = IR3_BARRIER_IMAGE_R;
1052 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
1053
1054 ir3_split_dest(b, dst, sam, 0, 4);
1055 }
1056
1057 static void
1058 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1059 struct ir3_instruction **dst)
1060 {
1061 struct ir3_block *b = ctx->block;
1062 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1063 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
1064 struct ir3_instruction *sam, *lod;
1065 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
1066
1067 lod = create_immed(b, 0);
1068 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
1069 samp_tex, lod, NULL);
1070
1071 /* Array size actually ends up in .w rather than .z. This doesn't
1072 * matter for miplevel 0, but for higher mips the value in z is
1073 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1074 * returned, which means that we have to add 1 to it for arrays for
1075 * a3xx.
1076 *
1077 * Note use a temporary dst and then copy, since the size of the dst
1078 * array that is passed in is based on nir's understanding of the
1079 * result size, not the hardware's
1080 */
1081 struct ir3_instruction *tmp[4];
1082
1083 ir3_split_dest(b, tmp, sam, 0, 4);
1084
1085 /* get_size instruction returns size in bytes instead of texels
1086 * for imageBuffer, so we need to divide it by the pixel size
1087 * of the image format.
1088 *
1089 * TODO: This is at least true on a5xx. Check other gens.
1090 */
1091 enum glsl_sampler_dim dim =
1092 glsl_get_sampler_dim(glsl_without_array(var->type));
1093 if (dim == GLSL_SAMPLER_DIM_BUF) {
1094 /* Since all the possible values the divisor can take are
1095 * power-of-two (4, 8, or 16), the division is implemented
1096 * as a shift-right.
1097 * During shader setup, the log2 of the image format's
1098 * bytes-per-pixel should have been emitted in 2nd slot of
1099 * image_dims. See ir3_shader::emit_image_dims().
1100 */
1101 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
1102 unsigned cb = regid(const_state->offsets.image_dims, 0) +
1103 const_state->image_dims.off[var->data.driver_location];
1104 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1105
1106 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1107 }
1108
1109 for (unsigned i = 0; i < ncoords; i++)
1110 dst[i] = tmp[i];
1111
1112 if (flags & IR3_INSTR_A) {
1113 if (ctx->compiler->levels_add_one) {
1114 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1115 } else {
1116 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1117 }
1118 }
1119 }
1120
1121 static void
1122 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1123 {
1124 struct ir3_block *b = ctx->block;
1125 struct ir3_instruction *barrier;
1126
1127 switch (intr->intrinsic) {
1128 case nir_intrinsic_barrier:
1129 barrier = ir3_BAR(b);
1130 barrier->cat7.g = true;
1131 barrier->cat7.l = true;
1132 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1133 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1134 break;
1135 case nir_intrinsic_memory_barrier:
1136 barrier = ir3_FENCE(b);
1137 barrier->cat7.g = true;
1138 barrier->cat7.r = true;
1139 barrier->cat7.w = true;
1140 barrier->cat7.l = true;
1141 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1142 IR3_BARRIER_BUFFER_W;
1143 barrier->barrier_conflict =
1144 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1145 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1146 break;
1147 case nir_intrinsic_memory_barrier_atomic_counter:
1148 case nir_intrinsic_memory_barrier_buffer:
1149 barrier = ir3_FENCE(b);
1150 barrier->cat7.g = true;
1151 barrier->cat7.r = true;
1152 barrier->cat7.w = true;
1153 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1154 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1155 IR3_BARRIER_BUFFER_W;
1156 break;
1157 case nir_intrinsic_memory_barrier_image:
1158 // TODO double check if this should have .g set
1159 barrier = ir3_FENCE(b);
1160 barrier->cat7.g = true;
1161 barrier->cat7.r = true;
1162 barrier->cat7.w = true;
1163 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1164 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1165 IR3_BARRIER_IMAGE_W;
1166 break;
1167 case nir_intrinsic_memory_barrier_shared:
1168 barrier = ir3_FENCE(b);
1169 barrier->cat7.g = true;
1170 barrier->cat7.l = true;
1171 barrier->cat7.r = true;
1172 barrier->cat7.w = true;
1173 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1174 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1175 IR3_BARRIER_SHARED_W;
1176 break;
1177 case nir_intrinsic_group_memory_barrier:
1178 barrier = ir3_FENCE(b);
1179 barrier->cat7.g = true;
1180 barrier->cat7.l = true;
1181 barrier->cat7.r = true;
1182 barrier->cat7.w = true;
1183 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1184 IR3_BARRIER_IMAGE_W |
1185 IR3_BARRIER_BUFFER_W;
1186 barrier->barrier_conflict =
1187 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1188 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1189 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1190 break;
1191 default:
1192 unreachable("boo");
1193 }
1194
1195 /* make sure barrier doesn't get DCE'd */
1196 array_insert(b, b->keeps, barrier);
1197 }
1198
1199 static void add_sysval_input_compmask(struct ir3_context *ctx,
1200 gl_system_value slot, unsigned compmask,
1201 struct ir3_instruction *instr)
1202 {
1203 struct ir3_shader_variant *so = ctx->so;
1204 unsigned r = regid(so->inputs_count, 0);
1205 unsigned n = so->inputs_count++;
1206
1207 assert(instr->opc == OPC_META_INPUT);
1208 instr->input.sysval = slot;
1209
1210 so->inputs[n].sysval = true;
1211 so->inputs[n].slot = slot;
1212 so->inputs[n].compmask = compmask;
1213 so->inputs[n].regid = r;
1214 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1215 so->total_in++;
1216
1217 ctx->ir->ninputs = MAX2(ctx->ir->ninputs, r + 1);
1218 ctx->ir->inputs[r] = instr;
1219 }
1220
1221 static void add_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1222 struct ir3_instruction *instr)
1223 {
1224 add_sysval_input_compmask(ctx, slot, 0x1, instr);
1225 }
1226
1227 static struct ir3_instruction *
1228 get_barycentric_centroid(struct ir3_context *ctx)
1229 {
1230 if (!ctx->ij_centroid) {
1231 struct ir3_instruction *xy[2];
1232 struct ir3_instruction *ij;
1233
1234 ij = create_input_compmask(ctx, 0, 0x3);
1235 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1236
1237 ctx->ij_centroid = ir3_create_collect(ctx, xy, 2);
1238
1239 add_sysval_input_compmask(ctx,
1240 SYSTEM_VALUE_BARYCENTRIC_CENTROID,
1241 0x3, ij);
1242 }
1243
1244 return ctx->ij_centroid;
1245 }
1246
1247 static struct ir3_instruction *
1248 get_barycentric_sample(struct ir3_context *ctx)
1249 {
1250 if (!ctx->ij_sample) {
1251 struct ir3_instruction *xy[2];
1252 struct ir3_instruction *ij;
1253
1254 ij = create_input_compmask(ctx, 0, 0x3);
1255 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1256
1257 ctx->ij_sample = ir3_create_collect(ctx, xy, 2);
1258
1259 add_sysval_input_compmask(ctx,
1260 SYSTEM_VALUE_BARYCENTRIC_SAMPLE,
1261 0x3, ij);
1262 }
1263
1264 return ctx->ij_sample;
1265 }
1266
1267 static struct ir3_instruction *
1268 get_barycentric_pixel(struct ir3_context *ctx)
1269 {
1270 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1271 * this to create ij_pixel only on demand:
1272 */
1273 return ctx->ij_pixel;
1274 }
1275
1276 static struct ir3_instruction *
1277 get_frag_coord(struct ir3_context *ctx)
1278 {
1279 if (!ctx->frag_coord) {
1280 struct ir3_block *b = ctx->block;
1281 struct ir3_instruction *xyzw[4];
1282 struct ir3_instruction *hw_frag_coord;
1283
1284 hw_frag_coord = create_input_compmask(ctx, 0, 0xf);
1285 ir3_split_dest(ctx->block, xyzw, hw_frag_coord, 0, 4);
1286
1287 /* for frag_coord.xy, we get unsigned values.. we need
1288 * to subtract (integer) 8 and divide by 16 (right-
1289 * shift by 4) then convert to float:
1290 *
1291 * sub.s tmp, src, 8
1292 * shr.b tmp, tmp, 4
1293 * mov.u32f32 dst, tmp
1294 *
1295 */
1296 for (int i = 0; i < 2; i++) {
1297 xyzw[i] = ir3_SUB_S(b, xyzw[i], 0,
1298 create_immed(b, 8), 0);
1299 xyzw[i] = ir3_SHR_B(b, xyzw[i], 0,
1300 create_immed(b, 4), 0);
1301 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1302 }
1303
1304 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1305
1306 add_sysval_input_compmask(ctx,
1307 SYSTEM_VALUE_FRAG_COORD,
1308 0xf, hw_frag_coord);
1309
1310 ctx->so->frag_coord = true;
1311 }
1312
1313 return ctx->frag_coord;
1314 }
1315
1316 static void
1317 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1318 {
1319 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1320 struct ir3_instruction **dst;
1321 struct ir3_instruction * const *src;
1322 struct ir3_block *b = ctx->block;
1323 int idx, comp;
1324
1325 if (info->has_dest) {
1326 unsigned n = nir_intrinsic_dest_components(intr);
1327 dst = ir3_get_dst(ctx, &intr->dest, n);
1328 } else {
1329 dst = NULL;
1330 }
1331
1332 const unsigned primitive_param = ctx->so->shader->const_state.offsets.primitive_param * 4;
1333 const unsigned primitive_map = ctx->so->shader->const_state.offsets.primitive_map * 4;
1334
1335 switch (intr->intrinsic) {
1336 case nir_intrinsic_load_uniform:
1337 idx = nir_intrinsic_base(intr);
1338 if (nir_src_is_const(intr->src[0])) {
1339 idx += nir_src_as_uint(intr->src[0]);
1340 for (int i = 0; i < intr->num_components; i++) {
1341 dst[i] = create_uniform_typed(b, idx + i,
1342 nir_dest_bit_size(intr->dest) < 32 ? TYPE_F16 : TYPE_F32);
1343 }
1344 } else {
1345 src = ir3_get_src(ctx, &intr->src[0]);
1346 for (int i = 0; i < intr->num_components; i++) {
1347 dst[i] = create_uniform_indirect(b, idx + i,
1348 ir3_get_addr(ctx, src[0], 1));
1349 }
1350 /* NOTE: if relative addressing is used, we set
1351 * constlen in the compiler (to worst-case value)
1352 * since we don't know in the assembler what the max
1353 * addr reg value can be:
1354 */
1355 ctx->so->constlen = MAX2(ctx->so->constlen,
1356 ctx->so->shader->ubo_state.size / 16);
1357 }
1358 break;
1359
1360 case nir_intrinsic_load_vs_primitive_stride_ir3:
1361 dst[0] = create_uniform(b, primitive_param + 0);
1362 break;
1363 case nir_intrinsic_load_vs_vertex_stride_ir3:
1364 dst[0] = create_uniform(b, primitive_param + 1);
1365 break;
1366 case nir_intrinsic_load_hs_patch_stride_ir3:
1367 dst[0] = create_uniform(b, primitive_param + 2);
1368 break;
1369 case nir_intrinsic_load_patch_vertices_in:
1370 dst[0] = create_uniform(b, primitive_param + 3);
1371 break;
1372 case nir_intrinsic_load_tess_param_base_ir3:
1373 dst[0] = create_uniform(b, primitive_param + 4);
1374 dst[1] = create_uniform(b, primitive_param + 5);
1375 break;
1376 case nir_intrinsic_load_tess_factor_base_ir3:
1377 dst[0] = create_uniform(b, primitive_param + 6);
1378 dst[1] = create_uniform(b, primitive_param + 7);
1379 break;
1380
1381 case nir_intrinsic_load_primitive_location_ir3:
1382 idx = nir_intrinsic_driver_location(intr);
1383 dst[0] = create_uniform(b, primitive_map + idx);
1384 break;
1385
1386 case nir_intrinsic_load_gs_header_ir3:
1387 dst[0] = ctx->gs_header;
1388 break;
1389 case nir_intrinsic_load_tcs_header_ir3:
1390 dst[0] = ctx->tcs_header;
1391 break;
1392
1393 case nir_intrinsic_load_primitive_id:
1394 dst[0] = ctx->primitive_id;
1395 break;
1396
1397 case nir_intrinsic_load_tess_coord:
1398 if (!ctx->tess_coord) {
1399 ctx->tess_coord = create_input_compmask(ctx, 0, 0x3);
1400 add_sysval_input_compmask(ctx, SYSTEM_VALUE_TESS_COORD,
1401 0x3, ctx->tess_coord);
1402 }
1403 ir3_split_dest(b, dst, ctx->tess_coord, 0, 2);
1404
1405 /* Unused, but ir3_put_dst() below wants to free something */
1406 dst[2] = create_immed(b, 0);
1407 break;
1408
1409 case nir_intrinsic_store_global_ir3: {
1410 struct ir3_instruction *value, *addr, *offset;
1411
1412 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1413 ir3_get_src(ctx, &intr->src[1])[0],
1414 ir3_get_src(ctx, &intr->src[1])[1]
1415 }, 2);
1416
1417 offset = ir3_get_src(ctx, &intr->src[2])[0];
1418
1419 value = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]),
1420 intr->num_components);
1421
1422 struct ir3_instruction *stg =
1423 ir3_STG_G(ctx->block, addr, 0, value, 0,
1424 create_immed(ctx->block, intr->num_components), 0, offset, 0);
1425 stg->cat6.type = TYPE_U32;
1426 stg->cat6.iim_val = 1;
1427
1428 array_insert(b, b->keeps, stg);
1429
1430 stg->barrier_class = IR3_BARRIER_BUFFER_W;
1431 stg->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1432 break;
1433 }
1434
1435 case nir_intrinsic_load_global_ir3: {
1436 struct ir3_instruction *addr, *offset;
1437
1438 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1439 ir3_get_src(ctx, &intr->src[0])[0],
1440 ir3_get_src(ctx, &intr->src[0])[1]
1441 }, 2);
1442
1443 offset = ir3_get_src(ctx, &intr->src[1])[0];
1444
1445 struct ir3_instruction *load =
1446 ir3_LDG(b, addr, 0, create_immed(ctx->block, intr->num_components),
1447 0, offset, 0);
1448 load->cat6.type = TYPE_U32;
1449 load->regs[0]->wrmask = MASK(intr->num_components);
1450
1451 load->barrier_class = IR3_BARRIER_BUFFER_R;
1452 load->barrier_conflict = IR3_BARRIER_BUFFER_W;
1453
1454 ir3_split_dest(b, dst, load, 0, intr->num_components);
1455 break;
1456 }
1457
1458 case nir_intrinsic_load_ubo:
1459 emit_intrinsic_load_ubo(ctx, intr, dst);
1460 break;
1461 case nir_intrinsic_load_frag_coord:
1462 ir3_split_dest(b, dst, get_frag_coord(ctx), 0, 4);
1463 break;
1464 case nir_intrinsic_load_sample_pos_from_id: {
1465 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1466 * but that doesn't seem necessary.
1467 */
1468 struct ir3_instruction *offset =
1469 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1470 offset->regs[0]->wrmask = 0x3;
1471 offset->cat5.type = TYPE_F32;
1472
1473 ir3_split_dest(b, dst, offset, 0, 2);
1474
1475 break;
1476 }
1477 case nir_intrinsic_load_size_ir3:
1478 if (!ctx->ij_size) {
1479 ctx->ij_size = create_input(ctx, 0);
1480
1481 add_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_SIZE,
1482 ctx->ij_size);
1483 }
1484 dst[0] = ctx->ij_size;
1485 break;
1486 case nir_intrinsic_load_barycentric_centroid:
1487 ir3_split_dest(b, dst, get_barycentric_centroid(ctx), 0, 2);
1488 break;
1489 case nir_intrinsic_load_barycentric_sample:
1490 if (ctx->so->key.msaa) {
1491 ir3_split_dest(b, dst, get_barycentric_sample(ctx), 0, 2);
1492 } else {
1493 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1494 }
1495 break;
1496 case nir_intrinsic_load_barycentric_pixel:
1497 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1498 break;
1499 case nir_intrinsic_load_interpolated_input:
1500 idx = nir_intrinsic_base(intr);
1501 comp = nir_intrinsic_component(intr);
1502 src = ir3_get_src(ctx, &intr->src[0]);
1503 if (nir_src_is_const(intr->src[1])) {
1504 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1505 idx += nir_src_as_uint(intr->src[1]);
1506 for (int i = 0; i < intr->num_components; i++) {
1507 unsigned inloc = idx * 4 + i + comp;
1508 if (ctx->so->inputs[idx].bary &&
1509 !ctx->so->inputs[idx].use_ldlv) {
1510 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1511 } else {
1512 /* for non-varyings use the pre-setup input, since
1513 * that is easier than mapping things back to a
1514 * nir_variable to figure out what it is.
1515 */
1516 dst[i] = ctx->ir->inputs[inloc];
1517 }
1518 }
1519 } else {
1520 ir3_context_error(ctx, "unhandled");
1521 }
1522 break;
1523 case nir_intrinsic_load_input:
1524 idx = nir_intrinsic_base(intr);
1525 comp = nir_intrinsic_component(intr);
1526 if (nir_src_is_const(intr->src[0])) {
1527 idx += nir_src_as_uint(intr->src[0]);
1528 for (int i = 0; i < intr->num_components; i++) {
1529 unsigned n = idx * 4 + i + comp;
1530 dst[i] = ctx->ir->inputs[n];
1531 compile_assert(ctx, ctx->ir->inputs[n]);
1532 }
1533 } else {
1534 src = ir3_get_src(ctx, &intr->src[0]);
1535 struct ir3_instruction *collect =
1536 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ir->ninputs);
1537 struct ir3_instruction *addr = ir3_get_addr(ctx, src[0], 4);
1538 for (int i = 0; i < intr->num_components; i++) {
1539 unsigned n = idx * 4 + i + comp;
1540 dst[i] = create_indirect_load(ctx, ctx->ir->ninputs,
1541 n, addr, collect);
1542 }
1543 }
1544 break;
1545 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1546 * pass and replaced by an ir3-specifc version that adds the
1547 * dword-offset in the last source.
1548 */
1549 case nir_intrinsic_load_ssbo_ir3:
1550 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1551 break;
1552 case nir_intrinsic_store_ssbo_ir3:
1553 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1554 !ctx->s->info.fs.early_fragment_tests)
1555 ctx->so->no_earlyz = true;
1556 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1557 break;
1558 case nir_intrinsic_get_buffer_size:
1559 emit_intrinsic_ssbo_size(ctx, intr, dst);
1560 break;
1561 case nir_intrinsic_ssbo_atomic_add_ir3:
1562 case nir_intrinsic_ssbo_atomic_imin_ir3:
1563 case nir_intrinsic_ssbo_atomic_umin_ir3:
1564 case nir_intrinsic_ssbo_atomic_imax_ir3:
1565 case nir_intrinsic_ssbo_atomic_umax_ir3:
1566 case nir_intrinsic_ssbo_atomic_and_ir3:
1567 case nir_intrinsic_ssbo_atomic_or_ir3:
1568 case nir_intrinsic_ssbo_atomic_xor_ir3:
1569 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1570 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1571 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1572 !ctx->s->info.fs.early_fragment_tests)
1573 ctx->so->no_earlyz = true;
1574 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1575 break;
1576 case nir_intrinsic_load_shared:
1577 emit_intrinsic_load_shared(ctx, intr, dst);
1578 break;
1579 case nir_intrinsic_store_shared:
1580 emit_intrinsic_store_shared(ctx, intr);
1581 break;
1582 case nir_intrinsic_shared_atomic_add:
1583 case nir_intrinsic_shared_atomic_imin:
1584 case nir_intrinsic_shared_atomic_umin:
1585 case nir_intrinsic_shared_atomic_imax:
1586 case nir_intrinsic_shared_atomic_umax:
1587 case nir_intrinsic_shared_atomic_and:
1588 case nir_intrinsic_shared_atomic_or:
1589 case nir_intrinsic_shared_atomic_xor:
1590 case nir_intrinsic_shared_atomic_exchange:
1591 case nir_intrinsic_shared_atomic_comp_swap:
1592 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1593 break;
1594 case nir_intrinsic_image_deref_load:
1595 emit_intrinsic_load_image(ctx, intr, dst);
1596 break;
1597 case nir_intrinsic_image_deref_store:
1598 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1599 !ctx->s->info.fs.early_fragment_tests)
1600 ctx->so->no_earlyz = true;
1601 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1602 break;
1603 case nir_intrinsic_image_deref_size:
1604 emit_intrinsic_image_size(ctx, intr, dst);
1605 break;
1606 case nir_intrinsic_image_deref_atomic_add:
1607 case nir_intrinsic_image_deref_atomic_imin:
1608 case nir_intrinsic_image_deref_atomic_umin:
1609 case nir_intrinsic_image_deref_atomic_imax:
1610 case nir_intrinsic_image_deref_atomic_umax:
1611 case nir_intrinsic_image_deref_atomic_and:
1612 case nir_intrinsic_image_deref_atomic_or:
1613 case nir_intrinsic_image_deref_atomic_xor:
1614 case nir_intrinsic_image_deref_atomic_exchange:
1615 case nir_intrinsic_image_deref_atomic_comp_swap:
1616 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1617 !ctx->s->info.fs.early_fragment_tests)
1618 ctx->so->no_earlyz = true;
1619 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1620 break;
1621 case nir_intrinsic_barrier:
1622 case nir_intrinsic_memory_barrier:
1623 case nir_intrinsic_group_memory_barrier:
1624 case nir_intrinsic_memory_barrier_atomic_counter:
1625 case nir_intrinsic_memory_barrier_buffer:
1626 case nir_intrinsic_memory_barrier_image:
1627 case nir_intrinsic_memory_barrier_shared:
1628 emit_intrinsic_barrier(ctx, intr);
1629 /* note that blk ptr no longer valid, make that obvious: */
1630 b = NULL;
1631 break;
1632 case nir_intrinsic_store_output:
1633 idx = nir_intrinsic_base(intr);
1634 comp = nir_intrinsic_component(intr);
1635 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1636 idx += nir_src_as_uint(intr->src[1]);
1637
1638 src = ir3_get_src(ctx, &intr->src[0]);
1639 for (int i = 0; i < intr->num_components; i++) {
1640 unsigned n = idx * 4 + i + comp;
1641 ctx->ir->outputs[n] = src[i];
1642 }
1643 break;
1644 case nir_intrinsic_load_base_vertex:
1645 case nir_intrinsic_load_first_vertex:
1646 if (!ctx->basevertex) {
1647 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1648 add_sysval_input(ctx, SYSTEM_VALUE_FIRST_VERTEX, ctx->basevertex);
1649 }
1650 dst[0] = ctx->basevertex;
1651 break;
1652 case nir_intrinsic_load_vertex_id_zero_base:
1653 case nir_intrinsic_load_vertex_id:
1654 if (!ctx->vertex_id) {
1655 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1656 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1657 ctx->vertex_id = create_input(ctx, 0);
1658 add_sysval_input(ctx, sv, ctx->vertex_id);
1659 }
1660 dst[0] = ctx->vertex_id;
1661 break;
1662 case nir_intrinsic_load_instance_id:
1663 if (!ctx->instance_id) {
1664 ctx->instance_id = create_input(ctx, 0);
1665 add_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID,
1666 ctx->instance_id);
1667 }
1668 dst[0] = ctx->instance_id;
1669 break;
1670 case nir_intrinsic_load_sample_id:
1671 ctx->so->per_samp = true;
1672 /* fall-thru */
1673 case nir_intrinsic_load_sample_id_no_per_sample:
1674 if (!ctx->samp_id) {
1675 ctx->samp_id = create_input(ctx, 0);
1676 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1677 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID,
1678 ctx->samp_id);
1679 }
1680 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1681 break;
1682 case nir_intrinsic_load_sample_mask_in:
1683 if (!ctx->samp_mask_in) {
1684 ctx->samp_mask_in = create_input(ctx, 0);
1685 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN,
1686 ctx->samp_mask_in);
1687 }
1688 dst[0] = ctx->samp_mask_in;
1689 break;
1690 case nir_intrinsic_load_user_clip_plane:
1691 idx = nir_intrinsic_ucp_id(intr);
1692 for (int i = 0; i < intr->num_components; i++) {
1693 unsigned n = idx * 4 + i;
1694 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1695 }
1696 break;
1697 case nir_intrinsic_load_front_face:
1698 if (!ctx->frag_face) {
1699 ctx->so->frag_face = true;
1700 ctx->frag_face = create_input(ctx, 0);
1701 add_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, ctx->frag_face);
1702 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1703 }
1704 /* for fragface, we get -1 for back and 0 for front. However this is
1705 * the inverse of what nir expects (where ~0 is true).
1706 */
1707 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1708 dst[0] = ir3_NOT_B(b, dst[0], 0);
1709 break;
1710 case nir_intrinsic_load_local_invocation_id:
1711 if (!ctx->local_invocation_id) {
1712 ctx->local_invocation_id = create_input_compmask(ctx, 0, 0x7);
1713 add_sysval_input_compmask(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID,
1714 0x7, ctx->local_invocation_id);
1715 }
1716 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1717 break;
1718 case nir_intrinsic_load_work_group_id:
1719 if (!ctx->work_group_id) {
1720 ctx->work_group_id = create_input_compmask(ctx, 0, 0x7);
1721 add_sysval_input_compmask(ctx, SYSTEM_VALUE_WORK_GROUP_ID,
1722 0x7, ctx->work_group_id);
1723 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1724 }
1725 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1726 break;
1727 case nir_intrinsic_load_num_work_groups:
1728 for (int i = 0; i < intr->num_components; i++) {
1729 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1730 }
1731 break;
1732 case nir_intrinsic_load_local_group_size:
1733 for (int i = 0; i < intr->num_components; i++) {
1734 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1735 }
1736 break;
1737 case nir_intrinsic_discard_if:
1738 case nir_intrinsic_discard: {
1739 struct ir3_instruction *cond, *kill;
1740
1741 if (intr->intrinsic == nir_intrinsic_discard_if) {
1742 /* conditional discard: */
1743 src = ir3_get_src(ctx, &intr->src[0]);
1744 cond = ir3_b2n(b, src[0]);
1745 } else {
1746 /* unconditional discard: */
1747 cond = create_immed(b, 1);
1748 }
1749
1750 /* NOTE: only cmps.*.* can write p0.x: */
1751 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1752 cond->cat2.condition = IR3_COND_NE;
1753
1754 /* condition always goes in predicate register: */
1755 cond->regs[0]->num = regid(REG_P0, 0);
1756
1757 kill = ir3_KILL(b, cond, 0);
1758 array_insert(ctx->ir, ctx->ir->predicates, kill);
1759
1760 array_insert(b, b->keeps, kill);
1761 ctx->so->no_earlyz = true;
1762
1763 break;
1764 }
1765 case nir_intrinsic_load_shared_ir3:
1766 emit_intrinsic_load_shared_ir3(ctx, intr, dst);
1767 break;
1768 case nir_intrinsic_store_shared_ir3:
1769 emit_intrinsic_store_shared_ir3(ctx, intr);
1770 break;
1771 default:
1772 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1773 nir_intrinsic_infos[intr->intrinsic].name);
1774 break;
1775 }
1776
1777 if (info->has_dest)
1778 ir3_put_dst(ctx, &intr->dest);
1779 }
1780
1781 static void
1782 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1783 {
1784 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1785 instr->def.num_components);
1786
1787 if (instr->def.bit_size < 32) {
1788 for (int i = 0; i < instr->def.num_components; i++)
1789 dst[i] = create_immed_typed(ctx->block,
1790 instr->value[i].u16,
1791 TYPE_U16);
1792 } else {
1793 for (int i = 0; i < instr->def.num_components; i++)
1794 dst[i] = create_immed_typed(ctx->block,
1795 instr->value[i].u32,
1796 TYPE_U32);
1797 }
1798
1799 }
1800
1801 static void
1802 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1803 {
1804 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1805 undef->def.num_components);
1806 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1807
1808 /* backend doesn't want undefined instructions, so just plug
1809 * in 0.0..
1810 */
1811 for (int i = 0; i < undef->def.num_components; i++)
1812 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1813 }
1814
1815 /*
1816 * texture fetch/sample instructions:
1817 */
1818
1819 static void
1820 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1821 {
1822 unsigned coords, flags = 0;
1823
1824 /* note: would use tex->coord_components.. except txs.. also,
1825 * since array index goes after shadow ref, we don't want to
1826 * count it:
1827 */
1828 switch (tex->sampler_dim) {
1829 case GLSL_SAMPLER_DIM_1D:
1830 case GLSL_SAMPLER_DIM_BUF:
1831 coords = 1;
1832 break;
1833 case GLSL_SAMPLER_DIM_2D:
1834 case GLSL_SAMPLER_DIM_RECT:
1835 case GLSL_SAMPLER_DIM_EXTERNAL:
1836 case GLSL_SAMPLER_DIM_MS:
1837 coords = 2;
1838 break;
1839 case GLSL_SAMPLER_DIM_3D:
1840 case GLSL_SAMPLER_DIM_CUBE:
1841 coords = 3;
1842 flags |= IR3_INSTR_3D;
1843 break;
1844 default:
1845 unreachable("bad sampler_dim");
1846 }
1847
1848 if (tex->is_shadow && tex->op != nir_texop_lod)
1849 flags |= IR3_INSTR_S;
1850
1851 if (tex->is_array && tex->op != nir_texop_lod)
1852 flags |= IR3_INSTR_A;
1853
1854 *flagsp = flags;
1855 *coordsp = coords;
1856 }
1857
1858 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
1859 * or immediate (in which case it will get lowered later to a non .s2en
1860 * version of the tex instruction which encode tex/samp as immediates:
1861 */
1862 static struct ir3_instruction *
1863 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
1864 {
1865 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
1866 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
1867 struct ir3_instruction *texture, *sampler;
1868
1869 if (texture_idx >= 0) {
1870 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
1871 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
1872 } else {
1873 /* TODO what to do for dynamic case? I guess we only need the
1874 * max index for astc srgb workaround so maybe not a problem
1875 * to worry about if we don't enable indirect samplers for
1876 * a4xx?
1877 */
1878 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
1879 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
1880 }
1881
1882 if (sampler_idx >= 0) {
1883 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
1884 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
1885 } else {
1886 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
1887 }
1888
1889 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1890 sampler,
1891 texture,
1892 }, 2);
1893 }
1894
1895 static void
1896 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
1897 {
1898 struct ir3_block *b = ctx->block;
1899 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1900 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
1901 struct ir3_instruction *lod, *compare, *proj, *sample_index;
1902 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1903 unsigned i, coords, flags, ncomp;
1904 unsigned nsrc0 = 0, nsrc1 = 0;
1905 type_t type;
1906 opc_t opc = 0;
1907
1908 ncomp = nir_dest_num_components(tex->dest);
1909
1910 coord = off = ddx = ddy = NULL;
1911 lod = proj = compare = sample_index = NULL;
1912
1913 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
1914
1915 for (unsigned i = 0; i < tex->num_srcs; i++) {
1916 switch (tex->src[i].src_type) {
1917 case nir_tex_src_coord:
1918 coord = ir3_get_src(ctx, &tex->src[i].src);
1919 break;
1920 case nir_tex_src_bias:
1921 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1922 has_bias = true;
1923 break;
1924 case nir_tex_src_lod:
1925 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1926 has_lod = true;
1927 break;
1928 case nir_tex_src_comparator: /* shadow comparator */
1929 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
1930 break;
1931 case nir_tex_src_projector:
1932 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
1933 has_proj = true;
1934 break;
1935 case nir_tex_src_offset:
1936 off = ir3_get_src(ctx, &tex->src[i].src);
1937 has_off = true;
1938 break;
1939 case nir_tex_src_ddx:
1940 ddx = ir3_get_src(ctx, &tex->src[i].src);
1941 break;
1942 case nir_tex_src_ddy:
1943 ddy = ir3_get_src(ctx, &tex->src[i].src);
1944 break;
1945 case nir_tex_src_ms_index:
1946 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
1947 break;
1948 case nir_tex_src_texture_offset:
1949 case nir_tex_src_sampler_offset:
1950 /* handled in get_tex_samp_src() */
1951 break;
1952 default:
1953 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
1954 tex->src[i].src_type);
1955 return;
1956 }
1957 }
1958
1959 switch (tex->op) {
1960 case nir_texop_tex_prefetch:
1961 compile_assert(ctx, !has_bias);
1962 compile_assert(ctx, !has_lod);
1963 compile_assert(ctx, !compare);
1964 compile_assert(ctx, !has_proj);
1965 compile_assert(ctx, !has_off);
1966 compile_assert(ctx, !ddx);
1967 compile_assert(ctx, !ddy);
1968 compile_assert(ctx, !sample_index);
1969 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_texture_offset) < 0);
1970 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset) < 0);
1971
1972 if (ctx->so->num_sampler_prefetch < IR3_MAX_SAMPLER_PREFETCH) {
1973 opc = OPC_META_TEX_PREFETCH;
1974 ctx->so->num_sampler_prefetch++;
1975 break;
1976 }
1977 /* fallthru */
1978 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
1979 case nir_texop_txb: opc = OPC_SAMB; break;
1980 case nir_texop_txl: opc = OPC_SAML; break;
1981 case nir_texop_txd: opc = OPC_SAMGQ; break;
1982 case nir_texop_txf: opc = OPC_ISAML; break;
1983 case nir_texop_lod: opc = OPC_GETLOD; break;
1984 case nir_texop_tg4:
1985 /* NOTE: a4xx might need to emulate gather w/ txf (this is
1986 * what blob does, seems gather is broken?), and a3xx did
1987 * not support it (but probably could also emulate).
1988 */
1989 switch (tex->component) {
1990 case 0: opc = OPC_GATHER4R; break;
1991 case 1: opc = OPC_GATHER4G; break;
1992 case 2: opc = OPC_GATHER4B; break;
1993 case 3: opc = OPC_GATHER4A; break;
1994 }
1995 break;
1996 case nir_texop_txf_ms_fb:
1997 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
1998 default:
1999 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
2000 return;
2001 }
2002
2003 tex_info(tex, &flags, &coords);
2004
2005 /*
2006 * lay out the first argument in the proper order:
2007 * - actual coordinates first
2008 * - shadow reference
2009 * - array index
2010 * - projection w
2011 * - starting at offset 4, dpdx.xy, dpdy.xy
2012 *
2013 * bias/lod go into the second arg
2014 */
2015
2016 /* insert tex coords: */
2017 for (i = 0; i < coords; i++)
2018 src0[i] = coord[i];
2019
2020 nsrc0 = i;
2021
2022 /* scale up integer coords for TXF based on the LOD */
2023 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
2024 assert(has_lod);
2025 for (i = 0; i < coords; i++)
2026 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
2027 }
2028
2029 if (coords == 1) {
2030 /* hw doesn't do 1d, so we treat it as 2d with
2031 * height of 1, and patch up the y coord.
2032 */
2033 if (is_isam(opc)) {
2034 src0[nsrc0++] = create_immed(b, 0);
2035 } else {
2036 src0[nsrc0++] = create_immed(b, fui(0.5));
2037 }
2038 }
2039
2040 if (tex->is_shadow && tex->op != nir_texop_lod)
2041 src0[nsrc0++] = compare;
2042
2043 if (tex->is_array && tex->op != nir_texop_lod) {
2044 struct ir3_instruction *idx = coord[coords];
2045
2046 /* the array coord for cube arrays needs 0.5 added to it */
2047 if (ctx->compiler->array_index_add_half && !is_isam(opc))
2048 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
2049
2050 src0[nsrc0++] = idx;
2051 }
2052
2053 if (has_proj) {
2054 src0[nsrc0++] = proj;
2055 flags |= IR3_INSTR_P;
2056 }
2057
2058 /* pad to 4, then ddx/ddy: */
2059 if (tex->op == nir_texop_txd) {
2060 while (nsrc0 < 4)
2061 src0[nsrc0++] = create_immed(b, fui(0.0));
2062 for (i = 0; i < coords; i++)
2063 src0[nsrc0++] = ddx[i];
2064 if (coords < 2)
2065 src0[nsrc0++] = create_immed(b, fui(0.0));
2066 for (i = 0; i < coords; i++)
2067 src0[nsrc0++] = ddy[i];
2068 if (coords < 2)
2069 src0[nsrc0++] = create_immed(b, fui(0.0));
2070 }
2071
2072 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2073 * with scaled x coord according to requested sample:
2074 */
2075 if (opc == OPC_ISAMM) {
2076 if (ctx->compiler->txf_ms_with_isaml) {
2077 /* the samples are laid out in x dimension as
2078 * 0 1 2 3
2079 * x_ms = (x << ms) + sample_index;
2080 */
2081 struct ir3_instruction *ms;
2082 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
2083
2084 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
2085 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
2086
2087 opc = OPC_ISAML;
2088 } else {
2089 src0[nsrc0++] = sample_index;
2090 }
2091 }
2092
2093 /*
2094 * second argument (if applicable):
2095 * - offsets
2096 * - lod
2097 * - bias
2098 */
2099 if (has_off | has_lod | has_bias) {
2100 if (has_off) {
2101 unsigned off_coords = coords;
2102 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2103 off_coords--;
2104 for (i = 0; i < off_coords; i++)
2105 src1[nsrc1++] = off[i];
2106 if (off_coords < 2)
2107 src1[nsrc1++] = create_immed(b, fui(0.0));
2108 flags |= IR3_INSTR_O;
2109 }
2110
2111 if (has_lod | has_bias)
2112 src1[nsrc1++] = lod;
2113 }
2114
2115 switch (tex->dest_type) {
2116 case nir_type_invalid:
2117 case nir_type_float:
2118 type = TYPE_F32;
2119 break;
2120 case nir_type_int:
2121 type = TYPE_S32;
2122 break;
2123 case nir_type_uint:
2124 case nir_type_bool:
2125 type = TYPE_U32;
2126 break;
2127 default:
2128 unreachable("bad dest_type");
2129 }
2130
2131 if (opc == OPC_GETLOD)
2132 type = TYPE_S32;
2133
2134 struct ir3_instruction *samp_tex;
2135
2136 if (tex->op == nir_texop_txf_ms_fb) {
2137 /* only expect a single txf_ms_fb per shader: */
2138 compile_assert(ctx, !ctx->so->fb_read);
2139 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
2140
2141 ctx->so->fb_read = true;
2142 samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2143 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2144 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2145 }, 2);
2146
2147 ctx->so->num_samp++;
2148 } else {
2149 samp_tex = get_tex_samp_tex_src(ctx, tex);
2150 }
2151
2152 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
2153 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
2154
2155 if (opc == OPC_META_TEX_PREFETCH) {
2156 int idx = nir_tex_instr_src_index(tex, nir_tex_src_coord);
2157
2158 compile_assert(ctx, tex->src[idx].src.is_ssa);
2159
2160 sam = ir3_META_TEX_PREFETCH(b);
2161 ir3_reg_create(sam, 0, 0)->wrmask = MASK(ncomp); /* dst */
2162 sam->prefetch.input_offset =
2163 ir3_nir_coord_offset(tex->src[idx].src.ssa);
2164 sam->prefetch.tex = tex->texture_index;
2165 sam->prefetch.samp = tex->sampler_index;
2166 } else {
2167 sam = ir3_SAM(b, opc, type, MASK(ncomp), flags,
2168 samp_tex, col0, col1);
2169 }
2170
2171 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
2172 assert(opc != OPC_META_TEX_PREFETCH);
2173
2174 /* only need first 3 components: */
2175 sam->regs[0]->wrmask = 0x7;
2176 ir3_split_dest(b, dst, sam, 0, 3);
2177
2178 /* we need to sample the alpha separately with a non-ASTC
2179 * texture state:
2180 */
2181 sam = ir3_SAM(b, opc, type, 0b1000, flags,
2182 samp_tex, col0, col1);
2183
2184 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
2185
2186 /* fixup .w component: */
2187 ir3_split_dest(b, &dst[3], sam, 3, 1);
2188 } else {
2189 /* normal (non-workaround) case: */
2190 ir3_split_dest(b, dst, sam, 0, ncomp);
2191 }
2192
2193 /* GETLOD returns results in 4.8 fixed point */
2194 if (opc == OPC_GETLOD) {
2195 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
2196
2197 compile_assert(ctx, tex->dest_type == nir_type_float);
2198 for (i = 0; i < 2; i++) {
2199 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_S32, TYPE_F32), 0,
2200 factor, 0);
2201 }
2202 }
2203
2204 ir3_put_dst(ctx, &tex->dest);
2205 }
2206
2207 static void
2208 emit_tex_info(struct ir3_context *ctx, nir_tex_instr *tex, unsigned idx)
2209 {
2210 struct ir3_block *b = ctx->block;
2211 struct ir3_instruction **dst, *sam;
2212
2213 dst = ir3_get_dst(ctx, &tex->dest, 1);
2214
2215 sam = ir3_SAM(b, OPC_GETINFO, TYPE_U32, 1 << idx, 0,
2216 get_tex_samp_tex_src(ctx, tex), NULL, NULL);
2217
2218 /* even though there is only one component, since it ends
2219 * up in .y/.z/.w rather than .x, we need a split_dest()
2220 */
2221 if (idx)
2222 ir3_split_dest(b, dst, sam, 0, idx + 1);
2223
2224 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2225 * the value in TEX_CONST_0 is zero-based.
2226 */
2227 if (ctx->compiler->levels_add_one)
2228 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2229
2230 ir3_put_dst(ctx, &tex->dest);
2231 }
2232
2233 static void
2234 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2235 {
2236 struct ir3_block *b = ctx->block;
2237 struct ir3_instruction **dst, *sam;
2238 struct ir3_instruction *lod;
2239 unsigned flags, coords;
2240
2241 tex_info(tex, &flags, &coords);
2242
2243 /* Actually we want the number of dimensions, not coordinates. This
2244 * distinction only matters for cubes.
2245 */
2246 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2247 coords = 2;
2248
2249 dst = ir3_get_dst(ctx, &tex->dest, 4);
2250
2251 compile_assert(ctx, tex->num_srcs == 1);
2252 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
2253
2254 lod = ir3_get_src(ctx, &tex->src[0].src)[0];
2255
2256 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
2257 get_tex_samp_tex_src(ctx, tex), lod, NULL);
2258
2259 ir3_split_dest(b, dst, sam, 0, 4);
2260
2261 /* Array size actually ends up in .w rather than .z. This doesn't
2262 * matter for miplevel 0, but for higher mips the value in z is
2263 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2264 * returned, which means that we have to add 1 to it for arrays.
2265 */
2266 if (tex->is_array) {
2267 if (ctx->compiler->levels_add_one) {
2268 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2269 } else {
2270 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2271 }
2272 }
2273
2274 ir3_put_dst(ctx, &tex->dest);
2275 }
2276
2277 static void
2278 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2279 {
2280 switch (jump->type) {
2281 case nir_jump_break:
2282 case nir_jump_continue:
2283 case nir_jump_return:
2284 /* I *think* we can simply just ignore this, and use the
2285 * successor block link to figure out where we need to
2286 * jump to for break/continue
2287 */
2288 break;
2289 default:
2290 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2291 break;
2292 }
2293 }
2294
2295 static void
2296 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2297 {
2298 switch (instr->type) {
2299 case nir_instr_type_alu:
2300 emit_alu(ctx, nir_instr_as_alu(instr));
2301 break;
2302 case nir_instr_type_deref:
2303 /* ignored, handled as part of the intrinsic they are src to */
2304 break;
2305 case nir_instr_type_intrinsic:
2306 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2307 break;
2308 case nir_instr_type_load_const:
2309 emit_load_const(ctx, nir_instr_as_load_const(instr));
2310 break;
2311 case nir_instr_type_ssa_undef:
2312 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2313 break;
2314 case nir_instr_type_tex: {
2315 nir_tex_instr *tex = nir_instr_as_tex(instr);
2316 /* couple tex instructions get special-cased:
2317 */
2318 switch (tex->op) {
2319 case nir_texop_txs:
2320 emit_tex_txs(ctx, tex);
2321 break;
2322 case nir_texop_query_levels:
2323 emit_tex_info(ctx, tex, 2);
2324 break;
2325 case nir_texop_texture_samples:
2326 emit_tex_info(ctx, tex, 3);
2327 break;
2328 default:
2329 emit_tex(ctx, tex);
2330 break;
2331 }
2332 break;
2333 }
2334 case nir_instr_type_jump:
2335 emit_jump(ctx, nir_instr_as_jump(instr));
2336 break;
2337 case nir_instr_type_phi:
2338 /* we have converted phi webs to regs in NIR by now */
2339 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2340 break;
2341 case nir_instr_type_call:
2342 case nir_instr_type_parallel_copy:
2343 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2344 break;
2345 }
2346 }
2347
2348 static struct ir3_block *
2349 get_block(struct ir3_context *ctx, const nir_block *nblock)
2350 {
2351 struct ir3_block *block;
2352 struct hash_entry *hentry;
2353
2354 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2355 if (hentry)
2356 return hentry->data;
2357
2358 block = ir3_block_create(ctx->ir);
2359 block->nblock = nblock;
2360 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2361
2362 block->predecessors = _mesa_pointer_set_create(block);
2363 set_foreach(nblock->predecessors, sentry) {
2364 _mesa_set_add(block->predecessors, get_block(ctx, sentry->key));
2365 }
2366
2367 return block;
2368 }
2369
2370 static void
2371 emit_block(struct ir3_context *ctx, nir_block *nblock)
2372 {
2373 struct ir3_block *block = get_block(ctx, nblock);
2374
2375 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2376 if (nblock->successors[i]) {
2377 block->successors[i] =
2378 get_block(ctx, nblock->successors[i]);
2379 }
2380 }
2381
2382 ctx->block = block;
2383 list_addtail(&block->node, &ctx->ir->block_list);
2384
2385 /* re-emit addr register in each block if needed: */
2386 for (int i = 0; i < ARRAY_SIZE(ctx->addr_ht); i++) {
2387 _mesa_hash_table_destroy(ctx->addr_ht[i], NULL);
2388 ctx->addr_ht[i] = NULL;
2389 }
2390
2391 nir_foreach_instr(instr, nblock) {
2392 ctx->cur_instr = instr;
2393 emit_instr(ctx, instr);
2394 ctx->cur_instr = NULL;
2395 if (ctx->error)
2396 return;
2397 }
2398 }
2399
2400 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2401
2402 static void
2403 emit_if(struct ir3_context *ctx, nir_if *nif)
2404 {
2405 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2406
2407 ctx->block->condition =
2408 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
2409
2410 emit_cf_list(ctx, &nif->then_list);
2411 emit_cf_list(ctx, &nif->else_list);
2412 }
2413
2414 static void
2415 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2416 {
2417 emit_cf_list(ctx, &nloop->body);
2418 ctx->so->loops++;
2419 }
2420
2421 static void
2422 stack_push(struct ir3_context *ctx)
2423 {
2424 ctx->stack++;
2425 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2426 }
2427
2428 static void
2429 stack_pop(struct ir3_context *ctx)
2430 {
2431 compile_assert(ctx, ctx->stack > 0);
2432 ctx->stack--;
2433 }
2434
2435 static void
2436 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2437 {
2438 foreach_list_typed(nir_cf_node, node, node, list) {
2439 switch (node->type) {
2440 case nir_cf_node_block:
2441 emit_block(ctx, nir_cf_node_as_block(node));
2442 break;
2443 case nir_cf_node_if:
2444 stack_push(ctx);
2445 emit_if(ctx, nir_cf_node_as_if(node));
2446 stack_pop(ctx);
2447 break;
2448 case nir_cf_node_loop:
2449 stack_push(ctx);
2450 emit_loop(ctx, nir_cf_node_as_loop(node));
2451 stack_pop(ctx);
2452 break;
2453 case nir_cf_node_function:
2454 ir3_context_error(ctx, "TODO\n");
2455 break;
2456 }
2457 }
2458 }
2459
2460 /* emit stream-out code. At this point, the current block is the original
2461 * (nir) end block, and nir ensures that all flow control paths terminate
2462 * into the end block. We re-purpose the original end block to generate
2463 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2464 * block holding stream-out write instructions, followed by the new end
2465 * block:
2466 *
2467 * blockOrigEnd {
2468 * p0.x = (vtxcnt < maxvtxcnt)
2469 * // succs: blockStreamOut, blockNewEnd
2470 * }
2471 * blockStreamOut {
2472 * ... stream-out instructions ...
2473 * // succs: blockNewEnd
2474 * }
2475 * blockNewEnd {
2476 * }
2477 */
2478 static void
2479 emit_stream_out(struct ir3_context *ctx)
2480 {
2481 struct ir3 *ir = ctx->ir;
2482 struct ir3_stream_output_info *strmout =
2483 &ctx->so->shader->stream_output;
2484 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2485 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2486 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2487
2488 /* create vtxcnt input in input block at top of shader,
2489 * so that it is seen as live over the entire duration
2490 * of the shader:
2491 */
2492 vtxcnt = create_input(ctx, 0);
2493 add_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, vtxcnt);
2494
2495 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2496
2497 /* at this point, we are at the original 'end' block,
2498 * re-purpose this block to stream-out condition, then
2499 * append stream-out block and new-end block
2500 */
2501 orig_end_block = ctx->block;
2502
2503 // TODO these blocks need to update predecessors..
2504 // maybe w/ store_global intrinsic, we could do this
2505 // stuff in nir->nir pass
2506
2507 stream_out_block = ir3_block_create(ir);
2508 list_addtail(&stream_out_block->node, &ir->block_list);
2509
2510 new_end_block = ir3_block_create(ir);
2511 list_addtail(&new_end_block->node, &ir->block_list);
2512
2513 orig_end_block->successors[0] = stream_out_block;
2514 orig_end_block->successors[1] = new_end_block;
2515 stream_out_block->successors[0] = new_end_block;
2516
2517 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2518 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2519 cond->regs[0]->num = regid(REG_P0, 0);
2520 cond->cat2.condition = IR3_COND_LT;
2521
2522 /* condition goes on previous block to the conditional,
2523 * since it is used to pick which of the two successor
2524 * paths to take:
2525 */
2526 orig_end_block->condition = cond;
2527
2528 /* switch to stream_out_block to generate the stream-out
2529 * instructions:
2530 */
2531 ctx->block = stream_out_block;
2532
2533 /* Calculate base addresses based on vtxcnt. Instructions
2534 * generated for bases not used in following loop will be
2535 * stripped out in the backend.
2536 */
2537 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2538 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
2539 unsigned stride = strmout->stride[i];
2540 struct ir3_instruction *base, *off;
2541
2542 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
2543
2544 /* 24-bit should be enough: */
2545 off = ir3_MUL_U24(ctx->block, vtxcnt, 0,
2546 create_immed(ctx->block, stride * 4), 0);
2547
2548 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2549 }
2550
2551 /* Generate the per-output store instructions: */
2552 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2553 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2554 unsigned c = j + strmout->output[i].start_component;
2555 struct ir3_instruction *base, *out, *stg;
2556
2557 base = bases[strmout->output[i].output_buffer];
2558 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2559
2560 stg = ir3_STG(ctx->block, base, 0, out, 0,
2561 create_immed(ctx->block, 1), 0);
2562 stg->cat6.type = TYPE_U32;
2563 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2564
2565 array_insert(ctx->block, ctx->block->keeps, stg);
2566 }
2567 }
2568
2569 /* and finally switch to the new_end_block: */
2570 ctx->block = new_end_block;
2571 }
2572
2573 static void
2574 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2575 {
2576 nir_metadata_require(impl, nir_metadata_block_index);
2577
2578 compile_assert(ctx, ctx->stack == 0);
2579
2580 emit_cf_list(ctx, &impl->body);
2581 emit_block(ctx, impl->end_block);
2582
2583 compile_assert(ctx, ctx->stack == 0);
2584
2585 /* at this point, we should have a single empty block,
2586 * into which we emit the 'end' instruction.
2587 */
2588 compile_assert(ctx, list_is_empty(&ctx->block->instr_list));
2589
2590 /* If stream-out (aka transform-feedback) enabled, emit the
2591 * stream-out instructions, followed by a new empty block (into
2592 * which the 'end' instruction lands).
2593 *
2594 * NOTE: it is done in this order, rather than inserting before
2595 * we emit end_block, because NIR guarantees that all blocks
2596 * flow into end_block, and that end_block has no successors.
2597 * So by re-purposing end_block as the first block of stream-
2598 * out, we guarantee that all exit paths flow into the stream-
2599 * out instructions.
2600 */
2601 if ((ctx->compiler->gpu_id < 500) &&
2602 (ctx->so->shader->stream_output.num_outputs > 0) &&
2603 !ctx->so->binning_pass) {
2604 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2605 emit_stream_out(ctx);
2606 }
2607
2608 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2609 * NOP and has an epilogue that writes the VS outputs to local storage, to
2610 * be read by the HS. Then it resets execution mask (chmask) and chains
2611 * to the next shader (chsh).
2612 */
2613 if ((ctx->so->type == MESA_SHADER_VERTEX &&
2614 (ctx->so->key.has_gs || ctx->so->key.tessellation)) ||
2615 (ctx->so->type == MESA_SHADER_TESS_EVAL && ctx->so->key.has_gs)) {
2616 struct ir3_instruction *chmask =
2617 ir3_CHMASK(ctx->block);
2618 chmask->barrier_class = IR3_BARRIER_EVERYTHING;
2619 chmask->barrier_conflict = IR3_BARRIER_EVERYTHING;
2620
2621 struct ir3_instruction *chsh =
2622 ir3_CHSH(ctx->block);
2623 chsh->barrier_class = IR3_BARRIER_EVERYTHING;
2624 chsh->barrier_conflict = IR3_BARRIER_EVERYTHING;
2625 } else {
2626 ir3_END(ctx->block);
2627 }
2628 }
2629
2630 static void
2631 setup_input(struct ir3_context *ctx, nir_variable *in)
2632 {
2633 struct ir3_shader_variant *so = ctx->so;
2634 unsigned ncomp = glsl_get_components(in->type);
2635 unsigned n = in->data.driver_location;
2636 unsigned frac = in->data.location_frac;
2637 unsigned slot = in->data.location;
2638
2639 /* Inputs are loaded using ldlw or ldg for these stages. */
2640 if (ctx->so->type == MESA_SHADER_TESS_CTRL ||
2641 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2642 ctx->so->type == MESA_SHADER_GEOMETRY)
2643 return;
2644
2645 /* skip unread inputs, we could end up with (for example), unsplit
2646 * matrix/etc inputs in the case they are not read, so just silently
2647 * skip these.
2648 */
2649 if (ncomp > 4)
2650 return;
2651
2652 so->inputs[n].slot = slot;
2653 so->inputs[n].compmask = (1 << (ncomp + frac)) - 1;
2654 so->inputs_count = MAX2(so->inputs_count, n + 1);
2655 so->inputs[n].interpolate = in->data.interpolation;
2656
2657 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2658
2659 /* if any varyings have 'sample' qualifer, that triggers us
2660 * to run in per-sample mode:
2661 */
2662 so->per_samp |= in->data.sample;
2663
2664 for (int i = 0; i < ncomp; i++) {
2665 struct ir3_instruction *instr = NULL;
2666 unsigned idx = (n * 4) + i + frac;
2667
2668 if (slot == VARYING_SLOT_POS) {
2669 ir3_context_error(ctx, "fragcoord should be a sysval!\n");
2670 } else if (slot == VARYING_SLOT_PNTC) {
2671 /* see for example st_nir_fixup_varying_slots().. this is
2672 * maybe a bit mesa/st specific. But we need things to line
2673 * up for this in fdN_program:
2674 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2675 * if (emit->sprite_coord_enable & texmask) {
2676 * ...
2677 * }
2678 */
2679 so->inputs[n].slot = VARYING_SLOT_VAR8;
2680 so->inputs[n].bary = true;
2681 instr = create_frag_input(ctx, false, idx);
2682 } else {
2683 /* detect the special case for front/back colors where
2684 * we need to do flat vs smooth shading depending on
2685 * rast state:
2686 */
2687 if (in->data.interpolation == INTERP_MODE_NONE) {
2688 switch (slot) {
2689 case VARYING_SLOT_COL0:
2690 case VARYING_SLOT_COL1:
2691 case VARYING_SLOT_BFC0:
2692 case VARYING_SLOT_BFC1:
2693 so->inputs[n].rasterflat = true;
2694 break;
2695 default:
2696 break;
2697 }
2698 }
2699
2700 if (ctx->compiler->flat_bypass) {
2701 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2702 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2703 so->inputs[n].use_ldlv = true;
2704 }
2705
2706 so->inputs[n].bary = true;
2707
2708 instr = create_frag_input(ctx, so->inputs[n].use_ldlv, idx);
2709 }
2710
2711 compile_assert(ctx, idx < ctx->ir->ninputs);
2712
2713 ctx->ir->inputs[idx] = instr;
2714 }
2715 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2716 for (int i = 0; i < ncomp; i++) {
2717 unsigned idx = (n * 4) + i + frac;
2718 compile_assert(ctx, idx < ctx->ir->ninputs);
2719 ctx->ir->inputs[idx] = create_input(ctx, idx);
2720 }
2721 } else {
2722 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2723 }
2724
2725 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
2726 so->total_in += ncomp;
2727 }
2728 }
2729
2730 /* Initially we assign non-packed inloc's for varyings, as we don't really
2731 * know up-front which components will be unused. After all the compilation
2732 * stages we scan the shader to see which components are actually used, and
2733 * re-pack the inlocs to eliminate unneeded varyings.
2734 */
2735 static void
2736 pack_inlocs(struct ir3_context *ctx)
2737 {
2738 struct ir3_shader_variant *so = ctx->so;
2739 uint8_t used_components[so->inputs_count];
2740
2741 memset(used_components, 0, sizeof(used_components));
2742
2743 /*
2744 * First Step: scan shader to find which bary.f/ldlv remain:
2745 */
2746
2747 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) {
2748 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
2749 if (is_input(instr)) {
2750 unsigned inloc = instr->regs[1]->iim_val;
2751 unsigned i = inloc / 4;
2752 unsigned j = inloc % 4;
2753
2754 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
2755 compile_assert(ctx, i < so->inputs_count);
2756
2757 used_components[i] |= 1 << j;
2758 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
2759 for (int n = 0; n < 2; n++) {
2760 unsigned inloc = instr->prefetch.input_offset + n;
2761 unsigned i = inloc / 4;
2762 unsigned j = inloc % 4;
2763
2764 compile_assert(ctx, i < so->inputs_count);
2765
2766 used_components[i] |= 1 << j;
2767 }
2768 }
2769 }
2770 }
2771
2772 /*
2773 * Second Step: reassign varying inloc/slots:
2774 */
2775
2776 unsigned actual_in = 0;
2777 unsigned inloc = 0;
2778
2779 for (unsigned i = 0; i < so->inputs_count; i++) {
2780 unsigned compmask = 0, maxcomp = 0;
2781
2782 so->inputs[i].inloc = inloc;
2783 so->inputs[i].bary = false;
2784
2785 for (unsigned j = 0; j < 4; j++) {
2786 if (!(used_components[i] & (1 << j)))
2787 continue;
2788
2789 compmask |= (1 << j);
2790 actual_in++;
2791 maxcomp = j + 1;
2792
2793 /* at this point, since used_components[i] mask is only
2794 * considering varyings (ie. not sysvals) we know this
2795 * is a varying:
2796 */
2797 so->inputs[i].bary = true;
2798 }
2799
2800 if (so->inputs[i].bary) {
2801 so->varying_in++;
2802 so->inputs[i].compmask = (1 << maxcomp) - 1;
2803 inloc += maxcomp;
2804 }
2805 }
2806
2807 /*
2808 * Third Step: reassign packed inloc's:
2809 */
2810
2811 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) {
2812 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
2813 if (is_input(instr)) {
2814 unsigned inloc = instr->regs[1]->iim_val;
2815 unsigned i = inloc / 4;
2816 unsigned j = inloc % 4;
2817
2818 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
2819 }
2820 }
2821 }
2822 }
2823
2824 static void
2825 setup_output(struct ir3_context *ctx, nir_variable *out)
2826 {
2827 struct ir3_shader_variant *so = ctx->so;
2828 unsigned ncomp = glsl_get_components(out->type);
2829 unsigned n = out->data.driver_location;
2830 unsigned frac = out->data.location_frac;
2831 unsigned slot = out->data.location;
2832 unsigned comp = 0;
2833
2834 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2835 switch (slot) {
2836 case FRAG_RESULT_DEPTH:
2837 comp = 2; /* tgsi will write to .z component */
2838 so->writes_pos = true;
2839 break;
2840 case FRAG_RESULT_COLOR:
2841 so->color0_mrt = 1;
2842 break;
2843 case FRAG_RESULT_SAMPLE_MASK:
2844 so->writes_smask = true;
2845 break;
2846 default:
2847 if (slot >= FRAG_RESULT_DATA0)
2848 break;
2849 ir3_context_error(ctx, "unknown FS output name: %s\n",
2850 gl_frag_result_name(slot));
2851 }
2852 } else if (ctx->so->type == MESA_SHADER_VERTEX ||
2853 ctx->so->type == MESA_SHADER_GEOMETRY) {
2854 switch (slot) {
2855 case VARYING_SLOT_POS:
2856 so->writes_pos = true;
2857 break;
2858 case VARYING_SLOT_PSIZ:
2859 so->writes_psize = true;
2860 break;
2861 case VARYING_SLOT_PRIMITIVE_ID:
2862 case VARYING_SLOT_LAYER:
2863 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
2864 debug_assert(ctx->so->type == MESA_SHADER_GEOMETRY);
2865 /* fall through */
2866 case VARYING_SLOT_COL0:
2867 case VARYING_SLOT_COL1:
2868 case VARYING_SLOT_BFC0:
2869 case VARYING_SLOT_BFC1:
2870 case VARYING_SLOT_FOGC:
2871 case VARYING_SLOT_CLIP_DIST0:
2872 case VARYING_SLOT_CLIP_DIST1:
2873 case VARYING_SLOT_CLIP_VERTEX:
2874 break;
2875 default:
2876 if (slot >= VARYING_SLOT_VAR0)
2877 break;
2878 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
2879 break;
2880 ir3_context_error(ctx, "unknown %s shader output name: %s\n",
2881 _mesa_shader_stage_to_string(ctx->so->type),
2882 gl_varying_slot_name(slot));
2883 }
2884 } else {
2885 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2886 }
2887
2888 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
2889
2890 so->outputs[n].slot = slot;
2891 so->outputs[n].regid = regid(n, comp);
2892 so->outputs_count = MAX2(so->outputs_count, n + 1);
2893
2894 for (int i = 0; i < ncomp; i++) {
2895 unsigned idx = (n * 4) + i + frac;
2896 compile_assert(ctx, idx < ctx->ir->noutputs);
2897 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2898 }
2899
2900 /* if varying packing doesn't happen, we could end up in a situation
2901 * with "holes" in the output, and since the per-generation code that
2902 * sets up varying linkage registers doesn't expect to have more than
2903 * one varying per vec4 slot, pad the holes.
2904 *
2905 * Note that this should probably generate a performance warning of
2906 * some sort.
2907 */
2908 for (int i = 0; i < frac; i++) {
2909 unsigned idx = (n * 4) + i;
2910 if (!ctx->ir->outputs[idx]) {
2911 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2912 }
2913 }
2914 }
2915
2916 static int
2917 max_drvloc(struct exec_list *vars)
2918 {
2919 int drvloc = -1;
2920 nir_foreach_variable(var, vars) {
2921 drvloc = MAX2(drvloc, (int)var->data.driver_location);
2922 }
2923 return drvloc;
2924 }
2925
2926 static const unsigned max_sysvals[] = {
2927 [MESA_SHADER_VERTEX] = 16,
2928 [MESA_SHADER_GEOMETRY] = 16,
2929 [MESA_SHADER_FRAGMENT] = 24, // TODO
2930 [MESA_SHADER_COMPUTE] = 16, // TODO how many do we actually need?
2931 [MESA_SHADER_KERNEL] = 16, // TODO how many do we actually need?
2932 };
2933
2934 static void
2935 emit_instructions(struct ir3_context *ctx)
2936 {
2937 unsigned ninputs, noutputs;
2938 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
2939
2940 ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4;
2941 noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4;
2942
2943 /* we need to leave room for sysvals:
2944 */
2945 ninputs += max_sysvals[ctx->so->type];
2946 if (ctx->so->type == MESA_SHADER_VERTEX)
2947 noutputs += 8; /* gs or tess header + primitive_id */
2948
2949 ctx->ir = ir3_create(ctx->compiler, ctx->so->type, ninputs, noutputs);
2950
2951 /* Create inputs in first block: */
2952 ctx->block = get_block(ctx, nir_start_block(fxn));
2953 ctx->in_block = ctx->block;
2954 list_addtail(&ctx->block->node, &ctx->ir->block_list);
2955
2956 ninputs -= max_sysvals[ctx->so->type];
2957
2958 if (ctx->so->key.has_gs) {
2959 if (ctx->so->type == MESA_SHADER_VERTEX ||
2960 ctx->so->type == MESA_SHADER_GEOMETRY) {
2961 ctx->gs_header = create_input(ctx, 0);
2962 ctx->primitive_id = create_input(ctx, 0);
2963 }
2964 }
2965
2966 /* for fragment shader, the vcoord input register is used as the
2967 * base for bary.f varying fetch instrs:
2968 *
2969 * TODO defer creating ctx->ij_pixel and corresponding sysvals
2970 * until emit_intrinsic when we know they are actually needed.
2971 * For now, we defer creating ctx->ij_centroid, etc, since we
2972 * only need ij_pixel for "old style" varying inputs (ie.
2973 * tgsi_to_nir)
2974 */
2975 struct ir3_instruction *vcoord = NULL;
2976 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2977 struct ir3_instruction *xy[2];
2978
2979 vcoord = create_input_compmask(ctx, 0, 0x3);
2980 ir3_split_dest(ctx->block, xy, vcoord, 0, 2);
2981
2982 ctx->ij_pixel = ir3_create_collect(ctx, xy, 2);
2983 }
2984
2985 /* Setup inputs: */
2986 nir_foreach_variable(var, &ctx->s->inputs) {
2987 setup_input(ctx, var);
2988 }
2989
2990 /* Defer add_sysval_input() stuff until after setup_inputs(),
2991 * because sysvals need to be appended after varyings:
2992 */
2993 if (vcoord) {
2994 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PIXEL,
2995 0x3, vcoord);
2996 }
2997
2998 if (ctx->primitive_id)
2999 add_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, ctx->primitive_id);
3000 if (ctx->gs_header)
3001 add_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, ctx->gs_header);
3002
3003 /* Setup outputs: */
3004 nir_foreach_variable(var, &ctx->s->outputs) {
3005 setup_output(ctx, var);
3006 }
3007
3008 /* Set up the gs header as an output for the vertex shader so it won't
3009 * clobber it for the tess ctrl shader. */
3010 if (ctx->so->type == MESA_SHADER_VERTEX) {
3011 struct ir3_shader_variant *so = ctx->so;
3012 if (ctx->primitive_id) {
3013 unsigned n = so->outputs_count++;
3014 so->outputs[n].slot = VARYING_SLOT_PRIMITIVE_ID;
3015 so->outputs[n].regid = regid(n, 0);
3016 ctx->ir->outputs[n * 4] = ctx->primitive_id;
3017
3018 compile_assert(ctx, n * 4 < ctx->ir->noutputs);
3019 }
3020
3021 if (ctx->gs_header) {
3022 unsigned n = so->outputs_count++;
3023 so->outputs[n].slot = VARYING_SLOT_GS_HEADER_IR3;
3024 so->outputs[n].regid = regid(n, 0);
3025 ctx->ir->outputs[n * 4] = ctx->gs_header;
3026
3027 compile_assert(ctx, n * 4 < ctx->ir->noutputs);
3028 }
3029
3030 }
3031
3032 /* Find # of samplers: */
3033 nir_foreach_variable(var, &ctx->s->uniforms) {
3034 ctx->so->num_samp += glsl_type_get_sampler_count(var->type);
3035 /* just assume that we'll be reading from images.. if it
3036 * is write-only we don't have to count it, but not sure
3037 * if there is a good way to know?
3038 */
3039 ctx->so->num_samp += glsl_type_get_image_count(var->type);
3040 }
3041
3042 /* NOTE: need to do something more clever when we support >1 fxn */
3043 nir_foreach_register(reg, &fxn->registers) {
3044 ir3_declare_array(ctx, reg);
3045 }
3046 /* And emit the body: */
3047 ctx->impl = fxn;
3048 emit_function(ctx, fxn);
3049 }
3050
3051 /* from NIR perspective, we actually have varying inputs. But the varying
3052 * inputs, from an IR standpoint, are just bary.f/ldlv instructions. The
3053 * only actual inputs are the sysvals.
3054 */
3055 static void
3056 fixup_frag_inputs(struct ir3_context *ctx)
3057 {
3058 struct ir3_shader_variant *so = ctx->so;
3059 struct ir3 *ir = ctx->ir;
3060 unsigned i = 0;
3061
3062 /* sysvals should appear at the end of the inputs, drop everything else: */
3063 while ((i < so->inputs_count) && !so->inputs[i].sysval)
3064 i++;
3065
3066 /* at IR level, inputs are always blocks of 4 scalars: */
3067 i *= 4;
3068
3069 ir->inputs = &ir->inputs[i];
3070 ir->ninputs -= i;
3071 }
3072
3073 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3074 * need to assign the tex state indexes for these after we know the
3075 * max tex index.
3076 */
3077 static void
3078 fixup_astc_srgb(struct ir3_context *ctx)
3079 {
3080 struct ir3_shader_variant *so = ctx->so;
3081 /* indexed by original tex idx, value is newly assigned alpha sampler
3082 * state tex idx. Zero is invalid since there is at least one sampler
3083 * if we get here.
3084 */
3085 unsigned alt_tex_state[16] = {0};
3086 unsigned tex_idx = ctx->max_texture_index + 1;
3087 unsigned idx = 0;
3088
3089 so->astc_srgb.base = tex_idx;
3090
3091 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
3092 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
3093
3094 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
3095
3096 if (alt_tex_state[sam->cat5.tex] == 0) {
3097 /* assign new alternate/alpha tex state slot: */
3098 alt_tex_state[sam->cat5.tex] = tex_idx++;
3099 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
3100 so->astc_srgb.count++;
3101 }
3102
3103 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
3104 }
3105 }
3106
3107 static void
3108 fixup_binning_pass(struct ir3_context *ctx)
3109 {
3110 struct ir3_shader_variant *so = ctx->so;
3111 struct ir3 *ir = ctx->ir;
3112 unsigned i, j;
3113
3114 for (i = 0, j = 0; i < so->outputs_count; i++) {
3115 unsigned slot = so->outputs[i].slot;
3116
3117 /* throw away everything but first position/psize */
3118 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3119 if (i != j) {
3120 so->outputs[j] = so->outputs[i];
3121 ir->outputs[(j*4)+0] = ir->outputs[(i*4)+0];
3122 ir->outputs[(j*4)+1] = ir->outputs[(i*4)+1];
3123 ir->outputs[(j*4)+2] = ir->outputs[(i*4)+2];
3124 ir->outputs[(j*4)+3] = ir->outputs[(i*4)+3];
3125 }
3126 j++;
3127 }
3128 }
3129 so->outputs_count = j;
3130 ir->noutputs = j * 4;
3131 }
3132
3133 static void
3134 collect_tex_prefetches(struct ir3_context *ctx, struct ir3 *ir)
3135 {
3136 unsigned idx = 0;
3137
3138 /* Collect sampling instructions eligible for pre-dispatch. */
3139 list_for_each_entry(struct ir3_block, block, &ir->block_list, node) {
3140 list_for_each_entry_safe(struct ir3_instruction, instr,
3141 &block->instr_list, node) {
3142 if (instr->opc == OPC_META_TEX_PREFETCH) {
3143 assert(idx < ARRAY_SIZE(ctx->so->sampler_prefetch));
3144 struct ir3_sampler_prefetch *fetch =
3145 &ctx->so->sampler_prefetch[idx];
3146 idx++;
3147
3148 fetch->cmd = IR3_SAMPLER_PREFETCH_CMD;
3149 fetch->wrmask = instr->regs[0]->wrmask;
3150 fetch->tex_id = instr->prefetch.tex;
3151 fetch->samp_id = instr->prefetch.samp;
3152 fetch->dst = instr->regs[0]->num;
3153 fetch->src = instr->prefetch.input_offset;
3154
3155 ctx->so->total_in =
3156 MAX2(ctx->so->total_in, instr->prefetch.input_offset + 2);
3157
3158 /* Disable half precision until supported. */
3159 fetch->half_precision = 0x0;
3160
3161 /* Remove the prefetch placeholder instruction: */
3162 list_delinit(&instr->node);
3163 }
3164 }
3165 }
3166 }
3167
3168 int
3169 ir3_compile_shader_nir(struct ir3_compiler *compiler,
3170 struct ir3_shader_variant *so)
3171 {
3172 struct ir3_context *ctx;
3173 struct ir3 *ir;
3174 struct ir3_instruction **inputs;
3175 unsigned i;
3176 int ret = 0, max_bary;
3177
3178 assert(!so->ir);
3179
3180 ctx = ir3_context_init(compiler, so);
3181 if (!ctx) {
3182 DBG("INIT failed!");
3183 ret = -1;
3184 goto out;
3185 }
3186
3187 emit_instructions(ctx);
3188
3189 if (ctx->error) {
3190 DBG("EMIT failed!");
3191 ret = -1;
3192 goto out;
3193 }
3194
3195 ir = so->ir = ctx->ir;
3196
3197 /* keep track of the inputs from TGSI perspective.. */
3198 inputs = ir->inputs;
3199
3200 /* but fixup actual inputs for frag shader: */
3201 if (so->type == MESA_SHADER_FRAGMENT)
3202 fixup_frag_inputs(ctx);
3203
3204 /* at this point, for binning pass, throw away unneeded outputs: */
3205 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
3206 fixup_binning_pass(ctx);
3207
3208 /* if we want half-precision outputs, mark the output registers
3209 * as half:
3210 */
3211 if (so->key.half_precision) {
3212 for (i = 0; i < ir->noutputs; i++) {
3213 struct ir3_instruction *out = ir->outputs[i];
3214
3215 if (!out)
3216 continue;
3217
3218 /* if frag shader writes z, that needs to be full precision: */
3219 if (so->outputs[i/4].slot == FRAG_RESULT_DEPTH)
3220 continue;
3221
3222 out->regs[0]->flags |= IR3_REG_HALF;
3223 /* output could be a fanout (ie. texture fetch output)
3224 * in which case we need to propagate the half-reg flag
3225 * up to the definer so that RA sees it:
3226 */
3227 if (out->opc == OPC_META_FO) {
3228 out = out->regs[1]->instr;
3229 out->regs[0]->flags |= IR3_REG_HALF;
3230 }
3231
3232 if (out->opc == OPC_MOV) {
3233 out->cat1.dst_type = half_type(out->cat1.dst_type);
3234 }
3235 }
3236 }
3237
3238 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3239 printf("BEFORE CP:\n");
3240 ir3_print(ir);
3241 }
3242
3243 ir3_cp(ir, so);
3244
3245 /* at this point, for binning pass, throw away unneeded outputs:
3246 * Note that for a6xx and later, we do this after ir3_cp to ensure
3247 * that the uniform/constant layout for BS and VS matches, so that
3248 * we can re-use same VS_CONST state group.
3249 */
3250 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
3251 fixup_binning_pass(ctx);
3252
3253 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3254 * need to make sure not to remove any inputs that are used by
3255 * the nonbinning VS.
3256 */
3257 if (ctx->compiler->gpu_id >= 600 && so->binning_pass) {
3258 debug_assert(so->type == MESA_SHADER_VERTEX);
3259 for (int i = 0; i < ir->ninputs; i++) {
3260 struct ir3_instruction *in = ir->inputs[i];
3261
3262 if (!in)
3263 continue;
3264
3265 unsigned n = i / 4;
3266 unsigned c = i % 4;
3267
3268 debug_assert(n < so->nonbinning->inputs_count);
3269
3270 if (so->nonbinning->inputs[n].sysval)
3271 continue;
3272
3273 /* be sure to keep inputs, even if only used in VS */
3274 if (so->nonbinning->inputs[n].compmask & (1 << c))
3275 array_insert(in->block, in->block->keeps, in);
3276 }
3277 }
3278
3279 /* Insert mov if there's same instruction for each output.
3280 * eg. dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_expression.vertex.sampler2dshadow
3281 */
3282 for (int i = ir->noutputs - 1; i >= 0; i--) {
3283 if (!ir->outputs[i])
3284 continue;
3285 for (unsigned j = 0; j < i; j++) {
3286 if (ir->outputs[i] == ir->outputs[j]) {
3287 ir->outputs[i] =
3288 ir3_MOV(ir->outputs[i]->block, ir->outputs[i], TYPE_F32);
3289 }
3290 }
3291 }
3292
3293 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3294 printf("BEFORE GROUPING:\n");
3295 ir3_print(ir);
3296 }
3297
3298 ir3_sched_add_deps(ir);
3299
3300 /* Group left/right neighbors, inserting mov's where needed to
3301 * solve conflicts:
3302 */
3303 ir3_group(ir);
3304
3305 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3306 printf("AFTER GROUPING:\n");
3307 ir3_print(ir);
3308 }
3309
3310 ir3_depth(ir, so);
3311
3312 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3313 printf("AFTER DEPTH:\n");
3314 ir3_print(ir);
3315 }
3316
3317 /* do Sethi–Ullman numbering before scheduling: */
3318 ir3_sun(ir);
3319
3320 ret = ir3_sched(ir);
3321 if (ret) {
3322 DBG("SCHED failed!");
3323 goto out;
3324 }
3325
3326 if (compiler->gpu_id >= 600) {
3327 ir3_a6xx_fixup_atomic_dests(ir, so);
3328 }
3329
3330 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3331 printf("AFTER SCHED:\n");
3332 ir3_print(ir);
3333 }
3334
3335 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3336 * with draw pass VS, so binning and draw pass can both use the
3337 * same VBO state.
3338 *
3339 * Note that VS inputs are expected to be full precision.
3340 */
3341 bool pre_assign_inputs = (ir->compiler->gpu_id >= 600) &&
3342 (ir->type == MESA_SHADER_VERTEX) &&
3343 so->binning_pass;
3344
3345 if (pre_assign_inputs) {
3346 for (unsigned i = 0; i < ir->ninputs; i++) {
3347 struct ir3_instruction *instr = ir->inputs[i];
3348
3349 if (!instr)
3350 continue;
3351
3352 unsigned n = i / 4;
3353 unsigned c = i % 4;
3354 unsigned regid = so->nonbinning->inputs[n].regid + c;
3355
3356 instr->regs[0]->num = regid;
3357 }
3358
3359 ret = ir3_ra(so, ir->inputs, ir->ninputs);
3360 } else if (ctx->gs_header) {
3361 /* We need to have these values in the same registers between VS and GS
3362 * since the VS chains to GS and doesn't get the sysvals redelivered.
3363 */
3364
3365 ctx->gs_header->regs[0]->num = 0;
3366 ctx->primitive_id->regs[0]->num = 1;
3367 struct ir3_instruction *precolor[] = { ctx->gs_header, ctx->primitive_id };
3368 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3369 } else if (so->num_sampler_prefetch) {
3370 assert(so->type == MESA_SHADER_FRAGMENT);
3371 struct ir3_instruction *precolor[2];
3372 int idx = 0;
3373
3374 for (unsigned i = 0; i < ir->ninputs; i++) {
3375 struct ir3_instruction *instr = ctx->ir->inputs[i];
3376
3377 if (!instr)
3378 continue;
3379
3380 if (instr->input.sysval != SYSTEM_VALUE_BARYCENTRIC_PIXEL)
3381 continue;
3382
3383 assert(idx < ARRAY_SIZE(precolor));
3384
3385 precolor[idx] = instr;
3386 instr->regs[0]->num = idx;
3387
3388 idx++;
3389 }
3390 ret = ir3_ra(so, precolor, idx);
3391 } else {
3392 ret = ir3_ra(so, NULL, 0);
3393 }
3394
3395 if (ret) {
3396 DBG("RA failed!");
3397 goto out;
3398 }
3399
3400 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3401 printf("AFTER RA:\n");
3402 ir3_print(ir);
3403 }
3404
3405 if (so->type == MESA_SHADER_FRAGMENT)
3406 pack_inlocs(ctx);
3407
3408 /* fixup input/outputs: */
3409 for (i = 0; i < so->outputs_count; i++) {
3410 /* sometimes we get outputs that don't write the .x coord, like:
3411 *
3412 * decl_var shader_out INTERP_MODE_NONE float Color (VARYING_SLOT_VAR9.z, 1, 0)
3413 *
3414 * Presumably the result of varying packing and then eliminating
3415 * some unneeded varyings? Just skip head to the first valid
3416 * component of the output.
3417 */
3418 for (unsigned j = 0; j < 4; j++) {
3419 struct ir3_instruction *instr = ir->outputs[(i*4) + j];
3420 if (instr) {
3421 so->outputs[i].regid = instr->regs[0]->num;
3422 so->outputs[i].half = !!(instr->regs[0]->flags & IR3_REG_HALF);
3423 break;
3424 }
3425 }
3426 }
3427
3428 /* Note that some or all channels of an input may be unused: */
3429 for (i = 0; i < so->inputs_count; i++) {
3430 unsigned j, reg = regid(63,0);
3431 bool half = false;
3432 for (j = 0; j < 4; j++) {
3433 struct ir3_instruction *in = inputs[(i*4) + j];
3434
3435 if (!in)
3436 continue;
3437
3438 if (in->flags & IR3_INSTR_UNUSED)
3439 continue;
3440
3441 reg = in->regs[0]->num - j;
3442 if (half) {
3443 compile_assert(ctx, in->regs[0]->flags & IR3_REG_HALF);
3444 } else {
3445 half = !!(in->regs[0]->flags & IR3_REG_HALF);
3446 }
3447 }
3448 so->inputs[i].regid = reg;
3449 so->inputs[i].half = half;
3450 }
3451
3452 if (ctx->astc_srgb)
3453 fixup_astc_srgb(ctx);
3454
3455 /* We need to do legalize after (for frag shader's) the "bary.f"
3456 * offsets (inloc) have been assigned.
3457 */
3458 ir3_legalize(ir, &so->has_ssbo, &so->need_pixlod, &max_bary);
3459
3460 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3461 printf("AFTER LEGALIZE:\n");
3462 ir3_print(ir);
3463 }
3464
3465 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3466 * know what we might have to wait on when coming in from VS chsh.
3467 */
3468 if (so->type == MESA_SHADER_TESS_CTRL ||
3469 so->type == MESA_SHADER_GEOMETRY ) {
3470 list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
3471 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
3472 instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
3473 break;
3474 }
3475 }
3476 }
3477
3478 so->branchstack = ctx->max_stack;
3479
3480 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3481 if (so->type == MESA_SHADER_FRAGMENT)
3482 so->total_in = max_bary + 1;
3483
3484 so->max_sun = ir->max_sun;
3485
3486 /* Collect sampling instructions eligible for pre-dispatch. */
3487 collect_tex_prefetches(ctx, ir);
3488
3489 out:
3490 if (ret) {
3491 if (so->ir)
3492 ir3_destroy(so->ir);
3493 so->ir = NULL;
3494 }
3495 ir3_context_free(ctx);
3496
3497 return ret;
3498 }