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freedreno/ir3: Stop doing b2n on the SEL condition.
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 __ssa_dst(mov);
55 src = __ssa_src(mov, collect, IR3_REG_RELATIV);
56 src->size = arrsz;
57 src->array.offset = n;
58
59 ir3_instr_set_address(mov, address);
60
61 return mov;
62 }
63
64 static struct ir3_instruction *
65 create_input(struct ir3_context *ctx, unsigned compmask)
66 {
67 struct ir3_instruction *in;
68
69 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
70 in->input.sysval = ~0;
71 __ssa_dst(in)->wrmask = compmask;
72
73 array_insert(ctx->ir, ctx->ir->inputs, in);
74
75 return in;
76 }
77
78 static struct ir3_instruction *
79 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
80 {
81 struct ir3_block *block = ctx->block;
82 struct ir3_instruction *instr;
83 /* packed inloc is fixed up later: */
84 struct ir3_instruction *inloc = create_immed(block, n);
85
86 if (use_ldlv) {
87 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
88 instr->cat6.type = TYPE_U32;
89 instr->cat6.iim_val = 1;
90 } else {
91 instr = ir3_BARY_F(block, inloc, 0, ctx->ij_pixel, 0);
92 instr->regs[2]->wrmask = 0x3;
93 }
94
95 return instr;
96 }
97
98 static struct ir3_instruction *
99 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
100 {
101 /* first four vec4 sysval's reserved for UBOs: */
102 /* NOTE: dp is in scalar, but there can be >4 dp components: */
103 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
104 unsigned n = const_state->offsets.driver_param;
105 unsigned r = regid(n + dp / 4, dp % 4);
106 return create_uniform(ctx->block, r);
107 }
108
109 /*
110 * Adreno uses uint rather than having dedicated bool type,
111 * which (potentially) requires some conversion, in particular
112 * when using output of an bool instr to int input, or visa
113 * versa.
114 *
115 * | Adreno | NIR |
116 * -------+---------+-------+-
117 * true | 1 | ~0 |
118 * false | 0 | 0 |
119 *
120 * To convert from an adreno bool (uint) to nir, use:
121 *
122 * absneg.s dst, (neg)src
123 *
124 * To convert back in the other direction:
125 *
126 * absneg.s dst, (abs)arc
127 *
128 * The CP step can clean up the absneg.s that cancel each other
129 * out, and with a slight bit of extra cleverness (to recognize
130 * the instructions which produce either a 0 or 1) can eliminate
131 * the absneg.s's completely when an instruction that wants
132 * 0/1 consumes the result. For example, when a nir 'bcsel'
133 * consumes the result of 'feq'. So we should be able to get by
134 * without a boolean resolve step, and without incuring any
135 * extra penalty in instruction count.
136 */
137
138 /* NIR bool -> native (adreno): */
139 static struct ir3_instruction *
140 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
141 {
142 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
143 }
144
145 /* native (adreno) -> NIR bool: */
146 static struct ir3_instruction *
147 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
148 {
149 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
150 }
151
152 /*
153 * alu/sfu instructions:
154 */
155
156 static struct ir3_instruction *
157 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
158 unsigned src_bitsize, nir_op op)
159 {
160 type_t src_type, dst_type;
161
162 switch (op) {
163 case nir_op_f2f32:
164 case nir_op_f2f16_rtne:
165 case nir_op_f2f16_rtz:
166 case nir_op_f2f16:
167 case nir_op_f2i32:
168 case nir_op_f2i16:
169 case nir_op_f2i8:
170 case nir_op_f2u32:
171 case nir_op_f2u16:
172 case nir_op_f2u8:
173 switch (src_bitsize) {
174 case 32:
175 src_type = TYPE_F32;
176 break;
177 case 16:
178 src_type = TYPE_F16;
179 break;
180 default:
181 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
182 }
183 break;
184
185 case nir_op_i2f32:
186 case nir_op_i2f16:
187 case nir_op_i2i32:
188 case nir_op_i2i16:
189 case nir_op_i2i8:
190 switch (src_bitsize) {
191 case 32:
192 src_type = TYPE_S32;
193 break;
194 case 16:
195 src_type = TYPE_S16;
196 break;
197 case 8:
198 src_type = TYPE_S8;
199 break;
200 default:
201 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
202 }
203 break;
204
205 case nir_op_u2f32:
206 case nir_op_u2f16:
207 case nir_op_u2u32:
208 case nir_op_u2u16:
209 case nir_op_u2u8:
210 switch (src_bitsize) {
211 case 32:
212 src_type = TYPE_U32;
213 break;
214 case 16:
215 src_type = TYPE_U16;
216 break;
217 case 8:
218 src_type = TYPE_U8;
219 break;
220 default:
221 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
222 }
223 break;
224
225 default:
226 ir3_context_error(ctx, "invalid conversion op: %u", op);
227 }
228
229 switch (op) {
230 case nir_op_f2f32:
231 case nir_op_i2f32:
232 case nir_op_u2f32:
233 dst_type = TYPE_F32;
234 break;
235
236 case nir_op_f2f16_rtne:
237 case nir_op_f2f16_rtz:
238 case nir_op_f2f16:
239 /* TODO how to handle rounding mode? */
240 case nir_op_i2f16:
241 case nir_op_u2f16:
242 dst_type = TYPE_F16;
243 break;
244
245 case nir_op_f2i32:
246 case nir_op_i2i32:
247 dst_type = TYPE_S32;
248 break;
249
250 case nir_op_f2i16:
251 case nir_op_i2i16:
252 dst_type = TYPE_S16;
253 break;
254
255 case nir_op_f2i8:
256 case nir_op_i2i8:
257 dst_type = TYPE_S8;
258 break;
259
260 case nir_op_f2u32:
261 case nir_op_u2u32:
262 dst_type = TYPE_U32;
263 break;
264
265 case nir_op_f2u16:
266 case nir_op_u2u16:
267 dst_type = TYPE_U16;
268 break;
269
270 case nir_op_f2u8:
271 case nir_op_u2u8:
272 dst_type = TYPE_U8;
273 break;
274
275 default:
276 ir3_context_error(ctx, "invalid conversion op: %u", op);
277 }
278
279 return ir3_COV(ctx->block, src, src_type, dst_type);
280 }
281
282 static void
283 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
284 {
285 const nir_op_info *info = &nir_op_infos[alu->op];
286 struct ir3_instruction **dst, *src[info->num_inputs];
287 unsigned bs[info->num_inputs]; /* bit size */
288 struct ir3_block *b = ctx->block;
289 unsigned dst_sz, wrmask;
290 type_t dst_type = nir_dest_bit_size(alu->dest.dest) < 32 ?
291 TYPE_U16 : TYPE_U32;
292
293 if (alu->dest.dest.is_ssa) {
294 dst_sz = alu->dest.dest.ssa.num_components;
295 wrmask = (1 << dst_sz) - 1;
296 } else {
297 dst_sz = alu->dest.dest.reg.reg->num_components;
298 wrmask = alu->dest.write_mask;
299 }
300
301 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
302
303 /* Vectors are special in that they have non-scalarized writemasks,
304 * and just take the first swizzle channel for each argument in
305 * order into each writemask channel.
306 */
307 if ((alu->op == nir_op_vec2) ||
308 (alu->op == nir_op_vec3) ||
309 (alu->op == nir_op_vec4)) {
310
311 for (int i = 0; i < info->num_inputs; i++) {
312 nir_alu_src *asrc = &alu->src[i];
313
314 compile_assert(ctx, !asrc->abs);
315 compile_assert(ctx, !asrc->negate);
316
317 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
318 if (!src[i])
319 src[i] = create_immed_typed(ctx->block, 0, dst_type);
320 dst[i] = ir3_MOV(b, src[i], dst_type);
321 }
322
323 ir3_put_dst(ctx, &alu->dest.dest);
324 return;
325 }
326
327 /* We also get mov's with more than one component for mov's so
328 * handle those specially:
329 */
330 if (alu->op == nir_op_mov) {
331 nir_alu_src *asrc = &alu->src[0];
332 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
333
334 for (unsigned i = 0; i < dst_sz; i++) {
335 if (wrmask & (1 << i)) {
336 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
337 } else {
338 dst[i] = NULL;
339 }
340 }
341
342 ir3_put_dst(ctx, &alu->dest.dest);
343 return;
344 }
345
346 /* General case: We can just grab the one used channel per src. */
347 for (int i = 0; i < info->num_inputs; i++) {
348 unsigned chan = ffs(alu->dest.write_mask) - 1;
349 nir_alu_src *asrc = &alu->src[i];
350
351 compile_assert(ctx, !asrc->abs);
352 compile_assert(ctx, !asrc->negate);
353
354 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
355 bs[i] = nir_src_bit_size(asrc->src);
356
357 compile_assert(ctx, src[i]);
358 }
359
360 switch (alu->op) {
361 case nir_op_f2f32:
362 case nir_op_f2f16_rtne:
363 case nir_op_f2f16_rtz:
364 case nir_op_f2f16:
365 case nir_op_f2i32:
366 case nir_op_f2i16:
367 case nir_op_f2i8:
368 case nir_op_f2u32:
369 case nir_op_f2u16:
370 case nir_op_f2u8:
371 case nir_op_i2f32:
372 case nir_op_i2f16:
373 case nir_op_i2i32:
374 case nir_op_i2i16:
375 case nir_op_i2i8:
376 case nir_op_u2f32:
377 case nir_op_u2f16:
378 case nir_op_u2u32:
379 case nir_op_u2u16:
380 case nir_op_u2u8:
381 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
382 break;
383 case nir_op_fquantize2f16:
384 dst[0] = create_cov(ctx,
385 create_cov(ctx, src[0], 32, nir_op_f2f16),
386 16, nir_op_f2f32);
387 break;
388 case nir_op_f2b16: {
389 struct ir3_instruction *zero = create_immed_typed(b, 0, TYPE_F16);
390 dst[0] = ir3_CMPS_F(b, src[0], 0, zero, 0);
391 dst[0]->cat2.condition = IR3_COND_NE;
392 break;
393 }
394 case nir_op_f2b32:
395 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
396 dst[0]->cat2.condition = IR3_COND_NE;
397 break;
398 case nir_op_b2f16:
399 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F16);
400 break;
401 case nir_op_b2f32:
402 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
403 break;
404 case nir_op_b2i8:
405 case nir_op_b2i16:
406 case nir_op_b2i32:
407 dst[0] = ir3_b2n(b, src[0]);
408 break;
409 case nir_op_i2b16: {
410 struct ir3_instruction *zero = create_immed_typed(b, 0, TYPE_S16);
411 dst[0] = ir3_CMPS_S(b, src[0], 0, zero, 0);
412 dst[0]->cat2.condition = IR3_COND_NE;
413 break;
414 }
415 case nir_op_i2b32:
416 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
417 dst[0]->cat2.condition = IR3_COND_NE;
418 break;
419
420 case nir_op_fneg:
421 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
422 break;
423 case nir_op_fabs:
424 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
425 break;
426 case nir_op_fmax:
427 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
428 break;
429 case nir_op_fmin:
430 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
431 break;
432 case nir_op_fsat:
433 /* if there is just a single use of the src, and it supports
434 * (sat) bit, we can just fold the (sat) flag back to the
435 * src instruction and create a mov. This is easier for cp
436 * to eliminate.
437 *
438 * TODO probably opc_cat==4 is ok too
439 */
440 if (alu->src[0].src.is_ssa &&
441 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
442 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
443 src[0]->flags |= IR3_INSTR_SAT;
444 dst[0] = ir3_MOV(b, src[0], dst_type);
445 } else {
446 /* otherwise generate a max.f that saturates.. blob does
447 * similar (generating a cat2 mov using max.f)
448 */
449 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
450 dst[0]->flags |= IR3_INSTR_SAT;
451 }
452 break;
453 case nir_op_fmul:
454 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
455 break;
456 case nir_op_fadd:
457 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
458 break;
459 case nir_op_fsub:
460 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
461 break;
462 case nir_op_ffma:
463 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
464 break;
465 case nir_op_fddx:
466 case nir_op_fddx_coarse:
467 dst[0] = ir3_DSX(b, src[0], 0);
468 dst[0]->cat5.type = TYPE_F32;
469 break;
470 case nir_op_fddx_fine:
471 dst[0] = ir3_DSXPP_1(b, src[0], 0);
472 dst[0]->cat5.type = TYPE_F32;
473 break;
474 case nir_op_fddy:
475 case nir_op_fddy_coarse:
476 dst[0] = ir3_DSY(b, src[0], 0);
477 dst[0]->cat5.type = TYPE_F32;
478 break;
479 break;
480 case nir_op_fddy_fine:
481 dst[0] = ir3_DSYPP_1(b, src[0], 0);
482 dst[0]->cat5.type = TYPE_F32;
483 break;
484 case nir_op_flt16:
485 case nir_op_flt32:
486 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
487 dst[0]->cat2.condition = IR3_COND_LT;
488 break;
489 case nir_op_fge16:
490 case nir_op_fge32:
491 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
492 dst[0]->cat2.condition = IR3_COND_GE;
493 break;
494 case nir_op_feq16:
495 case nir_op_feq32:
496 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
497 dst[0]->cat2.condition = IR3_COND_EQ;
498 break;
499 case nir_op_fne16:
500 case nir_op_fne32:
501 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
502 dst[0]->cat2.condition = IR3_COND_NE;
503 break;
504 case nir_op_fceil:
505 dst[0] = ir3_CEIL_F(b, src[0], 0);
506 break;
507 case nir_op_ffloor:
508 dst[0] = ir3_FLOOR_F(b, src[0], 0);
509 break;
510 case nir_op_ftrunc:
511 dst[0] = ir3_TRUNC_F(b, src[0], 0);
512 break;
513 case nir_op_fround_even:
514 dst[0] = ir3_RNDNE_F(b, src[0], 0);
515 break;
516 case nir_op_fsign:
517 dst[0] = ir3_SIGN_F(b, src[0], 0);
518 break;
519
520 case nir_op_fsin:
521 dst[0] = ir3_SIN(b, src[0], 0);
522 break;
523 case nir_op_fcos:
524 dst[0] = ir3_COS(b, src[0], 0);
525 break;
526 case nir_op_frsq:
527 dst[0] = ir3_RSQ(b, src[0], 0);
528 break;
529 case nir_op_frcp:
530 dst[0] = ir3_RCP(b, src[0], 0);
531 break;
532 case nir_op_flog2:
533 dst[0] = ir3_LOG2(b, src[0], 0);
534 break;
535 case nir_op_fexp2:
536 dst[0] = ir3_EXP2(b, src[0], 0);
537 break;
538 case nir_op_fsqrt:
539 dst[0] = ir3_SQRT(b, src[0], 0);
540 break;
541
542 case nir_op_iabs:
543 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
544 break;
545 case nir_op_iadd:
546 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
547 break;
548 case nir_op_iand:
549 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
550 break;
551 case nir_op_imax:
552 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
553 break;
554 case nir_op_umax:
555 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
556 break;
557 case nir_op_imin:
558 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
559 break;
560 case nir_op_umin:
561 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
562 break;
563 case nir_op_umul_low:
564 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
565 break;
566 case nir_op_imadsh_mix16:
567 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
568 break;
569 case nir_op_imad24_ir3:
570 dst[0] = ir3_MAD_S24(b, src[0], 0, src[1], 0, src[2], 0);
571 break;
572 case nir_op_imul24:
573 dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
574 break;
575 case nir_op_ineg:
576 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
577 break;
578 case nir_op_inot:
579 dst[0] = ir3_NOT_B(b, src[0], 0);
580 break;
581 case nir_op_ior:
582 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
583 break;
584 case nir_op_ishl:
585 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
586 break;
587 case nir_op_ishr:
588 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
589 break;
590 case nir_op_isub:
591 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
592 break;
593 case nir_op_ixor:
594 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
595 break;
596 case nir_op_ushr:
597 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
598 break;
599 case nir_op_ilt16:
600 case nir_op_ilt32:
601 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
602 dst[0]->cat2.condition = IR3_COND_LT;
603 break;
604 case nir_op_ige16:
605 case nir_op_ige32:
606 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
607 dst[0]->cat2.condition = IR3_COND_GE;
608 break;
609 case nir_op_ieq16:
610 case nir_op_ieq32:
611 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
612 dst[0]->cat2.condition = IR3_COND_EQ;
613 break;
614 case nir_op_ine16:
615 case nir_op_ine32:
616 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
617 dst[0]->cat2.condition = IR3_COND_NE;
618 break;
619 case nir_op_ult16:
620 case nir_op_ult32:
621 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
622 dst[0]->cat2.condition = IR3_COND_LT;
623 break;
624 case nir_op_uge16:
625 case nir_op_uge32:
626 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
627 dst[0]->cat2.condition = IR3_COND_GE;
628 break;
629
630 case nir_op_b16csel:
631 case nir_op_b32csel: {
632 struct ir3_instruction *cond = src[0];
633
634 /* If src[0] is a negation (likely as a result of an ir3_b2n(cond)),
635 * we can ignore that and use original cond, since the nonzero-ness of
636 * cond stays the same.
637 */
638 if (cond->opc == OPC_ABSNEG_S &&
639 cond->flags == 0 &&
640 (cond->regs[1]->flags & (IR3_REG_SNEG | IR3_REG_SABS)) == IR3_REG_SNEG) {
641 cond = cond->regs[1]->instr;
642 }
643
644 compile_assert(ctx, bs[1] == bs[2]);
645 /* Make sure the boolean condition has the same bit size as the other
646 * two arguments, adding a conversion if necessary.
647 */
648 if (bs[1] < bs[0])
649 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
650 else if (bs[1] > bs[0])
651 cond = ir3_COV(b, cond, TYPE_U16, TYPE_U32);
652
653 if (bs[1] > 16)
654 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
655 else
656 dst[0] = ir3_SEL_B16(b, src[1], 0, cond, 0, src[2], 0);
657 break;
658 }
659 case nir_op_bit_count: {
660 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
661 // double check on earlier gen's. Once half-precision support is
662 // in place, this should probably move to a NIR lowering pass:
663 struct ir3_instruction *hi, *lo;
664
665 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
666 TYPE_U32, TYPE_U16);
667 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
668
669 hi = ir3_CBITS_B(b, hi, 0);
670 lo = ir3_CBITS_B(b, lo, 0);
671
672 // TODO maybe the builders should default to making dst half-precision
673 // if the src's were half precision, to make this less awkward.. otoh
674 // we should probably just do this lowering in NIR.
675 hi->regs[0]->flags |= IR3_REG_HALF;
676 lo->regs[0]->flags |= IR3_REG_HALF;
677
678 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
679 dst[0]->regs[0]->flags |= IR3_REG_HALF;
680 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
681 break;
682 }
683 case nir_op_ifind_msb: {
684 struct ir3_instruction *cmp;
685 dst[0] = ir3_CLZ_S(b, src[0], 0);
686 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
687 cmp->cat2.condition = IR3_COND_GE;
688 dst[0] = ir3_SEL_B32(b,
689 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
690 cmp, 0, dst[0], 0);
691 break;
692 }
693 case nir_op_ufind_msb:
694 dst[0] = ir3_CLZ_B(b, src[0], 0);
695 dst[0] = ir3_SEL_B32(b,
696 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
697 src[0], 0, dst[0], 0);
698 break;
699 case nir_op_find_lsb:
700 dst[0] = ir3_BFREV_B(b, src[0], 0);
701 dst[0] = ir3_CLZ_B(b, dst[0], 0);
702 break;
703 case nir_op_bitfield_reverse:
704 dst[0] = ir3_BFREV_B(b, src[0], 0);
705 break;
706
707 default:
708 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
709 nir_op_infos[alu->op].name);
710 break;
711 }
712
713 if (nir_alu_type_get_base_type(info->output_type) == nir_type_bool) {
714 assert(dst_sz == 1);
715
716 if (nir_dest_bit_size(alu->dest.dest) < 32)
717 dst[0]->regs[0]->flags |= IR3_REG_HALF;
718
719 dst[0] = ir3_n2b(b, dst[0]);
720 }
721
722 if (nir_dest_bit_size(alu->dest.dest) < 32) {
723 for (unsigned i = 0; i < dst_sz; i++) {
724 dst[i]->regs[0]->flags |= IR3_REG_HALF;
725 }
726 }
727
728 ir3_put_dst(ctx, &alu->dest.dest);
729 }
730
731 static void
732 emit_intrinsic_load_ubo_ldc(struct ir3_context *ctx, nir_intrinsic_instr *intr,
733 struct ir3_instruction **dst)
734 {
735 struct ir3_block *b = ctx->block;
736
737 unsigned ncomp = intr->num_components;
738 struct ir3_instruction *offset = ir3_get_src(ctx, &intr->src[1])[0];
739 struct ir3_instruction *idx = ir3_get_src(ctx, &intr->src[0])[0];
740 struct ir3_instruction *ldc = ir3_LDC(b, idx, 0, offset, 0);
741 ldc->regs[0]->wrmask = MASK(ncomp);
742 ldc->cat6.iim_val = intr->num_components;
743 ldc->cat6.d = 1;
744 ldc->cat6.type = TYPE_U32;
745
746 nir_intrinsic_instr *bindless = ir3_bindless_resource(intr->src[0]);
747 if (bindless) {
748 ldc->flags |= IR3_INSTR_B;
749 ldc->cat6.base = nir_intrinsic_desc_set(bindless);
750 ctx->so->bindless_ubo = true;
751 }
752
753 ir3_split_dest(b, dst, ldc, 0, ncomp);
754 }
755
756
757 /* handles direct/indirect UBO reads: */
758 static void
759 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
760 struct ir3_instruction **dst)
761 {
762 if (ir3_bindless_resource(intr->src[0])) {
763 /* TODO: We should be using ldc for non-bindless things on a6xx as
764 * well.
765 */
766 emit_intrinsic_load_ubo_ldc(ctx, intr, dst);
767 return;
768 }
769 struct ir3_block *b = ctx->block;
770 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
771 /* UBO addresses are the first driver params, but subtract 2 here to
772 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
773 * is the uniforms: */
774 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
775 unsigned ubo = regid(const_state->offsets.ubo, 0) - 2;
776 const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
777
778 int off = 0;
779
780 /* First src is ubo index, which could either be an immed or not: */
781 src0 = ir3_get_src(ctx, &intr->src[0])[0];
782 if (is_same_type_mov(src0) &&
783 (src0->regs[1]->flags & IR3_REG_IMMED)) {
784 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
785 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
786 } else {
787 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr0(ctx, src0, ptrsz));
788 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr0(ctx, src0, ptrsz));
789
790 /* NOTE: since relative addressing is used, make sure constlen is
791 * at least big enough to cover all the UBO addresses, since the
792 * assembler won't know what the max address reg is.
793 */
794 ctx->so->constlen = MAX2(ctx->so->constlen,
795 const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
796 }
797
798 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
799 addr = base_lo;
800
801 if (nir_src_is_const(intr->src[1])) {
802 off += nir_src_as_uint(intr->src[1]);
803 } else {
804 /* For load_ubo_indirect, second src is indirect offset: */
805 src1 = ir3_get_src(ctx, &intr->src[1])[0];
806
807 /* and add offset to addr: */
808 addr = ir3_ADD_S(b, addr, 0, src1, 0);
809 }
810
811 /* if offset is to large to encode in the ldg, split it out: */
812 if ((off + (intr->num_components * 4)) > 1024) {
813 /* split out the minimal amount to improve the odds that
814 * cp can fit the immediate in the add.s instruction:
815 */
816 unsigned off2 = off + (intr->num_components * 4) - 1024;
817 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
818 off -= off2;
819 }
820
821 if (ptrsz == 2) {
822 struct ir3_instruction *carry;
823
824 /* handle 32b rollover, ie:
825 * if (addr < base_lo)
826 * base_hi++
827 */
828 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
829 carry->cat2.condition = IR3_COND_LT;
830 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
831
832 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
833 }
834
835 for (int i = 0; i < intr->num_components; i++) {
836 struct ir3_instruction *load =
837 ir3_LDG(b, addr, 0, create_immed(b, 1), 0, /* num components */
838 create_immed(b, off + i * 4), 0);
839 load->cat6.type = TYPE_U32;
840 dst[i] = load;
841 }
842 }
843
844 /* src[] = { block_index } */
845 static void
846 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
847 struct ir3_instruction **dst)
848 {
849 /* SSBO size stored as a const starting at ssbo_sizes: */
850 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
851 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
852 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
853 const_state->ssbo_size.off[blk_idx];
854
855 debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
856
857 dst[0] = create_uniform(ctx->block, idx);
858 }
859
860 /* src[] = { offset }. const_index[] = { base } */
861 static void
862 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
863 struct ir3_instruction **dst)
864 {
865 struct ir3_block *b = ctx->block;
866 struct ir3_instruction *ldl, *offset;
867 unsigned base;
868
869 offset = ir3_get_src(ctx, &intr->src[0])[0];
870 base = nir_intrinsic_base(intr);
871
872 ldl = ir3_LDL(b, offset, 0,
873 create_immed(b, intr->num_components), 0,
874 create_immed(b, base), 0);
875
876 ldl->cat6.type = utype_dst(intr->dest);
877 ldl->regs[0]->wrmask = MASK(intr->num_components);
878
879 ldl->barrier_class = IR3_BARRIER_SHARED_R;
880 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
881
882 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
883 }
884
885 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
886 static void
887 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
888 {
889 struct ir3_block *b = ctx->block;
890 struct ir3_instruction *stl, *offset;
891 struct ir3_instruction * const *value;
892 unsigned base, wrmask;
893
894 value = ir3_get_src(ctx, &intr->src[0]);
895 offset = ir3_get_src(ctx, &intr->src[1])[0];
896
897 base = nir_intrinsic_base(intr);
898 wrmask = nir_intrinsic_write_mask(intr);
899
900 /* Combine groups of consecutive enabled channels in one write
901 * message. We use ffs to find the first enabled channel and then ffs on
902 * the bit-inverse, down-shifted writemask to determine the length of
903 * the block of enabled bits.
904 *
905 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
906 */
907 while (wrmask) {
908 unsigned first_component = ffs(wrmask) - 1;
909 unsigned length = ffs(~(wrmask >> first_component)) - 1;
910
911 stl = ir3_STL(b, offset, 0,
912 ir3_create_collect(ctx, &value[first_component], length), 0,
913 create_immed(b, length), 0);
914 stl->cat6.dst_offset = first_component + base;
915 stl->cat6.type = utype_src(intr->src[0]);
916 stl->barrier_class = IR3_BARRIER_SHARED_W;
917 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
918
919 array_insert(b, b->keeps, stl);
920
921 /* Clear the bits in the writemask that we just wrote, then try
922 * again to see if more channels are left.
923 */
924 wrmask &= (15 << (first_component + length));
925 }
926 }
927
928 /* src[] = { offset }. const_index[] = { base } */
929 static void
930 emit_intrinsic_load_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr,
931 struct ir3_instruction **dst)
932 {
933 struct ir3_block *b = ctx->block;
934 struct ir3_instruction *load, *offset;
935 unsigned base;
936
937 offset = ir3_get_src(ctx, &intr->src[0])[0];
938 base = nir_intrinsic_base(intr);
939
940 load = ir3_LDLW(b, offset, 0,
941 create_immed(b, intr->num_components), 0,
942 create_immed(b, base), 0);
943
944 load->cat6.type = utype_dst(intr->dest);
945 load->regs[0]->wrmask = MASK(intr->num_components);
946
947 load->barrier_class = IR3_BARRIER_SHARED_R;
948 load->barrier_conflict = IR3_BARRIER_SHARED_W;
949
950 ir3_split_dest(b, dst, load, 0, intr->num_components);
951 }
952
953 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
954 static void
955 emit_intrinsic_store_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr)
956 {
957 struct ir3_block *b = ctx->block;
958 struct ir3_instruction *store, *offset;
959 struct ir3_instruction * const *value;
960 unsigned base, wrmask;
961
962 value = ir3_get_src(ctx, &intr->src[0]);
963 offset = ir3_get_src(ctx, &intr->src[1])[0];
964
965 base = nir_intrinsic_base(intr);
966 wrmask = nir_intrinsic_write_mask(intr);
967
968 /* Combine groups of consecutive enabled channels in one write
969 * message. We use ffs to find the first enabled channel and then ffs on
970 * the bit-inverse, down-shifted writemask to determine the length of
971 * the block of enabled bits.
972 *
973 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
974 */
975 while (wrmask) {
976 unsigned first_component = ffs(wrmask) - 1;
977 unsigned length = ffs(~(wrmask >> first_component)) - 1;
978
979 store = ir3_STLW(b, offset, 0,
980 ir3_create_collect(ctx, &value[first_component], length), 0,
981 create_immed(b, length), 0);
982
983 store->cat6.dst_offset = first_component + base;
984 store->cat6.type = utype_src(intr->src[0]);
985 store->barrier_class = IR3_BARRIER_SHARED_W;
986 store->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
987
988 array_insert(b, b->keeps, store);
989
990 /* Clear the bits in the writemask that we just wrote, then try
991 * again to see if more channels are left.
992 */
993 wrmask &= (15 << (first_component + length));
994 }
995 }
996
997 /*
998 * CS shared variable atomic intrinsics
999 *
1000 * All of the shared variable atomic memory operations read a value from
1001 * memory, compute a new value using one of the operations below, write the
1002 * new value to memory, and return the original value read.
1003 *
1004 * All operations take 2 sources except CompSwap that takes 3. These
1005 * sources represent:
1006 *
1007 * 0: The offset into the shared variable storage region that the atomic
1008 * operation will operate on.
1009 * 1: The data parameter to the atomic function (i.e. the value to add
1010 * in shared_atomic_add, etc).
1011 * 2: For CompSwap only: the second data parameter.
1012 */
1013 static struct ir3_instruction *
1014 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1015 {
1016 struct ir3_block *b = ctx->block;
1017 struct ir3_instruction *atomic, *src0, *src1;
1018 type_t type = TYPE_U32;
1019
1020 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
1021 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
1022
1023 switch (intr->intrinsic) {
1024 case nir_intrinsic_shared_atomic_add:
1025 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
1026 break;
1027 case nir_intrinsic_shared_atomic_imin:
1028 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
1029 type = TYPE_S32;
1030 break;
1031 case nir_intrinsic_shared_atomic_umin:
1032 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
1033 break;
1034 case nir_intrinsic_shared_atomic_imax:
1035 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1036 type = TYPE_S32;
1037 break;
1038 case nir_intrinsic_shared_atomic_umax:
1039 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1040 break;
1041 case nir_intrinsic_shared_atomic_and:
1042 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
1043 break;
1044 case nir_intrinsic_shared_atomic_or:
1045 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
1046 break;
1047 case nir_intrinsic_shared_atomic_xor:
1048 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
1049 break;
1050 case nir_intrinsic_shared_atomic_exchange:
1051 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
1052 break;
1053 case nir_intrinsic_shared_atomic_comp_swap:
1054 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1055 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1056 ir3_get_src(ctx, &intr->src[2])[0],
1057 src1,
1058 }, 2);
1059 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
1060 break;
1061 default:
1062 unreachable("boo");
1063 }
1064
1065 atomic->cat6.iim_val = 1;
1066 atomic->cat6.d = 1;
1067 atomic->cat6.type = type;
1068 atomic->barrier_class = IR3_BARRIER_SHARED_W;
1069 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
1070
1071 /* even if nothing consume the result, we can't DCE the instruction: */
1072 array_insert(b, b->keeps, atomic);
1073
1074 return atomic;
1075 }
1076
1077 struct tex_src_info {
1078 /* For prefetch */
1079 unsigned tex_base, samp_base, tex_idx, samp_idx;
1080 /* For normal tex instructions */
1081 unsigned base, combined_idx, a1_val, flags;
1082 struct ir3_instruction *samp_tex;
1083 };
1084
1085 /* TODO handle actual indirect/dynamic case.. which is going to be weird
1086 * to handle with the image_mapping table..
1087 */
1088 static struct tex_src_info
1089 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1090 {
1091 struct ir3_block *b = ctx->block;
1092 struct tex_src_info info = { 0 };
1093 nir_intrinsic_instr *bindless_tex = ir3_bindless_resource(intr->src[0]);
1094 ctx->so->bindless_tex = true;
1095
1096 if (bindless_tex) {
1097 /* Bindless case */
1098 info.flags |= IR3_INSTR_B;
1099
1100 /* Gather information required to determine which encoding to
1101 * choose as well as for prefetch.
1102 */
1103 info.tex_base = nir_intrinsic_desc_set(bindless_tex);
1104 bool tex_const = nir_src_is_const(bindless_tex->src[0]);
1105 if (tex_const)
1106 info.tex_idx = nir_src_as_uint(bindless_tex->src[0]);
1107 info.samp_idx = 0;
1108
1109 /* Choose encoding. */
1110 if (tex_const && info.tex_idx < 256) {
1111 if (info.tex_idx < 16) {
1112 /* Everything fits within the instruction */
1113 info.base = info.tex_base;
1114 info.combined_idx = info.samp_idx | (info.tex_idx << 4);
1115 } else {
1116 info.base = info.tex_base;
1117 info.a1_val = info.tex_idx << 3;
1118 info.combined_idx = 0;
1119 info.flags |= IR3_INSTR_A1EN;
1120 }
1121 info.samp_tex = NULL;
1122 } else {
1123 info.flags |= IR3_INSTR_S2EN;
1124 info.base = info.tex_base;
1125
1126 /* Note: the indirect source is now a vec2 instead of hvec2 */
1127 struct ir3_instruction *texture, *sampler;
1128
1129 texture = ir3_get_src(ctx, &intr->src[0])[0];
1130 sampler = create_immed(b, 0);
1131 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1132 texture,
1133 sampler,
1134 }, 2);
1135 }
1136 } else {
1137 info.flags |= IR3_INSTR_S2EN;
1138 unsigned slot = nir_src_as_uint(intr->src[0]);
1139 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
1140 struct ir3_instruction *texture, *sampler;
1141
1142 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1143 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1144
1145 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1146 sampler,
1147 texture,
1148 }, 2);
1149 }
1150
1151 return info;
1152 }
1153
1154 static struct ir3_instruction *
1155 emit_sam(struct ir3_context *ctx, opc_t opc, struct tex_src_info info,
1156 type_t type, unsigned wrmask, struct ir3_instruction *src0,
1157 struct ir3_instruction *src1)
1158 {
1159 struct ir3_instruction *sam, *addr;
1160 if (info.flags & IR3_INSTR_A1EN) {
1161 addr = ir3_get_addr1(ctx, info.a1_val);
1162 }
1163 sam = ir3_SAM(ctx->block, opc, type, 0b1111, info.flags,
1164 info.samp_tex, src0, src1);
1165 if (info.flags & IR3_INSTR_A1EN) {
1166 ir3_instr_set_address(sam, addr);
1167 }
1168 if (info.flags & IR3_INSTR_B) {
1169 sam->cat5.tex_base = info.base;
1170 sam->cat5.samp = info.combined_idx;
1171 }
1172 return sam;
1173 }
1174
1175 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1176 static void
1177 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1178 struct ir3_instruction **dst)
1179 {
1180 struct ir3_block *b = ctx->block;
1181 struct tex_src_info info = get_image_samp_tex_src(ctx, intr);
1182 struct ir3_instruction *sam;
1183 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
1184 struct ir3_instruction *coords[4];
1185 unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
1186 type_t type = ir3_get_type_for_image_intrinsic(intr);
1187
1188 /* hmm, this seems a bit odd, but it is what blob does and (at least
1189 * a5xx) just faults on bogus addresses otherwise:
1190 */
1191 if (flags & IR3_INSTR_3D) {
1192 flags &= ~IR3_INSTR_3D;
1193 flags |= IR3_INSTR_A;
1194 }
1195 info.flags |= flags;
1196
1197 for (unsigned i = 0; i < ncoords; i++)
1198 coords[i] = src0[i];
1199
1200 if (ncoords == 1)
1201 coords[ncoords++] = create_immed(b, 0);
1202
1203 sam = emit_sam(ctx, OPC_ISAM, info, type, 0b1111,
1204 ir3_create_collect(ctx, coords, ncoords), NULL);
1205
1206 sam->barrier_class = IR3_BARRIER_IMAGE_R;
1207 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
1208
1209 ir3_split_dest(b, dst, sam, 0, 4);
1210 }
1211
1212 static void
1213 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1214 struct ir3_instruction **dst)
1215 {
1216 struct ir3_block *b = ctx->block;
1217 struct tex_src_info info = get_image_samp_tex_src(ctx, intr);
1218 struct ir3_instruction *sam, *lod;
1219 unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
1220 type_t dst_type = nir_dest_bit_size(intr->dest) < 32 ?
1221 TYPE_U16 : TYPE_U32;
1222
1223 info.flags |= flags;
1224 lod = create_immed(b, 0);
1225 sam = emit_sam(ctx, OPC_GETSIZE, info, dst_type, 0b1111, lod, NULL);
1226
1227 /* Array size actually ends up in .w rather than .z. This doesn't
1228 * matter for miplevel 0, but for higher mips the value in z is
1229 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1230 * returned, which means that we have to add 1 to it for arrays for
1231 * a3xx.
1232 *
1233 * Note use a temporary dst and then copy, since the size of the dst
1234 * array that is passed in is based on nir's understanding of the
1235 * result size, not the hardware's
1236 */
1237 struct ir3_instruction *tmp[4];
1238
1239 ir3_split_dest(b, tmp, sam, 0, 4);
1240
1241 /* get_size instruction returns size in bytes instead of texels
1242 * for imageBuffer, so we need to divide it by the pixel size
1243 * of the image format.
1244 *
1245 * TODO: This is at least true on a5xx. Check other gens.
1246 */
1247 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF) {
1248 /* Since all the possible values the divisor can take are
1249 * power-of-two (4, 8, or 16), the division is implemented
1250 * as a shift-right.
1251 * During shader setup, the log2 of the image format's
1252 * bytes-per-pixel should have been emitted in 2nd slot of
1253 * image_dims. See ir3_shader::emit_image_dims().
1254 */
1255 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
1256 unsigned cb = regid(const_state->offsets.image_dims, 0) +
1257 const_state->image_dims.off[nir_src_as_uint(intr->src[0])];
1258 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1259
1260 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1261 }
1262
1263 for (unsigned i = 0; i < ncoords; i++)
1264 dst[i] = tmp[i];
1265
1266 if (flags & IR3_INSTR_A) {
1267 if (ctx->compiler->levels_add_one) {
1268 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1269 } else {
1270 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1271 }
1272 }
1273 }
1274
1275 static void
1276 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1277 {
1278 struct ir3_block *b = ctx->block;
1279 struct ir3_instruction *barrier;
1280
1281 switch (intr->intrinsic) {
1282 case nir_intrinsic_control_barrier:
1283 barrier = ir3_BAR(b);
1284 barrier->cat7.g = true;
1285 barrier->cat7.l = true;
1286 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1287 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1288 break;
1289 case nir_intrinsic_memory_barrier:
1290 barrier = ir3_FENCE(b);
1291 barrier->cat7.g = true;
1292 barrier->cat7.r = true;
1293 barrier->cat7.w = true;
1294 barrier->cat7.l = true;
1295 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1296 IR3_BARRIER_BUFFER_W;
1297 barrier->barrier_conflict =
1298 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1299 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1300 break;
1301 case nir_intrinsic_memory_barrier_buffer:
1302 barrier = ir3_FENCE(b);
1303 barrier->cat7.g = true;
1304 barrier->cat7.r = true;
1305 barrier->cat7.w = true;
1306 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1307 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1308 IR3_BARRIER_BUFFER_W;
1309 break;
1310 case nir_intrinsic_memory_barrier_image:
1311 // TODO double check if this should have .g set
1312 barrier = ir3_FENCE(b);
1313 barrier->cat7.g = true;
1314 barrier->cat7.r = true;
1315 barrier->cat7.w = true;
1316 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1317 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1318 IR3_BARRIER_IMAGE_W;
1319 break;
1320 case nir_intrinsic_memory_barrier_shared:
1321 barrier = ir3_FENCE(b);
1322 barrier->cat7.g = true;
1323 barrier->cat7.l = true;
1324 barrier->cat7.r = true;
1325 barrier->cat7.w = true;
1326 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1327 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1328 IR3_BARRIER_SHARED_W;
1329 break;
1330 case nir_intrinsic_group_memory_barrier:
1331 barrier = ir3_FENCE(b);
1332 barrier->cat7.g = true;
1333 barrier->cat7.l = true;
1334 barrier->cat7.r = true;
1335 barrier->cat7.w = true;
1336 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1337 IR3_BARRIER_IMAGE_W |
1338 IR3_BARRIER_BUFFER_W;
1339 barrier->barrier_conflict =
1340 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1341 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1342 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1343 break;
1344 default:
1345 unreachable("boo");
1346 }
1347
1348 /* make sure barrier doesn't get DCE'd */
1349 array_insert(b, b->keeps, barrier);
1350 }
1351
1352 static void add_sysval_input_compmask(struct ir3_context *ctx,
1353 gl_system_value slot, unsigned compmask,
1354 struct ir3_instruction *instr)
1355 {
1356 struct ir3_shader_variant *so = ctx->so;
1357 unsigned n = so->inputs_count++;
1358
1359 assert(instr->opc == OPC_META_INPUT);
1360 instr->input.inidx = n;
1361 instr->input.sysval = slot;
1362
1363 so->inputs[n].sysval = true;
1364 so->inputs[n].slot = slot;
1365 so->inputs[n].compmask = compmask;
1366 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1367 so->total_in++;
1368 }
1369
1370 static struct ir3_instruction *
1371 create_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1372 unsigned compmask)
1373 {
1374 assert(compmask);
1375 struct ir3_instruction *sysval = create_input(ctx, compmask);
1376 add_sysval_input_compmask(ctx, slot, compmask, sysval);
1377 return sysval;
1378 }
1379
1380 static struct ir3_instruction *
1381 get_barycentric_centroid(struct ir3_context *ctx)
1382 {
1383 if (!ctx->ij_centroid) {
1384 struct ir3_instruction *xy[2];
1385 struct ir3_instruction *ij;
1386
1387 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID, 0x3);
1388 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1389
1390 ctx->ij_centroid = ir3_create_collect(ctx, xy, 2);
1391 }
1392
1393 return ctx->ij_centroid;
1394 }
1395
1396 static struct ir3_instruction *
1397 get_barycentric_sample(struct ir3_context *ctx)
1398 {
1399 if (!ctx->ij_sample) {
1400 struct ir3_instruction *xy[2];
1401 struct ir3_instruction *ij;
1402
1403 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE, 0x3);
1404 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1405
1406 ctx->ij_sample = ir3_create_collect(ctx, xy, 2);
1407 }
1408
1409 return ctx->ij_sample;
1410 }
1411
1412 static struct ir3_instruction *
1413 get_barycentric_pixel(struct ir3_context *ctx)
1414 {
1415 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1416 * this to create ij_pixel only on demand:
1417 */
1418 return ctx->ij_pixel;
1419 }
1420
1421 static struct ir3_instruction *
1422 get_frag_coord(struct ir3_context *ctx)
1423 {
1424 if (!ctx->frag_coord) {
1425 struct ir3_block *b = ctx->in_block;
1426 struct ir3_instruction *xyzw[4];
1427 struct ir3_instruction *hw_frag_coord;
1428
1429 hw_frag_coord = create_sysval_input(ctx, SYSTEM_VALUE_FRAG_COORD, 0xf);
1430 ir3_split_dest(b, xyzw, hw_frag_coord, 0, 4);
1431
1432 /* for frag_coord.xy, we get unsigned values.. we need
1433 * to subtract (integer) 8 and divide by 16 (right-
1434 * shift by 4) then convert to float:
1435 *
1436 * sub.s tmp, src, 8
1437 * shr.b tmp, tmp, 4
1438 * mov.u32f32 dst, tmp
1439 *
1440 */
1441 for (int i = 0; i < 2; i++) {
1442 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1443 xyzw[i] = ir3_MUL_F(b, xyzw[i], 0, create_immed(b, fui(1.0 / 16.0)), 0);
1444 }
1445
1446 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1447 ctx->so->frag_coord = true;
1448 }
1449
1450 return ctx->frag_coord;
1451 }
1452
1453 static void
1454 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1455 {
1456 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1457 struct ir3_instruction **dst;
1458 struct ir3_instruction * const *src;
1459 struct ir3_block *b = ctx->block;
1460 int idx, comp;
1461
1462 if (info->has_dest) {
1463 unsigned n = nir_intrinsic_dest_components(intr);
1464 dst = ir3_get_dst(ctx, &intr->dest, n);
1465 } else {
1466 dst = NULL;
1467 }
1468
1469 const unsigned primitive_param = ctx->so->shader->const_state.offsets.primitive_param * 4;
1470 const unsigned primitive_map = ctx->so->shader->const_state.offsets.primitive_map * 4;
1471
1472 switch (intr->intrinsic) {
1473 case nir_intrinsic_load_uniform:
1474 idx = nir_intrinsic_base(intr);
1475 if (nir_src_is_const(intr->src[0])) {
1476 idx += nir_src_as_uint(intr->src[0]);
1477 for (int i = 0; i < intr->num_components; i++) {
1478 dst[i] = create_uniform_typed(b, idx + i,
1479 nir_dest_bit_size(intr->dest) < 32 ? TYPE_F16 : TYPE_F32);
1480 }
1481 } else {
1482 src = ir3_get_src(ctx, &intr->src[0]);
1483 for (int i = 0; i < intr->num_components; i++) {
1484 dst[i] = create_uniform_indirect(b, idx + i,
1485 ir3_get_addr0(ctx, src[0], 1));
1486 }
1487 /* NOTE: if relative addressing is used, we set
1488 * constlen in the compiler (to worst-case value)
1489 * since we don't know in the assembler what the max
1490 * addr reg value can be:
1491 */
1492 ctx->so->constlen = MAX2(ctx->so->constlen,
1493 ctx->so->shader->ubo_state.size / 16);
1494 }
1495 break;
1496
1497 case nir_intrinsic_load_vs_primitive_stride_ir3:
1498 dst[0] = create_uniform(b, primitive_param + 0);
1499 break;
1500 case nir_intrinsic_load_vs_vertex_stride_ir3:
1501 dst[0] = create_uniform(b, primitive_param + 1);
1502 break;
1503 case nir_intrinsic_load_hs_patch_stride_ir3:
1504 dst[0] = create_uniform(b, primitive_param + 2);
1505 break;
1506 case nir_intrinsic_load_patch_vertices_in:
1507 dst[0] = create_uniform(b, primitive_param + 3);
1508 break;
1509 case nir_intrinsic_load_tess_param_base_ir3:
1510 dst[0] = create_uniform(b, primitive_param + 4);
1511 dst[1] = create_uniform(b, primitive_param + 5);
1512 break;
1513 case nir_intrinsic_load_tess_factor_base_ir3:
1514 dst[0] = create_uniform(b, primitive_param + 6);
1515 dst[1] = create_uniform(b, primitive_param + 7);
1516 break;
1517
1518 case nir_intrinsic_load_primitive_location_ir3:
1519 idx = nir_intrinsic_driver_location(intr);
1520 dst[0] = create_uniform(b, primitive_map + idx);
1521 break;
1522
1523 case nir_intrinsic_load_gs_header_ir3:
1524 dst[0] = ctx->gs_header;
1525 break;
1526 case nir_intrinsic_load_tcs_header_ir3:
1527 dst[0] = ctx->tcs_header;
1528 break;
1529
1530 case nir_intrinsic_load_primitive_id:
1531 dst[0] = ctx->primitive_id;
1532 break;
1533
1534 case nir_intrinsic_load_tess_coord:
1535 if (!ctx->tess_coord) {
1536 ctx->tess_coord =
1537 create_sysval_input(ctx, SYSTEM_VALUE_TESS_COORD, 0x3);
1538 }
1539 ir3_split_dest(b, dst, ctx->tess_coord, 0, 2);
1540
1541 /* Unused, but ir3_put_dst() below wants to free something */
1542 dst[2] = create_immed(b, 0);
1543 break;
1544
1545 case nir_intrinsic_end_patch_ir3:
1546 assert(ctx->so->type == MESA_SHADER_TESS_CTRL);
1547 struct ir3_instruction *end = ir3_ENDIF(b);
1548 array_insert(b, b->keeps, end);
1549
1550 end->barrier_class = IR3_BARRIER_EVERYTHING;
1551 end->barrier_conflict = IR3_BARRIER_EVERYTHING;
1552 break;
1553
1554 case nir_intrinsic_store_global_ir3: {
1555 struct ir3_instruction *value, *addr, *offset;
1556
1557 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1558 ir3_get_src(ctx, &intr->src[1])[0],
1559 ir3_get_src(ctx, &intr->src[1])[1]
1560 }, 2);
1561
1562 offset = ir3_get_src(ctx, &intr->src[2])[0];
1563
1564 value = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]),
1565 intr->num_components);
1566
1567 struct ir3_instruction *stg =
1568 ir3_STG_G(ctx->block, addr, 0, value, 0,
1569 create_immed(ctx->block, intr->num_components), 0, offset, 0);
1570 stg->cat6.type = TYPE_U32;
1571 stg->cat6.iim_val = 1;
1572
1573 array_insert(b, b->keeps, stg);
1574
1575 stg->barrier_class = IR3_BARRIER_BUFFER_W;
1576 stg->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1577 break;
1578 }
1579
1580 case nir_intrinsic_load_global_ir3: {
1581 struct ir3_instruction *addr, *offset;
1582
1583 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1584 ir3_get_src(ctx, &intr->src[0])[0],
1585 ir3_get_src(ctx, &intr->src[0])[1]
1586 }, 2);
1587
1588 offset = ir3_get_src(ctx, &intr->src[1])[0];
1589
1590 struct ir3_instruction *load =
1591 ir3_LDG(b, addr, 0, create_immed(ctx->block, intr->num_components),
1592 0, offset, 0);
1593 load->cat6.type = TYPE_U32;
1594 load->regs[0]->wrmask = MASK(intr->num_components);
1595
1596 load->barrier_class = IR3_BARRIER_BUFFER_R;
1597 load->barrier_conflict = IR3_BARRIER_BUFFER_W;
1598
1599 ir3_split_dest(b, dst, load, 0, intr->num_components);
1600 break;
1601 }
1602
1603 case nir_intrinsic_load_ubo:
1604 emit_intrinsic_load_ubo(ctx, intr, dst);
1605 break;
1606 case nir_intrinsic_load_frag_coord:
1607 ir3_split_dest(b, dst, get_frag_coord(ctx), 0, 4);
1608 break;
1609 case nir_intrinsic_load_sample_pos_from_id: {
1610 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1611 * but that doesn't seem necessary.
1612 */
1613 struct ir3_instruction *offset =
1614 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1615 offset->regs[0]->wrmask = 0x3;
1616 offset->cat5.type = TYPE_F32;
1617
1618 ir3_split_dest(b, dst, offset, 0, 2);
1619
1620 break;
1621 }
1622 case nir_intrinsic_load_size_ir3:
1623 if (!ctx->ij_size) {
1624 ctx->ij_size =
1625 create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE, 0x1);
1626 }
1627 dst[0] = ctx->ij_size;
1628 break;
1629 case nir_intrinsic_load_barycentric_centroid:
1630 ir3_split_dest(b, dst, get_barycentric_centroid(ctx), 0, 2);
1631 break;
1632 case nir_intrinsic_load_barycentric_sample:
1633 if (ctx->so->key.msaa) {
1634 ir3_split_dest(b, dst, get_barycentric_sample(ctx), 0, 2);
1635 } else {
1636 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1637 }
1638 break;
1639 case nir_intrinsic_load_barycentric_pixel:
1640 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1641 break;
1642 case nir_intrinsic_load_interpolated_input:
1643 idx = nir_intrinsic_base(intr);
1644 comp = nir_intrinsic_component(intr);
1645 src = ir3_get_src(ctx, &intr->src[0]);
1646 if (nir_src_is_const(intr->src[1])) {
1647 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1648 idx += nir_src_as_uint(intr->src[1]);
1649 for (int i = 0; i < intr->num_components; i++) {
1650 unsigned inloc = idx * 4 + i + comp;
1651 if (ctx->so->inputs[idx].bary &&
1652 !ctx->so->inputs[idx].use_ldlv) {
1653 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1654 } else {
1655 /* for non-varyings use the pre-setup input, since
1656 * that is easier than mapping things back to a
1657 * nir_variable to figure out what it is.
1658 */
1659 dst[i] = ctx->inputs[inloc];
1660 compile_assert(ctx, dst[i]);
1661 }
1662 }
1663 } else {
1664 ir3_context_error(ctx, "unhandled");
1665 }
1666 break;
1667 case nir_intrinsic_load_input:
1668 idx = nir_intrinsic_base(intr);
1669 comp = nir_intrinsic_component(intr);
1670 if (nir_src_is_const(intr->src[0])) {
1671 idx += nir_src_as_uint(intr->src[0]);
1672 for (int i = 0; i < intr->num_components; i++) {
1673 unsigned n = idx * 4 + i + comp;
1674 dst[i] = ctx->inputs[n];
1675 compile_assert(ctx, ctx->inputs[n]);
1676 }
1677 } else {
1678 src = ir3_get_src(ctx, &intr->src[0]);
1679 struct ir3_instruction *collect =
1680 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ninputs);
1681 struct ir3_instruction *addr = ir3_get_addr0(ctx, src[0], 4);
1682 for (int i = 0; i < intr->num_components; i++) {
1683 unsigned n = idx * 4 + i + comp;
1684 dst[i] = create_indirect_load(ctx, ctx->ninputs,
1685 n, addr, collect);
1686 }
1687 }
1688 break;
1689 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1690 * pass and replaced by an ir3-specifc version that adds the
1691 * dword-offset in the last source.
1692 */
1693 case nir_intrinsic_load_ssbo_ir3:
1694 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1695 break;
1696 case nir_intrinsic_store_ssbo_ir3:
1697 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1698 !ctx->s->info.fs.early_fragment_tests)
1699 ctx->so->no_earlyz = true;
1700 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1701 break;
1702 case nir_intrinsic_get_buffer_size:
1703 emit_intrinsic_ssbo_size(ctx, intr, dst);
1704 break;
1705 case nir_intrinsic_ssbo_atomic_add_ir3:
1706 case nir_intrinsic_ssbo_atomic_imin_ir3:
1707 case nir_intrinsic_ssbo_atomic_umin_ir3:
1708 case nir_intrinsic_ssbo_atomic_imax_ir3:
1709 case nir_intrinsic_ssbo_atomic_umax_ir3:
1710 case nir_intrinsic_ssbo_atomic_and_ir3:
1711 case nir_intrinsic_ssbo_atomic_or_ir3:
1712 case nir_intrinsic_ssbo_atomic_xor_ir3:
1713 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1714 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1715 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1716 !ctx->s->info.fs.early_fragment_tests)
1717 ctx->so->no_earlyz = true;
1718 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1719 break;
1720 case nir_intrinsic_load_shared:
1721 emit_intrinsic_load_shared(ctx, intr, dst);
1722 break;
1723 case nir_intrinsic_store_shared:
1724 emit_intrinsic_store_shared(ctx, intr);
1725 break;
1726 case nir_intrinsic_shared_atomic_add:
1727 case nir_intrinsic_shared_atomic_imin:
1728 case nir_intrinsic_shared_atomic_umin:
1729 case nir_intrinsic_shared_atomic_imax:
1730 case nir_intrinsic_shared_atomic_umax:
1731 case nir_intrinsic_shared_atomic_and:
1732 case nir_intrinsic_shared_atomic_or:
1733 case nir_intrinsic_shared_atomic_xor:
1734 case nir_intrinsic_shared_atomic_exchange:
1735 case nir_intrinsic_shared_atomic_comp_swap:
1736 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1737 break;
1738 case nir_intrinsic_image_load:
1739 emit_intrinsic_load_image(ctx, intr, dst);
1740 break;
1741 case nir_intrinsic_bindless_image_load:
1742 /* Bindless uses the IBO state, which doesn't have swizzle filled out,
1743 * so using isam doesn't work.
1744 *
1745 * TODO: can we use isam if we fill out more fields?
1746 */
1747 ctx->funcs->emit_intrinsic_load_image(ctx, intr, dst);
1748 break;
1749 case nir_intrinsic_image_store:
1750 case nir_intrinsic_bindless_image_store:
1751 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1752 !ctx->s->info.fs.early_fragment_tests)
1753 ctx->so->no_earlyz = true;
1754 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1755 break;
1756 case nir_intrinsic_image_size:
1757 case nir_intrinsic_bindless_image_size:
1758 emit_intrinsic_image_size(ctx, intr, dst);
1759 break;
1760 case nir_intrinsic_image_atomic_add:
1761 case nir_intrinsic_bindless_image_atomic_add:
1762 case nir_intrinsic_image_atomic_imin:
1763 case nir_intrinsic_bindless_image_atomic_imin:
1764 case nir_intrinsic_image_atomic_umin:
1765 case nir_intrinsic_bindless_image_atomic_umin:
1766 case nir_intrinsic_image_atomic_imax:
1767 case nir_intrinsic_bindless_image_atomic_imax:
1768 case nir_intrinsic_image_atomic_umax:
1769 case nir_intrinsic_bindless_image_atomic_umax:
1770 case nir_intrinsic_image_atomic_and:
1771 case nir_intrinsic_bindless_image_atomic_and:
1772 case nir_intrinsic_image_atomic_or:
1773 case nir_intrinsic_bindless_image_atomic_or:
1774 case nir_intrinsic_image_atomic_xor:
1775 case nir_intrinsic_bindless_image_atomic_xor:
1776 case nir_intrinsic_image_atomic_exchange:
1777 case nir_intrinsic_bindless_image_atomic_exchange:
1778 case nir_intrinsic_image_atomic_comp_swap:
1779 case nir_intrinsic_bindless_image_atomic_comp_swap:
1780 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1781 !ctx->s->info.fs.early_fragment_tests)
1782 ctx->so->no_earlyz = true;
1783 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1784 break;
1785 case nir_intrinsic_control_barrier:
1786 case nir_intrinsic_memory_barrier:
1787 case nir_intrinsic_group_memory_barrier:
1788 case nir_intrinsic_memory_barrier_buffer:
1789 case nir_intrinsic_memory_barrier_image:
1790 case nir_intrinsic_memory_barrier_shared:
1791 emit_intrinsic_barrier(ctx, intr);
1792 /* note that blk ptr no longer valid, make that obvious: */
1793 b = NULL;
1794 break;
1795 case nir_intrinsic_store_output:
1796 idx = nir_intrinsic_base(intr);
1797 comp = nir_intrinsic_component(intr);
1798 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1799 idx += nir_src_as_uint(intr->src[1]);
1800
1801 src = ir3_get_src(ctx, &intr->src[0]);
1802 for (int i = 0; i < intr->num_components; i++) {
1803 unsigned n = idx * 4 + i + comp;
1804 ctx->outputs[n] = src[i];
1805 }
1806 break;
1807 case nir_intrinsic_load_base_vertex:
1808 case nir_intrinsic_load_first_vertex:
1809 if (!ctx->basevertex) {
1810 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1811 }
1812 dst[0] = ctx->basevertex;
1813 break;
1814 case nir_intrinsic_load_base_instance:
1815 if (!ctx->base_instance) {
1816 ctx->base_instance = create_driver_param(ctx, IR3_DP_INSTID_BASE);
1817 }
1818 dst[0] = ctx->base_instance;
1819 break;
1820 case nir_intrinsic_load_vertex_id_zero_base:
1821 case nir_intrinsic_load_vertex_id:
1822 if (!ctx->vertex_id) {
1823 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1824 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1825 ctx->vertex_id = create_sysval_input(ctx, sv, 0x1);
1826 }
1827 dst[0] = ctx->vertex_id;
1828 break;
1829 case nir_intrinsic_load_instance_id:
1830 if (!ctx->instance_id) {
1831 ctx->instance_id = create_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID, 0x1);
1832 }
1833 dst[0] = ctx->instance_id;
1834 break;
1835 case nir_intrinsic_load_sample_id:
1836 ctx->so->per_samp = true;
1837 /* fall-thru */
1838 case nir_intrinsic_load_sample_id_no_per_sample:
1839 if (!ctx->samp_id) {
1840 ctx->samp_id = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID, 0x1);
1841 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1842 }
1843 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1844 break;
1845 case nir_intrinsic_load_sample_mask_in:
1846 if (!ctx->samp_mask_in) {
1847 ctx->samp_mask_in = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN, 0x1);
1848 }
1849 dst[0] = ctx->samp_mask_in;
1850 break;
1851 case nir_intrinsic_load_user_clip_plane:
1852 idx = nir_intrinsic_ucp_id(intr);
1853 for (int i = 0; i < intr->num_components; i++) {
1854 unsigned n = idx * 4 + i;
1855 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1856 }
1857 break;
1858 case nir_intrinsic_load_front_face:
1859 if (!ctx->frag_face) {
1860 ctx->so->frag_face = true;
1861 ctx->frag_face = create_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, 0x1);
1862 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1863 }
1864 /* for fragface, we get -1 for back and 0 for front. However this is
1865 * the inverse of what nir expects (where ~0 is true).
1866 */
1867 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1868 dst[0] = ir3_NOT_B(b, dst[0], 0);
1869 break;
1870 case nir_intrinsic_load_local_invocation_id:
1871 if (!ctx->local_invocation_id) {
1872 ctx->local_invocation_id =
1873 create_sysval_input(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID, 0x7);
1874 }
1875 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1876 break;
1877 case nir_intrinsic_load_work_group_id:
1878 if (!ctx->work_group_id) {
1879 ctx->work_group_id =
1880 create_sysval_input(ctx, SYSTEM_VALUE_WORK_GROUP_ID, 0x7);
1881 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1882 }
1883 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1884 break;
1885 case nir_intrinsic_load_num_work_groups:
1886 for (int i = 0; i < intr->num_components; i++) {
1887 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1888 }
1889 break;
1890 case nir_intrinsic_load_local_group_size:
1891 for (int i = 0; i < intr->num_components; i++) {
1892 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1893 }
1894 break;
1895 case nir_intrinsic_discard_if:
1896 case nir_intrinsic_discard: {
1897 struct ir3_instruction *cond, *kill;
1898
1899 if (intr->intrinsic == nir_intrinsic_discard_if) {
1900 /* conditional discard: */
1901 src = ir3_get_src(ctx, &intr->src[0]);
1902 cond = ir3_b2n(b, src[0]);
1903 } else {
1904 /* unconditional discard: */
1905 cond = create_immed(b, 1);
1906 }
1907
1908 /* NOTE: only cmps.*.* can write p0.x: */
1909 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1910 cond->cat2.condition = IR3_COND_NE;
1911
1912 /* condition always goes in predicate register: */
1913 cond->regs[0]->num = regid(REG_P0, 0);
1914 cond->regs[0]->flags &= ~IR3_REG_SSA;
1915
1916 kill = ir3_KILL(b, cond, 0);
1917 kill->regs[1]->num = regid(REG_P0, 0);
1918 array_insert(ctx->ir, ctx->ir->predicates, kill);
1919
1920 array_insert(b, b->keeps, kill);
1921 ctx->so->no_earlyz = true;
1922
1923 break;
1924 }
1925
1926 case nir_intrinsic_cond_end_ir3: {
1927 struct ir3_instruction *cond, *kill;
1928
1929 src = ir3_get_src(ctx, &intr->src[0]);
1930 cond = ir3_b2n(b, src[0]);
1931
1932 /* NOTE: only cmps.*.* can write p0.x: */
1933 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1934 cond->cat2.condition = IR3_COND_NE;
1935
1936 /* condition always goes in predicate register: */
1937 cond->regs[0]->num = regid(REG_P0, 0);
1938
1939 kill = ir3_IF(b, cond, 0);
1940
1941 kill->barrier_class = IR3_BARRIER_EVERYTHING;
1942 kill->barrier_conflict = IR3_BARRIER_EVERYTHING;
1943
1944 array_insert(ctx->ir, ctx->ir->predicates, kill);
1945 array_insert(b, b->keeps, kill);
1946 break;
1947 }
1948
1949 case nir_intrinsic_load_shared_ir3:
1950 emit_intrinsic_load_shared_ir3(ctx, intr, dst);
1951 break;
1952 case nir_intrinsic_store_shared_ir3:
1953 emit_intrinsic_store_shared_ir3(ctx, intr);
1954 break;
1955 case nir_intrinsic_bindless_resource_ir3:
1956 dst[0] = ir3_get_src(ctx, &intr->src[0])[0];
1957 break;
1958 default:
1959 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1960 nir_intrinsic_infos[intr->intrinsic].name);
1961 break;
1962 }
1963
1964 if (info->has_dest)
1965 ir3_put_dst(ctx, &intr->dest);
1966 }
1967
1968 static void
1969 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1970 {
1971 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1972 instr->def.num_components);
1973
1974 if (instr->def.bit_size < 32) {
1975 for (int i = 0; i < instr->def.num_components; i++)
1976 dst[i] = create_immed_typed(ctx->block,
1977 instr->value[i].u16,
1978 TYPE_U16);
1979 } else {
1980 for (int i = 0; i < instr->def.num_components; i++)
1981 dst[i] = create_immed_typed(ctx->block,
1982 instr->value[i].u32,
1983 TYPE_U32);
1984 }
1985
1986 }
1987
1988 static void
1989 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1990 {
1991 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1992 undef->def.num_components);
1993 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1994
1995 /* backend doesn't want undefined instructions, so just plug
1996 * in 0.0..
1997 */
1998 for (int i = 0; i < undef->def.num_components; i++)
1999 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
2000 }
2001
2002 /*
2003 * texture fetch/sample instructions:
2004 */
2005
2006 static type_t
2007 get_tex_dest_type(nir_tex_instr *tex)
2008 {
2009 type_t type;
2010
2011 switch (nir_alu_type_get_base_type(tex->dest_type)) {
2012 case nir_type_invalid:
2013 case nir_type_float:
2014 type = nir_dest_bit_size(tex->dest) < 32 ? TYPE_F16 : TYPE_F32;
2015 break;
2016 case nir_type_int:
2017 type = nir_dest_bit_size(tex->dest) < 32 ? TYPE_S16 : TYPE_S32;
2018 break;
2019 case nir_type_uint:
2020 case nir_type_bool:
2021 type = nir_dest_bit_size(tex->dest) < 32 ? TYPE_U16 : TYPE_U32;
2022 break;
2023 default:
2024 unreachable("bad dest_type");
2025 }
2026
2027 return type;
2028 }
2029
2030 static void
2031 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
2032 {
2033 unsigned coords = glsl_get_sampler_dim_coordinate_components(tex->sampler_dim);
2034 unsigned flags = 0;
2035
2036 /* note: would use tex->coord_components.. except txs.. also,
2037 * since array index goes after shadow ref, we don't want to
2038 * count it:
2039 */
2040 if (coords == 3)
2041 flags |= IR3_INSTR_3D;
2042
2043 if (tex->is_shadow && tex->op != nir_texop_lod)
2044 flags |= IR3_INSTR_S;
2045
2046 if (tex->is_array && tex->op != nir_texop_lod)
2047 flags |= IR3_INSTR_A;
2048
2049 *flagsp = flags;
2050 *coordsp = coords;
2051 }
2052
2053 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
2054 * or immediate (in which case it will get lowered later to a non .s2en
2055 * version of the tex instruction which encode tex/samp as immediates:
2056 */
2057 static struct tex_src_info
2058 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
2059 {
2060 struct ir3_block *b = ctx->block;
2061 struct tex_src_info info = { 0 };
2062 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_handle);
2063 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_handle);
2064 struct ir3_instruction *texture, *sampler;
2065
2066 if (texture_idx >= 0 || sampler_idx >= 0) {
2067 /* Bindless case */
2068 info.flags |= IR3_INSTR_B;
2069
2070 /* Gather information required to determine which encoding to
2071 * choose as well as for prefetch.
2072 */
2073 nir_intrinsic_instr *bindless_tex = NULL;
2074 bool tex_const;
2075 if (texture_idx >= 0) {
2076 ctx->so->bindless_tex = true;
2077 bindless_tex = ir3_bindless_resource(tex->src[texture_idx].src);
2078 assert(bindless_tex);
2079 info.tex_base = nir_intrinsic_desc_set(bindless_tex);
2080 tex_const = nir_src_is_const(bindless_tex->src[0]);
2081 if (tex_const)
2082 info.tex_idx = nir_src_as_uint(bindless_tex->src[0]);
2083 } else {
2084 /* To simplify some of the logic below, assume the index is
2085 * constant 0 when it's not enabled.
2086 */
2087 tex_const = true;
2088 info.tex_idx = 0;
2089 }
2090 nir_intrinsic_instr *bindless_samp = NULL;
2091 bool samp_const;
2092 if (sampler_idx >= 0) {
2093 ctx->so->bindless_samp = true;
2094 bindless_samp = ir3_bindless_resource(tex->src[sampler_idx].src);
2095 assert(bindless_samp);
2096 info.samp_base = nir_intrinsic_desc_set(bindless_samp);
2097 samp_const = nir_src_is_const(bindless_samp->src[0]);
2098 if (samp_const)
2099 info.samp_idx = nir_src_as_uint(bindless_samp->src[0]);
2100 } else {
2101 samp_const = true;
2102 info.samp_idx = 0;
2103 }
2104
2105 /* Choose encoding. */
2106 if (tex_const && samp_const && info.tex_idx < 256 && info.samp_idx < 256) {
2107 if (info.tex_idx < 16 && info.samp_idx < 16 &&
2108 (!bindless_tex || !bindless_samp || info.tex_base == info.samp_base)) {
2109 /* Everything fits within the instruction */
2110 info.base = info.tex_base;
2111 info.combined_idx = info.samp_idx | (info.tex_idx << 4);
2112 } else {
2113 info.base = info.tex_base;
2114 info.a1_val = info.tex_idx << 3 | info.samp_base;
2115 info.combined_idx = info.samp_idx;
2116 info.flags |= IR3_INSTR_A1EN;
2117 }
2118 info.samp_tex = NULL;
2119 } else {
2120 info.flags |= IR3_INSTR_S2EN;
2121 /* In the indirect case, we only use a1.x to store the sampler
2122 * base if it differs from the texture base.
2123 */
2124 if (!bindless_tex || !bindless_samp || info.tex_base == info.samp_base) {
2125 info.base = info.tex_base;
2126 } else {
2127 info.base = info.tex_base;
2128 info.a1_val = info.samp_base;
2129 info.flags |= IR3_INSTR_A1EN;
2130 }
2131
2132 /* Note: the indirect source is now a vec2 instead of hvec2, and
2133 * for some reason the texture and sampler are swapped.
2134 */
2135 struct ir3_instruction *texture, *sampler;
2136
2137 if (bindless_tex) {
2138 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
2139 } else {
2140 texture = create_immed(b, 0);
2141 }
2142
2143 if (bindless_samp) {
2144 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
2145 } else {
2146 sampler = create_immed(b, 0);
2147 }
2148 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2149 texture,
2150 sampler,
2151 }, 2);
2152 }
2153 } else {
2154 info.flags |= IR3_INSTR_S2EN;
2155 texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
2156 sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
2157 if (texture_idx >= 0) {
2158 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
2159 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
2160 } else {
2161 /* TODO what to do for dynamic case? I guess we only need the
2162 * max index for astc srgb workaround so maybe not a problem
2163 * to worry about if we don't enable indirect samplers for
2164 * a4xx?
2165 */
2166 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
2167 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
2168 info.tex_idx = tex->texture_index;
2169 }
2170
2171 if (sampler_idx >= 0) {
2172 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
2173 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
2174 } else {
2175 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
2176 info.samp_idx = tex->texture_index;
2177 }
2178
2179 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2180 sampler,
2181 texture,
2182 }, 2);
2183 }
2184
2185 return info;
2186 }
2187
2188 static void
2189 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
2190 {
2191 struct ir3_block *b = ctx->block;
2192 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
2193 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
2194 struct ir3_instruction *lod, *compare, *proj, *sample_index;
2195 struct tex_src_info info = { 0 };
2196 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
2197 unsigned i, coords, flags, ncomp;
2198 unsigned nsrc0 = 0, nsrc1 = 0;
2199 type_t type;
2200 opc_t opc = 0;
2201
2202 ncomp = nir_dest_num_components(tex->dest);
2203
2204 coord = off = ddx = ddy = NULL;
2205 lod = proj = compare = sample_index = NULL;
2206
2207 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
2208
2209 for (unsigned i = 0; i < tex->num_srcs; i++) {
2210 switch (tex->src[i].src_type) {
2211 case nir_tex_src_coord:
2212 coord = ir3_get_src(ctx, &tex->src[i].src);
2213 break;
2214 case nir_tex_src_bias:
2215 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
2216 has_bias = true;
2217 break;
2218 case nir_tex_src_lod:
2219 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
2220 has_lod = true;
2221 break;
2222 case nir_tex_src_comparator: /* shadow comparator */
2223 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
2224 break;
2225 case nir_tex_src_projector:
2226 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
2227 has_proj = true;
2228 break;
2229 case nir_tex_src_offset:
2230 off = ir3_get_src(ctx, &tex->src[i].src);
2231 has_off = true;
2232 break;
2233 case nir_tex_src_ddx:
2234 ddx = ir3_get_src(ctx, &tex->src[i].src);
2235 break;
2236 case nir_tex_src_ddy:
2237 ddy = ir3_get_src(ctx, &tex->src[i].src);
2238 break;
2239 case nir_tex_src_ms_index:
2240 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
2241 break;
2242 case nir_tex_src_texture_offset:
2243 case nir_tex_src_sampler_offset:
2244 case nir_tex_src_texture_handle:
2245 case nir_tex_src_sampler_handle:
2246 /* handled in get_tex_samp_src() */
2247 break;
2248 default:
2249 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
2250 tex->src[i].src_type);
2251 return;
2252 }
2253 }
2254
2255 switch (tex->op) {
2256 case nir_texop_tex_prefetch:
2257 compile_assert(ctx, !has_bias);
2258 compile_assert(ctx, !has_lod);
2259 compile_assert(ctx, !compare);
2260 compile_assert(ctx, !has_proj);
2261 compile_assert(ctx, !has_off);
2262 compile_assert(ctx, !ddx);
2263 compile_assert(ctx, !ddy);
2264 compile_assert(ctx, !sample_index);
2265 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_texture_offset) < 0);
2266 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset) < 0);
2267
2268 if (ctx->so->num_sampler_prefetch < IR3_MAX_SAMPLER_PREFETCH) {
2269 opc = OPC_META_TEX_PREFETCH;
2270 ctx->so->num_sampler_prefetch++;
2271 break;
2272 }
2273 /* fallthru */
2274 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
2275 case nir_texop_txb: opc = OPC_SAMB; break;
2276 case nir_texop_txl: opc = OPC_SAML; break;
2277 case nir_texop_txd: opc = OPC_SAMGQ; break;
2278 case nir_texop_txf: opc = OPC_ISAML; break;
2279 case nir_texop_lod: opc = OPC_GETLOD; break;
2280 case nir_texop_tg4:
2281 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2282 * what blob does, seems gather is broken?), and a3xx did
2283 * not support it (but probably could also emulate).
2284 */
2285 switch (tex->component) {
2286 case 0: opc = OPC_GATHER4R; break;
2287 case 1: opc = OPC_GATHER4G; break;
2288 case 2: opc = OPC_GATHER4B; break;
2289 case 3: opc = OPC_GATHER4A; break;
2290 }
2291 break;
2292 case nir_texop_txf_ms_fb:
2293 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
2294 default:
2295 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
2296 return;
2297 }
2298
2299 tex_info(tex, &flags, &coords);
2300
2301 /*
2302 * lay out the first argument in the proper order:
2303 * - actual coordinates first
2304 * - shadow reference
2305 * - array index
2306 * - projection w
2307 * - starting at offset 4, dpdx.xy, dpdy.xy
2308 *
2309 * bias/lod go into the second arg
2310 */
2311
2312 /* insert tex coords: */
2313 for (i = 0; i < coords; i++)
2314 src0[i] = coord[i];
2315
2316 nsrc0 = i;
2317
2318 /* scale up integer coords for TXF based on the LOD */
2319 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
2320 assert(has_lod);
2321 for (i = 0; i < coords; i++)
2322 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
2323 }
2324
2325 if (coords == 1) {
2326 /* hw doesn't do 1d, so we treat it as 2d with
2327 * height of 1, and patch up the y coord.
2328 */
2329 if (is_isam(opc)) {
2330 src0[nsrc0++] = create_immed(b, 0);
2331 } else {
2332 src0[nsrc0++] = create_immed(b, fui(0.5));
2333 }
2334 }
2335
2336 if (tex->is_shadow && tex->op != nir_texop_lod)
2337 src0[nsrc0++] = compare;
2338
2339 if (tex->is_array && tex->op != nir_texop_lod) {
2340 struct ir3_instruction *idx = coord[coords];
2341
2342 /* the array coord for cube arrays needs 0.5 added to it */
2343 if (ctx->compiler->array_index_add_half && !is_isam(opc))
2344 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
2345
2346 src0[nsrc0++] = idx;
2347 }
2348
2349 if (has_proj) {
2350 src0[nsrc0++] = proj;
2351 flags |= IR3_INSTR_P;
2352 }
2353
2354 /* pad to 4, then ddx/ddy: */
2355 if (tex->op == nir_texop_txd) {
2356 while (nsrc0 < 4)
2357 src0[nsrc0++] = create_immed(b, fui(0.0));
2358 for (i = 0; i < coords; i++)
2359 src0[nsrc0++] = ddx[i];
2360 if (coords < 2)
2361 src0[nsrc0++] = create_immed(b, fui(0.0));
2362 for (i = 0; i < coords; i++)
2363 src0[nsrc0++] = ddy[i];
2364 if (coords < 2)
2365 src0[nsrc0++] = create_immed(b, fui(0.0));
2366 }
2367
2368 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2369 * with scaled x coord according to requested sample:
2370 */
2371 if (opc == OPC_ISAMM) {
2372 if (ctx->compiler->txf_ms_with_isaml) {
2373 /* the samples are laid out in x dimension as
2374 * 0 1 2 3
2375 * x_ms = (x << ms) + sample_index;
2376 */
2377 struct ir3_instruction *ms;
2378 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
2379
2380 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
2381 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
2382
2383 opc = OPC_ISAML;
2384 } else {
2385 src0[nsrc0++] = sample_index;
2386 }
2387 }
2388
2389 /*
2390 * second argument (if applicable):
2391 * - offsets
2392 * - lod
2393 * - bias
2394 */
2395 if (has_off | has_lod | has_bias) {
2396 if (has_off) {
2397 unsigned off_coords = coords;
2398 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2399 off_coords--;
2400 for (i = 0; i < off_coords; i++)
2401 src1[nsrc1++] = off[i];
2402 if (off_coords < 2)
2403 src1[nsrc1++] = create_immed(b, fui(0.0));
2404 flags |= IR3_INSTR_O;
2405 }
2406
2407 if (has_lod | has_bias)
2408 src1[nsrc1++] = lod;
2409 }
2410
2411 type = get_tex_dest_type(tex);
2412
2413 if (opc == OPC_GETLOD)
2414 type = TYPE_S32;
2415
2416
2417 if (tex->op == nir_texop_txf_ms_fb) {
2418 /* only expect a single txf_ms_fb per shader: */
2419 compile_assert(ctx, !ctx->so->fb_read);
2420 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
2421
2422 ctx->so->fb_read = true;
2423 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2424 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2425 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2426 }, 2);
2427 info.flags = IR3_INSTR_S2EN;
2428
2429 ctx->so->num_samp++;
2430 } else {
2431 info = get_tex_samp_tex_src(ctx, tex);
2432 }
2433
2434 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
2435 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
2436
2437 if (opc == OPC_META_TEX_PREFETCH) {
2438 int idx = nir_tex_instr_src_index(tex, nir_tex_src_coord);
2439
2440 compile_assert(ctx, tex->src[idx].src.is_ssa);
2441
2442 sam = ir3_META_TEX_PREFETCH(b);
2443 __ssa_dst(sam)->wrmask = MASK(ncomp); /* dst */
2444 __ssa_src(sam, get_barycentric_pixel(ctx), 0);
2445 sam->prefetch.input_offset =
2446 ir3_nir_coord_offset(tex->src[idx].src.ssa);
2447 /* make sure not to add irrelevant flags like S2EN */
2448 sam->flags = flags | (info.flags & IR3_INSTR_B);
2449 sam->prefetch.tex = info.tex_idx;
2450 sam->prefetch.samp = info.samp_idx;
2451 sam->prefetch.tex_base = info.tex_base;
2452 sam->prefetch.samp_base = info.samp_base;
2453 } else {
2454 info.flags |= flags;
2455 sam = emit_sam(ctx, opc, info, type, MASK(ncomp), col0, col1);
2456 }
2457
2458 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
2459 assert(opc != OPC_META_TEX_PREFETCH);
2460
2461 /* only need first 3 components: */
2462 sam->regs[0]->wrmask = 0x7;
2463 ir3_split_dest(b, dst, sam, 0, 3);
2464
2465 /* we need to sample the alpha separately with a non-ASTC
2466 * texture state:
2467 */
2468 sam = ir3_SAM(b, opc, type, 0b1000, flags | info.flags,
2469 info.samp_tex, col0, col1);
2470
2471 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
2472
2473 /* fixup .w component: */
2474 ir3_split_dest(b, &dst[3], sam, 3, 1);
2475 } else {
2476 /* normal (non-workaround) case: */
2477 ir3_split_dest(b, dst, sam, 0, ncomp);
2478 }
2479
2480 /* GETLOD returns results in 4.8 fixed point */
2481 if (opc == OPC_GETLOD) {
2482 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
2483
2484 compile_assert(ctx, tex->dest_type == nir_type_float);
2485 for (i = 0; i < 2; i++) {
2486 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_S32, TYPE_F32), 0,
2487 factor, 0);
2488 }
2489 }
2490
2491 ir3_put_dst(ctx, &tex->dest);
2492 }
2493
2494 static void
2495 emit_tex_info(struct ir3_context *ctx, nir_tex_instr *tex, unsigned idx)
2496 {
2497 struct ir3_block *b = ctx->block;
2498 struct ir3_instruction **dst, *sam;
2499 type_t dst_type = get_tex_dest_type(tex);
2500 struct tex_src_info info = get_tex_samp_tex_src(ctx, tex);
2501
2502 dst = ir3_get_dst(ctx, &tex->dest, 1);
2503
2504 sam = emit_sam(ctx, OPC_GETINFO, info, dst_type, 1 << idx, NULL, NULL);
2505
2506 /* even though there is only one component, since it ends
2507 * up in .y/.z/.w rather than .x, we need a split_dest()
2508 */
2509 if (idx)
2510 ir3_split_dest(b, dst, sam, 0, idx + 1);
2511
2512 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2513 * the value in TEX_CONST_0 is zero-based.
2514 */
2515 if (ctx->compiler->levels_add_one)
2516 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2517
2518 ir3_put_dst(ctx, &tex->dest);
2519 }
2520
2521 static void
2522 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2523 {
2524 struct ir3_block *b = ctx->block;
2525 struct ir3_instruction **dst, *sam;
2526 struct ir3_instruction *lod;
2527 unsigned flags, coords;
2528 type_t dst_type = get_tex_dest_type(tex);
2529 struct tex_src_info info = get_tex_samp_tex_src(ctx, tex);
2530
2531 tex_info(tex, &flags, &coords);
2532 info.flags |= flags;
2533
2534 /* Actually we want the number of dimensions, not coordinates. This
2535 * distinction only matters for cubes.
2536 */
2537 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2538 coords = 2;
2539
2540 dst = ir3_get_dst(ctx, &tex->dest, 4);
2541
2542 compile_assert(ctx, tex->num_srcs == 1);
2543 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
2544
2545 lod = ir3_get_src(ctx, &tex->src[0].src)[0];
2546
2547 sam = emit_sam(ctx, OPC_GETSIZE, info, dst_type, 0b1111, lod, NULL);
2548 ir3_split_dest(b, dst, sam, 0, 4);
2549
2550 /* Array size actually ends up in .w rather than .z. This doesn't
2551 * matter for miplevel 0, but for higher mips the value in z is
2552 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2553 * returned, which means that we have to add 1 to it for arrays.
2554 */
2555 if (tex->is_array) {
2556 if (ctx->compiler->levels_add_one) {
2557 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2558 } else {
2559 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2560 }
2561 }
2562
2563 ir3_put_dst(ctx, &tex->dest);
2564 }
2565
2566 static void
2567 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2568 {
2569 switch (jump->type) {
2570 case nir_jump_break:
2571 case nir_jump_continue:
2572 case nir_jump_return:
2573 /* I *think* we can simply just ignore this, and use the
2574 * successor block link to figure out where we need to
2575 * jump to for break/continue
2576 */
2577 break;
2578 default:
2579 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2580 break;
2581 }
2582 }
2583
2584 static void
2585 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2586 {
2587 switch (instr->type) {
2588 case nir_instr_type_alu:
2589 emit_alu(ctx, nir_instr_as_alu(instr));
2590 break;
2591 case nir_instr_type_deref:
2592 /* ignored, handled as part of the intrinsic they are src to */
2593 break;
2594 case nir_instr_type_intrinsic:
2595 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2596 break;
2597 case nir_instr_type_load_const:
2598 emit_load_const(ctx, nir_instr_as_load_const(instr));
2599 break;
2600 case nir_instr_type_ssa_undef:
2601 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2602 break;
2603 case nir_instr_type_tex: {
2604 nir_tex_instr *tex = nir_instr_as_tex(instr);
2605 /* couple tex instructions get special-cased:
2606 */
2607 switch (tex->op) {
2608 case nir_texop_txs:
2609 emit_tex_txs(ctx, tex);
2610 break;
2611 case nir_texop_query_levels:
2612 emit_tex_info(ctx, tex, 2);
2613 break;
2614 case nir_texop_texture_samples:
2615 emit_tex_info(ctx, tex, 3);
2616 break;
2617 default:
2618 emit_tex(ctx, tex);
2619 break;
2620 }
2621 break;
2622 }
2623 case nir_instr_type_jump:
2624 emit_jump(ctx, nir_instr_as_jump(instr));
2625 break;
2626 case nir_instr_type_phi:
2627 /* we have converted phi webs to regs in NIR by now */
2628 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2629 break;
2630 case nir_instr_type_call:
2631 case nir_instr_type_parallel_copy:
2632 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2633 break;
2634 }
2635 }
2636
2637 static struct ir3_block *
2638 get_block(struct ir3_context *ctx, const nir_block *nblock)
2639 {
2640 struct ir3_block *block;
2641 struct hash_entry *hentry;
2642
2643 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2644 if (hentry)
2645 return hentry->data;
2646
2647 block = ir3_block_create(ctx->ir);
2648 block->nblock = nblock;
2649 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2650
2651 block->predecessors = _mesa_pointer_set_create(block);
2652 set_foreach(nblock->predecessors, sentry) {
2653 _mesa_set_add(block->predecessors, get_block(ctx, sentry->key));
2654 }
2655
2656 return block;
2657 }
2658
2659 static void
2660 emit_block(struct ir3_context *ctx, nir_block *nblock)
2661 {
2662 struct ir3_block *block = get_block(ctx, nblock);
2663
2664 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2665 if (nblock->successors[i]) {
2666 block->successors[i] =
2667 get_block(ctx, nblock->successors[i]);
2668 }
2669 }
2670
2671 ctx->block = block;
2672 list_addtail(&block->node, &ctx->ir->block_list);
2673
2674 /* re-emit addr register in each block if needed: */
2675 for (int i = 0; i < ARRAY_SIZE(ctx->addr0_ht); i++) {
2676 _mesa_hash_table_destroy(ctx->addr0_ht[i], NULL);
2677 ctx->addr0_ht[i] = NULL;
2678 }
2679
2680 _mesa_hash_table_u64_destroy(ctx->addr1_ht, NULL);
2681 ctx->addr1_ht = NULL;
2682
2683 nir_foreach_instr (instr, nblock) {
2684 ctx->cur_instr = instr;
2685 emit_instr(ctx, instr);
2686 ctx->cur_instr = NULL;
2687 if (ctx->error)
2688 return;
2689 }
2690 }
2691
2692 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2693
2694 static void
2695 emit_if(struct ir3_context *ctx, nir_if *nif)
2696 {
2697 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2698
2699 ctx->block->condition =
2700 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
2701
2702 emit_cf_list(ctx, &nif->then_list);
2703 emit_cf_list(ctx, &nif->else_list);
2704 }
2705
2706 static void
2707 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2708 {
2709 emit_cf_list(ctx, &nloop->body);
2710 ctx->so->loops++;
2711 }
2712
2713 static void
2714 stack_push(struct ir3_context *ctx)
2715 {
2716 ctx->stack++;
2717 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2718 }
2719
2720 static void
2721 stack_pop(struct ir3_context *ctx)
2722 {
2723 compile_assert(ctx, ctx->stack > 0);
2724 ctx->stack--;
2725 }
2726
2727 static void
2728 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2729 {
2730 foreach_list_typed (nir_cf_node, node, node, list) {
2731 switch (node->type) {
2732 case nir_cf_node_block:
2733 emit_block(ctx, nir_cf_node_as_block(node));
2734 break;
2735 case nir_cf_node_if:
2736 stack_push(ctx);
2737 emit_if(ctx, nir_cf_node_as_if(node));
2738 stack_pop(ctx);
2739 break;
2740 case nir_cf_node_loop:
2741 stack_push(ctx);
2742 emit_loop(ctx, nir_cf_node_as_loop(node));
2743 stack_pop(ctx);
2744 break;
2745 case nir_cf_node_function:
2746 ir3_context_error(ctx, "TODO\n");
2747 break;
2748 }
2749 }
2750 }
2751
2752 /* emit stream-out code. At this point, the current block is the original
2753 * (nir) end block, and nir ensures that all flow control paths terminate
2754 * into the end block. We re-purpose the original end block to generate
2755 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2756 * block holding stream-out write instructions, followed by the new end
2757 * block:
2758 *
2759 * blockOrigEnd {
2760 * p0.x = (vtxcnt < maxvtxcnt)
2761 * // succs: blockStreamOut, blockNewEnd
2762 * }
2763 * blockStreamOut {
2764 * ... stream-out instructions ...
2765 * // succs: blockNewEnd
2766 * }
2767 * blockNewEnd {
2768 * }
2769 */
2770 static void
2771 emit_stream_out(struct ir3_context *ctx)
2772 {
2773 struct ir3 *ir = ctx->ir;
2774 struct ir3_stream_output_info *strmout =
2775 &ctx->so->shader->stream_output;
2776 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2777 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2778 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2779
2780 /* create vtxcnt input in input block at top of shader,
2781 * so that it is seen as live over the entire duration
2782 * of the shader:
2783 */
2784 vtxcnt = create_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, 0x1);
2785 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2786
2787 /* at this point, we are at the original 'end' block,
2788 * re-purpose this block to stream-out condition, then
2789 * append stream-out block and new-end block
2790 */
2791 orig_end_block = ctx->block;
2792
2793 // TODO these blocks need to update predecessors..
2794 // maybe w/ store_global intrinsic, we could do this
2795 // stuff in nir->nir pass
2796
2797 stream_out_block = ir3_block_create(ir);
2798 list_addtail(&stream_out_block->node, &ir->block_list);
2799
2800 new_end_block = ir3_block_create(ir);
2801 list_addtail(&new_end_block->node, &ir->block_list);
2802
2803 orig_end_block->successors[0] = stream_out_block;
2804 orig_end_block->successors[1] = new_end_block;
2805 stream_out_block->successors[0] = new_end_block;
2806
2807 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2808 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2809 cond->regs[0]->num = regid(REG_P0, 0);
2810 cond->regs[0]->flags &= ~IR3_REG_SSA;
2811 cond->cat2.condition = IR3_COND_LT;
2812
2813 /* condition goes on previous block to the conditional,
2814 * since it is used to pick which of the two successor
2815 * paths to take:
2816 */
2817 orig_end_block->condition = cond;
2818
2819 /* switch to stream_out_block to generate the stream-out
2820 * instructions:
2821 */
2822 ctx->block = stream_out_block;
2823
2824 /* Calculate base addresses based on vtxcnt. Instructions
2825 * generated for bases not used in following loop will be
2826 * stripped out in the backend.
2827 */
2828 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2829 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
2830 unsigned stride = strmout->stride[i];
2831 struct ir3_instruction *base, *off;
2832
2833 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
2834
2835 /* 24-bit should be enough: */
2836 off = ir3_MUL_U24(ctx->block, vtxcnt, 0,
2837 create_immed(ctx->block, stride * 4), 0);
2838
2839 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2840 }
2841
2842 /* Generate the per-output store instructions: */
2843 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2844 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2845 unsigned c = j + strmout->output[i].start_component;
2846 struct ir3_instruction *base, *out, *stg;
2847
2848 base = bases[strmout->output[i].output_buffer];
2849 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2850
2851 stg = ir3_STG(ctx->block, base, 0, out, 0,
2852 create_immed(ctx->block, 1), 0);
2853 stg->cat6.type = TYPE_U32;
2854 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2855
2856 array_insert(ctx->block, ctx->block->keeps, stg);
2857 }
2858 }
2859
2860 /* and finally switch to the new_end_block: */
2861 ctx->block = new_end_block;
2862 }
2863
2864 static void
2865 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2866 {
2867 nir_metadata_require(impl, nir_metadata_block_index);
2868
2869 compile_assert(ctx, ctx->stack == 0);
2870
2871 emit_cf_list(ctx, &impl->body);
2872 emit_block(ctx, impl->end_block);
2873
2874 compile_assert(ctx, ctx->stack == 0);
2875
2876 /* at this point, we should have a single empty block,
2877 * into which we emit the 'end' instruction.
2878 */
2879 compile_assert(ctx, list_is_empty(&ctx->block->instr_list));
2880
2881 /* If stream-out (aka transform-feedback) enabled, emit the
2882 * stream-out instructions, followed by a new empty block (into
2883 * which the 'end' instruction lands).
2884 *
2885 * NOTE: it is done in this order, rather than inserting before
2886 * we emit end_block, because NIR guarantees that all blocks
2887 * flow into end_block, and that end_block has no successors.
2888 * So by re-purposing end_block as the first block of stream-
2889 * out, we guarantee that all exit paths flow into the stream-
2890 * out instructions.
2891 */
2892 if ((ctx->compiler->gpu_id < 500) &&
2893 (ctx->so->shader->stream_output.num_outputs > 0) &&
2894 !ctx->so->binning_pass) {
2895 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2896 emit_stream_out(ctx);
2897 }
2898
2899 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2900 * NOP and has an epilogue that writes the VS outputs to local storage, to
2901 * be read by the HS. Then it resets execution mask (chmask) and chains
2902 * to the next shader (chsh).
2903 */
2904 if ((ctx->so->type == MESA_SHADER_VERTEX &&
2905 (ctx->so->key.has_gs || ctx->so->key.tessellation)) ||
2906 (ctx->so->type == MESA_SHADER_TESS_EVAL && ctx->so->key.has_gs)) {
2907 struct ir3_instruction *chmask =
2908 ir3_CHMASK(ctx->block);
2909 chmask->barrier_class = IR3_BARRIER_EVERYTHING;
2910 chmask->barrier_conflict = IR3_BARRIER_EVERYTHING;
2911
2912 struct ir3_instruction *chsh =
2913 ir3_CHSH(ctx->block);
2914 chsh->barrier_class = IR3_BARRIER_EVERYTHING;
2915 chsh->barrier_conflict = IR3_BARRIER_EVERYTHING;
2916 } else {
2917 ir3_END(ctx->block);
2918 }
2919 }
2920
2921 static void
2922 setup_input(struct ir3_context *ctx, nir_variable *in)
2923 {
2924 struct ir3_shader_variant *so = ctx->so;
2925 unsigned ncomp = glsl_get_components(in->type);
2926 unsigned n = in->data.driver_location;
2927 unsigned frac = in->data.location_frac;
2928 unsigned slot = in->data.location;
2929
2930 /* Inputs are loaded using ldlw or ldg for these stages. */
2931 if (ctx->so->type == MESA_SHADER_TESS_CTRL ||
2932 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2933 ctx->so->type == MESA_SHADER_GEOMETRY)
2934 return;
2935
2936 /* skip unread inputs, we could end up with (for example), unsplit
2937 * matrix/etc inputs in the case they are not read, so just silently
2938 * skip these.
2939 */
2940 if (ncomp > 4)
2941 return;
2942
2943 so->inputs[n].slot = slot;
2944 so->inputs[n].compmask |= (1 << (ncomp + frac)) - 1;
2945 so->inputs_count = MAX2(so->inputs_count, n + 1);
2946 so->inputs[n].interpolate = in->data.interpolation;
2947
2948 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2949
2950 /* if any varyings have 'sample' qualifer, that triggers us
2951 * to run in per-sample mode:
2952 */
2953 so->per_samp |= in->data.sample;
2954
2955 for (int i = 0; i < ncomp; i++) {
2956 struct ir3_instruction *instr = NULL;
2957 unsigned idx = (n * 4) + i + frac;
2958
2959 if (slot == VARYING_SLOT_POS) {
2960 ir3_context_error(ctx, "fragcoord should be a sysval!\n");
2961 } else if (slot == VARYING_SLOT_PNTC) {
2962 /* see for example st_nir_fixup_varying_slots().. this is
2963 * maybe a bit mesa/st specific. But we need things to line
2964 * up for this in fdN_program:
2965 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2966 * if (emit->sprite_coord_enable & texmask) {
2967 * ...
2968 * }
2969 */
2970 so->inputs[n].slot = VARYING_SLOT_VAR8;
2971 so->inputs[n].bary = true;
2972 instr = create_frag_input(ctx, false, idx);
2973 } else {
2974 /* detect the special case for front/back colors where
2975 * we need to do flat vs smooth shading depending on
2976 * rast state:
2977 */
2978 if (in->data.interpolation == INTERP_MODE_NONE) {
2979 switch (slot) {
2980 case VARYING_SLOT_COL0:
2981 case VARYING_SLOT_COL1:
2982 case VARYING_SLOT_BFC0:
2983 case VARYING_SLOT_BFC1:
2984 so->inputs[n].rasterflat = true;
2985 break;
2986 default:
2987 break;
2988 }
2989 }
2990
2991 if (ctx->compiler->flat_bypass) {
2992 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2993 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2994 so->inputs[n].use_ldlv = true;
2995 }
2996
2997 so->inputs[n].bary = true;
2998
2999 instr = create_frag_input(ctx, so->inputs[n].use_ldlv, idx);
3000 }
3001
3002 compile_assert(ctx, idx < ctx->ninputs);
3003
3004 ctx->inputs[idx] = instr;
3005 }
3006 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
3007 struct ir3_instruction *input = NULL, *in;
3008 struct ir3_instruction *components[4];
3009 unsigned mask = (1 << (ncomp + frac)) - 1;
3010
3011 foreach_input (in, ctx->ir) {
3012 if (in->input.inidx == n) {
3013 input = in;
3014 break;
3015 }
3016 }
3017
3018 if (!input) {
3019 input = create_input(ctx, mask);
3020 input->input.inidx = n;
3021 } else {
3022 input->regs[0]->wrmask |= mask;
3023 }
3024
3025 ir3_split_dest(ctx->block, components, input, frac, ncomp);
3026
3027 for (int i = 0; i < ncomp; i++) {
3028 unsigned idx = (n * 4) + i + frac;
3029 compile_assert(ctx, idx < ctx->ninputs);
3030 ctx->inputs[idx] = components[i];
3031 }
3032 } else {
3033 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
3034 }
3035
3036 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
3037 so->total_in += ncomp;
3038 }
3039 }
3040
3041 /* Initially we assign non-packed inloc's for varyings, as we don't really
3042 * know up-front which components will be unused. After all the compilation
3043 * stages we scan the shader to see which components are actually used, and
3044 * re-pack the inlocs to eliminate unneeded varyings.
3045 */
3046 static void
3047 pack_inlocs(struct ir3_context *ctx)
3048 {
3049 struct ir3_shader_variant *so = ctx->so;
3050 uint8_t used_components[so->inputs_count];
3051
3052 memset(used_components, 0, sizeof(used_components));
3053
3054 /*
3055 * First Step: scan shader to find which bary.f/ldlv remain:
3056 */
3057
3058 foreach_block (block, &ctx->ir->block_list) {
3059 foreach_instr (instr, &block->instr_list) {
3060 if (is_input(instr)) {
3061 unsigned inloc = instr->regs[1]->iim_val;
3062 unsigned i = inloc / 4;
3063 unsigned j = inloc % 4;
3064
3065 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
3066 compile_assert(ctx, i < so->inputs_count);
3067
3068 used_components[i] |= 1 << j;
3069 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
3070 for (int n = 0; n < 2; n++) {
3071 unsigned inloc = instr->prefetch.input_offset + n;
3072 unsigned i = inloc / 4;
3073 unsigned j = inloc % 4;
3074
3075 compile_assert(ctx, i < so->inputs_count);
3076
3077 used_components[i] |= 1 << j;
3078 }
3079 }
3080 }
3081 }
3082
3083 /*
3084 * Second Step: reassign varying inloc/slots:
3085 */
3086
3087 unsigned actual_in = 0;
3088 unsigned inloc = 0;
3089
3090 for (unsigned i = 0; i < so->inputs_count; i++) {
3091 unsigned compmask = 0, maxcomp = 0;
3092
3093 so->inputs[i].inloc = inloc;
3094 so->inputs[i].bary = false;
3095
3096 for (unsigned j = 0; j < 4; j++) {
3097 if (!(used_components[i] & (1 << j)))
3098 continue;
3099
3100 compmask |= (1 << j);
3101 actual_in++;
3102 maxcomp = j + 1;
3103
3104 /* at this point, since used_components[i] mask is only
3105 * considering varyings (ie. not sysvals) we know this
3106 * is a varying:
3107 */
3108 so->inputs[i].bary = true;
3109 }
3110
3111 if (so->inputs[i].bary) {
3112 so->varying_in++;
3113 so->inputs[i].compmask = (1 << maxcomp) - 1;
3114 inloc += maxcomp;
3115 }
3116 }
3117
3118 /*
3119 * Third Step: reassign packed inloc's:
3120 */
3121
3122 foreach_block (block, &ctx->ir->block_list) {
3123 foreach_instr (instr, &block->instr_list) {
3124 if (is_input(instr)) {
3125 unsigned inloc = instr->regs[1]->iim_val;
3126 unsigned i = inloc / 4;
3127 unsigned j = inloc % 4;
3128
3129 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
3130 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
3131 unsigned i = instr->prefetch.input_offset / 4;
3132 unsigned j = instr->prefetch.input_offset % 4;
3133 instr->prefetch.input_offset = so->inputs[i].inloc + j;
3134 }
3135 }
3136 }
3137 }
3138
3139 static void
3140 setup_output(struct ir3_context *ctx, nir_variable *out)
3141 {
3142 struct ir3_shader_variant *so = ctx->so;
3143 unsigned ncomp = glsl_get_components(out->type);
3144 unsigned n = out->data.driver_location;
3145 unsigned frac = out->data.location_frac;
3146 unsigned slot = out->data.location;
3147 unsigned comp = 0;
3148
3149 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3150 switch (slot) {
3151 case FRAG_RESULT_DEPTH:
3152 comp = 2; /* tgsi will write to .z component */
3153 so->writes_pos = true;
3154 break;
3155 case FRAG_RESULT_COLOR:
3156 so->color0_mrt = 1;
3157 break;
3158 case FRAG_RESULT_SAMPLE_MASK:
3159 so->writes_smask = true;
3160 break;
3161 default:
3162 if (slot >= FRAG_RESULT_DATA0)
3163 break;
3164 ir3_context_error(ctx, "unknown FS output name: %s\n",
3165 gl_frag_result_name(slot));
3166 }
3167 } else if (ctx->so->type == MESA_SHADER_VERTEX ||
3168 ctx->so->type == MESA_SHADER_TESS_EVAL ||
3169 ctx->so->type == MESA_SHADER_GEOMETRY) {
3170 switch (slot) {
3171 case VARYING_SLOT_POS:
3172 so->writes_pos = true;
3173 break;
3174 case VARYING_SLOT_PSIZ:
3175 so->writes_psize = true;
3176 break;
3177 case VARYING_SLOT_PRIMITIVE_ID:
3178 case VARYING_SLOT_LAYER:
3179 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
3180 debug_assert(ctx->so->type == MESA_SHADER_GEOMETRY);
3181 /* fall through */
3182 case VARYING_SLOT_COL0:
3183 case VARYING_SLOT_COL1:
3184 case VARYING_SLOT_BFC0:
3185 case VARYING_SLOT_BFC1:
3186 case VARYING_SLOT_FOGC:
3187 case VARYING_SLOT_CLIP_DIST0:
3188 case VARYING_SLOT_CLIP_DIST1:
3189 case VARYING_SLOT_CLIP_VERTEX:
3190 break;
3191 default:
3192 if (slot >= VARYING_SLOT_VAR0)
3193 break;
3194 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
3195 break;
3196 ir3_context_error(ctx, "unknown %s shader output name: %s\n",
3197 _mesa_shader_stage_to_string(ctx->so->type),
3198 gl_varying_slot_name(slot));
3199 }
3200 } else if (ctx->so->type == MESA_SHADER_TESS_CTRL) {
3201 /* output lowered to buffer writes. */
3202 return;
3203 } else {
3204 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
3205 }
3206
3207 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
3208
3209 so->outputs[n].slot = slot;
3210 so->outputs[n].regid = regid(n, comp);
3211 so->outputs_count = MAX2(so->outputs_count, n + 1);
3212
3213 for (int i = 0; i < ncomp; i++) {
3214 unsigned idx = (n * 4) + i + frac;
3215 compile_assert(ctx, idx < ctx->noutputs);
3216 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
3217 }
3218
3219 /* if varying packing doesn't happen, we could end up in a situation
3220 * with "holes" in the output, and since the per-generation code that
3221 * sets up varying linkage registers doesn't expect to have more than
3222 * one varying per vec4 slot, pad the holes.
3223 *
3224 * Note that this should probably generate a performance warning of
3225 * some sort.
3226 */
3227 for (int i = 0; i < frac; i++) {
3228 unsigned idx = (n * 4) + i;
3229 if (!ctx->outputs[idx]) {
3230 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
3231 }
3232 }
3233 }
3234
3235 static int
3236 max_drvloc(struct exec_list *vars)
3237 {
3238 int drvloc = -1;
3239 nir_foreach_variable (var, vars) {
3240 drvloc = MAX2(drvloc, (int)var->data.driver_location);
3241 }
3242 return drvloc;
3243 }
3244
3245 static void
3246 emit_instructions(struct ir3_context *ctx)
3247 {
3248 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
3249
3250 ctx->ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4;
3251 ctx->noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4;
3252
3253 ctx->inputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->ninputs);
3254 ctx->outputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->noutputs);
3255
3256 ctx->ir = ir3_create(ctx->compiler, ctx->so->type);
3257
3258 /* Create inputs in first block: */
3259 ctx->block = get_block(ctx, nir_start_block(fxn));
3260 ctx->in_block = ctx->block;
3261 list_addtail(&ctx->block->node, &ctx->ir->block_list);
3262
3263 /* for fragment shader, the vcoord input register is used as the
3264 * base for bary.f varying fetch instrs:
3265 *
3266 * TODO defer creating ctx->ij_pixel and corresponding sysvals
3267 * until emit_intrinsic when we know they are actually needed.
3268 * For now, we defer creating ctx->ij_centroid, etc, since we
3269 * only need ij_pixel for "old style" varying inputs (ie.
3270 * tgsi_to_nir)
3271 */
3272 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3273 ctx->ij_pixel = create_input(ctx, 0x3);
3274 }
3275
3276 /* Setup inputs: */
3277 nir_foreach_variable (var, &ctx->s->inputs) {
3278 setup_input(ctx, var);
3279 }
3280
3281 /* Defer add_sysval_input() stuff until after setup_inputs(),
3282 * because sysvals need to be appended after varyings:
3283 */
3284 if (ctx->ij_pixel) {
3285 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL,
3286 0x3, ctx->ij_pixel);
3287 }
3288
3289
3290 /* Tesselation shaders always need primitive ID for indexing the
3291 * BO. Geometry shaders don't always need it but when they do it has be
3292 * delivered and unclobbered in the VS. To make things easy, we always
3293 * make room for it in VS/DS.
3294 */
3295 bool has_tess = ctx->so->key.tessellation != IR3_TESS_NONE;
3296 bool has_gs = ctx->so->key.has_gs;
3297 switch (ctx->so->type) {
3298 case MESA_SHADER_VERTEX:
3299 if (has_tess) {
3300 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3301 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3302 } else if (has_gs) {
3303 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3304 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3305 }
3306 break;
3307 case MESA_SHADER_TESS_CTRL:
3308 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3309 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3310 break;
3311 case MESA_SHADER_TESS_EVAL:
3312 if (has_gs)
3313 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3314 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3315 break;
3316 case MESA_SHADER_GEOMETRY:
3317 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3318 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3319 break;
3320 default:
3321 break;
3322 }
3323
3324 /* Setup outputs: */
3325 nir_foreach_variable (var, &ctx->s->outputs) {
3326 setup_output(ctx, var);
3327 }
3328
3329 /* Find # of samplers: */
3330 nir_foreach_variable (var, &ctx->s->uniforms) {
3331 ctx->so->num_samp += glsl_type_get_sampler_count(var->type);
3332 /* just assume that we'll be reading from images.. if it
3333 * is write-only we don't have to count it, but not sure
3334 * if there is a good way to know?
3335 */
3336 ctx->so->num_samp += glsl_type_get_image_count(var->type);
3337 }
3338
3339 /* NOTE: need to do something more clever when we support >1 fxn */
3340 nir_foreach_register (reg, &fxn->registers) {
3341 ir3_declare_array(ctx, reg);
3342 }
3343 /* And emit the body: */
3344 ctx->impl = fxn;
3345 emit_function(ctx, fxn);
3346 }
3347
3348 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3349 * need to assign the tex state indexes for these after we know the
3350 * max tex index.
3351 */
3352 static void
3353 fixup_astc_srgb(struct ir3_context *ctx)
3354 {
3355 struct ir3_shader_variant *so = ctx->so;
3356 /* indexed by original tex idx, value is newly assigned alpha sampler
3357 * state tex idx. Zero is invalid since there is at least one sampler
3358 * if we get here.
3359 */
3360 unsigned alt_tex_state[16] = {0};
3361 unsigned tex_idx = ctx->max_texture_index + 1;
3362 unsigned idx = 0;
3363
3364 so->astc_srgb.base = tex_idx;
3365
3366 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
3367 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
3368
3369 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
3370
3371 if (alt_tex_state[sam->cat5.tex] == 0) {
3372 /* assign new alternate/alpha tex state slot: */
3373 alt_tex_state[sam->cat5.tex] = tex_idx++;
3374 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
3375 so->astc_srgb.count++;
3376 }
3377
3378 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
3379 }
3380 }
3381
3382 static void
3383 fixup_binning_pass(struct ir3_context *ctx)
3384 {
3385 struct ir3_shader_variant *so = ctx->so;
3386 struct ir3 *ir = ctx->ir;
3387 unsigned i, j;
3388
3389 /* first pass, remove unused outputs from the IR level outputs: */
3390 for (i = 0, j = 0; i < ir->outputs_count; i++) {
3391 struct ir3_instruction *out = ir->outputs[i];
3392 assert(out->opc == OPC_META_COLLECT);
3393 unsigned outidx = out->collect.outidx;
3394 unsigned slot = so->outputs[outidx].slot;
3395
3396 /* throw away everything but first position/psize */
3397 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3398 ir->outputs[j] = ir->outputs[i];
3399 j++;
3400 }
3401 }
3402 ir->outputs_count = j;
3403
3404 /* second pass, cleanup the unused slots in ir3_shader_variant::outputs
3405 * table:
3406 */
3407 for (i = 0, j = 0; i < so->outputs_count; i++) {
3408 unsigned slot = so->outputs[i].slot;
3409
3410 /* throw away everything but first position/psize */
3411 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3412 so->outputs[j] = so->outputs[i];
3413
3414 /* fixup outidx to point to new output table entry: */
3415 struct ir3_instruction *out;
3416 foreach_output (out, ir) {
3417 if (out->collect.outidx == i) {
3418 out->collect.outidx = j;
3419 break;
3420 }
3421 }
3422
3423 j++;
3424 }
3425 }
3426 so->outputs_count = j;
3427 }
3428
3429 static void
3430 collect_tex_prefetches(struct ir3_context *ctx, struct ir3 *ir)
3431 {
3432 unsigned idx = 0;
3433
3434 /* Collect sampling instructions eligible for pre-dispatch. */
3435 foreach_block (block, &ir->block_list) {
3436 foreach_instr_safe (instr, &block->instr_list) {
3437 if (instr->opc == OPC_META_TEX_PREFETCH) {
3438 assert(idx < ARRAY_SIZE(ctx->so->sampler_prefetch));
3439 struct ir3_sampler_prefetch *fetch =
3440 &ctx->so->sampler_prefetch[idx];
3441 idx++;
3442
3443 if (instr->flags & IR3_INSTR_B) {
3444 fetch->cmd = IR3_SAMPLER_BINDLESS_PREFETCH_CMD;
3445 /* In bindless mode, the index is actually the base */
3446 fetch->tex_id = instr->prefetch.tex_base;
3447 fetch->samp_id = instr->prefetch.samp_base;
3448 fetch->tex_bindless_id = instr->prefetch.tex;
3449 fetch->samp_bindless_id = instr->prefetch.samp;
3450 } else {
3451 fetch->cmd = IR3_SAMPLER_PREFETCH_CMD;
3452 fetch->tex_id = instr->prefetch.tex;
3453 fetch->samp_id = instr->prefetch.samp;
3454 }
3455 fetch->wrmask = instr->regs[0]->wrmask;
3456 fetch->dst = instr->regs[0]->num;
3457 fetch->src = instr->prefetch.input_offset;
3458
3459 ctx->so->total_in =
3460 MAX2(ctx->so->total_in, instr->prefetch.input_offset + 2);
3461
3462 /* Disable half precision until supported. */
3463 fetch->half_precision = !!(instr->regs[0]->flags & IR3_REG_HALF);
3464
3465 /* Remove the prefetch placeholder instruction: */
3466 list_delinit(&instr->node);
3467 }
3468 }
3469 }
3470 }
3471
3472 int
3473 ir3_compile_shader_nir(struct ir3_compiler *compiler,
3474 struct ir3_shader_variant *so)
3475 {
3476 struct ir3_context *ctx;
3477 struct ir3 *ir;
3478 int ret = 0, max_bary;
3479
3480 assert(!so->ir);
3481
3482 ctx = ir3_context_init(compiler, so);
3483 if (!ctx) {
3484 DBG("INIT failed!");
3485 ret = -1;
3486 goto out;
3487 }
3488
3489 emit_instructions(ctx);
3490
3491 if (ctx->error) {
3492 DBG("EMIT failed!");
3493 ret = -1;
3494 goto out;
3495 }
3496
3497 ir = so->ir = ctx->ir;
3498
3499 assert((ctx->noutputs % 4) == 0);
3500
3501 /* Setup IR level outputs, which are "collects" that gather
3502 * the scalar components of outputs.
3503 */
3504 for (unsigned i = 0; i < ctx->noutputs; i += 4) {
3505 unsigned ncomp = 0;
3506 /* figure out the # of components written:
3507 *
3508 * TODO do we need to handle holes, ie. if .x and .z
3509 * components written, but .y component not written?
3510 */
3511 for (unsigned j = 0; j < 4; j++) {
3512 if (!ctx->outputs[i + j])
3513 break;
3514 ncomp++;
3515 }
3516
3517 /* Note that in some stages, like TCS, store_output is
3518 * lowered to memory writes, so no components of the
3519 * are "written" from the PoV of traditional store-
3520 * output instructions:
3521 */
3522 if (!ncomp)
3523 continue;
3524
3525 struct ir3_instruction *out =
3526 ir3_create_collect(ctx, &ctx->outputs[i], ncomp);
3527
3528 int outidx = i / 4;
3529 assert(outidx < so->outputs_count);
3530
3531 /* stash index into so->outputs[] so we can map the
3532 * output back to slot/etc later:
3533 */
3534 out->collect.outidx = outidx;
3535
3536 array_insert(ir, ir->outputs, out);
3537 }
3538
3539 /* Set up the gs header as an output for the vertex shader so it won't
3540 * clobber it for the tess ctrl shader.
3541 *
3542 * TODO this could probably be done more cleanly in a nir pass.
3543 */
3544 if (ctx->so->type == MESA_SHADER_VERTEX ||
3545 (ctx->so->key.has_gs && ctx->so->type == MESA_SHADER_TESS_EVAL)) {
3546 if (ctx->primitive_id) {
3547 unsigned n = so->outputs_count++;
3548 so->outputs[n].slot = VARYING_SLOT_PRIMITIVE_ID;
3549
3550 struct ir3_instruction *out =
3551 ir3_create_collect(ctx, &ctx->primitive_id, 1);
3552 out->collect.outidx = n;
3553 array_insert(ir, ir->outputs, out);
3554 }
3555
3556 if (ctx->gs_header) {
3557 unsigned n = so->outputs_count++;
3558 so->outputs[n].slot = VARYING_SLOT_GS_HEADER_IR3;
3559 struct ir3_instruction *out =
3560 ir3_create_collect(ctx, &ctx->gs_header, 1);
3561 out->collect.outidx = n;
3562 array_insert(ir, ir->outputs, out);
3563 }
3564
3565 if (ctx->tcs_header) {
3566 unsigned n = so->outputs_count++;
3567 so->outputs[n].slot = VARYING_SLOT_TCS_HEADER_IR3;
3568 struct ir3_instruction *out =
3569 ir3_create_collect(ctx, &ctx->tcs_header, 1);
3570 out->collect.outidx = n;
3571 array_insert(ir, ir->outputs, out);
3572 }
3573 }
3574
3575 /* at this point, for binning pass, throw away unneeded outputs: */
3576 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
3577 fixup_binning_pass(ctx);
3578
3579 ir3_debug_print(ir, "BEFORE CF");
3580
3581 ir3_cf(ir);
3582
3583 ir3_debug_print(ir, "BEFORE CP");
3584
3585 ir3_cp(ir, so);
3586
3587 /* at this point, for binning pass, throw away unneeded outputs:
3588 * Note that for a6xx and later, we do this after ir3_cp to ensure
3589 * that the uniform/constant layout for BS and VS matches, so that
3590 * we can re-use same VS_CONST state group.
3591 */
3592 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
3593 fixup_binning_pass(ctx);
3594
3595 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3596 * need to make sure not to remove any inputs that are used by
3597 * the nonbinning VS.
3598 */
3599 if (ctx->compiler->gpu_id >= 600 && so->binning_pass &&
3600 so->type == MESA_SHADER_VERTEX) {
3601 for (int i = 0; i < ctx->ninputs; i++) {
3602 struct ir3_instruction *in = ctx->inputs[i];
3603
3604 if (!in)
3605 continue;
3606
3607 unsigned n = i / 4;
3608 unsigned c = i % 4;
3609
3610 debug_assert(n < so->nonbinning->inputs_count);
3611
3612 if (so->nonbinning->inputs[n].sysval)
3613 continue;
3614
3615 /* be sure to keep inputs, even if only used in VS */
3616 if (so->nonbinning->inputs[n].compmask & (1 << c))
3617 array_insert(in->block, in->block->keeps, in);
3618 }
3619 }
3620
3621 ir3_debug_print(ir, "BEFORE GROUPING");
3622
3623 ir3_sched_add_deps(ir);
3624
3625 /* Group left/right neighbors, inserting mov's where needed to
3626 * solve conflicts:
3627 */
3628 ir3_group(ir);
3629
3630 ir3_debug_print(ir, "AFTER GROUPING");
3631
3632 ir3_depth(ir, so);
3633
3634 ir3_debug_print(ir, "AFTER DEPTH");
3635
3636 /* do Sethi–Ullman numbering before scheduling: */
3637 ir3_sun(ir);
3638
3639 ret = ir3_sched(ir);
3640 if (ret) {
3641 DBG("SCHED failed!");
3642 goto out;
3643 }
3644
3645 ir3_debug_print(ir, "AFTER SCHED");
3646
3647 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3648 * with draw pass VS, so binning and draw pass can both use the
3649 * same VBO state.
3650 *
3651 * Note that VS inputs are expected to be full precision.
3652 */
3653 bool pre_assign_inputs = (ir->compiler->gpu_id >= 600) &&
3654 (ir->type == MESA_SHADER_VERTEX) &&
3655 so->binning_pass;
3656
3657 if (pre_assign_inputs) {
3658 for (unsigned i = 0; i < ctx->ninputs; i++) {
3659 struct ir3_instruction *instr = ctx->inputs[i];
3660
3661 if (!instr)
3662 continue;
3663
3664 unsigned n = i / 4;
3665 unsigned c = i % 4;
3666 unsigned regid = so->nonbinning->inputs[n].regid + c;
3667
3668 instr->regs[0]->num = regid;
3669 }
3670
3671 ret = ir3_ra(so, ctx->inputs, ctx->ninputs);
3672 } else if (ctx->tcs_header) {
3673 /* We need to have these values in the same registers between VS and TCS
3674 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3675 */
3676
3677 ctx->tcs_header->regs[0]->num = regid(0, 0);
3678 ctx->primitive_id->regs[0]->num = regid(0, 1);
3679 struct ir3_instruction *precolor[] = { ctx->tcs_header, ctx->primitive_id };
3680 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3681 } else if (ctx->gs_header) {
3682 /* We need to have these values in the same registers between producer
3683 * (VS or DS) and GS since the producer chains to GS and doesn't get
3684 * the sysvals redelivered.
3685 */
3686
3687 ctx->gs_header->regs[0]->num = regid(0, 0);
3688 ctx->primitive_id->regs[0]->num = regid(0, 1);
3689 struct ir3_instruction *precolor[] = { ctx->gs_header, ctx->primitive_id };
3690 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3691 } else if (so->num_sampler_prefetch) {
3692 assert(so->type == MESA_SHADER_FRAGMENT);
3693 struct ir3_instruction *instr, *precolor[2];
3694 int idx = 0;
3695
3696 foreach_input (instr, ir) {
3697 if (instr->input.sysval != SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL)
3698 continue;
3699
3700 assert(idx < ARRAY_SIZE(precolor));
3701
3702 precolor[idx] = instr;
3703 instr->regs[0]->num = idx;
3704
3705 idx++;
3706 }
3707 ret = ir3_ra(so, precolor, idx);
3708 } else {
3709 ret = ir3_ra(so, NULL, 0);
3710 }
3711
3712 if (ret) {
3713 DBG("RA failed!");
3714 goto out;
3715 }
3716
3717 ir3_postsched(ctx);
3718 ir3_debug_print(ir, "AFTER POSTSCHED");
3719
3720 if (compiler->gpu_id >= 600) {
3721 if (ir3_a6xx_fixup_atomic_dests(ir, so)) {
3722 ir3_debug_print(ir, "AFTER ATOMIC FIXUP");
3723 }
3724 }
3725
3726 if (so->type == MESA_SHADER_FRAGMENT)
3727 pack_inlocs(ctx);
3728
3729 /*
3730 * Fixup inputs/outputs to point to the actual registers assigned:
3731 *
3732 * 1) initialize to r63.x (invalid/unused)
3733 * 2) iterate IR level inputs/outputs and update the variants
3734 * inputs/outputs table based on the assigned registers for
3735 * the remaining inputs/outputs.
3736 */
3737
3738 for (unsigned i = 0; i < so->inputs_count; i++)
3739 so->inputs[i].regid = INVALID_REG;
3740 for (unsigned i = 0; i < so->outputs_count; i++)
3741 so->outputs[i].regid = INVALID_REG;
3742
3743 struct ir3_instruction *out;
3744 foreach_output (out, ir) {
3745 assert(out->opc == OPC_META_COLLECT);
3746 unsigned outidx = out->collect.outidx;
3747
3748 so->outputs[outidx].regid = out->regs[0]->num;
3749 so->outputs[outidx].half = !!(out->regs[0]->flags & IR3_REG_HALF);
3750 }
3751
3752 struct ir3_instruction *in;
3753 foreach_input (in, ir) {
3754 assert(in->opc == OPC_META_INPUT);
3755 unsigned inidx = in->input.inidx;
3756
3757 if (pre_assign_inputs && !so->inputs[inidx].sysval) {
3758 if (VALIDREG(so->nonbinning->inputs[inidx].regid)) {
3759 compile_assert(ctx, in->regs[0]->num ==
3760 so->nonbinning->inputs[inidx].regid);
3761 compile_assert(ctx, !!(in->regs[0]->flags & IR3_REG_HALF) ==
3762 so->nonbinning->inputs[inidx].half);
3763 }
3764 so->inputs[inidx].regid = so->nonbinning->inputs[inidx].regid;
3765 so->inputs[inidx].half = so->nonbinning->inputs[inidx].half;
3766 } else {
3767 so->inputs[inidx].regid = in->regs[0]->num;
3768 so->inputs[inidx].half = !!(in->regs[0]->flags & IR3_REG_HALF);
3769 }
3770 }
3771
3772 if (ctx->astc_srgb)
3773 fixup_astc_srgb(ctx);
3774
3775 /* We need to do legalize after (for frag shader's) the "bary.f"
3776 * offsets (inloc) have been assigned.
3777 */
3778 ir3_legalize(ir, so, &max_bary);
3779
3780 ir3_debug_print(ir, "AFTER LEGALIZE");
3781
3782 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3783 * know what we might have to wait on when coming in from VS chsh.
3784 */
3785 if (so->type == MESA_SHADER_TESS_CTRL ||
3786 so->type == MESA_SHADER_GEOMETRY ) {
3787 foreach_block (block, &ir->block_list) {
3788 foreach_instr (instr, &block->instr_list) {
3789 instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
3790 break;
3791 }
3792 }
3793 }
3794
3795 so->branchstack = ctx->max_stack;
3796
3797 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3798 if (so->type == MESA_SHADER_FRAGMENT)
3799 so->total_in = max_bary + 1;
3800
3801 so->max_sun = ir->max_sun;
3802
3803 /* Collect sampling instructions eligible for pre-dispatch. */
3804 collect_tex_prefetches(ctx, ir);
3805
3806 if (so->type == MESA_SHADER_FRAGMENT &&
3807 ctx->s->info.fs.needs_helper_invocations)
3808 so->need_pixlod = true;
3809
3810 out:
3811 if (ret) {
3812 if (so->ir)
3813 ir3_destroy(so->ir);
3814 so->ir = NULL;
3815 }
3816 ir3_context_free(ctx);
3817
3818 return ret;
3819 }