projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
freedreno/ir3: small cleanup and comments
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 __ssa_dst(mov);
55 src = __ssa_src(mov, collect, IR3_REG_RELATIV);
56 src->size = arrsz;
57 src->array.offset = n;
58
59 ir3_instr_set_address(mov, address);
60
61 return mov;
62 }
63
64 static struct ir3_instruction *
65 create_input(struct ir3_context *ctx, unsigned compmask)
66 {
67 struct ir3_instruction *in;
68
69 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
70 in->input.sysval = ~0;
71 __ssa_dst(in)->wrmask = compmask;
72
73 array_insert(ctx->ir, ctx->ir->inputs, in);
74
75 return in;
76 }
77
78 static struct ir3_instruction *
79 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
80 {
81 struct ir3_block *block = ctx->block;
82 struct ir3_instruction *instr;
83 /* packed inloc is fixed up later: */
84 struct ir3_instruction *inloc = create_immed(block, n);
85
86 if (use_ldlv) {
87 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
88 instr->cat6.type = TYPE_U32;
89 instr->cat6.iim_val = 1;
90 } else {
91 instr = ir3_BARY_F(block, inloc, 0, ctx->ij_pixel, 0);
92 instr->regs[2]->wrmask = 0x3;
93 }
94
95 return instr;
96 }
97
98 static struct ir3_instruction *
99 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
100 {
101 /* first four vec4 sysval's reserved for UBOs: */
102 /* NOTE: dp is in scalar, but there can be >4 dp components: */
103 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
104 unsigned n = const_state->offsets.driver_param;
105 unsigned r = regid(n + dp / 4, dp % 4);
106 return create_uniform(ctx->block, r);
107 }
108
109 /*
110 * Adreno uses uint rather than having dedicated bool type,
111 * which (potentially) requires some conversion, in particular
112 * when using output of an bool instr to int input, or visa
113 * versa.
114 *
115 * | Adreno | NIR |
116 * -------+---------+-------+-
117 * true | 1 | ~0 |
118 * false | 0 | 0 |
119 *
120 * To convert from an adreno bool (uint) to nir, use:
121 *
122 * absneg.s dst, (neg)src
123 *
124 * To convert back in the other direction:
125 *
126 * absneg.s dst, (abs)arc
127 *
128 * The CP step can clean up the absneg.s that cancel each other
129 * out, and with a slight bit of extra cleverness (to recognize
130 * the instructions which produce either a 0 or 1) can eliminate
131 * the absneg.s's completely when an instruction that wants
132 * 0/1 consumes the result. For example, when a nir 'bcsel'
133 * consumes the result of 'feq'. So we should be able to get by
134 * without a boolean resolve step, and without incuring any
135 * extra penalty in instruction count.
136 */
137
138 /* NIR bool -> native (adreno): */
139 static struct ir3_instruction *
140 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
141 {
142 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
143 }
144
145 /* native (adreno) -> NIR bool: */
146 static struct ir3_instruction *
147 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
148 {
149 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
150 }
151
152 /*
153 * alu/sfu instructions:
154 */
155
156 static struct ir3_instruction *
157 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
158 unsigned src_bitsize, nir_op op)
159 {
160 type_t src_type, dst_type;
161
162 switch (op) {
163 case nir_op_f2f32:
164 case nir_op_f2f16_rtne:
165 case nir_op_f2f16_rtz:
166 case nir_op_f2f16:
167 case nir_op_f2i32:
168 case nir_op_f2i16:
169 case nir_op_f2i8:
170 case nir_op_f2u32:
171 case nir_op_f2u16:
172 case nir_op_f2u8:
173 switch (src_bitsize) {
174 case 32:
175 src_type = TYPE_F32;
176 break;
177 case 16:
178 src_type = TYPE_F16;
179 break;
180 default:
181 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
182 }
183 break;
184
185 case nir_op_i2f32:
186 case nir_op_i2f16:
187 case nir_op_i2i32:
188 case nir_op_i2i16:
189 case nir_op_i2i8:
190 switch (src_bitsize) {
191 case 32:
192 src_type = TYPE_S32;
193 break;
194 case 16:
195 src_type = TYPE_S16;
196 break;
197 case 8:
198 src_type = TYPE_S8;
199 break;
200 default:
201 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
202 }
203 break;
204
205 case nir_op_u2f32:
206 case nir_op_u2f16:
207 case nir_op_u2u32:
208 case nir_op_u2u16:
209 case nir_op_u2u8:
210 switch (src_bitsize) {
211 case 32:
212 src_type = TYPE_U32;
213 break;
214 case 16:
215 src_type = TYPE_U16;
216 break;
217 case 8:
218 src_type = TYPE_U8;
219 break;
220 default:
221 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
222 }
223 break;
224
225 default:
226 ir3_context_error(ctx, "invalid conversion op: %u", op);
227 }
228
229 switch (op) {
230 case nir_op_f2f32:
231 case nir_op_i2f32:
232 case nir_op_u2f32:
233 dst_type = TYPE_F32;
234 break;
235
236 case nir_op_f2f16_rtne:
237 case nir_op_f2f16_rtz:
238 case nir_op_f2f16:
239 /* TODO how to handle rounding mode? */
240 case nir_op_i2f16:
241 case nir_op_u2f16:
242 dst_type = TYPE_F16;
243 break;
244
245 case nir_op_f2i32:
246 case nir_op_i2i32:
247 dst_type = TYPE_S32;
248 break;
249
250 case nir_op_f2i16:
251 case nir_op_i2i16:
252 dst_type = TYPE_S16;
253 break;
254
255 case nir_op_f2i8:
256 case nir_op_i2i8:
257 dst_type = TYPE_S8;
258 break;
259
260 case nir_op_f2u32:
261 case nir_op_u2u32:
262 dst_type = TYPE_U32;
263 break;
264
265 case nir_op_f2u16:
266 case nir_op_u2u16:
267 dst_type = TYPE_U16;
268 break;
269
270 case nir_op_f2u8:
271 case nir_op_u2u8:
272 dst_type = TYPE_U8;
273 break;
274
275 default:
276 ir3_context_error(ctx, "invalid conversion op: %u", op);
277 }
278
279 return ir3_COV(ctx->block, src, src_type, dst_type);
280 }
281
282 static void
283 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
284 {
285 const nir_op_info *info = &nir_op_infos[alu->op];
286 struct ir3_instruction **dst, *src[info->num_inputs];
287 unsigned bs[info->num_inputs]; /* bit size */
288 struct ir3_block *b = ctx->block;
289 unsigned dst_sz, wrmask;
290 type_t dst_type = nir_dest_bit_size(alu->dest.dest) < 32 ?
291 TYPE_U16 : TYPE_U32;
292
293 if (alu->dest.dest.is_ssa) {
294 dst_sz = alu->dest.dest.ssa.num_components;
295 wrmask = (1 << dst_sz) - 1;
296 } else {
297 dst_sz = alu->dest.dest.reg.reg->num_components;
298 wrmask = alu->dest.write_mask;
299 }
300
301 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
302
303 /* Vectors are special in that they have non-scalarized writemasks,
304 * and just take the first swizzle channel for each argument in
305 * order into each writemask channel.
306 */
307 if ((alu->op == nir_op_vec2) ||
308 (alu->op == nir_op_vec3) ||
309 (alu->op == nir_op_vec4)) {
310
311 for (int i = 0; i < info->num_inputs; i++) {
312 nir_alu_src *asrc = &alu->src[i];
313
314 compile_assert(ctx, !asrc->abs);
315 compile_assert(ctx, !asrc->negate);
316
317 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
318 if (!src[i])
319 src[i] = create_immed_typed(ctx->block, 0, dst_type);
320 dst[i] = ir3_MOV(b, src[i], dst_type);
321 }
322
323 ir3_put_dst(ctx, &alu->dest.dest);
324 return;
325 }
326
327 /* We also get mov's with more than one component for mov's so
328 * handle those specially:
329 */
330 if (alu->op == nir_op_mov) {
331 nir_alu_src *asrc = &alu->src[0];
332 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
333
334 for (unsigned i = 0; i < dst_sz; i++) {
335 if (wrmask & (1 << i)) {
336 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
337 } else {
338 dst[i] = NULL;
339 }
340 }
341
342 ir3_put_dst(ctx, &alu->dest.dest);
343 return;
344 }
345
346 /* General case: We can just grab the one used channel per src. */
347 for (int i = 0; i < info->num_inputs; i++) {
348 unsigned chan = ffs(alu->dest.write_mask) - 1;
349 nir_alu_src *asrc = &alu->src[i];
350
351 compile_assert(ctx, !asrc->abs);
352 compile_assert(ctx, !asrc->negate);
353
354 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
355 bs[i] = nir_src_bit_size(asrc->src);
356
357 compile_assert(ctx, src[i]);
358 }
359
360 switch (alu->op) {
361 case nir_op_f2f32:
362 case nir_op_f2f16_rtne:
363 case nir_op_f2f16_rtz:
364 case nir_op_f2f16:
365 case nir_op_f2i32:
366 case nir_op_f2i16:
367 case nir_op_f2i8:
368 case nir_op_f2u32:
369 case nir_op_f2u16:
370 case nir_op_f2u8:
371 case nir_op_i2f32:
372 case nir_op_i2f16:
373 case nir_op_i2i32:
374 case nir_op_i2i16:
375 case nir_op_i2i8:
376 case nir_op_u2f32:
377 case nir_op_u2f16:
378 case nir_op_u2u32:
379 case nir_op_u2u16:
380 case nir_op_u2u8:
381 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
382 break;
383 case nir_op_fquantize2f16:
384 dst[0] = create_cov(ctx,
385 create_cov(ctx, src[0], 32, nir_op_f2f16),
386 16, nir_op_f2f32);
387 break;
388 case nir_op_f2b16: {
389 struct ir3_instruction *zero = create_immed_typed(b, 0, TYPE_F16);
390 dst[0] = ir3_CMPS_F(b, src[0], 0, zero, 0);
391 dst[0]->cat2.condition = IR3_COND_NE;
392 break;
393 }
394 case nir_op_f2b32:
395 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
396 dst[0]->cat2.condition = IR3_COND_NE;
397 break;
398 case nir_op_b2f16:
399 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F16);
400 break;
401 case nir_op_b2f32:
402 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
403 break;
404 case nir_op_b2i8:
405 case nir_op_b2i16:
406 case nir_op_b2i32:
407 dst[0] = ir3_b2n(b, src[0]);
408 break;
409 case nir_op_i2b16: {
410 struct ir3_instruction *zero = create_immed_typed(b, 0, TYPE_S16);
411 dst[0] = ir3_CMPS_S(b, src[0], 0, zero, 0);
412 dst[0]->cat2.condition = IR3_COND_NE;
413 break;
414 }
415 case nir_op_i2b32:
416 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
417 dst[0]->cat2.condition = IR3_COND_NE;
418 break;
419
420 case nir_op_fneg:
421 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
422 break;
423 case nir_op_fabs:
424 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
425 break;
426 case nir_op_fmax:
427 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
428 break;
429 case nir_op_fmin:
430 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
431 break;
432 case nir_op_fsat:
433 /* if there is just a single use of the src, and it supports
434 * (sat) bit, we can just fold the (sat) flag back to the
435 * src instruction and create a mov. This is easier for cp
436 * to eliminate.
437 *
438 * TODO probably opc_cat==4 is ok too
439 */
440 if (alu->src[0].src.is_ssa &&
441 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
442 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
443 src[0]->flags |= IR3_INSTR_SAT;
444 dst[0] = ir3_MOV(b, src[0], dst_type);
445 } else {
446 /* otherwise generate a max.f that saturates.. blob does
447 * similar (generating a cat2 mov using max.f)
448 */
449 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
450 dst[0]->flags |= IR3_INSTR_SAT;
451 }
452 break;
453 case nir_op_fmul:
454 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
455 break;
456 case nir_op_fadd:
457 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
458 break;
459 case nir_op_fsub:
460 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
461 break;
462 case nir_op_ffma:
463 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
464 break;
465 case nir_op_fddx:
466 case nir_op_fddx_coarse:
467 dst[0] = ir3_DSX(b, src[0], 0);
468 dst[0]->cat5.type = TYPE_F32;
469 break;
470 case nir_op_fddx_fine:
471 dst[0] = ir3_DSXPP_1(b, src[0], 0);
472 dst[0]->cat5.type = TYPE_F32;
473 break;
474 case nir_op_fddy:
475 case nir_op_fddy_coarse:
476 dst[0] = ir3_DSY(b, src[0], 0);
477 dst[0]->cat5.type = TYPE_F32;
478 break;
479 break;
480 case nir_op_fddy_fine:
481 dst[0] = ir3_DSYPP_1(b, src[0], 0);
482 dst[0]->cat5.type = TYPE_F32;
483 break;
484 case nir_op_flt16:
485 case nir_op_flt32:
486 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
487 dst[0]->cat2.condition = IR3_COND_LT;
488 break;
489 case nir_op_fge16:
490 case nir_op_fge32:
491 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
492 dst[0]->cat2.condition = IR3_COND_GE;
493 break;
494 case nir_op_feq16:
495 case nir_op_feq32:
496 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
497 dst[0]->cat2.condition = IR3_COND_EQ;
498 break;
499 case nir_op_fne16:
500 case nir_op_fne32:
501 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
502 dst[0]->cat2.condition = IR3_COND_NE;
503 break;
504 case nir_op_fceil:
505 dst[0] = ir3_CEIL_F(b, src[0], 0);
506 break;
507 case nir_op_ffloor:
508 dst[0] = ir3_FLOOR_F(b, src[0], 0);
509 break;
510 case nir_op_ftrunc:
511 dst[0] = ir3_TRUNC_F(b, src[0], 0);
512 break;
513 case nir_op_fround_even:
514 dst[0] = ir3_RNDNE_F(b, src[0], 0);
515 break;
516 case nir_op_fsign:
517 dst[0] = ir3_SIGN_F(b, src[0], 0);
518 break;
519
520 case nir_op_fsin:
521 dst[0] = ir3_SIN(b, src[0], 0);
522 break;
523 case nir_op_fcos:
524 dst[0] = ir3_COS(b, src[0], 0);
525 break;
526 case nir_op_frsq:
527 dst[0] = ir3_RSQ(b, src[0], 0);
528 break;
529 case nir_op_frcp:
530 dst[0] = ir3_RCP(b, src[0], 0);
531 break;
532 case nir_op_flog2:
533 dst[0] = ir3_LOG2(b, src[0], 0);
534 break;
535 case nir_op_fexp2:
536 dst[0] = ir3_EXP2(b, src[0], 0);
537 break;
538 case nir_op_fsqrt:
539 dst[0] = ir3_SQRT(b, src[0], 0);
540 break;
541
542 case nir_op_iabs:
543 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
544 break;
545 case nir_op_iadd:
546 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
547 break;
548 case nir_op_iand:
549 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
550 break;
551 case nir_op_imax:
552 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
553 break;
554 case nir_op_umax:
555 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
556 break;
557 case nir_op_imin:
558 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
559 break;
560 case nir_op_umin:
561 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
562 break;
563 case nir_op_umul_low:
564 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
565 break;
566 case nir_op_imadsh_mix16:
567 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
568 break;
569 case nir_op_imad24_ir3:
570 dst[0] = ir3_MAD_S24(b, src[0], 0, src[1], 0, src[2], 0);
571 break;
572 case nir_op_imul24:
573 dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
574 break;
575 case nir_op_ineg:
576 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
577 break;
578 case nir_op_inot:
579 dst[0] = ir3_NOT_B(b, src[0], 0);
580 break;
581 case nir_op_ior:
582 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
583 break;
584 case nir_op_ishl:
585 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
586 break;
587 case nir_op_ishr:
588 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
589 break;
590 case nir_op_isub:
591 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
592 break;
593 case nir_op_ixor:
594 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
595 break;
596 case nir_op_ushr:
597 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
598 break;
599 case nir_op_ilt16:
600 case nir_op_ilt32:
601 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
602 dst[0]->cat2.condition = IR3_COND_LT;
603 break;
604 case nir_op_ige16:
605 case nir_op_ige32:
606 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
607 dst[0]->cat2.condition = IR3_COND_GE;
608 break;
609 case nir_op_ieq16:
610 case nir_op_ieq32:
611 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
612 dst[0]->cat2.condition = IR3_COND_EQ;
613 break;
614 case nir_op_ine16:
615 case nir_op_ine32:
616 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
617 dst[0]->cat2.condition = IR3_COND_NE;
618 break;
619 case nir_op_ult16:
620 case nir_op_ult32:
621 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
622 dst[0]->cat2.condition = IR3_COND_LT;
623 break;
624 case nir_op_uge16:
625 case nir_op_uge32:
626 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
627 dst[0]->cat2.condition = IR3_COND_GE;
628 break;
629
630 case nir_op_b16csel:
631 case nir_op_b32csel: {
632 struct ir3_instruction *cond = ir3_b2n(b, src[0]);
633
634 if ((src[0]->regs[0]->flags & IR3_REG_HALF))
635 cond->regs[0]->flags |= IR3_REG_HALF;
636
637 compile_assert(ctx, bs[1] == bs[2]);
638 /* Make sure the boolean condition has the same bit size as the other
639 * two arguments, adding a conversion if necessary.
640 */
641 if (bs[1] < bs[0])
642 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
643 else if (bs[1] > bs[0])
644 cond = ir3_COV(b, cond, TYPE_U16, TYPE_U32);
645
646 if (bs[1] > 16)
647 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
648 else
649 dst[0] = ir3_SEL_B16(b, src[1], 0, cond, 0, src[2], 0);
650 break;
651 }
652 case nir_op_bit_count: {
653 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
654 // double check on earlier gen's. Once half-precision support is
655 // in place, this should probably move to a NIR lowering pass:
656 struct ir3_instruction *hi, *lo;
657
658 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
659 TYPE_U32, TYPE_U16);
660 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
661
662 hi = ir3_CBITS_B(b, hi, 0);
663 lo = ir3_CBITS_B(b, lo, 0);
664
665 // TODO maybe the builders should default to making dst half-precision
666 // if the src's were half precision, to make this less awkward.. otoh
667 // we should probably just do this lowering in NIR.
668 hi->regs[0]->flags |= IR3_REG_HALF;
669 lo->regs[0]->flags |= IR3_REG_HALF;
670
671 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
672 dst[0]->regs[0]->flags |= IR3_REG_HALF;
673 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
674 break;
675 }
676 case nir_op_ifind_msb: {
677 struct ir3_instruction *cmp;
678 dst[0] = ir3_CLZ_S(b, src[0], 0);
679 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
680 cmp->cat2.condition = IR3_COND_GE;
681 dst[0] = ir3_SEL_B32(b,
682 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
683 cmp, 0, dst[0], 0);
684 break;
685 }
686 case nir_op_ufind_msb:
687 dst[0] = ir3_CLZ_B(b, src[0], 0);
688 dst[0] = ir3_SEL_B32(b,
689 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
690 src[0], 0, dst[0], 0);
691 break;
692 case nir_op_find_lsb:
693 dst[0] = ir3_BFREV_B(b, src[0], 0);
694 dst[0] = ir3_CLZ_B(b, dst[0], 0);
695 break;
696 case nir_op_bitfield_reverse:
697 dst[0] = ir3_BFREV_B(b, src[0], 0);
698 break;
699
700 default:
701 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
702 nir_op_infos[alu->op].name);
703 break;
704 }
705
706 if (nir_alu_type_get_base_type(info->output_type) == nir_type_bool) {
707 assert(dst_sz == 1);
708
709 if (nir_dest_bit_size(alu->dest.dest) < 32)
710 dst[0]->regs[0]->flags |= IR3_REG_HALF;
711
712 dst[0] = ir3_n2b(b, dst[0]);
713 }
714
715 if (nir_dest_bit_size(alu->dest.dest) < 32) {
716 for (unsigned i = 0; i < dst_sz; i++) {
717 dst[i]->regs[0]->flags |= IR3_REG_HALF;
718 }
719 }
720
721 ir3_put_dst(ctx, &alu->dest.dest);
722 }
723
724 /* handles direct/indirect UBO reads: */
725 static void
726 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
727 struct ir3_instruction **dst)
728 {
729 struct ir3_block *b = ctx->block;
730 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
731 /* UBO addresses are the first driver params, but subtract 2 here to
732 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
733 * is the uniforms: */
734 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
735 unsigned ubo = regid(const_state->offsets.ubo, 0) - 2;
736 const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
737
738 int off = 0;
739
740 /* First src is ubo index, which could either be an immed or not: */
741 src0 = ir3_get_src(ctx, &intr->src[0])[0];
742 if (is_same_type_mov(src0) &&
743 (src0->regs[1]->flags & IR3_REG_IMMED)) {
744 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
745 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
746 } else {
747 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, ptrsz));
748 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, ptrsz));
749
750 /* NOTE: since relative addressing is used, make sure constlen is
751 * at least big enough to cover all the UBO addresses, since the
752 * assembler won't know what the max address reg is.
753 */
754 ctx->so->constlen = MAX2(ctx->so->constlen,
755 const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
756 }
757
758 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
759 addr = base_lo;
760
761 if (nir_src_is_const(intr->src[1])) {
762 off += nir_src_as_uint(intr->src[1]);
763 } else {
764 /* For load_ubo_indirect, second src is indirect offset: */
765 src1 = ir3_get_src(ctx, &intr->src[1])[0];
766
767 /* and add offset to addr: */
768 addr = ir3_ADD_S(b, addr, 0, src1, 0);
769 }
770
771 /* if offset is to large to encode in the ldg, split it out: */
772 if ((off + (intr->num_components * 4)) > 1024) {
773 /* split out the minimal amount to improve the odds that
774 * cp can fit the immediate in the add.s instruction:
775 */
776 unsigned off2 = off + (intr->num_components * 4) - 1024;
777 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
778 off -= off2;
779 }
780
781 if (ptrsz == 2) {
782 struct ir3_instruction *carry;
783
784 /* handle 32b rollover, ie:
785 * if (addr < base_lo)
786 * base_hi++
787 */
788 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
789 carry->cat2.condition = IR3_COND_LT;
790 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
791
792 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
793 }
794
795 for (int i = 0; i < intr->num_components; i++) {
796 struct ir3_instruction *load =
797 ir3_LDG(b, addr, 0, create_immed(b, 1), 0, /* num components */
798 create_immed(b, off + i * 4), 0);
799 load->cat6.type = TYPE_U32;
800 dst[i] = load;
801 }
802 }
803
804 /* src[] = { block_index } */
805 static void
806 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
807 struct ir3_instruction **dst)
808 {
809 /* SSBO size stored as a const starting at ssbo_sizes: */
810 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
811 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
812 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
813 const_state->ssbo_size.off[blk_idx];
814
815 debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
816
817 dst[0] = create_uniform(ctx->block, idx);
818 }
819
820 /* src[] = { offset }. const_index[] = { base } */
821 static void
822 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
823 struct ir3_instruction **dst)
824 {
825 struct ir3_block *b = ctx->block;
826 struct ir3_instruction *ldl, *offset;
827 unsigned base;
828
829 offset = ir3_get_src(ctx, &intr->src[0])[0];
830 base = nir_intrinsic_base(intr);
831
832 ldl = ir3_LDL(b, offset, 0,
833 create_immed(b, intr->num_components), 0,
834 create_immed(b, base), 0);
835
836 ldl->cat6.type = utype_dst(intr->dest);
837 ldl->regs[0]->wrmask = MASK(intr->num_components);
838
839 ldl->barrier_class = IR3_BARRIER_SHARED_R;
840 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
841
842 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
843 }
844
845 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
846 static void
847 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
848 {
849 struct ir3_block *b = ctx->block;
850 struct ir3_instruction *stl, *offset;
851 struct ir3_instruction * const *value;
852 unsigned base, wrmask;
853
854 value = ir3_get_src(ctx, &intr->src[0]);
855 offset = ir3_get_src(ctx, &intr->src[1])[0];
856
857 base = nir_intrinsic_base(intr);
858 wrmask = nir_intrinsic_write_mask(intr);
859
860 /* Combine groups of consecutive enabled channels in one write
861 * message. We use ffs to find the first enabled channel and then ffs on
862 * the bit-inverse, down-shifted writemask to determine the length of
863 * the block of enabled bits.
864 *
865 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
866 */
867 while (wrmask) {
868 unsigned first_component = ffs(wrmask) - 1;
869 unsigned length = ffs(~(wrmask >> first_component)) - 1;
870
871 stl = ir3_STL(b, offset, 0,
872 ir3_create_collect(ctx, &value[first_component], length), 0,
873 create_immed(b, length), 0);
874 stl->cat6.dst_offset = first_component + base;
875 stl->cat6.type = utype_src(intr->src[0]);
876 stl->barrier_class = IR3_BARRIER_SHARED_W;
877 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
878
879 array_insert(b, b->keeps, stl);
880
881 /* Clear the bits in the writemask that we just wrote, then try
882 * again to see if more channels are left.
883 */
884 wrmask &= (15 << (first_component + length));
885 }
886 }
887
888 /* src[] = { offset }. const_index[] = { base } */
889 static void
890 emit_intrinsic_load_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr,
891 struct ir3_instruction **dst)
892 {
893 struct ir3_block *b = ctx->block;
894 struct ir3_instruction *load, *offset;
895 unsigned base;
896
897 offset = ir3_get_src(ctx, &intr->src[0])[0];
898 base = nir_intrinsic_base(intr);
899
900 load = ir3_LDLW(b, offset, 0,
901 create_immed(b, intr->num_components), 0,
902 create_immed(b, base), 0);
903
904 load->cat6.type = utype_dst(intr->dest);
905 load->regs[0]->wrmask = MASK(intr->num_components);
906
907 load->barrier_class = IR3_BARRIER_SHARED_R;
908 load->barrier_conflict = IR3_BARRIER_SHARED_W;
909
910 ir3_split_dest(b, dst, load, 0, intr->num_components);
911 }
912
913 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
914 static void
915 emit_intrinsic_store_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr)
916 {
917 struct ir3_block *b = ctx->block;
918 struct ir3_instruction *store, *offset;
919 struct ir3_instruction * const *value;
920 unsigned base, wrmask;
921
922 value = ir3_get_src(ctx, &intr->src[0]);
923 offset = ir3_get_src(ctx, &intr->src[1])[0];
924
925 base = nir_intrinsic_base(intr);
926 wrmask = nir_intrinsic_write_mask(intr);
927
928 /* Combine groups of consecutive enabled channels in one write
929 * message. We use ffs to find the first enabled channel and then ffs on
930 * the bit-inverse, down-shifted writemask to determine the length of
931 * the block of enabled bits.
932 *
933 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
934 */
935 while (wrmask) {
936 unsigned first_component = ffs(wrmask) - 1;
937 unsigned length = ffs(~(wrmask >> first_component)) - 1;
938
939 store = ir3_STLW(b, offset, 0,
940 ir3_create_collect(ctx, &value[first_component], length), 0,
941 create_immed(b, length), 0);
942
943 store->cat6.dst_offset = first_component + base;
944 store->cat6.type = utype_src(intr->src[0]);
945 store->barrier_class = IR3_BARRIER_SHARED_W;
946 store->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
947
948 array_insert(b, b->keeps, store);
949
950 /* Clear the bits in the writemask that we just wrote, then try
951 * again to see if more channels are left.
952 */
953 wrmask &= (15 << (first_component + length));
954 }
955 }
956
957 /*
958 * CS shared variable atomic intrinsics
959 *
960 * All of the shared variable atomic memory operations read a value from
961 * memory, compute a new value using one of the operations below, write the
962 * new value to memory, and return the original value read.
963 *
964 * All operations take 2 sources except CompSwap that takes 3. These
965 * sources represent:
966 *
967 * 0: The offset into the shared variable storage region that the atomic
968 * operation will operate on.
969 * 1: The data parameter to the atomic function (i.e. the value to add
970 * in shared_atomic_add, etc).
971 * 2: For CompSwap only: the second data parameter.
972 */
973 static struct ir3_instruction *
974 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
975 {
976 struct ir3_block *b = ctx->block;
977 struct ir3_instruction *atomic, *src0, *src1;
978 type_t type = TYPE_U32;
979
980 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
981 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
982
983 switch (intr->intrinsic) {
984 case nir_intrinsic_shared_atomic_add:
985 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
986 break;
987 case nir_intrinsic_shared_atomic_imin:
988 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
989 type = TYPE_S32;
990 break;
991 case nir_intrinsic_shared_atomic_umin:
992 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
993 break;
994 case nir_intrinsic_shared_atomic_imax:
995 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
996 type = TYPE_S32;
997 break;
998 case nir_intrinsic_shared_atomic_umax:
999 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1000 break;
1001 case nir_intrinsic_shared_atomic_and:
1002 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
1003 break;
1004 case nir_intrinsic_shared_atomic_or:
1005 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
1006 break;
1007 case nir_intrinsic_shared_atomic_xor:
1008 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
1009 break;
1010 case nir_intrinsic_shared_atomic_exchange:
1011 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
1012 break;
1013 case nir_intrinsic_shared_atomic_comp_swap:
1014 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1015 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1016 ir3_get_src(ctx, &intr->src[2])[0],
1017 src1,
1018 }, 2);
1019 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
1020 break;
1021 default:
1022 unreachable("boo");
1023 }
1024
1025 atomic->cat6.iim_val = 1;
1026 atomic->cat6.d = 1;
1027 atomic->cat6.type = type;
1028 atomic->barrier_class = IR3_BARRIER_SHARED_W;
1029 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
1030
1031 /* even if nothing consume the result, we can't DCE the instruction: */
1032 array_insert(b, b->keeps, atomic);
1033
1034 return atomic;
1035 }
1036
1037 /* TODO handle actual indirect/dynamic case.. which is going to be weird
1038 * to handle with the image_mapping table..
1039 */
1040 static struct ir3_instruction *
1041 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1042 {
1043 unsigned slot = nir_src_as_uint(intr->src[0]);
1044 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
1045 struct ir3_instruction *texture, *sampler;
1046
1047 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1048 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1049
1050 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1051 sampler,
1052 texture,
1053 }, 2);
1054 }
1055
1056 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1057 static void
1058 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1059 struct ir3_instruction **dst)
1060 {
1061 struct ir3_block *b = ctx->block;
1062 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
1063 struct ir3_instruction *sam;
1064 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
1065 struct ir3_instruction *coords[4];
1066 unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
1067 type_t type = ir3_get_type_for_image_intrinsic(intr);
1068
1069 /* hmm, this seems a bit odd, but it is what blob does and (at least
1070 * a5xx) just faults on bogus addresses otherwise:
1071 */
1072 if (flags & IR3_INSTR_3D) {
1073 flags &= ~IR3_INSTR_3D;
1074 flags |= IR3_INSTR_A;
1075 }
1076
1077 for (unsigned i = 0; i < ncoords; i++)
1078 coords[i] = src0[i];
1079
1080 if (ncoords == 1)
1081 coords[ncoords++] = create_immed(b, 0);
1082
1083 sam = ir3_SAM(b, OPC_ISAM, type, 0b1111, flags,
1084 samp_tex, ir3_create_collect(ctx, coords, ncoords), NULL);
1085
1086 sam->barrier_class = IR3_BARRIER_IMAGE_R;
1087 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
1088
1089 ir3_split_dest(b, dst, sam, 0, 4);
1090 }
1091
1092 static void
1093 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1094 struct ir3_instruction **dst)
1095 {
1096 struct ir3_block *b = ctx->block;
1097 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
1098 struct ir3_instruction *sam, *lod;
1099 unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
1100 type_t dst_type = nir_dest_bit_size(intr->dest) < 32 ?
1101 TYPE_U16 : TYPE_U32;
1102
1103 lod = create_immed(b, 0);
1104 sam = ir3_SAM(b, OPC_GETSIZE, dst_type, 0b1111, flags,
1105 samp_tex, lod, NULL);
1106
1107 /* Array size actually ends up in .w rather than .z. This doesn't
1108 * matter for miplevel 0, but for higher mips the value in z is
1109 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1110 * returned, which means that we have to add 1 to it for arrays for
1111 * a3xx.
1112 *
1113 * Note use a temporary dst and then copy, since the size of the dst
1114 * array that is passed in is based on nir's understanding of the
1115 * result size, not the hardware's
1116 */
1117 struct ir3_instruction *tmp[4];
1118
1119 ir3_split_dest(b, tmp, sam, 0, 4);
1120
1121 /* get_size instruction returns size in bytes instead of texels
1122 * for imageBuffer, so we need to divide it by the pixel size
1123 * of the image format.
1124 *
1125 * TODO: This is at least true on a5xx. Check other gens.
1126 */
1127 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF) {
1128 /* Since all the possible values the divisor can take are
1129 * power-of-two (4, 8, or 16), the division is implemented
1130 * as a shift-right.
1131 * During shader setup, the log2 of the image format's
1132 * bytes-per-pixel should have been emitted in 2nd slot of
1133 * image_dims. See ir3_shader::emit_image_dims().
1134 */
1135 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
1136 unsigned cb = regid(const_state->offsets.image_dims, 0) +
1137 const_state->image_dims.off[nir_src_as_uint(intr->src[0])];
1138 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1139
1140 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1141 }
1142
1143 for (unsigned i = 0; i < ncoords; i++)
1144 dst[i] = tmp[i];
1145
1146 if (flags & IR3_INSTR_A) {
1147 if (ctx->compiler->levels_add_one) {
1148 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1149 } else {
1150 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1151 }
1152 }
1153 }
1154
1155 static void
1156 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1157 {
1158 struct ir3_block *b = ctx->block;
1159 struct ir3_instruction *barrier;
1160
1161 switch (intr->intrinsic) {
1162 case nir_intrinsic_control_barrier:
1163 barrier = ir3_BAR(b);
1164 barrier->cat7.g = true;
1165 barrier->cat7.l = true;
1166 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1167 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1168 break;
1169 case nir_intrinsic_memory_barrier:
1170 barrier = ir3_FENCE(b);
1171 barrier->cat7.g = true;
1172 barrier->cat7.r = true;
1173 barrier->cat7.w = true;
1174 barrier->cat7.l = true;
1175 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1176 IR3_BARRIER_BUFFER_W;
1177 barrier->barrier_conflict =
1178 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1179 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1180 break;
1181 case nir_intrinsic_memory_barrier_buffer:
1182 barrier = ir3_FENCE(b);
1183 barrier->cat7.g = true;
1184 barrier->cat7.r = true;
1185 barrier->cat7.w = true;
1186 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1187 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1188 IR3_BARRIER_BUFFER_W;
1189 break;
1190 case nir_intrinsic_memory_barrier_image:
1191 // TODO double check if this should have .g set
1192 barrier = ir3_FENCE(b);
1193 barrier->cat7.g = true;
1194 barrier->cat7.r = true;
1195 barrier->cat7.w = true;
1196 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1197 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1198 IR3_BARRIER_IMAGE_W;
1199 break;
1200 case nir_intrinsic_memory_barrier_shared:
1201 barrier = ir3_FENCE(b);
1202 barrier->cat7.g = true;
1203 barrier->cat7.l = true;
1204 barrier->cat7.r = true;
1205 barrier->cat7.w = true;
1206 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1207 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1208 IR3_BARRIER_SHARED_W;
1209 break;
1210 case nir_intrinsic_group_memory_barrier:
1211 barrier = ir3_FENCE(b);
1212 barrier->cat7.g = true;
1213 barrier->cat7.l = true;
1214 barrier->cat7.r = true;
1215 barrier->cat7.w = true;
1216 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1217 IR3_BARRIER_IMAGE_W |
1218 IR3_BARRIER_BUFFER_W;
1219 barrier->barrier_conflict =
1220 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1221 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1222 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1223 break;
1224 default:
1225 unreachable("boo");
1226 }
1227
1228 /* make sure barrier doesn't get DCE'd */
1229 array_insert(b, b->keeps, barrier);
1230 }
1231
1232 static void add_sysval_input_compmask(struct ir3_context *ctx,
1233 gl_system_value slot, unsigned compmask,
1234 struct ir3_instruction *instr)
1235 {
1236 struct ir3_shader_variant *so = ctx->so;
1237 unsigned n = so->inputs_count++;
1238
1239 assert(instr->opc == OPC_META_INPUT);
1240 instr->input.inidx = n;
1241 instr->input.sysval = slot;
1242
1243 so->inputs[n].sysval = true;
1244 so->inputs[n].slot = slot;
1245 so->inputs[n].compmask = compmask;
1246 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1247 so->total_in++;
1248 }
1249
1250 static struct ir3_instruction *
1251 create_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1252 unsigned compmask)
1253 {
1254 assert(compmask);
1255 struct ir3_instruction *sysval = create_input(ctx, compmask);
1256 add_sysval_input_compmask(ctx, slot, compmask, sysval);
1257 return sysval;
1258 }
1259
1260 static struct ir3_instruction *
1261 get_barycentric_centroid(struct ir3_context *ctx)
1262 {
1263 if (!ctx->ij_centroid) {
1264 struct ir3_instruction *xy[2];
1265 struct ir3_instruction *ij;
1266
1267 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID, 0x3);
1268 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1269
1270 ctx->ij_centroid = ir3_create_collect(ctx, xy, 2);
1271 }
1272
1273 return ctx->ij_centroid;
1274 }
1275
1276 static struct ir3_instruction *
1277 get_barycentric_sample(struct ir3_context *ctx)
1278 {
1279 if (!ctx->ij_sample) {
1280 struct ir3_instruction *xy[2];
1281 struct ir3_instruction *ij;
1282
1283 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE, 0x3);
1284 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1285
1286 ctx->ij_sample = ir3_create_collect(ctx, xy, 2);
1287 }
1288
1289 return ctx->ij_sample;
1290 }
1291
1292 static struct ir3_instruction *
1293 get_barycentric_pixel(struct ir3_context *ctx)
1294 {
1295 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1296 * this to create ij_pixel only on demand:
1297 */
1298 return ctx->ij_pixel;
1299 }
1300
1301 static struct ir3_instruction *
1302 get_frag_coord(struct ir3_context *ctx)
1303 {
1304 if (!ctx->frag_coord) {
1305 struct ir3_block *b = ctx->in_block;
1306 struct ir3_instruction *xyzw[4];
1307 struct ir3_instruction *hw_frag_coord;
1308
1309 hw_frag_coord = create_sysval_input(ctx, SYSTEM_VALUE_FRAG_COORD, 0xf);
1310 ir3_split_dest(b, xyzw, hw_frag_coord, 0, 4);
1311
1312 /* for frag_coord.xy, we get unsigned values.. we need
1313 * to subtract (integer) 8 and divide by 16 (right-
1314 * shift by 4) then convert to float:
1315 *
1316 * sub.s tmp, src, 8
1317 * shr.b tmp, tmp, 4
1318 * mov.u32f32 dst, tmp
1319 *
1320 */
1321 for (int i = 0; i < 2; i++) {
1322 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1323 xyzw[i] = ir3_MUL_F(b, xyzw[i], 0, create_immed(b, fui(1.0 / 16.0)), 0);
1324 }
1325
1326 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1327 ctx->so->frag_coord = true;
1328 }
1329
1330 return ctx->frag_coord;
1331 }
1332
1333 static void
1334 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1335 {
1336 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1337 struct ir3_instruction **dst;
1338 struct ir3_instruction * const *src;
1339 struct ir3_block *b = ctx->block;
1340 int idx, comp;
1341
1342 if (info->has_dest) {
1343 unsigned n = nir_intrinsic_dest_components(intr);
1344 dst = ir3_get_dst(ctx, &intr->dest, n);
1345 } else {
1346 dst = NULL;
1347 }
1348
1349 const unsigned primitive_param = ctx->so->shader->const_state.offsets.primitive_param * 4;
1350 const unsigned primitive_map = ctx->so->shader->const_state.offsets.primitive_map * 4;
1351
1352 switch (intr->intrinsic) {
1353 case nir_intrinsic_load_uniform:
1354 idx = nir_intrinsic_base(intr);
1355 if (nir_src_is_const(intr->src[0])) {
1356 idx += nir_src_as_uint(intr->src[0]);
1357 for (int i = 0; i < intr->num_components; i++) {
1358 dst[i] = create_uniform_typed(b, idx + i,
1359 nir_dest_bit_size(intr->dest) < 32 ? TYPE_F16 : TYPE_F32);
1360 }
1361 } else {
1362 src = ir3_get_src(ctx, &intr->src[0]);
1363 for (int i = 0; i < intr->num_components; i++) {
1364 dst[i] = create_uniform_indirect(b, idx + i,
1365 ir3_get_addr(ctx, src[0], 1));
1366 }
1367 /* NOTE: if relative addressing is used, we set
1368 * constlen in the compiler (to worst-case value)
1369 * since we don't know in the assembler what the max
1370 * addr reg value can be:
1371 */
1372 ctx->so->constlen = MAX2(ctx->so->constlen,
1373 ctx->so->shader->ubo_state.size / 16);
1374 }
1375 break;
1376
1377 case nir_intrinsic_load_vs_primitive_stride_ir3:
1378 dst[0] = create_uniform(b, primitive_param + 0);
1379 break;
1380 case nir_intrinsic_load_vs_vertex_stride_ir3:
1381 dst[0] = create_uniform(b, primitive_param + 1);
1382 break;
1383 case nir_intrinsic_load_hs_patch_stride_ir3:
1384 dst[0] = create_uniform(b, primitive_param + 2);
1385 break;
1386 case nir_intrinsic_load_patch_vertices_in:
1387 dst[0] = create_uniform(b, primitive_param + 3);
1388 break;
1389 case nir_intrinsic_load_tess_param_base_ir3:
1390 dst[0] = create_uniform(b, primitive_param + 4);
1391 dst[1] = create_uniform(b, primitive_param + 5);
1392 break;
1393 case nir_intrinsic_load_tess_factor_base_ir3:
1394 dst[0] = create_uniform(b, primitive_param + 6);
1395 dst[1] = create_uniform(b, primitive_param + 7);
1396 break;
1397
1398 case nir_intrinsic_load_primitive_location_ir3:
1399 idx = nir_intrinsic_driver_location(intr);
1400 dst[0] = create_uniform(b, primitive_map + idx);
1401 break;
1402
1403 case nir_intrinsic_load_gs_header_ir3:
1404 dst[0] = ctx->gs_header;
1405 break;
1406 case nir_intrinsic_load_tcs_header_ir3:
1407 dst[0] = ctx->tcs_header;
1408 break;
1409
1410 case nir_intrinsic_load_primitive_id:
1411 dst[0] = ctx->primitive_id;
1412 break;
1413
1414 case nir_intrinsic_load_tess_coord:
1415 if (!ctx->tess_coord) {
1416 ctx->tess_coord =
1417 create_sysval_input(ctx, SYSTEM_VALUE_TESS_COORD, 0x3);
1418 }
1419 ir3_split_dest(b, dst, ctx->tess_coord, 0, 2);
1420
1421 /* Unused, but ir3_put_dst() below wants to free something */
1422 dst[2] = create_immed(b, 0);
1423 break;
1424
1425 case nir_intrinsic_end_patch_ir3:
1426 assert(ctx->so->type == MESA_SHADER_TESS_CTRL);
1427 struct ir3_instruction *end = ir3_ENDIF(b);
1428 array_insert(b, b->keeps, end);
1429
1430 end->barrier_class = IR3_BARRIER_EVERYTHING;
1431 end->barrier_conflict = IR3_BARRIER_EVERYTHING;
1432 break;
1433
1434 case nir_intrinsic_store_global_ir3: {
1435 struct ir3_instruction *value, *addr, *offset;
1436
1437 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1438 ir3_get_src(ctx, &intr->src[1])[0],
1439 ir3_get_src(ctx, &intr->src[1])[1]
1440 }, 2);
1441
1442 offset = ir3_get_src(ctx, &intr->src[2])[0];
1443
1444 value = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]),
1445 intr->num_components);
1446
1447 struct ir3_instruction *stg =
1448 ir3_STG_G(ctx->block, addr, 0, value, 0,
1449 create_immed(ctx->block, intr->num_components), 0, offset, 0);
1450 stg->cat6.type = TYPE_U32;
1451 stg->cat6.iim_val = 1;
1452
1453 array_insert(b, b->keeps, stg);
1454
1455 stg->barrier_class = IR3_BARRIER_BUFFER_W;
1456 stg->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1457 break;
1458 }
1459
1460 case nir_intrinsic_load_global_ir3: {
1461 struct ir3_instruction *addr, *offset;
1462
1463 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1464 ir3_get_src(ctx, &intr->src[0])[0],
1465 ir3_get_src(ctx, &intr->src[0])[1]
1466 }, 2);
1467
1468 offset = ir3_get_src(ctx, &intr->src[1])[0];
1469
1470 struct ir3_instruction *load =
1471 ir3_LDG(b, addr, 0, create_immed(ctx->block, intr->num_components),
1472 0, offset, 0);
1473 load->cat6.type = TYPE_U32;
1474 load->regs[0]->wrmask = MASK(intr->num_components);
1475
1476 load->barrier_class = IR3_BARRIER_BUFFER_R;
1477 load->barrier_conflict = IR3_BARRIER_BUFFER_W;
1478
1479 ir3_split_dest(b, dst, load, 0, intr->num_components);
1480 break;
1481 }
1482
1483 case nir_intrinsic_load_ubo:
1484 emit_intrinsic_load_ubo(ctx, intr, dst);
1485 break;
1486 case nir_intrinsic_load_frag_coord:
1487 ir3_split_dest(b, dst, get_frag_coord(ctx), 0, 4);
1488 break;
1489 case nir_intrinsic_load_sample_pos_from_id: {
1490 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1491 * but that doesn't seem necessary.
1492 */
1493 struct ir3_instruction *offset =
1494 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1495 offset->regs[0]->wrmask = 0x3;
1496 offset->cat5.type = TYPE_F32;
1497
1498 ir3_split_dest(b, dst, offset, 0, 2);
1499
1500 break;
1501 }
1502 case nir_intrinsic_load_size_ir3:
1503 if (!ctx->ij_size) {
1504 ctx->ij_size =
1505 create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE, 0x1);
1506 }
1507 dst[0] = ctx->ij_size;
1508 break;
1509 case nir_intrinsic_load_barycentric_centroid:
1510 ir3_split_dest(b, dst, get_barycentric_centroid(ctx), 0, 2);
1511 break;
1512 case nir_intrinsic_load_barycentric_sample:
1513 if (ctx->so->key.msaa) {
1514 ir3_split_dest(b, dst, get_barycentric_sample(ctx), 0, 2);
1515 } else {
1516 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1517 }
1518 break;
1519 case nir_intrinsic_load_barycentric_pixel:
1520 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1521 break;
1522 case nir_intrinsic_load_interpolated_input:
1523 idx = nir_intrinsic_base(intr);
1524 comp = nir_intrinsic_component(intr);
1525 src = ir3_get_src(ctx, &intr->src[0]);
1526 if (nir_src_is_const(intr->src[1])) {
1527 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1528 idx += nir_src_as_uint(intr->src[1]);
1529 for (int i = 0; i < intr->num_components; i++) {
1530 unsigned inloc = idx * 4 + i + comp;
1531 if (ctx->so->inputs[idx].bary &&
1532 !ctx->so->inputs[idx].use_ldlv) {
1533 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1534 } else {
1535 /* for non-varyings use the pre-setup input, since
1536 * that is easier than mapping things back to a
1537 * nir_variable to figure out what it is.
1538 */
1539 dst[i] = ctx->inputs[inloc];
1540 compile_assert(ctx, dst[i]);
1541 }
1542 }
1543 } else {
1544 ir3_context_error(ctx, "unhandled");
1545 }
1546 break;
1547 case nir_intrinsic_load_input:
1548 idx = nir_intrinsic_base(intr);
1549 comp = nir_intrinsic_component(intr);
1550 if (nir_src_is_const(intr->src[0])) {
1551 idx += nir_src_as_uint(intr->src[0]);
1552 for (int i = 0; i < intr->num_components; i++) {
1553 unsigned n = idx * 4 + i + comp;
1554 dst[i] = ctx->inputs[n];
1555 compile_assert(ctx, ctx->inputs[n]);
1556 }
1557 } else {
1558 src = ir3_get_src(ctx, &intr->src[0]);
1559 struct ir3_instruction *collect =
1560 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ninputs);
1561 struct ir3_instruction *addr = ir3_get_addr(ctx, src[0], 4);
1562 for (int i = 0; i < intr->num_components; i++) {
1563 unsigned n = idx * 4 + i + comp;
1564 dst[i] = create_indirect_load(ctx, ctx->ninputs,
1565 n, addr, collect);
1566 }
1567 }
1568 break;
1569 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1570 * pass and replaced by an ir3-specifc version that adds the
1571 * dword-offset in the last source.
1572 */
1573 case nir_intrinsic_load_ssbo_ir3:
1574 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1575 break;
1576 case nir_intrinsic_store_ssbo_ir3:
1577 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1578 !ctx->s->info.fs.early_fragment_tests)
1579 ctx->so->no_earlyz = true;
1580 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1581 break;
1582 case nir_intrinsic_get_buffer_size:
1583 emit_intrinsic_ssbo_size(ctx, intr, dst);
1584 break;
1585 case nir_intrinsic_ssbo_atomic_add_ir3:
1586 case nir_intrinsic_ssbo_atomic_imin_ir3:
1587 case nir_intrinsic_ssbo_atomic_umin_ir3:
1588 case nir_intrinsic_ssbo_atomic_imax_ir3:
1589 case nir_intrinsic_ssbo_atomic_umax_ir3:
1590 case nir_intrinsic_ssbo_atomic_and_ir3:
1591 case nir_intrinsic_ssbo_atomic_or_ir3:
1592 case nir_intrinsic_ssbo_atomic_xor_ir3:
1593 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1594 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1595 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1596 !ctx->s->info.fs.early_fragment_tests)
1597 ctx->so->no_earlyz = true;
1598 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1599 break;
1600 case nir_intrinsic_load_shared:
1601 emit_intrinsic_load_shared(ctx, intr, dst);
1602 break;
1603 case nir_intrinsic_store_shared:
1604 emit_intrinsic_store_shared(ctx, intr);
1605 break;
1606 case nir_intrinsic_shared_atomic_add:
1607 case nir_intrinsic_shared_atomic_imin:
1608 case nir_intrinsic_shared_atomic_umin:
1609 case nir_intrinsic_shared_atomic_imax:
1610 case nir_intrinsic_shared_atomic_umax:
1611 case nir_intrinsic_shared_atomic_and:
1612 case nir_intrinsic_shared_atomic_or:
1613 case nir_intrinsic_shared_atomic_xor:
1614 case nir_intrinsic_shared_atomic_exchange:
1615 case nir_intrinsic_shared_atomic_comp_swap:
1616 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1617 break;
1618 case nir_intrinsic_image_load:
1619 emit_intrinsic_load_image(ctx, intr, dst);
1620 break;
1621 case nir_intrinsic_image_store:
1622 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1623 !ctx->s->info.fs.early_fragment_tests)
1624 ctx->so->no_earlyz = true;
1625 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1626 break;
1627 case nir_intrinsic_image_size:
1628 emit_intrinsic_image_size(ctx, intr, dst);
1629 break;
1630 case nir_intrinsic_image_atomic_add:
1631 case nir_intrinsic_image_atomic_imin:
1632 case nir_intrinsic_image_atomic_umin:
1633 case nir_intrinsic_image_atomic_imax:
1634 case nir_intrinsic_image_atomic_umax:
1635 case nir_intrinsic_image_atomic_and:
1636 case nir_intrinsic_image_atomic_or:
1637 case nir_intrinsic_image_atomic_xor:
1638 case nir_intrinsic_image_atomic_exchange:
1639 case nir_intrinsic_image_atomic_comp_swap:
1640 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1641 !ctx->s->info.fs.early_fragment_tests)
1642 ctx->so->no_earlyz = true;
1643 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1644 break;
1645 case nir_intrinsic_control_barrier:
1646 case nir_intrinsic_memory_barrier:
1647 case nir_intrinsic_group_memory_barrier:
1648 case nir_intrinsic_memory_barrier_buffer:
1649 case nir_intrinsic_memory_barrier_image:
1650 case nir_intrinsic_memory_barrier_shared:
1651 emit_intrinsic_barrier(ctx, intr);
1652 /* note that blk ptr no longer valid, make that obvious: */
1653 b = NULL;
1654 break;
1655 case nir_intrinsic_store_output:
1656 idx = nir_intrinsic_base(intr);
1657 comp = nir_intrinsic_component(intr);
1658 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1659 idx += nir_src_as_uint(intr->src[1]);
1660
1661 src = ir3_get_src(ctx, &intr->src[0]);
1662 for (int i = 0; i < intr->num_components; i++) {
1663 unsigned n = idx * 4 + i + comp;
1664 ctx->outputs[n] = src[i];
1665 }
1666 break;
1667 case nir_intrinsic_load_base_vertex:
1668 case nir_intrinsic_load_first_vertex:
1669 if (!ctx->basevertex) {
1670 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1671 }
1672 dst[0] = ctx->basevertex;
1673 break;
1674 case nir_intrinsic_load_base_instance:
1675 if (!ctx->base_instance) {
1676 ctx->base_instance = create_driver_param(ctx, IR3_DP_INSTID_BASE);
1677 }
1678 dst[0] = ctx->base_instance;
1679 break;
1680 case nir_intrinsic_load_vertex_id_zero_base:
1681 case nir_intrinsic_load_vertex_id:
1682 if (!ctx->vertex_id) {
1683 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1684 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1685 ctx->vertex_id = create_sysval_input(ctx, sv, 0x1);
1686 }
1687 dst[0] = ctx->vertex_id;
1688 break;
1689 case nir_intrinsic_load_instance_id:
1690 if (!ctx->instance_id) {
1691 ctx->instance_id = create_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID, 0x1);
1692 }
1693 dst[0] = ctx->instance_id;
1694 break;
1695 case nir_intrinsic_load_sample_id:
1696 ctx->so->per_samp = true;
1697 /* fall-thru */
1698 case nir_intrinsic_load_sample_id_no_per_sample:
1699 if (!ctx->samp_id) {
1700 ctx->samp_id = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID, 0x1);
1701 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1702 }
1703 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1704 break;
1705 case nir_intrinsic_load_sample_mask_in:
1706 if (!ctx->samp_mask_in) {
1707 ctx->samp_mask_in = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN, 0x1);
1708 }
1709 dst[0] = ctx->samp_mask_in;
1710 break;
1711 case nir_intrinsic_load_user_clip_plane:
1712 idx = nir_intrinsic_ucp_id(intr);
1713 for (int i = 0; i < intr->num_components; i++) {
1714 unsigned n = idx * 4 + i;
1715 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1716 }
1717 break;
1718 case nir_intrinsic_load_front_face:
1719 if (!ctx->frag_face) {
1720 ctx->so->frag_face = true;
1721 ctx->frag_face = create_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, 0x1);
1722 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1723 }
1724 /* for fragface, we get -1 for back and 0 for front. However this is
1725 * the inverse of what nir expects (where ~0 is true).
1726 */
1727 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1728 dst[0] = ir3_NOT_B(b, dst[0], 0);
1729 break;
1730 case nir_intrinsic_load_local_invocation_id:
1731 if (!ctx->local_invocation_id) {
1732 ctx->local_invocation_id =
1733 create_sysval_input(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID, 0x7);
1734 }
1735 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1736 break;
1737 case nir_intrinsic_load_work_group_id:
1738 if (!ctx->work_group_id) {
1739 ctx->work_group_id =
1740 create_sysval_input(ctx, SYSTEM_VALUE_WORK_GROUP_ID, 0x7);
1741 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1742 }
1743 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1744 break;
1745 case nir_intrinsic_load_num_work_groups:
1746 for (int i = 0; i < intr->num_components; i++) {
1747 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1748 }
1749 break;
1750 case nir_intrinsic_load_local_group_size:
1751 for (int i = 0; i < intr->num_components; i++) {
1752 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1753 }
1754 break;
1755 case nir_intrinsic_discard_if:
1756 case nir_intrinsic_discard: {
1757 struct ir3_instruction *cond, *kill;
1758
1759 if (intr->intrinsic == nir_intrinsic_discard_if) {
1760 /* conditional discard: */
1761 src = ir3_get_src(ctx, &intr->src[0]);
1762 cond = ir3_b2n(b, src[0]);
1763 } else {
1764 /* unconditional discard: */
1765 cond = create_immed(b, 1);
1766 }
1767
1768 /* NOTE: only cmps.*.* can write p0.x: */
1769 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1770 cond->cat2.condition = IR3_COND_NE;
1771
1772 /* condition always goes in predicate register: */
1773 cond->regs[0]->num = regid(REG_P0, 0);
1774 cond->regs[0]->flags &= ~IR3_REG_SSA;
1775
1776 kill = ir3_KILL(b, cond, 0);
1777 kill->regs[1]->num = regid(REG_P0, 0);
1778 array_insert(ctx->ir, ctx->ir->predicates, kill);
1779
1780 array_insert(b, b->keeps, kill);
1781 ctx->so->no_earlyz = true;
1782
1783 break;
1784 }
1785
1786 case nir_intrinsic_cond_end_ir3: {
1787 struct ir3_instruction *cond, *kill;
1788
1789 src = ir3_get_src(ctx, &intr->src[0]);
1790 cond = ir3_b2n(b, src[0]);
1791
1792 /* NOTE: only cmps.*.* can write p0.x: */
1793 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1794 cond->cat2.condition = IR3_COND_NE;
1795
1796 /* condition always goes in predicate register: */
1797 cond->regs[0]->num = regid(REG_P0, 0);
1798
1799 kill = ir3_IF(b, cond, 0);
1800
1801 kill->barrier_class = IR3_BARRIER_EVERYTHING;
1802 kill->barrier_conflict = IR3_BARRIER_EVERYTHING;
1803
1804 array_insert(ctx->ir, ctx->ir->predicates, kill);
1805 array_insert(b, b->keeps, kill);
1806 break;
1807 }
1808
1809 case nir_intrinsic_load_shared_ir3:
1810 emit_intrinsic_load_shared_ir3(ctx, intr, dst);
1811 break;
1812 case nir_intrinsic_store_shared_ir3:
1813 emit_intrinsic_store_shared_ir3(ctx, intr);
1814 break;
1815 default:
1816 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1817 nir_intrinsic_infos[intr->intrinsic].name);
1818 break;
1819 }
1820
1821 if (info->has_dest)
1822 ir3_put_dst(ctx, &intr->dest);
1823 }
1824
1825 static void
1826 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1827 {
1828 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1829 instr->def.num_components);
1830
1831 if (instr->def.bit_size < 32) {
1832 for (int i = 0; i < instr->def.num_components; i++)
1833 dst[i] = create_immed_typed(ctx->block,
1834 instr->value[i].u16,
1835 TYPE_U16);
1836 } else {
1837 for (int i = 0; i < instr->def.num_components; i++)
1838 dst[i] = create_immed_typed(ctx->block,
1839 instr->value[i].u32,
1840 TYPE_U32);
1841 }
1842
1843 }
1844
1845 static void
1846 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1847 {
1848 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1849 undef->def.num_components);
1850 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1851
1852 /* backend doesn't want undefined instructions, so just plug
1853 * in 0.0..
1854 */
1855 for (int i = 0; i < undef->def.num_components; i++)
1856 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1857 }
1858
1859 /*
1860 * texture fetch/sample instructions:
1861 */
1862
1863 static type_t
1864 get_tex_dest_type(nir_tex_instr *tex)
1865 {
1866 type_t type;
1867
1868 switch (nir_alu_type_get_base_type(tex->dest_type)) {
1869 case nir_type_invalid:
1870 case nir_type_float:
1871 type = nir_dest_bit_size(tex->dest) < 32 ? TYPE_F16 : TYPE_F32;
1872 break;
1873 case nir_type_int:
1874 type = nir_dest_bit_size(tex->dest) < 32 ? TYPE_S16 : TYPE_S32;
1875 break;
1876 case nir_type_uint:
1877 case nir_type_bool:
1878 type = nir_dest_bit_size(tex->dest) < 32 ? TYPE_U16 : TYPE_U32;
1879 break;
1880 default:
1881 unreachable("bad dest_type");
1882 }
1883
1884 return type;
1885 }
1886
1887 static void
1888 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1889 {
1890 unsigned coords = glsl_get_sampler_dim_coordinate_components(tex->sampler_dim);
1891 unsigned flags = 0;
1892
1893 /* note: would use tex->coord_components.. except txs.. also,
1894 * since array index goes after shadow ref, we don't want to
1895 * count it:
1896 */
1897 if (coords == 3)
1898 flags |= IR3_INSTR_3D;
1899
1900 if (tex->is_shadow && tex->op != nir_texop_lod)
1901 flags |= IR3_INSTR_S;
1902
1903 if (tex->is_array && tex->op != nir_texop_lod)
1904 flags |= IR3_INSTR_A;
1905
1906 *flagsp = flags;
1907 *coordsp = coords;
1908 }
1909
1910 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
1911 * or immediate (in which case it will get lowered later to a non .s2en
1912 * version of the tex instruction which encode tex/samp as immediates:
1913 */
1914 static struct ir3_instruction *
1915 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
1916 {
1917 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
1918 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
1919 struct ir3_instruction *texture, *sampler;
1920
1921 if (texture_idx >= 0) {
1922 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
1923 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
1924 } else {
1925 /* TODO what to do for dynamic case? I guess we only need the
1926 * max index for astc srgb workaround so maybe not a problem
1927 * to worry about if we don't enable indirect samplers for
1928 * a4xx?
1929 */
1930 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
1931 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
1932 }
1933
1934 if (sampler_idx >= 0) {
1935 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
1936 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
1937 } else {
1938 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
1939 }
1940
1941 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1942 sampler,
1943 texture,
1944 }, 2);
1945 }
1946
1947 static void
1948 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
1949 {
1950 struct ir3_block *b = ctx->block;
1951 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1952 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
1953 struct ir3_instruction *lod, *compare, *proj, *sample_index;
1954 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1955 unsigned i, coords, flags, ncomp;
1956 unsigned nsrc0 = 0, nsrc1 = 0;
1957 type_t type;
1958 opc_t opc = 0;
1959
1960 ncomp = nir_dest_num_components(tex->dest);
1961
1962 coord = off = ddx = ddy = NULL;
1963 lod = proj = compare = sample_index = NULL;
1964
1965 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
1966
1967 for (unsigned i = 0; i < tex->num_srcs; i++) {
1968 switch (tex->src[i].src_type) {
1969 case nir_tex_src_coord:
1970 coord = ir3_get_src(ctx, &tex->src[i].src);
1971 break;
1972 case nir_tex_src_bias:
1973 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1974 has_bias = true;
1975 break;
1976 case nir_tex_src_lod:
1977 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1978 has_lod = true;
1979 break;
1980 case nir_tex_src_comparator: /* shadow comparator */
1981 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
1982 break;
1983 case nir_tex_src_projector:
1984 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
1985 has_proj = true;
1986 break;
1987 case nir_tex_src_offset:
1988 off = ir3_get_src(ctx, &tex->src[i].src);
1989 has_off = true;
1990 break;
1991 case nir_tex_src_ddx:
1992 ddx = ir3_get_src(ctx, &tex->src[i].src);
1993 break;
1994 case nir_tex_src_ddy:
1995 ddy = ir3_get_src(ctx, &tex->src[i].src);
1996 break;
1997 case nir_tex_src_ms_index:
1998 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
1999 break;
2000 case nir_tex_src_texture_offset:
2001 case nir_tex_src_sampler_offset:
2002 /* handled in get_tex_samp_src() */
2003 break;
2004 default:
2005 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
2006 tex->src[i].src_type);
2007 return;
2008 }
2009 }
2010
2011 switch (tex->op) {
2012 case nir_texop_tex_prefetch:
2013 compile_assert(ctx, !has_bias);
2014 compile_assert(ctx, !has_lod);
2015 compile_assert(ctx, !compare);
2016 compile_assert(ctx, !has_proj);
2017 compile_assert(ctx, !has_off);
2018 compile_assert(ctx, !ddx);
2019 compile_assert(ctx, !ddy);
2020 compile_assert(ctx, !sample_index);
2021 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_texture_offset) < 0);
2022 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset) < 0);
2023
2024 if (ctx->so->num_sampler_prefetch < IR3_MAX_SAMPLER_PREFETCH) {
2025 opc = OPC_META_TEX_PREFETCH;
2026 ctx->so->num_sampler_prefetch++;
2027 break;
2028 }
2029 /* fallthru */
2030 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
2031 case nir_texop_txb: opc = OPC_SAMB; break;
2032 case nir_texop_txl: opc = OPC_SAML; break;
2033 case nir_texop_txd: opc = OPC_SAMGQ; break;
2034 case nir_texop_txf: opc = OPC_ISAML; break;
2035 case nir_texop_lod: opc = OPC_GETLOD; break;
2036 case nir_texop_tg4:
2037 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2038 * what blob does, seems gather is broken?), and a3xx did
2039 * not support it (but probably could also emulate).
2040 */
2041 switch (tex->component) {
2042 case 0: opc = OPC_GATHER4R; break;
2043 case 1: opc = OPC_GATHER4G; break;
2044 case 2: opc = OPC_GATHER4B; break;
2045 case 3: opc = OPC_GATHER4A; break;
2046 }
2047 break;
2048 case nir_texop_txf_ms_fb:
2049 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
2050 default:
2051 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
2052 return;
2053 }
2054
2055 tex_info(tex, &flags, &coords);
2056
2057 /*
2058 * lay out the first argument in the proper order:
2059 * - actual coordinates first
2060 * - shadow reference
2061 * - array index
2062 * - projection w
2063 * - starting at offset 4, dpdx.xy, dpdy.xy
2064 *
2065 * bias/lod go into the second arg
2066 */
2067
2068 /* insert tex coords: */
2069 for (i = 0; i < coords; i++)
2070 src0[i] = coord[i];
2071
2072 nsrc0 = i;
2073
2074 /* scale up integer coords for TXF based on the LOD */
2075 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
2076 assert(has_lod);
2077 for (i = 0; i < coords; i++)
2078 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
2079 }
2080
2081 if (coords == 1) {
2082 /* hw doesn't do 1d, so we treat it as 2d with
2083 * height of 1, and patch up the y coord.
2084 */
2085 if (is_isam(opc)) {
2086 src0[nsrc0++] = create_immed(b, 0);
2087 } else {
2088 src0[nsrc0++] = create_immed(b, fui(0.5));
2089 }
2090 }
2091
2092 if (tex->is_shadow && tex->op != nir_texop_lod)
2093 src0[nsrc0++] = compare;
2094
2095 if (tex->is_array && tex->op != nir_texop_lod) {
2096 struct ir3_instruction *idx = coord[coords];
2097
2098 /* the array coord for cube arrays needs 0.5 added to it */
2099 if (ctx->compiler->array_index_add_half && !is_isam(opc))
2100 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
2101
2102 src0[nsrc0++] = idx;
2103 }
2104
2105 if (has_proj) {
2106 src0[nsrc0++] = proj;
2107 flags |= IR3_INSTR_P;
2108 }
2109
2110 /* pad to 4, then ddx/ddy: */
2111 if (tex->op == nir_texop_txd) {
2112 while (nsrc0 < 4)
2113 src0[nsrc0++] = create_immed(b, fui(0.0));
2114 for (i = 0; i < coords; i++)
2115 src0[nsrc0++] = ddx[i];
2116 if (coords < 2)
2117 src0[nsrc0++] = create_immed(b, fui(0.0));
2118 for (i = 0; i < coords; i++)
2119 src0[nsrc0++] = ddy[i];
2120 if (coords < 2)
2121 src0[nsrc0++] = create_immed(b, fui(0.0));
2122 }
2123
2124 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2125 * with scaled x coord according to requested sample:
2126 */
2127 if (opc == OPC_ISAMM) {
2128 if (ctx->compiler->txf_ms_with_isaml) {
2129 /* the samples are laid out in x dimension as
2130 * 0 1 2 3
2131 * x_ms = (x << ms) + sample_index;
2132 */
2133 struct ir3_instruction *ms;
2134 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
2135
2136 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
2137 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
2138
2139 opc = OPC_ISAML;
2140 } else {
2141 src0[nsrc0++] = sample_index;
2142 }
2143 }
2144
2145 /*
2146 * second argument (if applicable):
2147 * - offsets
2148 * - lod
2149 * - bias
2150 */
2151 if (has_off | has_lod | has_bias) {
2152 if (has_off) {
2153 unsigned off_coords = coords;
2154 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2155 off_coords--;
2156 for (i = 0; i < off_coords; i++)
2157 src1[nsrc1++] = off[i];
2158 if (off_coords < 2)
2159 src1[nsrc1++] = create_immed(b, fui(0.0));
2160 flags |= IR3_INSTR_O;
2161 }
2162
2163 if (has_lod | has_bias)
2164 src1[nsrc1++] = lod;
2165 }
2166
2167 type = get_tex_dest_type(tex);
2168
2169 if (opc == OPC_GETLOD)
2170 type = TYPE_S32;
2171
2172 struct ir3_instruction *samp_tex;
2173
2174 if (tex->op == nir_texop_txf_ms_fb) {
2175 /* only expect a single txf_ms_fb per shader: */
2176 compile_assert(ctx, !ctx->so->fb_read);
2177 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
2178
2179 ctx->so->fb_read = true;
2180 samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2181 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2182 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2183 }, 2);
2184
2185 ctx->so->num_samp++;
2186 } else {
2187 samp_tex = get_tex_samp_tex_src(ctx, tex);
2188 }
2189
2190 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
2191 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
2192
2193 if (opc == OPC_META_TEX_PREFETCH) {
2194 int idx = nir_tex_instr_src_index(tex, nir_tex_src_coord);
2195
2196 compile_assert(ctx, tex->src[idx].src.is_ssa);
2197
2198 sam = ir3_META_TEX_PREFETCH(b);
2199 __ssa_dst(sam)->wrmask = MASK(ncomp); /* dst */
2200 sam->prefetch.input_offset =
2201 ir3_nir_coord_offset(tex->src[idx].src.ssa);
2202 sam->prefetch.tex = tex->texture_index;
2203 sam->prefetch.samp = tex->sampler_index;
2204 } else {
2205 sam = ir3_SAM(b, opc, type, MASK(ncomp), flags,
2206 samp_tex, col0, col1);
2207 }
2208
2209 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
2210 assert(opc != OPC_META_TEX_PREFETCH);
2211
2212 /* only need first 3 components: */
2213 sam->regs[0]->wrmask = 0x7;
2214 ir3_split_dest(b, dst, sam, 0, 3);
2215
2216 /* we need to sample the alpha separately with a non-ASTC
2217 * texture state:
2218 */
2219 sam = ir3_SAM(b, opc, type, 0b1000, flags,
2220 samp_tex, col0, col1);
2221
2222 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
2223
2224 /* fixup .w component: */
2225 ir3_split_dest(b, &dst[3], sam, 3, 1);
2226 } else {
2227 /* normal (non-workaround) case: */
2228 ir3_split_dest(b, dst, sam, 0, ncomp);
2229 }
2230
2231 /* GETLOD returns results in 4.8 fixed point */
2232 if (opc == OPC_GETLOD) {
2233 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
2234
2235 compile_assert(ctx, tex->dest_type == nir_type_float);
2236 for (i = 0; i < 2; i++) {
2237 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_S32, TYPE_F32), 0,
2238 factor, 0);
2239 }
2240 }
2241
2242 ir3_put_dst(ctx, &tex->dest);
2243 }
2244
2245 static void
2246 emit_tex_info(struct ir3_context *ctx, nir_tex_instr *tex, unsigned idx)
2247 {
2248 struct ir3_block *b = ctx->block;
2249 struct ir3_instruction **dst, *sam;
2250 type_t dst_type = get_tex_dest_type(tex);
2251
2252 dst = ir3_get_dst(ctx, &tex->dest, 1);
2253
2254 sam = ir3_SAM(b, OPC_GETINFO, dst_type, 1 << idx, 0,
2255 get_tex_samp_tex_src(ctx, tex), NULL, NULL);
2256
2257 /* even though there is only one component, since it ends
2258 * up in .y/.z/.w rather than .x, we need a split_dest()
2259 */
2260 if (idx)
2261 ir3_split_dest(b, dst, sam, 0, idx + 1);
2262
2263 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2264 * the value in TEX_CONST_0 is zero-based.
2265 */
2266 if (ctx->compiler->levels_add_one)
2267 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2268
2269 ir3_put_dst(ctx, &tex->dest);
2270 }
2271
2272 static void
2273 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2274 {
2275 struct ir3_block *b = ctx->block;
2276 struct ir3_instruction **dst, *sam;
2277 struct ir3_instruction *lod;
2278 unsigned flags, coords;
2279 type_t dst_type = get_tex_dest_type(tex);
2280
2281 tex_info(tex, &flags, &coords);
2282
2283 /* Actually we want the number of dimensions, not coordinates. This
2284 * distinction only matters for cubes.
2285 */
2286 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2287 coords = 2;
2288
2289 dst = ir3_get_dst(ctx, &tex->dest, 4);
2290
2291 compile_assert(ctx, tex->num_srcs == 1);
2292 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
2293
2294 lod = ir3_get_src(ctx, &tex->src[0].src)[0];
2295
2296 sam = ir3_SAM(b, OPC_GETSIZE, dst_type, 0b1111, flags,
2297 get_tex_samp_tex_src(ctx, tex), lod, NULL);
2298
2299 ir3_split_dest(b, dst, sam, 0, 4);
2300
2301 /* Array size actually ends up in .w rather than .z. This doesn't
2302 * matter for miplevel 0, but for higher mips the value in z is
2303 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2304 * returned, which means that we have to add 1 to it for arrays.
2305 */
2306 if (tex->is_array) {
2307 if (ctx->compiler->levels_add_one) {
2308 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2309 } else {
2310 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2311 }
2312 }
2313
2314 ir3_put_dst(ctx, &tex->dest);
2315 }
2316
2317 static void
2318 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2319 {
2320 switch (jump->type) {
2321 case nir_jump_break:
2322 case nir_jump_continue:
2323 case nir_jump_return:
2324 /* I *think* we can simply just ignore this, and use the
2325 * successor block link to figure out where we need to
2326 * jump to for break/continue
2327 */
2328 break;
2329 default:
2330 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2331 break;
2332 }
2333 }
2334
2335 static void
2336 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2337 {
2338 switch (instr->type) {
2339 case nir_instr_type_alu:
2340 emit_alu(ctx, nir_instr_as_alu(instr));
2341 break;
2342 case nir_instr_type_deref:
2343 /* ignored, handled as part of the intrinsic they are src to */
2344 break;
2345 case nir_instr_type_intrinsic:
2346 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2347 break;
2348 case nir_instr_type_load_const:
2349 emit_load_const(ctx, nir_instr_as_load_const(instr));
2350 break;
2351 case nir_instr_type_ssa_undef:
2352 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2353 break;
2354 case nir_instr_type_tex: {
2355 nir_tex_instr *tex = nir_instr_as_tex(instr);
2356 /* couple tex instructions get special-cased:
2357 */
2358 switch (tex->op) {
2359 case nir_texop_txs:
2360 emit_tex_txs(ctx, tex);
2361 break;
2362 case nir_texop_query_levels:
2363 emit_tex_info(ctx, tex, 2);
2364 break;
2365 case nir_texop_texture_samples:
2366 emit_tex_info(ctx, tex, 3);
2367 break;
2368 default:
2369 emit_tex(ctx, tex);
2370 break;
2371 }
2372 break;
2373 }
2374 case nir_instr_type_jump:
2375 emit_jump(ctx, nir_instr_as_jump(instr));
2376 break;
2377 case nir_instr_type_phi:
2378 /* we have converted phi webs to regs in NIR by now */
2379 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2380 break;
2381 case nir_instr_type_call:
2382 case nir_instr_type_parallel_copy:
2383 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2384 break;
2385 }
2386 }
2387
2388 static struct ir3_block *
2389 get_block(struct ir3_context *ctx, const nir_block *nblock)
2390 {
2391 struct ir3_block *block;
2392 struct hash_entry *hentry;
2393
2394 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2395 if (hentry)
2396 return hentry->data;
2397
2398 block = ir3_block_create(ctx->ir);
2399 block->nblock = nblock;
2400 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2401
2402 block->predecessors = _mesa_pointer_set_create(block);
2403 set_foreach(nblock->predecessors, sentry) {
2404 _mesa_set_add(block->predecessors, get_block(ctx, sentry->key));
2405 }
2406
2407 return block;
2408 }
2409
2410 static void
2411 emit_block(struct ir3_context *ctx, nir_block *nblock)
2412 {
2413 struct ir3_block *block = get_block(ctx, nblock);
2414
2415 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2416 if (nblock->successors[i]) {
2417 block->successors[i] =
2418 get_block(ctx, nblock->successors[i]);
2419 }
2420 }
2421
2422 ctx->block = block;
2423 list_addtail(&block->node, &ctx->ir->block_list);
2424
2425 /* re-emit addr register in each block if needed: */
2426 for (int i = 0; i < ARRAY_SIZE(ctx->addr_ht); i++) {
2427 _mesa_hash_table_destroy(ctx->addr_ht[i], NULL);
2428 ctx->addr_ht[i] = NULL;
2429 }
2430
2431 nir_foreach_instr (instr, nblock) {
2432 ctx->cur_instr = instr;
2433 emit_instr(ctx, instr);
2434 ctx->cur_instr = NULL;
2435 if (ctx->error)
2436 return;
2437 }
2438 }
2439
2440 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2441
2442 static void
2443 emit_if(struct ir3_context *ctx, nir_if *nif)
2444 {
2445 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2446
2447 ctx->block->condition =
2448 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
2449
2450 emit_cf_list(ctx, &nif->then_list);
2451 emit_cf_list(ctx, &nif->else_list);
2452 }
2453
2454 static void
2455 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2456 {
2457 emit_cf_list(ctx, &nloop->body);
2458 ctx->so->loops++;
2459 }
2460
2461 static void
2462 stack_push(struct ir3_context *ctx)
2463 {
2464 ctx->stack++;
2465 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2466 }
2467
2468 static void
2469 stack_pop(struct ir3_context *ctx)
2470 {
2471 compile_assert(ctx, ctx->stack > 0);
2472 ctx->stack--;
2473 }
2474
2475 static void
2476 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2477 {
2478 foreach_list_typed (nir_cf_node, node, node, list) {
2479 switch (node->type) {
2480 case nir_cf_node_block:
2481 emit_block(ctx, nir_cf_node_as_block(node));
2482 break;
2483 case nir_cf_node_if:
2484 stack_push(ctx);
2485 emit_if(ctx, nir_cf_node_as_if(node));
2486 stack_pop(ctx);
2487 break;
2488 case nir_cf_node_loop:
2489 stack_push(ctx);
2490 emit_loop(ctx, nir_cf_node_as_loop(node));
2491 stack_pop(ctx);
2492 break;
2493 case nir_cf_node_function:
2494 ir3_context_error(ctx, "TODO\n");
2495 break;
2496 }
2497 }
2498 }
2499
2500 /* emit stream-out code. At this point, the current block is the original
2501 * (nir) end block, and nir ensures that all flow control paths terminate
2502 * into the end block. We re-purpose the original end block to generate
2503 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2504 * block holding stream-out write instructions, followed by the new end
2505 * block:
2506 *
2507 * blockOrigEnd {
2508 * p0.x = (vtxcnt < maxvtxcnt)
2509 * // succs: blockStreamOut, blockNewEnd
2510 * }
2511 * blockStreamOut {
2512 * ... stream-out instructions ...
2513 * // succs: blockNewEnd
2514 * }
2515 * blockNewEnd {
2516 * }
2517 */
2518 static void
2519 emit_stream_out(struct ir3_context *ctx)
2520 {
2521 struct ir3 *ir = ctx->ir;
2522 struct ir3_stream_output_info *strmout =
2523 &ctx->so->shader->stream_output;
2524 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2525 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2526 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2527
2528 /* create vtxcnt input in input block at top of shader,
2529 * so that it is seen as live over the entire duration
2530 * of the shader:
2531 */
2532 vtxcnt = create_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, 0x1);
2533 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2534
2535 /* at this point, we are at the original 'end' block,
2536 * re-purpose this block to stream-out condition, then
2537 * append stream-out block and new-end block
2538 */
2539 orig_end_block = ctx->block;
2540
2541 // TODO these blocks need to update predecessors..
2542 // maybe w/ store_global intrinsic, we could do this
2543 // stuff in nir->nir pass
2544
2545 stream_out_block = ir3_block_create(ir);
2546 list_addtail(&stream_out_block->node, &ir->block_list);
2547
2548 new_end_block = ir3_block_create(ir);
2549 list_addtail(&new_end_block->node, &ir->block_list);
2550
2551 orig_end_block->successors[0] = stream_out_block;
2552 orig_end_block->successors[1] = new_end_block;
2553 stream_out_block->successors[0] = new_end_block;
2554
2555 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2556 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2557 cond->regs[0]->num = regid(REG_P0, 0);
2558 cond->regs[0]->flags &= ~IR3_REG_SSA;
2559 cond->cat2.condition = IR3_COND_LT;
2560
2561 /* condition goes on previous block to the conditional,
2562 * since it is used to pick which of the two successor
2563 * paths to take:
2564 */
2565 orig_end_block->condition = cond;
2566
2567 /* switch to stream_out_block to generate the stream-out
2568 * instructions:
2569 */
2570 ctx->block = stream_out_block;
2571
2572 /* Calculate base addresses based on vtxcnt. Instructions
2573 * generated for bases not used in following loop will be
2574 * stripped out in the backend.
2575 */
2576 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2577 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
2578 unsigned stride = strmout->stride[i];
2579 struct ir3_instruction *base, *off;
2580
2581 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
2582
2583 /* 24-bit should be enough: */
2584 off = ir3_MUL_U24(ctx->block, vtxcnt, 0,
2585 create_immed(ctx->block, stride * 4), 0);
2586
2587 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2588 }
2589
2590 /* Generate the per-output store instructions: */
2591 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2592 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2593 unsigned c = j + strmout->output[i].start_component;
2594 struct ir3_instruction *base, *out, *stg;
2595
2596 base = bases[strmout->output[i].output_buffer];
2597 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2598
2599 stg = ir3_STG(ctx->block, base, 0, out, 0,
2600 create_immed(ctx->block, 1), 0);
2601 stg->cat6.type = TYPE_U32;
2602 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2603
2604 array_insert(ctx->block, ctx->block->keeps, stg);
2605 }
2606 }
2607
2608 /* and finally switch to the new_end_block: */
2609 ctx->block = new_end_block;
2610 }
2611
2612 static void
2613 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2614 {
2615 nir_metadata_require(impl, nir_metadata_block_index);
2616
2617 compile_assert(ctx, ctx->stack == 0);
2618
2619 emit_cf_list(ctx, &impl->body);
2620 emit_block(ctx, impl->end_block);
2621
2622 compile_assert(ctx, ctx->stack == 0);
2623
2624 /* at this point, we should have a single empty block,
2625 * into which we emit the 'end' instruction.
2626 */
2627 compile_assert(ctx, list_is_empty(&ctx->block->instr_list));
2628
2629 /* If stream-out (aka transform-feedback) enabled, emit the
2630 * stream-out instructions, followed by a new empty block (into
2631 * which the 'end' instruction lands).
2632 *
2633 * NOTE: it is done in this order, rather than inserting before
2634 * we emit end_block, because NIR guarantees that all blocks
2635 * flow into end_block, and that end_block has no successors.
2636 * So by re-purposing end_block as the first block of stream-
2637 * out, we guarantee that all exit paths flow into the stream-
2638 * out instructions.
2639 */
2640 if ((ctx->compiler->gpu_id < 500) &&
2641 (ctx->so->shader->stream_output.num_outputs > 0) &&
2642 !ctx->so->binning_pass) {
2643 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2644 emit_stream_out(ctx);
2645 }
2646
2647 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2648 * NOP and has an epilogue that writes the VS outputs to local storage, to
2649 * be read by the HS. Then it resets execution mask (chmask) and chains
2650 * to the next shader (chsh).
2651 */
2652 if ((ctx->so->type == MESA_SHADER_VERTEX &&
2653 (ctx->so->key.has_gs || ctx->so->key.tessellation)) ||
2654 (ctx->so->type == MESA_SHADER_TESS_EVAL && ctx->so->key.has_gs)) {
2655 struct ir3_instruction *chmask =
2656 ir3_CHMASK(ctx->block);
2657 chmask->barrier_class = IR3_BARRIER_EVERYTHING;
2658 chmask->barrier_conflict = IR3_BARRIER_EVERYTHING;
2659
2660 struct ir3_instruction *chsh =
2661 ir3_CHSH(ctx->block);
2662 chsh->barrier_class = IR3_BARRIER_EVERYTHING;
2663 chsh->barrier_conflict = IR3_BARRIER_EVERYTHING;
2664 } else {
2665 ir3_END(ctx->block);
2666 }
2667 }
2668
2669 static void
2670 setup_input(struct ir3_context *ctx, nir_variable *in)
2671 {
2672 struct ir3_shader_variant *so = ctx->so;
2673 unsigned ncomp = glsl_get_components(in->type);
2674 unsigned n = in->data.driver_location;
2675 unsigned frac = in->data.location_frac;
2676 unsigned slot = in->data.location;
2677
2678 /* Inputs are loaded using ldlw or ldg for these stages. */
2679 if (ctx->so->type == MESA_SHADER_TESS_CTRL ||
2680 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2681 ctx->so->type == MESA_SHADER_GEOMETRY)
2682 return;
2683
2684 /* skip unread inputs, we could end up with (for example), unsplit
2685 * matrix/etc inputs in the case they are not read, so just silently
2686 * skip these.
2687 */
2688 if (ncomp > 4)
2689 return;
2690
2691 so->inputs[n].slot = slot;
2692 so->inputs[n].compmask |= (1 << (ncomp + frac)) - 1;
2693 so->inputs_count = MAX2(so->inputs_count, n + 1);
2694 so->inputs[n].interpolate = in->data.interpolation;
2695
2696 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2697
2698 /* if any varyings have 'sample' qualifer, that triggers us
2699 * to run in per-sample mode:
2700 */
2701 so->per_samp |= in->data.sample;
2702
2703 for (int i = 0; i < ncomp; i++) {
2704 struct ir3_instruction *instr = NULL;
2705 unsigned idx = (n * 4) + i + frac;
2706
2707 if (slot == VARYING_SLOT_POS) {
2708 ir3_context_error(ctx, "fragcoord should be a sysval!\n");
2709 } else if (slot == VARYING_SLOT_PNTC) {
2710 /* see for example st_nir_fixup_varying_slots().. this is
2711 * maybe a bit mesa/st specific. But we need things to line
2712 * up for this in fdN_program:
2713 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2714 * if (emit->sprite_coord_enable & texmask) {
2715 * ...
2716 * }
2717 */
2718 so->inputs[n].slot = VARYING_SLOT_VAR8;
2719 so->inputs[n].bary = true;
2720 instr = create_frag_input(ctx, false, idx);
2721 } else {
2722 /* detect the special case for front/back colors where
2723 * we need to do flat vs smooth shading depending on
2724 * rast state:
2725 */
2726 if (in->data.interpolation == INTERP_MODE_NONE) {
2727 switch (slot) {
2728 case VARYING_SLOT_COL0:
2729 case VARYING_SLOT_COL1:
2730 case VARYING_SLOT_BFC0:
2731 case VARYING_SLOT_BFC1:
2732 so->inputs[n].rasterflat = true;
2733 break;
2734 default:
2735 break;
2736 }
2737 }
2738
2739 if (ctx->compiler->flat_bypass) {
2740 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2741 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2742 so->inputs[n].use_ldlv = true;
2743 }
2744
2745 so->inputs[n].bary = true;
2746
2747 instr = create_frag_input(ctx, so->inputs[n].use_ldlv, idx);
2748 }
2749
2750 compile_assert(ctx, idx < ctx->ninputs);
2751
2752 ctx->inputs[idx] = instr;
2753 }
2754 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2755 struct ir3_instruction *input = NULL, *in;
2756 struct ir3_instruction *components[4];
2757 unsigned mask = (1 << (ncomp + frac)) - 1;
2758
2759 foreach_input (in, ctx->ir) {
2760 if (in->input.inidx == n) {
2761 input = in;
2762 break;
2763 }
2764 }
2765
2766 if (!input) {
2767 input = create_input(ctx, mask);
2768 input->input.inidx = n;
2769 } else {
2770 input->regs[0]->wrmask |= mask;
2771 }
2772
2773 ir3_split_dest(ctx->block, components, input, frac, ncomp);
2774
2775 for (int i = 0; i < ncomp; i++) {
2776 unsigned idx = (n * 4) + i + frac;
2777 compile_assert(ctx, idx < ctx->ninputs);
2778 ctx->inputs[idx] = components[i];
2779 }
2780 } else {
2781 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2782 }
2783
2784 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
2785 so->total_in += ncomp;
2786 }
2787 }
2788
2789 /* Initially we assign non-packed inloc's for varyings, as we don't really
2790 * know up-front which components will be unused. After all the compilation
2791 * stages we scan the shader to see which components are actually used, and
2792 * re-pack the inlocs to eliminate unneeded varyings.
2793 */
2794 static void
2795 pack_inlocs(struct ir3_context *ctx)
2796 {
2797 struct ir3_shader_variant *so = ctx->so;
2798 uint8_t used_components[so->inputs_count];
2799
2800 memset(used_components, 0, sizeof(used_components));
2801
2802 /*
2803 * First Step: scan shader to find which bary.f/ldlv remain:
2804 */
2805
2806 foreach_block (block, &ctx->ir->block_list) {
2807 foreach_instr (instr, &block->instr_list) {
2808 if (is_input(instr)) {
2809 unsigned inloc = instr->regs[1]->iim_val;
2810 unsigned i = inloc / 4;
2811 unsigned j = inloc % 4;
2812
2813 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
2814 compile_assert(ctx, i < so->inputs_count);
2815
2816 used_components[i] |= 1 << j;
2817 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
2818 for (int n = 0; n < 2; n++) {
2819 unsigned inloc = instr->prefetch.input_offset + n;
2820 unsigned i = inloc / 4;
2821 unsigned j = inloc % 4;
2822
2823 compile_assert(ctx, i < so->inputs_count);
2824
2825 used_components[i] |= 1 << j;
2826 }
2827 }
2828 }
2829 }
2830
2831 /*
2832 * Second Step: reassign varying inloc/slots:
2833 */
2834
2835 unsigned actual_in = 0;
2836 unsigned inloc = 0;
2837
2838 for (unsigned i = 0; i < so->inputs_count; i++) {
2839 unsigned compmask = 0, maxcomp = 0;
2840
2841 so->inputs[i].inloc = inloc;
2842 so->inputs[i].bary = false;
2843
2844 for (unsigned j = 0; j < 4; j++) {
2845 if (!(used_components[i] & (1 << j)))
2846 continue;
2847
2848 compmask |= (1 << j);
2849 actual_in++;
2850 maxcomp = j + 1;
2851
2852 /* at this point, since used_components[i] mask is only
2853 * considering varyings (ie. not sysvals) we know this
2854 * is a varying:
2855 */
2856 so->inputs[i].bary = true;
2857 }
2858
2859 if (so->inputs[i].bary) {
2860 so->varying_in++;
2861 so->inputs[i].compmask = (1 << maxcomp) - 1;
2862 inloc += maxcomp;
2863 }
2864 }
2865
2866 /*
2867 * Third Step: reassign packed inloc's:
2868 */
2869
2870 foreach_block (block, &ctx->ir->block_list) {
2871 foreach_instr (instr, &block->instr_list) {
2872 if (is_input(instr)) {
2873 unsigned inloc = instr->regs[1]->iim_val;
2874 unsigned i = inloc / 4;
2875 unsigned j = inloc % 4;
2876
2877 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
2878 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
2879 unsigned i = instr->prefetch.input_offset / 4;
2880 unsigned j = instr->prefetch.input_offset % 4;
2881 instr->prefetch.input_offset = so->inputs[i].inloc + j;
2882 }
2883 }
2884 }
2885 }
2886
2887 static void
2888 setup_output(struct ir3_context *ctx, nir_variable *out)
2889 {
2890 struct ir3_shader_variant *so = ctx->so;
2891 unsigned ncomp = glsl_get_components(out->type);
2892 unsigned n = out->data.driver_location;
2893 unsigned frac = out->data.location_frac;
2894 unsigned slot = out->data.location;
2895 unsigned comp = 0;
2896
2897 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2898 switch (slot) {
2899 case FRAG_RESULT_DEPTH:
2900 comp = 2; /* tgsi will write to .z component */
2901 so->writes_pos = true;
2902 break;
2903 case FRAG_RESULT_COLOR:
2904 so->color0_mrt = 1;
2905 break;
2906 case FRAG_RESULT_SAMPLE_MASK:
2907 so->writes_smask = true;
2908 break;
2909 default:
2910 if (slot >= FRAG_RESULT_DATA0)
2911 break;
2912 ir3_context_error(ctx, "unknown FS output name: %s\n",
2913 gl_frag_result_name(slot));
2914 }
2915 } else if (ctx->so->type == MESA_SHADER_VERTEX ||
2916 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2917 ctx->so->type == MESA_SHADER_GEOMETRY) {
2918 switch (slot) {
2919 case VARYING_SLOT_POS:
2920 so->writes_pos = true;
2921 break;
2922 case VARYING_SLOT_PSIZ:
2923 so->writes_psize = true;
2924 break;
2925 case VARYING_SLOT_PRIMITIVE_ID:
2926 case VARYING_SLOT_LAYER:
2927 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
2928 debug_assert(ctx->so->type == MESA_SHADER_GEOMETRY);
2929 /* fall through */
2930 case VARYING_SLOT_COL0:
2931 case VARYING_SLOT_COL1:
2932 case VARYING_SLOT_BFC0:
2933 case VARYING_SLOT_BFC1:
2934 case VARYING_SLOT_FOGC:
2935 case VARYING_SLOT_CLIP_DIST0:
2936 case VARYING_SLOT_CLIP_DIST1:
2937 case VARYING_SLOT_CLIP_VERTEX:
2938 break;
2939 default:
2940 if (slot >= VARYING_SLOT_VAR0)
2941 break;
2942 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
2943 break;
2944 ir3_context_error(ctx, "unknown %s shader output name: %s\n",
2945 _mesa_shader_stage_to_string(ctx->so->type),
2946 gl_varying_slot_name(slot));
2947 }
2948 } else if (ctx->so->type == MESA_SHADER_TESS_CTRL) {
2949 /* output lowered to buffer writes. */
2950 return;
2951 } else {
2952 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2953 }
2954
2955 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
2956
2957 so->outputs[n].slot = slot;
2958 so->outputs[n].regid = regid(n, comp);
2959 so->outputs_count = MAX2(so->outputs_count, n + 1);
2960
2961 for (int i = 0; i < ncomp; i++) {
2962 unsigned idx = (n * 4) + i + frac;
2963 compile_assert(ctx, idx < ctx->noutputs);
2964 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
2965 }
2966
2967 /* if varying packing doesn't happen, we could end up in a situation
2968 * with "holes" in the output, and since the per-generation code that
2969 * sets up varying linkage registers doesn't expect to have more than
2970 * one varying per vec4 slot, pad the holes.
2971 *
2972 * Note that this should probably generate a performance warning of
2973 * some sort.
2974 */
2975 for (int i = 0; i < frac; i++) {
2976 unsigned idx = (n * 4) + i;
2977 if (!ctx->outputs[idx]) {
2978 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
2979 }
2980 }
2981 }
2982
2983 static int
2984 max_drvloc(struct exec_list *vars)
2985 {
2986 int drvloc = -1;
2987 nir_foreach_variable (var, vars) {
2988 drvloc = MAX2(drvloc, (int)var->data.driver_location);
2989 }
2990 return drvloc;
2991 }
2992
2993 static void
2994 emit_instructions(struct ir3_context *ctx)
2995 {
2996 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
2997
2998 ctx->ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4;
2999 ctx->noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4;
3000
3001 ctx->inputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->ninputs);
3002 ctx->outputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->noutputs);
3003
3004 ctx->ir = ir3_create(ctx->compiler, ctx->so->type);
3005
3006 /* Create inputs in first block: */
3007 ctx->block = get_block(ctx, nir_start_block(fxn));
3008 ctx->in_block = ctx->block;
3009 list_addtail(&ctx->block->node, &ctx->ir->block_list);
3010
3011 /* for fragment shader, the vcoord input register is used as the
3012 * base for bary.f varying fetch instrs:
3013 *
3014 * TODO defer creating ctx->ij_pixel and corresponding sysvals
3015 * until emit_intrinsic when we know they are actually needed.
3016 * For now, we defer creating ctx->ij_centroid, etc, since we
3017 * only need ij_pixel for "old style" varying inputs (ie.
3018 * tgsi_to_nir)
3019 */
3020 struct ir3_instruction *vcoord = NULL;
3021 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3022 struct ir3_instruction *xy[2];
3023
3024 vcoord = create_input(ctx, 0x3);
3025 ir3_split_dest(ctx->block, xy, vcoord, 0, 2);
3026
3027 ctx->ij_pixel = ir3_create_collect(ctx, xy, 2);
3028 }
3029
3030 /* Setup inputs: */
3031 nir_foreach_variable (var, &ctx->s->inputs) {
3032 setup_input(ctx, var);
3033 }
3034
3035 /* Defer add_sysval_input() stuff until after setup_inputs(),
3036 * because sysvals need to be appended after varyings:
3037 */
3038 if (vcoord) {
3039 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL,
3040 0x3, vcoord);
3041 }
3042
3043
3044 /* Tesselation shaders always need primitive ID for indexing the
3045 * BO. Geometry shaders don't always need it but when they do it has be
3046 * delivered and unclobbered in the VS. To make things easy, we always
3047 * make room for it in VS/DS.
3048 */
3049 bool has_tess = ctx->so->key.tessellation != IR3_TESS_NONE;
3050 bool has_gs = ctx->so->key.has_gs;
3051 switch (ctx->so->type) {
3052 case MESA_SHADER_VERTEX:
3053 if (has_tess) {
3054 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3055 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3056 } else if (has_gs) {
3057 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3058 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3059 }
3060 break;
3061 case MESA_SHADER_TESS_CTRL:
3062 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3063 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3064 break;
3065 case MESA_SHADER_TESS_EVAL:
3066 if (has_gs)
3067 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3068 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3069 break;
3070 case MESA_SHADER_GEOMETRY:
3071 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3072 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3073 break;
3074 default:
3075 break;
3076 }
3077
3078 /* Setup outputs: */
3079 nir_foreach_variable (var, &ctx->s->outputs) {
3080 setup_output(ctx, var);
3081 }
3082
3083 /* Find # of samplers: */
3084 nir_foreach_variable (var, &ctx->s->uniforms) {
3085 ctx->so->num_samp += glsl_type_get_sampler_count(var->type);
3086 /* just assume that we'll be reading from images.. if it
3087 * is write-only we don't have to count it, but not sure
3088 * if there is a good way to know?
3089 */
3090 ctx->so->num_samp += glsl_type_get_image_count(var->type);
3091 }
3092
3093 /* NOTE: need to do something more clever when we support >1 fxn */
3094 nir_foreach_register (reg, &fxn->registers) {
3095 ir3_declare_array(ctx, reg);
3096 }
3097 /* And emit the body: */
3098 ctx->impl = fxn;
3099 emit_function(ctx, fxn);
3100 }
3101
3102 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3103 * need to assign the tex state indexes for these after we know the
3104 * max tex index.
3105 */
3106 static void
3107 fixup_astc_srgb(struct ir3_context *ctx)
3108 {
3109 struct ir3_shader_variant *so = ctx->so;
3110 /* indexed by original tex idx, value is newly assigned alpha sampler
3111 * state tex idx. Zero is invalid since there is at least one sampler
3112 * if we get here.
3113 */
3114 unsigned alt_tex_state[16] = {0};
3115 unsigned tex_idx = ctx->max_texture_index + 1;
3116 unsigned idx = 0;
3117
3118 so->astc_srgb.base = tex_idx;
3119
3120 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
3121 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
3122
3123 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
3124
3125 if (alt_tex_state[sam->cat5.tex] == 0) {
3126 /* assign new alternate/alpha tex state slot: */
3127 alt_tex_state[sam->cat5.tex] = tex_idx++;
3128 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
3129 so->astc_srgb.count++;
3130 }
3131
3132 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
3133 }
3134 }
3135
3136 static void
3137 fixup_binning_pass(struct ir3_context *ctx)
3138 {
3139 struct ir3_shader_variant *so = ctx->so;
3140 struct ir3 *ir = ctx->ir;
3141 unsigned i, j;
3142
3143 /* first pass, remove unused outputs from the IR level outputs: */
3144 for (i = 0, j = 0; i < ir->outputs_count; i++) {
3145 struct ir3_instruction *out = ir->outputs[i];
3146 assert(out->opc == OPC_META_COLLECT);
3147 unsigned outidx = out->collect.outidx;
3148 unsigned slot = so->outputs[outidx].slot;
3149
3150 /* throw away everything but first position/psize */
3151 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3152 ir->outputs[j] = ir->outputs[i];
3153 j++;
3154 }
3155 }
3156 ir->outputs_count = j;
3157
3158 /* second pass, cleanup the unused slots in ir3_shader_variant::outputs
3159 * table:
3160 */
3161 for (i = 0, j = 0; i < so->outputs_count; i++) {
3162 unsigned slot = so->outputs[i].slot;
3163
3164 /* throw away everything but first position/psize */
3165 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3166 so->outputs[j] = so->outputs[i];
3167
3168 /* fixup outidx to point to new output table entry: */
3169 struct ir3_instruction *out;
3170 foreach_output (out, ir) {
3171 if (out->collect.outidx == i) {
3172 out->collect.outidx = j;
3173 break;
3174 }
3175 }
3176
3177 j++;
3178 }
3179 }
3180 so->outputs_count = j;
3181 }
3182
3183 static void
3184 collect_tex_prefetches(struct ir3_context *ctx, struct ir3 *ir)
3185 {
3186 unsigned idx = 0;
3187
3188 /* Collect sampling instructions eligible for pre-dispatch. */
3189 foreach_block (block, &ir->block_list) {
3190 foreach_instr_safe (instr, &block->instr_list) {
3191 if (instr->opc == OPC_META_TEX_PREFETCH) {
3192 assert(idx < ARRAY_SIZE(ctx->so->sampler_prefetch));
3193 struct ir3_sampler_prefetch *fetch =
3194 &ctx->so->sampler_prefetch[idx];
3195 idx++;
3196
3197 fetch->cmd = IR3_SAMPLER_PREFETCH_CMD;
3198 fetch->wrmask = instr->regs[0]->wrmask;
3199 fetch->tex_id = instr->prefetch.tex;
3200 fetch->samp_id = instr->prefetch.samp;
3201 fetch->dst = instr->regs[0]->num;
3202 fetch->src = instr->prefetch.input_offset;
3203
3204 ctx->so->total_in =
3205 MAX2(ctx->so->total_in, instr->prefetch.input_offset + 2);
3206
3207 /* Disable half precision until supported. */
3208 fetch->half_precision = !!(instr->regs[0]->flags & IR3_REG_HALF);
3209
3210 /* Remove the prefetch placeholder instruction: */
3211 list_delinit(&instr->node);
3212 }
3213 }
3214 }
3215 }
3216
3217 int
3218 ir3_compile_shader_nir(struct ir3_compiler *compiler,
3219 struct ir3_shader_variant *so)
3220 {
3221 struct ir3_context *ctx;
3222 struct ir3 *ir;
3223 int ret = 0, max_bary;
3224
3225 assert(!so->ir);
3226
3227 ctx = ir3_context_init(compiler, so);
3228 if (!ctx) {
3229 DBG("INIT failed!");
3230 ret = -1;
3231 goto out;
3232 }
3233
3234 emit_instructions(ctx);
3235
3236 if (ctx->error) {
3237 DBG("EMIT failed!");
3238 ret = -1;
3239 goto out;
3240 }
3241
3242 ir = so->ir = ctx->ir;
3243
3244 assert((ctx->noutputs % 4) == 0);
3245
3246 /* Setup IR level outputs, which are "collects" that gather
3247 * the scalar components of outputs.
3248 */
3249 for (unsigned i = 0; i < ctx->noutputs; i += 4) {
3250 unsigned ncomp = 0;
3251 /* figure out the # of components written:
3252 *
3253 * TODO do we need to handle holes, ie. if .x and .z
3254 * components written, but .y component not written?
3255 */
3256 for (unsigned j = 0; j < 4; j++) {
3257 if (!ctx->outputs[i + j])
3258 break;
3259 ncomp++;
3260 }
3261
3262 /* Note that in some stages, like TCS, store_output is
3263 * lowered to memory writes, so no components of the
3264 * are "written" from the PoV of traditional store-
3265 * output instructions:
3266 */
3267 if (!ncomp)
3268 continue;
3269
3270 struct ir3_instruction *out =
3271 ir3_create_collect(ctx, &ctx->outputs[i], ncomp);
3272
3273 int outidx = i / 4;
3274 assert(outidx < so->outputs_count);
3275
3276 /* stash index into so->outputs[] so we can map the
3277 * output back to slot/etc later:
3278 */
3279 out->collect.outidx = outidx;
3280
3281 array_insert(ir, ir->outputs, out);
3282 }
3283
3284 /* Set up the gs header as an output for the vertex shader so it won't
3285 * clobber it for the tess ctrl shader.
3286 *
3287 * TODO this could probably be done more cleanly in a nir pass.
3288 */
3289 if (ctx->so->type == MESA_SHADER_VERTEX ||
3290 (ctx->so->key.has_gs && ctx->so->type == MESA_SHADER_TESS_EVAL)) {
3291 if (ctx->primitive_id) {
3292 unsigned n = so->outputs_count++;
3293 so->outputs[n].slot = VARYING_SLOT_PRIMITIVE_ID;
3294
3295 struct ir3_instruction *out =
3296 ir3_create_collect(ctx, &ctx->primitive_id, 1);
3297 out->collect.outidx = n;
3298 array_insert(ir, ir->outputs, out);
3299 }
3300
3301 if (ctx->gs_header) {
3302 unsigned n = so->outputs_count++;
3303 so->outputs[n].slot = VARYING_SLOT_GS_HEADER_IR3;
3304 struct ir3_instruction *out =
3305 ir3_create_collect(ctx, &ctx->gs_header, 1);
3306 out->collect.outidx = n;
3307 array_insert(ir, ir->outputs, out);
3308 }
3309
3310 if (ctx->tcs_header) {
3311 unsigned n = so->outputs_count++;
3312 so->outputs[n].slot = VARYING_SLOT_TCS_HEADER_IR3;
3313 struct ir3_instruction *out =
3314 ir3_create_collect(ctx, &ctx->tcs_header, 1);
3315 out->collect.outidx = n;
3316 array_insert(ir, ir->outputs, out);
3317 }
3318 }
3319
3320 /* at this point, for binning pass, throw away unneeded outputs: */
3321 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
3322 fixup_binning_pass(ctx);
3323
3324 ir3_debug_print(ir, "BEFORE CF");
3325
3326 ir3_cf(ir);
3327
3328 ir3_debug_print(ir, "BEFORE CP");
3329
3330 ir3_cp(ir, so);
3331
3332 /* at this point, for binning pass, throw away unneeded outputs:
3333 * Note that for a6xx and later, we do this after ir3_cp to ensure
3334 * that the uniform/constant layout for BS and VS matches, so that
3335 * we can re-use same VS_CONST state group.
3336 */
3337 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
3338 fixup_binning_pass(ctx);
3339
3340 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3341 * need to make sure not to remove any inputs that are used by
3342 * the nonbinning VS.
3343 */
3344 if (ctx->compiler->gpu_id >= 600 && so->binning_pass &&
3345 so->type == MESA_SHADER_VERTEX) {
3346 for (int i = 0; i < ctx->ninputs; i++) {
3347 struct ir3_instruction *in = ctx->inputs[i];
3348
3349 if (!in)
3350 continue;
3351
3352 unsigned n = i / 4;
3353 unsigned c = i % 4;
3354
3355 debug_assert(n < so->nonbinning->inputs_count);
3356
3357 if (so->nonbinning->inputs[n].sysval)
3358 continue;
3359
3360 /* be sure to keep inputs, even if only used in VS */
3361 if (so->nonbinning->inputs[n].compmask & (1 << c))
3362 array_insert(in->block, in->block->keeps, in);
3363 }
3364 }
3365
3366 ir3_debug_print(ir, "BEFORE GROUPING");
3367
3368 ir3_sched_add_deps(ir);
3369
3370 /* Group left/right neighbors, inserting mov's where needed to
3371 * solve conflicts:
3372 */
3373 ir3_group(ir);
3374
3375 ir3_debug_print(ir, "AFTER GROUPING");
3376
3377 ir3_depth(ir, so);
3378
3379 ir3_debug_print(ir, "AFTER DEPTH");
3380
3381 /* do Sethi–Ullman numbering before scheduling: */
3382 ir3_sun(ir);
3383
3384 ret = ir3_sched(ir);
3385 if (ret) {
3386 DBG("SCHED failed!");
3387 goto out;
3388 }
3389
3390 ir3_debug_print(ir, "AFTER SCHED");
3391
3392 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3393 * with draw pass VS, so binning and draw pass can both use the
3394 * same VBO state.
3395 *
3396 * Note that VS inputs are expected to be full precision.
3397 */
3398 bool pre_assign_inputs = (ir->compiler->gpu_id >= 600) &&
3399 (ir->type == MESA_SHADER_VERTEX) &&
3400 so->binning_pass;
3401
3402 if (pre_assign_inputs) {
3403 for (unsigned i = 0; i < ctx->ninputs; i++) {
3404 struct ir3_instruction *instr = ctx->inputs[i];
3405
3406 if (!instr)
3407 continue;
3408
3409 unsigned n = i / 4;
3410 unsigned c = i % 4;
3411 unsigned regid = so->nonbinning->inputs[n].regid + c;
3412
3413 instr->regs[0]->num = regid;
3414 }
3415
3416 ret = ir3_ra(so, ctx->inputs, ctx->ninputs);
3417 } else if (ctx->tcs_header) {
3418 /* We need to have these values in the same registers between VS and TCS
3419 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3420 */
3421
3422 ctx->tcs_header->regs[0]->num = regid(0, 0);
3423 ctx->primitive_id->regs[0]->num = regid(0, 1);
3424 struct ir3_instruction *precolor[] = { ctx->tcs_header, ctx->primitive_id };
3425 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3426 } else if (ctx->gs_header) {
3427 /* We need to have these values in the same registers between producer
3428 * (VS or DS) and GS since the producer chains to GS and doesn't get
3429 * the sysvals redelivered.
3430 */
3431
3432 ctx->gs_header->regs[0]->num = regid(0, 0);
3433 ctx->primitive_id->regs[0]->num = regid(0, 1);
3434 struct ir3_instruction *precolor[] = { ctx->gs_header, ctx->primitive_id };
3435 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3436 } else if (so->num_sampler_prefetch) {
3437 assert(so->type == MESA_SHADER_FRAGMENT);
3438 struct ir3_instruction *instr, *precolor[2];
3439 int idx = 0;
3440
3441 foreach_input (instr, ir) {
3442 if (instr->input.sysval != SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL)
3443 continue;
3444
3445 assert(idx < ARRAY_SIZE(precolor));
3446
3447 precolor[idx] = instr;
3448 instr->regs[0]->num = idx;
3449
3450 idx++;
3451 }
3452 ret = ir3_ra(so, precolor, idx);
3453 } else {
3454 ret = ir3_ra(so, NULL, 0);
3455 }
3456
3457 if (ret) {
3458 DBG("RA failed!");
3459 goto out;
3460 }
3461
3462 ir3_postsched(ctx);
3463 ir3_debug_print(ir, "AFTER POSTSCHED");
3464
3465 if (compiler->gpu_id >= 600) {
3466 if (ir3_a6xx_fixup_atomic_dests(ir, so)) {
3467 ir3_debug_print(ir, "AFTER ATOMIC FIXUP");
3468 }
3469 }
3470
3471 if (so->type == MESA_SHADER_FRAGMENT)
3472 pack_inlocs(ctx);
3473
3474 /*
3475 * Fixup inputs/outputs to point to the actual registers assigned:
3476 *
3477 * 1) initialize to r63.x (invalid/unused)
3478 * 2) iterate IR level inputs/outputs and update the variants
3479 * inputs/outputs table based on the assigned registers for
3480 * the remaining inputs/outputs.
3481 */
3482
3483 for (unsigned i = 0; i < so->inputs_count; i++)
3484 so->inputs[i].regid = INVALID_REG;
3485 for (unsigned i = 0; i < so->outputs_count; i++)
3486 so->outputs[i].regid = INVALID_REG;
3487
3488 struct ir3_instruction *out;
3489 foreach_output (out, ir) {
3490 assert(out->opc == OPC_META_COLLECT);
3491 unsigned outidx = out->collect.outidx;
3492
3493 so->outputs[outidx].regid = out->regs[0]->num;
3494 so->outputs[outidx].half = !!(out->regs[0]->flags & IR3_REG_HALF);
3495 }
3496
3497 struct ir3_instruction *in;
3498 foreach_input (in, ir) {
3499 assert(in->opc == OPC_META_INPUT);
3500 unsigned inidx = in->input.inidx;
3501
3502 if (pre_assign_inputs && !so->inputs[inidx].sysval) {
3503 if (VALIDREG(so->nonbinning->inputs[inidx].regid)) {
3504 compile_assert(ctx, in->regs[0]->num ==
3505 so->nonbinning->inputs[inidx].regid);
3506 compile_assert(ctx, !!(in->regs[0]->flags & IR3_REG_HALF) ==
3507 so->nonbinning->inputs[inidx].half);
3508 }
3509 so->inputs[inidx].regid = so->nonbinning->inputs[inidx].regid;
3510 so->inputs[inidx].half = so->nonbinning->inputs[inidx].half;
3511 } else {
3512 so->inputs[inidx].regid = in->regs[0]->num;
3513 so->inputs[inidx].half = !!(in->regs[0]->flags & IR3_REG_HALF);
3514 }
3515 }
3516
3517 if (ctx->astc_srgb)
3518 fixup_astc_srgb(ctx);
3519
3520 /* We need to do legalize after (for frag shader's) the "bary.f"
3521 * offsets (inloc) have been assigned.
3522 */
3523 ir3_legalize(ir, so, &max_bary);
3524
3525 ir3_debug_print(ir, "AFTER LEGALIZE");
3526
3527 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3528 * know what we might have to wait on when coming in from VS chsh.
3529 */
3530 if (so->type == MESA_SHADER_TESS_CTRL ||
3531 so->type == MESA_SHADER_GEOMETRY ) {
3532 foreach_block (block, &ir->block_list) {
3533 foreach_instr (instr, &block->instr_list) {
3534 instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
3535 break;
3536 }
3537 }
3538 }
3539
3540 so->branchstack = ctx->max_stack;
3541
3542 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3543 if (so->type == MESA_SHADER_FRAGMENT)
3544 so->total_in = max_bary + 1;
3545
3546 so->max_sun = ir->max_sun;
3547
3548 /* Collect sampling instructions eligible for pre-dispatch. */
3549 collect_tex_prefetches(ctx, ir);
3550
3551 out:
3552 if (ret) {
3553 if (so->ir)
3554 ir3_destroy(so->ir);
3555 so->ir = NULL;
3556 }
3557 ir3_context_free(ctx);
3558
3559 return ret;
3560 }