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ir3: Fix LDC offset units
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 __ssa_dst(mov);
55 src = __ssa_src(mov, collect, IR3_REG_RELATIV);
56 src->size = arrsz;
57 src->array.offset = n;
58
59 ir3_instr_set_address(mov, address);
60
61 return mov;
62 }
63
64 static struct ir3_instruction *
65 create_input(struct ir3_context *ctx, unsigned compmask)
66 {
67 struct ir3_instruction *in;
68
69 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
70 in->input.sysval = ~0;
71 __ssa_dst(in)->wrmask = compmask;
72
73 array_insert(ctx->ir, ctx->ir->inputs, in);
74
75 return in;
76 }
77
78 static struct ir3_instruction *
79 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
80 {
81 struct ir3_block *block = ctx->block;
82 struct ir3_instruction *instr;
83 /* packed inloc is fixed up later: */
84 struct ir3_instruction *inloc = create_immed(block, n);
85
86 if (use_ldlv) {
87 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
88 instr->cat6.type = TYPE_U32;
89 instr->cat6.iim_val = 1;
90 } else {
91 instr = ir3_BARY_F(block, inloc, 0, ctx->ij_pixel, 0);
92 instr->regs[2]->wrmask = 0x3;
93 }
94
95 return instr;
96 }
97
98 static struct ir3_instruction *
99 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
100 {
101 /* first four vec4 sysval's reserved for UBOs: */
102 /* NOTE: dp is in scalar, but there can be >4 dp components: */
103 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
104 unsigned n = const_state->offsets.driver_param;
105 unsigned r = regid(n + dp / 4, dp % 4);
106 return create_uniform(ctx->block, r);
107 }
108
109 /*
110 * Adreno uses uint rather than having dedicated bool type,
111 * which (potentially) requires some conversion, in particular
112 * when using output of an bool instr to int input, or visa
113 * versa.
114 *
115 * | Adreno | NIR |
116 * -------+---------+-------+-
117 * true | 1 | ~0 |
118 * false | 0 | 0 |
119 *
120 * To convert from an adreno bool (uint) to nir, use:
121 *
122 * absneg.s dst, (neg)src
123 *
124 * To convert back in the other direction:
125 *
126 * absneg.s dst, (abs)arc
127 *
128 * The CP step can clean up the absneg.s that cancel each other
129 * out, and with a slight bit of extra cleverness (to recognize
130 * the instructions which produce either a 0 or 1) can eliminate
131 * the absneg.s's completely when an instruction that wants
132 * 0/1 consumes the result. For example, when a nir 'bcsel'
133 * consumes the result of 'feq'. So we should be able to get by
134 * without a boolean resolve step, and without incuring any
135 * extra penalty in instruction count.
136 */
137
138 /* NIR bool -> native (adreno): */
139 static struct ir3_instruction *
140 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
141 {
142 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
143 }
144
145 /* native (adreno) -> NIR bool: */
146 static struct ir3_instruction *
147 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
148 {
149 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
150 }
151
152 /*
153 * alu/sfu instructions:
154 */
155
156 static struct ir3_instruction *
157 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
158 unsigned src_bitsize, nir_op op)
159 {
160 type_t src_type, dst_type;
161
162 switch (op) {
163 case nir_op_f2f32:
164 case nir_op_f2f16_rtne:
165 case nir_op_f2f16_rtz:
166 case nir_op_f2f16:
167 case nir_op_f2i32:
168 case nir_op_f2i16:
169 case nir_op_f2i8:
170 case nir_op_f2u32:
171 case nir_op_f2u16:
172 case nir_op_f2u8:
173 switch (src_bitsize) {
174 case 32:
175 src_type = TYPE_F32;
176 break;
177 case 16:
178 src_type = TYPE_F16;
179 break;
180 default:
181 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
182 }
183 break;
184
185 case nir_op_i2f32:
186 case nir_op_i2f16:
187 case nir_op_i2i32:
188 case nir_op_i2i16:
189 case nir_op_i2i8:
190 switch (src_bitsize) {
191 case 32:
192 src_type = TYPE_S32;
193 break;
194 case 16:
195 src_type = TYPE_S16;
196 break;
197 case 8:
198 src_type = TYPE_S8;
199 break;
200 default:
201 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
202 }
203 break;
204
205 case nir_op_u2f32:
206 case nir_op_u2f16:
207 case nir_op_u2u32:
208 case nir_op_u2u16:
209 case nir_op_u2u8:
210 switch (src_bitsize) {
211 case 32:
212 src_type = TYPE_U32;
213 break;
214 case 16:
215 src_type = TYPE_U16;
216 break;
217 case 8:
218 src_type = TYPE_U8;
219 break;
220 default:
221 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
222 }
223 break;
224
225 default:
226 ir3_context_error(ctx, "invalid conversion op: %u", op);
227 }
228
229 switch (op) {
230 case nir_op_f2f32:
231 case nir_op_i2f32:
232 case nir_op_u2f32:
233 dst_type = TYPE_F32;
234 break;
235
236 case nir_op_f2f16_rtne:
237 case nir_op_f2f16_rtz:
238 case nir_op_f2f16:
239 /* TODO how to handle rounding mode? */
240 case nir_op_i2f16:
241 case nir_op_u2f16:
242 dst_type = TYPE_F16;
243 break;
244
245 case nir_op_f2i32:
246 case nir_op_i2i32:
247 dst_type = TYPE_S32;
248 break;
249
250 case nir_op_f2i16:
251 case nir_op_i2i16:
252 dst_type = TYPE_S16;
253 break;
254
255 case nir_op_f2i8:
256 case nir_op_i2i8:
257 dst_type = TYPE_S8;
258 break;
259
260 case nir_op_f2u32:
261 case nir_op_u2u32:
262 dst_type = TYPE_U32;
263 break;
264
265 case nir_op_f2u16:
266 case nir_op_u2u16:
267 dst_type = TYPE_U16;
268 break;
269
270 case nir_op_f2u8:
271 case nir_op_u2u8:
272 dst_type = TYPE_U8;
273 break;
274
275 default:
276 ir3_context_error(ctx, "invalid conversion op: %u", op);
277 }
278
279 return ir3_COV(ctx->block, src, src_type, dst_type);
280 }
281
282 static void
283 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
284 {
285 const nir_op_info *info = &nir_op_infos[alu->op];
286 struct ir3_instruction **dst, *src[info->num_inputs];
287 unsigned bs[info->num_inputs]; /* bit size */
288 struct ir3_block *b = ctx->block;
289 unsigned dst_sz, wrmask;
290 type_t dst_type = nir_dest_bit_size(alu->dest.dest) < 32 ?
291 TYPE_U16 : TYPE_U32;
292
293 if (alu->dest.dest.is_ssa) {
294 dst_sz = alu->dest.dest.ssa.num_components;
295 wrmask = (1 << dst_sz) - 1;
296 } else {
297 dst_sz = alu->dest.dest.reg.reg->num_components;
298 wrmask = alu->dest.write_mask;
299 }
300
301 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
302
303 /* Vectors are special in that they have non-scalarized writemasks,
304 * and just take the first swizzle channel for each argument in
305 * order into each writemask channel.
306 */
307 if ((alu->op == nir_op_vec2) ||
308 (alu->op == nir_op_vec3) ||
309 (alu->op == nir_op_vec4)) {
310
311 for (int i = 0; i < info->num_inputs; i++) {
312 nir_alu_src *asrc = &alu->src[i];
313
314 compile_assert(ctx, !asrc->abs);
315 compile_assert(ctx, !asrc->negate);
316
317 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
318 if (!src[i])
319 src[i] = create_immed_typed(ctx->block, 0, dst_type);
320 dst[i] = ir3_MOV(b, src[i], dst_type);
321 }
322
323 ir3_put_dst(ctx, &alu->dest.dest);
324 return;
325 }
326
327 /* We also get mov's with more than one component for mov's so
328 * handle those specially:
329 */
330 if (alu->op == nir_op_mov) {
331 nir_alu_src *asrc = &alu->src[0];
332 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
333
334 for (unsigned i = 0; i < dst_sz; i++) {
335 if (wrmask & (1 << i)) {
336 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
337 } else {
338 dst[i] = NULL;
339 }
340 }
341
342 ir3_put_dst(ctx, &alu->dest.dest);
343 return;
344 }
345
346 /* General case: We can just grab the one used channel per src. */
347 for (int i = 0; i < info->num_inputs; i++) {
348 unsigned chan = ffs(alu->dest.write_mask) - 1;
349 nir_alu_src *asrc = &alu->src[i];
350
351 compile_assert(ctx, !asrc->abs);
352 compile_assert(ctx, !asrc->negate);
353
354 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
355 bs[i] = nir_src_bit_size(asrc->src);
356
357 compile_assert(ctx, src[i]);
358 }
359
360 switch (alu->op) {
361 case nir_op_f2f32:
362 case nir_op_f2f16_rtne:
363 case nir_op_f2f16_rtz:
364 case nir_op_f2f16:
365 case nir_op_f2i32:
366 case nir_op_f2i16:
367 case nir_op_f2i8:
368 case nir_op_f2u32:
369 case nir_op_f2u16:
370 case nir_op_f2u8:
371 case nir_op_i2f32:
372 case nir_op_i2f16:
373 case nir_op_i2i32:
374 case nir_op_i2i16:
375 case nir_op_i2i8:
376 case nir_op_u2f32:
377 case nir_op_u2f16:
378 case nir_op_u2u32:
379 case nir_op_u2u16:
380 case nir_op_u2u8:
381 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
382 break;
383 case nir_op_fquantize2f16:
384 dst[0] = create_cov(ctx,
385 create_cov(ctx, src[0], 32, nir_op_f2f16),
386 16, nir_op_f2f32);
387 break;
388 case nir_op_f2b16: {
389 struct ir3_instruction *zero = create_immed_typed(b, 0, TYPE_F16);
390 dst[0] = ir3_CMPS_F(b, src[0], 0, zero, 0);
391 dst[0]->cat2.condition = IR3_COND_NE;
392 break;
393 }
394 case nir_op_f2b32:
395 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
396 dst[0]->cat2.condition = IR3_COND_NE;
397 break;
398 case nir_op_b2f16:
399 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F16);
400 break;
401 case nir_op_b2f32:
402 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
403 break;
404 case nir_op_b2i8:
405 case nir_op_b2i16:
406 case nir_op_b2i32:
407 dst[0] = ir3_b2n(b, src[0]);
408 break;
409 case nir_op_i2b16: {
410 struct ir3_instruction *zero = create_immed_typed(b, 0, TYPE_S16);
411 dst[0] = ir3_CMPS_S(b, src[0], 0, zero, 0);
412 dst[0]->cat2.condition = IR3_COND_NE;
413 break;
414 }
415 case nir_op_i2b32:
416 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
417 dst[0]->cat2.condition = IR3_COND_NE;
418 break;
419
420 case nir_op_fneg:
421 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
422 break;
423 case nir_op_fabs:
424 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
425 break;
426 case nir_op_fmax:
427 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
428 break;
429 case nir_op_fmin:
430 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
431 break;
432 case nir_op_fsat:
433 /* if there is just a single use of the src, and it supports
434 * (sat) bit, we can just fold the (sat) flag back to the
435 * src instruction and create a mov. This is easier for cp
436 * to eliminate.
437 *
438 * TODO probably opc_cat==4 is ok too
439 */
440 if (alu->src[0].src.is_ssa &&
441 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
442 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
443 src[0]->flags |= IR3_INSTR_SAT;
444 dst[0] = ir3_MOV(b, src[0], dst_type);
445 } else {
446 /* otherwise generate a max.f that saturates.. blob does
447 * similar (generating a cat2 mov using max.f)
448 */
449 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
450 dst[0]->flags |= IR3_INSTR_SAT;
451 }
452 break;
453 case nir_op_fmul:
454 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
455 break;
456 case nir_op_fadd:
457 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
458 break;
459 case nir_op_fsub:
460 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
461 break;
462 case nir_op_ffma:
463 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
464 break;
465 case nir_op_fddx:
466 case nir_op_fddx_coarse:
467 dst[0] = ir3_DSX(b, src[0], 0);
468 dst[0]->cat5.type = TYPE_F32;
469 break;
470 case nir_op_fddx_fine:
471 dst[0] = ir3_DSXPP_1(b, src[0], 0);
472 dst[0]->cat5.type = TYPE_F32;
473 break;
474 case nir_op_fddy:
475 case nir_op_fddy_coarse:
476 dst[0] = ir3_DSY(b, src[0], 0);
477 dst[0]->cat5.type = TYPE_F32;
478 break;
479 break;
480 case nir_op_fddy_fine:
481 dst[0] = ir3_DSYPP_1(b, src[0], 0);
482 dst[0]->cat5.type = TYPE_F32;
483 break;
484 case nir_op_flt16:
485 case nir_op_flt32:
486 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
487 dst[0]->cat2.condition = IR3_COND_LT;
488 break;
489 case nir_op_fge16:
490 case nir_op_fge32:
491 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
492 dst[0]->cat2.condition = IR3_COND_GE;
493 break;
494 case nir_op_feq16:
495 case nir_op_feq32:
496 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
497 dst[0]->cat2.condition = IR3_COND_EQ;
498 break;
499 case nir_op_fne16:
500 case nir_op_fne32:
501 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
502 dst[0]->cat2.condition = IR3_COND_NE;
503 break;
504 case nir_op_fceil:
505 dst[0] = ir3_CEIL_F(b, src[0], 0);
506 break;
507 case nir_op_ffloor:
508 dst[0] = ir3_FLOOR_F(b, src[0], 0);
509 break;
510 case nir_op_ftrunc:
511 dst[0] = ir3_TRUNC_F(b, src[0], 0);
512 break;
513 case nir_op_fround_even:
514 dst[0] = ir3_RNDNE_F(b, src[0], 0);
515 break;
516 case nir_op_fsign:
517 dst[0] = ir3_SIGN_F(b, src[0], 0);
518 break;
519
520 case nir_op_fsin:
521 dst[0] = ir3_SIN(b, src[0], 0);
522 break;
523 case nir_op_fcos:
524 dst[0] = ir3_COS(b, src[0], 0);
525 break;
526 case nir_op_frsq:
527 dst[0] = ir3_RSQ(b, src[0], 0);
528 break;
529 case nir_op_frcp:
530 dst[0] = ir3_RCP(b, src[0], 0);
531 break;
532 case nir_op_flog2:
533 dst[0] = ir3_LOG2(b, src[0], 0);
534 break;
535 case nir_op_fexp2:
536 dst[0] = ir3_EXP2(b, src[0], 0);
537 break;
538 case nir_op_fsqrt:
539 dst[0] = ir3_SQRT(b, src[0], 0);
540 break;
541
542 case nir_op_iabs:
543 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
544 break;
545 case nir_op_iadd:
546 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
547 break;
548 case nir_op_iand:
549 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
550 break;
551 case nir_op_imax:
552 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
553 break;
554 case nir_op_umax:
555 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
556 break;
557 case nir_op_imin:
558 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
559 break;
560 case nir_op_umin:
561 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
562 break;
563 case nir_op_umul_low:
564 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
565 break;
566 case nir_op_imadsh_mix16:
567 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
568 break;
569 case nir_op_imad24_ir3:
570 dst[0] = ir3_MAD_S24(b, src[0], 0, src[1], 0, src[2], 0);
571 break;
572 case nir_op_imul24:
573 dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
574 break;
575 case nir_op_ineg:
576 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
577 break;
578 case nir_op_inot:
579 dst[0] = ir3_NOT_B(b, src[0], 0);
580 break;
581 case nir_op_ior:
582 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
583 break;
584 case nir_op_ishl:
585 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
586 break;
587 case nir_op_ishr:
588 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
589 break;
590 case nir_op_isub:
591 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
592 break;
593 case nir_op_ixor:
594 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
595 break;
596 case nir_op_ushr:
597 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
598 break;
599 case nir_op_ilt16:
600 case nir_op_ilt32:
601 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
602 dst[0]->cat2.condition = IR3_COND_LT;
603 break;
604 case nir_op_ige16:
605 case nir_op_ige32:
606 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
607 dst[0]->cat2.condition = IR3_COND_GE;
608 break;
609 case nir_op_ieq16:
610 case nir_op_ieq32:
611 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
612 dst[0]->cat2.condition = IR3_COND_EQ;
613 break;
614 case nir_op_ine16:
615 case nir_op_ine32:
616 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
617 dst[0]->cat2.condition = IR3_COND_NE;
618 break;
619 case nir_op_ult16:
620 case nir_op_ult32:
621 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
622 dst[0]->cat2.condition = IR3_COND_LT;
623 break;
624 case nir_op_uge16:
625 case nir_op_uge32:
626 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
627 dst[0]->cat2.condition = IR3_COND_GE;
628 break;
629
630 case nir_op_b16csel:
631 case nir_op_b32csel: {
632 struct ir3_instruction *cond = src[0];
633
634 /* If src[0] is a negation (likely as a result of an ir3_b2n(cond)),
635 * we can ignore that and use original cond, since the nonzero-ness of
636 * cond stays the same.
637 */
638 if (cond->opc == OPC_ABSNEG_S &&
639 cond->flags == 0 &&
640 (cond->regs[1]->flags & (IR3_REG_SNEG | IR3_REG_SABS)) == IR3_REG_SNEG) {
641 cond = cond->regs[1]->instr;
642 }
643
644 compile_assert(ctx, bs[1] == bs[2]);
645 if (bs[1] != bs[0]) {
646 struct hash_entry *prev_entry =
647 _mesa_hash_table_search(ctx->sel_cond_conversions, src[0]);
648 if (prev_entry) {
649 cond = prev_entry->data;
650 } else {
651 /* Make sure the boolean condition has the same bit size as the other
652 * two arguments, adding a conversion if necessary.
653 */
654 if (bs[1] < bs[0])
655 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
656 else if (bs[1] > bs[0])
657 cond = ir3_COV(b, cond, TYPE_U16, TYPE_U32);
658 _mesa_hash_table_insert(ctx->sel_cond_conversions, src[0], cond);
659 }
660 }
661
662 if (bs[1] > 16)
663 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
664 else
665 dst[0] = ir3_SEL_B16(b, src[1], 0, cond, 0, src[2], 0);
666 break;
667 }
668 case nir_op_bit_count: {
669 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
670 // double check on earlier gen's. Once half-precision support is
671 // in place, this should probably move to a NIR lowering pass:
672 struct ir3_instruction *hi, *lo;
673
674 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
675 TYPE_U32, TYPE_U16);
676 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
677
678 hi = ir3_CBITS_B(b, hi, 0);
679 lo = ir3_CBITS_B(b, lo, 0);
680
681 // TODO maybe the builders should default to making dst half-precision
682 // if the src's were half precision, to make this less awkward.. otoh
683 // we should probably just do this lowering in NIR.
684 hi->regs[0]->flags |= IR3_REG_HALF;
685 lo->regs[0]->flags |= IR3_REG_HALF;
686
687 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
688 dst[0]->regs[0]->flags |= IR3_REG_HALF;
689 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
690 break;
691 }
692 case nir_op_ifind_msb: {
693 struct ir3_instruction *cmp;
694 dst[0] = ir3_CLZ_S(b, src[0], 0);
695 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
696 cmp->cat2.condition = IR3_COND_GE;
697 dst[0] = ir3_SEL_B32(b,
698 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
699 cmp, 0, dst[0], 0);
700 break;
701 }
702 case nir_op_ufind_msb:
703 dst[0] = ir3_CLZ_B(b, src[0], 0);
704 dst[0] = ir3_SEL_B32(b,
705 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
706 src[0], 0, dst[0], 0);
707 break;
708 case nir_op_find_lsb:
709 dst[0] = ir3_BFREV_B(b, src[0], 0);
710 dst[0] = ir3_CLZ_B(b, dst[0], 0);
711 break;
712 case nir_op_bitfield_reverse:
713 dst[0] = ir3_BFREV_B(b, src[0], 0);
714 break;
715
716 default:
717 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
718 nir_op_infos[alu->op].name);
719 break;
720 }
721
722 if (nir_alu_type_get_base_type(info->output_type) == nir_type_bool) {
723 assert(dst_sz == 1);
724
725 if (nir_dest_bit_size(alu->dest.dest) < 32)
726 dst[0]->regs[0]->flags |= IR3_REG_HALF;
727
728 dst[0] = ir3_n2b(b, dst[0]);
729 }
730
731 if (nir_dest_bit_size(alu->dest.dest) < 32) {
732 for (unsigned i = 0; i < dst_sz; i++) {
733 dst[i]->regs[0]->flags |= IR3_REG_HALF;
734 }
735 }
736
737 ir3_put_dst(ctx, &alu->dest.dest);
738 }
739
740 static void
741 emit_intrinsic_load_ubo_ldc(struct ir3_context *ctx, nir_intrinsic_instr *intr,
742 struct ir3_instruction **dst)
743 {
744 struct ir3_block *b = ctx->block;
745
746 unsigned ncomp = intr->num_components;
747 struct ir3_instruction *offset = ir3_get_src(ctx, &intr->src[1])[0];
748 struct ir3_instruction *idx = ir3_get_src(ctx, &intr->src[0])[0];
749 struct ir3_instruction *ldc = ir3_LDC(b, idx, 0, offset, 0);
750 ldc->regs[0]->wrmask = MASK(ncomp);
751 ldc->cat6.iim_val = ncomp;
752 ldc->cat6.d = nir_intrinsic_base(intr);
753 ldc->cat6.type = TYPE_U32;
754
755 nir_intrinsic_instr *bindless = ir3_bindless_resource(intr->src[0]);
756 if (bindless) {
757 ldc->flags |= IR3_INSTR_B;
758 ldc->cat6.base = nir_intrinsic_desc_set(bindless);
759 ctx->so->bindless_ubo = true;
760 }
761
762 ir3_split_dest(b, dst, ldc, 0, ncomp);
763 }
764
765
766 /* handles direct/indirect UBO reads: */
767 static void
768 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
769 struct ir3_instruction **dst)
770 {
771 struct ir3_block *b = ctx->block;
772 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
773 /* UBO addresses are the first driver params, but subtract 2 here to
774 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
775 * is the uniforms: */
776 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
777 unsigned ubo = regid(const_state->offsets.ubo, 0) - 2;
778 const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
779
780 int off = 0;
781
782 /* First src is ubo index, which could either be an immed or not: */
783 src0 = ir3_get_src(ctx, &intr->src[0])[0];
784 if (is_same_type_mov(src0) &&
785 (src0->regs[1]->flags & IR3_REG_IMMED)) {
786 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
787 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
788 } else {
789 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr0(ctx, src0, ptrsz));
790 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr0(ctx, src0, ptrsz));
791
792 /* NOTE: since relative addressing is used, make sure constlen is
793 * at least big enough to cover all the UBO addresses, since the
794 * assembler won't know what the max address reg is.
795 */
796 ctx->so->constlen = MAX2(ctx->so->constlen,
797 const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
798 }
799
800 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
801 addr = base_lo;
802
803 if (nir_src_is_const(intr->src[1])) {
804 off += nir_src_as_uint(intr->src[1]);
805 } else {
806 /* For load_ubo_indirect, second src is indirect offset: */
807 src1 = ir3_get_src(ctx, &intr->src[1])[0];
808
809 /* and add offset to addr: */
810 addr = ir3_ADD_S(b, addr, 0, src1, 0);
811 }
812
813 /* if offset is to large to encode in the ldg, split it out: */
814 if ((off + (intr->num_components * 4)) > 1024) {
815 /* split out the minimal amount to improve the odds that
816 * cp can fit the immediate in the add.s instruction:
817 */
818 unsigned off2 = off + (intr->num_components * 4) - 1024;
819 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
820 off -= off2;
821 }
822
823 if (ptrsz == 2) {
824 struct ir3_instruction *carry;
825
826 /* handle 32b rollover, ie:
827 * if (addr < base_lo)
828 * base_hi++
829 */
830 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
831 carry->cat2.condition = IR3_COND_LT;
832 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
833
834 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
835 }
836
837 for (int i = 0; i < intr->num_components; i++) {
838 struct ir3_instruction *load =
839 ir3_LDG(b, addr, 0, create_immed(b, 1), 0, /* num components */
840 create_immed(b, off + i * 4), 0);
841 load->cat6.type = TYPE_U32;
842 dst[i] = load;
843 }
844 }
845
846 /* src[] = { block_index } */
847 static void
848 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
849 struct ir3_instruction **dst)
850 {
851 /* SSBO size stored as a const starting at ssbo_sizes: */
852 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
853 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
854 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
855 const_state->ssbo_size.off[blk_idx];
856
857 debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
858
859 dst[0] = create_uniform(ctx->block, idx);
860 }
861
862 /* src[] = { offset }. const_index[] = { base } */
863 static void
864 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
865 struct ir3_instruction **dst)
866 {
867 struct ir3_block *b = ctx->block;
868 struct ir3_instruction *ldl, *offset;
869 unsigned base;
870
871 offset = ir3_get_src(ctx, &intr->src[0])[0];
872 base = nir_intrinsic_base(intr);
873
874 ldl = ir3_LDL(b, offset, 0,
875 create_immed(b, intr->num_components), 0,
876 create_immed(b, base), 0);
877
878 ldl->cat6.type = utype_dst(intr->dest);
879 ldl->regs[0]->wrmask = MASK(intr->num_components);
880
881 ldl->barrier_class = IR3_BARRIER_SHARED_R;
882 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
883
884 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
885 }
886
887 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
888 static void
889 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
890 {
891 struct ir3_block *b = ctx->block;
892 struct ir3_instruction *stl, *offset;
893 struct ir3_instruction * const *value;
894 unsigned base, wrmask;
895
896 value = ir3_get_src(ctx, &intr->src[0]);
897 offset = ir3_get_src(ctx, &intr->src[1])[0];
898
899 base = nir_intrinsic_base(intr);
900 wrmask = nir_intrinsic_write_mask(intr);
901
902 /* Combine groups of consecutive enabled channels in one write
903 * message. We use ffs to find the first enabled channel and then ffs on
904 * the bit-inverse, down-shifted writemask to determine the length of
905 * the block of enabled bits.
906 *
907 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
908 */
909 while (wrmask) {
910 unsigned first_component = ffs(wrmask) - 1;
911 unsigned length = ffs(~(wrmask >> first_component)) - 1;
912
913 stl = ir3_STL(b, offset, 0,
914 ir3_create_collect(ctx, &value[first_component], length), 0,
915 create_immed(b, length), 0);
916 stl->cat6.dst_offset = first_component + base;
917 stl->cat6.type = utype_src(intr->src[0]);
918 stl->barrier_class = IR3_BARRIER_SHARED_W;
919 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
920
921 array_insert(b, b->keeps, stl);
922
923 /* Clear the bits in the writemask that we just wrote, then try
924 * again to see if more channels are left.
925 */
926 wrmask &= (15 << (first_component + length));
927 }
928 }
929
930 /* src[] = { offset }. const_index[] = { base } */
931 static void
932 emit_intrinsic_load_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr,
933 struct ir3_instruction **dst)
934 {
935 struct ir3_block *b = ctx->block;
936 struct ir3_instruction *load, *offset;
937 unsigned base;
938
939 offset = ir3_get_src(ctx, &intr->src[0])[0];
940 base = nir_intrinsic_base(intr);
941
942 load = ir3_LDLW(b, offset, 0,
943 create_immed(b, intr->num_components), 0,
944 create_immed(b, base), 0);
945
946 load->cat6.type = utype_dst(intr->dest);
947 load->regs[0]->wrmask = MASK(intr->num_components);
948
949 load->barrier_class = IR3_BARRIER_SHARED_R;
950 load->barrier_conflict = IR3_BARRIER_SHARED_W;
951
952 ir3_split_dest(b, dst, load, 0, intr->num_components);
953 }
954
955 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
956 static void
957 emit_intrinsic_store_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr)
958 {
959 struct ir3_block *b = ctx->block;
960 struct ir3_instruction *store, *offset;
961 struct ir3_instruction * const *value;
962 unsigned base, wrmask;
963
964 value = ir3_get_src(ctx, &intr->src[0]);
965 offset = ir3_get_src(ctx, &intr->src[1])[0];
966
967 base = nir_intrinsic_base(intr);
968 wrmask = nir_intrinsic_write_mask(intr);
969
970 /* Combine groups of consecutive enabled channels in one write
971 * message. We use ffs to find the first enabled channel and then ffs on
972 * the bit-inverse, down-shifted writemask to determine the length of
973 * the block of enabled bits.
974 *
975 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
976 */
977 while (wrmask) {
978 unsigned first_component = ffs(wrmask) - 1;
979 unsigned length = ffs(~(wrmask >> first_component)) - 1;
980
981 store = ir3_STLW(b, offset, 0,
982 ir3_create_collect(ctx, &value[first_component], length), 0,
983 create_immed(b, length), 0);
984
985 store->cat6.dst_offset = first_component + base;
986 store->cat6.type = utype_src(intr->src[0]);
987 store->barrier_class = IR3_BARRIER_SHARED_W;
988 store->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
989
990 array_insert(b, b->keeps, store);
991
992 /* Clear the bits in the writemask that we just wrote, then try
993 * again to see if more channels are left.
994 */
995 wrmask &= (15 << (first_component + length));
996 }
997 }
998
999 /*
1000 * CS shared variable atomic intrinsics
1001 *
1002 * All of the shared variable atomic memory operations read a value from
1003 * memory, compute a new value using one of the operations below, write the
1004 * new value to memory, and return the original value read.
1005 *
1006 * All operations take 2 sources except CompSwap that takes 3. These
1007 * sources represent:
1008 *
1009 * 0: The offset into the shared variable storage region that the atomic
1010 * operation will operate on.
1011 * 1: The data parameter to the atomic function (i.e. the value to add
1012 * in shared_atomic_add, etc).
1013 * 2: For CompSwap only: the second data parameter.
1014 */
1015 static struct ir3_instruction *
1016 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1017 {
1018 struct ir3_block *b = ctx->block;
1019 struct ir3_instruction *atomic, *src0, *src1;
1020 type_t type = TYPE_U32;
1021
1022 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
1023 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
1024
1025 switch (intr->intrinsic) {
1026 case nir_intrinsic_shared_atomic_add:
1027 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
1028 break;
1029 case nir_intrinsic_shared_atomic_imin:
1030 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
1031 type = TYPE_S32;
1032 break;
1033 case nir_intrinsic_shared_atomic_umin:
1034 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
1035 break;
1036 case nir_intrinsic_shared_atomic_imax:
1037 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1038 type = TYPE_S32;
1039 break;
1040 case nir_intrinsic_shared_atomic_umax:
1041 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1042 break;
1043 case nir_intrinsic_shared_atomic_and:
1044 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
1045 break;
1046 case nir_intrinsic_shared_atomic_or:
1047 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
1048 break;
1049 case nir_intrinsic_shared_atomic_xor:
1050 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
1051 break;
1052 case nir_intrinsic_shared_atomic_exchange:
1053 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
1054 break;
1055 case nir_intrinsic_shared_atomic_comp_swap:
1056 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1057 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1058 ir3_get_src(ctx, &intr->src[2])[0],
1059 src1,
1060 }, 2);
1061 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
1062 break;
1063 default:
1064 unreachable("boo");
1065 }
1066
1067 atomic->cat6.iim_val = 1;
1068 atomic->cat6.d = 1;
1069 atomic->cat6.type = type;
1070 atomic->barrier_class = IR3_BARRIER_SHARED_W;
1071 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
1072
1073 /* even if nothing consume the result, we can't DCE the instruction: */
1074 array_insert(b, b->keeps, atomic);
1075
1076 return atomic;
1077 }
1078
1079 struct tex_src_info {
1080 /* For prefetch */
1081 unsigned tex_base, samp_base, tex_idx, samp_idx;
1082 /* For normal tex instructions */
1083 unsigned base, combined_idx, a1_val, flags;
1084 struct ir3_instruction *samp_tex;
1085 };
1086
1087 /* TODO handle actual indirect/dynamic case.. which is going to be weird
1088 * to handle with the image_mapping table..
1089 */
1090 static struct tex_src_info
1091 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1092 {
1093 struct ir3_block *b = ctx->block;
1094 struct tex_src_info info = { 0 };
1095 nir_intrinsic_instr *bindless_tex = ir3_bindless_resource(intr->src[0]);
1096 ctx->so->bindless_tex = true;
1097
1098 if (bindless_tex) {
1099 /* Bindless case */
1100 info.flags |= IR3_INSTR_B;
1101
1102 /* Gather information required to determine which encoding to
1103 * choose as well as for prefetch.
1104 */
1105 info.tex_base = nir_intrinsic_desc_set(bindless_tex);
1106 bool tex_const = nir_src_is_const(bindless_tex->src[0]);
1107 if (tex_const)
1108 info.tex_idx = nir_src_as_uint(bindless_tex->src[0]);
1109 info.samp_idx = 0;
1110
1111 /* Choose encoding. */
1112 if (tex_const && info.tex_idx < 256) {
1113 if (info.tex_idx < 16) {
1114 /* Everything fits within the instruction */
1115 info.base = info.tex_base;
1116 info.combined_idx = info.samp_idx | (info.tex_idx << 4);
1117 } else {
1118 info.base = info.tex_base;
1119 info.a1_val = info.tex_idx << 3;
1120 info.combined_idx = 0;
1121 info.flags |= IR3_INSTR_A1EN;
1122 }
1123 info.samp_tex = NULL;
1124 } else {
1125 info.flags |= IR3_INSTR_S2EN;
1126 info.base = info.tex_base;
1127
1128 /* Note: the indirect source is now a vec2 instead of hvec2 */
1129 struct ir3_instruction *texture, *sampler;
1130
1131 texture = ir3_get_src(ctx, &intr->src[0])[0];
1132 sampler = create_immed(b, 0);
1133 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1134 texture,
1135 sampler,
1136 }, 2);
1137 }
1138 } else {
1139 info.flags |= IR3_INSTR_S2EN;
1140 unsigned slot = nir_src_as_uint(intr->src[0]);
1141 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
1142 struct ir3_instruction *texture, *sampler;
1143
1144 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1145 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1146
1147 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1148 sampler,
1149 texture,
1150 }, 2);
1151 }
1152
1153 return info;
1154 }
1155
1156 static struct ir3_instruction *
1157 emit_sam(struct ir3_context *ctx, opc_t opc, struct tex_src_info info,
1158 type_t type, unsigned wrmask, struct ir3_instruction *src0,
1159 struct ir3_instruction *src1)
1160 {
1161 struct ir3_instruction *sam, *addr;
1162 if (info.flags & IR3_INSTR_A1EN) {
1163 addr = ir3_get_addr1(ctx, info.a1_val);
1164 }
1165 sam = ir3_SAM(ctx->block, opc, type, 0b1111, info.flags,
1166 info.samp_tex, src0, src1);
1167 if (info.flags & IR3_INSTR_A1EN) {
1168 ir3_instr_set_address(sam, addr);
1169 }
1170 if (info.flags & IR3_INSTR_B) {
1171 sam->cat5.tex_base = info.base;
1172 sam->cat5.samp = info.combined_idx;
1173 }
1174 return sam;
1175 }
1176
1177 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1178 static void
1179 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1180 struct ir3_instruction **dst)
1181 {
1182 struct ir3_block *b = ctx->block;
1183 struct tex_src_info info = get_image_samp_tex_src(ctx, intr);
1184 struct ir3_instruction *sam;
1185 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
1186 struct ir3_instruction *coords[4];
1187 unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
1188 type_t type = ir3_get_type_for_image_intrinsic(intr);
1189
1190 /* hmm, this seems a bit odd, but it is what blob does and (at least
1191 * a5xx) just faults on bogus addresses otherwise:
1192 */
1193 if (flags & IR3_INSTR_3D) {
1194 flags &= ~IR3_INSTR_3D;
1195 flags |= IR3_INSTR_A;
1196 }
1197 info.flags |= flags;
1198
1199 for (unsigned i = 0; i < ncoords; i++)
1200 coords[i] = src0[i];
1201
1202 if (ncoords == 1)
1203 coords[ncoords++] = create_immed(b, 0);
1204
1205 sam = emit_sam(ctx, OPC_ISAM, info, type, 0b1111,
1206 ir3_create_collect(ctx, coords, ncoords), NULL);
1207
1208 sam->barrier_class = IR3_BARRIER_IMAGE_R;
1209 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
1210
1211 ir3_split_dest(b, dst, sam, 0, 4);
1212 }
1213
1214 static void
1215 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1216 struct ir3_instruction **dst)
1217 {
1218 struct ir3_block *b = ctx->block;
1219 struct tex_src_info info = get_image_samp_tex_src(ctx, intr);
1220 struct ir3_instruction *sam, *lod;
1221 unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
1222 type_t dst_type = nir_dest_bit_size(intr->dest) < 32 ?
1223 TYPE_U16 : TYPE_U32;
1224
1225 info.flags |= flags;
1226 lod = create_immed(b, 0);
1227 sam = emit_sam(ctx, OPC_GETSIZE, info, dst_type, 0b1111, lod, NULL);
1228
1229 /* Array size actually ends up in .w rather than .z. This doesn't
1230 * matter for miplevel 0, but for higher mips the value in z is
1231 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1232 * returned, which means that we have to add 1 to it for arrays for
1233 * a3xx.
1234 *
1235 * Note use a temporary dst and then copy, since the size of the dst
1236 * array that is passed in is based on nir's understanding of the
1237 * result size, not the hardware's
1238 */
1239 struct ir3_instruction *tmp[4];
1240
1241 ir3_split_dest(b, tmp, sam, 0, 4);
1242
1243 /* get_size instruction returns size in bytes instead of texels
1244 * for imageBuffer, so we need to divide it by the pixel size
1245 * of the image format.
1246 *
1247 * TODO: This is at least true on a5xx. Check other gens.
1248 */
1249 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF) {
1250 /* Since all the possible values the divisor can take are
1251 * power-of-two (4, 8, or 16), the division is implemented
1252 * as a shift-right.
1253 * During shader setup, the log2 of the image format's
1254 * bytes-per-pixel should have been emitted in 2nd slot of
1255 * image_dims. See ir3_shader::emit_image_dims().
1256 */
1257 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
1258 unsigned cb = regid(const_state->offsets.image_dims, 0) +
1259 const_state->image_dims.off[nir_src_as_uint(intr->src[0])];
1260 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1261
1262 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1263 }
1264
1265 for (unsigned i = 0; i < ncoords; i++)
1266 dst[i] = tmp[i];
1267
1268 if (flags & IR3_INSTR_A) {
1269 if (ctx->compiler->levels_add_one) {
1270 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1271 } else {
1272 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1273 }
1274 }
1275 }
1276
1277 static void
1278 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1279 {
1280 struct ir3_block *b = ctx->block;
1281 struct ir3_instruction *barrier;
1282
1283 switch (intr->intrinsic) {
1284 case nir_intrinsic_control_barrier:
1285 barrier = ir3_BAR(b);
1286 barrier->cat7.g = true;
1287 barrier->cat7.l = true;
1288 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1289 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1290 break;
1291 case nir_intrinsic_memory_barrier:
1292 barrier = ir3_FENCE(b);
1293 barrier->cat7.g = true;
1294 barrier->cat7.r = true;
1295 barrier->cat7.w = true;
1296 barrier->cat7.l = true;
1297 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1298 IR3_BARRIER_BUFFER_W;
1299 barrier->barrier_conflict =
1300 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1301 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1302 break;
1303 case nir_intrinsic_memory_barrier_buffer:
1304 barrier = ir3_FENCE(b);
1305 barrier->cat7.g = true;
1306 barrier->cat7.r = true;
1307 barrier->cat7.w = true;
1308 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1309 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1310 IR3_BARRIER_BUFFER_W;
1311 break;
1312 case nir_intrinsic_memory_barrier_image:
1313 // TODO double check if this should have .g set
1314 barrier = ir3_FENCE(b);
1315 barrier->cat7.g = true;
1316 barrier->cat7.r = true;
1317 barrier->cat7.w = true;
1318 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1319 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1320 IR3_BARRIER_IMAGE_W;
1321 break;
1322 case nir_intrinsic_memory_barrier_shared:
1323 barrier = ir3_FENCE(b);
1324 barrier->cat7.g = true;
1325 barrier->cat7.l = true;
1326 barrier->cat7.r = true;
1327 barrier->cat7.w = true;
1328 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1329 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1330 IR3_BARRIER_SHARED_W;
1331 break;
1332 case nir_intrinsic_group_memory_barrier:
1333 barrier = ir3_FENCE(b);
1334 barrier->cat7.g = true;
1335 barrier->cat7.l = true;
1336 barrier->cat7.r = true;
1337 barrier->cat7.w = true;
1338 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1339 IR3_BARRIER_IMAGE_W |
1340 IR3_BARRIER_BUFFER_W;
1341 barrier->barrier_conflict =
1342 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1343 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1344 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1345 break;
1346 default:
1347 unreachable("boo");
1348 }
1349
1350 /* make sure barrier doesn't get DCE'd */
1351 array_insert(b, b->keeps, barrier);
1352 }
1353
1354 static void add_sysval_input_compmask(struct ir3_context *ctx,
1355 gl_system_value slot, unsigned compmask,
1356 struct ir3_instruction *instr)
1357 {
1358 struct ir3_shader_variant *so = ctx->so;
1359 unsigned n = so->inputs_count++;
1360
1361 assert(instr->opc == OPC_META_INPUT);
1362 instr->input.inidx = n;
1363 instr->input.sysval = slot;
1364
1365 so->inputs[n].sysval = true;
1366 so->inputs[n].slot = slot;
1367 so->inputs[n].compmask = compmask;
1368 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1369 so->total_in++;
1370 }
1371
1372 static struct ir3_instruction *
1373 create_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1374 unsigned compmask)
1375 {
1376 assert(compmask);
1377 struct ir3_instruction *sysval = create_input(ctx, compmask);
1378 add_sysval_input_compmask(ctx, slot, compmask, sysval);
1379 return sysval;
1380 }
1381
1382 static struct ir3_instruction *
1383 get_barycentric_centroid(struct ir3_context *ctx)
1384 {
1385 if (!ctx->ij_centroid) {
1386 struct ir3_instruction *xy[2];
1387 struct ir3_instruction *ij;
1388
1389 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID, 0x3);
1390 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1391
1392 ctx->ij_centroid = ir3_create_collect(ctx, xy, 2);
1393 }
1394
1395 return ctx->ij_centroid;
1396 }
1397
1398 static struct ir3_instruction *
1399 get_barycentric_sample(struct ir3_context *ctx)
1400 {
1401 if (!ctx->ij_sample) {
1402 struct ir3_instruction *xy[2];
1403 struct ir3_instruction *ij;
1404
1405 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE, 0x3);
1406 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1407
1408 ctx->ij_sample = ir3_create_collect(ctx, xy, 2);
1409 }
1410
1411 return ctx->ij_sample;
1412 }
1413
1414 static struct ir3_instruction *
1415 get_barycentric_pixel(struct ir3_context *ctx)
1416 {
1417 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1418 * this to create ij_pixel only on demand:
1419 */
1420 return ctx->ij_pixel;
1421 }
1422
1423 static struct ir3_instruction *
1424 get_frag_coord(struct ir3_context *ctx)
1425 {
1426 if (!ctx->frag_coord) {
1427 struct ir3_block *b = ctx->in_block;
1428 struct ir3_instruction *xyzw[4];
1429 struct ir3_instruction *hw_frag_coord;
1430
1431 hw_frag_coord = create_sysval_input(ctx, SYSTEM_VALUE_FRAG_COORD, 0xf);
1432 ir3_split_dest(b, xyzw, hw_frag_coord, 0, 4);
1433
1434 /* for frag_coord.xy, we get unsigned values.. we need
1435 * to subtract (integer) 8 and divide by 16 (right-
1436 * shift by 4) then convert to float:
1437 *
1438 * sub.s tmp, src, 8
1439 * shr.b tmp, tmp, 4
1440 * mov.u32f32 dst, tmp
1441 *
1442 */
1443 for (int i = 0; i < 2; i++) {
1444 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1445 xyzw[i] = ir3_MUL_F(b, xyzw[i], 0, create_immed(b, fui(1.0 / 16.0)), 0);
1446 }
1447
1448 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1449 ctx->so->frag_coord = true;
1450 }
1451
1452 return ctx->frag_coord;
1453 }
1454
1455 static void
1456 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1457 {
1458 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1459 struct ir3_instruction **dst;
1460 struct ir3_instruction * const *src;
1461 struct ir3_block *b = ctx->block;
1462 int idx, comp;
1463
1464 if (info->has_dest) {
1465 unsigned n = nir_intrinsic_dest_components(intr);
1466 dst = ir3_get_dst(ctx, &intr->dest, n);
1467 } else {
1468 dst = NULL;
1469 }
1470
1471 const unsigned primitive_param = ctx->so->shader->const_state.offsets.primitive_param * 4;
1472 const unsigned primitive_map = ctx->so->shader->const_state.offsets.primitive_map * 4;
1473
1474 switch (intr->intrinsic) {
1475 case nir_intrinsic_load_uniform:
1476 idx = nir_intrinsic_base(intr);
1477 if (nir_src_is_const(intr->src[0])) {
1478 idx += nir_src_as_uint(intr->src[0]);
1479 for (int i = 0; i < intr->num_components; i++) {
1480 dst[i] = create_uniform_typed(b, idx + i,
1481 nir_dest_bit_size(intr->dest) < 32 ? TYPE_F16 : TYPE_F32);
1482 }
1483 } else {
1484 src = ir3_get_src(ctx, &intr->src[0]);
1485 for (int i = 0; i < intr->num_components; i++) {
1486 dst[i] = create_uniform_indirect(b, idx + i,
1487 ir3_get_addr0(ctx, src[0], 1));
1488 }
1489 /* NOTE: if relative addressing is used, we set
1490 * constlen in the compiler (to worst-case value)
1491 * since we don't know in the assembler what the max
1492 * addr reg value can be:
1493 */
1494 ctx->so->constlen = MAX2(ctx->so->constlen,
1495 ctx->so->shader->ubo_state.size / 16);
1496 }
1497 break;
1498
1499 case nir_intrinsic_load_vs_primitive_stride_ir3:
1500 dst[0] = create_uniform(b, primitive_param + 0);
1501 break;
1502 case nir_intrinsic_load_vs_vertex_stride_ir3:
1503 dst[0] = create_uniform(b, primitive_param + 1);
1504 break;
1505 case nir_intrinsic_load_hs_patch_stride_ir3:
1506 dst[0] = create_uniform(b, primitive_param + 2);
1507 break;
1508 case nir_intrinsic_load_patch_vertices_in:
1509 dst[0] = create_uniform(b, primitive_param + 3);
1510 break;
1511 case nir_intrinsic_load_tess_param_base_ir3:
1512 dst[0] = create_uniform(b, primitive_param + 4);
1513 dst[1] = create_uniform(b, primitive_param + 5);
1514 break;
1515 case nir_intrinsic_load_tess_factor_base_ir3:
1516 dst[0] = create_uniform(b, primitive_param + 6);
1517 dst[1] = create_uniform(b, primitive_param + 7);
1518 break;
1519
1520 case nir_intrinsic_load_primitive_location_ir3:
1521 idx = nir_intrinsic_driver_location(intr);
1522 dst[0] = create_uniform(b, primitive_map + idx);
1523 break;
1524
1525 case nir_intrinsic_load_gs_header_ir3:
1526 dst[0] = ctx->gs_header;
1527 break;
1528 case nir_intrinsic_load_tcs_header_ir3:
1529 dst[0] = ctx->tcs_header;
1530 break;
1531
1532 case nir_intrinsic_load_primitive_id:
1533 dst[0] = ctx->primitive_id;
1534 break;
1535
1536 case nir_intrinsic_load_tess_coord:
1537 if (!ctx->tess_coord) {
1538 ctx->tess_coord =
1539 create_sysval_input(ctx, SYSTEM_VALUE_TESS_COORD, 0x3);
1540 }
1541 ir3_split_dest(b, dst, ctx->tess_coord, 0, 2);
1542
1543 /* Unused, but ir3_put_dst() below wants to free something */
1544 dst[2] = create_immed(b, 0);
1545 break;
1546
1547 case nir_intrinsic_end_patch_ir3:
1548 assert(ctx->so->type == MESA_SHADER_TESS_CTRL);
1549 struct ir3_instruction *end = ir3_ENDIF(b);
1550 array_insert(b, b->keeps, end);
1551
1552 end->barrier_class = IR3_BARRIER_EVERYTHING;
1553 end->barrier_conflict = IR3_BARRIER_EVERYTHING;
1554 break;
1555
1556 case nir_intrinsic_store_global_ir3: {
1557 struct ir3_instruction *value, *addr, *offset;
1558
1559 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1560 ir3_get_src(ctx, &intr->src[1])[0],
1561 ir3_get_src(ctx, &intr->src[1])[1]
1562 }, 2);
1563
1564 offset = ir3_get_src(ctx, &intr->src[2])[0];
1565
1566 value = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]),
1567 intr->num_components);
1568
1569 struct ir3_instruction *stg =
1570 ir3_STG_G(ctx->block, addr, 0, value, 0,
1571 create_immed(ctx->block, intr->num_components), 0, offset, 0);
1572 stg->cat6.type = TYPE_U32;
1573 stg->cat6.iim_val = 1;
1574
1575 array_insert(b, b->keeps, stg);
1576
1577 stg->barrier_class = IR3_BARRIER_BUFFER_W;
1578 stg->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1579 break;
1580 }
1581
1582 case nir_intrinsic_load_global_ir3: {
1583 struct ir3_instruction *addr, *offset;
1584
1585 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1586 ir3_get_src(ctx, &intr->src[0])[0],
1587 ir3_get_src(ctx, &intr->src[0])[1]
1588 }, 2);
1589
1590 offset = ir3_get_src(ctx, &intr->src[1])[0];
1591
1592 struct ir3_instruction *load =
1593 ir3_LDG(b, addr, 0, create_immed(ctx->block, intr->num_components),
1594 0, offset, 0);
1595 load->cat6.type = TYPE_U32;
1596 load->regs[0]->wrmask = MASK(intr->num_components);
1597
1598 load->barrier_class = IR3_BARRIER_BUFFER_R;
1599 load->barrier_conflict = IR3_BARRIER_BUFFER_W;
1600
1601 ir3_split_dest(b, dst, load, 0, intr->num_components);
1602 break;
1603 }
1604
1605 case nir_intrinsic_load_ubo:
1606 emit_intrinsic_load_ubo(ctx, intr, dst);
1607 break;
1608 case nir_intrinsic_load_ubo_ir3:
1609 emit_intrinsic_load_ubo_ldc(ctx, intr, dst);
1610 break;
1611 case nir_intrinsic_load_frag_coord:
1612 ir3_split_dest(b, dst, get_frag_coord(ctx), 0, 4);
1613 break;
1614 case nir_intrinsic_load_sample_pos_from_id: {
1615 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1616 * but that doesn't seem necessary.
1617 */
1618 struct ir3_instruction *offset =
1619 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1620 offset->regs[0]->wrmask = 0x3;
1621 offset->cat5.type = TYPE_F32;
1622
1623 ir3_split_dest(b, dst, offset, 0, 2);
1624
1625 break;
1626 }
1627 case nir_intrinsic_load_size_ir3:
1628 if (!ctx->ij_size) {
1629 ctx->ij_size =
1630 create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE, 0x1);
1631 }
1632 dst[0] = ctx->ij_size;
1633 break;
1634 case nir_intrinsic_load_barycentric_centroid:
1635 ir3_split_dest(b, dst, get_barycentric_centroid(ctx), 0, 2);
1636 break;
1637 case nir_intrinsic_load_barycentric_sample:
1638 if (ctx->so->key.msaa) {
1639 ir3_split_dest(b, dst, get_barycentric_sample(ctx), 0, 2);
1640 } else {
1641 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1642 }
1643 break;
1644 case nir_intrinsic_load_barycentric_pixel:
1645 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1646 break;
1647 case nir_intrinsic_load_interpolated_input:
1648 idx = nir_intrinsic_base(intr);
1649 comp = nir_intrinsic_component(intr);
1650 src = ir3_get_src(ctx, &intr->src[0]);
1651 if (nir_src_is_const(intr->src[1])) {
1652 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1653 idx += nir_src_as_uint(intr->src[1]);
1654 for (int i = 0; i < intr->num_components; i++) {
1655 unsigned inloc = idx * 4 + i + comp;
1656 if (ctx->so->inputs[idx].bary &&
1657 !ctx->so->inputs[idx].use_ldlv) {
1658 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1659 } else {
1660 /* for non-varyings use the pre-setup input, since
1661 * that is easier than mapping things back to a
1662 * nir_variable to figure out what it is.
1663 */
1664 dst[i] = ctx->inputs[inloc];
1665 compile_assert(ctx, dst[i]);
1666 }
1667 }
1668 } else {
1669 ir3_context_error(ctx, "unhandled");
1670 }
1671 break;
1672 case nir_intrinsic_load_input:
1673 idx = nir_intrinsic_base(intr);
1674 comp = nir_intrinsic_component(intr);
1675 if (nir_src_is_const(intr->src[0])) {
1676 idx += nir_src_as_uint(intr->src[0]);
1677 for (int i = 0; i < intr->num_components; i++) {
1678 unsigned n = idx * 4 + i + comp;
1679 dst[i] = ctx->inputs[n];
1680 compile_assert(ctx, ctx->inputs[n]);
1681 }
1682 } else {
1683 src = ir3_get_src(ctx, &intr->src[0]);
1684 struct ir3_instruction *collect =
1685 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ninputs);
1686 struct ir3_instruction *addr = ir3_get_addr0(ctx, src[0], 4);
1687 for (int i = 0; i < intr->num_components; i++) {
1688 unsigned n = idx * 4 + i + comp;
1689 dst[i] = create_indirect_load(ctx, ctx->ninputs,
1690 n, addr, collect);
1691 }
1692 }
1693 break;
1694 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1695 * pass and replaced by an ir3-specifc version that adds the
1696 * dword-offset in the last source.
1697 */
1698 case nir_intrinsic_load_ssbo_ir3:
1699 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1700 break;
1701 case nir_intrinsic_store_ssbo_ir3:
1702 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1703 !ctx->s->info.fs.early_fragment_tests)
1704 ctx->so->no_earlyz = true;
1705 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1706 break;
1707 case nir_intrinsic_get_buffer_size:
1708 emit_intrinsic_ssbo_size(ctx, intr, dst);
1709 break;
1710 case nir_intrinsic_ssbo_atomic_add_ir3:
1711 case nir_intrinsic_ssbo_atomic_imin_ir3:
1712 case nir_intrinsic_ssbo_atomic_umin_ir3:
1713 case nir_intrinsic_ssbo_atomic_imax_ir3:
1714 case nir_intrinsic_ssbo_atomic_umax_ir3:
1715 case nir_intrinsic_ssbo_atomic_and_ir3:
1716 case nir_intrinsic_ssbo_atomic_or_ir3:
1717 case nir_intrinsic_ssbo_atomic_xor_ir3:
1718 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1719 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1720 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1721 !ctx->s->info.fs.early_fragment_tests)
1722 ctx->so->no_earlyz = true;
1723 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1724 break;
1725 case nir_intrinsic_load_shared:
1726 emit_intrinsic_load_shared(ctx, intr, dst);
1727 break;
1728 case nir_intrinsic_store_shared:
1729 emit_intrinsic_store_shared(ctx, intr);
1730 break;
1731 case nir_intrinsic_shared_atomic_add:
1732 case nir_intrinsic_shared_atomic_imin:
1733 case nir_intrinsic_shared_atomic_umin:
1734 case nir_intrinsic_shared_atomic_imax:
1735 case nir_intrinsic_shared_atomic_umax:
1736 case nir_intrinsic_shared_atomic_and:
1737 case nir_intrinsic_shared_atomic_or:
1738 case nir_intrinsic_shared_atomic_xor:
1739 case nir_intrinsic_shared_atomic_exchange:
1740 case nir_intrinsic_shared_atomic_comp_swap:
1741 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1742 break;
1743 case nir_intrinsic_image_load:
1744 emit_intrinsic_load_image(ctx, intr, dst);
1745 break;
1746 case nir_intrinsic_bindless_image_load:
1747 /* Bindless uses the IBO state, which doesn't have swizzle filled out,
1748 * so using isam doesn't work.
1749 *
1750 * TODO: can we use isam if we fill out more fields?
1751 */
1752 ctx->funcs->emit_intrinsic_load_image(ctx, intr, dst);
1753 break;
1754 case nir_intrinsic_image_store:
1755 case nir_intrinsic_bindless_image_store:
1756 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1757 !ctx->s->info.fs.early_fragment_tests)
1758 ctx->so->no_earlyz = true;
1759 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1760 break;
1761 case nir_intrinsic_image_size:
1762 case nir_intrinsic_bindless_image_size:
1763 emit_intrinsic_image_size(ctx, intr, dst);
1764 break;
1765 case nir_intrinsic_image_atomic_add:
1766 case nir_intrinsic_bindless_image_atomic_add:
1767 case nir_intrinsic_image_atomic_imin:
1768 case nir_intrinsic_bindless_image_atomic_imin:
1769 case nir_intrinsic_image_atomic_umin:
1770 case nir_intrinsic_bindless_image_atomic_umin:
1771 case nir_intrinsic_image_atomic_imax:
1772 case nir_intrinsic_bindless_image_atomic_imax:
1773 case nir_intrinsic_image_atomic_umax:
1774 case nir_intrinsic_bindless_image_atomic_umax:
1775 case nir_intrinsic_image_atomic_and:
1776 case nir_intrinsic_bindless_image_atomic_and:
1777 case nir_intrinsic_image_atomic_or:
1778 case nir_intrinsic_bindless_image_atomic_or:
1779 case nir_intrinsic_image_atomic_xor:
1780 case nir_intrinsic_bindless_image_atomic_xor:
1781 case nir_intrinsic_image_atomic_exchange:
1782 case nir_intrinsic_bindless_image_atomic_exchange:
1783 case nir_intrinsic_image_atomic_comp_swap:
1784 case nir_intrinsic_bindless_image_atomic_comp_swap:
1785 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1786 !ctx->s->info.fs.early_fragment_tests)
1787 ctx->so->no_earlyz = true;
1788 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1789 break;
1790 case nir_intrinsic_control_barrier:
1791 case nir_intrinsic_memory_barrier:
1792 case nir_intrinsic_group_memory_barrier:
1793 case nir_intrinsic_memory_barrier_buffer:
1794 case nir_intrinsic_memory_barrier_image:
1795 case nir_intrinsic_memory_barrier_shared:
1796 emit_intrinsic_barrier(ctx, intr);
1797 /* note that blk ptr no longer valid, make that obvious: */
1798 b = NULL;
1799 break;
1800 case nir_intrinsic_store_output:
1801 idx = nir_intrinsic_base(intr);
1802 comp = nir_intrinsic_component(intr);
1803 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1804 idx += nir_src_as_uint(intr->src[1]);
1805
1806 src = ir3_get_src(ctx, &intr->src[0]);
1807 for (int i = 0; i < intr->num_components; i++) {
1808 unsigned n = idx * 4 + i + comp;
1809 ctx->outputs[n] = src[i];
1810 }
1811 break;
1812 case nir_intrinsic_load_base_vertex:
1813 case nir_intrinsic_load_first_vertex:
1814 if (!ctx->basevertex) {
1815 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1816 }
1817 dst[0] = ctx->basevertex;
1818 break;
1819 case nir_intrinsic_load_base_instance:
1820 if (!ctx->base_instance) {
1821 ctx->base_instance = create_driver_param(ctx, IR3_DP_INSTID_BASE);
1822 }
1823 dst[0] = ctx->base_instance;
1824 break;
1825 case nir_intrinsic_load_vertex_id_zero_base:
1826 case nir_intrinsic_load_vertex_id:
1827 if (!ctx->vertex_id) {
1828 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1829 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1830 ctx->vertex_id = create_sysval_input(ctx, sv, 0x1);
1831 }
1832 dst[0] = ctx->vertex_id;
1833 break;
1834 case nir_intrinsic_load_instance_id:
1835 if (!ctx->instance_id) {
1836 ctx->instance_id = create_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID, 0x1);
1837 }
1838 dst[0] = ctx->instance_id;
1839 break;
1840 case nir_intrinsic_load_sample_id:
1841 ctx->so->per_samp = true;
1842 /* fall-thru */
1843 case nir_intrinsic_load_sample_id_no_per_sample:
1844 if (!ctx->samp_id) {
1845 ctx->samp_id = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID, 0x1);
1846 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1847 }
1848 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1849 break;
1850 case nir_intrinsic_load_sample_mask_in:
1851 if (!ctx->samp_mask_in) {
1852 ctx->samp_mask_in = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN, 0x1);
1853 }
1854 dst[0] = ctx->samp_mask_in;
1855 break;
1856 case nir_intrinsic_load_user_clip_plane:
1857 idx = nir_intrinsic_ucp_id(intr);
1858 for (int i = 0; i < intr->num_components; i++) {
1859 unsigned n = idx * 4 + i;
1860 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1861 }
1862 break;
1863 case nir_intrinsic_load_front_face:
1864 if (!ctx->frag_face) {
1865 ctx->so->frag_face = true;
1866 ctx->frag_face = create_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, 0x1);
1867 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1868 }
1869 /* for fragface, we get -1 for back and 0 for front. However this is
1870 * the inverse of what nir expects (where ~0 is true).
1871 */
1872 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1873 dst[0] = ir3_NOT_B(b, dst[0], 0);
1874 break;
1875 case nir_intrinsic_load_local_invocation_id:
1876 if (!ctx->local_invocation_id) {
1877 ctx->local_invocation_id =
1878 create_sysval_input(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID, 0x7);
1879 }
1880 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1881 break;
1882 case nir_intrinsic_load_work_group_id:
1883 if (!ctx->work_group_id) {
1884 ctx->work_group_id =
1885 create_sysval_input(ctx, SYSTEM_VALUE_WORK_GROUP_ID, 0x7);
1886 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1887 }
1888 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1889 break;
1890 case nir_intrinsic_load_num_work_groups:
1891 for (int i = 0; i < intr->num_components; i++) {
1892 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1893 }
1894 break;
1895 case nir_intrinsic_load_local_group_size:
1896 for (int i = 0; i < intr->num_components; i++) {
1897 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1898 }
1899 break;
1900 case nir_intrinsic_discard_if:
1901 case nir_intrinsic_discard: {
1902 struct ir3_instruction *cond, *kill;
1903
1904 if (intr->intrinsic == nir_intrinsic_discard_if) {
1905 /* conditional discard: */
1906 src = ir3_get_src(ctx, &intr->src[0]);
1907 cond = ir3_b2n(b, src[0]);
1908 } else {
1909 /* unconditional discard: */
1910 cond = create_immed(b, 1);
1911 }
1912
1913 /* NOTE: only cmps.*.* can write p0.x: */
1914 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1915 cond->cat2.condition = IR3_COND_NE;
1916
1917 /* condition always goes in predicate register: */
1918 cond->regs[0]->num = regid(REG_P0, 0);
1919 cond->regs[0]->flags &= ~IR3_REG_SSA;
1920
1921 kill = ir3_KILL(b, cond, 0);
1922 kill->regs[1]->num = regid(REG_P0, 0);
1923 array_insert(ctx->ir, ctx->ir->predicates, kill);
1924
1925 array_insert(b, b->keeps, kill);
1926 ctx->so->no_earlyz = true;
1927
1928 break;
1929 }
1930
1931 case nir_intrinsic_cond_end_ir3: {
1932 struct ir3_instruction *cond, *kill;
1933
1934 src = ir3_get_src(ctx, &intr->src[0]);
1935 cond = ir3_b2n(b, src[0]);
1936
1937 /* NOTE: only cmps.*.* can write p0.x: */
1938 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1939 cond->cat2.condition = IR3_COND_NE;
1940
1941 /* condition always goes in predicate register: */
1942 cond->regs[0]->num = regid(REG_P0, 0);
1943
1944 kill = ir3_IF(b, cond, 0);
1945
1946 kill->barrier_class = IR3_BARRIER_EVERYTHING;
1947 kill->barrier_conflict = IR3_BARRIER_EVERYTHING;
1948
1949 array_insert(ctx->ir, ctx->ir->predicates, kill);
1950 array_insert(b, b->keeps, kill);
1951 break;
1952 }
1953
1954 case nir_intrinsic_load_shared_ir3:
1955 emit_intrinsic_load_shared_ir3(ctx, intr, dst);
1956 break;
1957 case nir_intrinsic_store_shared_ir3:
1958 emit_intrinsic_store_shared_ir3(ctx, intr);
1959 break;
1960 case nir_intrinsic_bindless_resource_ir3:
1961 dst[0] = ir3_get_src(ctx, &intr->src[0])[0];
1962 break;
1963 default:
1964 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1965 nir_intrinsic_infos[intr->intrinsic].name);
1966 break;
1967 }
1968
1969 if (info->has_dest)
1970 ir3_put_dst(ctx, &intr->dest);
1971 }
1972
1973 static void
1974 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1975 {
1976 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1977 instr->def.num_components);
1978
1979 if (instr->def.bit_size < 32) {
1980 for (int i = 0; i < instr->def.num_components; i++)
1981 dst[i] = create_immed_typed(ctx->block,
1982 instr->value[i].u16,
1983 TYPE_U16);
1984 } else {
1985 for (int i = 0; i < instr->def.num_components; i++)
1986 dst[i] = create_immed_typed(ctx->block,
1987 instr->value[i].u32,
1988 TYPE_U32);
1989 }
1990
1991 }
1992
1993 static void
1994 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1995 {
1996 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1997 undef->def.num_components);
1998 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1999
2000 /* backend doesn't want undefined instructions, so just plug
2001 * in 0.0..
2002 */
2003 for (int i = 0; i < undef->def.num_components; i++)
2004 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
2005 }
2006
2007 /*
2008 * texture fetch/sample instructions:
2009 */
2010
2011 static type_t
2012 get_tex_dest_type(nir_tex_instr *tex)
2013 {
2014 type_t type;
2015
2016 switch (nir_alu_type_get_base_type(tex->dest_type)) {
2017 case nir_type_invalid:
2018 case nir_type_float:
2019 type = nir_dest_bit_size(tex->dest) < 32 ? TYPE_F16 : TYPE_F32;
2020 break;
2021 case nir_type_int:
2022 type = nir_dest_bit_size(tex->dest) < 32 ? TYPE_S16 : TYPE_S32;
2023 break;
2024 case nir_type_uint:
2025 case nir_type_bool:
2026 type = nir_dest_bit_size(tex->dest) < 32 ? TYPE_U16 : TYPE_U32;
2027 break;
2028 default:
2029 unreachable("bad dest_type");
2030 }
2031
2032 return type;
2033 }
2034
2035 static void
2036 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
2037 {
2038 unsigned coords = glsl_get_sampler_dim_coordinate_components(tex->sampler_dim);
2039 unsigned flags = 0;
2040
2041 /* note: would use tex->coord_components.. except txs.. also,
2042 * since array index goes after shadow ref, we don't want to
2043 * count it:
2044 */
2045 if (coords == 3)
2046 flags |= IR3_INSTR_3D;
2047
2048 if (tex->is_shadow && tex->op != nir_texop_lod)
2049 flags |= IR3_INSTR_S;
2050
2051 if (tex->is_array && tex->op != nir_texop_lod)
2052 flags |= IR3_INSTR_A;
2053
2054 *flagsp = flags;
2055 *coordsp = coords;
2056 }
2057
2058 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
2059 * or immediate (in which case it will get lowered later to a non .s2en
2060 * version of the tex instruction which encode tex/samp as immediates:
2061 */
2062 static struct tex_src_info
2063 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
2064 {
2065 struct ir3_block *b = ctx->block;
2066 struct tex_src_info info = { 0 };
2067 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_handle);
2068 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_handle);
2069 struct ir3_instruction *texture, *sampler;
2070
2071 if (texture_idx >= 0 || sampler_idx >= 0) {
2072 /* Bindless case */
2073 info.flags |= IR3_INSTR_B;
2074
2075 /* Gather information required to determine which encoding to
2076 * choose as well as for prefetch.
2077 */
2078 nir_intrinsic_instr *bindless_tex = NULL;
2079 bool tex_const;
2080 if (texture_idx >= 0) {
2081 ctx->so->bindless_tex = true;
2082 bindless_tex = ir3_bindless_resource(tex->src[texture_idx].src);
2083 assert(bindless_tex);
2084 info.tex_base = nir_intrinsic_desc_set(bindless_tex);
2085 tex_const = nir_src_is_const(bindless_tex->src[0]);
2086 if (tex_const)
2087 info.tex_idx = nir_src_as_uint(bindless_tex->src[0]);
2088 } else {
2089 /* To simplify some of the logic below, assume the index is
2090 * constant 0 when it's not enabled.
2091 */
2092 tex_const = true;
2093 info.tex_idx = 0;
2094 }
2095 nir_intrinsic_instr *bindless_samp = NULL;
2096 bool samp_const;
2097 if (sampler_idx >= 0) {
2098 ctx->so->bindless_samp = true;
2099 bindless_samp = ir3_bindless_resource(tex->src[sampler_idx].src);
2100 assert(bindless_samp);
2101 info.samp_base = nir_intrinsic_desc_set(bindless_samp);
2102 samp_const = nir_src_is_const(bindless_samp->src[0]);
2103 if (samp_const)
2104 info.samp_idx = nir_src_as_uint(bindless_samp->src[0]);
2105 } else {
2106 samp_const = true;
2107 info.samp_idx = 0;
2108 }
2109
2110 /* Choose encoding. */
2111 if (tex_const && samp_const && info.tex_idx < 256 && info.samp_idx < 256) {
2112 if (info.tex_idx < 16 && info.samp_idx < 16 &&
2113 (!bindless_tex || !bindless_samp || info.tex_base == info.samp_base)) {
2114 /* Everything fits within the instruction */
2115 info.base = info.tex_base;
2116 info.combined_idx = info.samp_idx | (info.tex_idx << 4);
2117 } else {
2118 info.base = info.tex_base;
2119 info.a1_val = info.tex_idx << 3 | info.samp_base;
2120 info.combined_idx = info.samp_idx;
2121 info.flags |= IR3_INSTR_A1EN;
2122 }
2123 info.samp_tex = NULL;
2124 } else {
2125 info.flags |= IR3_INSTR_S2EN;
2126 /* In the indirect case, we only use a1.x to store the sampler
2127 * base if it differs from the texture base.
2128 */
2129 if (!bindless_tex || !bindless_samp || info.tex_base == info.samp_base) {
2130 info.base = info.tex_base;
2131 } else {
2132 info.base = info.tex_base;
2133 info.a1_val = info.samp_base;
2134 info.flags |= IR3_INSTR_A1EN;
2135 }
2136
2137 /* Note: the indirect source is now a vec2 instead of hvec2, and
2138 * for some reason the texture and sampler are swapped.
2139 */
2140 struct ir3_instruction *texture, *sampler;
2141
2142 if (bindless_tex) {
2143 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
2144 } else {
2145 texture = create_immed(b, 0);
2146 }
2147
2148 if (bindless_samp) {
2149 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
2150 } else {
2151 sampler = create_immed(b, 0);
2152 }
2153 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2154 texture,
2155 sampler,
2156 }, 2);
2157 }
2158 } else {
2159 info.flags |= IR3_INSTR_S2EN;
2160 texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
2161 sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
2162 if (texture_idx >= 0) {
2163 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
2164 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
2165 } else {
2166 /* TODO what to do for dynamic case? I guess we only need the
2167 * max index for astc srgb workaround so maybe not a problem
2168 * to worry about if we don't enable indirect samplers for
2169 * a4xx?
2170 */
2171 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
2172 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
2173 info.tex_idx = tex->texture_index;
2174 }
2175
2176 if (sampler_idx >= 0) {
2177 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
2178 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
2179 } else {
2180 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
2181 info.samp_idx = tex->texture_index;
2182 }
2183
2184 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2185 sampler,
2186 texture,
2187 }, 2);
2188 }
2189
2190 return info;
2191 }
2192
2193 static void
2194 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
2195 {
2196 struct ir3_block *b = ctx->block;
2197 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
2198 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
2199 struct ir3_instruction *lod, *compare, *proj, *sample_index;
2200 struct tex_src_info info = { 0 };
2201 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
2202 unsigned i, coords, flags, ncomp;
2203 unsigned nsrc0 = 0, nsrc1 = 0;
2204 type_t type;
2205 opc_t opc = 0;
2206
2207 ncomp = nir_dest_num_components(tex->dest);
2208
2209 coord = off = ddx = ddy = NULL;
2210 lod = proj = compare = sample_index = NULL;
2211
2212 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
2213
2214 for (unsigned i = 0; i < tex->num_srcs; i++) {
2215 switch (tex->src[i].src_type) {
2216 case nir_tex_src_coord:
2217 coord = ir3_get_src(ctx, &tex->src[i].src);
2218 break;
2219 case nir_tex_src_bias:
2220 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
2221 has_bias = true;
2222 break;
2223 case nir_tex_src_lod:
2224 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
2225 has_lod = true;
2226 break;
2227 case nir_tex_src_comparator: /* shadow comparator */
2228 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
2229 break;
2230 case nir_tex_src_projector:
2231 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
2232 has_proj = true;
2233 break;
2234 case nir_tex_src_offset:
2235 off = ir3_get_src(ctx, &tex->src[i].src);
2236 has_off = true;
2237 break;
2238 case nir_tex_src_ddx:
2239 ddx = ir3_get_src(ctx, &tex->src[i].src);
2240 break;
2241 case nir_tex_src_ddy:
2242 ddy = ir3_get_src(ctx, &tex->src[i].src);
2243 break;
2244 case nir_tex_src_ms_index:
2245 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
2246 break;
2247 case nir_tex_src_texture_offset:
2248 case nir_tex_src_sampler_offset:
2249 case nir_tex_src_texture_handle:
2250 case nir_tex_src_sampler_handle:
2251 /* handled in get_tex_samp_src() */
2252 break;
2253 default:
2254 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
2255 tex->src[i].src_type);
2256 return;
2257 }
2258 }
2259
2260 switch (tex->op) {
2261 case nir_texop_tex_prefetch:
2262 compile_assert(ctx, !has_bias);
2263 compile_assert(ctx, !has_lod);
2264 compile_assert(ctx, !compare);
2265 compile_assert(ctx, !has_proj);
2266 compile_assert(ctx, !has_off);
2267 compile_assert(ctx, !ddx);
2268 compile_assert(ctx, !ddy);
2269 compile_assert(ctx, !sample_index);
2270 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_texture_offset) < 0);
2271 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset) < 0);
2272
2273 if (ctx->so->num_sampler_prefetch < IR3_MAX_SAMPLER_PREFETCH) {
2274 opc = OPC_META_TEX_PREFETCH;
2275 ctx->so->num_sampler_prefetch++;
2276 break;
2277 }
2278 /* fallthru */
2279 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
2280 case nir_texop_txb: opc = OPC_SAMB; break;
2281 case nir_texop_txl: opc = OPC_SAML; break;
2282 case nir_texop_txd: opc = OPC_SAMGQ; break;
2283 case nir_texop_txf: opc = OPC_ISAML; break;
2284 case nir_texop_lod: opc = OPC_GETLOD; break;
2285 case nir_texop_tg4:
2286 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2287 * what blob does, seems gather is broken?), and a3xx did
2288 * not support it (but probably could also emulate).
2289 */
2290 switch (tex->component) {
2291 case 0: opc = OPC_GATHER4R; break;
2292 case 1: opc = OPC_GATHER4G; break;
2293 case 2: opc = OPC_GATHER4B; break;
2294 case 3: opc = OPC_GATHER4A; break;
2295 }
2296 break;
2297 case nir_texop_txf_ms_fb:
2298 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
2299 default:
2300 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
2301 return;
2302 }
2303
2304 tex_info(tex, &flags, &coords);
2305
2306 /*
2307 * lay out the first argument in the proper order:
2308 * - actual coordinates first
2309 * - shadow reference
2310 * - array index
2311 * - projection w
2312 * - starting at offset 4, dpdx.xy, dpdy.xy
2313 *
2314 * bias/lod go into the second arg
2315 */
2316
2317 /* insert tex coords: */
2318 for (i = 0; i < coords; i++)
2319 src0[i] = coord[i];
2320
2321 nsrc0 = i;
2322
2323 /* scale up integer coords for TXF based on the LOD */
2324 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
2325 assert(has_lod);
2326 for (i = 0; i < coords; i++)
2327 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
2328 }
2329
2330 if (coords == 1) {
2331 /* hw doesn't do 1d, so we treat it as 2d with
2332 * height of 1, and patch up the y coord.
2333 */
2334 if (is_isam(opc)) {
2335 src0[nsrc0++] = create_immed(b, 0);
2336 } else {
2337 src0[nsrc0++] = create_immed(b, fui(0.5));
2338 }
2339 }
2340
2341 if (tex->is_shadow && tex->op != nir_texop_lod)
2342 src0[nsrc0++] = compare;
2343
2344 if (tex->is_array && tex->op != nir_texop_lod) {
2345 struct ir3_instruction *idx = coord[coords];
2346
2347 /* the array coord for cube arrays needs 0.5 added to it */
2348 if (ctx->compiler->array_index_add_half && !is_isam(opc))
2349 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
2350
2351 src0[nsrc0++] = idx;
2352 }
2353
2354 if (has_proj) {
2355 src0[nsrc0++] = proj;
2356 flags |= IR3_INSTR_P;
2357 }
2358
2359 /* pad to 4, then ddx/ddy: */
2360 if (tex->op == nir_texop_txd) {
2361 while (nsrc0 < 4)
2362 src0[nsrc0++] = create_immed(b, fui(0.0));
2363 for (i = 0; i < coords; i++)
2364 src0[nsrc0++] = ddx[i];
2365 if (coords < 2)
2366 src0[nsrc0++] = create_immed(b, fui(0.0));
2367 for (i = 0; i < coords; i++)
2368 src0[nsrc0++] = ddy[i];
2369 if (coords < 2)
2370 src0[nsrc0++] = create_immed(b, fui(0.0));
2371 }
2372
2373 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2374 * with scaled x coord according to requested sample:
2375 */
2376 if (opc == OPC_ISAMM) {
2377 if (ctx->compiler->txf_ms_with_isaml) {
2378 /* the samples are laid out in x dimension as
2379 * 0 1 2 3
2380 * x_ms = (x << ms) + sample_index;
2381 */
2382 struct ir3_instruction *ms;
2383 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
2384
2385 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
2386 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
2387
2388 opc = OPC_ISAML;
2389 } else {
2390 src0[nsrc0++] = sample_index;
2391 }
2392 }
2393
2394 /*
2395 * second argument (if applicable):
2396 * - offsets
2397 * - lod
2398 * - bias
2399 */
2400 if (has_off | has_lod | has_bias) {
2401 if (has_off) {
2402 unsigned off_coords = coords;
2403 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2404 off_coords--;
2405 for (i = 0; i < off_coords; i++)
2406 src1[nsrc1++] = off[i];
2407 if (off_coords < 2)
2408 src1[nsrc1++] = create_immed(b, fui(0.0));
2409 flags |= IR3_INSTR_O;
2410 }
2411
2412 if (has_lod | has_bias)
2413 src1[nsrc1++] = lod;
2414 }
2415
2416 type = get_tex_dest_type(tex);
2417
2418 if (opc == OPC_GETLOD)
2419 type = TYPE_S32;
2420
2421
2422 if (tex->op == nir_texop_txf_ms_fb) {
2423 /* only expect a single txf_ms_fb per shader: */
2424 compile_assert(ctx, !ctx->so->fb_read);
2425 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
2426
2427 ctx->so->fb_read = true;
2428 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2429 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2430 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2431 }, 2);
2432 info.flags = IR3_INSTR_S2EN;
2433
2434 ctx->so->num_samp++;
2435 } else {
2436 info = get_tex_samp_tex_src(ctx, tex);
2437 }
2438
2439 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
2440 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
2441
2442 if (opc == OPC_META_TEX_PREFETCH) {
2443 int idx = nir_tex_instr_src_index(tex, nir_tex_src_coord);
2444
2445 compile_assert(ctx, tex->src[idx].src.is_ssa);
2446
2447 sam = ir3_META_TEX_PREFETCH(b);
2448 __ssa_dst(sam)->wrmask = MASK(ncomp); /* dst */
2449 __ssa_src(sam, get_barycentric_pixel(ctx), 0);
2450 sam->prefetch.input_offset =
2451 ir3_nir_coord_offset(tex->src[idx].src.ssa);
2452 /* make sure not to add irrelevant flags like S2EN */
2453 sam->flags = flags | (info.flags & IR3_INSTR_B);
2454 sam->prefetch.tex = info.tex_idx;
2455 sam->prefetch.samp = info.samp_idx;
2456 sam->prefetch.tex_base = info.tex_base;
2457 sam->prefetch.samp_base = info.samp_base;
2458 } else {
2459 info.flags |= flags;
2460 sam = emit_sam(ctx, opc, info, type, MASK(ncomp), col0, col1);
2461 }
2462
2463 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
2464 assert(opc != OPC_META_TEX_PREFETCH);
2465
2466 /* only need first 3 components: */
2467 sam->regs[0]->wrmask = 0x7;
2468 ir3_split_dest(b, dst, sam, 0, 3);
2469
2470 /* we need to sample the alpha separately with a non-ASTC
2471 * texture state:
2472 */
2473 sam = ir3_SAM(b, opc, type, 0b1000, flags | info.flags,
2474 info.samp_tex, col0, col1);
2475
2476 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
2477
2478 /* fixup .w component: */
2479 ir3_split_dest(b, &dst[3], sam, 3, 1);
2480 } else {
2481 /* normal (non-workaround) case: */
2482 ir3_split_dest(b, dst, sam, 0, ncomp);
2483 }
2484
2485 /* GETLOD returns results in 4.8 fixed point */
2486 if (opc == OPC_GETLOD) {
2487 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
2488
2489 compile_assert(ctx, tex->dest_type == nir_type_float);
2490 for (i = 0; i < 2; i++) {
2491 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_S32, TYPE_F32), 0,
2492 factor, 0);
2493 }
2494 }
2495
2496 ir3_put_dst(ctx, &tex->dest);
2497 }
2498
2499 static void
2500 emit_tex_info(struct ir3_context *ctx, nir_tex_instr *tex, unsigned idx)
2501 {
2502 struct ir3_block *b = ctx->block;
2503 struct ir3_instruction **dst, *sam;
2504 type_t dst_type = get_tex_dest_type(tex);
2505 struct tex_src_info info = get_tex_samp_tex_src(ctx, tex);
2506
2507 dst = ir3_get_dst(ctx, &tex->dest, 1);
2508
2509 sam = emit_sam(ctx, OPC_GETINFO, info, dst_type, 1 << idx, NULL, NULL);
2510
2511 /* even though there is only one component, since it ends
2512 * up in .y/.z/.w rather than .x, we need a split_dest()
2513 */
2514 ir3_split_dest(b, dst, sam, idx, 1);
2515
2516 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2517 * the value in TEX_CONST_0 is zero-based.
2518 */
2519 if (ctx->compiler->levels_add_one)
2520 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2521
2522 ir3_put_dst(ctx, &tex->dest);
2523 }
2524
2525 static void
2526 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2527 {
2528 struct ir3_block *b = ctx->block;
2529 struct ir3_instruction **dst, *sam;
2530 struct ir3_instruction *lod;
2531 unsigned flags, coords;
2532 type_t dst_type = get_tex_dest_type(tex);
2533 struct tex_src_info info = get_tex_samp_tex_src(ctx, tex);
2534
2535 tex_info(tex, &flags, &coords);
2536 info.flags |= flags;
2537
2538 /* Actually we want the number of dimensions, not coordinates. This
2539 * distinction only matters for cubes.
2540 */
2541 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2542 coords = 2;
2543
2544 dst = ir3_get_dst(ctx, &tex->dest, 4);
2545
2546 int lod_idx = nir_tex_instr_src_index(tex, nir_tex_src_lod);
2547 compile_assert(ctx, lod_idx >= 0);
2548
2549 lod = ir3_get_src(ctx, &tex->src[lod_idx].src)[0];
2550
2551 sam = emit_sam(ctx, OPC_GETSIZE, info, dst_type, 0b1111, lod, NULL);
2552 ir3_split_dest(b, dst, sam, 0, 4);
2553
2554 /* Array size actually ends up in .w rather than .z. This doesn't
2555 * matter for miplevel 0, but for higher mips the value in z is
2556 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2557 * returned, which means that we have to add 1 to it for arrays.
2558 */
2559 if (tex->is_array) {
2560 if (ctx->compiler->levels_add_one) {
2561 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2562 } else {
2563 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2564 }
2565 }
2566
2567 ir3_put_dst(ctx, &tex->dest);
2568 }
2569
2570 static void
2571 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2572 {
2573 switch (jump->type) {
2574 case nir_jump_break:
2575 case nir_jump_continue:
2576 case nir_jump_return:
2577 /* I *think* we can simply just ignore this, and use the
2578 * successor block link to figure out where we need to
2579 * jump to for break/continue
2580 */
2581 break;
2582 default:
2583 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2584 break;
2585 }
2586 }
2587
2588 static void
2589 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2590 {
2591 switch (instr->type) {
2592 case nir_instr_type_alu:
2593 emit_alu(ctx, nir_instr_as_alu(instr));
2594 break;
2595 case nir_instr_type_deref:
2596 /* ignored, handled as part of the intrinsic they are src to */
2597 break;
2598 case nir_instr_type_intrinsic:
2599 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2600 break;
2601 case nir_instr_type_load_const:
2602 emit_load_const(ctx, nir_instr_as_load_const(instr));
2603 break;
2604 case nir_instr_type_ssa_undef:
2605 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2606 break;
2607 case nir_instr_type_tex: {
2608 nir_tex_instr *tex = nir_instr_as_tex(instr);
2609 /* couple tex instructions get special-cased:
2610 */
2611 switch (tex->op) {
2612 case nir_texop_txs:
2613 emit_tex_txs(ctx, tex);
2614 break;
2615 case nir_texop_query_levels:
2616 emit_tex_info(ctx, tex, 2);
2617 break;
2618 case nir_texop_texture_samples:
2619 emit_tex_info(ctx, tex, 3);
2620 break;
2621 default:
2622 emit_tex(ctx, tex);
2623 break;
2624 }
2625 break;
2626 }
2627 case nir_instr_type_jump:
2628 emit_jump(ctx, nir_instr_as_jump(instr));
2629 break;
2630 case nir_instr_type_phi:
2631 /* we have converted phi webs to regs in NIR by now */
2632 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2633 break;
2634 case nir_instr_type_call:
2635 case nir_instr_type_parallel_copy:
2636 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2637 break;
2638 }
2639 }
2640
2641 static struct ir3_block *
2642 get_block(struct ir3_context *ctx, const nir_block *nblock)
2643 {
2644 struct ir3_block *block;
2645 struct hash_entry *hentry;
2646
2647 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2648 if (hentry)
2649 return hentry->data;
2650
2651 block = ir3_block_create(ctx->ir);
2652 block->nblock = nblock;
2653 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2654
2655 block->predecessors = _mesa_pointer_set_create(block);
2656 set_foreach(nblock->predecessors, sentry) {
2657 _mesa_set_add(block->predecessors, get_block(ctx, sentry->key));
2658 }
2659
2660 return block;
2661 }
2662
2663 static void
2664 emit_block(struct ir3_context *ctx, nir_block *nblock)
2665 {
2666 struct ir3_block *block = get_block(ctx, nblock);
2667
2668 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2669 if (nblock->successors[i]) {
2670 block->successors[i] =
2671 get_block(ctx, nblock->successors[i]);
2672 }
2673 }
2674
2675 ctx->block = block;
2676 list_addtail(&block->node, &ctx->ir->block_list);
2677
2678 /* re-emit addr register in each block if needed: */
2679 for (int i = 0; i < ARRAY_SIZE(ctx->addr0_ht); i++) {
2680 _mesa_hash_table_destroy(ctx->addr0_ht[i], NULL);
2681 ctx->addr0_ht[i] = NULL;
2682 }
2683
2684 _mesa_hash_table_u64_destroy(ctx->addr1_ht, NULL);
2685 ctx->addr1_ht = NULL;
2686
2687 nir_foreach_instr (instr, nblock) {
2688 ctx->cur_instr = instr;
2689 emit_instr(ctx, instr);
2690 ctx->cur_instr = NULL;
2691 if (ctx->error)
2692 return;
2693 }
2694
2695 _mesa_hash_table_clear(ctx->sel_cond_conversions, NULL);
2696 }
2697
2698 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2699
2700 static void
2701 emit_if(struct ir3_context *ctx, nir_if *nif)
2702 {
2703 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2704
2705 ctx->block->condition =
2706 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
2707
2708 emit_cf_list(ctx, &nif->then_list);
2709 emit_cf_list(ctx, &nif->else_list);
2710 }
2711
2712 static void
2713 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2714 {
2715 emit_cf_list(ctx, &nloop->body);
2716 ctx->so->loops++;
2717 }
2718
2719 static void
2720 stack_push(struct ir3_context *ctx)
2721 {
2722 ctx->stack++;
2723 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2724 }
2725
2726 static void
2727 stack_pop(struct ir3_context *ctx)
2728 {
2729 compile_assert(ctx, ctx->stack > 0);
2730 ctx->stack--;
2731 }
2732
2733 static void
2734 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2735 {
2736 foreach_list_typed (nir_cf_node, node, node, list) {
2737 switch (node->type) {
2738 case nir_cf_node_block:
2739 emit_block(ctx, nir_cf_node_as_block(node));
2740 break;
2741 case nir_cf_node_if:
2742 stack_push(ctx);
2743 emit_if(ctx, nir_cf_node_as_if(node));
2744 stack_pop(ctx);
2745 break;
2746 case nir_cf_node_loop:
2747 stack_push(ctx);
2748 emit_loop(ctx, nir_cf_node_as_loop(node));
2749 stack_pop(ctx);
2750 break;
2751 case nir_cf_node_function:
2752 ir3_context_error(ctx, "TODO\n");
2753 break;
2754 }
2755 }
2756 }
2757
2758 /* emit stream-out code. At this point, the current block is the original
2759 * (nir) end block, and nir ensures that all flow control paths terminate
2760 * into the end block. We re-purpose the original end block to generate
2761 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2762 * block holding stream-out write instructions, followed by the new end
2763 * block:
2764 *
2765 * blockOrigEnd {
2766 * p0.x = (vtxcnt < maxvtxcnt)
2767 * // succs: blockStreamOut, blockNewEnd
2768 * }
2769 * blockStreamOut {
2770 * ... stream-out instructions ...
2771 * // succs: blockNewEnd
2772 * }
2773 * blockNewEnd {
2774 * }
2775 */
2776 static void
2777 emit_stream_out(struct ir3_context *ctx)
2778 {
2779 struct ir3 *ir = ctx->ir;
2780 struct ir3_stream_output_info *strmout =
2781 &ctx->so->shader->stream_output;
2782 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2783 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2784 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2785
2786 /* create vtxcnt input in input block at top of shader,
2787 * so that it is seen as live over the entire duration
2788 * of the shader:
2789 */
2790 vtxcnt = create_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, 0x1);
2791 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2792
2793 /* at this point, we are at the original 'end' block,
2794 * re-purpose this block to stream-out condition, then
2795 * append stream-out block and new-end block
2796 */
2797 orig_end_block = ctx->block;
2798
2799 // TODO these blocks need to update predecessors..
2800 // maybe w/ store_global intrinsic, we could do this
2801 // stuff in nir->nir pass
2802
2803 stream_out_block = ir3_block_create(ir);
2804 list_addtail(&stream_out_block->node, &ir->block_list);
2805
2806 new_end_block = ir3_block_create(ir);
2807 list_addtail(&new_end_block->node, &ir->block_list);
2808
2809 orig_end_block->successors[0] = stream_out_block;
2810 orig_end_block->successors[1] = new_end_block;
2811 stream_out_block->successors[0] = new_end_block;
2812
2813 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2814 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2815 cond->regs[0]->num = regid(REG_P0, 0);
2816 cond->regs[0]->flags &= ~IR3_REG_SSA;
2817 cond->cat2.condition = IR3_COND_LT;
2818
2819 /* condition goes on previous block to the conditional,
2820 * since it is used to pick which of the two successor
2821 * paths to take:
2822 */
2823 orig_end_block->condition = cond;
2824
2825 /* switch to stream_out_block to generate the stream-out
2826 * instructions:
2827 */
2828 ctx->block = stream_out_block;
2829
2830 /* Calculate base addresses based on vtxcnt. Instructions
2831 * generated for bases not used in following loop will be
2832 * stripped out in the backend.
2833 */
2834 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2835 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
2836 unsigned stride = strmout->stride[i];
2837 struct ir3_instruction *base, *off;
2838
2839 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
2840
2841 /* 24-bit should be enough: */
2842 off = ir3_MUL_U24(ctx->block, vtxcnt, 0,
2843 create_immed(ctx->block, stride * 4), 0);
2844
2845 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2846 }
2847
2848 /* Generate the per-output store instructions: */
2849 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2850 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2851 unsigned c = j + strmout->output[i].start_component;
2852 struct ir3_instruction *base, *out, *stg;
2853
2854 base = bases[strmout->output[i].output_buffer];
2855 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2856
2857 stg = ir3_STG(ctx->block, base, 0, out, 0,
2858 create_immed(ctx->block, 1), 0);
2859 stg->cat6.type = TYPE_U32;
2860 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2861
2862 array_insert(ctx->block, ctx->block->keeps, stg);
2863 }
2864 }
2865
2866 /* and finally switch to the new_end_block: */
2867 ctx->block = new_end_block;
2868 }
2869
2870 static void
2871 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2872 {
2873 nir_metadata_require(impl, nir_metadata_block_index);
2874
2875 compile_assert(ctx, ctx->stack == 0);
2876
2877 emit_cf_list(ctx, &impl->body);
2878 emit_block(ctx, impl->end_block);
2879
2880 compile_assert(ctx, ctx->stack == 0);
2881
2882 /* at this point, we should have a single empty block,
2883 * into which we emit the 'end' instruction.
2884 */
2885 compile_assert(ctx, list_is_empty(&ctx->block->instr_list));
2886
2887 /* If stream-out (aka transform-feedback) enabled, emit the
2888 * stream-out instructions, followed by a new empty block (into
2889 * which the 'end' instruction lands).
2890 *
2891 * NOTE: it is done in this order, rather than inserting before
2892 * we emit end_block, because NIR guarantees that all blocks
2893 * flow into end_block, and that end_block has no successors.
2894 * So by re-purposing end_block as the first block of stream-
2895 * out, we guarantee that all exit paths flow into the stream-
2896 * out instructions.
2897 */
2898 if ((ctx->compiler->gpu_id < 500) &&
2899 (ctx->so->shader->stream_output.num_outputs > 0) &&
2900 !ctx->so->binning_pass) {
2901 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2902 emit_stream_out(ctx);
2903 }
2904
2905 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2906 * NOP and has an epilogue that writes the VS outputs to local storage, to
2907 * be read by the HS. Then it resets execution mask (chmask) and chains
2908 * to the next shader (chsh).
2909 */
2910 if ((ctx->so->type == MESA_SHADER_VERTEX &&
2911 (ctx->so->key.has_gs || ctx->so->key.tessellation)) ||
2912 (ctx->so->type == MESA_SHADER_TESS_EVAL && ctx->so->key.has_gs)) {
2913 struct ir3_instruction *chmask =
2914 ir3_CHMASK(ctx->block);
2915 chmask->barrier_class = IR3_BARRIER_EVERYTHING;
2916 chmask->barrier_conflict = IR3_BARRIER_EVERYTHING;
2917
2918 struct ir3_instruction *chsh =
2919 ir3_CHSH(ctx->block);
2920 chsh->barrier_class = IR3_BARRIER_EVERYTHING;
2921 chsh->barrier_conflict = IR3_BARRIER_EVERYTHING;
2922 } else {
2923 ir3_END(ctx->block);
2924 }
2925 }
2926
2927 static void
2928 setup_input(struct ir3_context *ctx, nir_variable *in)
2929 {
2930 struct ir3_shader_variant *so = ctx->so;
2931 unsigned ncomp = glsl_get_components(in->type);
2932 unsigned n = in->data.driver_location;
2933 unsigned frac = in->data.location_frac;
2934 unsigned slot = in->data.location;
2935
2936 /* Inputs are loaded using ldlw or ldg for these stages. */
2937 if (ctx->so->type == MESA_SHADER_TESS_CTRL ||
2938 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2939 ctx->so->type == MESA_SHADER_GEOMETRY)
2940 return;
2941
2942 /* skip unread inputs, we could end up with (for example), unsplit
2943 * matrix/etc inputs in the case they are not read, so just silently
2944 * skip these.
2945 */
2946 if (ncomp > 4)
2947 return;
2948
2949 so->inputs[n].slot = slot;
2950 so->inputs[n].compmask |= (1 << (ncomp + frac)) - 1;
2951 so->inputs_count = MAX2(so->inputs_count, n + 1);
2952 so->inputs[n].interpolate = in->data.interpolation;
2953
2954 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2955
2956 /* if any varyings have 'sample' qualifer, that triggers us
2957 * to run in per-sample mode:
2958 */
2959 so->per_samp |= in->data.sample;
2960
2961 for (int i = 0; i < ncomp; i++) {
2962 struct ir3_instruction *instr = NULL;
2963 unsigned idx = (n * 4) + i + frac;
2964
2965 if (slot == VARYING_SLOT_POS) {
2966 ir3_context_error(ctx, "fragcoord should be a sysval!\n");
2967 } else if (slot == VARYING_SLOT_PNTC) {
2968 /* see for example st_nir_fixup_varying_slots().. this is
2969 * maybe a bit mesa/st specific. But we need things to line
2970 * up for this in fdN_program:
2971 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2972 * if (emit->sprite_coord_enable & texmask) {
2973 * ...
2974 * }
2975 */
2976 so->inputs[n].slot = VARYING_SLOT_VAR8;
2977 so->inputs[n].bary = true;
2978 instr = create_frag_input(ctx, false, idx);
2979 } else {
2980 /* detect the special case for front/back colors where
2981 * we need to do flat vs smooth shading depending on
2982 * rast state:
2983 */
2984 if (in->data.interpolation == INTERP_MODE_NONE) {
2985 switch (slot) {
2986 case VARYING_SLOT_COL0:
2987 case VARYING_SLOT_COL1:
2988 case VARYING_SLOT_BFC0:
2989 case VARYING_SLOT_BFC1:
2990 so->inputs[n].rasterflat = true;
2991 break;
2992 default:
2993 break;
2994 }
2995 }
2996
2997 if (ctx->compiler->flat_bypass) {
2998 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2999 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
3000 so->inputs[n].use_ldlv = true;
3001 }
3002
3003 so->inputs[n].bary = true;
3004
3005 instr = create_frag_input(ctx, so->inputs[n].use_ldlv, idx);
3006 }
3007
3008 compile_assert(ctx, idx < ctx->ninputs);
3009
3010 ctx->inputs[idx] = instr;
3011 }
3012 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
3013 struct ir3_instruction *input = NULL, *in;
3014 struct ir3_instruction *components[4];
3015 unsigned mask = (1 << (ncomp + frac)) - 1;
3016
3017 foreach_input (in, ctx->ir) {
3018 if (in->input.inidx == n) {
3019 input = in;
3020 break;
3021 }
3022 }
3023
3024 if (!input) {
3025 input = create_input(ctx, mask);
3026 input->input.inidx = n;
3027 } else {
3028 input->regs[0]->wrmask |= mask;
3029 }
3030
3031 ir3_split_dest(ctx->block, components, input, frac, ncomp);
3032
3033 for (int i = 0; i < ncomp; i++) {
3034 unsigned idx = (n * 4) + i + frac;
3035 compile_assert(ctx, idx < ctx->ninputs);
3036 ctx->inputs[idx] = components[i];
3037 }
3038 } else {
3039 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
3040 }
3041
3042 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
3043 so->total_in += ncomp;
3044 }
3045 }
3046
3047 /* Initially we assign non-packed inloc's for varyings, as we don't really
3048 * know up-front which components will be unused. After all the compilation
3049 * stages we scan the shader to see which components are actually used, and
3050 * re-pack the inlocs to eliminate unneeded varyings.
3051 */
3052 static void
3053 pack_inlocs(struct ir3_context *ctx)
3054 {
3055 struct ir3_shader_variant *so = ctx->so;
3056 uint8_t used_components[so->inputs_count];
3057
3058 memset(used_components, 0, sizeof(used_components));
3059
3060 /*
3061 * First Step: scan shader to find which bary.f/ldlv remain:
3062 */
3063
3064 foreach_block (block, &ctx->ir->block_list) {
3065 foreach_instr (instr, &block->instr_list) {
3066 if (is_input(instr)) {
3067 unsigned inloc = instr->regs[1]->iim_val;
3068 unsigned i = inloc / 4;
3069 unsigned j = inloc % 4;
3070
3071 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
3072 compile_assert(ctx, i < so->inputs_count);
3073
3074 used_components[i] |= 1 << j;
3075 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
3076 for (int n = 0; n < 2; n++) {
3077 unsigned inloc = instr->prefetch.input_offset + n;
3078 unsigned i = inloc / 4;
3079 unsigned j = inloc % 4;
3080
3081 compile_assert(ctx, i < so->inputs_count);
3082
3083 used_components[i] |= 1 << j;
3084 }
3085 }
3086 }
3087 }
3088
3089 /*
3090 * Second Step: reassign varying inloc/slots:
3091 */
3092
3093 unsigned actual_in = 0;
3094 unsigned inloc = 0;
3095
3096 for (unsigned i = 0; i < so->inputs_count; i++) {
3097 unsigned compmask = 0, maxcomp = 0;
3098
3099 so->inputs[i].inloc = inloc;
3100 so->inputs[i].bary = false;
3101
3102 for (unsigned j = 0; j < 4; j++) {
3103 if (!(used_components[i] & (1 << j)))
3104 continue;
3105
3106 compmask |= (1 << j);
3107 actual_in++;
3108 maxcomp = j + 1;
3109
3110 /* at this point, since used_components[i] mask is only
3111 * considering varyings (ie. not sysvals) we know this
3112 * is a varying:
3113 */
3114 so->inputs[i].bary = true;
3115 }
3116
3117 if (so->inputs[i].bary) {
3118 so->varying_in++;
3119 so->inputs[i].compmask = (1 << maxcomp) - 1;
3120 inloc += maxcomp;
3121 }
3122 }
3123
3124 /*
3125 * Third Step: reassign packed inloc's:
3126 */
3127
3128 foreach_block (block, &ctx->ir->block_list) {
3129 foreach_instr (instr, &block->instr_list) {
3130 if (is_input(instr)) {
3131 unsigned inloc = instr->regs[1]->iim_val;
3132 unsigned i = inloc / 4;
3133 unsigned j = inloc % 4;
3134
3135 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
3136 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
3137 unsigned i = instr->prefetch.input_offset / 4;
3138 unsigned j = instr->prefetch.input_offset % 4;
3139 instr->prefetch.input_offset = so->inputs[i].inloc + j;
3140 }
3141 }
3142 }
3143 }
3144
3145 static void
3146 setup_output(struct ir3_context *ctx, nir_variable *out)
3147 {
3148 struct ir3_shader_variant *so = ctx->so;
3149 unsigned ncomp = glsl_get_components(out->type);
3150 unsigned n = out->data.driver_location;
3151 unsigned frac = out->data.location_frac;
3152 unsigned slot = out->data.location;
3153 unsigned comp = 0;
3154
3155 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3156 switch (slot) {
3157 case FRAG_RESULT_DEPTH:
3158 comp = 2; /* tgsi will write to .z component */
3159 so->writes_pos = true;
3160 break;
3161 case FRAG_RESULT_COLOR:
3162 so->color0_mrt = 1;
3163 break;
3164 case FRAG_RESULT_SAMPLE_MASK:
3165 so->writes_smask = true;
3166 break;
3167 default:
3168 if (slot >= FRAG_RESULT_DATA0)
3169 break;
3170 ir3_context_error(ctx, "unknown FS output name: %s\n",
3171 gl_frag_result_name(slot));
3172 }
3173 } else if (ctx->so->type == MESA_SHADER_VERTEX ||
3174 ctx->so->type == MESA_SHADER_TESS_EVAL ||
3175 ctx->so->type == MESA_SHADER_GEOMETRY) {
3176 switch (slot) {
3177 case VARYING_SLOT_POS:
3178 so->writes_pos = true;
3179 break;
3180 case VARYING_SLOT_PSIZ:
3181 so->writes_psize = true;
3182 break;
3183 case VARYING_SLOT_PRIMITIVE_ID:
3184 case VARYING_SLOT_LAYER:
3185 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
3186 debug_assert(ctx->so->type == MESA_SHADER_GEOMETRY);
3187 /* fall through */
3188 case VARYING_SLOT_COL0:
3189 case VARYING_SLOT_COL1:
3190 case VARYING_SLOT_BFC0:
3191 case VARYING_SLOT_BFC1:
3192 case VARYING_SLOT_FOGC:
3193 case VARYING_SLOT_CLIP_DIST0:
3194 case VARYING_SLOT_CLIP_DIST1:
3195 case VARYING_SLOT_CLIP_VERTEX:
3196 break;
3197 default:
3198 if (slot >= VARYING_SLOT_VAR0)
3199 break;
3200 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
3201 break;
3202 ir3_context_error(ctx, "unknown %s shader output name: %s\n",
3203 _mesa_shader_stage_to_string(ctx->so->type),
3204 gl_varying_slot_name(slot));
3205 }
3206 } else if (ctx->so->type == MESA_SHADER_TESS_CTRL) {
3207 /* output lowered to buffer writes. */
3208 return;
3209 } else {
3210 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
3211 }
3212
3213 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
3214
3215 so->outputs[n].slot = slot;
3216 so->outputs[n].regid = regid(n, comp);
3217 so->outputs_count = MAX2(so->outputs_count, n + 1);
3218
3219 for (int i = 0; i < ncomp; i++) {
3220 unsigned idx = (n * 4) + i + frac;
3221 compile_assert(ctx, idx < ctx->noutputs);
3222 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
3223 }
3224
3225 /* if varying packing doesn't happen, we could end up in a situation
3226 * with "holes" in the output, and since the per-generation code that
3227 * sets up varying linkage registers doesn't expect to have more than
3228 * one varying per vec4 slot, pad the holes.
3229 *
3230 * Note that this should probably generate a performance warning of
3231 * some sort.
3232 */
3233 for (int i = 0; i < frac; i++) {
3234 unsigned idx = (n * 4) + i;
3235 if (!ctx->outputs[idx]) {
3236 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
3237 }
3238 }
3239 }
3240
3241 static int
3242 max_drvloc(struct exec_list *vars)
3243 {
3244 int drvloc = -1;
3245 nir_foreach_variable (var, vars) {
3246 drvloc = MAX2(drvloc, (int)var->data.driver_location);
3247 }
3248 return drvloc;
3249 }
3250
3251 static void
3252 emit_instructions(struct ir3_context *ctx)
3253 {
3254 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
3255
3256 ctx->ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4;
3257 ctx->noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4;
3258
3259 ctx->inputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->ninputs);
3260 ctx->outputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->noutputs);
3261
3262 ctx->ir = ir3_create(ctx->compiler, ctx->so->type);
3263
3264 /* Create inputs in first block: */
3265 ctx->block = get_block(ctx, nir_start_block(fxn));
3266 ctx->in_block = ctx->block;
3267 list_addtail(&ctx->block->node, &ctx->ir->block_list);
3268
3269 /* for fragment shader, the vcoord input register is used as the
3270 * base for bary.f varying fetch instrs:
3271 *
3272 * TODO defer creating ctx->ij_pixel and corresponding sysvals
3273 * until emit_intrinsic when we know they are actually needed.
3274 * For now, we defer creating ctx->ij_centroid, etc, since we
3275 * only need ij_pixel for "old style" varying inputs (ie.
3276 * tgsi_to_nir)
3277 */
3278 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3279 ctx->ij_pixel = create_input(ctx, 0x3);
3280 }
3281
3282 /* Setup inputs: */
3283 nir_foreach_variable (var, &ctx->s->inputs) {
3284 setup_input(ctx, var);
3285 }
3286
3287 /* Defer add_sysval_input() stuff until after setup_inputs(),
3288 * because sysvals need to be appended after varyings:
3289 */
3290 if (ctx->ij_pixel) {
3291 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL,
3292 0x3, ctx->ij_pixel);
3293 }
3294
3295
3296 /* Tesselation shaders always need primitive ID for indexing the
3297 * BO. Geometry shaders don't always need it but when they do it has be
3298 * delivered and unclobbered in the VS. To make things easy, we always
3299 * make room for it in VS/DS.
3300 */
3301 bool has_tess = ctx->so->key.tessellation != IR3_TESS_NONE;
3302 bool has_gs = ctx->so->key.has_gs;
3303 switch (ctx->so->type) {
3304 case MESA_SHADER_VERTEX:
3305 if (has_tess) {
3306 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3307 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3308 } else if (has_gs) {
3309 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3310 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3311 }
3312 break;
3313 case MESA_SHADER_TESS_CTRL:
3314 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3315 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3316 break;
3317 case MESA_SHADER_TESS_EVAL:
3318 if (has_gs)
3319 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3320 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3321 break;
3322 case MESA_SHADER_GEOMETRY:
3323 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3324 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3325 break;
3326 default:
3327 break;
3328 }
3329
3330 /* Setup outputs: */
3331 nir_foreach_variable (var, &ctx->s->outputs) {
3332 setup_output(ctx, var);
3333 }
3334
3335 /* Find # of samplers: */
3336 nir_foreach_variable (var, &ctx->s->uniforms) {
3337 ctx->so->num_samp += glsl_type_get_sampler_count(var->type);
3338 /* just assume that we'll be reading from images.. if it
3339 * is write-only we don't have to count it, but not sure
3340 * if there is a good way to know?
3341 */
3342 ctx->so->num_samp += glsl_type_get_image_count(var->type);
3343 }
3344
3345 /* NOTE: need to do something more clever when we support >1 fxn */
3346 nir_foreach_register (reg, &fxn->registers) {
3347 ir3_declare_array(ctx, reg);
3348 }
3349 /* And emit the body: */
3350 ctx->impl = fxn;
3351 emit_function(ctx, fxn);
3352 }
3353
3354 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3355 * need to assign the tex state indexes for these after we know the
3356 * max tex index.
3357 */
3358 static void
3359 fixup_astc_srgb(struct ir3_context *ctx)
3360 {
3361 struct ir3_shader_variant *so = ctx->so;
3362 /* indexed by original tex idx, value is newly assigned alpha sampler
3363 * state tex idx. Zero is invalid since there is at least one sampler
3364 * if we get here.
3365 */
3366 unsigned alt_tex_state[16] = {0};
3367 unsigned tex_idx = ctx->max_texture_index + 1;
3368 unsigned idx = 0;
3369
3370 so->astc_srgb.base = tex_idx;
3371
3372 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
3373 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
3374
3375 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
3376
3377 if (alt_tex_state[sam->cat5.tex] == 0) {
3378 /* assign new alternate/alpha tex state slot: */
3379 alt_tex_state[sam->cat5.tex] = tex_idx++;
3380 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
3381 so->astc_srgb.count++;
3382 }
3383
3384 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
3385 }
3386 }
3387
3388 static void
3389 fixup_binning_pass(struct ir3_context *ctx)
3390 {
3391 struct ir3_shader_variant *so = ctx->so;
3392 struct ir3 *ir = ctx->ir;
3393 unsigned i, j;
3394
3395 /* first pass, remove unused outputs from the IR level outputs: */
3396 for (i = 0, j = 0; i < ir->outputs_count; i++) {
3397 struct ir3_instruction *out = ir->outputs[i];
3398 assert(out->opc == OPC_META_COLLECT);
3399 unsigned outidx = out->collect.outidx;
3400 unsigned slot = so->outputs[outidx].slot;
3401
3402 /* throw away everything but first position/psize */
3403 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3404 ir->outputs[j] = ir->outputs[i];
3405 j++;
3406 }
3407 }
3408 ir->outputs_count = j;
3409
3410 /* second pass, cleanup the unused slots in ir3_shader_variant::outputs
3411 * table:
3412 */
3413 for (i = 0, j = 0; i < so->outputs_count; i++) {
3414 unsigned slot = so->outputs[i].slot;
3415
3416 /* throw away everything but first position/psize */
3417 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3418 so->outputs[j] = so->outputs[i];
3419
3420 /* fixup outidx to point to new output table entry: */
3421 struct ir3_instruction *out;
3422 foreach_output (out, ir) {
3423 if (out->collect.outidx == i) {
3424 out->collect.outidx = j;
3425 break;
3426 }
3427 }
3428
3429 j++;
3430 }
3431 }
3432 so->outputs_count = j;
3433 }
3434
3435 static void
3436 collect_tex_prefetches(struct ir3_context *ctx, struct ir3 *ir)
3437 {
3438 unsigned idx = 0;
3439
3440 /* Collect sampling instructions eligible for pre-dispatch. */
3441 foreach_block (block, &ir->block_list) {
3442 foreach_instr_safe (instr, &block->instr_list) {
3443 if (instr->opc == OPC_META_TEX_PREFETCH) {
3444 assert(idx < ARRAY_SIZE(ctx->so->sampler_prefetch));
3445 struct ir3_sampler_prefetch *fetch =
3446 &ctx->so->sampler_prefetch[idx];
3447 idx++;
3448
3449 if (instr->flags & IR3_INSTR_B) {
3450 fetch->cmd = IR3_SAMPLER_BINDLESS_PREFETCH_CMD;
3451 /* In bindless mode, the index is actually the base */
3452 fetch->tex_id = instr->prefetch.tex_base;
3453 fetch->samp_id = instr->prefetch.samp_base;
3454 fetch->tex_bindless_id = instr->prefetch.tex;
3455 fetch->samp_bindless_id = instr->prefetch.samp;
3456 } else {
3457 fetch->cmd = IR3_SAMPLER_PREFETCH_CMD;
3458 fetch->tex_id = instr->prefetch.tex;
3459 fetch->samp_id = instr->prefetch.samp;
3460 }
3461 fetch->wrmask = instr->regs[0]->wrmask;
3462 fetch->dst = instr->regs[0]->num;
3463 fetch->src = instr->prefetch.input_offset;
3464
3465 ctx->so->total_in =
3466 MAX2(ctx->so->total_in, instr->prefetch.input_offset + 2);
3467
3468 /* Disable half precision until supported. */
3469 fetch->half_precision = !!(instr->regs[0]->flags & IR3_REG_HALF);
3470
3471 /* Remove the prefetch placeholder instruction: */
3472 list_delinit(&instr->node);
3473 }
3474 }
3475 }
3476 }
3477
3478 int
3479 ir3_compile_shader_nir(struct ir3_compiler *compiler,
3480 struct ir3_shader_variant *so)
3481 {
3482 struct ir3_context *ctx;
3483 struct ir3 *ir;
3484 int ret = 0, max_bary;
3485
3486 assert(!so->ir);
3487
3488 ctx = ir3_context_init(compiler, so);
3489 if (!ctx) {
3490 DBG("INIT failed!");
3491 ret = -1;
3492 goto out;
3493 }
3494
3495 emit_instructions(ctx);
3496
3497 if (ctx->error) {
3498 DBG("EMIT failed!");
3499 ret = -1;
3500 goto out;
3501 }
3502
3503 ir = so->ir = ctx->ir;
3504
3505 assert((ctx->noutputs % 4) == 0);
3506
3507 /* Setup IR level outputs, which are "collects" that gather
3508 * the scalar components of outputs.
3509 */
3510 for (unsigned i = 0; i < ctx->noutputs; i += 4) {
3511 unsigned ncomp = 0;
3512 /* figure out the # of components written:
3513 *
3514 * TODO do we need to handle holes, ie. if .x and .z
3515 * components written, but .y component not written?
3516 */
3517 for (unsigned j = 0; j < 4; j++) {
3518 if (!ctx->outputs[i + j])
3519 break;
3520 ncomp++;
3521 }
3522
3523 /* Note that in some stages, like TCS, store_output is
3524 * lowered to memory writes, so no components of the
3525 * are "written" from the PoV of traditional store-
3526 * output instructions:
3527 */
3528 if (!ncomp)
3529 continue;
3530
3531 struct ir3_instruction *out =
3532 ir3_create_collect(ctx, &ctx->outputs[i], ncomp);
3533
3534 int outidx = i / 4;
3535 assert(outidx < so->outputs_count);
3536
3537 /* stash index into so->outputs[] so we can map the
3538 * output back to slot/etc later:
3539 */
3540 out->collect.outidx = outidx;
3541
3542 array_insert(ir, ir->outputs, out);
3543 }
3544
3545 /* Set up the gs header as an output for the vertex shader so it won't
3546 * clobber it for the tess ctrl shader.
3547 *
3548 * TODO this could probably be done more cleanly in a nir pass.
3549 */
3550 if (ctx->so->type == MESA_SHADER_VERTEX ||
3551 (ctx->so->key.has_gs && ctx->so->type == MESA_SHADER_TESS_EVAL)) {
3552 if (ctx->primitive_id) {
3553 unsigned n = so->outputs_count++;
3554 so->outputs[n].slot = VARYING_SLOT_PRIMITIVE_ID;
3555
3556 struct ir3_instruction *out =
3557 ir3_create_collect(ctx, &ctx->primitive_id, 1);
3558 out->collect.outidx = n;
3559 array_insert(ir, ir->outputs, out);
3560 }
3561
3562 if (ctx->gs_header) {
3563 unsigned n = so->outputs_count++;
3564 so->outputs[n].slot = VARYING_SLOT_GS_HEADER_IR3;
3565 struct ir3_instruction *out =
3566 ir3_create_collect(ctx, &ctx->gs_header, 1);
3567 out->collect.outidx = n;
3568 array_insert(ir, ir->outputs, out);
3569 }
3570
3571 if (ctx->tcs_header) {
3572 unsigned n = so->outputs_count++;
3573 so->outputs[n].slot = VARYING_SLOT_TCS_HEADER_IR3;
3574 struct ir3_instruction *out =
3575 ir3_create_collect(ctx, &ctx->tcs_header, 1);
3576 out->collect.outidx = n;
3577 array_insert(ir, ir->outputs, out);
3578 }
3579 }
3580
3581 /* at this point, for binning pass, throw away unneeded outputs: */
3582 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
3583 fixup_binning_pass(ctx);
3584
3585 ir3_debug_print(ir, "BEFORE CF");
3586
3587 ir3_cf(ir);
3588
3589 ir3_debug_print(ir, "BEFORE CP");
3590
3591 ir3_cp(ir, so);
3592
3593 /* at this point, for binning pass, throw away unneeded outputs:
3594 * Note that for a6xx and later, we do this after ir3_cp to ensure
3595 * that the uniform/constant layout for BS and VS matches, so that
3596 * we can re-use same VS_CONST state group.
3597 */
3598 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
3599 fixup_binning_pass(ctx);
3600
3601 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3602 * need to make sure not to remove any inputs that are used by
3603 * the nonbinning VS.
3604 */
3605 if (ctx->compiler->gpu_id >= 600 && so->binning_pass &&
3606 so->type == MESA_SHADER_VERTEX) {
3607 for (int i = 0; i < ctx->ninputs; i++) {
3608 struct ir3_instruction *in = ctx->inputs[i];
3609
3610 if (!in)
3611 continue;
3612
3613 unsigned n = i / 4;
3614 unsigned c = i % 4;
3615
3616 debug_assert(n < so->nonbinning->inputs_count);
3617
3618 if (so->nonbinning->inputs[n].sysval)
3619 continue;
3620
3621 /* be sure to keep inputs, even if only used in VS */
3622 if (so->nonbinning->inputs[n].compmask & (1 << c))
3623 array_insert(in->block, in->block->keeps, in);
3624 }
3625 }
3626
3627 ir3_debug_print(ir, "BEFORE GROUPING");
3628
3629 ir3_sched_add_deps(ir);
3630
3631 /* Group left/right neighbors, inserting mov's where needed to
3632 * solve conflicts:
3633 */
3634 ir3_group(ir);
3635
3636 ir3_debug_print(ir, "AFTER GROUPING");
3637
3638 ir3_dce(ir, so);
3639
3640 ir3_debug_print(ir, "AFTER DCE");
3641
3642 /* do Sethi–Ullman numbering before scheduling: */
3643 ir3_sun(ir);
3644
3645 ret = ir3_sched(ir);
3646 if (ret) {
3647 DBG("SCHED failed!");
3648 goto out;
3649 }
3650
3651 ir3_debug_print(ir, "AFTER SCHED");
3652
3653 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3654 * with draw pass VS, so binning and draw pass can both use the
3655 * same VBO state.
3656 *
3657 * Note that VS inputs are expected to be full precision.
3658 */
3659 bool pre_assign_inputs = (ir->compiler->gpu_id >= 600) &&
3660 (ir->type == MESA_SHADER_VERTEX) &&
3661 so->binning_pass;
3662
3663 if (pre_assign_inputs) {
3664 for (unsigned i = 0; i < ctx->ninputs; i++) {
3665 struct ir3_instruction *instr = ctx->inputs[i];
3666
3667 if (!instr)
3668 continue;
3669
3670 unsigned n = i / 4;
3671 unsigned c = i % 4;
3672 unsigned regid = so->nonbinning->inputs[n].regid + c;
3673
3674 instr->regs[0]->num = regid;
3675 }
3676
3677 ret = ir3_ra(so, ctx->inputs, ctx->ninputs);
3678 } else if (ctx->tcs_header) {
3679 /* We need to have these values in the same registers between VS and TCS
3680 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3681 */
3682
3683 ctx->tcs_header->regs[0]->num = regid(0, 0);
3684 ctx->primitive_id->regs[0]->num = regid(0, 1);
3685 struct ir3_instruction *precolor[] = { ctx->tcs_header, ctx->primitive_id };
3686 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3687 } else if (ctx->gs_header) {
3688 /* We need to have these values in the same registers between producer
3689 * (VS or DS) and GS since the producer chains to GS and doesn't get
3690 * the sysvals redelivered.
3691 */
3692
3693 ctx->gs_header->regs[0]->num = regid(0, 0);
3694 ctx->primitive_id->regs[0]->num = regid(0, 1);
3695 struct ir3_instruction *precolor[] = { ctx->gs_header, ctx->primitive_id };
3696 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3697 } else if (so->num_sampler_prefetch) {
3698 assert(so->type == MESA_SHADER_FRAGMENT);
3699 struct ir3_instruction *instr, *precolor[2];
3700 int idx = 0;
3701
3702 foreach_input (instr, ir) {
3703 if (instr->input.sysval != SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL)
3704 continue;
3705
3706 assert(idx < ARRAY_SIZE(precolor));
3707
3708 precolor[idx] = instr;
3709 instr->regs[0]->num = idx;
3710
3711 idx++;
3712 }
3713 ret = ir3_ra(so, precolor, idx);
3714 } else {
3715 ret = ir3_ra(so, NULL, 0);
3716 }
3717
3718 if (ret) {
3719 DBG("RA failed!");
3720 goto out;
3721 }
3722
3723 ir3_postsched(ctx);
3724 ir3_debug_print(ir, "AFTER POSTSCHED");
3725
3726 if (compiler->gpu_id >= 600) {
3727 if (ir3_a6xx_fixup_atomic_dests(ir, so)) {
3728 ir3_debug_print(ir, "AFTER ATOMIC FIXUP");
3729 }
3730 }
3731
3732 if (so->type == MESA_SHADER_FRAGMENT)
3733 pack_inlocs(ctx);
3734
3735 /*
3736 * Fixup inputs/outputs to point to the actual registers assigned:
3737 *
3738 * 1) initialize to r63.x (invalid/unused)
3739 * 2) iterate IR level inputs/outputs and update the variants
3740 * inputs/outputs table based on the assigned registers for
3741 * the remaining inputs/outputs.
3742 */
3743
3744 for (unsigned i = 0; i < so->inputs_count; i++)
3745 so->inputs[i].regid = INVALID_REG;
3746 for (unsigned i = 0; i < so->outputs_count; i++)
3747 so->outputs[i].regid = INVALID_REG;
3748
3749 struct ir3_instruction *out;
3750 foreach_output (out, ir) {
3751 assert(out->opc == OPC_META_COLLECT);
3752 unsigned outidx = out->collect.outidx;
3753
3754 so->outputs[outidx].regid = out->regs[0]->num;
3755 so->outputs[outidx].half = !!(out->regs[0]->flags & IR3_REG_HALF);
3756 }
3757
3758 struct ir3_instruction *in;
3759 foreach_input (in, ir) {
3760 assert(in->opc == OPC_META_INPUT);
3761 unsigned inidx = in->input.inidx;
3762
3763 if (pre_assign_inputs && !so->inputs[inidx].sysval) {
3764 if (VALIDREG(so->nonbinning->inputs[inidx].regid)) {
3765 compile_assert(ctx, in->regs[0]->num ==
3766 so->nonbinning->inputs[inidx].regid);
3767 compile_assert(ctx, !!(in->regs[0]->flags & IR3_REG_HALF) ==
3768 so->nonbinning->inputs[inidx].half);
3769 }
3770 so->inputs[inidx].regid = so->nonbinning->inputs[inidx].regid;
3771 so->inputs[inidx].half = so->nonbinning->inputs[inidx].half;
3772 } else {
3773 so->inputs[inidx].regid = in->regs[0]->num;
3774 so->inputs[inidx].half = !!(in->regs[0]->flags & IR3_REG_HALF);
3775 }
3776 }
3777
3778 if (ctx->astc_srgb)
3779 fixup_astc_srgb(ctx);
3780
3781 /* We need to do legalize after (for frag shader's) the "bary.f"
3782 * offsets (inloc) have been assigned.
3783 */
3784 ir3_legalize(ir, so, &max_bary);
3785
3786 ir3_debug_print(ir, "AFTER LEGALIZE");
3787
3788 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3789 * know what we might have to wait on when coming in from VS chsh.
3790 */
3791 if (so->type == MESA_SHADER_TESS_CTRL ||
3792 so->type == MESA_SHADER_GEOMETRY ) {
3793 foreach_block (block, &ir->block_list) {
3794 foreach_instr (instr, &block->instr_list) {
3795 instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
3796 break;
3797 }
3798 }
3799 }
3800
3801 so->branchstack = ctx->max_stack;
3802
3803 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3804 if (so->type == MESA_SHADER_FRAGMENT)
3805 so->total_in = max_bary + 1;
3806
3807 so->max_sun = ir->max_sun;
3808
3809 /* Collect sampling instructions eligible for pre-dispatch. */
3810 collect_tex_prefetches(ctx, ir);
3811
3812 if (so->type == MESA_SHADER_FRAGMENT &&
3813 ctx->s->info.fs.needs_helper_invocations)
3814 so->need_pixlod = true;
3815
3816 out:
3817 if (ret) {
3818 if (so->ir)
3819 ir3_destroy(so->ir);
3820 so->ir = NULL;
3821 }
3822 ir3_context_free(ctx);
3823
3824 return ret;
3825 }