projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
freedreno/ir3: add input/output iterators
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 __ssa_dst(mov);
55 src = __ssa_src(mov, collect, IR3_REG_RELATIV);
56 src->size = arrsz;
57 src->array.offset = n;
58
59 ir3_instr_set_address(mov, address);
60
61 return mov;
62 }
63
64 static struct ir3_instruction *
65 create_input_compmask(struct ir3_context *ctx, unsigned n, unsigned compmask)
66 {
67 struct ir3_instruction *in;
68
69 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
70 in->input.sysval = ~0;
71 __ssa_dst(in)->wrmask = compmask;
72
73 return in;
74 }
75
76 static struct ir3_instruction *
77 create_input(struct ir3_context *ctx, unsigned n)
78 {
79 return create_input_compmask(ctx, n, 0x1);
80 }
81
82 static struct ir3_instruction *
83 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
84 {
85 struct ir3_block *block = ctx->block;
86 struct ir3_instruction *instr;
87 /* packed inloc is fixed up later: */
88 struct ir3_instruction *inloc = create_immed(block, n);
89
90 if (use_ldlv) {
91 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
92 instr->cat6.type = TYPE_U32;
93 instr->cat6.iim_val = 1;
94 } else {
95 instr = ir3_BARY_F(block, inloc, 0, ctx->ij_pixel, 0);
96 instr->regs[2]->wrmask = 0x3;
97 }
98
99 return instr;
100 }
101
102 static struct ir3_instruction *
103 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
104 {
105 /* first four vec4 sysval's reserved for UBOs: */
106 /* NOTE: dp is in scalar, but there can be >4 dp components: */
107 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
108 unsigned n = const_state->offsets.driver_param;
109 unsigned r = regid(n + dp / 4, dp % 4);
110 return create_uniform(ctx->block, r);
111 }
112
113 /*
114 * Adreno uses uint rather than having dedicated bool type,
115 * which (potentially) requires some conversion, in particular
116 * when using output of an bool instr to int input, or visa
117 * versa.
118 *
119 * | Adreno | NIR |
120 * -------+---------+-------+-
121 * true | 1 | ~0 |
122 * false | 0 | 0 |
123 *
124 * To convert from an adreno bool (uint) to nir, use:
125 *
126 * absneg.s dst, (neg)src
127 *
128 * To convert back in the other direction:
129 *
130 * absneg.s dst, (abs)arc
131 *
132 * The CP step can clean up the absneg.s that cancel each other
133 * out, and with a slight bit of extra cleverness (to recognize
134 * the instructions which produce either a 0 or 1) can eliminate
135 * the absneg.s's completely when an instruction that wants
136 * 0/1 consumes the result. For example, when a nir 'bcsel'
137 * consumes the result of 'feq'. So we should be able to get by
138 * without a boolean resolve step, and without incuring any
139 * extra penalty in instruction count.
140 */
141
142 /* NIR bool -> native (adreno): */
143 static struct ir3_instruction *
144 ir3_b2n(struct ir3_block *block, struct ir3_instruction *instr)
145 {
146 return ir3_ABSNEG_S(block, instr, IR3_REG_SABS);
147 }
148
149 /* native (adreno) -> NIR bool: */
150 static struct ir3_instruction *
151 ir3_n2b(struct ir3_block *block, struct ir3_instruction *instr)
152 {
153 return ir3_ABSNEG_S(block, instr, IR3_REG_SNEG);
154 }
155
156 /*
157 * alu/sfu instructions:
158 */
159
160 static struct ir3_instruction *
161 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
162 unsigned src_bitsize, nir_op op)
163 {
164 type_t src_type, dst_type;
165
166 switch (op) {
167 case nir_op_f2f32:
168 case nir_op_f2f16_rtne:
169 case nir_op_f2f16_rtz:
170 case nir_op_f2f16:
171 case nir_op_f2i32:
172 case nir_op_f2i16:
173 case nir_op_f2i8:
174 case nir_op_f2u32:
175 case nir_op_f2u16:
176 case nir_op_f2u8:
177 switch (src_bitsize) {
178 case 32:
179 src_type = TYPE_F32;
180 break;
181 case 16:
182 src_type = TYPE_F16;
183 break;
184 default:
185 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
186 }
187 break;
188
189 case nir_op_i2f32:
190 case nir_op_i2f16:
191 case nir_op_i2i32:
192 case nir_op_i2i16:
193 case nir_op_i2i8:
194 switch (src_bitsize) {
195 case 32:
196 src_type = TYPE_S32;
197 break;
198 case 16:
199 src_type = TYPE_S16;
200 break;
201 case 8:
202 src_type = TYPE_S8;
203 break;
204 default:
205 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
206 }
207 break;
208
209 case nir_op_u2f32:
210 case nir_op_u2f16:
211 case nir_op_u2u32:
212 case nir_op_u2u16:
213 case nir_op_u2u8:
214 switch (src_bitsize) {
215 case 32:
216 src_type = TYPE_U32;
217 break;
218 case 16:
219 src_type = TYPE_U16;
220 break;
221 case 8:
222 src_type = TYPE_U8;
223 break;
224 default:
225 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
226 }
227 break;
228
229 default:
230 ir3_context_error(ctx, "invalid conversion op: %u", op);
231 }
232
233 switch (op) {
234 case nir_op_f2f32:
235 case nir_op_i2f32:
236 case nir_op_u2f32:
237 dst_type = TYPE_F32;
238 break;
239
240 case nir_op_f2f16_rtne:
241 case nir_op_f2f16_rtz:
242 case nir_op_f2f16:
243 /* TODO how to handle rounding mode? */
244 case nir_op_i2f16:
245 case nir_op_u2f16:
246 dst_type = TYPE_F16;
247 break;
248
249 case nir_op_f2i32:
250 case nir_op_i2i32:
251 dst_type = TYPE_S32;
252 break;
253
254 case nir_op_f2i16:
255 case nir_op_i2i16:
256 dst_type = TYPE_S16;
257 break;
258
259 case nir_op_f2i8:
260 case nir_op_i2i8:
261 dst_type = TYPE_S8;
262 break;
263
264 case nir_op_f2u32:
265 case nir_op_u2u32:
266 dst_type = TYPE_U32;
267 break;
268
269 case nir_op_f2u16:
270 case nir_op_u2u16:
271 dst_type = TYPE_U16;
272 break;
273
274 case nir_op_f2u8:
275 case nir_op_u2u8:
276 dst_type = TYPE_U8;
277 break;
278
279 default:
280 ir3_context_error(ctx, "invalid conversion op: %u", op);
281 }
282
283 return ir3_COV(ctx->block, src, src_type, dst_type);
284 }
285
286 static void
287 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
288 {
289 const nir_op_info *info = &nir_op_infos[alu->op];
290 struct ir3_instruction **dst, *src[info->num_inputs];
291 unsigned bs[info->num_inputs]; /* bit size */
292 struct ir3_block *b = ctx->block;
293 unsigned dst_sz, wrmask;
294 type_t dst_type = nir_dest_bit_size(alu->dest.dest) < 32 ?
295 TYPE_U16 : TYPE_U32;
296
297 if (alu->dest.dest.is_ssa) {
298 dst_sz = alu->dest.dest.ssa.num_components;
299 wrmask = (1 << dst_sz) - 1;
300 } else {
301 dst_sz = alu->dest.dest.reg.reg->num_components;
302 wrmask = alu->dest.write_mask;
303 }
304
305 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
306
307 /* Vectors are special in that they have non-scalarized writemasks,
308 * and just take the first swizzle channel for each argument in
309 * order into each writemask channel.
310 */
311 if ((alu->op == nir_op_vec2) ||
312 (alu->op == nir_op_vec3) ||
313 (alu->op == nir_op_vec4)) {
314
315 for (int i = 0; i < info->num_inputs; i++) {
316 nir_alu_src *asrc = &alu->src[i];
317
318 compile_assert(ctx, !asrc->abs);
319 compile_assert(ctx, !asrc->negate);
320
321 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
322 if (!src[i])
323 src[i] = create_immed_typed(ctx->block, 0, dst_type);
324 dst[i] = ir3_MOV(b, src[i], dst_type);
325 }
326
327 ir3_put_dst(ctx, &alu->dest.dest);
328 return;
329 }
330
331 /* We also get mov's with more than one component for mov's so
332 * handle those specially:
333 */
334 if (alu->op == nir_op_mov) {
335 nir_alu_src *asrc = &alu->src[0];
336 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
337
338 for (unsigned i = 0; i < dst_sz; i++) {
339 if (wrmask & (1 << i)) {
340 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
341 } else {
342 dst[i] = NULL;
343 }
344 }
345
346 ir3_put_dst(ctx, &alu->dest.dest);
347 return;
348 }
349
350 /* General case: We can just grab the one used channel per src. */
351 for (int i = 0; i < info->num_inputs; i++) {
352 unsigned chan = ffs(alu->dest.write_mask) - 1;
353 nir_alu_src *asrc = &alu->src[i];
354
355 compile_assert(ctx, !asrc->abs);
356 compile_assert(ctx, !asrc->negate);
357
358 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
359 bs[i] = nir_src_bit_size(asrc->src);
360
361 compile_assert(ctx, src[i]);
362 }
363
364 switch (alu->op) {
365 case nir_op_f2f32:
366 case nir_op_f2f16_rtne:
367 case nir_op_f2f16_rtz:
368 case nir_op_f2f16:
369 case nir_op_f2i32:
370 case nir_op_f2i16:
371 case nir_op_f2i8:
372 case nir_op_f2u32:
373 case nir_op_f2u16:
374 case nir_op_f2u8:
375 case nir_op_i2f32:
376 case nir_op_i2f16:
377 case nir_op_i2i32:
378 case nir_op_i2i16:
379 case nir_op_i2i8:
380 case nir_op_u2f32:
381 case nir_op_u2f16:
382 case nir_op_u2u32:
383 case nir_op_u2u16:
384 case nir_op_u2u8:
385 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
386 break;
387 case nir_op_fquantize2f16:
388 dst[0] = create_cov(ctx,
389 create_cov(ctx, src[0], 32, nir_op_f2f16),
390 16, nir_op_f2f32);
391 break;
392 case nir_op_f2b32:
393 dst[0] = ir3_CMPS_F(b, src[0], 0, create_immed(b, fui(0.0)), 0);
394 dst[0]->cat2.condition = IR3_COND_NE;
395 dst[0] = ir3_n2b(b, dst[0]);
396 break;
397 case nir_op_b2f16:
398 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F16);
399 break;
400 case nir_op_b2f32:
401 dst[0] = ir3_COV(b, ir3_b2n(b, src[0]), TYPE_U32, TYPE_F32);
402 break;
403 case nir_op_b2i8:
404 case nir_op_b2i16:
405 case nir_op_b2i32:
406 dst[0] = ir3_b2n(b, src[0]);
407 break;
408 case nir_op_i2b32:
409 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
410 dst[0]->cat2.condition = IR3_COND_NE;
411 dst[0] = ir3_n2b(b, dst[0]);
412 break;
413
414 case nir_op_fneg:
415 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
416 break;
417 case nir_op_fabs:
418 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
419 break;
420 case nir_op_fmax:
421 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
422 break;
423 case nir_op_fmin:
424 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
425 break;
426 case nir_op_fsat:
427 /* if there is just a single use of the src, and it supports
428 * (sat) bit, we can just fold the (sat) flag back to the
429 * src instruction and create a mov. This is easier for cp
430 * to eliminate.
431 *
432 * TODO probably opc_cat==4 is ok too
433 */
434 if (alu->src[0].src.is_ssa &&
435 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
436 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
437 src[0]->flags |= IR3_INSTR_SAT;
438 dst[0] = ir3_MOV(b, src[0], dst_type);
439 } else {
440 /* otherwise generate a max.f that saturates.. blob does
441 * similar (generating a cat2 mov using max.f)
442 */
443 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
444 dst[0]->flags |= IR3_INSTR_SAT;
445 }
446 break;
447 case nir_op_fmul:
448 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
449 break;
450 case nir_op_fadd:
451 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
452 break;
453 case nir_op_fsub:
454 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
455 break;
456 case nir_op_ffma:
457 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
458 break;
459 case nir_op_fddx:
460 case nir_op_fddx_coarse:
461 dst[0] = ir3_DSX(b, src[0], 0);
462 dst[0]->cat5.type = TYPE_F32;
463 break;
464 case nir_op_fddy:
465 case nir_op_fddy_coarse:
466 dst[0] = ir3_DSY(b, src[0], 0);
467 dst[0]->cat5.type = TYPE_F32;
468 break;
469 break;
470 case nir_op_flt32:
471 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
472 dst[0]->cat2.condition = IR3_COND_LT;
473 dst[0] = ir3_n2b(b, dst[0]);
474 break;
475 case nir_op_fge32:
476 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
477 dst[0]->cat2.condition = IR3_COND_GE;
478 dst[0] = ir3_n2b(b, dst[0]);
479 break;
480 case nir_op_feq32:
481 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
482 dst[0]->cat2.condition = IR3_COND_EQ;
483 dst[0] = ir3_n2b(b, dst[0]);
484 break;
485 case nir_op_fne32:
486 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
487 dst[0]->cat2.condition = IR3_COND_NE;
488 dst[0] = ir3_n2b(b, dst[0]);
489 break;
490 case nir_op_fceil:
491 dst[0] = ir3_CEIL_F(b, src[0], 0);
492 break;
493 case nir_op_ffloor:
494 dst[0] = ir3_FLOOR_F(b, src[0], 0);
495 break;
496 case nir_op_ftrunc:
497 dst[0] = ir3_TRUNC_F(b, src[0], 0);
498 break;
499 case nir_op_fround_even:
500 dst[0] = ir3_RNDNE_F(b, src[0], 0);
501 break;
502 case nir_op_fsign:
503 dst[0] = ir3_SIGN_F(b, src[0], 0);
504 break;
505
506 case nir_op_fsin:
507 dst[0] = ir3_SIN(b, src[0], 0);
508 break;
509 case nir_op_fcos:
510 dst[0] = ir3_COS(b, src[0], 0);
511 break;
512 case nir_op_frsq:
513 dst[0] = ir3_RSQ(b, src[0], 0);
514 break;
515 case nir_op_frcp:
516 dst[0] = ir3_RCP(b, src[0], 0);
517 break;
518 case nir_op_flog2:
519 dst[0] = ir3_LOG2(b, src[0], 0);
520 break;
521 case nir_op_fexp2:
522 dst[0] = ir3_EXP2(b, src[0], 0);
523 break;
524 case nir_op_fsqrt:
525 dst[0] = ir3_SQRT(b, src[0], 0);
526 break;
527
528 case nir_op_iabs:
529 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
530 break;
531 case nir_op_iadd:
532 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
533 break;
534 case nir_op_iand:
535 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
536 break;
537 case nir_op_imax:
538 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
539 break;
540 case nir_op_umax:
541 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
542 break;
543 case nir_op_imin:
544 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
545 break;
546 case nir_op_umin:
547 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
548 break;
549 case nir_op_umul_low:
550 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
551 break;
552 case nir_op_imadsh_mix16:
553 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
554 break;
555 case nir_op_imad24_ir3:
556 dst[0] = ir3_MAD_S24(b, src[0], 0, src[1], 0, src[2], 0);
557 break;
558 case nir_op_imul24:
559 dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
560 break;
561 case nir_op_ineg:
562 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
563 break;
564 case nir_op_inot:
565 dst[0] = ir3_NOT_B(b, src[0], 0);
566 break;
567 case nir_op_ior:
568 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
569 break;
570 case nir_op_ishl:
571 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
572 break;
573 case nir_op_ishr:
574 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
575 break;
576 case nir_op_isub:
577 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
578 break;
579 case nir_op_ixor:
580 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
581 break;
582 case nir_op_ushr:
583 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
584 break;
585 case nir_op_ilt32:
586 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
587 dst[0]->cat2.condition = IR3_COND_LT;
588 dst[0] = ir3_n2b(b, dst[0]);
589 break;
590 case nir_op_ige32:
591 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
592 dst[0]->cat2.condition = IR3_COND_GE;
593 dst[0] = ir3_n2b(b, dst[0]);
594 break;
595 case nir_op_ieq32:
596 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
597 dst[0]->cat2.condition = IR3_COND_EQ;
598 dst[0] = ir3_n2b(b, dst[0]);
599 break;
600 case nir_op_ine32:
601 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
602 dst[0]->cat2.condition = IR3_COND_NE;
603 dst[0] = ir3_n2b(b, dst[0]);
604 break;
605 case nir_op_ult32:
606 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
607 dst[0]->cat2.condition = IR3_COND_LT;
608 dst[0] = ir3_n2b(b, dst[0]);
609 break;
610 case nir_op_uge32:
611 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
612 dst[0]->cat2.condition = IR3_COND_GE;
613 dst[0] = ir3_n2b(b, dst[0]);
614 break;
615
616 case nir_op_b32csel: {
617 struct ir3_instruction *cond = ir3_b2n(b, src[0]);
618 compile_assert(ctx, bs[1] == bs[2]);
619 /* the boolean condition is 32b even if src[1] and src[2] are
620 * half-precision, but sel.b16 wants all three src's to be the
621 * same type.
622 */
623 if (bs[1] < 32)
624 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
625 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
626 break;
627 }
628 case nir_op_bit_count: {
629 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
630 // double check on earlier gen's. Once half-precision support is
631 // in place, this should probably move to a NIR lowering pass:
632 struct ir3_instruction *hi, *lo;
633
634 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
635 TYPE_U32, TYPE_U16);
636 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
637
638 hi = ir3_CBITS_B(b, hi, 0);
639 lo = ir3_CBITS_B(b, lo, 0);
640
641 // TODO maybe the builders should default to making dst half-precision
642 // if the src's were half precision, to make this less awkward.. otoh
643 // we should probably just do this lowering in NIR.
644 hi->regs[0]->flags |= IR3_REG_HALF;
645 lo->regs[0]->flags |= IR3_REG_HALF;
646
647 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
648 dst[0]->regs[0]->flags |= IR3_REG_HALF;
649 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
650 break;
651 }
652 case nir_op_ifind_msb: {
653 struct ir3_instruction *cmp;
654 dst[0] = ir3_CLZ_S(b, src[0], 0);
655 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
656 cmp->cat2.condition = IR3_COND_GE;
657 dst[0] = ir3_SEL_B32(b,
658 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
659 cmp, 0, dst[0], 0);
660 break;
661 }
662 case nir_op_ufind_msb:
663 dst[0] = ir3_CLZ_B(b, src[0], 0);
664 dst[0] = ir3_SEL_B32(b,
665 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
666 src[0], 0, dst[0], 0);
667 break;
668 case nir_op_find_lsb:
669 dst[0] = ir3_BFREV_B(b, src[0], 0);
670 dst[0] = ir3_CLZ_B(b, dst[0], 0);
671 break;
672 case nir_op_bitfield_reverse:
673 dst[0] = ir3_BFREV_B(b, src[0], 0);
674 break;
675
676 default:
677 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
678 nir_op_infos[alu->op].name);
679 break;
680 }
681
682 ir3_put_dst(ctx, &alu->dest.dest);
683 }
684
685 /* handles direct/indirect UBO reads: */
686 static void
687 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
688 struct ir3_instruction **dst)
689 {
690 struct ir3_block *b = ctx->block;
691 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
692 /* UBO addresses are the first driver params, but subtract 2 here to
693 * account for nir_lower_uniforms_to_ubo rebasing the UBOs such that UBO 0
694 * is the uniforms: */
695 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
696 unsigned ubo = regid(const_state->offsets.ubo, 0) - 2;
697 const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
698
699 int off = 0;
700
701 /* First src is ubo index, which could either be an immed or not: */
702 src0 = ir3_get_src(ctx, &intr->src[0])[0];
703 if (is_same_type_mov(src0) &&
704 (src0->regs[1]->flags & IR3_REG_IMMED)) {
705 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
706 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
707 } else {
708 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr(ctx, src0, ptrsz));
709 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr(ctx, src0, ptrsz));
710
711 /* NOTE: since relative addressing is used, make sure constlen is
712 * at least big enough to cover all the UBO addresses, since the
713 * assembler won't know what the max address reg is.
714 */
715 ctx->so->constlen = MAX2(ctx->so->constlen,
716 const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
717 }
718
719 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
720 addr = base_lo;
721
722 if (nir_src_is_const(intr->src[1])) {
723 off += nir_src_as_uint(intr->src[1]);
724 } else {
725 /* For load_ubo_indirect, second src is indirect offset: */
726 src1 = ir3_get_src(ctx, &intr->src[1])[0];
727
728 /* and add offset to addr: */
729 addr = ir3_ADD_S(b, addr, 0, src1, 0);
730 }
731
732 /* if offset is to large to encode in the ldg, split it out: */
733 if ((off + (intr->num_components * 4)) > 1024) {
734 /* split out the minimal amount to improve the odds that
735 * cp can fit the immediate in the add.s instruction:
736 */
737 unsigned off2 = off + (intr->num_components * 4) - 1024;
738 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
739 off -= off2;
740 }
741
742 if (ptrsz == 2) {
743 struct ir3_instruction *carry;
744
745 /* handle 32b rollover, ie:
746 * if (addr < base_lo)
747 * base_hi++
748 */
749 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
750 carry->cat2.condition = IR3_COND_LT;
751 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
752
753 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
754 }
755
756 for (int i = 0; i < intr->num_components; i++) {
757 struct ir3_instruction *load =
758 ir3_LDG(b, addr, 0, create_immed(b, 1), 0, /* num components */
759 create_immed(b, off + i * 4), 0);
760 load->cat6.type = TYPE_U32;
761 dst[i] = load;
762 }
763 }
764
765 /* src[] = { block_index } */
766 static void
767 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
768 struct ir3_instruction **dst)
769 {
770 /* SSBO size stored as a const starting at ssbo_sizes: */
771 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
772 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
773 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
774 const_state->ssbo_size.off[blk_idx];
775
776 debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
777
778 dst[0] = create_uniform(ctx->block, idx);
779 }
780
781 /* src[] = { offset }. const_index[] = { base } */
782 static void
783 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
784 struct ir3_instruction **dst)
785 {
786 struct ir3_block *b = ctx->block;
787 struct ir3_instruction *ldl, *offset;
788 unsigned base;
789
790 offset = ir3_get_src(ctx, &intr->src[0])[0];
791 base = nir_intrinsic_base(intr);
792
793 ldl = ir3_LDL(b, offset, 0,
794 create_immed(b, intr->num_components), 0,
795 create_immed(b, base), 0);
796
797 ldl->cat6.type = utype_dst(intr->dest);
798 ldl->regs[0]->wrmask = MASK(intr->num_components);
799
800 ldl->barrier_class = IR3_BARRIER_SHARED_R;
801 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
802
803 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
804 }
805
806 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
807 static void
808 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
809 {
810 struct ir3_block *b = ctx->block;
811 struct ir3_instruction *stl, *offset;
812 struct ir3_instruction * const *value;
813 unsigned base, wrmask;
814
815 value = ir3_get_src(ctx, &intr->src[0]);
816 offset = ir3_get_src(ctx, &intr->src[1])[0];
817
818 base = nir_intrinsic_base(intr);
819 wrmask = nir_intrinsic_write_mask(intr);
820
821 /* Combine groups of consecutive enabled channels in one write
822 * message. We use ffs to find the first enabled channel and then ffs on
823 * the bit-inverse, down-shifted writemask to determine the length of
824 * the block of enabled bits.
825 *
826 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
827 */
828 while (wrmask) {
829 unsigned first_component = ffs(wrmask) - 1;
830 unsigned length = ffs(~(wrmask >> first_component)) - 1;
831
832 stl = ir3_STL(b, offset, 0,
833 ir3_create_collect(ctx, &value[first_component], length), 0,
834 create_immed(b, length), 0);
835 stl->cat6.dst_offset = first_component + base;
836 stl->cat6.type = utype_src(intr->src[0]);
837 stl->barrier_class = IR3_BARRIER_SHARED_W;
838 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
839
840 array_insert(b, b->keeps, stl);
841
842 /* Clear the bits in the writemask that we just wrote, then try
843 * again to see if more channels are left.
844 */
845 wrmask &= (15 << (first_component + length));
846 }
847 }
848
849 /* src[] = { offset }. const_index[] = { base } */
850 static void
851 emit_intrinsic_load_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr,
852 struct ir3_instruction **dst)
853 {
854 struct ir3_block *b = ctx->block;
855 struct ir3_instruction *load, *offset;
856 unsigned base;
857
858 offset = ir3_get_src(ctx, &intr->src[0])[0];
859 base = nir_intrinsic_base(intr);
860
861 load = ir3_LDLW(b, offset, 0,
862 create_immed(b, intr->num_components), 0,
863 create_immed(b, base), 0);
864
865 load->cat6.type = utype_dst(intr->dest);
866 load->regs[0]->wrmask = MASK(intr->num_components);
867
868 load->barrier_class = IR3_BARRIER_SHARED_R;
869 load->barrier_conflict = IR3_BARRIER_SHARED_W;
870
871 ir3_split_dest(b, dst, load, 0, intr->num_components);
872 }
873
874 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
875 static void
876 emit_intrinsic_store_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr)
877 {
878 struct ir3_block *b = ctx->block;
879 struct ir3_instruction *store, *offset;
880 struct ir3_instruction * const *value;
881 unsigned base, wrmask;
882
883 value = ir3_get_src(ctx, &intr->src[0]);
884 offset = ir3_get_src(ctx, &intr->src[1])[0];
885
886 base = nir_intrinsic_base(intr);
887 wrmask = nir_intrinsic_write_mask(intr);
888
889 /* Combine groups of consecutive enabled channels in one write
890 * message. We use ffs to find the first enabled channel and then ffs on
891 * the bit-inverse, down-shifted writemask to determine the length of
892 * the block of enabled bits.
893 *
894 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
895 */
896 while (wrmask) {
897 unsigned first_component = ffs(wrmask) - 1;
898 unsigned length = ffs(~(wrmask >> first_component)) - 1;
899
900 store = ir3_STLW(b, offset, 0,
901 ir3_create_collect(ctx, &value[first_component], length), 0,
902 create_immed(b, length), 0);
903
904 store->cat6.dst_offset = first_component + base;
905 store->cat6.type = utype_src(intr->src[0]);
906 store->barrier_class = IR3_BARRIER_SHARED_W;
907 store->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
908
909 array_insert(b, b->keeps, store);
910
911 /* Clear the bits in the writemask that we just wrote, then try
912 * again to see if more channels are left.
913 */
914 wrmask &= (15 << (first_component + length));
915 }
916 }
917
918 /*
919 * CS shared variable atomic intrinsics
920 *
921 * All of the shared variable atomic memory operations read a value from
922 * memory, compute a new value using one of the operations below, write the
923 * new value to memory, and return the original value read.
924 *
925 * All operations take 2 sources except CompSwap that takes 3. These
926 * sources represent:
927 *
928 * 0: The offset into the shared variable storage region that the atomic
929 * operation will operate on.
930 * 1: The data parameter to the atomic function (i.e. the value to add
931 * in shared_atomic_add, etc).
932 * 2: For CompSwap only: the second data parameter.
933 */
934 static struct ir3_instruction *
935 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
936 {
937 struct ir3_block *b = ctx->block;
938 struct ir3_instruction *atomic, *src0, *src1;
939 type_t type = TYPE_U32;
940
941 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
942 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
943
944 switch (intr->intrinsic) {
945 case nir_intrinsic_shared_atomic_add:
946 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
947 break;
948 case nir_intrinsic_shared_atomic_imin:
949 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
950 type = TYPE_S32;
951 break;
952 case nir_intrinsic_shared_atomic_umin:
953 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
954 break;
955 case nir_intrinsic_shared_atomic_imax:
956 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
957 type = TYPE_S32;
958 break;
959 case nir_intrinsic_shared_atomic_umax:
960 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
961 break;
962 case nir_intrinsic_shared_atomic_and:
963 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
964 break;
965 case nir_intrinsic_shared_atomic_or:
966 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
967 break;
968 case nir_intrinsic_shared_atomic_xor:
969 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
970 break;
971 case nir_intrinsic_shared_atomic_exchange:
972 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
973 break;
974 case nir_intrinsic_shared_atomic_comp_swap:
975 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
976 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
977 ir3_get_src(ctx, &intr->src[2])[0],
978 src1,
979 }, 2);
980 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
981 break;
982 default:
983 unreachable("boo");
984 }
985
986 atomic->cat6.iim_val = 1;
987 atomic->cat6.d = 1;
988 atomic->cat6.type = type;
989 atomic->barrier_class = IR3_BARRIER_SHARED_W;
990 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
991
992 /* even if nothing consume the result, we can't DCE the instruction: */
993 array_insert(b, b->keeps, atomic);
994
995 return atomic;
996 }
997
998 /* TODO handle actual indirect/dynamic case.. which is going to be weird
999 * to handle with the image_mapping table..
1000 */
1001 static struct ir3_instruction *
1002 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1003 {
1004 unsigned slot = ir3_get_image_slot(nir_src_as_deref(intr->src[0]));
1005 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
1006 struct ir3_instruction *texture, *sampler;
1007
1008 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1009 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1010
1011 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1012 sampler,
1013 texture,
1014 }, 2);
1015 }
1016
1017 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1018 static void
1019 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1020 struct ir3_instruction **dst)
1021 {
1022 struct ir3_block *b = ctx->block;
1023 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1024 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
1025 struct ir3_instruction *sam;
1026 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
1027 struct ir3_instruction *coords[4];
1028 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
1029 type_t type = ir3_get_image_type(var);
1030
1031 /* hmm, this seems a bit odd, but it is what blob does and (at least
1032 * a5xx) just faults on bogus addresses otherwise:
1033 */
1034 if (flags & IR3_INSTR_3D) {
1035 flags &= ~IR3_INSTR_3D;
1036 flags |= IR3_INSTR_A;
1037 }
1038
1039 for (unsigned i = 0; i < ncoords; i++)
1040 coords[i] = src0[i];
1041
1042 if (ncoords == 1)
1043 coords[ncoords++] = create_immed(b, 0);
1044
1045 sam = ir3_SAM(b, OPC_ISAM, type, 0b1111, flags,
1046 samp_tex, ir3_create_collect(ctx, coords, ncoords), NULL);
1047
1048 sam->barrier_class = IR3_BARRIER_IMAGE_R;
1049 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
1050
1051 ir3_split_dest(b, dst, sam, 0, 4);
1052 }
1053
1054 static void
1055 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1056 struct ir3_instruction **dst)
1057 {
1058 struct ir3_block *b = ctx->block;
1059 const nir_variable *var = nir_intrinsic_get_var(intr, 0);
1060 struct ir3_instruction *samp_tex = get_image_samp_tex_src(ctx, intr);
1061 struct ir3_instruction *sam, *lod;
1062 unsigned flags, ncoords = ir3_get_image_coords(var, &flags);
1063
1064 lod = create_immed(b, 0);
1065 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
1066 samp_tex, lod, NULL);
1067
1068 /* Array size actually ends up in .w rather than .z. This doesn't
1069 * matter for miplevel 0, but for higher mips the value in z is
1070 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1071 * returned, which means that we have to add 1 to it for arrays for
1072 * a3xx.
1073 *
1074 * Note use a temporary dst and then copy, since the size of the dst
1075 * array that is passed in is based on nir's understanding of the
1076 * result size, not the hardware's
1077 */
1078 struct ir3_instruction *tmp[4];
1079
1080 ir3_split_dest(b, tmp, sam, 0, 4);
1081
1082 /* get_size instruction returns size in bytes instead of texels
1083 * for imageBuffer, so we need to divide it by the pixel size
1084 * of the image format.
1085 *
1086 * TODO: This is at least true on a5xx. Check other gens.
1087 */
1088 enum glsl_sampler_dim dim =
1089 glsl_get_sampler_dim(glsl_without_array(var->type));
1090 if (dim == GLSL_SAMPLER_DIM_BUF) {
1091 /* Since all the possible values the divisor can take are
1092 * power-of-two (4, 8, or 16), the division is implemented
1093 * as a shift-right.
1094 * During shader setup, the log2 of the image format's
1095 * bytes-per-pixel should have been emitted in 2nd slot of
1096 * image_dims. See ir3_shader::emit_image_dims().
1097 */
1098 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
1099 unsigned cb = regid(const_state->offsets.image_dims, 0) +
1100 const_state->image_dims.off[var->data.driver_location];
1101 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1102
1103 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1104 }
1105
1106 for (unsigned i = 0; i < ncoords; i++)
1107 dst[i] = tmp[i];
1108
1109 if (flags & IR3_INSTR_A) {
1110 if (ctx->compiler->levels_add_one) {
1111 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1112 } else {
1113 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1114 }
1115 }
1116 }
1117
1118 static void
1119 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1120 {
1121 struct ir3_block *b = ctx->block;
1122 struct ir3_instruction *barrier;
1123
1124 switch (intr->intrinsic) {
1125 case nir_intrinsic_barrier:
1126 barrier = ir3_BAR(b);
1127 barrier->cat7.g = true;
1128 barrier->cat7.l = true;
1129 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1130 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1131 break;
1132 case nir_intrinsic_memory_barrier:
1133 barrier = ir3_FENCE(b);
1134 barrier->cat7.g = true;
1135 barrier->cat7.r = true;
1136 barrier->cat7.w = true;
1137 barrier->cat7.l = true;
1138 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1139 IR3_BARRIER_BUFFER_W;
1140 barrier->barrier_conflict =
1141 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1142 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1143 break;
1144 case nir_intrinsic_memory_barrier_atomic_counter:
1145 case nir_intrinsic_memory_barrier_buffer:
1146 barrier = ir3_FENCE(b);
1147 barrier->cat7.g = true;
1148 barrier->cat7.r = true;
1149 barrier->cat7.w = true;
1150 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1151 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1152 IR3_BARRIER_BUFFER_W;
1153 break;
1154 case nir_intrinsic_memory_barrier_image:
1155 // TODO double check if this should have .g set
1156 barrier = ir3_FENCE(b);
1157 barrier->cat7.g = true;
1158 barrier->cat7.r = true;
1159 barrier->cat7.w = true;
1160 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1161 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1162 IR3_BARRIER_IMAGE_W;
1163 break;
1164 case nir_intrinsic_memory_barrier_shared:
1165 barrier = ir3_FENCE(b);
1166 barrier->cat7.g = true;
1167 barrier->cat7.l = true;
1168 barrier->cat7.r = true;
1169 barrier->cat7.w = true;
1170 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1171 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1172 IR3_BARRIER_SHARED_W;
1173 break;
1174 case nir_intrinsic_group_memory_barrier:
1175 barrier = ir3_FENCE(b);
1176 barrier->cat7.g = true;
1177 barrier->cat7.l = true;
1178 barrier->cat7.r = true;
1179 barrier->cat7.w = true;
1180 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1181 IR3_BARRIER_IMAGE_W |
1182 IR3_BARRIER_BUFFER_W;
1183 barrier->barrier_conflict =
1184 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1185 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1186 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1187 break;
1188 default:
1189 unreachable("boo");
1190 }
1191
1192 /* make sure barrier doesn't get DCE'd */
1193 array_insert(b, b->keeps, barrier);
1194 }
1195
1196 static void add_sysval_input_compmask(struct ir3_context *ctx,
1197 gl_system_value slot, unsigned compmask,
1198 struct ir3_instruction *instr)
1199 {
1200 struct ir3_shader_variant *so = ctx->so;
1201 unsigned r = regid(so->inputs_count, 0);
1202 unsigned n = so->inputs_count++;
1203
1204 assert(instr->opc == OPC_META_INPUT);
1205 instr->input.sysval = slot;
1206
1207 so->inputs[n].sysval = true;
1208 so->inputs[n].slot = slot;
1209 so->inputs[n].compmask = compmask;
1210 so->inputs[n].regid = r;
1211 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1212 so->total_in++;
1213
1214 ctx->ir->ninputs = MAX2(ctx->ir->ninputs, r + 1);
1215 ctx->ir->inputs[r] = instr;
1216 }
1217
1218 static void add_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1219 struct ir3_instruction *instr)
1220 {
1221 add_sysval_input_compmask(ctx, slot, 0x1, instr);
1222 }
1223
1224 static struct ir3_instruction *
1225 get_barycentric_centroid(struct ir3_context *ctx)
1226 {
1227 if (!ctx->ij_centroid) {
1228 struct ir3_instruction *xy[2];
1229 struct ir3_instruction *ij;
1230
1231 ij = create_input_compmask(ctx, 0, 0x3);
1232 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1233
1234 ctx->ij_centroid = ir3_create_collect(ctx, xy, 2);
1235
1236 add_sysval_input_compmask(ctx,
1237 SYSTEM_VALUE_BARYCENTRIC_CENTROID,
1238 0x3, ij);
1239 }
1240
1241 return ctx->ij_centroid;
1242 }
1243
1244 static struct ir3_instruction *
1245 get_barycentric_sample(struct ir3_context *ctx)
1246 {
1247 if (!ctx->ij_sample) {
1248 struct ir3_instruction *xy[2];
1249 struct ir3_instruction *ij;
1250
1251 ij = create_input_compmask(ctx, 0, 0x3);
1252 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1253
1254 ctx->ij_sample = ir3_create_collect(ctx, xy, 2);
1255
1256 add_sysval_input_compmask(ctx,
1257 SYSTEM_VALUE_BARYCENTRIC_SAMPLE,
1258 0x3, ij);
1259 }
1260
1261 return ctx->ij_sample;
1262 }
1263
1264 static struct ir3_instruction *
1265 get_barycentric_pixel(struct ir3_context *ctx)
1266 {
1267 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1268 * this to create ij_pixel only on demand:
1269 */
1270 return ctx->ij_pixel;
1271 }
1272
1273 static struct ir3_instruction *
1274 get_frag_coord(struct ir3_context *ctx)
1275 {
1276 if (!ctx->frag_coord) {
1277 struct ir3_block *b = ctx->block;
1278 struct ir3_instruction *xyzw[4];
1279 struct ir3_instruction *hw_frag_coord;
1280
1281 hw_frag_coord = create_input_compmask(ctx, 0, 0xf);
1282 ir3_split_dest(ctx->block, xyzw, hw_frag_coord, 0, 4);
1283
1284 /* for frag_coord.xy, we get unsigned values.. we need
1285 * to subtract (integer) 8 and divide by 16 (right-
1286 * shift by 4) then convert to float:
1287 *
1288 * sub.s tmp, src, 8
1289 * shr.b tmp, tmp, 4
1290 * mov.u32f32 dst, tmp
1291 *
1292 */
1293 for (int i = 0; i < 2; i++) {
1294 xyzw[i] = ir3_SUB_S(b, xyzw[i], 0,
1295 create_immed(b, 8), 0);
1296 xyzw[i] = ir3_SHR_B(b, xyzw[i], 0,
1297 create_immed(b, 4), 0);
1298 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1299 }
1300
1301 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1302
1303 add_sysval_input_compmask(ctx,
1304 SYSTEM_VALUE_FRAG_COORD,
1305 0xf, hw_frag_coord);
1306
1307 ctx->so->frag_coord = true;
1308 }
1309
1310 return ctx->frag_coord;
1311 }
1312
1313 static void
1314 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1315 {
1316 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1317 struct ir3_instruction **dst;
1318 struct ir3_instruction * const *src;
1319 struct ir3_block *b = ctx->block;
1320 int idx, comp;
1321
1322 if (info->has_dest) {
1323 unsigned n = nir_intrinsic_dest_components(intr);
1324 dst = ir3_get_dst(ctx, &intr->dest, n);
1325 } else {
1326 dst = NULL;
1327 }
1328
1329 const unsigned primitive_param = ctx->so->shader->const_state.offsets.primitive_param * 4;
1330 const unsigned primitive_map = ctx->so->shader->const_state.offsets.primitive_map * 4;
1331
1332 switch (intr->intrinsic) {
1333 case nir_intrinsic_load_uniform:
1334 idx = nir_intrinsic_base(intr);
1335 if (nir_src_is_const(intr->src[0])) {
1336 idx += nir_src_as_uint(intr->src[0]);
1337 for (int i = 0; i < intr->num_components; i++) {
1338 dst[i] = create_uniform_typed(b, idx + i,
1339 nir_dest_bit_size(intr->dest) < 32 ? TYPE_F16 : TYPE_F32);
1340 }
1341 } else {
1342 src = ir3_get_src(ctx, &intr->src[0]);
1343 for (int i = 0; i < intr->num_components; i++) {
1344 dst[i] = create_uniform_indirect(b, idx + i,
1345 ir3_get_addr(ctx, src[0], 1));
1346 }
1347 /* NOTE: if relative addressing is used, we set
1348 * constlen in the compiler (to worst-case value)
1349 * since we don't know in the assembler what the max
1350 * addr reg value can be:
1351 */
1352 ctx->so->constlen = MAX2(ctx->so->constlen,
1353 ctx->so->shader->ubo_state.size / 16);
1354 }
1355 break;
1356
1357 case nir_intrinsic_load_vs_primitive_stride_ir3:
1358 dst[0] = create_uniform(b, primitive_param + 0);
1359 break;
1360 case nir_intrinsic_load_vs_vertex_stride_ir3:
1361 dst[0] = create_uniform(b, primitive_param + 1);
1362 break;
1363 case nir_intrinsic_load_hs_patch_stride_ir3:
1364 dst[0] = create_uniform(b, primitive_param + 2);
1365 break;
1366 case nir_intrinsic_load_patch_vertices_in:
1367 dst[0] = create_uniform(b, primitive_param + 3);
1368 break;
1369 case nir_intrinsic_load_tess_param_base_ir3:
1370 dst[0] = create_uniform(b, primitive_param + 4);
1371 dst[1] = create_uniform(b, primitive_param + 5);
1372 break;
1373 case nir_intrinsic_load_tess_factor_base_ir3:
1374 dst[0] = create_uniform(b, primitive_param + 6);
1375 dst[1] = create_uniform(b, primitive_param + 7);
1376 break;
1377
1378 case nir_intrinsic_load_primitive_location_ir3:
1379 idx = nir_intrinsic_driver_location(intr);
1380 dst[0] = create_uniform(b, primitive_map + idx);
1381 break;
1382
1383 case nir_intrinsic_load_gs_header_ir3:
1384 dst[0] = ctx->gs_header;
1385 break;
1386 case nir_intrinsic_load_tcs_header_ir3:
1387 dst[0] = ctx->tcs_header;
1388 break;
1389
1390 case nir_intrinsic_load_primitive_id:
1391 dst[0] = ctx->primitive_id;
1392 break;
1393
1394 case nir_intrinsic_load_tess_coord:
1395 if (!ctx->tess_coord) {
1396 ctx->tess_coord = create_input_compmask(ctx, 0, 0x3);
1397 add_sysval_input_compmask(ctx, SYSTEM_VALUE_TESS_COORD,
1398 0x3, ctx->tess_coord);
1399 }
1400 ir3_split_dest(b, dst, ctx->tess_coord, 0, 2);
1401
1402 /* Unused, but ir3_put_dst() below wants to free something */
1403 dst[2] = create_immed(b, 0);
1404 break;
1405
1406 case nir_intrinsic_end_patch_ir3:
1407 assert(ctx->so->type == MESA_SHADER_TESS_CTRL);
1408 struct ir3_instruction *end = ir3_ENDPATCH(b);
1409 array_insert(b, b->keeps, end);
1410
1411 end->barrier_class = IR3_BARRIER_EVERYTHING;
1412 end->barrier_conflict = IR3_BARRIER_EVERYTHING;
1413 break;
1414
1415 case nir_intrinsic_store_global_ir3: {
1416 struct ir3_instruction *value, *addr, *offset;
1417
1418 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1419 ir3_get_src(ctx, &intr->src[1])[0],
1420 ir3_get_src(ctx, &intr->src[1])[1]
1421 }, 2);
1422
1423 offset = ir3_get_src(ctx, &intr->src[2])[0];
1424
1425 value = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]),
1426 intr->num_components);
1427
1428 struct ir3_instruction *stg =
1429 ir3_STG_G(ctx->block, addr, 0, value, 0,
1430 create_immed(ctx->block, intr->num_components), 0, offset, 0);
1431 stg->cat6.type = TYPE_U32;
1432 stg->cat6.iim_val = 1;
1433
1434 array_insert(b, b->keeps, stg);
1435
1436 stg->barrier_class = IR3_BARRIER_BUFFER_W;
1437 stg->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1438 break;
1439 }
1440
1441 case nir_intrinsic_load_global_ir3: {
1442 struct ir3_instruction *addr, *offset;
1443
1444 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1445 ir3_get_src(ctx, &intr->src[0])[0],
1446 ir3_get_src(ctx, &intr->src[0])[1]
1447 }, 2);
1448
1449 offset = ir3_get_src(ctx, &intr->src[1])[0];
1450
1451 struct ir3_instruction *load =
1452 ir3_LDG(b, addr, 0, create_immed(ctx->block, intr->num_components),
1453 0, offset, 0);
1454 load->cat6.type = TYPE_U32;
1455 load->regs[0]->wrmask = MASK(intr->num_components);
1456
1457 load->barrier_class = IR3_BARRIER_BUFFER_R;
1458 load->barrier_conflict = IR3_BARRIER_BUFFER_W;
1459
1460 ir3_split_dest(b, dst, load, 0, intr->num_components);
1461 break;
1462 }
1463
1464 case nir_intrinsic_load_ubo:
1465 emit_intrinsic_load_ubo(ctx, intr, dst);
1466 break;
1467 case nir_intrinsic_load_frag_coord:
1468 ir3_split_dest(b, dst, get_frag_coord(ctx), 0, 4);
1469 break;
1470 case nir_intrinsic_load_sample_pos_from_id: {
1471 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1472 * but that doesn't seem necessary.
1473 */
1474 struct ir3_instruction *offset =
1475 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1476 offset->regs[0]->wrmask = 0x3;
1477 offset->cat5.type = TYPE_F32;
1478
1479 ir3_split_dest(b, dst, offset, 0, 2);
1480
1481 break;
1482 }
1483 case nir_intrinsic_load_size_ir3:
1484 if (!ctx->ij_size) {
1485 ctx->ij_size = create_input(ctx, 0);
1486
1487 add_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_SIZE,
1488 ctx->ij_size);
1489 }
1490 dst[0] = ctx->ij_size;
1491 break;
1492 case nir_intrinsic_load_barycentric_centroid:
1493 ir3_split_dest(b, dst, get_barycentric_centroid(ctx), 0, 2);
1494 break;
1495 case nir_intrinsic_load_barycentric_sample:
1496 if (ctx->so->key.msaa) {
1497 ir3_split_dest(b, dst, get_barycentric_sample(ctx), 0, 2);
1498 } else {
1499 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1500 }
1501 break;
1502 case nir_intrinsic_load_barycentric_pixel:
1503 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1504 break;
1505 case nir_intrinsic_load_interpolated_input:
1506 idx = nir_intrinsic_base(intr);
1507 comp = nir_intrinsic_component(intr);
1508 src = ir3_get_src(ctx, &intr->src[0]);
1509 if (nir_src_is_const(intr->src[1])) {
1510 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1511 idx += nir_src_as_uint(intr->src[1]);
1512 for (int i = 0; i < intr->num_components; i++) {
1513 unsigned inloc = idx * 4 + i + comp;
1514 if (ctx->so->inputs[idx].bary &&
1515 !ctx->so->inputs[idx].use_ldlv) {
1516 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1517 } else {
1518 /* for non-varyings use the pre-setup input, since
1519 * that is easier than mapping things back to a
1520 * nir_variable to figure out what it is.
1521 */
1522 dst[i] = ctx->ir->inputs[inloc];
1523 }
1524 }
1525 } else {
1526 ir3_context_error(ctx, "unhandled");
1527 }
1528 break;
1529 case nir_intrinsic_load_input:
1530 idx = nir_intrinsic_base(intr);
1531 comp = nir_intrinsic_component(intr);
1532 if (nir_src_is_const(intr->src[0])) {
1533 idx += nir_src_as_uint(intr->src[0]);
1534 for (int i = 0; i < intr->num_components; i++) {
1535 unsigned n = idx * 4 + i + comp;
1536 dst[i] = ctx->ir->inputs[n];
1537 compile_assert(ctx, ctx->ir->inputs[n]);
1538 }
1539 } else {
1540 src = ir3_get_src(ctx, &intr->src[0]);
1541 struct ir3_instruction *collect =
1542 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ir->ninputs);
1543 struct ir3_instruction *addr = ir3_get_addr(ctx, src[0], 4);
1544 for (int i = 0; i < intr->num_components; i++) {
1545 unsigned n = idx * 4 + i + comp;
1546 dst[i] = create_indirect_load(ctx, ctx->ir->ninputs,
1547 n, addr, collect);
1548 }
1549 }
1550 break;
1551 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1552 * pass and replaced by an ir3-specifc version that adds the
1553 * dword-offset in the last source.
1554 */
1555 case nir_intrinsic_load_ssbo_ir3:
1556 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1557 break;
1558 case nir_intrinsic_store_ssbo_ir3:
1559 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1560 !ctx->s->info.fs.early_fragment_tests)
1561 ctx->so->no_earlyz = true;
1562 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1563 break;
1564 case nir_intrinsic_get_buffer_size:
1565 emit_intrinsic_ssbo_size(ctx, intr, dst);
1566 break;
1567 case nir_intrinsic_ssbo_atomic_add_ir3:
1568 case nir_intrinsic_ssbo_atomic_imin_ir3:
1569 case nir_intrinsic_ssbo_atomic_umin_ir3:
1570 case nir_intrinsic_ssbo_atomic_imax_ir3:
1571 case nir_intrinsic_ssbo_atomic_umax_ir3:
1572 case nir_intrinsic_ssbo_atomic_and_ir3:
1573 case nir_intrinsic_ssbo_atomic_or_ir3:
1574 case nir_intrinsic_ssbo_atomic_xor_ir3:
1575 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1576 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1577 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1578 !ctx->s->info.fs.early_fragment_tests)
1579 ctx->so->no_earlyz = true;
1580 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1581 break;
1582 case nir_intrinsic_load_shared:
1583 emit_intrinsic_load_shared(ctx, intr, dst);
1584 break;
1585 case nir_intrinsic_store_shared:
1586 emit_intrinsic_store_shared(ctx, intr);
1587 break;
1588 case nir_intrinsic_shared_atomic_add:
1589 case nir_intrinsic_shared_atomic_imin:
1590 case nir_intrinsic_shared_atomic_umin:
1591 case nir_intrinsic_shared_atomic_imax:
1592 case nir_intrinsic_shared_atomic_umax:
1593 case nir_intrinsic_shared_atomic_and:
1594 case nir_intrinsic_shared_atomic_or:
1595 case nir_intrinsic_shared_atomic_xor:
1596 case nir_intrinsic_shared_atomic_exchange:
1597 case nir_intrinsic_shared_atomic_comp_swap:
1598 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1599 break;
1600 case nir_intrinsic_image_deref_load:
1601 emit_intrinsic_load_image(ctx, intr, dst);
1602 break;
1603 case nir_intrinsic_image_deref_store:
1604 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1605 !ctx->s->info.fs.early_fragment_tests)
1606 ctx->so->no_earlyz = true;
1607 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1608 break;
1609 case nir_intrinsic_image_deref_size:
1610 emit_intrinsic_image_size(ctx, intr, dst);
1611 break;
1612 case nir_intrinsic_image_deref_atomic_add:
1613 case nir_intrinsic_image_deref_atomic_imin:
1614 case nir_intrinsic_image_deref_atomic_umin:
1615 case nir_intrinsic_image_deref_atomic_imax:
1616 case nir_intrinsic_image_deref_atomic_umax:
1617 case nir_intrinsic_image_deref_atomic_and:
1618 case nir_intrinsic_image_deref_atomic_or:
1619 case nir_intrinsic_image_deref_atomic_xor:
1620 case nir_intrinsic_image_deref_atomic_exchange:
1621 case nir_intrinsic_image_deref_atomic_comp_swap:
1622 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1623 !ctx->s->info.fs.early_fragment_tests)
1624 ctx->so->no_earlyz = true;
1625 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1626 break;
1627 case nir_intrinsic_barrier:
1628 case nir_intrinsic_memory_barrier:
1629 case nir_intrinsic_group_memory_barrier:
1630 case nir_intrinsic_memory_barrier_atomic_counter:
1631 case nir_intrinsic_memory_barrier_buffer:
1632 case nir_intrinsic_memory_barrier_image:
1633 case nir_intrinsic_memory_barrier_shared:
1634 emit_intrinsic_barrier(ctx, intr);
1635 /* note that blk ptr no longer valid, make that obvious: */
1636 b = NULL;
1637 break;
1638 case nir_intrinsic_store_output:
1639 idx = nir_intrinsic_base(intr);
1640 comp = nir_intrinsic_component(intr);
1641 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1642 idx += nir_src_as_uint(intr->src[1]);
1643
1644 src = ir3_get_src(ctx, &intr->src[0]);
1645 for (int i = 0; i < intr->num_components; i++) {
1646 unsigned n = idx * 4 + i + comp;
1647 ctx->ir->outputs[n] = src[i];
1648 }
1649 break;
1650 case nir_intrinsic_load_base_vertex:
1651 case nir_intrinsic_load_first_vertex:
1652 if (!ctx->basevertex) {
1653 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1654 add_sysval_input(ctx, SYSTEM_VALUE_FIRST_VERTEX, ctx->basevertex);
1655 }
1656 dst[0] = ctx->basevertex;
1657 break;
1658 case nir_intrinsic_load_vertex_id_zero_base:
1659 case nir_intrinsic_load_vertex_id:
1660 if (!ctx->vertex_id) {
1661 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1662 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1663 ctx->vertex_id = create_input(ctx, 0);
1664 add_sysval_input(ctx, sv, ctx->vertex_id);
1665 }
1666 dst[0] = ctx->vertex_id;
1667 break;
1668 case nir_intrinsic_load_instance_id:
1669 if (!ctx->instance_id) {
1670 ctx->instance_id = create_input(ctx, 0);
1671 add_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID,
1672 ctx->instance_id);
1673 }
1674 dst[0] = ctx->instance_id;
1675 break;
1676 case nir_intrinsic_load_sample_id:
1677 ctx->so->per_samp = true;
1678 /* fall-thru */
1679 case nir_intrinsic_load_sample_id_no_per_sample:
1680 if (!ctx->samp_id) {
1681 ctx->samp_id = create_input(ctx, 0);
1682 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1683 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID,
1684 ctx->samp_id);
1685 }
1686 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1687 break;
1688 case nir_intrinsic_load_sample_mask_in:
1689 if (!ctx->samp_mask_in) {
1690 ctx->samp_mask_in = create_input(ctx, 0);
1691 add_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN,
1692 ctx->samp_mask_in);
1693 }
1694 dst[0] = ctx->samp_mask_in;
1695 break;
1696 case nir_intrinsic_load_user_clip_plane:
1697 idx = nir_intrinsic_ucp_id(intr);
1698 for (int i = 0; i < intr->num_components; i++) {
1699 unsigned n = idx * 4 + i;
1700 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1701 }
1702 break;
1703 case nir_intrinsic_load_front_face:
1704 if (!ctx->frag_face) {
1705 ctx->so->frag_face = true;
1706 ctx->frag_face = create_input(ctx, 0);
1707 add_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, ctx->frag_face);
1708 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1709 }
1710 /* for fragface, we get -1 for back and 0 for front. However this is
1711 * the inverse of what nir expects (where ~0 is true).
1712 */
1713 dst[0] = ir3_COV(b, ctx->frag_face, TYPE_S16, TYPE_S32);
1714 dst[0] = ir3_NOT_B(b, dst[0], 0);
1715 break;
1716 case nir_intrinsic_load_local_invocation_id:
1717 if (!ctx->local_invocation_id) {
1718 ctx->local_invocation_id = create_input_compmask(ctx, 0, 0x7);
1719 add_sysval_input_compmask(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID,
1720 0x7, ctx->local_invocation_id);
1721 }
1722 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1723 break;
1724 case nir_intrinsic_load_work_group_id:
1725 if (!ctx->work_group_id) {
1726 ctx->work_group_id = create_input_compmask(ctx, 0, 0x7);
1727 add_sysval_input_compmask(ctx, SYSTEM_VALUE_WORK_GROUP_ID,
1728 0x7, ctx->work_group_id);
1729 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1730 }
1731 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1732 break;
1733 case nir_intrinsic_load_num_work_groups:
1734 for (int i = 0; i < intr->num_components; i++) {
1735 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1736 }
1737 break;
1738 case nir_intrinsic_load_local_group_size:
1739 for (int i = 0; i < intr->num_components; i++) {
1740 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1741 }
1742 break;
1743 case nir_intrinsic_discard_if:
1744 case nir_intrinsic_discard: {
1745 struct ir3_instruction *cond, *kill;
1746
1747 if (intr->intrinsic == nir_intrinsic_discard_if) {
1748 /* conditional discard: */
1749 src = ir3_get_src(ctx, &intr->src[0]);
1750 cond = ir3_b2n(b, src[0]);
1751 } else {
1752 /* unconditional discard: */
1753 cond = create_immed(b, 1);
1754 }
1755
1756 /* NOTE: only cmps.*.* can write p0.x: */
1757 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1758 cond->cat2.condition = IR3_COND_NE;
1759
1760 /* condition always goes in predicate register: */
1761 cond->regs[0]->num = regid(REG_P0, 0);
1762 cond->regs[0]->flags &= ~IR3_REG_SSA;
1763
1764 kill = ir3_KILL(b, cond, 0);
1765 array_insert(ctx->ir, ctx->ir->predicates, kill);
1766
1767 array_insert(b, b->keeps, kill);
1768 ctx->so->no_earlyz = true;
1769
1770 break;
1771 }
1772
1773 case nir_intrinsic_cond_end_ir3: {
1774 struct ir3_instruction *cond, *kill;
1775
1776 src = ir3_get_src(ctx, &intr->src[0]);
1777 cond = ir3_b2n(b, src[0]);
1778
1779 /* NOTE: only cmps.*.* can write p0.x: */
1780 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1781 cond->cat2.condition = IR3_COND_NE;
1782
1783 /* condition always goes in predicate register: */
1784 cond->regs[0]->num = regid(REG_P0, 0);
1785
1786 kill = ir3_CONDEND(b, cond, 0);
1787
1788 kill->barrier_class = IR3_BARRIER_EVERYTHING;
1789 kill->barrier_conflict = IR3_BARRIER_EVERYTHING;
1790
1791 array_insert(ctx->ir, ctx->ir->predicates, kill);
1792 array_insert(b, b->keeps, kill);
1793 break;
1794 }
1795
1796 case nir_intrinsic_load_shared_ir3:
1797 emit_intrinsic_load_shared_ir3(ctx, intr, dst);
1798 break;
1799 case nir_intrinsic_store_shared_ir3:
1800 emit_intrinsic_store_shared_ir3(ctx, intr);
1801 break;
1802 default:
1803 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1804 nir_intrinsic_infos[intr->intrinsic].name);
1805 break;
1806 }
1807
1808 if (info->has_dest)
1809 ir3_put_dst(ctx, &intr->dest);
1810 }
1811
1812 static void
1813 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1814 {
1815 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1816 instr->def.num_components);
1817
1818 if (instr->def.bit_size < 32) {
1819 for (int i = 0; i < instr->def.num_components; i++)
1820 dst[i] = create_immed_typed(ctx->block,
1821 instr->value[i].u16,
1822 TYPE_U16);
1823 } else {
1824 for (int i = 0; i < instr->def.num_components; i++)
1825 dst[i] = create_immed_typed(ctx->block,
1826 instr->value[i].u32,
1827 TYPE_U32);
1828 }
1829
1830 }
1831
1832 static void
1833 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1834 {
1835 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1836 undef->def.num_components);
1837 type_t type = (undef->def.bit_size < 32) ? TYPE_U16 : TYPE_U32;
1838
1839 /* backend doesn't want undefined instructions, so just plug
1840 * in 0.0..
1841 */
1842 for (int i = 0; i < undef->def.num_components; i++)
1843 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1844 }
1845
1846 /*
1847 * texture fetch/sample instructions:
1848 */
1849
1850 static void
1851 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
1852 {
1853 unsigned coords, flags = 0;
1854
1855 /* note: would use tex->coord_components.. except txs.. also,
1856 * since array index goes after shadow ref, we don't want to
1857 * count it:
1858 */
1859 switch (tex->sampler_dim) {
1860 case GLSL_SAMPLER_DIM_1D:
1861 case GLSL_SAMPLER_DIM_BUF:
1862 coords = 1;
1863 break;
1864 case GLSL_SAMPLER_DIM_2D:
1865 case GLSL_SAMPLER_DIM_RECT:
1866 case GLSL_SAMPLER_DIM_EXTERNAL:
1867 case GLSL_SAMPLER_DIM_MS:
1868 coords = 2;
1869 break;
1870 case GLSL_SAMPLER_DIM_3D:
1871 case GLSL_SAMPLER_DIM_CUBE:
1872 coords = 3;
1873 flags |= IR3_INSTR_3D;
1874 break;
1875 default:
1876 unreachable("bad sampler_dim");
1877 }
1878
1879 if (tex->is_shadow && tex->op != nir_texop_lod)
1880 flags |= IR3_INSTR_S;
1881
1882 if (tex->is_array && tex->op != nir_texop_lod)
1883 flags |= IR3_INSTR_A;
1884
1885 *flagsp = flags;
1886 *coordsp = coords;
1887 }
1888
1889 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
1890 * or immediate (in which case it will get lowered later to a non .s2en
1891 * version of the tex instruction which encode tex/samp as immediates:
1892 */
1893 static struct ir3_instruction *
1894 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
1895 {
1896 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
1897 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
1898 struct ir3_instruction *texture, *sampler;
1899
1900 if (texture_idx >= 0) {
1901 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
1902 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
1903 } else {
1904 /* TODO what to do for dynamic case? I guess we only need the
1905 * max index for astc srgb workaround so maybe not a problem
1906 * to worry about if we don't enable indirect samplers for
1907 * a4xx?
1908 */
1909 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
1910 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
1911 }
1912
1913 if (sampler_idx >= 0) {
1914 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
1915 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
1916 } else {
1917 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
1918 }
1919
1920 return ir3_create_collect(ctx, (struct ir3_instruction*[]){
1921 sampler,
1922 texture,
1923 }, 2);
1924 }
1925
1926 static void
1927 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
1928 {
1929 struct ir3_block *b = ctx->block;
1930 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
1931 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
1932 struct ir3_instruction *lod, *compare, *proj, *sample_index;
1933 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
1934 unsigned i, coords, flags, ncomp;
1935 unsigned nsrc0 = 0, nsrc1 = 0;
1936 type_t type;
1937 opc_t opc = 0;
1938
1939 ncomp = nir_dest_num_components(tex->dest);
1940
1941 coord = off = ddx = ddy = NULL;
1942 lod = proj = compare = sample_index = NULL;
1943
1944 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
1945
1946 for (unsigned i = 0; i < tex->num_srcs; i++) {
1947 switch (tex->src[i].src_type) {
1948 case nir_tex_src_coord:
1949 coord = ir3_get_src(ctx, &tex->src[i].src);
1950 break;
1951 case nir_tex_src_bias:
1952 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1953 has_bias = true;
1954 break;
1955 case nir_tex_src_lod:
1956 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
1957 has_lod = true;
1958 break;
1959 case nir_tex_src_comparator: /* shadow comparator */
1960 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
1961 break;
1962 case nir_tex_src_projector:
1963 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
1964 has_proj = true;
1965 break;
1966 case nir_tex_src_offset:
1967 off = ir3_get_src(ctx, &tex->src[i].src);
1968 has_off = true;
1969 break;
1970 case nir_tex_src_ddx:
1971 ddx = ir3_get_src(ctx, &tex->src[i].src);
1972 break;
1973 case nir_tex_src_ddy:
1974 ddy = ir3_get_src(ctx, &tex->src[i].src);
1975 break;
1976 case nir_tex_src_ms_index:
1977 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
1978 break;
1979 case nir_tex_src_texture_offset:
1980 case nir_tex_src_sampler_offset:
1981 /* handled in get_tex_samp_src() */
1982 break;
1983 default:
1984 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
1985 tex->src[i].src_type);
1986 return;
1987 }
1988 }
1989
1990 switch (tex->op) {
1991 case nir_texop_tex_prefetch:
1992 compile_assert(ctx, !has_bias);
1993 compile_assert(ctx, !has_lod);
1994 compile_assert(ctx, !compare);
1995 compile_assert(ctx, !has_proj);
1996 compile_assert(ctx, !has_off);
1997 compile_assert(ctx, !ddx);
1998 compile_assert(ctx, !ddy);
1999 compile_assert(ctx, !sample_index);
2000 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_texture_offset) < 0);
2001 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset) < 0);
2002
2003 if (ctx->so->num_sampler_prefetch < IR3_MAX_SAMPLER_PREFETCH) {
2004 opc = OPC_META_TEX_PREFETCH;
2005 ctx->so->num_sampler_prefetch++;
2006 break;
2007 }
2008 /* fallthru */
2009 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
2010 case nir_texop_txb: opc = OPC_SAMB; break;
2011 case nir_texop_txl: opc = OPC_SAML; break;
2012 case nir_texop_txd: opc = OPC_SAMGQ; break;
2013 case nir_texop_txf: opc = OPC_ISAML; break;
2014 case nir_texop_lod: opc = OPC_GETLOD; break;
2015 case nir_texop_tg4:
2016 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2017 * what blob does, seems gather is broken?), and a3xx did
2018 * not support it (but probably could also emulate).
2019 */
2020 switch (tex->component) {
2021 case 0: opc = OPC_GATHER4R; break;
2022 case 1: opc = OPC_GATHER4G; break;
2023 case 2: opc = OPC_GATHER4B; break;
2024 case 3: opc = OPC_GATHER4A; break;
2025 }
2026 break;
2027 case nir_texop_txf_ms_fb:
2028 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
2029 default:
2030 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
2031 return;
2032 }
2033
2034 tex_info(tex, &flags, &coords);
2035
2036 /*
2037 * lay out the first argument in the proper order:
2038 * - actual coordinates first
2039 * - shadow reference
2040 * - array index
2041 * - projection w
2042 * - starting at offset 4, dpdx.xy, dpdy.xy
2043 *
2044 * bias/lod go into the second arg
2045 */
2046
2047 /* insert tex coords: */
2048 for (i = 0; i < coords; i++)
2049 src0[i] = coord[i];
2050
2051 nsrc0 = i;
2052
2053 /* scale up integer coords for TXF based on the LOD */
2054 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
2055 assert(has_lod);
2056 for (i = 0; i < coords; i++)
2057 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
2058 }
2059
2060 if (coords == 1) {
2061 /* hw doesn't do 1d, so we treat it as 2d with
2062 * height of 1, and patch up the y coord.
2063 */
2064 if (is_isam(opc)) {
2065 src0[nsrc0++] = create_immed(b, 0);
2066 } else {
2067 src0[nsrc0++] = create_immed(b, fui(0.5));
2068 }
2069 }
2070
2071 if (tex->is_shadow && tex->op != nir_texop_lod)
2072 src0[nsrc0++] = compare;
2073
2074 if (tex->is_array && tex->op != nir_texop_lod) {
2075 struct ir3_instruction *idx = coord[coords];
2076
2077 /* the array coord for cube arrays needs 0.5 added to it */
2078 if (ctx->compiler->array_index_add_half && !is_isam(opc))
2079 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
2080
2081 src0[nsrc0++] = idx;
2082 }
2083
2084 if (has_proj) {
2085 src0[nsrc0++] = proj;
2086 flags |= IR3_INSTR_P;
2087 }
2088
2089 /* pad to 4, then ddx/ddy: */
2090 if (tex->op == nir_texop_txd) {
2091 while (nsrc0 < 4)
2092 src0[nsrc0++] = create_immed(b, fui(0.0));
2093 for (i = 0; i < coords; i++)
2094 src0[nsrc0++] = ddx[i];
2095 if (coords < 2)
2096 src0[nsrc0++] = create_immed(b, fui(0.0));
2097 for (i = 0; i < coords; i++)
2098 src0[nsrc0++] = ddy[i];
2099 if (coords < 2)
2100 src0[nsrc0++] = create_immed(b, fui(0.0));
2101 }
2102
2103 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2104 * with scaled x coord according to requested sample:
2105 */
2106 if (opc == OPC_ISAMM) {
2107 if (ctx->compiler->txf_ms_with_isaml) {
2108 /* the samples are laid out in x dimension as
2109 * 0 1 2 3
2110 * x_ms = (x << ms) + sample_index;
2111 */
2112 struct ir3_instruction *ms;
2113 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
2114
2115 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
2116 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
2117
2118 opc = OPC_ISAML;
2119 } else {
2120 src0[nsrc0++] = sample_index;
2121 }
2122 }
2123
2124 /*
2125 * second argument (if applicable):
2126 * - offsets
2127 * - lod
2128 * - bias
2129 */
2130 if (has_off | has_lod | has_bias) {
2131 if (has_off) {
2132 unsigned off_coords = coords;
2133 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2134 off_coords--;
2135 for (i = 0; i < off_coords; i++)
2136 src1[nsrc1++] = off[i];
2137 if (off_coords < 2)
2138 src1[nsrc1++] = create_immed(b, fui(0.0));
2139 flags |= IR3_INSTR_O;
2140 }
2141
2142 if (has_lod | has_bias)
2143 src1[nsrc1++] = lod;
2144 }
2145
2146 switch (tex->dest_type) {
2147 case nir_type_invalid:
2148 case nir_type_float:
2149 type = TYPE_F32;
2150 break;
2151 case nir_type_int:
2152 type = TYPE_S32;
2153 break;
2154 case nir_type_uint:
2155 case nir_type_bool:
2156 type = TYPE_U32;
2157 break;
2158 default:
2159 unreachable("bad dest_type");
2160 }
2161
2162 if (opc == OPC_GETLOD)
2163 type = TYPE_S32;
2164
2165 struct ir3_instruction *samp_tex;
2166
2167 if (tex->op == nir_texop_txf_ms_fb) {
2168 /* only expect a single txf_ms_fb per shader: */
2169 compile_assert(ctx, !ctx->so->fb_read);
2170 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
2171
2172 ctx->so->fb_read = true;
2173 samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2174 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2175 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2176 }, 2);
2177
2178 ctx->so->num_samp++;
2179 } else {
2180 samp_tex = get_tex_samp_tex_src(ctx, tex);
2181 }
2182
2183 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
2184 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
2185
2186 if (opc == OPC_META_TEX_PREFETCH) {
2187 int idx = nir_tex_instr_src_index(tex, nir_tex_src_coord);
2188
2189 compile_assert(ctx, tex->src[idx].src.is_ssa);
2190
2191 sam = ir3_META_TEX_PREFETCH(b);
2192 __ssa_dst(sam)->wrmask = MASK(ncomp); /* dst */
2193 sam->prefetch.input_offset =
2194 ir3_nir_coord_offset(tex->src[idx].src.ssa);
2195 sam->prefetch.tex = tex->texture_index;
2196 sam->prefetch.samp = tex->sampler_index;
2197 } else {
2198 sam = ir3_SAM(b, opc, type, MASK(ncomp), flags,
2199 samp_tex, col0, col1);
2200 }
2201
2202 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
2203 assert(opc != OPC_META_TEX_PREFETCH);
2204
2205 /* only need first 3 components: */
2206 sam->regs[0]->wrmask = 0x7;
2207 ir3_split_dest(b, dst, sam, 0, 3);
2208
2209 /* we need to sample the alpha separately with a non-ASTC
2210 * texture state:
2211 */
2212 sam = ir3_SAM(b, opc, type, 0b1000, flags,
2213 samp_tex, col0, col1);
2214
2215 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
2216
2217 /* fixup .w component: */
2218 ir3_split_dest(b, &dst[3], sam, 3, 1);
2219 } else {
2220 /* normal (non-workaround) case: */
2221 ir3_split_dest(b, dst, sam, 0, ncomp);
2222 }
2223
2224 /* GETLOD returns results in 4.8 fixed point */
2225 if (opc == OPC_GETLOD) {
2226 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
2227
2228 compile_assert(ctx, tex->dest_type == nir_type_float);
2229 for (i = 0; i < 2; i++) {
2230 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_S32, TYPE_F32), 0,
2231 factor, 0);
2232 }
2233 }
2234
2235 ir3_put_dst(ctx, &tex->dest);
2236 }
2237
2238 static void
2239 emit_tex_info(struct ir3_context *ctx, nir_tex_instr *tex, unsigned idx)
2240 {
2241 struct ir3_block *b = ctx->block;
2242 struct ir3_instruction **dst, *sam;
2243
2244 dst = ir3_get_dst(ctx, &tex->dest, 1);
2245
2246 sam = ir3_SAM(b, OPC_GETINFO, TYPE_U32, 1 << idx, 0,
2247 get_tex_samp_tex_src(ctx, tex), NULL, NULL);
2248
2249 /* even though there is only one component, since it ends
2250 * up in .y/.z/.w rather than .x, we need a split_dest()
2251 */
2252 if (idx)
2253 ir3_split_dest(b, dst, sam, 0, idx + 1);
2254
2255 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2256 * the value in TEX_CONST_0 is zero-based.
2257 */
2258 if (ctx->compiler->levels_add_one)
2259 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2260
2261 ir3_put_dst(ctx, &tex->dest);
2262 }
2263
2264 static void
2265 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2266 {
2267 struct ir3_block *b = ctx->block;
2268 struct ir3_instruction **dst, *sam;
2269 struct ir3_instruction *lod;
2270 unsigned flags, coords;
2271
2272 tex_info(tex, &flags, &coords);
2273
2274 /* Actually we want the number of dimensions, not coordinates. This
2275 * distinction only matters for cubes.
2276 */
2277 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2278 coords = 2;
2279
2280 dst = ir3_get_dst(ctx, &tex->dest, 4);
2281
2282 compile_assert(ctx, tex->num_srcs == 1);
2283 compile_assert(ctx, tex->src[0].src_type == nir_tex_src_lod);
2284
2285 lod = ir3_get_src(ctx, &tex->src[0].src)[0];
2286
2287 sam = ir3_SAM(b, OPC_GETSIZE, TYPE_U32, 0b1111, flags,
2288 get_tex_samp_tex_src(ctx, tex), lod, NULL);
2289
2290 ir3_split_dest(b, dst, sam, 0, 4);
2291
2292 /* Array size actually ends up in .w rather than .z. This doesn't
2293 * matter for miplevel 0, but for higher mips the value in z is
2294 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2295 * returned, which means that we have to add 1 to it for arrays.
2296 */
2297 if (tex->is_array) {
2298 if (ctx->compiler->levels_add_one) {
2299 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2300 } else {
2301 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2302 }
2303 }
2304
2305 ir3_put_dst(ctx, &tex->dest);
2306 }
2307
2308 static void
2309 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2310 {
2311 switch (jump->type) {
2312 case nir_jump_break:
2313 case nir_jump_continue:
2314 case nir_jump_return:
2315 /* I *think* we can simply just ignore this, and use the
2316 * successor block link to figure out where we need to
2317 * jump to for break/continue
2318 */
2319 break;
2320 default:
2321 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2322 break;
2323 }
2324 }
2325
2326 static void
2327 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2328 {
2329 switch (instr->type) {
2330 case nir_instr_type_alu:
2331 emit_alu(ctx, nir_instr_as_alu(instr));
2332 break;
2333 case nir_instr_type_deref:
2334 /* ignored, handled as part of the intrinsic they are src to */
2335 break;
2336 case nir_instr_type_intrinsic:
2337 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2338 break;
2339 case nir_instr_type_load_const:
2340 emit_load_const(ctx, nir_instr_as_load_const(instr));
2341 break;
2342 case nir_instr_type_ssa_undef:
2343 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2344 break;
2345 case nir_instr_type_tex: {
2346 nir_tex_instr *tex = nir_instr_as_tex(instr);
2347 /* couple tex instructions get special-cased:
2348 */
2349 switch (tex->op) {
2350 case nir_texop_txs:
2351 emit_tex_txs(ctx, tex);
2352 break;
2353 case nir_texop_query_levels:
2354 emit_tex_info(ctx, tex, 2);
2355 break;
2356 case nir_texop_texture_samples:
2357 emit_tex_info(ctx, tex, 3);
2358 break;
2359 default:
2360 emit_tex(ctx, tex);
2361 break;
2362 }
2363 break;
2364 }
2365 case nir_instr_type_jump:
2366 emit_jump(ctx, nir_instr_as_jump(instr));
2367 break;
2368 case nir_instr_type_phi:
2369 /* we have converted phi webs to regs in NIR by now */
2370 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2371 break;
2372 case nir_instr_type_call:
2373 case nir_instr_type_parallel_copy:
2374 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2375 break;
2376 }
2377 }
2378
2379 static struct ir3_block *
2380 get_block(struct ir3_context *ctx, const nir_block *nblock)
2381 {
2382 struct ir3_block *block;
2383 struct hash_entry *hentry;
2384
2385 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2386 if (hentry)
2387 return hentry->data;
2388
2389 block = ir3_block_create(ctx->ir);
2390 block->nblock = nblock;
2391 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2392
2393 block->predecessors = _mesa_pointer_set_create(block);
2394 set_foreach(nblock->predecessors, sentry) {
2395 _mesa_set_add(block->predecessors, get_block(ctx, sentry->key));
2396 }
2397
2398 return block;
2399 }
2400
2401 static void
2402 emit_block(struct ir3_context *ctx, nir_block *nblock)
2403 {
2404 struct ir3_block *block = get_block(ctx, nblock);
2405
2406 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2407 if (nblock->successors[i]) {
2408 block->successors[i] =
2409 get_block(ctx, nblock->successors[i]);
2410 }
2411 }
2412
2413 ctx->block = block;
2414 list_addtail(&block->node, &ctx->ir->block_list);
2415
2416 /* re-emit addr register in each block if needed: */
2417 for (int i = 0; i < ARRAY_SIZE(ctx->addr_ht); i++) {
2418 _mesa_hash_table_destroy(ctx->addr_ht[i], NULL);
2419 ctx->addr_ht[i] = NULL;
2420 }
2421
2422 nir_foreach_instr(instr, nblock) {
2423 ctx->cur_instr = instr;
2424 emit_instr(ctx, instr);
2425 ctx->cur_instr = NULL;
2426 if (ctx->error)
2427 return;
2428 }
2429 }
2430
2431 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2432
2433 static void
2434 emit_if(struct ir3_context *ctx, nir_if *nif)
2435 {
2436 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2437
2438 ctx->block->condition =
2439 ir3_get_predicate(ctx, ir3_b2n(condition->block, condition));
2440
2441 emit_cf_list(ctx, &nif->then_list);
2442 emit_cf_list(ctx, &nif->else_list);
2443 }
2444
2445 static void
2446 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2447 {
2448 emit_cf_list(ctx, &nloop->body);
2449 ctx->so->loops++;
2450 }
2451
2452 static void
2453 stack_push(struct ir3_context *ctx)
2454 {
2455 ctx->stack++;
2456 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2457 }
2458
2459 static void
2460 stack_pop(struct ir3_context *ctx)
2461 {
2462 compile_assert(ctx, ctx->stack > 0);
2463 ctx->stack--;
2464 }
2465
2466 static void
2467 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2468 {
2469 foreach_list_typed(nir_cf_node, node, node, list) {
2470 switch (node->type) {
2471 case nir_cf_node_block:
2472 emit_block(ctx, nir_cf_node_as_block(node));
2473 break;
2474 case nir_cf_node_if:
2475 stack_push(ctx);
2476 emit_if(ctx, nir_cf_node_as_if(node));
2477 stack_pop(ctx);
2478 break;
2479 case nir_cf_node_loop:
2480 stack_push(ctx);
2481 emit_loop(ctx, nir_cf_node_as_loop(node));
2482 stack_pop(ctx);
2483 break;
2484 case nir_cf_node_function:
2485 ir3_context_error(ctx, "TODO\n");
2486 break;
2487 }
2488 }
2489 }
2490
2491 /* emit stream-out code. At this point, the current block is the original
2492 * (nir) end block, and nir ensures that all flow control paths terminate
2493 * into the end block. We re-purpose the original end block to generate
2494 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2495 * block holding stream-out write instructions, followed by the new end
2496 * block:
2497 *
2498 * blockOrigEnd {
2499 * p0.x = (vtxcnt < maxvtxcnt)
2500 * // succs: blockStreamOut, blockNewEnd
2501 * }
2502 * blockStreamOut {
2503 * ... stream-out instructions ...
2504 * // succs: blockNewEnd
2505 * }
2506 * blockNewEnd {
2507 * }
2508 */
2509 static void
2510 emit_stream_out(struct ir3_context *ctx)
2511 {
2512 struct ir3 *ir = ctx->ir;
2513 struct ir3_stream_output_info *strmout =
2514 &ctx->so->shader->stream_output;
2515 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2516 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2517 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2518
2519 /* create vtxcnt input in input block at top of shader,
2520 * so that it is seen as live over the entire duration
2521 * of the shader:
2522 */
2523 vtxcnt = create_input(ctx, 0);
2524 add_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, vtxcnt);
2525
2526 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2527
2528 /* at this point, we are at the original 'end' block,
2529 * re-purpose this block to stream-out condition, then
2530 * append stream-out block and new-end block
2531 */
2532 orig_end_block = ctx->block;
2533
2534 // TODO these blocks need to update predecessors..
2535 // maybe w/ store_global intrinsic, we could do this
2536 // stuff in nir->nir pass
2537
2538 stream_out_block = ir3_block_create(ir);
2539 list_addtail(&stream_out_block->node, &ir->block_list);
2540
2541 new_end_block = ir3_block_create(ir);
2542 list_addtail(&new_end_block->node, &ir->block_list);
2543
2544 orig_end_block->successors[0] = stream_out_block;
2545 orig_end_block->successors[1] = new_end_block;
2546 stream_out_block->successors[0] = new_end_block;
2547
2548 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2549 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2550 cond->regs[0]->num = regid(REG_P0, 0);
2551 cond->regs[0]->flags &= ~IR3_REG_SSA;
2552 cond->cat2.condition = IR3_COND_LT;
2553
2554 /* condition goes on previous block to the conditional,
2555 * since it is used to pick which of the two successor
2556 * paths to take:
2557 */
2558 orig_end_block->condition = cond;
2559
2560 /* switch to stream_out_block to generate the stream-out
2561 * instructions:
2562 */
2563 ctx->block = stream_out_block;
2564
2565 /* Calculate base addresses based on vtxcnt. Instructions
2566 * generated for bases not used in following loop will be
2567 * stripped out in the backend.
2568 */
2569 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2570 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
2571 unsigned stride = strmout->stride[i];
2572 struct ir3_instruction *base, *off;
2573
2574 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
2575
2576 /* 24-bit should be enough: */
2577 off = ir3_MUL_U24(ctx->block, vtxcnt, 0,
2578 create_immed(ctx->block, stride * 4), 0);
2579
2580 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2581 }
2582
2583 /* Generate the per-output store instructions: */
2584 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2585 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2586 unsigned c = j + strmout->output[i].start_component;
2587 struct ir3_instruction *base, *out, *stg;
2588
2589 base = bases[strmout->output[i].output_buffer];
2590 out = ctx->ir->outputs[regid(strmout->output[i].register_index, c)];
2591
2592 stg = ir3_STG(ctx->block, base, 0, out, 0,
2593 create_immed(ctx->block, 1), 0);
2594 stg->cat6.type = TYPE_U32;
2595 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2596
2597 array_insert(ctx->block, ctx->block->keeps, stg);
2598 }
2599 }
2600
2601 /* and finally switch to the new_end_block: */
2602 ctx->block = new_end_block;
2603 }
2604
2605 static void
2606 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2607 {
2608 nir_metadata_require(impl, nir_metadata_block_index);
2609
2610 compile_assert(ctx, ctx->stack == 0);
2611
2612 emit_cf_list(ctx, &impl->body);
2613 emit_block(ctx, impl->end_block);
2614
2615 compile_assert(ctx, ctx->stack == 0);
2616
2617 /* at this point, we should have a single empty block,
2618 * into which we emit the 'end' instruction.
2619 */
2620 compile_assert(ctx, list_is_empty(&ctx->block->instr_list));
2621
2622 /* If stream-out (aka transform-feedback) enabled, emit the
2623 * stream-out instructions, followed by a new empty block (into
2624 * which the 'end' instruction lands).
2625 *
2626 * NOTE: it is done in this order, rather than inserting before
2627 * we emit end_block, because NIR guarantees that all blocks
2628 * flow into end_block, and that end_block has no successors.
2629 * So by re-purposing end_block as the first block of stream-
2630 * out, we guarantee that all exit paths flow into the stream-
2631 * out instructions.
2632 */
2633 if ((ctx->compiler->gpu_id < 500) &&
2634 (ctx->so->shader->stream_output.num_outputs > 0) &&
2635 !ctx->so->binning_pass) {
2636 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2637 emit_stream_out(ctx);
2638 }
2639
2640 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2641 * NOP and has an epilogue that writes the VS outputs to local storage, to
2642 * be read by the HS. Then it resets execution mask (chmask) and chains
2643 * to the next shader (chsh).
2644 */
2645 if ((ctx->so->type == MESA_SHADER_VERTEX &&
2646 (ctx->so->key.has_gs || ctx->so->key.tessellation)) ||
2647 (ctx->so->type == MESA_SHADER_TESS_EVAL && ctx->so->key.has_gs)) {
2648 struct ir3_instruction *chmask =
2649 ir3_CHMASK(ctx->block);
2650 chmask->barrier_class = IR3_BARRIER_EVERYTHING;
2651 chmask->barrier_conflict = IR3_BARRIER_EVERYTHING;
2652
2653 struct ir3_instruction *chsh =
2654 ir3_CHSH(ctx->block);
2655 chsh->barrier_class = IR3_BARRIER_EVERYTHING;
2656 chsh->barrier_conflict = IR3_BARRIER_EVERYTHING;
2657 } else {
2658 ir3_END(ctx->block);
2659 }
2660 }
2661
2662 static void
2663 setup_input(struct ir3_context *ctx, nir_variable *in)
2664 {
2665 struct ir3_shader_variant *so = ctx->so;
2666 unsigned ncomp = glsl_get_components(in->type);
2667 unsigned n = in->data.driver_location;
2668 unsigned frac = in->data.location_frac;
2669 unsigned slot = in->data.location;
2670
2671 /* Inputs are loaded using ldlw or ldg for these stages. */
2672 if (ctx->so->type == MESA_SHADER_TESS_CTRL ||
2673 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2674 ctx->so->type == MESA_SHADER_GEOMETRY)
2675 return;
2676
2677 /* skip unread inputs, we could end up with (for example), unsplit
2678 * matrix/etc inputs in the case they are not read, so just silently
2679 * skip these.
2680 */
2681 if (ncomp > 4)
2682 return;
2683
2684 so->inputs[n].slot = slot;
2685 so->inputs[n].compmask = (1 << (ncomp + frac)) - 1;
2686 so->inputs_count = MAX2(so->inputs_count, n + 1);
2687 so->inputs[n].interpolate = in->data.interpolation;
2688
2689 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2690
2691 /* if any varyings have 'sample' qualifer, that triggers us
2692 * to run in per-sample mode:
2693 */
2694 so->per_samp |= in->data.sample;
2695
2696 for (int i = 0; i < ncomp; i++) {
2697 struct ir3_instruction *instr = NULL;
2698 unsigned idx = (n * 4) + i + frac;
2699
2700 if (slot == VARYING_SLOT_POS) {
2701 ir3_context_error(ctx, "fragcoord should be a sysval!\n");
2702 } else if (slot == VARYING_SLOT_PNTC) {
2703 /* see for example st_nir_fixup_varying_slots().. this is
2704 * maybe a bit mesa/st specific. But we need things to line
2705 * up for this in fdN_program:
2706 * unsigned texmask = 1 << (slot - VARYING_SLOT_VAR0);
2707 * if (emit->sprite_coord_enable & texmask) {
2708 * ...
2709 * }
2710 */
2711 so->inputs[n].slot = VARYING_SLOT_VAR8;
2712 so->inputs[n].bary = true;
2713 instr = create_frag_input(ctx, false, idx);
2714 } else {
2715 /* detect the special case for front/back colors where
2716 * we need to do flat vs smooth shading depending on
2717 * rast state:
2718 */
2719 if (in->data.interpolation == INTERP_MODE_NONE) {
2720 switch (slot) {
2721 case VARYING_SLOT_COL0:
2722 case VARYING_SLOT_COL1:
2723 case VARYING_SLOT_BFC0:
2724 case VARYING_SLOT_BFC1:
2725 so->inputs[n].rasterflat = true;
2726 break;
2727 default:
2728 break;
2729 }
2730 }
2731
2732 if (ctx->compiler->flat_bypass) {
2733 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2734 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2735 so->inputs[n].use_ldlv = true;
2736 }
2737
2738 so->inputs[n].bary = true;
2739
2740 instr = create_frag_input(ctx, so->inputs[n].use_ldlv, idx);
2741 }
2742
2743 compile_assert(ctx, idx < ctx->ir->ninputs);
2744
2745 ctx->ir->inputs[idx] = instr;
2746 }
2747 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2748 for (int i = 0; i < ncomp; i++) {
2749 unsigned idx = (n * 4) + i + frac;
2750 compile_assert(ctx, idx < ctx->ir->ninputs);
2751 ctx->ir->inputs[idx] = create_input(ctx, idx);
2752 }
2753 } else {
2754 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2755 }
2756
2757 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
2758 so->total_in += ncomp;
2759 }
2760 }
2761
2762 /* Initially we assign non-packed inloc's for varyings, as we don't really
2763 * know up-front which components will be unused. After all the compilation
2764 * stages we scan the shader to see which components are actually used, and
2765 * re-pack the inlocs to eliminate unneeded varyings.
2766 */
2767 static void
2768 pack_inlocs(struct ir3_context *ctx)
2769 {
2770 struct ir3_shader_variant *so = ctx->so;
2771 uint8_t used_components[so->inputs_count];
2772
2773 memset(used_components, 0, sizeof(used_components));
2774
2775 /*
2776 * First Step: scan shader to find which bary.f/ldlv remain:
2777 */
2778
2779 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) {
2780 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
2781 if (is_input(instr)) {
2782 unsigned inloc = instr->regs[1]->iim_val;
2783 unsigned i = inloc / 4;
2784 unsigned j = inloc % 4;
2785
2786 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
2787 compile_assert(ctx, i < so->inputs_count);
2788
2789 used_components[i] |= 1 << j;
2790 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
2791 for (int n = 0; n < 2; n++) {
2792 unsigned inloc = instr->prefetch.input_offset + n;
2793 unsigned i = inloc / 4;
2794 unsigned j = inloc % 4;
2795
2796 compile_assert(ctx, i < so->inputs_count);
2797
2798 used_components[i] |= 1 << j;
2799 }
2800 }
2801 }
2802 }
2803
2804 /*
2805 * Second Step: reassign varying inloc/slots:
2806 */
2807
2808 unsigned actual_in = 0;
2809 unsigned inloc = 0;
2810
2811 for (unsigned i = 0; i < so->inputs_count; i++) {
2812 unsigned compmask = 0, maxcomp = 0;
2813
2814 so->inputs[i].inloc = inloc;
2815 so->inputs[i].bary = false;
2816
2817 for (unsigned j = 0; j < 4; j++) {
2818 if (!(used_components[i] & (1 << j)))
2819 continue;
2820
2821 compmask |= (1 << j);
2822 actual_in++;
2823 maxcomp = j + 1;
2824
2825 /* at this point, since used_components[i] mask is only
2826 * considering varyings (ie. not sysvals) we know this
2827 * is a varying:
2828 */
2829 so->inputs[i].bary = true;
2830 }
2831
2832 if (so->inputs[i].bary) {
2833 so->varying_in++;
2834 so->inputs[i].compmask = (1 << maxcomp) - 1;
2835 inloc += maxcomp;
2836 }
2837 }
2838
2839 /*
2840 * Third Step: reassign packed inloc's:
2841 */
2842
2843 list_for_each_entry (struct ir3_block, block, &ctx->ir->block_list, node) {
2844 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
2845 if (is_input(instr)) {
2846 unsigned inloc = instr->regs[1]->iim_val;
2847 unsigned i = inloc / 4;
2848 unsigned j = inloc % 4;
2849
2850 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
2851 }
2852 }
2853 }
2854 }
2855
2856 static void
2857 setup_output(struct ir3_context *ctx, nir_variable *out)
2858 {
2859 struct ir3_shader_variant *so = ctx->so;
2860 unsigned ncomp = glsl_get_components(out->type);
2861 unsigned n = out->data.driver_location;
2862 unsigned frac = out->data.location_frac;
2863 unsigned slot = out->data.location;
2864 unsigned comp = 0;
2865
2866 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2867 switch (slot) {
2868 case FRAG_RESULT_DEPTH:
2869 comp = 2; /* tgsi will write to .z component */
2870 so->writes_pos = true;
2871 break;
2872 case FRAG_RESULT_COLOR:
2873 so->color0_mrt = 1;
2874 break;
2875 case FRAG_RESULT_SAMPLE_MASK:
2876 so->writes_smask = true;
2877 break;
2878 default:
2879 if (slot >= FRAG_RESULT_DATA0)
2880 break;
2881 ir3_context_error(ctx, "unknown FS output name: %s\n",
2882 gl_frag_result_name(slot));
2883 }
2884 } else if (ctx->so->type == MESA_SHADER_VERTEX ||
2885 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2886 ctx->so->type == MESA_SHADER_GEOMETRY) {
2887 switch (slot) {
2888 case VARYING_SLOT_POS:
2889 so->writes_pos = true;
2890 break;
2891 case VARYING_SLOT_PSIZ:
2892 so->writes_psize = true;
2893 break;
2894 case VARYING_SLOT_PRIMITIVE_ID:
2895 case VARYING_SLOT_LAYER:
2896 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
2897 debug_assert(ctx->so->type == MESA_SHADER_GEOMETRY);
2898 /* fall through */
2899 case VARYING_SLOT_COL0:
2900 case VARYING_SLOT_COL1:
2901 case VARYING_SLOT_BFC0:
2902 case VARYING_SLOT_BFC1:
2903 case VARYING_SLOT_FOGC:
2904 case VARYING_SLOT_CLIP_DIST0:
2905 case VARYING_SLOT_CLIP_DIST1:
2906 case VARYING_SLOT_CLIP_VERTEX:
2907 break;
2908 default:
2909 if (slot >= VARYING_SLOT_VAR0)
2910 break;
2911 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
2912 break;
2913 ir3_context_error(ctx, "unknown %s shader output name: %s\n",
2914 _mesa_shader_stage_to_string(ctx->so->type),
2915 gl_varying_slot_name(slot));
2916 }
2917 } else if (ctx->so->type == MESA_SHADER_TESS_CTRL) {
2918 /* output lowered to buffer writes. */
2919 return;
2920 } else {
2921 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
2922 }
2923
2924 compile_assert(ctx, n < ARRAY_SIZE(so->outputs));
2925
2926 so->outputs[n].slot = slot;
2927 so->outputs[n].regid = regid(n, comp);
2928 so->outputs_count = MAX2(so->outputs_count, n + 1);
2929
2930 for (int i = 0; i < ncomp; i++) {
2931 unsigned idx = (n * 4) + i + frac;
2932 compile_assert(ctx, idx < ctx->ir->noutputs);
2933 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2934 }
2935
2936 /* if varying packing doesn't happen, we could end up in a situation
2937 * with "holes" in the output, and since the per-generation code that
2938 * sets up varying linkage registers doesn't expect to have more than
2939 * one varying per vec4 slot, pad the holes.
2940 *
2941 * Note that this should probably generate a performance warning of
2942 * some sort.
2943 */
2944 for (int i = 0; i < frac; i++) {
2945 unsigned idx = (n * 4) + i;
2946 if (!ctx->ir->outputs[idx]) {
2947 ctx->ir->outputs[idx] = create_immed(ctx->block, fui(0.0));
2948 }
2949 }
2950 }
2951
2952 static int
2953 max_drvloc(struct exec_list *vars)
2954 {
2955 int drvloc = -1;
2956 nir_foreach_variable(var, vars) {
2957 drvloc = MAX2(drvloc, (int)var->data.driver_location);
2958 }
2959 return drvloc;
2960 }
2961
2962 static const unsigned max_sysvals[] = {
2963 [MESA_SHADER_VERTEX] = 16,
2964 [MESA_SHADER_TESS_CTRL] = 16,
2965 [MESA_SHADER_TESS_EVAL] = 16,
2966 [MESA_SHADER_GEOMETRY] = 16,
2967 [MESA_SHADER_FRAGMENT] = 24, // TODO
2968 [MESA_SHADER_COMPUTE] = 16, // TODO how many do we actually need?
2969 [MESA_SHADER_KERNEL] = 16, // TODO how many do we actually need?
2970 };
2971
2972 static void
2973 emit_instructions(struct ir3_context *ctx)
2974 {
2975 unsigned ninputs, noutputs;
2976 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
2977
2978 ninputs = (max_drvloc(&ctx->s->inputs) + 1) * 4;
2979 noutputs = (max_drvloc(&ctx->s->outputs) + 1) * 4;
2980
2981 /* we need to leave room for sysvals:
2982 */
2983 ninputs += max_sysvals[ctx->so->type];
2984 if (ctx->so->type == MESA_SHADER_VERTEX ||
2985 ctx->so->type == MESA_SHADER_TESS_EVAL)
2986 noutputs += 8; /* gs or tess header + primitive_id */
2987
2988 ctx->ir = ir3_create(ctx->compiler, ctx->so->type, ninputs, noutputs);
2989
2990 /* Create inputs in first block: */
2991 ctx->block = get_block(ctx, nir_start_block(fxn));
2992 ctx->in_block = ctx->block;
2993 list_addtail(&ctx->block->node, &ctx->ir->block_list);
2994
2995 ninputs -= max_sysvals[ctx->so->type];
2996
2997 /* Tesselation shaders always need primitive ID for indexing the
2998 * BO. Geometry shaders don't always need it but when they do it has be
2999 * delivered and unclobbered in the VS. To make things easy, we always
3000 * make room for it in VS/DS.
3001 */
3002 bool has_tess = ctx->so->key.tessellation != IR3_TESS_NONE;
3003 bool has_gs = ctx->so->key.has_gs;
3004 switch (ctx->so->type) {
3005 case MESA_SHADER_VERTEX:
3006 if (has_tess) {
3007 ctx->tcs_header = create_input(ctx, 0);
3008 ctx->primitive_id = create_input(ctx, 0);
3009 } else if (has_gs) {
3010 ctx->gs_header = create_input(ctx, 0);
3011 ctx->primitive_id = create_input(ctx, 0);
3012 }
3013 break;
3014 case MESA_SHADER_TESS_CTRL:
3015 ctx->tcs_header = create_input(ctx, 0);
3016 ctx->primitive_id = create_input(ctx, 0);
3017 break;
3018 case MESA_SHADER_TESS_EVAL:
3019 if (has_gs)
3020 ctx->gs_header = create_input(ctx, 0);
3021 ctx->primitive_id = create_input(ctx, 0);
3022 break;
3023 case MESA_SHADER_GEOMETRY:
3024 ctx->gs_header = create_input(ctx, 0);
3025 ctx->primitive_id = create_input(ctx, 0);
3026 break;
3027 default:
3028 break;
3029 }
3030
3031 /* for fragment shader, the vcoord input register is used as the
3032 * base for bary.f varying fetch instrs:
3033 *
3034 * TODO defer creating ctx->ij_pixel and corresponding sysvals
3035 * until emit_intrinsic when we know they are actually needed.
3036 * For now, we defer creating ctx->ij_centroid, etc, since we
3037 * only need ij_pixel for "old style" varying inputs (ie.
3038 * tgsi_to_nir)
3039 */
3040 struct ir3_instruction *vcoord = NULL;
3041 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3042 struct ir3_instruction *xy[2];
3043
3044 vcoord = create_input_compmask(ctx, 0, 0x3);
3045 ir3_split_dest(ctx->block, xy, vcoord, 0, 2);
3046
3047 ctx->ij_pixel = ir3_create_collect(ctx, xy, 2);
3048 }
3049
3050 /* Setup inputs: */
3051 nir_foreach_variable(var, &ctx->s->inputs) {
3052 setup_input(ctx, var);
3053 }
3054
3055 /* Defer add_sysval_input() stuff until after setup_inputs(),
3056 * because sysvals need to be appended after varyings:
3057 */
3058 if (vcoord) {
3059 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PIXEL,
3060 0x3, vcoord);
3061 }
3062
3063 if (ctx->primitive_id)
3064 add_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, ctx->primitive_id);
3065 if (ctx->gs_header)
3066 add_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, ctx->gs_header);
3067 if (ctx->tcs_header)
3068 add_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, ctx->tcs_header);
3069
3070 /* Setup outputs: */
3071 nir_foreach_variable(var, &ctx->s->outputs) {
3072 setup_output(ctx, var);
3073 }
3074
3075 /* Set up the shared system values as outputs for the vertex and tess eval
3076 * shaders so they don't clobber them for the next shader in the pipeline.
3077 */
3078 if (ctx->so->type == MESA_SHADER_VERTEX ||
3079 (has_gs && ctx->so->type == MESA_SHADER_TESS_EVAL)) {
3080 struct ir3_shader_variant *so = ctx->so;
3081 if (ctx->primitive_id) {
3082 unsigned n = so->outputs_count++;
3083 so->outputs[n].slot = VARYING_SLOT_PRIMITIVE_ID;
3084 so->outputs[n].regid = regid(n, 0);
3085 ctx->ir->outputs[n * 4] = ctx->primitive_id;
3086
3087 compile_assert(ctx, n * 4 < ctx->ir->noutputs);
3088 }
3089
3090 if (ctx->gs_header) {
3091 unsigned n = so->outputs_count++;
3092 so->outputs[n].slot = VARYING_SLOT_GS_HEADER_IR3;
3093 so->outputs[n].regid = regid(n, 0);
3094 ctx->ir->outputs[n * 4] = ctx->gs_header;
3095
3096 compile_assert(ctx, n * 4 < ctx->ir->noutputs);
3097 }
3098
3099 if (ctx->tcs_header) {
3100 unsigned n = so->outputs_count++;
3101 so->outputs[n].slot = VARYING_SLOT_TCS_HEADER_IR3;
3102 so->outputs[n].regid = regid(n, 0);
3103 ctx->ir->outputs[n * 4] = ctx->tcs_header;
3104
3105 compile_assert(ctx, n * 4 < ctx->ir->noutputs);
3106 }
3107 }
3108
3109 /* Find # of samplers: */
3110 nir_foreach_variable(var, &ctx->s->uniforms) {
3111 ctx->so->num_samp += glsl_type_get_sampler_count(var->type);
3112 /* just assume that we'll be reading from images.. if it
3113 * is write-only we don't have to count it, but not sure
3114 * if there is a good way to know?
3115 */
3116 ctx->so->num_samp += glsl_type_get_image_count(var->type);
3117 }
3118
3119 /* NOTE: need to do something more clever when we support >1 fxn */
3120 nir_foreach_register(reg, &fxn->registers) {
3121 ir3_declare_array(ctx, reg);
3122 }
3123 /* And emit the body: */
3124 ctx->impl = fxn;
3125 emit_function(ctx, fxn);
3126 }
3127
3128 /* from NIR perspective, we actually have varying inputs. But the varying
3129 * inputs, from an IR standpoint, are just bary.f/ldlv instructions. The
3130 * only actual inputs are the sysvals.
3131 */
3132 static void
3133 fixup_frag_inputs(struct ir3_context *ctx)
3134 {
3135 struct ir3_shader_variant *so = ctx->so;
3136 struct ir3 *ir = ctx->ir;
3137 unsigned i = 0;
3138
3139 /* sysvals should appear at the end of the inputs, drop everything else: */
3140 while ((i < so->inputs_count) && !so->inputs[i].sysval)
3141 i++;
3142
3143 /* at IR level, inputs are always blocks of 4 scalars: */
3144 i *= 4;
3145
3146 ir->inputs = &ir->inputs[i];
3147 ir->ninputs -= i;
3148 }
3149
3150 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3151 * need to assign the tex state indexes for these after we know the
3152 * max tex index.
3153 */
3154 static void
3155 fixup_astc_srgb(struct ir3_context *ctx)
3156 {
3157 struct ir3_shader_variant *so = ctx->so;
3158 /* indexed by original tex idx, value is newly assigned alpha sampler
3159 * state tex idx. Zero is invalid since there is at least one sampler
3160 * if we get here.
3161 */
3162 unsigned alt_tex_state[16] = {0};
3163 unsigned tex_idx = ctx->max_texture_index + 1;
3164 unsigned idx = 0;
3165
3166 so->astc_srgb.base = tex_idx;
3167
3168 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
3169 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
3170
3171 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
3172
3173 if (alt_tex_state[sam->cat5.tex] == 0) {
3174 /* assign new alternate/alpha tex state slot: */
3175 alt_tex_state[sam->cat5.tex] = tex_idx++;
3176 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
3177 so->astc_srgb.count++;
3178 }
3179
3180 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
3181 }
3182 }
3183
3184 static void
3185 fixup_binning_pass(struct ir3_context *ctx)
3186 {
3187 struct ir3_shader_variant *so = ctx->so;
3188 struct ir3 *ir = ctx->ir;
3189 unsigned i, j;
3190
3191 for (i = 0, j = 0; i < so->outputs_count; i++) {
3192 unsigned slot = so->outputs[i].slot;
3193
3194 /* throw away everything but first position/psize */
3195 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3196 if (i != j) {
3197 so->outputs[j] = so->outputs[i];
3198 ir->outputs[(j*4)+0] = ir->outputs[(i*4)+0];
3199 ir->outputs[(j*4)+1] = ir->outputs[(i*4)+1];
3200 ir->outputs[(j*4)+2] = ir->outputs[(i*4)+2];
3201 ir->outputs[(j*4)+3] = ir->outputs[(i*4)+3];
3202 }
3203 j++;
3204 }
3205 }
3206 so->outputs_count = j;
3207 ir->noutputs = j * 4;
3208 }
3209
3210 static void
3211 collect_tex_prefetches(struct ir3_context *ctx, struct ir3 *ir)
3212 {
3213 unsigned idx = 0;
3214
3215 /* Collect sampling instructions eligible for pre-dispatch. */
3216 list_for_each_entry(struct ir3_block, block, &ir->block_list, node) {
3217 list_for_each_entry_safe(struct ir3_instruction, instr,
3218 &block->instr_list, node) {
3219 if (instr->opc == OPC_META_TEX_PREFETCH) {
3220 assert(idx < ARRAY_SIZE(ctx->so->sampler_prefetch));
3221 struct ir3_sampler_prefetch *fetch =
3222 &ctx->so->sampler_prefetch[idx];
3223 idx++;
3224
3225 fetch->cmd = IR3_SAMPLER_PREFETCH_CMD;
3226 fetch->wrmask = instr->regs[0]->wrmask;
3227 fetch->tex_id = instr->prefetch.tex;
3228 fetch->samp_id = instr->prefetch.samp;
3229 fetch->dst = instr->regs[0]->num;
3230 fetch->src = instr->prefetch.input_offset;
3231
3232 ctx->so->total_in =
3233 MAX2(ctx->so->total_in, instr->prefetch.input_offset + 2);
3234
3235 /* Disable half precision until supported. */
3236 fetch->half_precision = 0x0;
3237
3238 /* Remove the prefetch placeholder instruction: */
3239 list_delinit(&instr->node);
3240 }
3241 }
3242 }
3243 }
3244
3245 int
3246 ir3_compile_shader_nir(struct ir3_compiler *compiler,
3247 struct ir3_shader_variant *so)
3248 {
3249 struct ir3_context *ctx;
3250 struct ir3 *ir;
3251 struct ir3_instruction **inputs;
3252 unsigned i;
3253 int ret = 0, max_bary;
3254
3255 assert(!so->ir);
3256
3257 ctx = ir3_context_init(compiler, so);
3258 if (!ctx) {
3259 DBG("INIT failed!");
3260 ret = -1;
3261 goto out;
3262 }
3263
3264 emit_instructions(ctx);
3265
3266 if (ctx->error) {
3267 DBG("EMIT failed!");
3268 ret = -1;
3269 goto out;
3270 }
3271
3272 ir = so->ir = ctx->ir;
3273
3274 /* keep track of the inputs from TGSI perspective.. */
3275 inputs = ir->inputs;
3276
3277 /* but fixup actual inputs for frag shader: */
3278 if (so->type == MESA_SHADER_FRAGMENT)
3279 fixup_frag_inputs(ctx);
3280
3281 /* at this point, for binning pass, throw away unneeded outputs: */
3282 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
3283 fixup_binning_pass(ctx);
3284
3285 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3286 printf("BEFORE CP:\n");
3287 ir3_print(ir);
3288 }
3289
3290 ir3_cp(ir, so);
3291
3292 /* at this point, for binning pass, throw away unneeded outputs:
3293 * Note that for a6xx and later, we do this after ir3_cp to ensure
3294 * that the uniform/constant layout for BS and VS matches, so that
3295 * we can re-use same VS_CONST state group.
3296 */
3297 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
3298 fixup_binning_pass(ctx);
3299
3300 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3301 * need to make sure not to remove any inputs that are used by
3302 * the nonbinning VS.
3303 */
3304 if (ctx->compiler->gpu_id >= 600 && so->binning_pass &&
3305 so->type == MESA_SHADER_VERTEX) {
3306 for (int i = 0; i < ir->ninputs; i++) {
3307 struct ir3_instruction *in = ir->inputs[i];
3308
3309 if (!in)
3310 continue;
3311
3312 unsigned n = i / 4;
3313 unsigned c = i % 4;
3314
3315 debug_assert(n < so->nonbinning->inputs_count);
3316
3317 if (so->nonbinning->inputs[n].sysval)
3318 continue;
3319
3320 /* be sure to keep inputs, even if only used in VS */
3321 if (so->nonbinning->inputs[n].compmask & (1 << c))
3322 array_insert(in->block, in->block->keeps, in);
3323 }
3324 }
3325
3326 /* Insert mov if there's same instruction for each output.
3327 * eg. dEQP-GLES31.functional.shaders.opaque_type_indexing.sampler.const_expression.vertex.sampler2dshadow
3328 */
3329 for (int i = ir->noutputs - 1; i >= 0; i--) {
3330 if (!ir->outputs[i])
3331 continue;
3332 for (unsigned j = 0; j < i; j++) {
3333 if (ir->outputs[i] == ir->outputs[j]) {
3334 ir->outputs[i] =
3335 ir3_MOV(ir->outputs[i]->block, ir->outputs[i], TYPE_F32);
3336 }
3337 }
3338 }
3339
3340 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3341 printf("BEFORE GROUPING:\n");
3342 ir3_print(ir);
3343 }
3344
3345 ir3_sched_add_deps(ir);
3346
3347 /* Group left/right neighbors, inserting mov's where needed to
3348 * solve conflicts:
3349 */
3350 ir3_group(ir);
3351
3352 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3353 printf("AFTER GROUPING:\n");
3354 ir3_print(ir);
3355 }
3356
3357 ir3_depth(ir, so);
3358
3359 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3360 printf("AFTER DEPTH:\n");
3361 ir3_print(ir);
3362 }
3363
3364 /* do Sethi–Ullman numbering before scheduling: */
3365 ir3_sun(ir);
3366
3367 ret = ir3_sched(ir);
3368 if (ret) {
3369 DBG("SCHED failed!");
3370 goto out;
3371 }
3372
3373 if (compiler->gpu_id >= 600) {
3374 ir3_a6xx_fixup_atomic_dests(ir, so);
3375 }
3376
3377 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3378 printf("AFTER SCHED:\n");
3379 ir3_print(ir);
3380 }
3381
3382 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3383 * with draw pass VS, so binning and draw pass can both use the
3384 * same VBO state.
3385 *
3386 * Note that VS inputs are expected to be full precision.
3387 */
3388 bool pre_assign_inputs = (ir->compiler->gpu_id >= 600) &&
3389 (ir->type == MESA_SHADER_VERTEX) &&
3390 so->binning_pass;
3391
3392 if (pre_assign_inputs) {
3393 for (unsigned i = 0; i < ir->ninputs; i++) {
3394 struct ir3_instruction *instr = ir->inputs[i];
3395
3396 if (!instr)
3397 continue;
3398
3399 unsigned n = i / 4;
3400 unsigned c = i % 4;
3401 unsigned regid = so->nonbinning->inputs[n].regid + c;
3402
3403 instr->regs[0]->num = regid;
3404 }
3405
3406 ret = ir3_ra(so, ir->inputs, ir->ninputs);
3407 } else if (ctx->tcs_header) {
3408 /* We need to have these values in the same registers between VS and TCS
3409 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3410 */
3411
3412 ctx->tcs_header->regs[0]->num = regid(0, 0);
3413 ctx->primitive_id->regs[0]->num = regid(0, 1);
3414 struct ir3_instruction *precolor[] = { ctx->tcs_header, ctx->primitive_id };
3415 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3416 } else if (ctx->gs_header) {
3417 /* We need to have these values in the same registers between producer
3418 * (VS or DS) and GS since the producer chains to GS and doesn't get
3419 * the sysvals redelivered.
3420 */
3421
3422 ctx->gs_header->regs[0]->num = regid(0, 0);
3423 ctx->primitive_id->regs[0]->num = regid(0, 1);
3424 struct ir3_instruction *precolor[] = { ctx->gs_header, ctx->primitive_id };
3425 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3426 } else if (so->num_sampler_prefetch) {
3427 assert(so->type == MESA_SHADER_FRAGMENT);
3428 struct ir3_instruction *instr, *precolor[2];
3429 int idx = 0;
3430
3431 foreach_input(instr, ir) {
3432 if (instr->input.sysval != SYSTEM_VALUE_BARYCENTRIC_PIXEL)
3433 continue;
3434
3435 assert(idx < ARRAY_SIZE(precolor));
3436
3437 precolor[idx] = instr;
3438 instr->regs[0]->num = idx;
3439
3440 idx++;
3441 }
3442 ret = ir3_ra(so, precolor, idx);
3443 } else {
3444 ret = ir3_ra(so, NULL, 0);
3445 }
3446
3447 if (ret) {
3448 DBG("RA failed!");
3449 goto out;
3450 }
3451
3452 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3453 printf("AFTER RA:\n");
3454 ir3_print(ir);
3455 }
3456
3457 if (so->type == MESA_SHADER_FRAGMENT)
3458 pack_inlocs(ctx);
3459
3460 /* fixup input/outputs: */
3461 for (i = 0; i < so->outputs_count; i++) {
3462 /* sometimes we get outputs that don't write the .x coord, like:
3463 *
3464 * decl_var shader_out INTERP_MODE_NONE float Color (VARYING_SLOT_VAR9.z, 1, 0)
3465 *
3466 * Presumably the result of varying packing and then eliminating
3467 * some unneeded varyings? Just skip head to the first valid
3468 * component of the output.
3469 */
3470 for (unsigned j = 0; j < 4; j++) {
3471 struct ir3_instruction *instr = ir->outputs[(i*4) + j];
3472 if (instr) {
3473 so->outputs[i].regid = instr->regs[0]->num;
3474 so->outputs[i].half = !!(instr->regs[0]->flags & IR3_REG_HALF);
3475 break;
3476 }
3477 }
3478 }
3479
3480 /* Note that some or all channels of an input may be unused: */
3481 for (i = 0; i < so->inputs_count; i++) {
3482 unsigned j, reg = regid(63,0);
3483 bool half = false;
3484 for (j = 0; j < 4; j++) {
3485 struct ir3_instruction *in = inputs[(i*4) + j];
3486
3487 if (!in)
3488 continue;
3489
3490 if (in->flags & IR3_INSTR_UNUSED)
3491 continue;
3492
3493 reg = in->regs[0]->num - j;
3494 if (half) {
3495 compile_assert(ctx, in->regs[0]->flags & IR3_REG_HALF);
3496 } else {
3497 half = !!(in->regs[0]->flags & IR3_REG_HALF);
3498 }
3499 }
3500 so->inputs[i].regid = reg;
3501 so->inputs[i].half = half;
3502 }
3503
3504 if (ctx->astc_srgb)
3505 fixup_astc_srgb(ctx);
3506
3507 /* We need to do legalize after (for frag shader's) the "bary.f"
3508 * offsets (inloc) have been assigned.
3509 */
3510 ir3_legalize(ir, &so->has_ssbo, &so->need_pixlod, &max_bary);
3511
3512 if (ir3_shader_debug & IR3_DBG_OPTMSGS) {
3513 printf("AFTER LEGALIZE:\n");
3514 ir3_print(ir);
3515 }
3516
3517 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3518 * know what we might have to wait on when coming in from VS chsh.
3519 */
3520 if (so->type == MESA_SHADER_TESS_CTRL ||
3521 so->type == MESA_SHADER_GEOMETRY ) {
3522 list_for_each_entry (struct ir3_block, block, &ir->block_list, node) {
3523 list_for_each_entry (struct ir3_instruction, instr, &block->instr_list, node) {
3524 instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
3525 break;
3526 }
3527 }
3528 }
3529
3530 so->branchstack = ctx->max_stack;
3531
3532 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3533 if (so->type == MESA_SHADER_FRAGMENT)
3534 so->total_in = max_bary + 1;
3535
3536 so->max_sun = ir->max_sun;
3537
3538 /* Collect sampling instructions eligible for pre-dispatch. */
3539 collect_tex_prefetches(ctx, ir);
3540
3541 out:
3542 if (ret) {
3543 if (so->ir)
3544 ir3_destroy(so->ir);
3545 so->ir = NULL;
3546 }
3547 ir3_context_free(ctx);
3548
3549 return ret;
3550 }