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freedreno: Fix non-constbuf-upload UBO block indices and count.
[mesa.git] / src / freedreno / ir3 / ir3_compiler_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27 #include <stdarg.h>
28
29 #include "util/u_string.h"
30 #include "util/u_memory.h"
31 #include "util/u_math.h"
32
33 #include "ir3_compiler.h"
34 #include "ir3_image.h"
35 #include "ir3_shader.h"
36 #include "ir3_nir.h"
37
38 #include "instr-a3xx.h"
39 #include "ir3.h"
40 #include "ir3_context.h"
41
42
43 static struct ir3_instruction *
44 create_indirect_load(struct ir3_context *ctx, unsigned arrsz, int n,
45 struct ir3_instruction *address, struct ir3_instruction *collect)
46 {
47 struct ir3_block *block = ctx->block;
48 struct ir3_instruction *mov;
49 struct ir3_register *src;
50
51 mov = ir3_instr_create(block, OPC_MOV);
52 mov->cat1.src_type = TYPE_U32;
53 mov->cat1.dst_type = TYPE_U32;
54 __ssa_dst(mov);
55 src = __ssa_src(mov, collect, IR3_REG_RELATIV);
56 src->size = arrsz;
57 src->array.offset = n;
58
59 ir3_instr_set_address(mov, address);
60
61 return mov;
62 }
63
64 static struct ir3_instruction *
65 create_input(struct ir3_context *ctx, unsigned compmask)
66 {
67 struct ir3_instruction *in;
68
69 in = ir3_instr_create(ctx->in_block, OPC_META_INPUT);
70 in->input.sysval = ~0;
71 __ssa_dst(in)->wrmask = compmask;
72
73 array_insert(ctx->ir, ctx->ir->inputs, in);
74
75 return in;
76 }
77
78 static struct ir3_instruction *
79 create_frag_input(struct ir3_context *ctx, bool use_ldlv, unsigned n)
80 {
81 struct ir3_block *block = ctx->block;
82 struct ir3_instruction *instr;
83 /* packed inloc is fixed up later: */
84 struct ir3_instruction *inloc = create_immed(block, n);
85
86 if (use_ldlv) {
87 instr = ir3_LDLV(block, inloc, 0, create_immed(block, 1), 0);
88 instr->cat6.type = TYPE_U32;
89 instr->cat6.iim_val = 1;
90 } else {
91 instr = ir3_BARY_F(block, inloc, 0, ctx->ij_pixel, 0);
92 instr->regs[2]->wrmask = 0x3;
93 }
94
95 return instr;
96 }
97
98 static struct ir3_instruction *
99 create_driver_param(struct ir3_context *ctx, enum ir3_driver_param dp)
100 {
101 /* first four vec4 sysval's reserved for UBOs: */
102 /* NOTE: dp is in scalar, but there can be >4 dp components: */
103 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
104 unsigned n = const_state->offsets.driver_param;
105 unsigned r = regid(n + dp / 4, dp % 4);
106 return create_uniform(ctx->block, r);
107 }
108
109 /*
110 * Adreno's comparisons produce a 1 for true and 0 for false, in either 16 or
111 * 32-bit registers. We use NIR's 1-bit integers to represent bools, and
112 * trust that we will only see and/or/xor on those 1-bit values, so we can
113 * safely store NIR i1s in a 32-bit reg while always containing either a 1 or
114 * 0.
115 */
116
117 /*
118 * alu/sfu instructions:
119 */
120
121 static struct ir3_instruction *
122 create_cov(struct ir3_context *ctx, struct ir3_instruction *src,
123 unsigned src_bitsize, nir_op op)
124 {
125 type_t src_type, dst_type;
126
127 switch (op) {
128 case nir_op_f2f32:
129 case nir_op_f2f16_rtne:
130 case nir_op_f2f16_rtz:
131 case nir_op_f2f16:
132 case nir_op_f2i32:
133 case nir_op_f2i16:
134 case nir_op_f2i8:
135 case nir_op_f2u32:
136 case nir_op_f2u16:
137 case nir_op_f2u8:
138 switch (src_bitsize) {
139 case 32:
140 src_type = TYPE_F32;
141 break;
142 case 16:
143 src_type = TYPE_F16;
144 break;
145 default:
146 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
147 }
148 break;
149
150 case nir_op_i2f32:
151 case nir_op_i2f16:
152 case nir_op_i2i32:
153 case nir_op_i2i16:
154 case nir_op_i2i8:
155 switch (src_bitsize) {
156 case 32:
157 src_type = TYPE_S32;
158 break;
159 case 16:
160 src_type = TYPE_S16;
161 break;
162 case 8:
163 src_type = TYPE_S8;
164 break;
165 default:
166 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
167 }
168 break;
169
170 case nir_op_u2f32:
171 case nir_op_u2f16:
172 case nir_op_u2u32:
173 case nir_op_u2u16:
174 case nir_op_u2u8:
175 switch (src_bitsize) {
176 case 32:
177 src_type = TYPE_U32;
178 break;
179 case 16:
180 src_type = TYPE_U16;
181 break;
182 case 8:
183 src_type = TYPE_U8;
184 break;
185 default:
186 ir3_context_error(ctx, "invalid src bit size: %u", src_bitsize);
187 }
188 break;
189
190 case nir_op_b2f16:
191 case nir_op_b2f32:
192 case nir_op_b2i8:
193 case nir_op_b2i16:
194 case nir_op_b2i32:
195 src_type = TYPE_U32;
196 break;
197
198 default:
199 ir3_context_error(ctx, "invalid conversion op: %u", op);
200 }
201
202 switch (op) {
203 case nir_op_f2f32:
204 case nir_op_i2f32:
205 case nir_op_u2f32:
206 case nir_op_b2f32:
207 dst_type = TYPE_F32;
208 break;
209
210 case nir_op_f2f16_rtne:
211 case nir_op_f2f16_rtz:
212 case nir_op_f2f16:
213 case nir_op_i2f16:
214 case nir_op_u2f16:
215 case nir_op_b2f16:
216 dst_type = TYPE_F16;
217 break;
218
219 case nir_op_f2i32:
220 case nir_op_i2i32:
221 case nir_op_b2i32:
222 dst_type = TYPE_S32;
223 break;
224
225 case nir_op_f2i16:
226 case nir_op_i2i16:
227 case nir_op_b2i16:
228 dst_type = TYPE_S16;
229 break;
230
231 case nir_op_f2i8:
232 case nir_op_i2i8:
233 case nir_op_b2i8:
234 dst_type = TYPE_S8;
235 break;
236
237 case nir_op_f2u32:
238 case nir_op_u2u32:
239 dst_type = TYPE_U32;
240 break;
241
242 case nir_op_f2u16:
243 case nir_op_u2u16:
244 dst_type = TYPE_U16;
245 break;
246
247 case nir_op_f2u8:
248 case nir_op_u2u8:
249 dst_type = TYPE_U8;
250 break;
251
252 default:
253 ir3_context_error(ctx, "invalid conversion op: %u", op);
254 }
255
256 if (src_type == dst_type)
257 return src;
258
259 struct ir3_instruction *cov =
260 ir3_COV(ctx->block, src, src_type, dst_type);
261
262 if (op == nir_op_f2f16_rtne)
263 cov->regs[0]->flags |= IR3_REG_EVEN;
264
265 return cov;
266 }
267
268 static void
269 emit_alu(struct ir3_context *ctx, nir_alu_instr *alu)
270 {
271 const nir_op_info *info = &nir_op_infos[alu->op];
272 struct ir3_instruction **dst, *src[info->num_inputs];
273 unsigned bs[info->num_inputs]; /* bit size */
274 struct ir3_block *b = ctx->block;
275 unsigned dst_sz, wrmask;
276 type_t dst_type = nir_dest_bit_size(alu->dest.dest) == 16 ?
277 TYPE_U16 : TYPE_U32;
278
279 if (alu->dest.dest.is_ssa) {
280 dst_sz = alu->dest.dest.ssa.num_components;
281 wrmask = (1 << dst_sz) - 1;
282 } else {
283 dst_sz = alu->dest.dest.reg.reg->num_components;
284 wrmask = alu->dest.write_mask;
285 }
286
287 dst = ir3_get_dst(ctx, &alu->dest.dest, dst_sz);
288
289 /* Vectors are special in that they have non-scalarized writemasks,
290 * and just take the first swizzle channel for each argument in
291 * order into each writemask channel.
292 */
293 if ((alu->op == nir_op_vec2) ||
294 (alu->op == nir_op_vec3) ||
295 (alu->op == nir_op_vec4)) {
296
297 for (int i = 0; i < info->num_inputs; i++) {
298 nir_alu_src *asrc = &alu->src[i];
299
300 compile_assert(ctx, !asrc->abs);
301 compile_assert(ctx, !asrc->negate);
302
303 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[0]];
304 if (!src[i])
305 src[i] = create_immed_typed(ctx->block, 0, dst_type);
306 dst[i] = ir3_MOV(b, src[i], dst_type);
307 }
308
309 ir3_put_dst(ctx, &alu->dest.dest);
310 return;
311 }
312
313 /* We also get mov's with more than one component for mov's so
314 * handle those specially:
315 */
316 if (alu->op == nir_op_mov) {
317 nir_alu_src *asrc = &alu->src[0];
318 struct ir3_instruction *const *src0 = ir3_get_src(ctx, &asrc->src);
319
320 for (unsigned i = 0; i < dst_sz; i++) {
321 if (wrmask & (1 << i)) {
322 dst[i] = ir3_MOV(b, src0[asrc->swizzle[i]], dst_type);
323 } else {
324 dst[i] = NULL;
325 }
326 }
327
328 ir3_put_dst(ctx, &alu->dest.dest);
329 return;
330 }
331
332 /* General case: We can just grab the one used channel per src. */
333 for (int i = 0; i < info->num_inputs; i++) {
334 unsigned chan = ffs(alu->dest.write_mask) - 1;
335 nir_alu_src *asrc = &alu->src[i];
336
337 compile_assert(ctx, !asrc->abs);
338 compile_assert(ctx, !asrc->negate);
339
340 src[i] = ir3_get_src(ctx, &asrc->src)[asrc->swizzle[chan]];
341 bs[i] = nir_src_bit_size(asrc->src);
342
343 compile_assert(ctx, src[i]);
344 }
345
346 switch (alu->op) {
347 case nir_op_f2f32:
348 case nir_op_f2f16_rtne:
349 case nir_op_f2f16_rtz:
350 case nir_op_f2f16:
351 case nir_op_f2i32:
352 case nir_op_f2i16:
353 case nir_op_f2i8:
354 case nir_op_f2u32:
355 case nir_op_f2u16:
356 case nir_op_f2u8:
357 case nir_op_i2f32:
358 case nir_op_i2f16:
359 case nir_op_i2i32:
360 case nir_op_i2i16:
361 case nir_op_i2i8:
362 case nir_op_u2f32:
363 case nir_op_u2f16:
364 case nir_op_u2u32:
365 case nir_op_u2u16:
366 case nir_op_u2u8:
367 case nir_op_b2f16:
368 case nir_op_b2f32:
369 case nir_op_b2i8:
370 case nir_op_b2i16:
371 case nir_op_b2i32:
372 dst[0] = create_cov(ctx, src[0], bs[0], alu->op);
373 break;
374
375 case nir_op_fquantize2f16:
376 dst[0] = create_cov(ctx,
377 create_cov(ctx, src[0], 32, nir_op_f2f16),
378 16, nir_op_f2f32);
379 break;
380 case nir_op_f2b1:
381 dst[0] = ir3_CMPS_F(b,
382 src[0], 0,
383 create_immed_typed(b, 0, bs[0] == 16 ? TYPE_F16 : TYPE_F32), 0);
384 dst[0]->cat2.condition = IR3_COND_NE;
385 break;
386
387 case nir_op_i2b1:
388 /* i2b1 will appear when translating from nir_load_ubo or
389 * nir_intrinsic_load_ssbo, where any non-zero value is true.
390 */
391 dst[0] = ir3_CMPS_S(b, src[0], 0, create_immed(b, 0), 0);
392 dst[0]->cat2.condition = IR3_COND_NE;
393 break;
394
395 case nir_op_b2b1:
396 /* b2b1 will appear when translating from
397 *
398 * - nir_intrinsic_load_shared of a 32-bit 0/~0 value.
399 * - nir_intrinsic_load_constant of a 32-bit 0/~0 value
400 *
401 * A negate can turn those into a 1 or 0 for us.
402 */
403 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
404 break;
405
406 case nir_op_b2b32:
407 /* b2b32 will appear when converting our 1-bit bools to a store_shared
408 * argument.
409 *
410 * A negate can turn those into a ~0 for us.
411 */
412 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
413 break;
414
415 case nir_op_fneg:
416 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FNEG);
417 break;
418 case nir_op_fabs:
419 dst[0] = ir3_ABSNEG_F(b, src[0], IR3_REG_FABS);
420 break;
421 case nir_op_fmax:
422 dst[0] = ir3_MAX_F(b, src[0], 0, src[1], 0);
423 break;
424 case nir_op_fmin:
425 dst[0] = ir3_MIN_F(b, src[0], 0, src[1], 0);
426 break;
427 case nir_op_fsat:
428 /* if there is just a single use of the src, and it supports
429 * (sat) bit, we can just fold the (sat) flag back to the
430 * src instruction and create a mov. This is easier for cp
431 * to eliminate.
432 *
433 * TODO probably opc_cat==4 is ok too
434 */
435 if (alu->src[0].src.is_ssa &&
436 (list_length(&alu->src[0].src.ssa->uses) == 1) &&
437 ((opc_cat(src[0]->opc) == 2) || (opc_cat(src[0]->opc) == 3))) {
438 src[0]->flags |= IR3_INSTR_SAT;
439 dst[0] = ir3_MOV(b, src[0], dst_type);
440 } else {
441 /* otherwise generate a max.f that saturates.. blob does
442 * similar (generating a cat2 mov using max.f)
443 */
444 dst[0] = ir3_MAX_F(b, src[0], 0, src[0], 0);
445 dst[0]->flags |= IR3_INSTR_SAT;
446 }
447 break;
448 case nir_op_fmul:
449 dst[0] = ir3_MUL_F(b, src[0], 0, src[1], 0);
450 break;
451 case nir_op_fadd:
452 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], 0);
453 break;
454 case nir_op_fsub:
455 dst[0] = ir3_ADD_F(b, src[0], 0, src[1], IR3_REG_FNEG);
456 break;
457 case nir_op_ffma:
458 dst[0] = ir3_MAD_F32(b, src[0], 0, src[1], 0, src[2], 0);
459 break;
460 case nir_op_fddx:
461 case nir_op_fddx_coarse:
462 dst[0] = ir3_DSX(b, src[0], 0);
463 dst[0]->cat5.type = TYPE_F32;
464 break;
465 case nir_op_fddx_fine:
466 dst[0] = ir3_DSXPP_1(b, src[0], 0);
467 dst[0]->cat5.type = TYPE_F32;
468 break;
469 case nir_op_fddy:
470 case nir_op_fddy_coarse:
471 dst[0] = ir3_DSY(b, src[0], 0);
472 dst[0]->cat5.type = TYPE_F32;
473 break;
474 break;
475 case nir_op_fddy_fine:
476 dst[0] = ir3_DSYPP_1(b, src[0], 0);
477 dst[0]->cat5.type = TYPE_F32;
478 break;
479 case nir_op_flt:
480 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
481 dst[0]->cat2.condition = IR3_COND_LT;
482 break;
483 case nir_op_fge:
484 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
485 dst[0]->cat2.condition = IR3_COND_GE;
486 break;
487 case nir_op_feq:
488 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
489 dst[0]->cat2.condition = IR3_COND_EQ;
490 break;
491 case nir_op_fne:
492 dst[0] = ir3_CMPS_F(b, src[0], 0, src[1], 0);
493 dst[0]->cat2.condition = IR3_COND_NE;
494 break;
495 case nir_op_fceil:
496 dst[0] = ir3_CEIL_F(b, src[0], 0);
497 break;
498 case nir_op_ffloor:
499 dst[0] = ir3_FLOOR_F(b, src[0], 0);
500 break;
501 case nir_op_ftrunc:
502 dst[0] = ir3_TRUNC_F(b, src[0], 0);
503 break;
504 case nir_op_fround_even:
505 dst[0] = ir3_RNDNE_F(b, src[0], 0);
506 break;
507 case nir_op_fsign:
508 dst[0] = ir3_SIGN_F(b, src[0], 0);
509 break;
510
511 case nir_op_fsin:
512 dst[0] = ir3_SIN(b, src[0], 0);
513 break;
514 case nir_op_fcos:
515 dst[0] = ir3_COS(b, src[0], 0);
516 break;
517 case nir_op_frsq:
518 dst[0] = ir3_RSQ(b, src[0], 0);
519 break;
520 case nir_op_frcp:
521 dst[0] = ir3_RCP(b, src[0], 0);
522 break;
523 case nir_op_flog2:
524 dst[0] = ir3_LOG2(b, src[0], 0);
525 break;
526 case nir_op_fexp2:
527 dst[0] = ir3_EXP2(b, src[0], 0);
528 break;
529 case nir_op_fsqrt:
530 dst[0] = ir3_SQRT(b, src[0], 0);
531 break;
532
533 case nir_op_iabs:
534 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SABS);
535 break;
536 case nir_op_iadd:
537 dst[0] = ir3_ADD_U(b, src[0], 0, src[1], 0);
538 break;
539 case nir_op_iand:
540 dst[0] = ir3_AND_B(b, src[0], 0, src[1], 0);
541 break;
542 case nir_op_imax:
543 dst[0] = ir3_MAX_S(b, src[0], 0, src[1], 0);
544 break;
545 case nir_op_umax:
546 dst[0] = ir3_MAX_U(b, src[0], 0, src[1], 0);
547 break;
548 case nir_op_imin:
549 dst[0] = ir3_MIN_S(b, src[0], 0, src[1], 0);
550 break;
551 case nir_op_umin:
552 dst[0] = ir3_MIN_U(b, src[0], 0, src[1], 0);
553 break;
554 case nir_op_umul_low:
555 dst[0] = ir3_MULL_U(b, src[0], 0, src[1], 0);
556 break;
557 case nir_op_imadsh_mix16:
558 dst[0] = ir3_MADSH_M16(b, src[0], 0, src[1], 0, src[2], 0);
559 break;
560 case nir_op_imad24_ir3:
561 dst[0] = ir3_MAD_S24(b, src[0], 0, src[1], 0, src[2], 0);
562 break;
563 case nir_op_imul24:
564 dst[0] = ir3_MUL_S24(b, src[0], 0, src[1], 0);
565 break;
566 case nir_op_ineg:
567 dst[0] = ir3_ABSNEG_S(b, src[0], IR3_REG_SNEG);
568 break;
569 case nir_op_inot:
570 if (bs[0] == 1) {
571 dst[0] = ir3_SUB_U(b, create_immed(ctx->block, 1), 0, src[0], 0);
572 } else {
573 dst[0] = ir3_NOT_B(b, src[0], 0);
574 }
575 break;
576 case nir_op_ior:
577 dst[0] = ir3_OR_B(b, src[0], 0, src[1], 0);
578 break;
579 case nir_op_ishl:
580 dst[0] = ir3_SHL_B(b, src[0], 0, src[1], 0);
581 break;
582 case nir_op_ishr:
583 dst[0] = ir3_ASHR_B(b, src[0], 0, src[1], 0);
584 break;
585 case nir_op_isub:
586 dst[0] = ir3_SUB_U(b, src[0], 0, src[1], 0);
587 break;
588 case nir_op_ixor:
589 dst[0] = ir3_XOR_B(b, src[0], 0, src[1], 0);
590 break;
591 case nir_op_ushr:
592 dst[0] = ir3_SHR_B(b, src[0], 0, src[1], 0);
593 break;
594 case nir_op_ilt:
595 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
596 dst[0]->cat2.condition = IR3_COND_LT;
597 break;
598 case nir_op_ige:
599 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
600 dst[0]->cat2.condition = IR3_COND_GE;
601 break;
602 case nir_op_ieq:
603 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
604 dst[0]->cat2.condition = IR3_COND_EQ;
605 break;
606 case nir_op_ine:
607 dst[0] = ir3_CMPS_S(b, src[0], 0, src[1], 0);
608 dst[0]->cat2.condition = IR3_COND_NE;
609 break;
610 case nir_op_ult:
611 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
612 dst[0]->cat2.condition = IR3_COND_LT;
613 break;
614 case nir_op_uge:
615 dst[0] = ir3_CMPS_U(b, src[0], 0, src[1], 0);
616 dst[0]->cat2.condition = IR3_COND_GE;
617 break;
618
619 case nir_op_bcsel: {
620 struct ir3_instruction *cond = src[0];
621
622 /* If src[0] is a negation (likely as a result of an ir3_b2n(cond)),
623 * we can ignore that and use original cond, since the nonzero-ness of
624 * cond stays the same.
625 */
626 if (cond->opc == OPC_ABSNEG_S &&
627 cond->flags == 0 &&
628 (cond->regs[1]->flags & (IR3_REG_SNEG | IR3_REG_SABS)) == IR3_REG_SNEG) {
629 cond = cond->regs[1]->instr;
630 }
631
632 compile_assert(ctx, bs[1] == bs[2]);
633 /* The condition's size has to match the other two arguments' size, so
634 * convert down if necessary.
635 */
636 if (bs[1] == 16) {
637 struct hash_entry *prev_entry =
638 _mesa_hash_table_search(ctx->sel_cond_conversions, src[0]);
639 if (prev_entry) {
640 cond = prev_entry->data;
641 } else {
642 cond = ir3_COV(b, cond, TYPE_U32, TYPE_U16);
643 _mesa_hash_table_insert(ctx->sel_cond_conversions, src[0], cond);
644 }
645 }
646
647 if (bs[1] != 16)
648 dst[0] = ir3_SEL_B32(b, src[1], 0, cond, 0, src[2], 0);
649 else
650 dst[0] = ir3_SEL_B16(b, src[1], 0, cond, 0, src[2], 0);
651 break;
652 }
653 case nir_op_bit_count: {
654 // TODO, we need to do this 16b at a time on a5xx+a6xx.. need to
655 // double check on earlier gen's. Once half-precision support is
656 // in place, this should probably move to a NIR lowering pass:
657 struct ir3_instruction *hi, *lo;
658
659 hi = ir3_COV(b, ir3_SHR_B(b, src[0], 0, create_immed(b, 16), 0),
660 TYPE_U32, TYPE_U16);
661 lo = ir3_COV(b, src[0], TYPE_U32, TYPE_U16);
662
663 hi = ir3_CBITS_B(b, hi, 0);
664 lo = ir3_CBITS_B(b, lo, 0);
665
666 // TODO maybe the builders should default to making dst half-precision
667 // if the src's were half precision, to make this less awkward.. otoh
668 // we should probably just do this lowering in NIR.
669 hi->regs[0]->flags |= IR3_REG_HALF;
670 lo->regs[0]->flags |= IR3_REG_HALF;
671
672 dst[0] = ir3_ADD_S(b, hi, 0, lo, 0);
673 dst[0]->regs[0]->flags |= IR3_REG_HALF;
674 dst[0] = ir3_COV(b, dst[0], TYPE_U16, TYPE_U32);
675 break;
676 }
677 case nir_op_ifind_msb: {
678 struct ir3_instruction *cmp;
679 dst[0] = ir3_CLZ_S(b, src[0], 0);
680 cmp = ir3_CMPS_S(b, dst[0], 0, create_immed(b, 0), 0);
681 cmp->cat2.condition = IR3_COND_GE;
682 dst[0] = ir3_SEL_B32(b,
683 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
684 cmp, 0, dst[0], 0);
685 break;
686 }
687 case nir_op_ufind_msb:
688 dst[0] = ir3_CLZ_B(b, src[0], 0);
689 dst[0] = ir3_SEL_B32(b,
690 ir3_SUB_U(b, create_immed(b, 31), 0, dst[0], 0), 0,
691 src[0], 0, dst[0], 0);
692 break;
693 case nir_op_find_lsb:
694 dst[0] = ir3_BFREV_B(b, src[0], 0);
695 dst[0] = ir3_CLZ_B(b, dst[0], 0);
696 break;
697 case nir_op_bitfield_reverse:
698 dst[0] = ir3_BFREV_B(b, src[0], 0);
699 break;
700
701 default:
702 ir3_context_error(ctx, "Unhandled ALU op: %s\n",
703 nir_op_infos[alu->op].name);
704 break;
705 }
706
707 if (nir_alu_type_get_base_type(info->output_type) == nir_type_bool) {
708 assert(nir_dest_bit_size(alu->dest.dest) == 1 ||
709 alu->op == nir_op_b2b32);
710 assert(dst_sz == 1);
711 } else {
712 /* 1-bit values stored in 32-bit registers are only valid for certain
713 * ALU ops.
714 */
715 switch (alu->op) {
716 case nir_op_iand:
717 case nir_op_ior:
718 case nir_op_ixor:
719 case nir_op_inot:
720 case nir_op_bcsel:
721 break;
722 default:
723 compile_assert(ctx, nir_dest_bit_size(alu->dest.dest) != 1);
724 }
725 }
726
727 ir3_put_dst(ctx, &alu->dest.dest);
728 }
729
730 static void
731 emit_intrinsic_load_ubo_ldc(struct ir3_context *ctx, nir_intrinsic_instr *intr,
732 struct ir3_instruction **dst)
733 {
734 struct ir3_block *b = ctx->block;
735
736 unsigned ncomp = intr->num_components;
737 struct ir3_instruction *offset = ir3_get_src(ctx, &intr->src[1])[0];
738 struct ir3_instruction *idx = ir3_get_src(ctx, &intr->src[0])[0];
739 struct ir3_instruction *ldc = ir3_LDC(b, idx, 0, offset, 0);
740 ldc->regs[0]->wrmask = MASK(ncomp);
741 ldc->cat6.iim_val = ncomp;
742 ldc->cat6.d = nir_intrinsic_base(intr);
743 ldc->cat6.type = TYPE_U32;
744
745 nir_intrinsic_instr *bindless = ir3_bindless_resource(intr->src[0]);
746 if (bindless) {
747 ldc->flags |= IR3_INSTR_B;
748 ldc->cat6.base = nir_intrinsic_desc_set(bindless);
749 ctx->so->bindless_ubo = true;
750 }
751
752 ir3_split_dest(b, dst, ldc, 0, ncomp);
753 }
754
755
756 /* handles direct/indirect UBO reads: */
757 static void
758 emit_intrinsic_load_ubo(struct ir3_context *ctx, nir_intrinsic_instr *intr,
759 struct ir3_instruction **dst)
760 {
761 struct ir3_block *b = ctx->block;
762 struct ir3_instruction *base_lo, *base_hi, *addr, *src0, *src1;
763 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
764 unsigned ubo = regid(const_state->offsets.ubo, 0);
765 const unsigned ptrsz = ir3_pointer_size(ctx->compiler);
766
767 int off = 0;
768
769 /* First src is ubo index, which could either be an immed or not: */
770 src0 = ir3_get_src(ctx, &intr->src[0])[0];
771 if (is_same_type_mov(src0) &&
772 (src0->regs[1]->flags & IR3_REG_IMMED)) {
773 base_lo = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz));
774 base_hi = create_uniform(b, ubo + (src0->regs[1]->iim_val * ptrsz) + 1);
775 } else {
776 base_lo = create_uniform_indirect(b, ubo, ir3_get_addr0(ctx, src0, ptrsz));
777 base_hi = create_uniform_indirect(b, ubo + 1, ir3_get_addr0(ctx, src0, ptrsz));
778
779 /* NOTE: since relative addressing is used, make sure constlen is
780 * at least big enough to cover all the UBO addresses, since the
781 * assembler won't know what the max address reg is.
782 */
783 ctx->so->constlen = MAX2(ctx->so->constlen,
784 const_state->offsets.ubo + (ctx->s->info.num_ubos * ptrsz));
785 }
786
787 /* note: on 32bit gpu's base_hi is ignored and DCE'd */
788 addr = base_lo;
789
790 if (nir_src_is_const(intr->src[1])) {
791 off += nir_src_as_uint(intr->src[1]);
792 } else {
793 /* For load_ubo_indirect, second src is indirect offset: */
794 src1 = ir3_get_src(ctx, &intr->src[1])[0];
795
796 /* and add offset to addr: */
797 addr = ir3_ADD_S(b, addr, 0, src1, 0);
798 }
799
800 /* if offset is to large to encode in the ldg, split it out: */
801 if ((off + (intr->num_components * 4)) > 1024) {
802 /* split out the minimal amount to improve the odds that
803 * cp can fit the immediate in the add.s instruction:
804 */
805 unsigned off2 = off + (intr->num_components * 4) - 1024;
806 addr = ir3_ADD_S(b, addr, 0, create_immed(b, off2), 0);
807 off -= off2;
808 }
809
810 if (ptrsz == 2) {
811 struct ir3_instruction *carry;
812
813 /* handle 32b rollover, ie:
814 * if (addr < base_lo)
815 * base_hi++
816 */
817 carry = ir3_CMPS_U(b, addr, 0, base_lo, 0);
818 carry->cat2.condition = IR3_COND_LT;
819 base_hi = ir3_ADD_S(b, base_hi, 0, carry, 0);
820
821 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){ addr, base_hi }, 2);
822 }
823
824 for (int i = 0; i < intr->num_components; i++) {
825 struct ir3_instruction *load =
826 ir3_LDG(b, addr, 0, create_immed(b, 1), 0, /* num components */
827 create_immed(b, off + i * 4), 0);
828 load->cat6.type = TYPE_U32;
829 dst[i] = load;
830 }
831 }
832
833 /* src[] = { block_index } */
834 static void
835 emit_intrinsic_ssbo_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
836 struct ir3_instruction **dst)
837 {
838 /* SSBO size stored as a const starting at ssbo_sizes: */
839 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
840 unsigned blk_idx = nir_src_as_uint(intr->src[0]);
841 unsigned idx = regid(const_state->offsets.ssbo_sizes, 0) +
842 const_state->ssbo_size.off[blk_idx];
843
844 debug_assert(const_state->ssbo_size.mask & (1 << blk_idx));
845
846 dst[0] = create_uniform(ctx->block, idx);
847 }
848
849 /* src[] = { offset }. const_index[] = { base } */
850 static void
851 emit_intrinsic_load_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr,
852 struct ir3_instruction **dst)
853 {
854 struct ir3_block *b = ctx->block;
855 struct ir3_instruction *ldl, *offset;
856 unsigned base;
857
858 offset = ir3_get_src(ctx, &intr->src[0])[0];
859 base = nir_intrinsic_base(intr);
860
861 ldl = ir3_LDL(b, offset, 0,
862 create_immed(b, intr->num_components), 0,
863 create_immed(b, base), 0);
864
865 ldl->cat6.type = utype_dst(intr->dest);
866 ldl->regs[0]->wrmask = MASK(intr->num_components);
867
868 ldl->barrier_class = IR3_BARRIER_SHARED_R;
869 ldl->barrier_conflict = IR3_BARRIER_SHARED_W;
870
871 ir3_split_dest(b, dst, ldl, 0, intr->num_components);
872 }
873
874 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
875 static void
876 emit_intrinsic_store_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
877 {
878 struct ir3_block *b = ctx->block;
879 struct ir3_instruction *stl, *offset;
880 struct ir3_instruction * const *value;
881 unsigned base, wrmask;
882
883 value = ir3_get_src(ctx, &intr->src[0]);
884 offset = ir3_get_src(ctx, &intr->src[1])[0];
885
886 base = nir_intrinsic_base(intr);
887 wrmask = nir_intrinsic_write_mask(intr);
888
889 /* Combine groups of consecutive enabled channels in one write
890 * message. We use ffs to find the first enabled channel and then ffs on
891 * the bit-inverse, down-shifted writemask to determine the length of
892 * the block of enabled bits.
893 *
894 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
895 */
896 while (wrmask) {
897 unsigned first_component = ffs(wrmask) - 1;
898 unsigned length = ffs(~(wrmask >> first_component)) - 1;
899
900 stl = ir3_STL(b, offset, 0,
901 ir3_create_collect(ctx, &value[first_component], length), 0,
902 create_immed(b, length), 0);
903 stl->cat6.dst_offset = first_component + base;
904 stl->cat6.type = utype_src(intr->src[0]);
905 stl->barrier_class = IR3_BARRIER_SHARED_W;
906 stl->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
907
908 array_insert(b, b->keeps, stl);
909
910 /* Clear the bits in the writemask that we just wrote, then try
911 * again to see if more channels are left.
912 */
913 wrmask &= (15 << (first_component + length));
914 }
915 }
916
917 /* src[] = { offset }. const_index[] = { base } */
918 static void
919 emit_intrinsic_load_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr,
920 struct ir3_instruction **dst)
921 {
922 struct ir3_block *b = ctx->block;
923 struct ir3_instruction *load, *offset;
924 unsigned base;
925
926 offset = ir3_get_src(ctx, &intr->src[0])[0];
927 base = nir_intrinsic_base(intr);
928
929 load = ir3_LDLW(b, offset, 0,
930 create_immed(b, intr->num_components), 0,
931 create_immed(b, base), 0);
932
933 load->cat6.type = utype_dst(intr->dest);
934 load->regs[0]->wrmask = MASK(intr->num_components);
935
936 load->barrier_class = IR3_BARRIER_SHARED_R;
937 load->barrier_conflict = IR3_BARRIER_SHARED_W;
938
939 ir3_split_dest(b, dst, load, 0, intr->num_components);
940 }
941
942 /* src[] = { value, offset }. const_index[] = { base, write_mask } */
943 static void
944 emit_intrinsic_store_shared_ir3(struct ir3_context *ctx, nir_intrinsic_instr *intr)
945 {
946 struct ir3_block *b = ctx->block;
947 struct ir3_instruction *store, *offset;
948 struct ir3_instruction * const *value;
949 unsigned base, wrmask;
950
951 value = ir3_get_src(ctx, &intr->src[0]);
952 offset = ir3_get_src(ctx, &intr->src[1])[0];
953
954 base = nir_intrinsic_base(intr);
955 wrmask = nir_intrinsic_write_mask(intr);
956
957 /* Combine groups of consecutive enabled channels in one write
958 * message. We use ffs to find the first enabled channel and then ffs on
959 * the bit-inverse, down-shifted writemask to determine the length of
960 * the block of enabled bits.
961 *
962 * (trick stolen from i965's fs_visitor::nir_emit_cs_intrinsic())
963 */
964 while (wrmask) {
965 unsigned first_component = ffs(wrmask) - 1;
966 unsigned length = ffs(~(wrmask >> first_component)) - 1;
967
968 store = ir3_STLW(b, offset, 0,
969 ir3_create_collect(ctx, &value[first_component], length), 0,
970 create_immed(b, length), 0);
971
972 store->cat6.dst_offset = first_component + base;
973 store->cat6.type = utype_src(intr->src[0]);
974 store->barrier_class = IR3_BARRIER_SHARED_W;
975 store->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
976
977 array_insert(b, b->keeps, store);
978
979 /* Clear the bits in the writemask that we just wrote, then try
980 * again to see if more channels are left.
981 */
982 wrmask &= (15 << (first_component + length));
983 }
984 }
985
986 /*
987 * CS shared variable atomic intrinsics
988 *
989 * All of the shared variable atomic memory operations read a value from
990 * memory, compute a new value using one of the operations below, write the
991 * new value to memory, and return the original value read.
992 *
993 * All operations take 2 sources except CompSwap that takes 3. These
994 * sources represent:
995 *
996 * 0: The offset into the shared variable storage region that the atomic
997 * operation will operate on.
998 * 1: The data parameter to the atomic function (i.e. the value to add
999 * in shared_atomic_add, etc).
1000 * 2: For CompSwap only: the second data parameter.
1001 */
1002 static struct ir3_instruction *
1003 emit_intrinsic_atomic_shared(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1004 {
1005 struct ir3_block *b = ctx->block;
1006 struct ir3_instruction *atomic, *src0, *src1;
1007 type_t type = TYPE_U32;
1008
1009 src0 = ir3_get_src(ctx, &intr->src[0])[0]; /* offset */
1010 src1 = ir3_get_src(ctx, &intr->src[1])[0]; /* value */
1011
1012 switch (intr->intrinsic) {
1013 case nir_intrinsic_shared_atomic_add:
1014 atomic = ir3_ATOMIC_ADD(b, src0, 0, src1, 0);
1015 break;
1016 case nir_intrinsic_shared_atomic_imin:
1017 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
1018 type = TYPE_S32;
1019 break;
1020 case nir_intrinsic_shared_atomic_umin:
1021 atomic = ir3_ATOMIC_MIN(b, src0, 0, src1, 0);
1022 break;
1023 case nir_intrinsic_shared_atomic_imax:
1024 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1025 type = TYPE_S32;
1026 break;
1027 case nir_intrinsic_shared_atomic_umax:
1028 atomic = ir3_ATOMIC_MAX(b, src0, 0, src1, 0);
1029 break;
1030 case nir_intrinsic_shared_atomic_and:
1031 atomic = ir3_ATOMIC_AND(b, src0, 0, src1, 0);
1032 break;
1033 case nir_intrinsic_shared_atomic_or:
1034 atomic = ir3_ATOMIC_OR(b, src0, 0, src1, 0);
1035 break;
1036 case nir_intrinsic_shared_atomic_xor:
1037 atomic = ir3_ATOMIC_XOR(b, src0, 0, src1, 0);
1038 break;
1039 case nir_intrinsic_shared_atomic_exchange:
1040 atomic = ir3_ATOMIC_XCHG(b, src0, 0, src1, 0);
1041 break;
1042 case nir_intrinsic_shared_atomic_comp_swap:
1043 /* for cmpxchg, src1 is [ui]vec2(data, compare): */
1044 src1 = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1045 ir3_get_src(ctx, &intr->src[2])[0],
1046 src1,
1047 }, 2);
1048 atomic = ir3_ATOMIC_CMPXCHG(b, src0, 0, src1, 0);
1049 break;
1050 default:
1051 unreachable("boo");
1052 }
1053
1054 atomic->cat6.iim_val = 1;
1055 atomic->cat6.d = 1;
1056 atomic->cat6.type = type;
1057 atomic->barrier_class = IR3_BARRIER_SHARED_W;
1058 atomic->barrier_conflict = IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W;
1059
1060 /* even if nothing consume the result, we can't DCE the instruction: */
1061 array_insert(b, b->keeps, atomic);
1062
1063 return atomic;
1064 }
1065
1066 struct tex_src_info {
1067 /* For prefetch */
1068 unsigned tex_base, samp_base, tex_idx, samp_idx;
1069 /* For normal tex instructions */
1070 unsigned base, combined_idx, a1_val, flags;
1071 struct ir3_instruction *samp_tex;
1072 };
1073
1074 /* TODO handle actual indirect/dynamic case.. which is going to be weird
1075 * to handle with the image_mapping table..
1076 */
1077 static struct tex_src_info
1078 get_image_samp_tex_src(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1079 {
1080 struct ir3_block *b = ctx->block;
1081 struct tex_src_info info = { 0 };
1082 nir_intrinsic_instr *bindless_tex = ir3_bindless_resource(intr->src[0]);
1083 ctx->so->bindless_tex = true;
1084
1085 if (bindless_tex) {
1086 /* Bindless case */
1087 info.flags |= IR3_INSTR_B;
1088
1089 /* Gather information required to determine which encoding to
1090 * choose as well as for prefetch.
1091 */
1092 info.tex_base = nir_intrinsic_desc_set(bindless_tex);
1093 bool tex_const = nir_src_is_const(bindless_tex->src[0]);
1094 if (tex_const)
1095 info.tex_idx = nir_src_as_uint(bindless_tex->src[0]);
1096 info.samp_idx = 0;
1097
1098 /* Choose encoding. */
1099 if (tex_const && info.tex_idx < 256) {
1100 if (info.tex_idx < 16) {
1101 /* Everything fits within the instruction */
1102 info.base = info.tex_base;
1103 info.combined_idx = info.samp_idx | (info.tex_idx << 4);
1104 } else {
1105 info.base = info.tex_base;
1106 info.a1_val = info.tex_idx << 3;
1107 info.combined_idx = 0;
1108 info.flags |= IR3_INSTR_A1EN;
1109 }
1110 info.samp_tex = NULL;
1111 } else {
1112 info.flags |= IR3_INSTR_S2EN;
1113 info.base = info.tex_base;
1114
1115 /* Note: the indirect source is now a vec2 instead of hvec2 */
1116 struct ir3_instruction *texture, *sampler;
1117
1118 texture = ir3_get_src(ctx, &intr->src[0])[0];
1119 sampler = create_immed(b, 0);
1120 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1121 texture,
1122 sampler,
1123 }, 2);
1124 }
1125 } else {
1126 info.flags |= IR3_INSTR_S2EN;
1127 unsigned slot = nir_src_as_uint(intr->src[0]);
1128 unsigned tex_idx = ir3_image_to_tex(&ctx->so->image_mapping, slot);
1129 struct ir3_instruction *texture, *sampler;
1130
1131 texture = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1132 sampler = create_immed_typed(ctx->block, tex_idx, TYPE_U16);
1133
1134 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1135 sampler,
1136 texture,
1137 }, 2);
1138 }
1139
1140 return info;
1141 }
1142
1143 static struct ir3_instruction *
1144 emit_sam(struct ir3_context *ctx, opc_t opc, struct tex_src_info info,
1145 type_t type, unsigned wrmask, struct ir3_instruction *src0,
1146 struct ir3_instruction *src1)
1147 {
1148 struct ir3_instruction *sam, *addr;
1149 if (info.flags & IR3_INSTR_A1EN) {
1150 addr = ir3_get_addr1(ctx, info.a1_val);
1151 }
1152 sam = ir3_SAM(ctx->block, opc, type, 0b1111, info.flags,
1153 info.samp_tex, src0, src1);
1154 if (info.flags & IR3_INSTR_A1EN) {
1155 ir3_instr_set_address(sam, addr);
1156 }
1157 if (info.flags & IR3_INSTR_B) {
1158 sam->cat5.tex_base = info.base;
1159 sam->cat5.samp = info.combined_idx;
1160 }
1161 return sam;
1162 }
1163
1164 /* src[] = { deref, coord, sample_index }. const_index[] = {} */
1165 static void
1166 emit_intrinsic_load_image(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1167 struct ir3_instruction **dst)
1168 {
1169 struct ir3_block *b = ctx->block;
1170 struct tex_src_info info = get_image_samp_tex_src(ctx, intr);
1171 struct ir3_instruction *sam;
1172 struct ir3_instruction * const *src0 = ir3_get_src(ctx, &intr->src[1]);
1173 struct ir3_instruction *coords[4];
1174 unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
1175 type_t type = ir3_get_type_for_image_intrinsic(intr);
1176
1177 /* hmm, this seems a bit odd, but it is what blob does and (at least
1178 * a5xx) just faults on bogus addresses otherwise:
1179 */
1180 if (flags & IR3_INSTR_3D) {
1181 flags &= ~IR3_INSTR_3D;
1182 flags |= IR3_INSTR_A;
1183 }
1184 info.flags |= flags;
1185
1186 for (unsigned i = 0; i < ncoords; i++)
1187 coords[i] = src0[i];
1188
1189 if (ncoords == 1)
1190 coords[ncoords++] = create_immed(b, 0);
1191
1192 sam = emit_sam(ctx, OPC_ISAM, info, type, 0b1111,
1193 ir3_create_collect(ctx, coords, ncoords), NULL);
1194
1195 sam->barrier_class = IR3_BARRIER_IMAGE_R;
1196 sam->barrier_conflict = IR3_BARRIER_IMAGE_W;
1197
1198 ir3_split_dest(b, dst, sam, 0, 4);
1199 }
1200
1201 static void
1202 emit_intrinsic_image_size(struct ir3_context *ctx, nir_intrinsic_instr *intr,
1203 struct ir3_instruction **dst)
1204 {
1205 struct ir3_block *b = ctx->block;
1206 struct tex_src_info info = get_image_samp_tex_src(ctx, intr);
1207 struct ir3_instruction *sam, *lod;
1208 unsigned flags, ncoords = ir3_get_image_coords(intr, &flags);
1209 type_t dst_type = nir_dest_bit_size(intr->dest) == 16 ?
1210 TYPE_U16 : TYPE_U32;
1211
1212 info.flags |= flags;
1213 lod = create_immed(b, 0);
1214 sam = emit_sam(ctx, OPC_GETSIZE, info, dst_type, 0b1111, lod, NULL);
1215
1216 /* Array size actually ends up in .w rather than .z. This doesn't
1217 * matter for miplevel 0, but for higher mips the value in z is
1218 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
1219 * returned, which means that we have to add 1 to it for arrays for
1220 * a3xx.
1221 *
1222 * Note use a temporary dst and then copy, since the size of the dst
1223 * array that is passed in is based on nir's understanding of the
1224 * result size, not the hardware's
1225 */
1226 struct ir3_instruction *tmp[4];
1227
1228 ir3_split_dest(b, tmp, sam, 0, 4);
1229
1230 /* get_size instruction returns size in bytes instead of texels
1231 * for imageBuffer, so we need to divide it by the pixel size
1232 * of the image format.
1233 *
1234 * TODO: This is at least true on a5xx. Check other gens.
1235 */
1236 if (nir_intrinsic_image_dim(intr) == GLSL_SAMPLER_DIM_BUF) {
1237 /* Since all the possible values the divisor can take are
1238 * power-of-two (4, 8, or 16), the division is implemented
1239 * as a shift-right.
1240 * During shader setup, the log2 of the image format's
1241 * bytes-per-pixel should have been emitted in 2nd slot of
1242 * image_dims. See ir3_shader::emit_image_dims().
1243 */
1244 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
1245 unsigned cb = regid(const_state->offsets.image_dims, 0) +
1246 const_state->image_dims.off[nir_src_as_uint(intr->src[0])];
1247 struct ir3_instruction *aux = create_uniform(b, cb + 1);
1248
1249 tmp[0] = ir3_SHR_B(b, tmp[0], 0, aux, 0);
1250 }
1251
1252 for (unsigned i = 0; i < ncoords; i++)
1253 dst[i] = tmp[i];
1254
1255 if (flags & IR3_INSTR_A) {
1256 if (ctx->compiler->levels_add_one) {
1257 dst[ncoords-1] = ir3_ADD_U(b, tmp[3], 0, create_immed(b, 1), 0);
1258 } else {
1259 dst[ncoords-1] = ir3_MOV(b, tmp[3], TYPE_U32);
1260 }
1261 }
1262 }
1263
1264 static void
1265 emit_intrinsic_barrier(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1266 {
1267 struct ir3_block *b = ctx->block;
1268 struct ir3_instruction *barrier;
1269
1270 switch (intr->intrinsic) {
1271 case nir_intrinsic_control_barrier:
1272 barrier = ir3_BAR(b);
1273 barrier->cat7.g = true;
1274 barrier->cat7.l = true;
1275 barrier->flags = IR3_INSTR_SS | IR3_INSTR_SY;
1276 barrier->barrier_class = IR3_BARRIER_EVERYTHING;
1277 break;
1278 case nir_intrinsic_memory_barrier:
1279 barrier = ir3_FENCE(b);
1280 barrier->cat7.g = true;
1281 barrier->cat7.r = true;
1282 barrier->cat7.w = true;
1283 barrier->cat7.l = true;
1284 barrier->barrier_class = IR3_BARRIER_IMAGE_W |
1285 IR3_BARRIER_BUFFER_W;
1286 barrier->barrier_conflict =
1287 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1288 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1289 break;
1290 case nir_intrinsic_memory_barrier_buffer:
1291 barrier = ir3_FENCE(b);
1292 barrier->cat7.g = true;
1293 barrier->cat7.r = true;
1294 barrier->cat7.w = true;
1295 barrier->barrier_class = IR3_BARRIER_BUFFER_W;
1296 barrier->barrier_conflict = IR3_BARRIER_BUFFER_R |
1297 IR3_BARRIER_BUFFER_W;
1298 break;
1299 case nir_intrinsic_memory_barrier_image:
1300 // TODO double check if this should have .g set
1301 barrier = ir3_FENCE(b);
1302 barrier->cat7.g = true;
1303 barrier->cat7.r = true;
1304 barrier->cat7.w = true;
1305 barrier->barrier_class = IR3_BARRIER_IMAGE_W;
1306 barrier->barrier_conflict = IR3_BARRIER_IMAGE_R |
1307 IR3_BARRIER_IMAGE_W;
1308 break;
1309 case nir_intrinsic_memory_barrier_shared:
1310 barrier = ir3_FENCE(b);
1311 barrier->cat7.g = true;
1312 barrier->cat7.l = true;
1313 barrier->cat7.r = true;
1314 barrier->cat7.w = true;
1315 barrier->barrier_class = IR3_BARRIER_SHARED_W;
1316 barrier->barrier_conflict = IR3_BARRIER_SHARED_R |
1317 IR3_BARRIER_SHARED_W;
1318 break;
1319 case nir_intrinsic_group_memory_barrier:
1320 barrier = ir3_FENCE(b);
1321 barrier->cat7.g = true;
1322 barrier->cat7.l = true;
1323 barrier->cat7.r = true;
1324 barrier->cat7.w = true;
1325 barrier->barrier_class = IR3_BARRIER_SHARED_W |
1326 IR3_BARRIER_IMAGE_W |
1327 IR3_BARRIER_BUFFER_W;
1328 barrier->barrier_conflict =
1329 IR3_BARRIER_SHARED_R | IR3_BARRIER_SHARED_W |
1330 IR3_BARRIER_IMAGE_R | IR3_BARRIER_IMAGE_W |
1331 IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1332 break;
1333 default:
1334 unreachable("boo");
1335 }
1336
1337 /* make sure barrier doesn't get DCE'd */
1338 array_insert(b, b->keeps, barrier);
1339 }
1340
1341 static void add_sysval_input_compmask(struct ir3_context *ctx,
1342 gl_system_value slot, unsigned compmask,
1343 struct ir3_instruction *instr)
1344 {
1345 struct ir3_shader_variant *so = ctx->so;
1346 unsigned n = so->inputs_count++;
1347
1348 assert(instr->opc == OPC_META_INPUT);
1349 instr->input.inidx = n;
1350 instr->input.sysval = slot;
1351
1352 so->inputs[n].sysval = true;
1353 so->inputs[n].slot = slot;
1354 so->inputs[n].compmask = compmask;
1355 so->inputs[n].interpolate = INTERP_MODE_FLAT;
1356 so->total_in++;
1357 }
1358
1359 static struct ir3_instruction *
1360 create_sysval_input(struct ir3_context *ctx, gl_system_value slot,
1361 unsigned compmask)
1362 {
1363 assert(compmask);
1364 struct ir3_instruction *sysval = create_input(ctx, compmask);
1365 add_sysval_input_compmask(ctx, slot, compmask, sysval);
1366 return sysval;
1367 }
1368
1369 static struct ir3_instruction *
1370 get_barycentric_centroid(struct ir3_context *ctx)
1371 {
1372 if (!ctx->ij_centroid) {
1373 struct ir3_instruction *xy[2];
1374 struct ir3_instruction *ij;
1375
1376 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID, 0x3);
1377 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1378
1379 ctx->ij_centroid = ir3_create_collect(ctx, xy, 2);
1380 }
1381
1382 return ctx->ij_centroid;
1383 }
1384
1385 static struct ir3_instruction *
1386 get_barycentric_sample(struct ir3_context *ctx)
1387 {
1388 if (!ctx->ij_sample) {
1389 struct ir3_instruction *xy[2];
1390 struct ir3_instruction *ij;
1391
1392 ij = create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_SAMPLE, 0x3);
1393 ir3_split_dest(ctx->block, xy, ij, 0, 2);
1394
1395 ctx->ij_sample = ir3_create_collect(ctx, xy, 2);
1396 }
1397
1398 return ctx->ij_sample;
1399 }
1400
1401 static struct ir3_instruction *
1402 get_barycentric_pixel(struct ir3_context *ctx)
1403 {
1404 /* TODO when tgsi_to_nir supports "new-style" FS inputs switch
1405 * this to create ij_pixel only on demand:
1406 */
1407 return ctx->ij_pixel;
1408 }
1409
1410 static struct ir3_instruction *
1411 get_frag_coord(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1412 {
1413 if (!ctx->frag_coord) {
1414 struct ir3_block *b = ctx->in_block;
1415 struct ir3_instruction *xyzw[4];
1416 struct ir3_instruction *hw_frag_coord;
1417
1418 hw_frag_coord = create_sysval_input(ctx, SYSTEM_VALUE_FRAG_COORD, 0xf);
1419 ir3_split_dest(b, xyzw, hw_frag_coord, 0, 4);
1420
1421 /* for frag_coord.xy, we get unsigned values.. we need
1422 * to subtract (integer) 8 and divide by 16 (right-
1423 * shift by 4) then convert to float:
1424 *
1425 * sub.s tmp, src, 8
1426 * shr.b tmp, tmp, 4
1427 * mov.u32f32 dst, tmp
1428 *
1429 */
1430 for (int i = 0; i < 2; i++) {
1431 xyzw[i] = ir3_COV(b, xyzw[i], TYPE_U32, TYPE_F32);
1432 xyzw[i] = ir3_MUL_F(b, xyzw[i], 0, create_immed(b, fui(1.0 / 16.0)), 0);
1433 }
1434
1435 ctx->frag_coord = ir3_create_collect(ctx, xyzw, 4);
1436 }
1437
1438 ctx->so->fragcoord_compmask |=
1439 nir_ssa_def_components_read(&intr->dest.ssa);
1440
1441 return ctx->frag_coord;
1442 }
1443
1444 static void
1445 emit_intrinsic(struct ir3_context *ctx, nir_intrinsic_instr *intr)
1446 {
1447 const nir_intrinsic_info *info = &nir_intrinsic_infos[intr->intrinsic];
1448 struct ir3_instruction **dst;
1449 struct ir3_instruction * const *src;
1450 struct ir3_block *b = ctx->block;
1451 int idx, comp;
1452
1453 if (info->has_dest) {
1454 unsigned n = nir_intrinsic_dest_components(intr);
1455 dst = ir3_get_dst(ctx, &intr->dest, n);
1456 } else {
1457 dst = NULL;
1458 }
1459
1460 const unsigned primitive_param = ctx->so->shader->const_state.offsets.primitive_param * 4;
1461 const unsigned primitive_map = ctx->so->shader->const_state.offsets.primitive_map * 4;
1462
1463 switch (intr->intrinsic) {
1464 case nir_intrinsic_load_uniform:
1465 idx = nir_intrinsic_base(intr);
1466 if (nir_src_is_const(intr->src[0])) {
1467 idx += nir_src_as_uint(intr->src[0]);
1468 for (int i = 0; i < intr->num_components; i++) {
1469 dst[i] = create_uniform_typed(b, idx + i,
1470 nir_dest_bit_size(intr->dest) == 16 ? TYPE_F16 : TYPE_F32);
1471 }
1472 } else {
1473 src = ir3_get_src(ctx, &intr->src[0]);
1474 for (int i = 0; i < intr->num_components; i++) {
1475 dst[i] = create_uniform_indirect(b, idx + i,
1476 ir3_get_addr0(ctx, src[0], 1));
1477 }
1478 /* NOTE: if relative addressing is used, we set
1479 * constlen in the compiler (to worst-case value)
1480 * since we don't know in the assembler what the max
1481 * addr reg value can be:
1482 */
1483 ctx->so->constlen = MAX2(ctx->so->constlen,
1484 ctx->so->shader->ubo_state.size / 16);
1485 }
1486 break;
1487
1488 case nir_intrinsic_load_vs_primitive_stride_ir3:
1489 dst[0] = create_uniform(b, primitive_param + 0);
1490 break;
1491 case nir_intrinsic_load_vs_vertex_stride_ir3:
1492 dst[0] = create_uniform(b, primitive_param + 1);
1493 break;
1494 case nir_intrinsic_load_hs_patch_stride_ir3:
1495 dst[0] = create_uniform(b, primitive_param + 2);
1496 break;
1497 case nir_intrinsic_load_patch_vertices_in:
1498 dst[0] = create_uniform(b, primitive_param + 3);
1499 break;
1500 case nir_intrinsic_load_tess_param_base_ir3:
1501 dst[0] = create_uniform(b, primitive_param + 4);
1502 dst[1] = create_uniform(b, primitive_param + 5);
1503 break;
1504 case nir_intrinsic_load_tess_factor_base_ir3:
1505 dst[0] = create_uniform(b, primitive_param + 6);
1506 dst[1] = create_uniform(b, primitive_param + 7);
1507 break;
1508
1509 case nir_intrinsic_load_primitive_location_ir3:
1510 idx = nir_intrinsic_driver_location(intr);
1511 dst[0] = create_uniform(b, primitive_map + idx);
1512 break;
1513
1514 case nir_intrinsic_load_gs_header_ir3:
1515 dst[0] = ctx->gs_header;
1516 break;
1517 case nir_intrinsic_load_tcs_header_ir3:
1518 dst[0] = ctx->tcs_header;
1519 break;
1520
1521 case nir_intrinsic_load_primitive_id:
1522 dst[0] = ctx->primitive_id;
1523 break;
1524
1525 case nir_intrinsic_load_tess_coord:
1526 if (!ctx->tess_coord) {
1527 ctx->tess_coord =
1528 create_sysval_input(ctx, SYSTEM_VALUE_TESS_COORD, 0x3);
1529 }
1530 ir3_split_dest(b, dst, ctx->tess_coord, 0, 2);
1531
1532 /* Unused, but ir3_put_dst() below wants to free something */
1533 dst[2] = create_immed(b, 0);
1534 break;
1535
1536 case nir_intrinsic_end_patch_ir3:
1537 assert(ctx->so->type == MESA_SHADER_TESS_CTRL);
1538 struct ir3_instruction *end = ir3_PREDE(b);
1539 array_insert(b, b->keeps, end);
1540
1541 end->barrier_class = IR3_BARRIER_EVERYTHING;
1542 end->barrier_conflict = IR3_BARRIER_EVERYTHING;
1543 break;
1544
1545 case nir_intrinsic_store_global_ir3: {
1546 struct ir3_instruction *value, *addr, *offset;
1547
1548 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1549 ir3_get_src(ctx, &intr->src[1])[0],
1550 ir3_get_src(ctx, &intr->src[1])[1]
1551 }, 2);
1552
1553 offset = ir3_get_src(ctx, &intr->src[2])[0];
1554
1555 value = ir3_create_collect(ctx, ir3_get_src(ctx, &intr->src[0]),
1556 intr->num_components);
1557
1558 struct ir3_instruction *stg =
1559 ir3_STG_G(ctx->block, addr, 0, value, 0,
1560 create_immed(ctx->block, intr->num_components), 0, offset, 0);
1561 stg->cat6.type = TYPE_U32;
1562 stg->cat6.iim_val = 1;
1563
1564 array_insert(b, b->keeps, stg);
1565
1566 stg->barrier_class = IR3_BARRIER_BUFFER_W;
1567 stg->barrier_conflict = IR3_BARRIER_BUFFER_R | IR3_BARRIER_BUFFER_W;
1568 break;
1569 }
1570
1571 case nir_intrinsic_load_global_ir3: {
1572 struct ir3_instruction *addr, *offset;
1573
1574 addr = ir3_create_collect(ctx, (struct ir3_instruction*[]){
1575 ir3_get_src(ctx, &intr->src[0])[0],
1576 ir3_get_src(ctx, &intr->src[0])[1]
1577 }, 2);
1578
1579 offset = ir3_get_src(ctx, &intr->src[1])[0];
1580
1581 struct ir3_instruction *load =
1582 ir3_LDG(b, addr, 0, create_immed(ctx->block, intr->num_components),
1583 0, offset, 0);
1584 load->cat6.type = TYPE_U32;
1585 load->regs[0]->wrmask = MASK(intr->num_components);
1586
1587 load->barrier_class = IR3_BARRIER_BUFFER_R;
1588 load->barrier_conflict = IR3_BARRIER_BUFFER_W;
1589
1590 ir3_split_dest(b, dst, load, 0, intr->num_components);
1591 break;
1592 }
1593
1594 case nir_intrinsic_load_ubo:
1595 emit_intrinsic_load_ubo(ctx, intr, dst);
1596 break;
1597 case nir_intrinsic_load_ubo_ir3:
1598 emit_intrinsic_load_ubo_ldc(ctx, intr, dst);
1599 break;
1600 case nir_intrinsic_load_frag_coord:
1601 ir3_split_dest(b, dst, get_frag_coord(ctx, intr), 0, 4);
1602 break;
1603 case nir_intrinsic_load_sample_pos_from_id: {
1604 /* NOTE: blob seems to always use TYPE_F16 and then cov.f16f32,
1605 * but that doesn't seem necessary.
1606 */
1607 struct ir3_instruction *offset =
1608 ir3_RGETPOS(b, ir3_get_src(ctx, &intr->src[0])[0], 0);
1609 offset->regs[0]->wrmask = 0x3;
1610 offset->cat5.type = TYPE_F32;
1611
1612 ir3_split_dest(b, dst, offset, 0, 2);
1613
1614 break;
1615 }
1616 case nir_intrinsic_load_size_ir3:
1617 if (!ctx->ij_size) {
1618 ctx->ij_size =
1619 create_sysval_input(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE, 0x1);
1620 }
1621 dst[0] = ctx->ij_size;
1622 break;
1623 case nir_intrinsic_load_barycentric_centroid:
1624 ir3_split_dest(b, dst, get_barycentric_centroid(ctx), 0, 2);
1625 break;
1626 case nir_intrinsic_load_barycentric_sample:
1627 if (ctx->so->key.msaa) {
1628 ir3_split_dest(b, dst, get_barycentric_sample(ctx), 0, 2);
1629 } else {
1630 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1631 }
1632 break;
1633 case nir_intrinsic_load_barycentric_pixel:
1634 ir3_split_dest(b, dst, get_barycentric_pixel(ctx), 0, 2);
1635 break;
1636 case nir_intrinsic_load_interpolated_input:
1637 idx = nir_intrinsic_base(intr);
1638 comp = nir_intrinsic_component(intr);
1639 src = ir3_get_src(ctx, &intr->src[0]);
1640 if (nir_src_is_const(intr->src[1])) {
1641 struct ir3_instruction *coord = ir3_create_collect(ctx, src, 2);
1642 idx += nir_src_as_uint(intr->src[1]);
1643 for (int i = 0; i < intr->num_components; i++) {
1644 unsigned inloc = idx * 4 + i + comp;
1645 if (ctx->so->inputs[idx].bary &&
1646 !ctx->so->inputs[idx].use_ldlv) {
1647 dst[i] = ir3_BARY_F(b, create_immed(b, inloc), 0, coord, 0);
1648 } else {
1649 /* for non-varyings use the pre-setup input, since
1650 * that is easier than mapping things back to a
1651 * nir_variable to figure out what it is.
1652 */
1653 dst[i] = ctx->inputs[inloc];
1654 compile_assert(ctx, dst[i]);
1655 }
1656 }
1657 } else {
1658 ir3_context_error(ctx, "unhandled");
1659 }
1660 break;
1661 case nir_intrinsic_load_input:
1662 idx = nir_intrinsic_base(intr);
1663 comp = nir_intrinsic_component(intr);
1664 if (nir_src_is_const(intr->src[0])) {
1665 idx += nir_src_as_uint(intr->src[0]);
1666 for (int i = 0; i < intr->num_components; i++) {
1667 unsigned n = idx * 4 + i + comp;
1668 dst[i] = ctx->inputs[n];
1669 compile_assert(ctx, ctx->inputs[n]);
1670 }
1671 } else {
1672 src = ir3_get_src(ctx, &intr->src[0]);
1673 struct ir3_instruction *collect =
1674 ir3_create_collect(ctx, ctx->ir->inputs, ctx->ninputs);
1675 struct ir3_instruction *addr = ir3_get_addr0(ctx, src[0], 4);
1676 for (int i = 0; i < intr->num_components; i++) {
1677 unsigned n = idx * 4 + i + comp;
1678 dst[i] = create_indirect_load(ctx, ctx->ninputs,
1679 n, addr, collect);
1680 }
1681 }
1682 break;
1683 /* All SSBO intrinsics should have been lowered by 'lower_io_offsets'
1684 * pass and replaced by an ir3-specifc version that adds the
1685 * dword-offset in the last source.
1686 */
1687 case nir_intrinsic_load_ssbo_ir3:
1688 ctx->funcs->emit_intrinsic_load_ssbo(ctx, intr, dst);
1689 break;
1690 case nir_intrinsic_store_ssbo_ir3:
1691 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1692 !ctx->s->info.fs.early_fragment_tests)
1693 ctx->so->no_earlyz = true;
1694 ctx->funcs->emit_intrinsic_store_ssbo(ctx, intr);
1695 break;
1696 case nir_intrinsic_get_buffer_size:
1697 emit_intrinsic_ssbo_size(ctx, intr, dst);
1698 break;
1699 case nir_intrinsic_ssbo_atomic_add_ir3:
1700 case nir_intrinsic_ssbo_atomic_imin_ir3:
1701 case nir_intrinsic_ssbo_atomic_umin_ir3:
1702 case nir_intrinsic_ssbo_atomic_imax_ir3:
1703 case nir_intrinsic_ssbo_atomic_umax_ir3:
1704 case nir_intrinsic_ssbo_atomic_and_ir3:
1705 case nir_intrinsic_ssbo_atomic_or_ir3:
1706 case nir_intrinsic_ssbo_atomic_xor_ir3:
1707 case nir_intrinsic_ssbo_atomic_exchange_ir3:
1708 case nir_intrinsic_ssbo_atomic_comp_swap_ir3:
1709 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1710 !ctx->s->info.fs.early_fragment_tests)
1711 ctx->so->no_earlyz = true;
1712 dst[0] = ctx->funcs->emit_intrinsic_atomic_ssbo(ctx, intr);
1713 break;
1714 case nir_intrinsic_load_shared:
1715 emit_intrinsic_load_shared(ctx, intr, dst);
1716 break;
1717 case nir_intrinsic_store_shared:
1718 emit_intrinsic_store_shared(ctx, intr);
1719 break;
1720 case nir_intrinsic_shared_atomic_add:
1721 case nir_intrinsic_shared_atomic_imin:
1722 case nir_intrinsic_shared_atomic_umin:
1723 case nir_intrinsic_shared_atomic_imax:
1724 case nir_intrinsic_shared_atomic_umax:
1725 case nir_intrinsic_shared_atomic_and:
1726 case nir_intrinsic_shared_atomic_or:
1727 case nir_intrinsic_shared_atomic_xor:
1728 case nir_intrinsic_shared_atomic_exchange:
1729 case nir_intrinsic_shared_atomic_comp_swap:
1730 dst[0] = emit_intrinsic_atomic_shared(ctx, intr);
1731 break;
1732 case nir_intrinsic_image_load:
1733 emit_intrinsic_load_image(ctx, intr, dst);
1734 break;
1735 case nir_intrinsic_bindless_image_load:
1736 /* Bindless uses the IBO state, which doesn't have swizzle filled out,
1737 * so using isam doesn't work.
1738 *
1739 * TODO: can we use isam if we fill out more fields?
1740 */
1741 ctx->funcs->emit_intrinsic_load_image(ctx, intr, dst);
1742 break;
1743 case nir_intrinsic_image_store:
1744 case nir_intrinsic_bindless_image_store:
1745 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1746 !ctx->s->info.fs.early_fragment_tests)
1747 ctx->so->no_earlyz = true;
1748 ctx->funcs->emit_intrinsic_store_image(ctx, intr);
1749 break;
1750 case nir_intrinsic_image_size:
1751 case nir_intrinsic_bindless_image_size:
1752 emit_intrinsic_image_size(ctx, intr, dst);
1753 break;
1754 case nir_intrinsic_image_atomic_add:
1755 case nir_intrinsic_bindless_image_atomic_add:
1756 case nir_intrinsic_image_atomic_imin:
1757 case nir_intrinsic_bindless_image_atomic_imin:
1758 case nir_intrinsic_image_atomic_umin:
1759 case nir_intrinsic_bindless_image_atomic_umin:
1760 case nir_intrinsic_image_atomic_imax:
1761 case nir_intrinsic_bindless_image_atomic_imax:
1762 case nir_intrinsic_image_atomic_umax:
1763 case nir_intrinsic_bindless_image_atomic_umax:
1764 case nir_intrinsic_image_atomic_and:
1765 case nir_intrinsic_bindless_image_atomic_and:
1766 case nir_intrinsic_image_atomic_or:
1767 case nir_intrinsic_bindless_image_atomic_or:
1768 case nir_intrinsic_image_atomic_xor:
1769 case nir_intrinsic_bindless_image_atomic_xor:
1770 case nir_intrinsic_image_atomic_exchange:
1771 case nir_intrinsic_bindless_image_atomic_exchange:
1772 case nir_intrinsic_image_atomic_comp_swap:
1773 case nir_intrinsic_bindless_image_atomic_comp_swap:
1774 if ((ctx->so->type == MESA_SHADER_FRAGMENT) &&
1775 !ctx->s->info.fs.early_fragment_tests)
1776 ctx->so->no_earlyz = true;
1777 dst[0] = ctx->funcs->emit_intrinsic_atomic_image(ctx, intr);
1778 break;
1779 case nir_intrinsic_control_barrier:
1780 case nir_intrinsic_memory_barrier:
1781 case nir_intrinsic_group_memory_barrier:
1782 case nir_intrinsic_memory_barrier_buffer:
1783 case nir_intrinsic_memory_barrier_image:
1784 case nir_intrinsic_memory_barrier_shared:
1785 emit_intrinsic_barrier(ctx, intr);
1786 /* note that blk ptr no longer valid, make that obvious: */
1787 b = NULL;
1788 break;
1789 case nir_intrinsic_store_output:
1790 idx = nir_intrinsic_base(intr);
1791 comp = nir_intrinsic_component(intr);
1792 compile_assert(ctx, nir_src_is_const(intr->src[1]));
1793 idx += nir_src_as_uint(intr->src[1]);
1794
1795 src = ir3_get_src(ctx, &intr->src[0]);
1796 for (int i = 0; i < intr->num_components; i++) {
1797 unsigned n = idx * 4 + i + comp;
1798 ctx->outputs[n] = src[i];
1799 }
1800 break;
1801 case nir_intrinsic_load_base_vertex:
1802 case nir_intrinsic_load_first_vertex:
1803 if (!ctx->basevertex) {
1804 ctx->basevertex = create_driver_param(ctx, IR3_DP_VTXID_BASE);
1805 }
1806 dst[0] = ctx->basevertex;
1807 break;
1808 case nir_intrinsic_load_base_instance:
1809 if (!ctx->base_instance) {
1810 ctx->base_instance = create_driver_param(ctx, IR3_DP_INSTID_BASE);
1811 }
1812 dst[0] = ctx->base_instance;
1813 break;
1814 case nir_intrinsic_load_vertex_id_zero_base:
1815 case nir_intrinsic_load_vertex_id:
1816 if (!ctx->vertex_id) {
1817 gl_system_value sv = (intr->intrinsic == nir_intrinsic_load_vertex_id) ?
1818 SYSTEM_VALUE_VERTEX_ID : SYSTEM_VALUE_VERTEX_ID_ZERO_BASE;
1819 ctx->vertex_id = create_sysval_input(ctx, sv, 0x1);
1820 }
1821 dst[0] = ctx->vertex_id;
1822 break;
1823 case nir_intrinsic_load_instance_id:
1824 if (!ctx->instance_id) {
1825 ctx->instance_id = create_sysval_input(ctx, SYSTEM_VALUE_INSTANCE_ID, 0x1);
1826 }
1827 dst[0] = ctx->instance_id;
1828 break;
1829 case nir_intrinsic_load_sample_id:
1830 ctx->so->per_samp = true;
1831 /* fall-thru */
1832 case nir_intrinsic_load_sample_id_no_per_sample:
1833 if (!ctx->samp_id) {
1834 ctx->samp_id = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_ID, 0x1);
1835 ctx->samp_id->regs[0]->flags |= IR3_REG_HALF;
1836 }
1837 dst[0] = ir3_COV(b, ctx->samp_id, TYPE_U16, TYPE_U32);
1838 break;
1839 case nir_intrinsic_load_sample_mask_in:
1840 if (!ctx->samp_mask_in) {
1841 ctx->samp_mask_in = create_sysval_input(ctx, SYSTEM_VALUE_SAMPLE_MASK_IN, 0x1);
1842 }
1843 dst[0] = ctx->samp_mask_in;
1844 break;
1845 case nir_intrinsic_load_user_clip_plane:
1846 idx = nir_intrinsic_ucp_id(intr);
1847 for (int i = 0; i < intr->num_components; i++) {
1848 unsigned n = idx * 4 + i;
1849 dst[i] = create_driver_param(ctx, IR3_DP_UCP0_X + n);
1850 }
1851 break;
1852 case nir_intrinsic_load_front_face:
1853 if (!ctx->frag_face) {
1854 ctx->so->frag_face = true;
1855 ctx->frag_face = create_sysval_input(ctx, SYSTEM_VALUE_FRONT_FACE, 0x1);
1856 ctx->frag_face->regs[0]->flags |= IR3_REG_HALF;
1857 }
1858 /* for fragface, we get -1 for back and 0 for front. However this is
1859 * the inverse of what nir expects (where ~0 is true).
1860 */
1861 dst[0] = ir3_CMPS_S(b,
1862 ctx->frag_face, 0,
1863 create_immed_typed(b, 0, TYPE_U16), 0);
1864 dst[0]->cat2.condition = IR3_COND_EQ;
1865 break;
1866 case nir_intrinsic_load_local_invocation_id:
1867 if (!ctx->local_invocation_id) {
1868 ctx->local_invocation_id =
1869 create_sysval_input(ctx, SYSTEM_VALUE_LOCAL_INVOCATION_ID, 0x7);
1870 }
1871 ir3_split_dest(b, dst, ctx->local_invocation_id, 0, 3);
1872 break;
1873 case nir_intrinsic_load_work_group_id:
1874 if (!ctx->work_group_id) {
1875 ctx->work_group_id =
1876 create_sysval_input(ctx, SYSTEM_VALUE_WORK_GROUP_ID, 0x7);
1877 ctx->work_group_id->regs[0]->flags |= IR3_REG_HIGH;
1878 }
1879 ir3_split_dest(b, dst, ctx->work_group_id, 0, 3);
1880 break;
1881 case nir_intrinsic_load_num_work_groups:
1882 for (int i = 0; i < intr->num_components; i++) {
1883 dst[i] = create_driver_param(ctx, IR3_DP_NUM_WORK_GROUPS_X + i);
1884 }
1885 break;
1886 case nir_intrinsic_load_local_group_size:
1887 for (int i = 0; i < intr->num_components; i++) {
1888 dst[i] = create_driver_param(ctx, IR3_DP_LOCAL_GROUP_SIZE_X + i);
1889 }
1890 break;
1891 case nir_intrinsic_discard_if:
1892 case nir_intrinsic_discard: {
1893 struct ir3_instruction *cond, *kill;
1894
1895 if (intr->intrinsic == nir_intrinsic_discard_if) {
1896 /* conditional discard: */
1897 src = ir3_get_src(ctx, &intr->src[0]);
1898 cond = src[0];
1899 } else {
1900 /* unconditional discard: */
1901 cond = create_immed(b, 1);
1902 }
1903
1904 /* NOTE: only cmps.*.* can write p0.x: */
1905 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1906 cond->cat2.condition = IR3_COND_NE;
1907
1908 /* condition always goes in predicate register: */
1909 cond->regs[0]->num = regid(REG_P0, 0);
1910 cond->regs[0]->flags &= ~IR3_REG_SSA;
1911
1912 kill = ir3_KILL(b, cond, 0);
1913 kill->regs[1]->num = regid(REG_P0, 0);
1914 array_insert(ctx->ir, ctx->ir->predicates, kill);
1915
1916 array_insert(b, b->keeps, kill);
1917 ctx->so->no_earlyz = true;
1918
1919 break;
1920 }
1921
1922 case nir_intrinsic_cond_end_ir3: {
1923 struct ir3_instruction *cond, *kill;
1924
1925 src = ir3_get_src(ctx, &intr->src[0]);
1926 cond = src[0];
1927
1928 /* NOTE: only cmps.*.* can write p0.x: */
1929 cond = ir3_CMPS_S(b, cond, 0, create_immed(b, 0), 0);
1930 cond->cat2.condition = IR3_COND_NE;
1931
1932 /* condition always goes in predicate register: */
1933 cond->regs[0]->num = regid(REG_P0, 0);
1934
1935 kill = ir3_PREDT(b, cond, 0);
1936
1937 kill->barrier_class = IR3_BARRIER_EVERYTHING;
1938 kill->barrier_conflict = IR3_BARRIER_EVERYTHING;
1939
1940 array_insert(ctx->ir, ctx->ir->predicates, kill);
1941 array_insert(b, b->keeps, kill);
1942 break;
1943 }
1944
1945 case nir_intrinsic_load_shared_ir3:
1946 emit_intrinsic_load_shared_ir3(ctx, intr, dst);
1947 break;
1948 case nir_intrinsic_store_shared_ir3:
1949 emit_intrinsic_store_shared_ir3(ctx, intr);
1950 break;
1951 case nir_intrinsic_bindless_resource_ir3:
1952 dst[0] = ir3_get_src(ctx, &intr->src[0])[0];
1953 break;
1954 default:
1955 ir3_context_error(ctx, "Unhandled intrinsic type: %s\n",
1956 nir_intrinsic_infos[intr->intrinsic].name);
1957 break;
1958 }
1959
1960 if (info->has_dest)
1961 ir3_put_dst(ctx, &intr->dest);
1962 }
1963
1964 static void
1965 emit_load_const(struct ir3_context *ctx, nir_load_const_instr *instr)
1966 {
1967 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &instr->def,
1968 instr->def.num_components);
1969
1970 if (instr->def.bit_size == 16) {
1971 for (int i = 0; i < instr->def.num_components; i++)
1972 dst[i] = create_immed_typed(ctx->block,
1973 instr->value[i].u16,
1974 TYPE_U16);
1975 } else {
1976 for (int i = 0; i < instr->def.num_components; i++)
1977 dst[i] = create_immed_typed(ctx->block,
1978 instr->value[i].u32,
1979 TYPE_U32);
1980 }
1981
1982 }
1983
1984 static void
1985 emit_undef(struct ir3_context *ctx, nir_ssa_undef_instr *undef)
1986 {
1987 struct ir3_instruction **dst = ir3_get_dst_ssa(ctx, &undef->def,
1988 undef->def.num_components);
1989 type_t type = (undef->def.bit_size == 16) ? TYPE_U16 : TYPE_U32;
1990
1991 /* backend doesn't want undefined instructions, so just plug
1992 * in 0.0..
1993 */
1994 for (int i = 0; i < undef->def.num_components; i++)
1995 dst[i] = create_immed_typed(ctx->block, fui(0.0), type);
1996 }
1997
1998 /*
1999 * texture fetch/sample instructions:
2000 */
2001
2002 static type_t
2003 get_tex_dest_type(nir_tex_instr *tex)
2004 {
2005 type_t type;
2006
2007 switch (nir_alu_type_get_base_type(tex->dest_type)) {
2008 case nir_type_invalid:
2009 case nir_type_float:
2010 type = nir_dest_bit_size(tex->dest) == 16 ? TYPE_F16 : TYPE_F32;
2011 break;
2012 case nir_type_int:
2013 type = nir_dest_bit_size(tex->dest) == 16 ? TYPE_S16 : TYPE_S32;
2014 break;
2015 case nir_type_uint:
2016 case nir_type_bool:
2017 type = nir_dest_bit_size(tex->dest) == 16 ? TYPE_U16 : TYPE_U32;
2018 break;
2019 default:
2020 unreachable("bad dest_type");
2021 }
2022
2023 return type;
2024 }
2025
2026 static void
2027 tex_info(nir_tex_instr *tex, unsigned *flagsp, unsigned *coordsp)
2028 {
2029 unsigned coords = glsl_get_sampler_dim_coordinate_components(tex->sampler_dim);
2030 unsigned flags = 0;
2031
2032 /* note: would use tex->coord_components.. except txs.. also,
2033 * since array index goes after shadow ref, we don't want to
2034 * count it:
2035 */
2036 if (coords == 3)
2037 flags |= IR3_INSTR_3D;
2038
2039 if (tex->is_shadow && tex->op != nir_texop_lod)
2040 flags |= IR3_INSTR_S;
2041
2042 if (tex->is_array && tex->op != nir_texop_lod)
2043 flags |= IR3_INSTR_A;
2044
2045 *flagsp = flags;
2046 *coordsp = coords;
2047 }
2048
2049 /* Gets the sampler/texture idx as a hvec2. Which could either be dynamic
2050 * or immediate (in which case it will get lowered later to a non .s2en
2051 * version of the tex instruction which encode tex/samp as immediates:
2052 */
2053 static struct tex_src_info
2054 get_tex_samp_tex_src(struct ir3_context *ctx, nir_tex_instr *tex)
2055 {
2056 struct ir3_block *b = ctx->block;
2057 struct tex_src_info info = { 0 };
2058 int texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_handle);
2059 int sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_handle);
2060 struct ir3_instruction *texture, *sampler;
2061
2062 if (texture_idx >= 0 || sampler_idx >= 0) {
2063 /* Bindless case */
2064 info.flags |= IR3_INSTR_B;
2065
2066 /* Gather information required to determine which encoding to
2067 * choose as well as for prefetch.
2068 */
2069 nir_intrinsic_instr *bindless_tex = NULL;
2070 bool tex_const;
2071 if (texture_idx >= 0) {
2072 ctx->so->bindless_tex = true;
2073 bindless_tex = ir3_bindless_resource(tex->src[texture_idx].src);
2074 assert(bindless_tex);
2075 info.tex_base = nir_intrinsic_desc_set(bindless_tex);
2076 tex_const = nir_src_is_const(bindless_tex->src[0]);
2077 if (tex_const)
2078 info.tex_idx = nir_src_as_uint(bindless_tex->src[0]);
2079 } else {
2080 /* To simplify some of the logic below, assume the index is
2081 * constant 0 when it's not enabled.
2082 */
2083 tex_const = true;
2084 info.tex_idx = 0;
2085 }
2086 nir_intrinsic_instr *bindless_samp = NULL;
2087 bool samp_const;
2088 if (sampler_idx >= 0) {
2089 ctx->so->bindless_samp = true;
2090 bindless_samp = ir3_bindless_resource(tex->src[sampler_idx].src);
2091 assert(bindless_samp);
2092 info.samp_base = nir_intrinsic_desc_set(bindless_samp);
2093 samp_const = nir_src_is_const(bindless_samp->src[0]);
2094 if (samp_const)
2095 info.samp_idx = nir_src_as_uint(bindless_samp->src[0]);
2096 } else {
2097 samp_const = true;
2098 info.samp_idx = 0;
2099 }
2100
2101 /* Choose encoding. */
2102 if (tex_const && samp_const && info.tex_idx < 256 && info.samp_idx < 256) {
2103 if (info.tex_idx < 16 && info.samp_idx < 16 &&
2104 (!bindless_tex || !bindless_samp || info.tex_base == info.samp_base)) {
2105 /* Everything fits within the instruction */
2106 info.base = info.tex_base;
2107 info.combined_idx = info.samp_idx | (info.tex_idx << 4);
2108 } else {
2109 info.base = info.tex_base;
2110 info.a1_val = info.tex_idx << 3 | info.samp_base;
2111 info.combined_idx = info.samp_idx;
2112 info.flags |= IR3_INSTR_A1EN;
2113 }
2114 info.samp_tex = NULL;
2115 } else {
2116 info.flags |= IR3_INSTR_S2EN;
2117 /* In the indirect case, we only use a1.x to store the sampler
2118 * base if it differs from the texture base.
2119 */
2120 if (!bindless_tex || !bindless_samp || info.tex_base == info.samp_base) {
2121 info.base = info.tex_base;
2122 } else {
2123 info.base = info.tex_base;
2124 info.a1_val = info.samp_base;
2125 info.flags |= IR3_INSTR_A1EN;
2126 }
2127
2128 /* Note: the indirect source is now a vec2 instead of hvec2, and
2129 * for some reason the texture and sampler are swapped.
2130 */
2131 struct ir3_instruction *texture, *sampler;
2132
2133 if (bindless_tex) {
2134 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
2135 } else {
2136 texture = create_immed(b, 0);
2137 }
2138
2139 if (bindless_samp) {
2140 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
2141 } else {
2142 sampler = create_immed(b, 0);
2143 }
2144 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2145 texture,
2146 sampler,
2147 }, 2);
2148 }
2149 } else {
2150 info.flags |= IR3_INSTR_S2EN;
2151 texture_idx = nir_tex_instr_src_index(tex, nir_tex_src_texture_offset);
2152 sampler_idx = nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset);
2153 if (texture_idx >= 0) {
2154 texture = ir3_get_src(ctx, &tex->src[texture_idx].src)[0];
2155 texture = ir3_COV(ctx->block, texture, TYPE_U32, TYPE_U16);
2156 } else {
2157 /* TODO what to do for dynamic case? I guess we only need the
2158 * max index for astc srgb workaround so maybe not a problem
2159 * to worry about if we don't enable indirect samplers for
2160 * a4xx?
2161 */
2162 ctx->max_texture_index = MAX2(ctx->max_texture_index, tex->texture_index);
2163 texture = create_immed_typed(ctx->block, tex->texture_index, TYPE_U16);
2164 info.tex_idx = tex->texture_index;
2165 }
2166
2167 if (sampler_idx >= 0) {
2168 sampler = ir3_get_src(ctx, &tex->src[sampler_idx].src)[0];
2169 sampler = ir3_COV(ctx->block, sampler, TYPE_U32, TYPE_U16);
2170 } else {
2171 sampler = create_immed_typed(ctx->block, tex->sampler_index, TYPE_U16);
2172 info.samp_idx = tex->texture_index;
2173 }
2174
2175 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2176 sampler,
2177 texture,
2178 }, 2);
2179 }
2180
2181 return info;
2182 }
2183
2184 static void
2185 emit_tex(struct ir3_context *ctx, nir_tex_instr *tex)
2186 {
2187 struct ir3_block *b = ctx->block;
2188 struct ir3_instruction **dst, *sam, *src0[12], *src1[4];
2189 struct ir3_instruction * const *coord, * const *off, * const *ddx, * const *ddy;
2190 struct ir3_instruction *lod, *compare, *proj, *sample_index;
2191 struct tex_src_info info = { 0 };
2192 bool has_bias = false, has_lod = false, has_proj = false, has_off = false;
2193 unsigned i, coords, flags, ncomp;
2194 unsigned nsrc0 = 0, nsrc1 = 0;
2195 type_t type;
2196 opc_t opc = 0;
2197
2198 ncomp = nir_dest_num_components(tex->dest);
2199
2200 coord = off = ddx = ddy = NULL;
2201 lod = proj = compare = sample_index = NULL;
2202
2203 dst = ir3_get_dst(ctx, &tex->dest, ncomp);
2204
2205 for (unsigned i = 0; i < tex->num_srcs; i++) {
2206 switch (tex->src[i].src_type) {
2207 case nir_tex_src_coord:
2208 coord = ir3_get_src(ctx, &tex->src[i].src);
2209 break;
2210 case nir_tex_src_bias:
2211 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
2212 has_bias = true;
2213 break;
2214 case nir_tex_src_lod:
2215 lod = ir3_get_src(ctx, &tex->src[i].src)[0];
2216 has_lod = true;
2217 break;
2218 case nir_tex_src_comparator: /* shadow comparator */
2219 compare = ir3_get_src(ctx, &tex->src[i].src)[0];
2220 break;
2221 case nir_tex_src_projector:
2222 proj = ir3_get_src(ctx, &tex->src[i].src)[0];
2223 has_proj = true;
2224 break;
2225 case nir_tex_src_offset:
2226 off = ir3_get_src(ctx, &tex->src[i].src);
2227 has_off = true;
2228 break;
2229 case nir_tex_src_ddx:
2230 ddx = ir3_get_src(ctx, &tex->src[i].src);
2231 break;
2232 case nir_tex_src_ddy:
2233 ddy = ir3_get_src(ctx, &tex->src[i].src);
2234 break;
2235 case nir_tex_src_ms_index:
2236 sample_index = ir3_get_src(ctx, &tex->src[i].src)[0];
2237 break;
2238 case nir_tex_src_texture_offset:
2239 case nir_tex_src_sampler_offset:
2240 case nir_tex_src_texture_handle:
2241 case nir_tex_src_sampler_handle:
2242 /* handled in get_tex_samp_src() */
2243 break;
2244 default:
2245 ir3_context_error(ctx, "Unhandled NIR tex src type: %d\n",
2246 tex->src[i].src_type);
2247 return;
2248 }
2249 }
2250
2251 switch (tex->op) {
2252 case nir_texop_tex_prefetch:
2253 compile_assert(ctx, !has_bias);
2254 compile_assert(ctx, !has_lod);
2255 compile_assert(ctx, !compare);
2256 compile_assert(ctx, !has_proj);
2257 compile_assert(ctx, !has_off);
2258 compile_assert(ctx, !ddx);
2259 compile_assert(ctx, !ddy);
2260 compile_assert(ctx, !sample_index);
2261 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_texture_offset) < 0);
2262 compile_assert(ctx, nir_tex_instr_src_index(tex, nir_tex_src_sampler_offset) < 0);
2263
2264 if (ctx->so->num_sampler_prefetch < IR3_MAX_SAMPLER_PREFETCH) {
2265 opc = OPC_META_TEX_PREFETCH;
2266 ctx->so->num_sampler_prefetch++;
2267 break;
2268 }
2269 /* fallthru */
2270 case nir_texop_tex: opc = has_lod ? OPC_SAML : OPC_SAM; break;
2271 case nir_texop_txb: opc = OPC_SAMB; break;
2272 case nir_texop_txl: opc = OPC_SAML; break;
2273 case nir_texop_txd: opc = OPC_SAMGQ; break;
2274 case nir_texop_txf: opc = OPC_ISAML; break;
2275 case nir_texop_lod: opc = OPC_GETLOD; break;
2276 case nir_texop_tg4:
2277 /* NOTE: a4xx might need to emulate gather w/ txf (this is
2278 * what blob does, seems gather is broken?), and a3xx did
2279 * not support it (but probably could also emulate).
2280 */
2281 switch (tex->component) {
2282 case 0: opc = OPC_GATHER4R; break;
2283 case 1: opc = OPC_GATHER4G; break;
2284 case 2: opc = OPC_GATHER4B; break;
2285 case 3: opc = OPC_GATHER4A; break;
2286 }
2287 break;
2288 case nir_texop_txf_ms_fb:
2289 case nir_texop_txf_ms: opc = OPC_ISAMM; break;
2290 default:
2291 ir3_context_error(ctx, "Unhandled NIR tex type: %d\n", tex->op);
2292 return;
2293 }
2294
2295 tex_info(tex, &flags, &coords);
2296
2297 /*
2298 * lay out the first argument in the proper order:
2299 * - actual coordinates first
2300 * - shadow reference
2301 * - array index
2302 * - projection w
2303 * - starting at offset 4, dpdx.xy, dpdy.xy
2304 *
2305 * bias/lod go into the second arg
2306 */
2307
2308 /* insert tex coords: */
2309 for (i = 0; i < coords; i++)
2310 src0[i] = coord[i];
2311
2312 nsrc0 = i;
2313
2314 /* scale up integer coords for TXF based on the LOD */
2315 if (ctx->compiler->unminify_coords && (opc == OPC_ISAML)) {
2316 assert(has_lod);
2317 for (i = 0; i < coords; i++)
2318 src0[i] = ir3_SHL_B(b, src0[i], 0, lod, 0);
2319 }
2320
2321 if (coords == 1) {
2322 /* hw doesn't do 1d, so we treat it as 2d with
2323 * height of 1, and patch up the y coord.
2324 */
2325 if (is_isam(opc)) {
2326 src0[nsrc0++] = create_immed(b, 0);
2327 } else {
2328 src0[nsrc0++] = create_immed(b, fui(0.5));
2329 }
2330 }
2331
2332 if (tex->is_shadow && tex->op != nir_texop_lod)
2333 src0[nsrc0++] = compare;
2334
2335 if (tex->is_array && tex->op != nir_texop_lod) {
2336 struct ir3_instruction *idx = coord[coords];
2337
2338 /* the array coord for cube arrays needs 0.5 added to it */
2339 if (ctx->compiler->array_index_add_half && !is_isam(opc))
2340 idx = ir3_ADD_F(b, idx, 0, create_immed(b, fui(0.5)), 0);
2341
2342 src0[nsrc0++] = idx;
2343 }
2344
2345 if (has_proj) {
2346 src0[nsrc0++] = proj;
2347 flags |= IR3_INSTR_P;
2348 }
2349
2350 /* pad to 4, then ddx/ddy: */
2351 if (tex->op == nir_texop_txd) {
2352 while (nsrc0 < 4)
2353 src0[nsrc0++] = create_immed(b, fui(0.0));
2354 for (i = 0; i < coords; i++)
2355 src0[nsrc0++] = ddx[i];
2356 if (coords < 2)
2357 src0[nsrc0++] = create_immed(b, fui(0.0));
2358 for (i = 0; i < coords; i++)
2359 src0[nsrc0++] = ddy[i];
2360 if (coords < 2)
2361 src0[nsrc0++] = create_immed(b, fui(0.0));
2362 }
2363
2364 /* NOTE a3xx (and possibly a4xx?) might be different, using isaml
2365 * with scaled x coord according to requested sample:
2366 */
2367 if (opc == OPC_ISAMM) {
2368 if (ctx->compiler->txf_ms_with_isaml) {
2369 /* the samples are laid out in x dimension as
2370 * 0 1 2 3
2371 * x_ms = (x << ms) + sample_index;
2372 */
2373 struct ir3_instruction *ms;
2374 ms = create_immed(b, (ctx->samples >> (2 * tex->texture_index)) & 3);
2375
2376 src0[0] = ir3_SHL_B(b, src0[0], 0, ms, 0);
2377 src0[0] = ir3_ADD_U(b, src0[0], 0, sample_index, 0);
2378
2379 opc = OPC_ISAML;
2380 } else {
2381 src0[nsrc0++] = sample_index;
2382 }
2383 }
2384
2385 /*
2386 * second argument (if applicable):
2387 * - offsets
2388 * - lod
2389 * - bias
2390 */
2391 if (has_off | has_lod | has_bias) {
2392 if (has_off) {
2393 unsigned off_coords = coords;
2394 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2395 off_coords--;
2396 for (i = 0; i < off_coords; i++)
2397 src1[nsrc1++] = off[i];
2398 if (off_coords < 2)
2399 src1[nsrc1++] = create_immed(b, fui(0.0));
2400 flags |= IR3_INSTR_O;
2401 }
2402
2403 if (has_lod | has_bias)
2404 src1[nsrc1++] = lod;
2405 }
2406
2407 type = get_tex_dest_type(tex);
2408
2409 if (opc == OPC_GETLOD)
2410 type = TYPE_S32;
2411
2412
2413 if (tex->op == nir_texop_txf_ms_fb) {
2414 /* only expect a single txf_ms_fb per shader: */
2415 compile_assert(ctx, !ctx->so->fb_read);
2416 compile_assert(ctx, ctx->so->type == MESA_SHADER_FRAGMENT);
2417
2418 ctx->so->fb_read = true;
2419 info.samp_tex = ir3_create_collect(ctx, (struct ir3_instruction*[]){
2420 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2421 create_immed_typed(ctx->block, ctx->so->num_samp, TYPE_U16),
2422 }, 2);
2423 info.flags = IR3_INSTR_S2EN;
2424
2425 ctx->so->num_samp++;
2426 } else {
2427 info = get_tex_samp_tex_src(ctx, tex);
2428 }
2429
2430 struct ir3_instruction *col0 = ir3_create_collect(ctx, src0, nsrc0);
2431 struct ir3_instruction *col1 = ir3_create_collect(ctx, src1, nsrc1);
2432
2433 if (opc == OPC_META_TEX_PREFETCH) {
2434 int idx = nir_tex_instr_src_index(tex, nir_tex_src_coord);
2435
2436 compile_assert(ctx, tex->src[idx].src.is_ssa);
2437
2438 sam = ir3_META_TEX_PREFETCH(b);
2439 __ssa_dst(sam)->wrmask = MASK(ncomp); /* dst */
2440 __ssa_src(sam, get_barycentric_pixel(ctx), 0);
2441 sam->prefetch.input_offset =
2442 ir3_nir_coord_offset(tex->src[idx].src.ssa);
2443 /* make sure not to add irrelevant flags like S2EN */
2444 sam->flags = flags | (info.flags & IR3_INSTR_B);
2445 sam->prefetch.tex = info.tex_idx;
2446 sam->prefetch.samp = info.samp_idx;
2447 sam->prefetch.tex_base = info.tex_base;
2448 sam->prefetch.samp_base = info.samp_base;
2449 } else {
2450 info.flags |= flags;
2451 sam = emit_sam(ctx, opc, info, type, MASK(ncomp), col0, col1);
2452 }
2453
2454 if ((ctx->astc_srgb & (1 << tex->texture_index)) && !nir_tex_instr_is_query(tex)) {
2455 assert(opc != OPC_META_TEX_PREFETCH);
2456
2457 /* only need first 3 components: */
2458 sam->regs[0]->wrmask = 0x7;
2459 ir3_split_dest(b, dst, sam, 0, 3);
2460
2461 /* we need to sample the alpha separately with a non-ASTC
2462 * texture state:
2463 */
2464 sam = ir3_SAM(b, opc, type, 0b1000, flags | info.flags,
2465 info.samp_tex, col0, col1);
2466
2467 array_insert(ctx->ir, ctx->ir->astc_srgb, sam);
2468
2469 /* fixup .w component: */
2470 ir3_split_dest(b, &dst[3], sam, 3, 1);
2471 } else {
2472 /* normal (non-workaround) case: */
2473 ir3_split_dest(b, dst, sam, 0, ncomp);
2474 }
2475
2476 /* GETLOD returns results in 4.8 fixed point */
2477 if (opc == OPC_GETLOD) {
2478 struct ir3_instruction *factor = create_immed(b, fui(1.0 / 256));
2479
2480 compile_assert(ctx, tex->dest_type == nir_type_float);
2481 for (i = 0; i < 2; i++) {
2482 dst[i] = ir3_MUL_F(b, ir3_COV(b, dst[i], TYPE_S32, TYPE_F32), 0,
2483 factor, 0);
2484 }
2485 }
2486
2487 ir3_put_dst(ctx, &tex->dest);
2488 }
2489
2490 static void
2491 emit_tex_info(struct ir3_context *ctx, nir_tex_instr *tex, unsigned idx)
2492 {
2493 struct ir3_block *b = ctx->block;
2494 struct ir3_instruction **dst, *sam;
2495 type_t dst_type = get_tex_dest_type(tex);
2496 struct tex_src_info info = get_tex_samp_tex_src(ctx, tex);
2497
2498 dst = ir3_get_dst(ctx, &tex->dest, 1);
2499
2500 sam = emit_sam(ctx, OPC_GETINFO, info, dst_type, 1 << idx, NULL, NULL);
2501
2502 /* even though there is only one component, since it ends
2503 * up in .y/.z/.w rather than .x, we need a split_dest()
2504 */
2505 ir3_split_dest(b, dst, sam, idx, 1);
2506
2507 /* The # of levels comes from getinfo.z. We need to add 1 to it, since
2508 * the value in TEX_CONST_0 is zero-based.
2509 */
2510 if (ctx->compiler->levels_add_one)
2511 dst[0] = ir3_ADD_U(b, dst[0], 0, create_immed(b, 1), 0);
2512
2513 ir3_put_dst(ctx, &tex->dest);
2514 }
2515
2516 static void
2517 emit_tex_txs(struct ir3_context *ctx, nir_tex_instr *tex)
2518 {
2519 struct ir3_block *b = ctx->block;
2520 struct ir3_instruction **dst, *sam;
2521 struct ir3_instruction *lod;
2522 unsigned flags, coords;
2523 type_t dst_type = get_tex_dest_type(tex);
2524 struct tex_src_info info = get_tex_samp_tex_src(ctx, tex);
2525
2526 tex_info(tex, &flags, &coords);
2527 info.flags |= flags;
2528
2529 /* Actually we want the number of dimensions, not coordinates. This
2530 * distinction only matters for cubes.
2531 */
2532 if (tex->sampler_dim == GLSL_SAMPLER_DIM_CUBE)
2533 coords = 2;
2534
2535 dst = ir3_get_dst(ctx, &tex->dest, 4);
2536
2537 int lod_idx = nir_tex_instr_src_index(tex, nir_tex_src_lod);
2538 compile_assert(ctx, lod_idx >= 0);
2539
2540 lod = ir3_get_src(ctx, &tex->src[lod_idx].src)[0];
2541
2542 sam = emit_sam(ctx, OPC_GETSIZE, info, dst_type, 0b1111, lod, NULL);
2543 ir3_split_dest(b, dst, sam, 0, 4);
2544
2545 /* Array size actually ends up in .w rather than .z. This doesn't
2546 * matter for miplevel 0, but for higher mips the value in z is
2547 * minified whereas w stays. Also, the value in TEX_CONST_3_DEPTH is
2548 * returned, which means that we have to add 1 to it for arrays.
2549 */
2550 if (tex->is_array) {
2551 if (ctx->compiler->levels_add_one) {
2552 dst[coords] = ir3_ADD_U(b, dst[3], 0, create_immed(b, 1), 0);
2553 } else {
2554 dst[coords] = ir3_MOV(b, dst[3], TYPE_U32);
2555 }
2556 }
2557
2558 ir3_put_dst(ctx, &tex->dest);
2559 }
2560
2561 static void
2562 emit_jump(struct ir3_context *ctx, nir_jump_instr *jump)
2563 {
2564 switch (jump->type) {
2565 case nir_jump_break:
2566 case nir_jump_continue:
2567 case nir_jump_return:
2568 /* I *think* we can simply just ignore this, and use the
2569 * successor block link to figure out where we need to
2570 * jump to for break/continue
2571 */
2572 break;
2573 default:
2574 ir3_context_error(ctx, "Unhandled NIR jump type: %d\n", jump->type);
2575 break;
2576 }
2577 }
2578
2579 static void
2580 emit_instr(struct ir3_context *ctx, nir_instr *instr)
2581 {
2582 switch (instr->type) {
2583 case nir_instr_type_alu:
2584 emit_alu(ctx, nir_instr_as_alu(instr));
2585 break;
2586 case nir_instr_type_deref:
2587 /* ignored, handled as part of the intrinsic they are src to */
2588 break;
2589 case nir_instr_type_intrinsic:
2590 emit_intrinsic(ctx, nir_instr_as_intrinsic(instr));
2591 break;
2592 case nir_instr_type_load_const:
2593 emit_load_const(ctx, nir_instr_as_load_const(instr));
2594 break;
2595 case nir_instr_type_ssa_undef:
2596 emit_undef(ctx, nir_instr_as_ssa_undef(instr));
2597 break;
2598 case nir_instr_type_tex: {
2599 nir_tex_instr *tex = nir_instr_as_tex(instr);
2600 /* couple tex instructions get special-cased:
2601 */
2602 switch (tex->op) {
2603 case nir_texop_txs:
2604 emit_tex_txs(ctx, tex);
2605 break;
2606 case nir_texop_query_levels:
2607 emit_tex_info(ctx, tex, 2);
2608 break;
2609 case nir_texop_texture_samples:
2610 emit_tex_info(ctx, tex, 3);
2611 break;
2612 default:
2613 emit_tex(ctx, tex);
2614 break;
2615 }
2616 break;
2617 }
2618 case nir_instr_type_jump:
2619 emit_jump(ctx, nir_instr_as_jump(instr));
2620 break;
2621 case nir_instr_type_phi:
2622 /* we have converted phi webs to regs in NIR by now */
2623 ir3_context_error(ctx, "Unexpected NIR instruction type: %d\n", instr->type);
2624 break;
2625 case nir_instr_type_call:
2626 case nir_instr_type_parallel_copy:
2627 ir3_context_error(ctx, "Unhandled NIR instruction type: %d\n", instr->type);
2628 break;
2629 }
2630 }
2631
2632 static struct ir3_block *
2633 get_block(struct ir3_context *ctx, const nir_block *nblock)
2634 {
2635 struct ir3_block *block;
2636 struct hash_entry *hentry;
2637
2638 hentry = _mesa_hash_table_search(ctx->block_ht, nblock);
2639 if (hentry)
2640 return hentry->data;
2641
2642 block = ir3_block_create(ctx->ir);
2643 block->nblock = nblock;
2644 _mesa_hash_table_insert(ctx->block_ht, nblock, block);
2645
2646 set_foreach(nblock->predecessors, sentry) {
2647 _mesa_set_add(block->predecessors, get_block(ctx, sentry->key));
2648 }
2649
2650 return block;
2651 }
2652
2653 static void
2654 emit_block(struct ir3_context *ctx, nir_block *nblock)
2655 {
2656 struct ir3_block *block = get_block(ctx, nblock);
2657
2658 for (int i = 0; i < ARRAY_SIZE(block->successors); i++) {
2659 if (nblock->successors[i]) {
2660 block->successors[i] =
2661 get_block(ctx, nblock->successors[i]);
2662 }
2663 }
2664
2665 ctx->block = block;
2666 list_addtail(&block->node, &ctx->ir->block_list);
2667
2668 /* re-emit addr register in each block if needed: */
2669 for (int i = 0; i < ARRAY_SIZE(ctx->addr0_ht); i++) {
2670 _mesa_hash_table_destroy(ctx->addr0_ht[i], NULL);
2671 ctx->addr0_ht[i] = NULL;
2672 }
2673
2674 _mesa_hash_table_u64_destroy(ctx->addr1_ht, NULL);
2675 ctx->addr1_ht = NULL;
2676
2677 nir_foreach_instr (instr, nblock) {
2678 ctx->cur_instr = instr;
2679 emit_instr(ctx, instr);
2680 ctx->cur_instr = NULL;
2681 if (ctx->error)
2682 return;
2683 }
2684
2685 _mesa_hash_table_clear(ctx->sel_cond_conversions, NULL);
2686 }
2687
2688 static void emit_cf_list(struct ir3_context *ctx, struct exec_list *list);
2689
2690 static void
2691 emit_if(struct ir3_context *ctx, nir_if *nif)
2692 {
2693 struct ir3_instruction *condition = ir3_get_src(ctx, &nif->condition)[0];
2694
2695 ctx->block->condition = ir3_get_predicate(ctx, condition);
2696
2697 emit_cf_list(ctx, &nif->then_list);
2698 emit_cf_list(ctx, &nif->else_list);
2699 }
2700
2701 static void
2702 emit_loop(struct ir3_context *ctx, nir_loop *nloop)
2703 {
2704 emit_cf_list(ctx, &nloop->body);
2705 ctx->so->loops++;
2706 }
2707
2708 static void
2709 stack_push(struct ir3_context *ctx)
2710 {
2711 ctx->stack++;
2712 ctx->max_stack = MAX2(ctx->max_stack, ctx->stack);
2713 }
2714
2715 static void
2716 stack_pop(struct ir3_context *ctx)
2717 {
2718 compile_assert(ctx, ctx->stack > 0);
2719 ctx->stack--;
2720 }
2721
2722 static void
2723 emit_cf_list(struct ir3_context *ctx, struct exec_list *list)
2724 {
2725 foreach_list_typed (nir_cf_node, node, node, list) {
2726 switch (node->type) {
2727 case nir_cf_node_block:
2728 emit_block(ctx, nir_cf_node_as_block(node));
2729 break;
2730 case nir_cf_node_if:
2731 stack_push(ctx);
2732 emit_if(ctx, nir_cf_node_as_if(node));
2733 stack_pop(ctx);
2734 break;
2735 case nir_cf_node_loop:
2736 stack_push(ctx);
2737 emit_loop(ctx, nir_cf_node_as_loop(node));
2738 stack_pop(ctx);
2739 break;
2740 case nir_cf_node_function:
2741 ir3_context_error(ctx, "TODO\n");
2742 break;
2743 }
2744 }
2745 }
2746
2747 /* emit stream-out code. At this point, the current block is the original
2748 * (nir) end block, and nir ensures that all flow control paths terminate
2749 * into the end block. We re-purpose the original end block to generate
2750 * the 'if (vtxcnt < maxvtxcnt)' condition, then append the conditional
2751 * block holding stream-out write instructions, followed by the new end
2752 * block:
2753 *
2754 * blockOrigEnd {
2755 * p0.x = (vtxcnt < maxvtxcnt)
2756 * // succs: blockStreamOut, blockNewEnd
2757 * }
2758 * blockStreamOut {
2759 * // preds: blockOrigEnd
2760 * ... stream-out instructions ...
2761 * // succs: blockNewEnd
2762 * }
2763 * blockNewEnd {
2764 * // preds: blockOrigEnd, blockStreamOut
2765 * }
2766 */
2767 static void
2768 emit_stream_out(struct ir3_context *ctx)
2769 {
2770 struct ir3 *ir = ctx->ir;
2771 struct ir3_stream_output_info *strmout =
2772 &ctx->so->shader->stream_output;
2773 struct ir3_block *orig_end_block, *stream_out_block, *new_end_block;
2774 struct ir3_instruction *vtxcnt, *maxvtxcnt, *cond;
2775 struct ir3_instruction *bases[IR3_MAX_SO_BUFFERS];
2776
2777 /* create vtxcnt input in input block at top of shader,
2778 * so that it is seen as live over the entire duration
2779 * of the shader:
2780 */
2781 vtxcnt = create_sysval_input(ctx, SYSTEM_VALUE_VERTEX_CNT, 0x1);
2782 maxvtxcnt = create_driver_param(ctx, IR3_DP_VTXCNT_MAX);
2783
2784 /* at this point, we are at the original 'end' block,
2785 * re-purpose this block to stream-out condition, then
2786 * append stream-out block and new-end block
2787 */
2788 orig_end_block = ctx->block;
2789
2790 // maybe w/ store_global intrinsic, we could do this
2791 // stuff in nir->nir pass
2792
2793 stream_out_block = ir3_block_create(ir);
2794 list_addtail(&stream_out_block->node, &ir->block_list);
2795
2796 new_end_block = ir3_block_create(ir);
2797 list_addtail(&new_end_block->node, &ir->block_list);
2798
2799 orig_end_block->successors[0] = stream_out_block;
2800 orig_end_block->successors[1] = new_end_block;
2801
2802 stream_out_block->successors[0] = new_end_block;
2803 _mesa_set_add(stream_out_block->predecessors, orig_end_block);
2804
2805 _mesa_set_add(new_end_block->predecessors, orig_end_block);
2806 _mesa_set_add(new_end_block->predecessors, stream_out_block);
2807
2808 /* setup 'if (vtxcnt < maxvtxcnt)' condition: */
2809 cond = ir3_CMPS_S(ctx->block, vtxcnt, 0, maxvtxcnt, 0);
2810 cond->regs[0]->num = regid(REG_P0, 0);
2811 cond->regs[0]->flags &= ~IR3_REG_SSA;
2812 cond->cat2.condition = IR3_COND_LT;
2813
2814 /* condition goes on previous block to the conditional,
2815 * since it is used to pick which of the two successor
2816 * paths to take:
2817 */
2818 orig_end_block->condition = cond;
2819
2820 /* switch to stream_out_block to generate the stream-out
2821 * instructions:
2822 */
2823 ctx->block = stream_out_block;
2824
2825 /* Calculate base addresses based on vtxcnt. Instructions
2826 * generated for bases not used in following loop will be
2827 * stripped out in the backend.
2828 */
2829 for (unsigned i = 0; i < IR3_MAX_SO_BUFFERS; i++) {
2830 struct ir3_const_state *const_state = &ctx->so->shader->const_state;
2831 unsigned stride = strmout->stride[i];
2832 struct ir3_instruction *base, *off;
2833
2834 base = create_uniform(ctx->block, regid(const_state->offsets.tfbo, i));
2835
2836 /* 24-bit should be enough: */
2837 off = ir3_MUL_U24(ctx->block, vtxcnt, 0,
2838 create_immed(ctx->block, stride * 4), 0);
2839
2840 bases[i] = ir3_ADD_S(ctx->block, off, 0, base, 0);
2841 }
2842
2843 /* Generate the per-output store instructions: */
2844 for (unsigned i = 0; i < strmout->num_outputs; i++) {
2845 for (unsigned j = 0; j < strmout->output[i].num_components; j++) {
2846 unsigned c = j + strmout->output[i].start_component;
2847 struct ir3_instruction *base, *out, *stg;
2848
2849 base = bases[strmout->output[i].output_buffer];
2850 out = ctx->outputs[regid(strmout->output[i].register_index, c)];
2851
2852 stg = ir3_STG(ctx->block, base, 0, out, 0,
2853 create_immed(ctx->block, 1), 0);
2854 stg->cat6.type = TYPE_U32;
2855 stg->cat6.dst_offset = (strmout->output[i].dst_offset + j) * 4;
2856
2857 array_insert(ctx->block, ctx->block->keeps, stg);
2858 }
2859 }
2860
2861 /* and finally switch to the new_end_block: */
2862 ctx->block = new_end_block;
2863 }
2864
2865 static void
2866 emit_function(struct ir3_context *ctx, nir_function_impl *impl)
2867 {
2868 nir_metadata_require(impl, nir_metadata_block_index);
2869
2870 compile_assert(ctx, ctx->stack == 0);
2871
2872 emit_cf_list(ctx, &impl->body);
2873 emit_block(ctx, impl->end_block);
2874
2875 compile_assert(ctx, ctx->stack == 0);
2876
2877 /* at this point, we should have a single empty block,
2878 * into which we emit the 'end' instruction.
2879 */
2880 compile_assert(ctx, list_is_empty(&ctx->block->instr_list));
2881
2882 /* If stream-out (aka transform-feedback) enabled, emit the
2883 * stream-out instructions, followed by a new empty block (into
2884 * which the 'end' instruction lands).
2885 *
2886 * NOTE: it is done in this order, rather than inserting before
2887 * we emit end_block, because NIR guarantees that all blocks
2888 * flow into end_block, and that end_block has no successors.
2889 * So by re-purposing end_block as the first block of stream-
2890 * out, we guarantee that all exit paths flow into the stream-
2891 * out instructions.
2892 */
2893 if ((ctx->compiler->gpu_id < 500) &&
2894 (ctx->so->shader->stream_output.num_outputs > 0) &&
2895 !ctx->so->binning_pass) {
2896 debug_assert(ctx->so->type == MESA_SHADER_VERTEX);
2897 emit_stream_out(ctx);
2898 }
2899
2900 /* Vertex shaders in a tessellation or geometry pipeline treat END as a
2901 * NOP and has an epilogue that writes the VS outputs to local storage, to
2902 * be read by the HS. Then it resets execution mask (chmask) and chains
2903 * to the next shader (chsh).
2904 */
2905 if ((ctx->so->type == MESA_SHADER_VERTEX &&
2906 (ctx->so->key.has_gs || ctx->so->key.tessellation)) ||
2907 (ctx->so->type == MESA_SHADER_TESS_EVAL && ctx->so->key.has_gs)) {
2908 struct ir3_instruction *chmask =
2909 ir3_CHMASK(ctx->block);
2910 chmask->barrier_class = IR3_BARRIER_EVERYTHING;
2911 chmask->barrier_conflict = IR3_BARRIER_EVERYTHING;
2912
2913 struct ir3_instruction *chsh =
2914 ir3_CHSH(ctx->block);
2915 chsh->barrier_class = IR3_BARRIER_EVERYTHING;
2916 chsh->barrier_conflict = IR3_BARRIER_EVERYTHING;
2917 } else {
2918 ir3_END(ctx->block);
2919 }
2920 }
2921
2922 static void
2923 setup_input(struct ir3_context *ctx, nir_variable *in)
2924 {
2925 struct ir3_shader_variant *so = ctx->so;
2926 unsigned ncomp = glsl_get_components(in->type);
2927 unsigned n = in->data.driver_location;
2928 unsigned frac = in->data.location_frac;
2929 unsigned slot = in->data.location;
2930
2931 /* Inputs are loaded using ldlw or ldg for these stages. */
2932 if (ctx->so->type == MESA_SHADER_TESS_CTRL ||
2933 ctx->so->type == MESA_SHADER_TESS_EVAL ||
2934 ctx->so->type == MESA_SHADER_GEOMETRY)
2935 return;
2936
2937 /* skip unread inputs, we could end up with (for example), unsplit
2938 * matrix/etc inputs in the case they are not read, so just silently
2939 * skip these.
2940 */
2941 if (ncomp > 4)
2942 return;
2943
2944 so->inputs[n].slot = slot;
2945 so->inputs[n].compmask |= (1 << (ncomp + frac)) - 1;
2946 so->inputs_count = MAX2(so->inputs_count, n + 1);
2947 so->inputs[n].interpolate = in->data.interpolation;
2948
2949 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
2950
2951 /* if any varyings have 'sample' qualifer, that triggers us
2952 * to run in per-sample mode:
2953 */
2954 so->per_samp |= in->data.sample;
2955
2956 for (int i = 0; i < ncomp; i++) {
2957 struct ir3_instruction *instr = NULL;
2958 unsigned idx = (n * 4) + i + frac;
2959
2960 if (slot == VARYING_SLOT_POS) {
2961 ir3_context_error(ctx, "fragcoord should be a sysval!\n");
2962 } else {
2963 /* detect the special case for front/back colors where
2964 * we need to do flat vs smooth shading depending on
2965 * rast state:
2966 */
2967 if (in->data.interpolation == INTERP_MODE_NONE) {
2968 switch (slot) {
2969 case VARYING_SLOT_COL0:
2970 case VARYING_SLOT_COL1:
2971 case VARYING_SLOT_BFC0:
2972 case VARYING_SLOT_BFC1:
2973 so->inputs[n].rasterflat = true;
2974 break;
2975 default:
2976 break;
2977 }
2978 }
2979
2980 if (ctx->compiler->flat_bypass) {
2981 if ((so->inputs[n].interpolate == INTERP_MODE_FLAT) ||
2982 (so->inputs[n].rasterflat && ctx->so->key.rasterflat))
2983 so->inputs[n].use_ldlv = true;
2984 }
2985
2986 so->inputs[n].bary = true;
2987
2988 instr = create_frag_input(ctx, so->inputs[n].use_ldlv, idx);
2989 }
2990
2991 compile_assert(ctx, idx < ctx->ninputs);
2992
2993 ctx->inputs[idx] = instr;
2994 }
2995 } else if (ctx->so->type == MESA_SHADER_VERTEX) {
2996 struct ir3_instruction *input = NULL, *in;
2997 struct ir3_instruction *components[4];
2998 unsigned mask = (1 << (ncomp + frac)) - 1;
2999
3000 foreach_input (in, ctx->ir) {
3001 if (in->input.inidx == n) {
3002 input = in;
3003 break;
3004 }
3005 }
3006
3007 if (!input) {
3008 input = create_input(ctx, mask);
3009 input->input.inidx = n;
3010 } else {
3011 input->regs[0]->wrmask |= mask;
3012 }
3013
3014 ir3_split_dest(ctx->block, components, input, frac, ncomp);
3015
3016 for (int i = 0; i < ncomp; i++) {
3017 unsigned idx = (n * 4) + i + frac;
3018 compile_assert(ctx, idx < ctx->ninputs);
3019 ctx->inputs[idx] = components[i];
3020 }
3021 } else {
3022 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
3023 }
3024
3025 if (so->inputs[n].bary || (ctx->so->type == MESA_SHADER_VERTEX)) {
3026 so->total_in += ncomp;
3027 }
3028 }
3029
3030 /* Initially we assign non-packed inloc's for varyings, as we don't really
3031 * know up-front which components will be unused. After all the compilation
3032 * stages we scan the shader to see which components are actually used, and
3033 * re-pack the inlocs to eliminate unneeded varyings.
3034 */
3035 static void
3036 pack_inlocs(struct ir3_context *ctx)
3037 {
3038 struct ir3_shader_variant *so = ctx->so;
3039 uint8_t used_components[so->inputs_count];
3040
3041 memset(used_components, 0, sizeof(used_components));
3042
3043 /*
3044 * First Step: scan shader to find which bary.f/ldlv remain:
3045 */
3046
3047 foreach_block (block, &ctx->ir->block_list) {
3048 foreach_instr (instr, &block->instr_list) {
3049 if (is_input(instr)) {
3050 unsigned inloc = instr->regs[1]->iim_val;
3051 unsigned i = inloc / 4;
3052 unsigned j = inloc % 4;
3053
3054 compile_assert(ctx, instr->regs[1]->flags & IR3_REG_IMMED);
3055 compile_assert(ctx, i < so->inputs_count);
3056
3057 used_components[i] |= 1 << j;
3058 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
3059 for (int n = 0; n < 2; n++) {
3060 unsigned inloc = instr->prefetch.input_offset + n;
3061 unsigned i = inloc / 4;
3062 unsigned j = inloc % 4;
3063
3064 compile_assert(ctx, i < so->inputs_count);
3065
3066 used_components[i] |= 1 << j;
3067 }
3068 }
3069 }
3070 }
3071
3072 /*
3073 * Second Step: reassign varying inloc/slots:
3074 */
3075
3076 unsigned actual_in = 0;
3077 unsigned inloc = 0;
3078
3079 for (unsigned i = 0; i < so->inputs_count; i++) {
3080 unsigned compmask = 0, maxcomp = 0;
3081
3082 so->inputs[i].inloc = inloc;
3083 so->inputs[i].bary = false;
3084
3085 for (unsigned j = 0; j < 4; j++) {
3086 if (!(used_components[i] & (1 << j)))
3087 continue;
3088
3089 compmask |= (1 << j);
3090 actual_in++;
3091 maxcomp = j + 1;
3092
3093 /* at this point, since used_components[i] mask is only
3094 * considering varyings (ie. not sysvals) we know this
3095 * is a varying:
3096 */
3097 so->inputs[i].bary = true;
3098 }
3099
3100 if (so->inputs[i].bary) {
3101 so->varying_in++;
3102 so->inputs[i].compmask = (1 << maxcomp) - 1;
3103 inloc += maxcomp;
3104 }
3105 }
3106
3107 /*
3108 * Third Step: reassign packed inloc's:
3109 */
3110
3111 foreach_block (block, &ctx->ir->block_list) {
3112 foreach_instr (instr, &block->instr_list) {
3113 if (is_input(instr)) {
3114 unsigned inloc = instr->regs[1]->iim_val;
3115 unsigned i = inloc / 4;
3116 unsigned j = inloc % 4;
3117
3118 instr->regs[1]->iim_val = so->inputs[i].inloc + j;
3119 } else if (instr->opc == OPC_META_TEX_PREFETCH) {
3120 unsigned i = instr->prefetch.input_offset / 4;
3121 unsigned j = instr->prefetch.input_offset % 4;
3122 instr->prefetch.input_offset = so->inputs[i].inloc + j;
3123 }
3124 }
3125 }
3126 }
3127
3128 static void
3129 setup_output(struct ir3_context *ctx, nir_variable *out)
3130 {
3131 struct ir3_shader_variant *so = ctx->so;
3132 unsigned slots = glsl_count_vec4_slots(out->type, false, false);
3133 unsigned ncomp = glsl_get_components(glsl_without_array(out->type));
3134 unsigned n = out->data.driver_location;
3135 unsigned frac = out->data.location_frac;
3136 unsigned slot = out->data.location;
3137
3138 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3139 switch (slot) {
3140 case FRAG_RESULT_DEPTH:
3141 so->writes_pos = true;
3142 break;
3143 case FRAG_RESULT_COLOR:
3144 so->color0_mrt = 1;
3145 break;
3146 case FRAG_RESULT_SAMPLE_MASK:
3147 so->writes_smask = true;
3148 break;
3149 default:
3150 if (slot >= FRAG_RESULT_DATA0)
3151 break;
3152 ir3_context_error(ctx, "unknown FS output name: %s\n",
3153 gl_frag_result_name(slot));
3154 }
3155 } else if (ctx->so->type == MESA_SHADER_VERTEX ||
3156 ctx->so->type == MESA_SHADER_TESS_EVAL ||
3157 ctx->so->type == MESA_SHADER_GEOMETRY) {
3158 switch (slot) {
3159 case VARYING_SLOT_POS:
3160 so->writes_pos = true;
3161 break;
3162 case VARYING_SLOT_PSIZ:
3163 so->writes_psize = true;
3164 break;
3165 case VARYING_SLOT_PRIMITIVE_ID:
3166 case VARYING_SLOT_LAYER:
3167 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
3168 debug_assert(ctx->so->type == MESA_SHADER_GEOMETRY);
3169 /* fall through */
3170 case VARYING_SLOT_COL0:
3171 case VARYING_SLOT_COL1:
3172 case VARYING_SLOT_BFC0:
3173 case VARYING_SLOT_BFC1:
3174 case VARYING_SLOT_FOGC:
3175 case VARYING_SLOT_CLIP_DIST0:
3176 case VARYING_SLOT_CLIP_DIST1:
3177 case VARYING_SLOT_CLIP_VERTEX:
3178 break;
3179 default:
3180 if (slot >= VARYING_SLOT_VAR0)
3181 break;
3182 if ((VARYING_SLOT_TEX0 <= slot) && (slot <= VARYING_SLOT_TEX7))
3183 break;
3184 ir3_context_error(ctx, "unknown %s shader output name: %s\n",
3185 _mesa_shader_stage_to_string(ctx->so->type),
3186 gl_varying_slot_name(slot));
3187 }
3188 } else if (ctx->so->type == MESA_SHADER_TESS_CTRL) {
3189 /* output lowered to buffer writes. */
3190 return;
3191 } else {
3192 ir3_context_error(ctx, "unknown shader type: %d\n", ctx->so->type);
3193 }
3194
3195
3196 so->outputs_count = out->data.driver_location + slots;
3197 compile_assert(ctx, so->outputs_count < ARRAY_SIZE(so->outputs));
3198
3199 for (int i = 0; i < slots; i++) {
3200 int slot_base = n + i;
3201 so->outputs[slot_base].slot = slot + i;
3202
3203 for (int i = 0; i < ncomp; i++) {
3204 unsigned idx = (slot_base * 4) + i + frac;
3205 compile_assert(ctx, idx < ctx->noutputs);
3206 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
3207 }
3208
3209 /* if varying packing doesn't happen, we could end up in a situation
3210 * with "holes" in the output, and since the per-generation code that
3211 * sets up varying linkage registers doesn't expect to have more than
3212 * one varying per vec4 slot, pad the holes.
3213 *
3214 * Note that this should probably generate a performance warning of
3215 * some sort.
3216 */
3217 for (int i = 0; i < frac; i++) {
3218 unsigned idx = (slot_base * 4) + i;
3219 if (!ctx->outputs[idx]) {
3220 ctx->outputs[idx] = create_immed(ctx->block, fui(0.0));
3221 }
3222 }
3223 }
3224 }
3225
3226 static void
3227 emit_instructions(struct ir3_context *ctx)
3228 {
3229 nir_function_impl *fxn = nir_shader_get_entrypoint(ctx->s);
3230
3231 ctx->ninputs = ctx->s->num_inputs * 4;
3232 ctx->noutputs = ctx->s->num_outputs * 4;
3233 ctx->inputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->ninputs);
3234 ctx->outputs = rzalloc_array(ctx, struct ir3_instruction *, ctx->noutputs);
3235
3236 ctx->ir = ir3_create(ctx->compiler, ctx->so->type);
3237
3238 /* Create inputs in first block: */
3239 ctx->block = get_block(ctx, nir_start_block(fxn));
3240 ctx->in_block = ctx->block;
3241
3242 /* for fragment shader, the vcoord input register is used as the
3243 * base for bary.f varying fetch instrs:
3244 *
3245 * TODO defer creating ctx->ij_pixel and corresponding sysvals
3246 * until emit_intrinsic when we know they are actually needed.
3247 * For now, we defer creating ctx->ij_centroid, etc, since we
3248 * only need ij_pixel for "old style" varying inputs (ie.
3249 * tgsi_to_nir)
3250 */
3251 if (ctx->so->type == MESA_SHADER_FRAGMENT) {
3252 ctx->ij_pixel = create_input(ctx, 0x3);
3253 }
3254
3255 /* Setup inputs: */
3256 nir_foreach_variable (var, &ctx->s->inputs) {
3257 setup_input(ctx, var);
3258 }
3259
3260 /* Defer add_sysval_input() stuff until after setup_inputs(),
3261 * because sysvals need to be appended after varyings:
3262 */
3263 if (ctx->ij_pixel) {
3264 add_sysval_input_compmask(ctx, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL,
3265 0x3, ctx->ij_pixel);
3266 }
3267
3268
3269 /* Tesselation shaders always need primitive ID for indexing the
3270 * BO. Geometry shaders don't always need it but when they do it has be
3271 * delivered and unclobbered in the VS. To make things easy, we always
3272 * make room for it in VS/DS.
3273 */
3274 bool has_tess = ctx->so->key.tessellation != IR3_TESS_NONE;
3275 bool has_gs = ctx->so->key.has_gs;
3276 switch (ctx->so->type) {
3277 case MESA_SHADER_VERTEX:
3278 if (has_tess) {
3279 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3280 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3281 } else if (has_gs) {
3282 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3283 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3284 }
3285 break;
3286 case MESA_SHADER_TESS_CTRL:
3287 ctx->tcs_header = create_sysval_input(ctx, SYSTEM_VALUE_TCS_HEADER_IR3, 0x1);
3288 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3289 break;
3290 case MESA_SHADER_TESS_EVAL:
3291 if (has_gs)
3292 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3293 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3294 break;
3295 case MESA_SHADER_GEOMETRY:
3296 ctx->gs_header = create_sysval_input(ctx, SYSTEM_VALUE_GS_HEADER_IR3, 0x1);
3297 ctx->primitive_id = create_sysval_input(ctx, SYSTEM_VALUE_PRIMITIVE_ID, 0x1);
3298 break;
3299 default:
3300 break;
3301 }
3302
3303 /* Setup outputs: */
3304 nir_foreach_variable (var, &ctx->s->outputs) {
3305 setup_output(ctx, var);
3306 }
3307
3308 /* Find # of samplers: */
3309 nir_foreach_variable (var, &ctx->s->uniforms) {
3310 ctx->so->num_samp += glsl_type_get_sampler_count(var->type);
3311 /* just assume that we'll be reading from images.. if it
3312 * is write-only we don't have to count it, but not sure
3313 * if there is a good way to know?
3314 */
3315 ctx->so->num_samp += glsl_type_get_image_count(var->type);
3316 }
3317
3318 /* NOTE: need to do something more clever when we support >1 fxn */
3319 nir_foreach_register (reg, &fxn->registers) {
3320 ir3_declare_array(ctx, reg);
3321 }
3322 /* And emit the body: */
3323 ctx->impl = fxn;
3324 emit_function(ctx, fxn);
3325 }
3326
3327 /* Fixup tex sampler state for astc/srgb workaround instructions. We
3328 * need to assign the tex state indexes for these after we know the
3329 * max tex index.
3330 */
3331 static void
3332 fixup_astc_srgb(struct ir3_context *ctx)
3333 {
3334 struct ir3_shader_variant *so = ctx->so;
3335 /* indexed by original tex idx, value is newly assigned alpha sampler
3336 * state tex idx. Zero is invalid since there is at least one sampler
3337 * if we get here.
3338 */
3339 unsigned alt_tex_state[16] = {0};
3340 unsigned tex_idx = ctx->max_texture_index + 1;
3341 unsigned idx = 0;
3342
3343 so->astc_srgb.base = tex_idx;
3344
3345 for (unsigned i = 0; i < ctx->ir->astc_srgb_count; i++) {
3346 struct ir3_instruction *sam = ctx->ir->astc_srgb[i];
3347
3348 compile_assert(ctx, sam->cat5.tex < ARRAY_SIZE(alt_tex_state));
3349
3350 if (alt_tex_state[sam->cat5.tex] == 0) {
3351 /* assign new alternate/alpha tex state slot: */
3352 alt_tex_state[sam->cat5.tex] = tex_idx++;
3353 so->astc_srgb.orig_idx[idx++] = sam->cat5.tex;
3354 so->astc_srgb.count++;
3355 }
3356
3357 sam->cat5.tex = alt_tex_state[sam->cat5.tex];
3358 }
3359 }
3360
3361 static void
3362 fixup_binning_pass(struct ir3_context *ctx)
3363 {
3364 struct ir3_shader_variant *so = ctx->so;
3365 struct ir3 *ir = ctx->ir;
3366 unsigned i, j;
3367
3368 /* first pass, remove unused outputs from the IR level outputs: */
3369 for (i = 0, j = 0; i < ir->outputs_count; i++) {
3370 struct ir3_instruction *out = ir->outputs[i];
3371 assert(out->opc == OPC_META_COLLECT);
3372 unsigned outidx = out->collect.outidx;
3373 unsigned slot = so->outputs[outidx].slot;
3374
3375 /* throw away everything but first position/psize */
3376 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3377 ir->outputs[j] = ir->outputs[i];
3378 j++;
3379 }
3380 }
3381 ir->outputs_count = j;
3382
3383 /* second pass, cleanup the unused slots in ir3_shader_variant::outputs
3384 * table:
3385 */
3386 for (i = 0, j = 0; i < so->outputs_count; i++) {
3387 unsigned slot = so->outputs[i].slot;
3388
3389 /* throw away everything but first position/psize */
3390 if ((slot == VARYING_SLOT_POS) || (slot == VARYING_SLOT_PSIZ)) {
3391 so->outputs[j] = so->outputs[i];
3392
3393 /* fixup outidx to point to new output table entry: */
3394 struct ir3_instruction *out;
3395 foreach_output (out, ir) {
3396 if (out->collect.outidx == i) {
3397 out->collect.outidx = j;
3398 break;
3399 }
3400 }
3401
3402 j++;
3403 }
3404 }
3405 so->outputs_count = j;
3406 }
3407
3408 static void
3409 collect_tex_prefetches(struct ir3_context *ctx, struct ir3 *ir)
3410 {
3411 unsigned idx = 0;
3412
3413 /* Collect sampling instructions eligible for pre-dispatch. */
3414 foreach_block (block, &ir->block_list) {
3415 foreach_instr_safe (instr, &block->instr_list) {
3416 if (instr->opc == OPC_META_TEX_PREFETCH) {
3417 assert(idx < ARRAY_SIZE(ctx->so->sampler_prefetch));
3418 struct ir3_sampler_prefetch *fetch =
3419 &ctx->so->sampler_prefetch[idx];
3420 idx++;
3421
3422 if (instr->flags & IR3_INSTR_B) {
3423 fetch->cmd = IR3_SAMPLER_BINDLESS_PREFETCH_CMD;
3424 /* In bindless mode, the index is actually the base */
3425 fetch->tex_id = instr->prefetch.tex_base;
3426 fetch->samp_id = instr->prefetch.samp_base;
3427 fetch->tex_bindless_id = instr->prefetch.tex;
3428 fetch->samp_bindless_id = instr->prefetch.samp;
3429 } else {
3430 fetch->cmd = IR3_SAMPLER_PREFETCH_CMD;
3431 fetch->tex_id = instr->prefetch.tex;
3432 fetch->samp_id = instr->prefetch.samp;
3433 }
3434 fetch->wrmask = instr->regs[0]->wrmask;
3435 fetch->dst = instr->regs[0]->num;
3436 fetch->src = instr->prefetch.input_offset;
3437
3438 ctx->so->total_in =
3439 MAX2(ctx->so->total_in, instr->prefetch.input_offset + 2);
3440
3441 /* Disable half precision until supported. */
3442 fetch->half_precision = !!(instr->regs[0]->flags & IR3_REG_HALF);
3443
3444 /* Remove the prefetch placeholder instruction: */
3445 list_delinit(&instr->node);
3446 }
3447 }
3448 }
3449 }
3450
3451 int
3452 ir3_compile_shader_nir(struct ir3_compiler *compiler,
3453 struct ir3_shader_variant *so)
3454 {
3455 struct ir3_context *ctx;
3456 struct ir3 *ir;
3457 int ret = 0, max_bary;
3458
3459 assert(!so->ir);
3460
3461 ctx = ir3_context_init(compiler, so);
3462 if (!ctx) {
3463 DBG("INIT failed!");
3464 ret = -1;
3465 goto out;
3466 }
3467
3468 emit_instructions(ctx);
3469
3470 if (ctx->error) {
3471 DBG("EMIT failed!");
3472 ret = -1;
3473 goto out;
3474 }
3475
3476 ir = so->ir = ctx->ir;
3477
3478 assert((ctx->noutputs % 4) == 0);
3479
3480 /* Setup IR level outputs, which are "collects" that gather
3481 * the scalar components of outputs.
3482 */
3483 for (unsigned i = 0; i < ctx->noutputs; i += 4) {
3484 unsigned ncomp = 0;
3485 /* figure out the # of components written:
3486 *
3487 * TODO do we need to handle holes, ie. if .x and .z
3488 * components written, but .y component not written?
3489 */
3490 for (unsigned j = 0; j < 4; j++) {
3491 if (!ctx->outputs[i + j])
3492 break;
3493 ncomp++;
3494 }
3495
3496 /* Note that in some stages, like TCS, store_output is
3497 * lowered to memory writes, so no components of the
3498 * are "written" from the PoV of traditional store-
3499 * output instructions:
3500 */
3501 if (!ncomp)
3502 continue;
3503
3504 struct ir3_instruction *out =
3505 ir3_create_collect(ctx, &ctx->outputs[i], ncomp);
3506
3507 int outidx = i / 4;
3508 assert(outidx < so->outputs_count);
3509
3510 /* stash index into so->outputs[] so we can map the
3511 * output back to slot/etc later:
3512 */
3513 out->collect.outidx = outidx;
3514
3515 array_insert(ir, ir->outputs, out);
3516 }
3517
3518 /* Set up the gs header as an output for the vertex shader so it won't
3519 * clobber it for the tess ctrl shader.
3520 *
3521 * TODO this could probably be done more cleanly in a nir pass.
3522 */
3523 if (ctx->so->type == MESA_SHADER_VERTEX ||
3524 (ctx->so->key.has_gs && ctx->so->type == MESA_SHADER_TESS_EVAL)) {
3525 if (ctx->primitive_id) {
3526 unsigned n = so->outputs_count++;
3527 so->outputs[n].slot = VARYING_SLOT_PRIMITIVE_ID;
3528
3529 struct ir3_instruction *out =
3530 ir3_create_collect(ctx, &ctx->primitive_id, 1);
3531 out->collect.outidx = n;
3532 array_insert(ir, ir->outputs, out);
3533 }
3534
3535 if (ctx->gs_header) {
3536 unsigned n = so->outputs_count++;
3537 so->outputs[n].slot = VARYING_SLOT_GS_HEADER_IR3;
3538 struct ir3_instruction *out =
3539 ir3_create_collect(ctx, &ctx->gs_header, 1);
3540 out->collect.outidx = n;
3541 array_insert(ir, ir->outputs, out);
3542 }
3543
3544 if (ctx->tcs_header) {
3545 unsigned n = so->outputs_count++;
3546 so->outputs[n].slot = VARYING_SLOT_TCS_HEADER_IR3;
3547 struct ir3_instruction *out =
3548 ir3_create_collect(ctx, &ctx->tcs_header, 1);
3549 out->collect.outidx = n;
3550 array_insert(ir, ir->outputs, out);
3551 }
3552 }
3553
3554 /* at this point, for binning pass, throw away unneeded outputs: */
3555 if (so->binning_pass && (ctx->compiler->gpu_id < 600))
3556 fixup_binning_pass(ctx);
3557
3558 ir3_debug_print(ir, "BEFORE CF");
3559
3560 ir3_cf(ir);
3561
3562 ir3_debug_print(ir, "BEFORE CP");
3563
3564 ir3_cp(ir, so);
3565
3566 /* at this point, for binning pass, throw away unneeded outputs:
3567 * Note that for a6xx and later, we do this after ir3_cp to ensure
3568 * that the uniform/constant layout for BS and VS matches, so that
3569 * we can re-use same VS_CONST state group.
3570 */
3571 if (so->binning_pass && (ctx->compiler->gpu_id >= 600))
3572 fixup_binning_pass(ctx);
3573
3574 /* for a6xx+, binning and draw pass VS use same VBO state, so we
3575 * need to make sure not to remove any inputs that are used by
3576 * the nonbinning VS.
3577 */
3578 if (ctx->compiler->gpu_id >= 600 && so->binning_pass &&
3579 so->type == MESA_SHADER_VERTEX) {
3580 for (int i = 0; i < ctx->ninputs; i++) {
3581 struct ir3_instruction *in = ctx->inputs[i];
3582
3583 if (!in)
3584 continue;
3585
3586 unsigned n = i / 4;
3587 unsigned c = i % 4;
3588
3589 debug_assert(n < so->nonbinning->inputs_count);
3590
3591 if (so->nonbinning->inputs[n].sysval)
3592 continue;
3593
3594 /* be sure to keep inputs, even if only used in VS */
3595 if (so->nonbinning->inputs[n].compmask & (1 << c))
3596 array_insert(in->block, in->block->keeps, in);
3597 }
3598 }
3599
3600 ir3_debug_print(ir, "BEFORE GROUPING");
3601
3602 ir3_sched_add_deps(ir);
3603
3604 /* Group left/right neighbors, inserting mov's where needed to
3605 * solve conflicts:
3606 */
3607 ir3_group(ir);
3608
3609 ir3_debug_print(ir, "AFTER GROUPING");
3610
3611 ir3_dce(ir, so);
3612
3613 ir3_debug_print(ir, "AFTER DCE");
3614
3615 /* do Sethi–Ullman numbering before scheduling: */
3616 ir3_sun(ir);
3617
3618 ret = ir3_sched(ir);
3619 if (ret) {
3620 DBG("SCHED failed!");
3621 goto out;
3622 }
3623
3624 ir3_debug_print(ir, "AFTER SCHED");
3625
3626 /* Pre-assign VS inputs on a6xx+ binning pass shader, to align
3627 * with draw pass VS, so binning and draw pass can both use the
3628 * same VBO state.
3629 *
3630 * Note that VS inputs are expected to be full precision.
3631 */
3632 bool pre_assign_inputs = (ir->compiler->gpu_id >= 600) &&
3633 (ir->type == MESA_SHADER_VERTEX) &&
3634 so->binning_pass;
3635
3636 if (pre_assign_inputs) {
3637 for (unsigned i = 0; i < ctx->ninputs; i++) {
3638 struct ir3_instruction *instr = ctx->inputs[i];
3639
3640 if (!instr)
3641 continue;
3642
3643 unsigned n = i / 4;
3644 unsigned c = i % 4;
3645 unsigned regid = so->nonbinning->inputs[n].regid + c;
3646
3647 instr->regs[0]->num = regid;
3648 }
3649
3650 ret = ir3_ra(so, ctx->inputs, ctx->ninputs);
3651 } else if (ctx->tcs_header) {
3652 /* We need to have these values in the same registers between VS and TCS
3653 * since the VS chains to TCS and doesn't get the sysvals redelivered.
3654 */
3655
3656 ctx->tcs_header->regs[0]->num = regid(0, 0);
3657 ctx->primitive_id->regs[0]->num = regid(0, 1);
3658 struct ir3_instruction *precolor[] = { ctx->tcs_header, ctx->primitive_id };
3659 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3660 } else if (ctx->gs_header) {
3661 /* We need to have these values in the same registers between producer
3662 * (VS or DS) and GS since the producer chains to GS and doesn't get
3663 * the sysvals redelivered.
3664 */
3665
3666 ctx->gs_header->regs[0]->num = regid(0, 0);
3667 ctx->primitive_id->regs[0]->num = regid(0, 1);
3668 struct ir3_instruction *precolor[] = { ctx->gs_header, ctx->primitive_id };
3669 ret = ir3_ra(so, precolor, ARRAY_SIZE(precolor));
3670 } else if (so->num_sampler_prefetch) {
3671 assert(so->type == MESA_SHADER_FRAGMENT);
3672 struct ir3_instruction *instr, *precolor[2];
3673 int idx = 0;
3674
3675 foreach_input (instr, ir) {
3676 if (instr->input.sysval != SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL)
3677 continue;
3678
3679 assert(idx < ARRAY_SIZE(precolor));
3680
3681 precolor[idx] = instr;
3682 instr->regs[0]->num = idx;
3683
3684 idx++;
3685 }
3686 ret = ir3_ra(so, precolor, idx);
3687 } else {
3688 ret = ir3_ra(so, NULL, 0);
3689 }
3690
3691 if (ret) {
3692 DBG("RA failed!");
3693 goto out;
3694 }
3695
3696 ir3_postsched(ctx);
3697 ir3_debug_print(ir, "AFTER POSTSCHED");
3698
3699 if (compiler->gpu_id >= 600) {
3700 if (ir3_a6xx_fixup_atomic_dests(ir, so)) {
3701 ir3_debug_print(ir, "AFTER ATOMIC FIXUP");
3702 }
3703 }
3704
3705 if (so->type == MESA_SHADER_FRAGMENT)
3706 pack_inlocs(ctx);
3707
3708 /*
3709 * Fixup inputs/outputs to point to the actual registers assigned:
3710 *
3711 * 1) initialize to r63.x (invalid/unused)
3712 * 2) iterate IR level inputs/outputs and update the variants
3713 * inputs/outputs table based on the assigned registers for
3714 * the remaining inputs/outputs.
3715 */
3716
3717 for (unsigned i = 0; i < so->inputs_count; i++)
3718 so->inputs[i].regid = INVALID_REG;
3719 for (unsigned i = 0; i < so->outputs_count; i++)
3720 so->outputs[i].regid = INVALID_REG;
3721
3722 struct ir3_instruction *out;
3723 foreach_output (out, ir) {
3724 assert(out->opc == OPC_META_COLLECT);
3725 unsigned outidx = out->collect.outidx;
3726
3727 so->outputs[outidx].regid = out->regs[0]->num;
3728 so->outputs[outidx].half = !!(out->regs[0]->flags & IR3_REG_HALF);
3729 }
3730
3731 struct ir3_instruction *in;
3732 foreach_input (in, ir) {
3733 assert(in->opc == OPC_META_INPUT);
3734 unsigned inidx = in->input.inidx;
3735
3736 if (pre_assign_inputs && !so->inputs[inidx].sysval) {
3737 if (VALIDREG(so->nonbinning->inputs[inidx].regid)) {
3738 compile_assert(ctx, in->regs[0]->num ==
3739 so->nonbinning->inputs[inidx].regid);
3740 compile_assert(ctx, !!(in->regs[0]->flags & IR3_REG_HALF) ==
3741 so->nonbinning->inputs[inidx].half);
3742 }
3743 so->inputs[inidx].regid = so->nonbinning->inputs[inidx].regid;
3744 so->inputs[inidx].half = so->nonbinning->inputs[inidx].half;
3745 } else {
3746 so->inputs[inidx].regid = in->regs[0]->num;
3747 so->inputs[inidx].half = !!(in->regs[0]->flags & IR3_REG_HALF);
3748 }
3749 }
3750
3751 if (ctx->astc_srgb)
3752 fixup_astc_srgb(ctx);
3753
3754 /* We need to do legalize after (for frag shader's) the "bary.f"
3755 * offsets (inloc) have been assigned.
3756 */
3757 ir3_legalize(ir, so, &max_bary);
3758
3759 ir3_debug_print(ir, "AFTER LEGALIZE");
3760
3761 /* Set (ss)(sy) on first TCS and GEOMETRY instructions, since we don't
3762 * know what we might have to wait on when coming in from VS chsh.
3763 */
3764 if (so->type == MESA_SHADER_TESS_CTRL ||
3765 so->type == MESA_SHADER_GEOMETRY ) {
3766 foreach_block (block, &ir->block_list) {
3767 foreach_instr (instr, &block->instr_list) {
3768 instr->flags |= IR3_INSTR_SS | IR3_INSTR_SY;
3769 break;
3770 }
3771 }
3772 }
3773
3774 so->branchstack = ctx->max_stack;
3775
3776 /* Note that actual_in counts inputs that are not bary.f'd for FS: */
3777 if (so->type == MESA_SHADER_FRAGMENT)
3778 so->total_in = max_bary + 1;
3779
3780 so->max_sun = ir->max_sun;
3781
3782 /* Collect sampling instructions eligible for pre-dispatch. */
3783 collect_tex_prefetches(ctx, ir);
3784
3785 if (so->type == MESA_SHADER_FRAGMENT &&
3786 ctx->s->info.fs.needs_helper_invocations)
3787 so->need_pixlod = true;
3788
3789 out:
3790 if (ret) {
3791 if (so->ir)
3792 ir3_destroy(so->ir);
3793 so->ir = NULL;
3794 }
3795 ir3_context_free(ctx);
3796
3797 return ret;
3798 }