src/freedreno/ir3/ir3_context.h

   1 /*
   2  * Copyright (C) 2015-2018 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #ifndef IR3_CONTEXT_H_
  28 #define IR3_CONTEXT_H_
  29
  30 #include "ir3_nir.h"
  31 #include "ir3.h"
  32
  33 /* for conditionally setting boolean flag(s): */
  34 #define COND(bool, val) ((bool) ? (val) : 0)
  35
  36 #define DBG(fmt, ...) \
  37                 do { debug_printf("%s:%d: "fmt "\n", \
  38                                 __FUNCTION__, __LINE__, ##__VA_ARGS__); } while (0)
  39
  40 /**
  41  * The context for compilation of a single shader.
  42  */
  43 struct ir3_context {
  44         struct ir3_compiler *compiler;
  45
  46         struct nir_shader *s;
  47
  48         struct nir_instr *cur_instr;  /* current instruction, just for debug */
  49
  50         struct ir3 *ir;
  51         struct ir3_shader_variant *so;
  52
  53         struct ir3_block *block;      /* the current block */
  54         struct ir3_block *in_block;   /* block created for shader inputs */
  55
  56         nir_function_impl *impl;
  57
  58         /* For fragment shaders, varyings are not actual shader inputs,
  59          * instead the hw passes a varying-coord which is used with
  60          * bary.f.
  61          *
  62          * But NIR doesn't know that, it still declares varyings as
  63          * inputs.  So we do all the input tracking normally and fix
  64          * things up after compile_instructions()
  65          *
  66          * NOTE that frag_vcoord is the hardware position (possibly it
  67          * is actually an index or tag or some such.. it is *not*
  68          * values that can be directly used for gl_FragCoord..)
  69          */
  70         struct ir3_instruction *frag_vcoord;
  71
  72         /* for fragment shaders, for gl_FrontFacing and gl_FragCoord: */
  73         struct ir3_instruction *frag_face, *frag_coord;
  74
  75         /* For vertex shaders, keep track of the system values sources */
  76         struct ir3_instruction *vertex_id, *basevertex, *instance_id;
  77
  78         /* For fragment shaders: */
  79         struct ir3_instruction *samp_id, *samp_mask_in;
  80
  81         /* Compute shader inputs: */
  82         struct ir3_instruction *local_invocation_id, *work_group_id;
  83
  84         /* mapping from nir_register to defining instruction: */
  85         struct hash_table *def_ht;
  86
  87         unsigned num_arrays;
  88
  89         /* Tracking for max level of flowcontrol (branchstack) needed
  90          * by a5xx+:
  91          */
  92         unsigned stack, max_stack;
  93
  94         /* a common pattern for indirect addressing is to request the
  95          * same address register multiple times.  To avoid generating
  96          * duplicate instruction sequences (which our backend does not
  97          * try to clean up, since that should be done as the NIR stage)
  98          * we cache the address value generated for a given src value:
  99          *
 100          * Note that we have to cache these per alignment, since same
 101          * src used for an array of vec1 cannot be also used for an
 102          * array of vec4.
 103          */
 104         struct hash_table *addr_ht[4];
 105
 106         /* last dst array, for indirect we need to insert a var-store.
 107          */
 108         struct ir3_instruction **last_dst;
 109         unsigned last_dst_n;
 110
 111         /* maps nir_block to ir3_block, mostly for the purposes of
 112          * figuring out the blocks successors
 113          */
 114         struct hash_table *block_ht;
 115
 116         /* on a4xx, bitmask of samplers which need astc+srgb workaround: */
 117         unsigned astc_srgb;
 118
 119         unsigned samples;             /* bitmask of x,y sample shifts */
 120
 121         unsigned max_texture_index;
 122
 123         /* set if we encounter something we can't handle yet, so we
 124          * can bail cleanly and fallback to TGSI compiler f/e
 125          */
 126         bool error;
 127 };
 128
 129 struct ir3_context * ir3_context_init(struct ir3_compiler *compiler,
 130                 struct ir3_shader_variant *so);
 131 void ir3_context_free(struct ir3_context *ctx);
 132
 133 /* gpu pointer size in units of 32bit registers/slots */
 134 static inline
 135 unsigned ir3_pointer_size(struct ir3_context *ctx)
 136 {
 137         return (ctx->compiler->gpu_id >= 500) ? 2 : 1;
 138 }
 139
 140 struct ir3_instruction ** ir3_get_dst_ssa(struct ir3_context *ctx, nir_ssa_def *dst, unsigned n);
 141 struct ir3_instruction ** ir3_get_dst(struct ir3_context *ctx, nir_dest *dst, unsigned n);
 142 struct ir3_instruction * const * ir3_get_src(struct ir3_context *ctx, nir_src *src);
 143 void put_dst(struct ir3_context *ctx, nir_dest *dst);
 144 struct ir3_instruction * ir3_create_collect(struct ir3_context *ctx,
 145                 struct ir3_instruction *const *arr, unsigned arrsz);
 146 void ir3_split_dest(struct ir3_block *block, struct ir3_instruction **dst,
 147                 struct ir3_instruction *src, unsigned base, unsigned n);
 148
 149 void ir3_context_error(struct ir3_context *ctx, const char *format, ...);
 150
 151 #define compile_assert(ctx, cond) do { \
 152                 if (!(cond)) ir3_context_error((ctx), "failed assert: "#cond"\n"); \
 153         } while (0)
 154
 155 struct ir3_instruction * ir3_get_addr(struct ir3_context *ctx,
 156                 struct ir3_instruction *src, int align);
 157 struct ir3_instruction * ir3_get_predicate(struct ir3_context *ctx,
 158                 struct ir3_instruction *src);
 159
 160 void ir3_declare_array(struct ir3_context *ctx, nir_register *reg);
 161 struct ir3_array * ir3_get_array(struct ir3_context *ctx, nir_register *reg);
 162 struct ir3_instruction *ir3_create_array_load(struct ir3_context *ctx,
 163                 struct ir3_array *arr, int n, struct ir3_instruction *address);
 164 void ir3_create_array_store(struct ir3_context *ctx, struct ir3_array *arr, int n,
 165                 struct ir3_instruction *src, struct ir3_instruction *address);
 166
 167 static inline type_t utype_for_size(unsigned bit_size)
 168 {
 169         switch (bit_size) {
 170         case 32: return TYPE_U32;
 171         case 16: return TYPE_U16;
 172         case  8: return TYPE_U8;
 173         default: unreachable("bad bitsize"); return ~0;
 174         }
 175 }
 176
 177 static inline type_t utype_src(nir_src src)
 178 { return utype_for_size(nir_src_bit_size(src)); }
 179
 180 static inline type_t utype_dst(nir_dest dst)
 181 { return utype_for_size(nir_dest_bit_size(dst)); }
 182
 183 #endif /* IR3_CONTEXT_H_ */