2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
28 #include "util/half_float.h"
29 #include "util/u_math.h"
32 #include "ir3_compiler.h"
33 #include "ir3_shader.h"
36 do { __typeof(a) __tmp = (a); (a) = (b); (b) = __tmp; } while (0)
44 struct ir3_shader_variant
*so
;
48 /* is it a type preserving mov, with ok flags?
50 * @instr: the mov to consider removing
51 * @dst_instr: the instruction consuming the mov (instr)
53 * TODO maybe drop allow_flags since this is only false when dst is
56 static bool is_eligible_mov(struct ir3_instruction
*instr
,
57 struct ir3_instruction
*dst_instr
, bool allow_flags
)
59 if (is_same_type_mov(instr
)) {
60 struct ir3_register
*dst
= instr
->regs
[0];
61 struct ir3_register
*src
= instr
->regs
[1];
62 struct ir3_instruction
*src_instr
= ssa(src
);
64 /* only if mov src is SSA (not const/immed): */
69 if (dst
->flags
& IR3_REG_RELATIV
)
71 if (src
->flags
& IR3_REG_RELATIV
)
74 if (src
->flags
& IR3_REG_ARRAY
)
78 if (src
->flags
& (IR3_REG_FABS
| IR3_REG_FNEG
|
79 IR3_REG_SABS
| IR3_REG_SNEG
| IR3_REG_BNOT
))
82 /* If src is coming from fanout/split (ie. one component of a
83 * texture fetch, etc) and we have constraints on swizzle of
84 * destination, then skip it.
86 * We could possibly do a bit better, and copy-propagation if
87 * we can CP all components that are being fanned out.
89 if (src_instr
->opc
== OPC_META_SPLIT
) {
92 if (dst_instr
->opc
== OPC_META_COLLECT
)
94 if (dst_instr
->cp
.left
|| dst_instr
->cp
.right
)
103 /* propagate register flags from src to dst.. negates need special
104 * handling to cancel each other out.
106 static void combine_flags(unsigned *dstflags
, struct ir3_instruction
*src
)
108 unsigned srcflags
= src
->regs
[1]->flags
;
110 /* if what we are combining into already has (abs) flags,
111 * we can drop (neg) from src:
113 if (*dstflags
& IR3_REG_FABS
)
114 srcflags
&= ~IR3_REG_FNEG
;
115 if (*dstflags
& IR3_REG_SABS
)
116 srcflags
&= ~IR3_REG_SNEG
;
118 if (srcflags
& IR3_REG_FABS
)
119 *dstflags
|= IR3_REG_FABS
;
120 if (srcflags
& IR3_REG_SABS
)
121 *dstflags
|= IR3_REG_SABS
;
122 if (srcflags
& IR3_REG_FNEG
)
123 *dstflags
^= IR3_REG_FNEG
;
124 if (srcflags
& IR3_REG_SNEG
)
125 *dstflags
^= IR3_REG_SNEG
;
126 if (srcflags
& IR3_REG_BNOT
)
127 *dstflags
^= IR3_REG_BNOT
;
129 *dstflags
&= ~IR3_REG_SSA
;
130 *dstflags
|= srcflags
& IR3_REG_SSA
;
131 *dstflags
|= srcflags
& IR3_REG_CONST
;
132 *dstflags
|= srcflags
& IR3_REG_IMMED
;
133 *dstflags
|= srcflags
& IR3_REG_RELATIV
;
134 *dstflags
|= srcflags
& IR3_REG_ARRAY
;
135 *dstflags
|= srcflags
& IR3_REG_HIGH
;
137 /* if src of the src is boolean we can drop the (abs) since we know
138 * the source value is already a postitive integer. This cleans
139 * up the absnegs that get inserted when converting between nir and
140 * native boolean (see ir3_b2n/n2b)
142 struct ir3_instruction
*srcsrc
= ssa(src
->regs
[1]);
143 if (srcsrc
&& is_bool(srcsrc
))
144 *dstflags
&= ~IR3_REG_SABS
;
147 /* Tries lowering an immediate register argument to a const buffer access by
148 * adding to the list of immediates to be pushed to the const buffer when
149 * switching to this shader.
152 lower_immed(struct ir3_cp_ctx
*ctx
, struct ir3_instruction
*instr
, unsigned n
,
153 struct ir3_register
*reg
, unsigned new_flags
)
155 if (!(new_flags
& IR3_REG_IMMED
))
158 new_flags
&= ~IR3_REG_IMMED
;
159 new_flags
|= IR3_REG_CONST
;
161 if (!ir3_valid_flags(instr
, n
, new_flags
))
164 reg
= ir3_reg_clone(ctx
->shader
, reg
);
166 /* Half constant registers seems to handle only 32-bit values
167 * within floating-point opcodes. So convert back to 32-bit values.
169 bool f_opcode
= (is_cat2_float(instr
->opc
) ||
170 is_cat3_float(instr
->opc
)) ? true : false;
171 if (f_opcode
&& (new_flags
& IR3_REG_HALF
))
172 reg
->uim_val
= fui(_mesa_half_to_float(reg
->uim_val
));
174 /* in some cases, there are restrictions on (abs)/(neg) plus const..
175 * so just evaluate those and clear the flags:
177 if (new_flags
& IR3_REG_SABS
) {
178 reg
->iim_val
= abs(reg
->iim_val
);
179 new_flags
&= ~IR3_REG_SABS
;
182 if (new_flags
& IR3_REG_FABS
) {
183 reg
->fim_val
= fabs(reg
->fim_val
);
184 new_flags
&= ~IR3_REG_FABS
;
187 if (new_flags
& IR3_REG_SNEG
) {
188 reg
->iim_val
= -reg
->iim_val
;
189 new_flags
&= ~IR3_REG_SNEG
;
192 if (new_flags
& IR3_REG_FNEG
) {
193 reg
->fim_val
= -reg
->fim_val
;
194 new_flags
&= ~IR3_REG_FNEG
;
197 /* Reallocate for 4 more elements whenever it's necessary. Note that ir3
198 * printing relies on having groups of 4 dwords, so we fill the unused
199 * slots with a dummy value.
201 struct ir3_const_state
*const_state
= ir3_const_state(ctx
->so
);
202 if (const_state
->immediates_count
== const_state
->immediates_size
) {
203 const_state
->immediates
= rerzalloc(const_state
,
204 const_state
->immediates
,
205 __typeof__(const_state
->immediates
[0]),
206 const_state
->immediates_size
,
207 const_state
->immediates_size
+ 4);
208 const_state
->immediates_size
+= 4;
210 for (int i
= const_state
->immediates_count
; i
< const_state
->immediates_size
; i
++)
211 const_state
->immediates
[i
] = 0xd0d0d0d0;
215 for (i
= 0; i
< const_state
->immediates_count
; i
++) {
216 if (const_state
->immediates
[i
] == reg
->uim_val
)
220 if (i
== const_state
->immediates_count
) {
221 /* Add on a new immediate to be pushed, if we have space left in the
224 if (const_state
->offsets
.immediate
+ const_state
->immediates_count
/ 4 >=
225 ir3_max_const(ctx
->so
))
228 const_state
->immediates
[i
] = reg
->uim_val
;
229 const_state
->immediates_count
++;
232 reg
->flags
= new_flags
;
233 reg
->num
= i
+ (4 * const_state
->offsets
.immediate
);
235 instr
->regs
[n
+ 1] = reg
;
241 unuse(struct ir3_instruction
*instr
)
243 debug_assert(instr
->use_count
> 0);
245 if (--instr
->use_count
== 0) {
246 struct ir3_block
*block
= instr
->block
;
248 instr
->barrier_class
= 0;
249 instr
->barrier_conflict
= 0;
251 /* we don't want to remove anything in keeps (which could
252 * be things like array store's)
254 for (unsigned i
= 0; i
< block
->keeps_count
; i
++) {
255 debug_assert(block
->keeps
[i
] != instr
);
261 * Handles the special case of the 2nd src (n == 1) to "normal" mad
262 * instructions, which cannot reference a constant. See if it is
263 * possible to swap the 1st and 2nd sources.
266 try_swap_mad_two_srcs(struct ir3_instruction
*instr
, unsigned new_flags
)
268 if (!is_mad(instr
->opc
))
271 /* NOTE: pre-swap first two src's before valid_flags(),
272 * which might try to dereference the n'th src:
274 swap(instr
->regs
[0 + 1], instr
->regs
[1 + 1]);
276 /* cat3 doesn't encode immediate, but we can lower immediate
277 * to const if that helps:
279 if (new_flags
& IR3_REG_IMMED
) {
280 new_flags
&= ~IR3_REG_IMMED
;
281 new_flags
|= IR3_REG_CONST
;
285 /* can we propagate mov if we move 2nd src to first? */
286 ir3_valid_flags(instr
, 0, new_flags
) &&
287 /* and does first src fit in second slot? */
288 ir3_valid_flags(instr
, 1, instr
->regs
[1 + 1]->flags
);
291 /* put things back the way they were: */
292 swap(instr
->regs
[0 + 1], instr
->regs
[1 + 1]);
293 } /* otherwise leave things swapped */
299 * Handle cp for a given src register. This additionally handles
300 * the cases of collapsing immedate/const (which replace the src
301 * register with a non-ssa src) or collapsing mov's from relative
302 * src (which needs to also fixup the address src reference by the
306 reg_cp(struct ir3_cp_ctx
*ctx
, struct ir3_instruction
*instr
,
307 struct ir3_register
*reg
, unsigned n
)
309 struct ir3_instruction
*src
= ssa(reg
);
311 if (is_eligible_mov(src
, instr
, true)) {
312 /* simple case, no immed/const/relativ, only mov's w/ ssa src: */
313 struct ir3_register
*src_reg
= src
->regs
[1];
314 unsigned new_flags
= reg
->flags
;
316 combine_flags(&new_flags
, src
);
318 if (ir3_valid_flags(instr
, n
, new_flags
)) {
319 if (new_flags
& IR3_REG_ARRAY
) {
320 debug_assert(!(reg
->flags
& IR3_REG_ARRAY
));
321 reg
->array
= src_reg
->array
;
323 reg
->flags
= new_flags
;
324 reg
->instr
= ssa(src_reg
);
326 instr
->barrier_class
|= src
->barrier_class
;
327 instr
->barrier_conflict
|= src
->barrier_conflict
;
330 reg
->instr
->use_count
++;
334 } else if ((is_same_type_mov(src
) || is_const_mov(src
)) &&
335 /* cannot collapse const/immed/etc into meta instrs: */
337 /* immed/const/etc cases, which require some special handling: */
338 struct ir3_register
*src_reg
= src
->regs
[1];
339 unsigned new_flags
= reg
->flags
;
341 combine_flags(&new_flags
, src
);
343 if (!ir3_valid_flags(instr
, n
, new_flags
)) {
344 /* See if lowering an immediate to const would help. */
345 if (lower_immed(ctx
, instr
, n
, src_reg
, new_flags
))
348 /* special case for "normal" mad instructions, we can
349 * try swapping the first two args if that fits better.
351 * the "plain" MAD's (ie. the ones that don't shift first
352 * src prior to multiply) can swap their first two srcs if
353 * src[0] is !CONST and src[1] is CONST:
355 if ((n
== 1) && try_swap_mad_two_srcs(instr
, new_flags
)) {
362 /* Here we handle the special case of mov from
363 * CONST and/or RELATIV. These need to be handled
364 * specially, because in the case of move from CONST
365 * there is no src ir3_instruction so we need to
366 * replace the ir3_register. And in the case of
367 * RELATIV we need to handle the address register
370 if (src_reg
->flags
& IR3_REG_CONST
) {
371 /* an instruction cannot reference two different
374 if ((src_reg
->flags
& IR3_REG_RELATIV
) &&
375 conflicts(instr
->address
, reg
->instr
->address
))
378 /* This seems to be a hw bug, or something where the timings
379 * just somehow don't work out. This restriction may only
380 * apply if the first src is also CONST.
382 if ((opc_cat(instr
->opc
) == 3) && (n
== 2) &&
383 (src_reg
->flags
& IR3_REG_RELATIV
) &&
384 (src_reg
->array
.offset
== 0))
387 /* When narrowing constant from 32b to 16b, it seems
388 * to work only for float. So we should do this only with
391 if (src
->cat1
.dst_type
== TYPE_F16
) {
392 if (instr
->opc
== OPC_MOV
&& !type_float(instr
->cat1
.src_type
))
394 if (!is_cat2_float(instr
->opc
) && !is_cat3_float(instr
->opc
))
398 src_reg
= ir3_reg_clone(instr
->block
->shader
, src_reg
);
399 src_reg
->flags
= new_flags
;
400 instr
->regs
[n
+1] = src_reg
;
402 if (src_reg
->flags
& IR3_REG_RELATIV
)
403 ir3_instr_set_address(instr
, reg
->instr
->address
);
408 if ((src_reg
->flags
& IR3_REG_RELATIV
) &&
409 !conflicts(instr
->address
, reg
->instr
->address
)) {
410 src_reg
= ir3_reg_clone(instr
->block
->shader
, src_reg
);
411 src_reg
->flags
= new_flags
;
412 instr
->regs
[n
+1] = src_reg
;
413 ir3_instr_set_address(instr
, reg
->instr
->address
);
418 /* NOTE: seems we can only do immed integers, so don't
419 * need to care about float. But we do need to handle
420 * abs/neg *before* checking that the immediate requires
421 * few enough bits to encode:
423 * TODO: do we need to do something to avoid accidentally
424 * catching a float immed?
426 if (src_reg
->flags
& IR3_REG_IMMED
) {
427 int32_t iim_val
= src_reg
->iim_val
;
429 debug_assert((opc_cat(instr
->opc
) == 1) ||
430 (opc_cat(instr
->opc
) == 6) ||
431 ir3_cat2_int(instr
->opc
) ||
432 (is_mad(instr
->opc
) && (n
== 0)));
434 if (new_flags
& IR3_REG_SABS
)
435 iim_val
= abs(iim_val
);
437 if (new_flags
& IR3_REG_SNEG
)
440 if (new_flags
& IR3_REG_BNOT
)
443 /* other than category 1 (mov) we can only encode up to 10 bits: */
444 if (ir3_valid_flags(instr
, n
, new_flags
) &&
445 ((instr
->opc
== OPC_MOV
) ||
446 !((iim_val
& ~0x3ff) && (-iim_val
& ~0x3ff)))) {
447 new_flags
&= ~(IR3_REG_SABS
| IR3_REG_SNEG
| IR3_REG_BNOT
);
448 src_reg
= ir3_reg_clone(instr
->block
->shader
, src_reg
);
449 src_reg
->flags
= new_flags
;
450 src_reg
->iim_val
= iim_val
;
451 instr
->regs
[n
+1] = src_reg
;
454 } else if (lower_immed(ctx
, instr
, n
, src_reg
, new_flags
)) {
455 /* Fell back to loading the immediate as a const */
464 /* Handle special case of eliminating output mov, and similar cases where
465 * there isn't a normal "consuming" instruction. In this case we cannot
466 * collapse flags (ie. output mov from const, or w/ abs/neg flags, cannot
469 static struct ir3_instruction
*
470 eliminate_output_mov(struct ir3_cp_ctx
*ctx
, struct ir3_instruction
*instr
)
472 if (is_eligible_mov(instr
, NULL
, false)) {
473 struct ir3_register
*reg
= instr
->regs
[1];
474 if (!(reg
->flags
& IR3_REG_ARRAY
)) {
475 struct ir3_instruction
*src_instr
= ssa(reg
);
476 debug_assert(src_instr
);
477 ctx
->progress
= true;
485 * Find instruction src's which are mov's that can be collapsed, replacing
486 * the mov dst with the mov src
489 instr_cp(struct ir3_cp_ctx
*ctx
, struct ir3_instruction
*instr
)
491 if (instr
->regs_count
== 0)
494 if (ir3_instr_check_mark(instr
))
497 /* walk down the graph from each src: */
501 foreach_src_n (reg
, n
, instr
) {
502 struct ir3_instruction
*src
= ssa(reg
);
509 /* TODO non-indirect access we could figure out which register
510 * we actually want and allow cp..
512 if (reg
->flags
& IR3_REG_ARRAY
)
515 /* Don't CP absneg into meta instructions, that won't end well: */
516 if (is_meta(instr
) && (src
->opc
!= OPC_MOV
))
519 progress
|= reg_cp(ctx
, instr
, reg
, n
);
520 ctx
->progress
|= progress
;
524 if (instr
->regs
[0]->flags
& IR3_REG_ARRAY
) {
525 struct ir3_instruction
*src
= ssa(instr
->regs
[0]);
530 if (instr
->address
) {
531 instr_cp(ctx
, instr
->address
);
532 ir3_instr_set_address(instr
, eliminate_output_mov(ctx
, instr
->address
));
535 /* we can end up with extra cmps.s from frontend, which uses a
537 * cmps.s p0.x, cond, 0
539 * as a way to mov into the predicate register. But frequently 'cond'
540 * is itself a cmps.s/cmps.f/cmps.u. So detect this special case and
541 * just re-write the instruction writing predicate register to get rid
542 * of the double cmps.
544 if ((instr
->opc
== OPC_CMPS_S
) &&
545 (instr
->regs
[0]->num
== regid(REG_P0
, 0)) &&
546 ssa(instr
->regs
[1]) &&
547 (instr
->regs
[2]->flags
& IR3_REG_IMMED
) &&
548 (instr
->regs
[2]->iim_val
== 0) &&
549 (instr
->cat2
.condition
== IR3_COND_NE
)) {
550 struct ir3_instruction
*cond
= ssa(instr
->regs
[1]);
555 instr
->opc
= cond
->opc
;
556 instr
->flags
= cond
->flags
;
557 instr
->cat2
= cond
->cat2
;
558 ir3_instr_set_address(instr
, cond
->address
);
559 instr
->regs
[1] = cond
->regs
[1];
560 instr
->regs
[2] = cond
->regs
[2];
561 instr
->barrier_class
|= cond
->barrier_class
;
562 instr
->barrier_conflict
|= cond
->barrier_conflict
;
564 ctx
->progress
= true;
571 /* Handle converting a sam.s2en (taking samp/tex idx params via register)
572 * into a normal sam (encoding immediate samp/tex idx) if they are
573 * immediate. This saves some instructions and regs in the common case
574 * where we know samp/tex at compile time. This needs to be done in the
575 * frontend for bindless tex, though, so don't replicate it here.
577 if (is_tex(instr
) && (instr
->flags
& IR3_INSTR_S2EN
) &&
578 !(instr
->flags
& IR3_INSTR_B
) &&
579 !(ir3_shader_debug
& IR3_DBG_FORCES2EN
)) {
580 /* The first src will be a collect, if both of it's
581 * two sources are mov from imm, then we can
583 struct ir3_instruction
*samp_tex
= ssa(instr
->regs
[1]);
585 debug_assert(samp_tex
->opc
== OPC_META_COLLECT
);
587 struct ir3_instruction
*samp
= ssa(samp_tex
->regs
[1]);
588 struct ir3_instruction
*tex
= ssa(samp_tex
->regs
[2]);
590 if ((samp
->opc
== OPC_MOV
) &&
591 (samp
->regs
[1]->flags
& IR3_REG_IMMED
) &&
592 (tex
->opc
== OPC_MOV
) &&
593 (tex
->regs
[1]->flags
& IR3_REG_IMMED
)) {
594 instr
->flags
&= ~IR3_INSTR_S2EN
;
595 instr
->cat5
.samp
= samp
->regs
[1]->iim_val
;
596 instr
->cat5
.tex
= tex
->regs
[1]->iim_val
;
598 /* shuffle around the regs to remove the first src: */
600 for (unsigned i
= 1; i
< instr
->regs_count
; i
++) {
601 instr
->regs
[i
] = instr
->regs
[i
+ 1];
604 ctx
->progress
= true;
610 ir3_cp(struct ir3
*ir
, struct ir3_shader_variant
*so
)
612 struct ir3_cp_ctx ctx
= {
617 /* This is a bit annoying, and probably wouldn't be necessary if we
618 * tracked a reverse link from producing instruction to consumer.
619 * But we need to know when we've eliminated the last consumer of
620 * a mov, so we need to do a pass to first count consumers of a
623 foreach_block (block
, &ir
->block_list
) {
624 foreach_instr (instr
, &block
->instr_list
) {
626 /* by the way, we don't account for false-dep's, so the CP
627 * pass should always happen before false-dep's are inserted
629 debug_assert(instr
->deps_count
== 0);
631 foreach_ssa_src (src
, instr
) {
639 foreach_output_n (out
, n
, ir
) {
641 ir
->outputs
[n
] = eliminate_output_mov(&ctx
, out
);
644 foreach_block (block
, &ir
->block_list
) {
645 if (block
->condition
) {
646 instr_cp(&ctx
, block
->condition
);
647 block
->condition
= eliminate_output_mov(&ctx
, block
->condition
);
650 for (unsigned i
= 0; i
< block
->keeps_count
; i
++) {
651 instr_cp(&ctx
, block
->keeps
[i
]);
652 block
->keeps
[i
] = eliminate_output_mov(&ctx
, block
->keeps
[i
]);