src/freedreno/ir3/ir3_nir.c

   1 /*
   2  * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27
  28 #include "util/debug.h"
  29 #include "util/u_math.h"
  30
  31 #include "ir3_nir.h"
  32 #include "ir3_compiler.h"
  33 #include "ir3_shader.h"
  34
  35 static void ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir);
  36
  37 static const nir_shader_compiler_options options = {
  38                 .lower_fpow = true,
  39                 .lower_scmp = true,
  40                 .lower_flrp32 = true,
  41                 .lower_flrp64 = true,
  42                 .lower_ffract = true,
  43                 .lower_fmod = true,
  44                 .lower_fdiv = true,
  45                 .lower_isign = true,
  46                 .lower_ldexp = true,
  47                 .lower_uadd_carry = true,
  48                 .lower_mul_high = true,
  49                 .fuse_ffma = true,
  50                 .vertex_id_zero_based = true,
  51                 .lower_extract_byte = true,
  52                 .lower_extract_word = true,
  53                 .lower_all_io_to_elements = true,
  54                 .lower_helper_invocation = true,
  55                 .lower_bitfield_insert_to_shifts = true,
  56                 .lower_bitfield_extract_to_shifts = true,
  57                 .use_interpolated_input_intrinsics = true,
  58 };
  59
  60 /* we don't want to lower vertex_id to _zero_based on newer gpus: */
  61 static const nir_shader_compiler_options options_a6xx = {
  62                 .lower_fpow = true,
  63                 .lower_scmp = true,
  64                 .lower_flrp32 = true,
  65                 .lower_flrp64 = true,
  66                 .lower_ffract = true,
  67                 .lower_fmod = true,
  68                 .lower_fdiv = true,
  69                 .lower_isign = true,
  70                 .lower_ldexp = true,
  71                 .lower_uadd_carry = true,
  72                 .lower_mul_high = true,
  73                 .fuse_ffma = true,
  74                 .vertex_id_zero_based = false,
  75                 .lower_extract_byte = true,
  76                 .lower_extract_word = true,
  77                 .lower_all_io_to_elements = true,
  78                 .lower_helper_invocation = true,
  79                 .lower_bitfield_insert_to_shifts = true,
  80                 .lower_bitfield_extract_to_shifts = true,
  81                 .use_interpolated_input_intrinsics = true,
  82 };
  83
  84 const nir_shader_compiler_options *
  85 ir3_get_compiler_options(struct ir3_compiler *compiler)
  86 {
  87         if (compiler->gpu_id >= 600)
  88                 return &options_a6xx;
  89         return &options;
  90 }
  91
  92 /* for given shader key, are any steps handled in nir? */
  93 bool
  94 ir3_key_lowers_nir(const struct ir3_shader_key *key)
  95 {
  96         return key->fsaturate_s | key->fsaturate_t | key->fsaturate_r |
  97                         key->vsaturate_s | key->vsaturate_t | key->vsaturate_r |
  98                         key->ucp_enables | key->color_two_side |
  99                         key->fclamp_color | key->vclamp_color;
 100 }
 101
 102 #define OPT(nir, pass, ...) ({                             \
 103    bool this_progress = false;                             \
 104    NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__);      \
 105    this_progress;                                          \
 106 })
 107
 108 #define OPT_V(nir, pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
 109
 110 static void
 111 ir3_optimize_loop(nir_shader *s)
 112 {
 113         bool progress;
 114         unsigned lower_flrp =
 115                 (s->options->lower_flrp16 ? 16 : 0) |
 116                 (s->options->lower_flrp32 ? 32 : 0) |
 117                 (s->options->lower_flrp64 ? 64 : 0);
 118
 119         do {
 120                 progress = false;
 121
 122                 OPT_V(s, nir_lower_vars_to_ssa);
 123                 progress |= OPT(s, nir_opt_copy_prop_vars);
 124                 progress |= OPT(s, nir_opt_dead_write_vars);
 125                 progress |= OPT(s, nir_lower_alu_to_scalar, NULL);
 126                 progress |= OPT(s, nir_lower_phis_to_scalar);
 127
 128                 progress |= OPT(s, nir_copy_prop);
 129                 progress |= OPT(s, nir_opt_dce);
 130                 progress |= OPT(s, nir_opt_cse);
 131                 static int gcm = -1;
 132                 if (gcm == -1)
 133                         gcm = env_var_as_unsigned("GCM", 0);
 134                 if (gcm == 1)
 135                         progress |= OPT(s, nir_opt_gcm, true);
 136                 else if (gcm == 2)
 137                         progress |= OPT(s, nir_opt_gcm, false);
 138                 progress |= OPT(s, nir_opt_peephole_select, 16, true, true);
 139                 progress |= OPT(s, nir_opt_intrinsics);
 140                 progress |= OPT(s, nir_opt_algebraic);
 141                 progress |= OPT(s, nir_opt_constant_folding);
 142
 143                 if (lower_flrp != 0) {
 144                         if (OPT(s, nir_lower_flrp,
 145                                         lower_flrp,
 146                                         false /* always_precise */,
 147                                         s->options->lower_ffma)) {
 148                                 OPT(s, nir_opt_constant_folding);
 149                                 progress = true;
 150                         }
 151
 152                         /* Nothing should rematerialize any flrps, so we only
 153                          * need to do this lowering once.
 154                          */
 155                         lower_flrp = 0;
 156                 }
 157
 158                 progress |= OPT(s, nir_opt_dead_cf);
 159                 if (OPT(s, nir_opt_trivial_continues)) {
 160                         progress |= true;
 161                         /* If nir_opt_trivial_continues makes progress, then we need to clean
 162                          * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
 163                          * to make progress.
 164                          */
 165                         OPT(s, nir_copy_prop);
 166                         OPT(s, nir_opt_dce);
 167                 }
 168                 progress |= OPT(s, nir_opt_if, false);
 169                 progress |= OPT(s, nir_opt_remove_phis);
 170                 progress |= OPT(s, nir_opt_undef);
 171
 172         } while (progress);
 173 }
 174
 175 void
 176 ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
 177                 const struct ir3_shader_key *key)
 178 {
 179         struct nir_lower_tex_options tex_options = {
 180                         .lower_rect = 0,
 181                         .lower_tg4_offsets = true,
 182         };
 183
 184         if (key) {
 185                 switch (shader->type) {
 186                 case MESA_SHADER_FRAGMENT:
 187                         tex_options.saturate_s = key->fsaturate_s;
 188                         tex_options.saturate_t = key->fsaturate_t;
 189                         tex_options.saturate_r = key->fsaturate_r;
 190                         break;
 191                 case MESA_SHADER_VERTEX:
 192                         tex_options.saturate_s = key->vsaturate_s;
 193                         tex_options.saturate_t = key->vsaturate_t;
 194                         tex_options.saturate_r = key->vsaturate_r;
 195                         break;
 196                 default:
 197                         /* TODO */
 198                         break;
 199                 }
 200         }
 201
 202         if (shader->compiler->gpu_id >= 400) {
 203                 /* a4xx seems to have *no* sam.p */
 204                 tex_options.lower_txp = ~0;  /* lower all txp */
 205         } else {
 206                 /* a3xx just needs to avoid sam.p for 3d tex */
 207                 tex_options.lower_txp = (1 << GLSL_SAMPLER_DIM_3D);
 208         }
 209
 210         if (ir3_shader_debug & IR3_DBG_DISASM) {
 211                 debug_printf("----------------------\n");
 212                 nir_print_shader(s, stdout);
 213                 debug_printf("----------------------\n");
 214         }
 215
 216         OPT_V(s, nir_lower_regs_to_ssa);
 217         OPT_V(s, ir3_nir_lower_io_offsets);
 218
 219         if (key) {
 220                 if (s->info.stage == MESA_SHADER_VERTEX) {
 221                         OPT_V(s, nir_lower_clip_vs, key->ucp_enables, false);
 222                         if (key->vclamp_color)
 223                                 OPT_V(s, nir_lower_clamp_color_outputs);
 224                 } else if (s->info.stage == MESA_SHADER_FRAGMENT) {
 225                         OPT_V(s, nir_lower_clip_fs, key->ucp_enables);
 226                         if (key->fclamp_color)
 227                                 OPT_V(s, nir_lower_clamp_color_outputs);
 228                 }
 229                 if (key->color_two_side) {
 230                         OPT_V(s, nir_lower_two_sided_color);
 231                 }
 232         } else {
 233                 /* only want to do this the first time (when key is null)
 234                  * and not again on any potential 2nd variant lowering pass:
 235                  */
 236                 OPT_V(s, ir3_nir_apply_trig_workarounds);
 237
 238                 /* This wouldn't hurt to run multiple times, but there is
 239                  * no need to:
 240                  */
 241                 if (shader->type == MESA_SHADER_FRAGMENT)
 242                         OPT_V(s, nir_lower_fb_read);
 243         }
 244
 245         OPT_V(s, nir_lower_tex, &tex_options);
 246         OPT_V(s, nir_lower_load_const_to_scalar);
 247         if (shader->compiler->gpu_id < 500)
 248                 OPT_V(s, ir3_nir_lower_tg4_to_tex);
 249
 250         ir3_optimize_loop(s);
 251
 252         /* do ubo load and idiv lowering after first opt loop to get a chance to
 253          * propagate constants for divide by immed power-of-two and constant ubo
 254          * block/offsets:
 255          *
 256          * NOTE that UBO analysis pass should only be done once, before variants
 257          */
 258         const bool ubo_progress = !key && OPT(s, ir3_nir_analyze_ubo_ranges, shader);
 259         const bool idiv_progress = OPT(s, nir_lower_idiv);
 260         if (ubo_progress || idiv_progress)
 261                 ir3_optimize_loop(s);
 262
 263         OPT_V(s, nir_remove_dead_variables, nir_var_function_temp);
 264
 265         OPT_V(s, nir_move_load_const);
 266
 267         if (ir3_shader_debug & IR3_DBG_DISASM) {
 268                 debug_printf("----------------------\n");
 269                 nir_print_shader(s, stdout);
 270                 debug_printf("----------------------\n");
 271         }
 272
 273         nir_sweep(s);
 274
 275         /* The first time thru, when not creating variant, do the one-time
 276          * const_state layout setup.  This should be done after ubo range
 277          * analysis.
 278          */
 279         if (!key) {
 280                 ir3_setup_const_state(shader, s);
 281         }
 282 }
 283
 284 static void
 285 ir3_nir_scan_driver_consts(nir_shader *shader,
 286                 struct ir3_const_state *layout)
 287 {
 288         nir_foreach_function(function, shader) {
 289                 if (!function->impl)
 290                         continue;
 291
 292                 nir_foreach_block(block, function->impl) {
 293                         nir_foreach_instr(instr, block) {
 294                                 if (instr->type != nir_instr_type_intrinsic)
 295                                         continue;
 296
 297                                 nir_intrinsic_instr *intr =
 298                                         nir_instr_as_intrinsic(instr);
 299                                 unsigned idx;
 300
 301                                 switch (intr->intrinsic) {
 302                                 case nir_intrinsic_get_buffer_size:
 303                                         idx = nir_src_as_uint(intr->src[0]);
 304                                         if (layout->ssbo_size.mask & (1 << idx))
 305                                                 break;
 306                                         layout->ssbo_size.mask |= (1 << idx);
 307                                         layout->ssbo_size.off[idx] =
 308                                                 layout->ssbo_size.count;
 309                                         layout->ssbo_size.count += 1; /* one const per */
 310                                         break;
 311                                 case nir_intrinsic_image_deref_atomic_add:
 312                                 case nir_intrinsic_image_deref_atomic_min:
 313                                 case nir_intrinsic_image_deref_atomic_max:
 314                                 case nir_intrinsic_image_deref_atomic_and:
 315                                 case nir_intrinsic_image_deref_atomic_or:
 316                                 case nir_intrinsic_image_deref_atomic_xor:
 317                                 case nir_intrinsic_image_deref_atomic_exchange:
 318                                 case nir_intrinsic_image_deref_atomic_comp_swap:
 319                                 case nir_intrinsic_image_deref_store:
 320                                 case nir_intrinsic_image_deref_size:
 321                                         idx = nir_intrinsic_get_var(intr, 0)->data.driver_location;
 322                                         if (layout->image_dims.mask & (1 << idx))
 323                                                 break;
 324                                         layout->image_dims.mask |= (1 << idx);
 325                                         layout->image_dims.off[idx] =
 326                                                 layout->image_dims.count;
 327                                         layout->image_dims.count += 3; /* three const per */
 328                                         break;
 329                                 case nir_intrinsic_load_ubo:
 330                                         if (nir_src_is_const(intr->src[0])) {
 331                                                 layout->num_ubos = MAX2(layout->num_ubos,
 332                                                                 nir_src_as_uint(intr->src[0]) + 1);
 333                                         } else {
 334                                                 layout->num_ubos = shader->info.num_ubos;
 335                                         }
 336                                 default:
 337                                         break;
 338                                 }
 339                         }
 340                 }
 341         }
 342 }
 343
 344 static void
 345 ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir)
 346 {
 347         struct ir3_compiler *compiler = shader->compiler;
 348         struct ir3_const_state *const_state = &shader->const_state;
 349
 350         memset(&const_state->offsets, ~0, sizeof(const_state->offsets));
 351
 352         ir3_nir_scan_driver_consts(nir, const_state);
 353
 354         debug_assert((shader->ubo_state.size % 16) == 0);
 355         unsigned constoff = align(shader->ubo_state.size / 16, 4);
 356         unsigned ptrsz = ir3_pointer_size(compiler);
 357
 358         if (const_state->num_ubos > 0) {
 359                 const_state->offsets.ubo = constoff;
 360                 constoff += align(nir->info.num_ubos * ptrsz, 4) / 4;
 361         }
 362
 363         if (const_state->ssbo_size.count > 0) {
 364                 unsigned cnt = const_state->ssbo_size.count;
 365                 const_state->offsets.ssbo_sizes = constoff;
 366                 constoff += align(cnt, 4) / 4;
 367         }
 368
 369         if (const_state->image_dims.count > 0) {
 370                 unsigned cnt = const_state->image_dims.count;
 371                 const_state->offsets.image_dims = constoff;
 372                 constoff += align(cnt, 4) / 4;
 373         }
 374
 375         unsigned num_driver_params = 0;
 376         if (shader->type == MESA_SHADER_VERTEX) {
 377                 num_driver_params = IR3_DP_VS_COUNT;
 378         } else if (shader->type == MESA_SHADER_COMPUTE) {
 379                 num_driver_params = IR3_DP_CS_COUNT;
 380         }
 381
 382         const_state->offsets.driver_param = constoff;
 383         constoff += align(num_driver_params, 4) / 4;
 384
 385         if ((shader->type == MESA_SHADER_VERTEX) &&
 386                         (compiler->gpu_id < 500) &&
 387                         shader->stream_output.num_outputs > 0) {
 388                 const_state->offsets.tfbo = constoff;
 389                 constoff += align(IR3_MAX_SO_BUFFERS * ptrsz, 4) / 4;
 390         }
 391
 392         const_state->offsets.immediate = constoff;
 393 }