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[mesa.git] / src / freedreno / ir3 / ir3_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27
28 #include "util/debug.h"
29 #include "util/u_math.h"
30
31 #include "ir3_nir.h"
32 #include "ir3_compiler.h"
33 #include "ir3_shader.h"
34
35 static const nir_shader_compiler_options options = {
36 .lower_fpow = true,
37 .lower_scmp = true,
38 .lower_flrp16 = true,
39 .lower_flrp32 = true,
40 .lower_flrp64 = true,
41 .lower_ffract = true,
42 .lower_fmod = true,
43 .lower_fdiv = true,
44 .lower_isign = true,
45 .lower_ldexp = true,
46 .lower_uadd_carry = true,
47 .lower_usub_borrow = true,
48 .lower_mul_high = true,
49 .lower_mul_2x32_64 = true,
50 .fuse_ffma = true,
51 .vertex_id_zero_based = true,
52 .lower_extract_byte = true,
53 .lower_extract_word = true,
54 .lower_all_io_to_elements = true,
55 .lower_helper_invocation = true,
56 .lower_bitfield_insert_to_shifts = true,
57 .lower_bitfield_extract_to_shifts = true,
58 .lower_pack_half_2x16 = true,
59 .lower_pack_snorm_4x8 = true,
60 .lower_pack_snorm_2x16 = true,
61 .lower_pack_unorm_4x8 = true,
62 .lower_pack_unorm_2x16 = true,
63 .lower_unpack_half_2x16 = true,
64 .lower_unpack_snorm_4x8 = true,
65 .lower_unpack_snorm_2x16 = true,
66 .lower_unpack_unorm_4x8 = true,
67 .lower_unpack_unorm_2x16 = true,
68 .lower_pack_split = true,
69 .use_interpolated_input_intrinsics = true,
70 .lower_rotate = true,
71 .lower_to_scalar = true,
72 .has_imul24 = true,
73 .lower_wpos_pntc = true,
74 .lower_cs_local_index_from_id = true,
75
76 /* Only needed for the spirv_to_nir() pass done in ir3_cmdline.c
77 * but that should be harmless for GL since 64b is not
78 * supported there.
79 */
80 .lower_int64_options = (nir_lower_int64_options)~0,
81 };
82
83 /* we don't want to lower vertex_id to _zero_based on newer gpus: */
84 static const nir_shader_compiler_options options_a6xx = {
85 .lower_fpow = true,
86 .lower_scmp = true,
87 .lower_flrp16 = true,
88 .lower_flrp32 = true,
89 .lower_flrp64 = true,
90 .lower_ffract = true,
91 .lower_fmod = true,
92 .lower_fdiv = true,
93 .lower_isign = true,
94 .lower_ldexp = true,
95 .lower_uadd_carry = true,
96 .lower_usub_borrow = true,
97 .lower_mul_high = true,
98 .lower_mul_2x32_64 = true,
99 .fuse_ffma = true,
100 .vertex_id_zero_based = false,
101 .lower_extract_byte = true,
102 .lower_extract_word = true,
103 .lower_all_io_to_elements = true,
104 .lower_helper_invocation = true,
105 .lower_bitfield_insert_to_shifts = true,
106 .lower_bitfield_extract_to_shifts = true,
107 .lower_pack_half_2x16 = true,
108 .lower_pack_snorm_4x8 = true,
109 .lower_pack_snorm_2x16 = true,
110 .lower_pack_unorm_4x8 = true,
111 .lower_pack_unorm_2x16 = true,
112 .lower_unpack_half_2x16 = true,
113 .lower_unpack_snorm_4x8 = true,
114 .lower_unpack_snorm_2x16 = true,
115 .lower_unpack_unorm_4x8 = true,
116 .lower_unpack_unorm_2x16 = true,
117 .lower_pack_split = true,
118 .use_interpolated_input_intrinsics = true,
119 .lower_rotate = true,
120 .vectorize_io = true,
121 .lower_to_scalar = true,
122 .has_imul24 = true,
123 .max_unroll_iterations = 32,
124 .lower_wpos_pntc = true,
125 .lower_cs_local_index_from_id = true,
126
127 /* Only needed for the spirv_to_nir() pass done in ir3_cmdline.c
128 * but that should be harmless for GL since 64b is not
129 * supported there.
130 */
131 .lower_int64_options = (nir_lower_int64_options)~0,
132 };
133
134 const nir_shader_compiler_options *
135 ir3_get_compiler_options(struct ir3_compiler *compiler)
136 {
137 if (compiler->gpu_id >= 600)
138 return &options_a6xx;
139 return &options;
140 }
141
142 #define OPT(nir, pass, ...) ({ \
143 bool this_progress = false; \
144 NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__); \
145 this_progress; \
146 })
147
148 #define OPT_V(nir, pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
149
150 static void
151 ir3_optimize_loop(nir_shader *s)
152 {
153 bool progress;
154 unsigned lower_flrp =
155 (s->options->lower_flrp16 ? 16 : 0) |
156 (s->options->lower_flrp32 ? 32 : 0) |
157 (s->options->lower_flrp64 ? 64 : 0);
158
159 do {
160 progress = false;
161
162 OPT_V(s, nir_lower_vars_to_ssa);
163 progress |= OPT(s, nir_opt_copy_prop_vars);
164 progress |= OPT(s, nir_opt_dead_write_vars);
165 progress |= OPT(s, nir_lower_alu_to_scalar, NULL, NULL);
166 progress |= OPT(s, nir_lower_phis_to_scalar);
167
168 progress |= OPT(s, nir_copy_prop);
169 progress |= OPT(s, nir_opt_dce);
170 progress |= OPT(s, nir_opt_cse);
171 static int gcm = -1;
172 if (gcm == -1)
173 gcm = env_var_as_unsigned("GCM", 0);
174 if (gcm == 1)
175 progress |= OPT(s, nir_opt_gcm, true);
176 else if (gcm == 2)
177 progress |= OPT(s, nir_opt_gcm, false);
178 progress |= OPT(s, nir_opt_peephole_select, 16, true, true);
179 progress |= OPT(s, nir_opt_intrinsics);
180 progress |= OPT(s, nir_opt_algebraic);
181 progress |= OPT(s, nir_lower_alu);
182 progress |= OPT(s, nir_lower_pack);
183 progress |= OPT(s, nir_opt_constant_folding);
184
185 if (lower_flrp != 0) {
186 if (OPT(s, nir_lower_flrp,
187 lower_flrp,
188 false /* always_precise */,
189 s->options->lower_ffma)) {
190 OPT(s, nir_opt_constant_folding);
191 progress = true;
192 }
193
194 /* Nothing should rematerialize any flrps, so we only
195 * need to do this lowering once.
196 */
197 lower_flrp = 0;
198 }
199
200 progress |= OPT(s, nir_opt_dead_cf);
201 if (OPT(s, nir_opt_trivial_continues)) {
202 progress |= true;
203 /* If nir_opt_trivial_continues makes progress, then we need to clean
204 * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
205 * to make progress.
206 */
207 OPT(s, nir_copy_prop);
208 OPT(s, nir_opt_dce);
209 }
210 progress |= OPT(s, nir_opt_if, false);
211 progress |= OPT(s, nir_opt_loop_unroll, nir_var_all);
212 progress |= OPT(s, nir_opt_remove_phis);
213 progress |= OPT(s, nir_opt_undef);
214 } while (progress);
215 }
216
217 static bool
218 should_split_wrmask(const nir_instr *instr, const void *data)
219 {
220 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
221
222 switch (intr->intrinsic) {
223 case nir_intrinsic_store_ssbo:
224 case nir_intrinsic_store_shared:
225 case nir_intrinsic_store_global:
226 return true;
227 default:
228 return false;
229 }
230 }
231
232 void
233 ir3_finalize_nir(struct ir3_compiler *compiler, nir_shader *s)
234 {
235 struct nir_lower_tex_options tex_options = {
236 .lower_rect = 0,
237 .lower_tg4_offsets = true,
238 };
239
240 if (compiler->gpu_id >= 400) {
241 /* a4xx seems to have *no* sam.p */
242 tex_options.lower_txp = ~0; /* lower all txp */
243 } else {
244 /* a3xx just needs to avoid sam.p for 3d tex */
245 tex_options.lower_txp = (1 << GLSL_SAMPLER_DIM_3D);
246 }
247
248 if (ir3_shader_debug & IR3_DBG_DISASM) {
249 debug_printf("----------------------\n");
250 nir_print_shader(s, stdout);
251 debug_printf("----------------------\n");
252 }
253
254 if (s->info.stage == MESA_SHADER_GEOMETRY)
255 NIR_PASS_V(s, ir3_nir_lower_gs);
256
257 NIR_PASS_V(s, nir_lower_io_arrays_to_elements_no_indirects, false);
258
259 NIR_PASS_V(s, nir_lower_amul, ir3_glsl_type_size);
260
261 OPT_V(s, nir_lower_regs_to_ssa);
262 OPT_V(s, nir_lower_wrmasks, should_split_wrmask, s);
263
264 OPT_V(s, nir_lower_tex, &tex_options);
265 OPT_V(s, nir_lower_load_const_to_scalar);
266 if (compiler->gpu_id < 500)
267 OPT_V(s, ir3_nir_lower_tg4_to_tex);
268
269 ir3_optimize_loop(s);
270
271 /* do idiv lowering after first opt loop to get a chance to propagate
272 * constants for divide by immed power-of-two:
273 */
274 const bool idiv_progress = OPT(s, nir_lower_idiv, nir_lower_idiv_fast);
275
276 if (idiv_progress)
277 ir3_optimize_loop(s);
278
279 OPT_V(s, nir_remove_dead_variables, nir_var_function_temp, NULL);
280
281 if (ir3_shader_debug & IR3_DBG_DISASM) {
282 debug_printf("----------------------\n");
283 nir_print_shader(s, stdout);
284 debug_printf("----------------------\n");
285 }
286
287 nir_sweep(s);
288 }
289
290 /**
291 * Late passes that need to be done after pscreen->finalize_nir()
292 */
293 void
294 ir3_nir_post_finalize(struct ir3_compiler *compiler, nir_shader *s)
295 {
296 NIR_PASS_V(s, nir_lower_io, nir_var_shader_in | nir_var_shader_out,
297 ir3_glsl_type_size, (nir_lower_io_options)0);
298
299 if (s->info.stage == MESA_SHADER_FRAGMENT) {
300 /* NOTE: lower load_barycentric_at_sample first, since it
301 * produces load_barycentric_at_offset:
302 */
303 NIR_PASS_V(s, ir3_nir_lower_load_barycentric_at_sample);
304 NIR_PASS_V(s, ir3_nir_lower_load_barycentric_at_offset);
305 NIR_PASS_V(s, ir3_nir_move_varying_inputs);
306 NIR_PASS_V(s, nir_lower_fb_read);
307 }
308
309 if (compiler->gpu_id >= 600 &&
310 s->info.stage == MESA_SHADER_FRAGMENT &&
311 !(ir3_shader_debug & IR3_DBG_NOFP16)) {
312 NIR_PASS_V(s, nir_lower_mediump_outputs);
313 }
314
315 /* we cannot ensure that ir3_finalize_nir() is only called once, so
316 * we also need to do trig workarounds here:
317 */
318 OPT_V(s, ir3_nir_apply_trig_workarounds);
319
320 ir3_optimize_loop(s);
321 }
322
323 static bool
324 ir3_nir_lower_layer_id(nir_shader *nir)
325 {
326 unsigned layer_id_loc = ~0;
327 nir_foreach_shader_in_variable(var, nir) {
328 if (var->data.location == VARYING_SLOT_LAYER) {
329 layer_id_loc = var->data.driver_location;
330 break;
331 }
332 }
333
334 assert(layer_id_loc != ~0);
335
336 bool progress = false;
337 nir_builder b;
338
339 nir_foreach_function(func, nir) {
340 nir_builder_init(&b, func->impl);
341
342 nir_foreach_block(block, func->impl) {
343 nir_foreach_instr_safe(instr, block) {
344 if (instr->type != nir_instr_type_intrinsic)
345 continue;
346
347 nir_intrinsic_instr *intrin =
348 nir_instr_as_intrinsic(instr);
349
350 if (intrin->intrinsic != nir_intrinsic_load_input)
351 continue;
352
353 unsigned base = nir_intrinsic_base(intrin);
354 if (base != layer_id_loc)
355 continue;
356
357 b.cursor = nir_before_instr(&intrin->instr);
358 nir_ssa_def *zero = nir_imm_int(&b, 0);
359 nir_ssa_def_rewrite_uses(&intrin->dest.ssa,
360 nir_src_for_ssa(zero));
361 nir_instr_remove(&intrin->instr);
362 progress = true;
363 }
364 }
365
366 if (progress) {
367 nir_metadata_preserve(func->impl,
368 nir_metadata_block_index |
369 nir_metadata_dominance);
370 } else {
371 nir_metadata_preserve(func->impl, nir_metadata_all);
372 }
373 }
374
375 return progress;
376 }
377
378 void
379 ir3_nir_lower_variant(struct ir3_shader_variant *so, nir_shader *s)
380 {
381 if (ir3_shader_debug & IR3_DBG_DISASM) {
382 debug_printf("----------------------\n");
383 nir_print_shader(s, stdout);
384 debug_printf("----------------------\n");
385 }
386
387 bool progress = false;
388
389 if (so->key.has_gs || so->key.tessellation) {
390 switch (so->shader->type) {
391 case MESA_SHADER_VERTEX:
392 NIR_PASS_V(s, ir3_nir_lower_to_explicit_output, so, so->key.tessellation);
393 progress = true;
394 break;
395 case MESA_SHADER_TESS_CTRL:
396 NIR_PASS_V(s, ir3_nir_lower_tess_ctrl, so, so->key.tessellation);
397 NIR_PASS_V(s, ir3_nir_lower_to_explicit_input, so->shader->compiler);
398 progress = true;
399 break;
400 case MESA_SHADER_TESS_EVAL:
401 NIR_PASS_V(s, ir3_nir_lower_tess_eval, so->key.tessellation);
402 if (so->key.has_gs)
403 NIR_PASS_V(s, ir3_nir_lower_to_explicit_output, so, so->key.tessellation);
404 progress = true;
405 break;
406 case MESA_SHADER_GEOMETRY:
407 NIR_PASS_V(s, ir3_nir_lower_to_explicit_input, so->shader->compiler);
408 progress = true;
409 break;
410 default:
411 break;
412 }
413 }
414
415 if (s->info.stage == MESA_SHADER_VERTEX) {
416 if (so->key.ucp_enables)
417 progress |= OPT(s, nir_lower_clip_vs, so->key.ucp_enables, false, false, NULL);
418 if (so->key.vclamp_color)
419 progress |= OPT(s, nir_lower_clamp_color_outputs);
420 } else if (s->info.stage == MESA_SHADER_FRAGMENT) {
421 if (so->key.ucp_enables)
422 progress |= OPT(s, nir_lower_clip_fs, so->key.ucp_enables, false);
423 if (so->key.fclamp_color)
424 progress |= OPT(s, nir_lower_clamp_color_outputs);
425 if (so->key.layer_zero && (s->info.inputs_read & VARYING_BIT_LAYER))
426 progress |= OPT(s, ir3_nir_lower_layer_id);
427 }
428 if (so->key.color_two_side) {
429 OPT_V(s, nir_lower_two_sided_color, true);
430 progress = true;
431 }
432
433 struct nir_lower_tex_options tex_options = { };
434
435 switch (so->shader->type) {
436 case MESA_SHADER_FRAGMENT:
437 tex_options.saturate_s = so->key.fsaturate_s;
438 tex_options.saturate_t = so->key.fsaturate_t;
439 tex_options.saturate_r = so->key.fsaturate_r;
440 break;
441 case MESA_SHADER_VERTEX:
442 tex_options.saturate_s = so->key.vsaturate_s;
443 tex_options.saturate_t = so->key.vsaturate_t;
444 tex_options.saturate_r = so->key.vsaturate_r;
445 break;
446 default:
447 /* TODO */
448 break;
449 }
450
451 if (tex_options.saturate_s || tex_options.saturate_t ||
452 tex_options.saturate_r) {
453 progress |= OPT(s, nir_lower_tex, &tex_options);
454 }
455
456 if (!so->binning_pass)
457 OPT_V(s, ir3_nir_analyze_ubo_ranges, so);
458
459 progress |= OPT(s, ir3_nir_lower_ubo_loads, so);
460
461 /* UBO offset lowering has to come after we've decided what will
462 * be left as load_ubo
463 */
464 OPT_V(s, ir3_nir_lower_io_offsets, so->shader->compiler->gpu_id);
465
466 if (progress)
467 ir3_optimize_loop(s);
468
469 /* Do late algebraic optimization to turn add(a, neg(b)) back into
470 * subs, then the mandatory cleanup after algebraic. Note that it may
471 * produce fnegs, and if so then we need to keep running to squash
472 * fneg(fneg(a)).
473 */
474 bool more_late_algebraic = true;
475 while (more_late_algebraic) {
476 more_late_algebraic = OPT(s, nir_opt_algebraic_late);
477 OPT_V(s, nir_opt_constant_folding);
478 OPT_V(s, nir_copy_prop);
479 OPT_V(s, nir_opt_dce);
480 OPT_V(s, nir_opt_cse);
481 }
482
483 OPT_V(s, nir_opt_sink, nir_move_const_undef);
484
485 if (ir3_shader_debug & IR3_DBG_DISASM) {
486 debug_printf("----------------------\n");
487 nir_print_shader(s, stdout);
488 debug_printf("----------------------\n");
489 }
490
491 nir_sweep(s);
492
493 /* Binning pass variants re-use the const_state of the corresponding
494 * draw pass shader, so that same const emit can be re-used for both
495 * passes:
496 */
497 if (!so->binning_pass)
498 ir3_setup_const_state(s, so, ir3_const_state(so));
499 }
500
501 static void
502 ir3_nir_scan_driver_consts(nir_shader *shader,
503 struct ir3_const_state *layout)
504 {
505 nir_foreach_function (function, shader) {
506 if (!function->impl)
507 continue;
508
509 nir_foreach_block (block, function->impl) {
510 nir_foreach_instr (instr, block) {
511 if (instr->type != nir_instr_type_intrinsic)
512 continue;
513
514 nir_intrinsic_instr *intr =
515 nir_instr_as_intrinsic(instr);
516 unsigned idx;
517
518 switch (intr->intrinsic) {
519 case nir_intrinsic_get_buffer_size:
520 if (ir3_bindless_resource(intr->src[0]))
521 break;
522 idx = nir_src_as_uint(intr->src[0]);
523 if (layout->ssbo_size.mask & (1 << idx))
524 break;
525 layout->ssbo_size.mask |= (1 << idx);
526 layout->ssbo_size.off[idx] =
527 layout->ssbo_size.count;
528 layout->ssbo_size.count += 1; /* one const per */
529 break;
530 case nir_intrinsic_image_atomic_add:
531 case nir_intrinsic_image_atomic_imin:
532 case nir_intrinsic_image_atomic_umin:
533 case nir_intrinsic_image_atomic_imax:
534 case nir_intrinsic_image_atomic_umax:
535 case nir_intrinsic_image_atomic_and:
536 case nir_intrinsic_image_atomic_or:
537 case nir_intrinsic_image_atomic_xor:
538 case nir_intrinsic_image_atomic_exchange:
539 case nir_intrinsic_image_atomic_comp_swap:
540 case nir_intrinsic_image_store:
541 case nir_intrinsic_image_size:
542 idx = nir_src_as_uint(intr->src[0]);
543 if (layout->image_dims.mask & (1 << idx))
544 break;
545 layout->image_dims.mask |= (1 << idx);
546 layout->image_dims.off[idx] =
547 layout->image_dims.count;
548 layout->image_dims.count += 3; /* three const per */
549 break;
550 case nir_intrinsic_load_base_vertex:
551 case nir_intrinsic_load_first_vertex:
552 layout->num_driver_params =
553 MAX2(layout->num_driver_params, IR3_DP_VTXID_BASE + 1);
554 break;
555 case nir_intrinsic_load_base_instance:
556 layout->num_driver_params =
557 MAX2(layout->num_driver_params, IR3_DP_INSTID_BASE + 1);
558 break;
559 case nir_intrinsic_load_user_clip_plane:
560 idx = nir_intrinsic_ucp_id(intr);
561 layout->num_driver_params =
562 MAX2(layout->num_driver_params, IR3_DP_UCP0_X + (idx + 1) * 4);
563 break;
564 case nir_intrinsic_load_num_work_groups:
565 layout->num_driver_params =
566 MAX2(layout->num_driver_params, IR3_DP_NUM_WORK_GROUPS_Z + 1);
567 break;
568 case nir_intrinsic_load_local_group_size:
569 layout->num_driver_params =
570 MAX2(layout->num_driver_params, IR3_DP_LOCAL_GROUP_SIZE_Z + 1);
571 break;
572 default:
573 break;
574 }
575 }
576 }
577 }
578 }
579
580 /* Sets up the variant-dependent constant state for the ir3_shader. Note
581 * that it is also used from ir3_nir_analyze_ubo_ranges() to figure out the
582 * maximum number of driver params that would eventually be used, to leave
583 * space for this function to allocate the driver params.
584 */
585 void
586 ir3_setup_const_state(nir_shader *nir, struct ir3_shader_variant *v,
587 struct ir3_const_state *const_state)
588 {
589 struct ir3_compiler *compiler = v->shader->compiler;
590
591 memset(&const_state->offsets, ~0, sizeof(const_state->offsets));
592
593 ir3_nir_scan_driver_consts(nir, const_state);
594
595 if ((compiler->gpu_id < 500) &&
596 (v->shader->stream_output.num_outputs > 0)) {
597 const_state->num_driver_params =
598 MAX2(const_state->num_driver_params, IR3_DP_VTXCNT_MAX + 1);
599 }
600
601 const_state->num_ubos = nir->info.num_ubos;
602
603 /* num_driver_params is scalar, align to vec4: */
604 const_state->num_driver_params = align(const_state->num_driver_params, 4);
605
606 debug_assert((const_state->ubo_state.size % 16) == 0);
607 unsigned constoff = const_state->ubo_state.size / 16;
608 unsigned ptrsz = ir3_pointer_size(compiler);
609
610 if (const_state->num_ubos > 0) {
611 const_state->offsets.ubo = constoff;
612 constoff += align(const_state->num_ubos * ptrsz, 4) / 4;
613 }
614
615 if (const_state->ssbo_size.count > 0) {
616 unsigned cnt = const_state->ssbo_size.count;
617 const_state->offsets.ssbo_sizes = constoff;
618 constoff += align(cnt, 4) / 4;
619 }
620
621 if (const_state->image_dims.count > 0) {
622 unsigned cnt = const_state->image_dims.count;
623 const_state->offsets.image_dims = constoff;
624 constoff += align(cnt, 4) / 4;
625 }
626
627 if (const_state->num_driver_params > 0) {
628 /* offset cannot be 0 for vs params loaded by CP_DRAW_INDIRECT_MULTI */
629 if (v->type == MESA_SHADER_VERTEX && compiler->gpu_id >= 600)
630 constoff = MAX2(constoff, 1);
631 const_state->offsets.driver_param = constoff;
632 }
633 constoff += const_state->num_driver_params / 4;
634
635 if ((v->type == MESA_SHADER_VERTEX) &&
636 (compiler->gpu_id < 500) &&
637 v->shader->stream_output.num_outputs > 0) {
638 const_state->offsets.tfbo = constoff;
639 constoff += align(IR3_MAX_SO_BUFFERS * ptrsz, 4) / 4;
640 }
641
642 switch (v->type) {
643 case MESA_SHADER_VERTEX:
644 const_state->offsets.primitive_param = constoff;
645 constoff += 1;
646 break;
647 case MESA_SHADER_TESS_CTRL:
648 case MESA_SHADER_TESS_EVAL:
649 constoff = align(constoff - 1, 4) + 3;
650 const_state->offsets.primitive_param = constoff;
651 const_state->offsets.primitive_map = constoff + 5;
652 constoff += 5 + DIV_ROUND_UP(nir->num_inputs, 4);
653 break;
654 case MESA_SHADER_GEOMETRY:
655 const_state->offsets.primitive_param = constoff;
656 const_state->offsets.primitive_map = constoff + 1;
657 constoff += 1 + DIV_ROUND_UP(nir->num_inputs, 4);
658 break;
659 default:
660 break;
661 }
662
663 const_state->offsets.immediate = constoff;
664
665 assert(constoff <= ir3_max_const(v));
666 }