src/freedreno/ir3/ir3_nir.c

   1 /*
   2  * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27
  28 #include "util/debug.h"
  29 #include "util/u_math.h"
  30
  31 #include "ir3_nir.h"
  32 #include "ir3_compiler.h"
  33 #include "ir3_shader.h"
  34
  35 static void ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir);
  36
  37 static const nir_shader_compiler_options options = {
  38                 .lower_fpow = true,
  39                 .lower_scmp = true,
  40                 .lower_flrp32 = true,
  41                 .lower_flrp64 = true,
  42                 .lower_ffract = true,
  43                 .lower_fmod32 = true,
  44                 .lower_fmod64 = true,
  45                 .lower_fdiv = true,
  46                 .lower_isign = true,
  47                 .lower_ldexp = true,
  48                 .lower_uadd_carry = true,
  49                 .lower_mul_high = true,
  50                 .fuse_ffma = true,
  51                 .vertex_id_zero_based = true,
  52                 .lower_extract_byte = true,
  53                 .lower_extract_word = true,
  54                 .lower_all_io_to_elements = true,
  55                 .lower_helper_invocation = true,
  56                 .lower_bitfield_insert_to_shifts = true,
  57                 .lower_bitfield_extract_to_shifts = true,
  58                 .lower_bfm = true,
  59                 .use_interpolated_input_intrinsics = true,
  60 };
  61
  62 /* we don't want to lower vertex_id to _zero_based on newer gpus: */
  63 static const nir_shader_compiler_options options_a6xx = {
  64                 .lower_fpow = true,
  65                 .lower_scmp = true,
  66                 .lower_flrp32 = true,
  67                 .lower_flrp64 = true,
  68                 .lower_ffract = true,
  69                 .lower_fmod32 = true,
  70                 .lower_fmod64 = true,
  71                 .lower_fdiv = true,
  72                 .lower_isign = true,
  73                 .lower_ldexp = true,
  74                 .lower_uadd_carry = true,
  75                 .lower_mul_high = true,
  76                 .fuse_ffma = true,
  77                 .vertex_id_zero_based = false,
  78                 .lower_extract_byte = true,
  79                 .lower_extract_word = true,
  80                 .lower_all_io_to_elements = true,
  81                 .lower_helper_invocation = true,
  82                 .lower_bitfield_insert_to_shifts = true,
  83                 .lower_bitfield_extract_to_shifts = true,
  84                 .lower_bfm = true,
  85                 .use_interpolated_input_intrinsics = true,
  86 };
  87
  88 const nir_shader_compiler_options *
  89 ir3_get_compiler_options(struct ir3_compiler *compiler)
  90 {
  91         if (compiler->gpu_id >= 600)
  92                 return &options_a6xx;
  93         return &options;
  94 }
  95
  96 /* for given shader key, are any steps handled in nir? */
  97 bool
  98 ir3_key_lowers_nir(const struct ir3_shader_key *key)
  99 {
 100         return key->fsaturate_s | key->fsaturate_t | key->fsaturate_r |
 101                         key->vsaturate_s | key->vsaturate_t | key->vsaturate_r |
 102                         key->ucp_enables | key->color_two_side |
 103                         key->fclamp_color | key->vclamp_color;
 104 }
 105
 106 #define OPT(nir, pass, ...) ({                             \
 107    bool this_progress = false;                             \
 108    NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__);      \
 109    this_progress;                                          \
 110 })
 111
 112 #define OPT_V(nir, pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
 113
 114 static void
 115 ir3_optimize_loop(nir_shader *s)
 116 {
 117         bool progress;
 118         unsigned lower_flrp =
 119                 (s->options->lower_flrp16 ? 16 : 0) |
 120                 (s->options->lower_flrp32 ? 32 : 0) |
 121                 (s->options->lower_flrp64 ? 64 : 0);
 122
 123         do {
 124                 progress = false;
 125
 126                 OPT_V(s, nir_lower_vars_to_ssa);
 127                 progress |= OPT(s, nir_opt_copy_prop_vars);
 128                 progress |= OPT(s, nir_opt_dead_write_vars);
 129                 progress |= OPT(s, nir_lower_alu_to_scalar, NULL);
 130                 progress |= OPT(s, nir_lower_phis_to_scalar);
 131
 132                 progress |= OPT(s, nir_copy_prop);
 133                 progress |= OPT(s, nir_opt_dce);
 134                 progress |= OPT(s, nir_opt_cse);
 135                 static int gcm = -1;
 136                 if (gcm == -1)
 137                         gcm = env_var_as_unsigned("GCM", 0);
 138                 if (gcm == 1)
 139                         progress |= OPT(s, nir_opt_gcm, true);
 140                 else if (gcm == 2)
 141                         progress |= OPT(s, nir_opt_gcm, false);
 142                 progress |= OPT(s, nir_opt_peephole_select, 16, true, true);
 143                 progress |= OPT(s, nir_opt_intrinsics);
 144                 progress |= OPT(s, nir_opt_algebraic);
 145                 progress |= OPT(s, nir_opt_constant_folding);
 146
 147                 if (lower_flrp != 0) {
 148                         if (OPT(s, nir_lower_flrp,
 149                                         lower_flrp,
 150                                         false /* always_precise */,
 151                                         s->options->lower_ffma)) {
 152                                 OPT(s, nir_opt_constant_folding);
 153                                 progress = true;
 154                         }
 155
 156                         /* Nothing should rematerialize any flrps, so we only
 157                          * need to do this lowering once.
 158                          */
 159                         lower_flrp = 0;
 160                 }
 161
 162                 progress |= OPT(s, nir_opt_dead_cf);
 163                 if (OPT(s, nir_opt_trivial_continues)) {
 164                         progress |= true;
 165                         /* If nir_opt_trivial_continues makes progress, then we need to clean
 166                          * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
 167                          * to make progress.
 168                          */
 169                         OPT(s, nir_copy_prop);
 170                         OPT(s, nir_opt_dce);
 171                 }
 172                 progress |= OPT(s, nir_opt_if, false);
 173                 progress |= OPT(s, nir_opt_remove_phis);
 174                 progress |= OPT(s, nir_opt_undef);
 175
 176         } while (progress);
 177 }
 178
 179 struct nir_shader *
 180 ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
 181                 const struct ir3_shader_key *key)
 182 {
 183         struct nir_lower_tex_options tex_options = {
 184                         .lower_rect = 0,
 185                         .lower_tg4_offsets = true,
 186         };
 187
 188         if (key) {
 189                 switch (shader->type) {
 190                 case MESA_SHADER_FRAGMENT:
 191                         tex_options.saturate_s = key->fsaturate_s;
 192                         tex_options.saturate_t = key->fsaturate_t;
 193                         tex_options.saturate_r = key->fsaturate_r;
 194                         break;
 195                 case MESA_SHADER_VERTEX:
 196                         tex_options.saturate_s = key->vsaturate_s;
 197                         tex_options.saturate_t = key->vsaturate_t;
 198                         tex_options.saturate_r = key->vsaturate_r;
 199                         break;
 200                 default:
 201                         /* TODO */
 202                         break;
 203                 }
 204         }
 205
 206         if (shader->compiler->gpu_id >= 400) {
 207                 /* a4xx seems to have *no* sam.p */
 208                 tex_options.lower_txp = ~0;  /* lower all txp */
 209         } else {
 210                 /* a3xx just needs to avoid sam.p for 3d tex */
 211                 tex_options.lower_txp = (1 << GLSL_SAMPLER_DIM_3D);
 212         }
 213
 214         if (ir3_shader_debug & IR3_DBG_DISASM) {
 215                 debug_printf("----------------------\n");
 216                 nir_print_shader(s, stdout);
 217                 debug_printf("----------------------\n");
 218         }
 219
 220         OPT_V(s, nir_lower_regs_to_ssa);
 221         OPT_V(s, ir3_nir_lower_io_offsets);
 222
 223         if (key) {
 224                 if (s->info.stage == MESA_SHADER_VERTEX) {
 225                         OPT_V(s, nir_lower_clip_vs, key->ucp_enables, false);
 226                         if (key->vclamp_color)
 227                                 OPT_V(s, nir_lower_clamp_color_outputs);
 228                 } else if (s->info.stage == MESA_SHADER_FRAGMENT) {
 229                         OPT_V(s, nir_lower_clip_fs, key->ucp_enables);
 230                         if (key->fclamp_color)
 231                                 OPT_V(s, nir_lower_clamp_color_outputs);
 232                 }
 233                 if (key->color_two_side) {
 234                         OPT_V(s, nir_lower_two_sided_color);
 235                 }
 236         } else {
 237                 /* only want to do this the first time (when key is null)
 238                  * and not again on any potential 2nd variant lowering pass:
 239                  */
 240                 OPT_V(s, ir3_nir_apply_trig_workarounds);
 241
 242                 /* This wouldn't hurt to run multiple times, but there is
 243                  * no need to:
 244                  */
 245                 if (shader->type == MESA_SHADER_FRAGMENT)
 246                         OPT_V(s, nir_lower_fb_read);
 247         }
 248
 249         OPT_V(s, nir_lower_tex, &tex_options);
 250         OPT_V(s, nir_lower_load_const_to_scalar);
 251         if (shader->compiler->gpu_id < 500)
 252                 OPT_V(s, ir3_nir_lower_tg4_to_tex);
 253
 254         ir3_optimize_loop(s);
 255
 256         /* do ubo load and idiv lowering after first opt loop to get a chance to
 257          * propagate constants for divide by immed power-of-two and constant ubo
 258          * block/offsets:
 259          *
 260          * NOTE that UBO analysis pass should only be done once, before variants
 261          */
 262         const bool ubo_progress = !key && OPT(s, ir3_nir_analyze_ubo_ranges, shader);
 263         const bool idiv_progress = OPT(s, nir_lower_idiv);
 264         if (ubo_progress || idiv_progress)
 265                 ir3_optimize_loop(s);
 266
 267         OPT_V(s, nir_remove_dead_variables, nir_var_function_temp);
 268
 269         OPT_V(s, nir_move_load_const);
 270
 271         if (ir3_shader_debug & IR3_DBG_DISASM) {
 272                 debug_printf("----------------------\n");
 273                 nir_print_shader(s, stdout);
 274                 debug_printf("----------------------\n");
 275         }
 276
 277         nir_sweep(s);
 278
 279         /* The first time thru, when not creating variant, do the one-time
 280          * const_state layout setup.  This should be done after ubo range
 281          * analysis.
 282          */
 283         if (!key) {
 284                 ir3_setup_const_state(shader, s);
 285         }
 286
 287         return s;
 288 }
 289
 290 static void
 291 ir3_nir_scan_driver_consts(nir_shader *shader,
 292                 struct ir3_const_state *layout)
 293 {
 294         nir_foreach_function(function, shader) {
 295                 if (!function->impl)
 296                         continue;
 297
 298                 nir_foreach_block(block, function->impl) {
 299                         nir_foreach_instr(instr, block) {
 300                                 if (instr->type != nir_instr_type_intrinsic)
 301                                         continue;
 302
 303                                 nir_intrinsic_instr *intr =
 304                                         nir_instr_as_intrinsic(instr);
 305                                 unsigned idx;
 306
 307                                 switch (intr->intrinsic) {
 308                                 case nir_intrinsic_get_buffer_size:
 309                                         idx = nir_src_as_uint(intr->src[0]);
 310                                         if (layout->ssbo_size.mask & (1 << idx))
 311                                                 break;
 312                                         layout->ssbo_size.mask |= (1 << idx);
 313                                         layout->ssbo_size.off[idx] =
 314                                                 layout->ssbo_size.count;
 315                                         layout->ssbo_size.count += 1; /* one const per */
 316                                         break;
 317                                 case nir_intrinsic_image_deref_atomic_add:
 318                                 case nir_intrinsic_image_deref_atomic_min:
 319                                 case nir_intrinsic_image_deref_atomic_max:
 320                                 case nir_intrinsic_image_deref_atomic_and:
 321                                 case nir_intrinsic_image_deref_atomic_or:
 322                                 case nir_intrinsic_image_deref_atomic_xor:
 323                                 case nir_intrinsic_image_deref_atomic_exchange:
 324                                 case nir_intrinsic_image_deref_atomic_comp_swap:
 325                                 case nir_intrinsic_image_deref_store:
 326                                 case nir_intrinsic_image_deref_size:
 327                                         idx = nir_intrinsic_get_var(intr, 0)->data.driver_location;
 328                                         if (layout->image_dims.mask & (1 << idx))
 329                                                 break;
 330                                         layout->image_dims.mask |= (1 << idx);
 331                                         layout->image_dims.off[idx] =
 332                                                 layout->image_dims.count;
 333                                         layout->image_dims.count += 3; /* three const per */
 334                                         break;
 335                                 default:
 336                                         break;
 337                                 }
 338                         }
 339                 }
 340         }
 341 }
 342
 343 static void
 344 ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir)
 345 {
 346         struct ir3_compiler *compiler = shader->compiler;
 347         struct ir3_const_state *const_state = &shader->const_state;
 348
 349         memset(&const_state->offsets, ~0, sizeof(const_state->offsets));
 350
 351         ir3_nir_scan_driver_consts(nir, const_state);
 352
 353         const_state->num_uniforms = nir->num_uniforms;
 354         const_state->num_ubos = nir->info.num_ubos;
 355
 356         debug_assert((shader->ubo_state.size % 16) == 0);
 357         unsigned constoff = align(shader->ubo_state.size / 16, 4);
 358         unsigned ptrsz = ir3_pointer_size(compiler);
 359
 360         if (const_state->num_ubos > 0) {
 361                 const_state->offsets.ubo = constoff;
 362                 constoff += align(nir->info.num_ubos * ptrsz, 4) / 4;
 363         }
 364
 365         if (const_state->ssbo_size.count > 0) {
 366                 unsigned cnt = const_state->ssbo_size.count;
 367                 const_state->offsets.ssbo_sizes = constoff;
 368                 constoff += align(cnt, 4) / 4;
 369         }
 370
 371         if (const_state->image_dims.count > 0) {
 372                 unsigned cnt = const_state->image_dims.count;
 373                 const_state->offsets.image_dims = constoff;
 374                 constoff += align(cnt, 4) / 4;
 375         }
 376
 377         unsigned num_driver_params = 0;
 378         if (shader->type == MESA_SHADER_VERTEX) {
 379                 num_driver_params = IR3_DP_VS_COUNT;
 380         } else if (shader->type == MESA_SHADER_COMPUTE) {
 381                 num_driver_params = IR3_DP_CS_COUNT;
 382         }
 383
 384         const_state->offsets.driver_param = constoff;
 385         constoff += align(num_driver_params, 4) / 4;
 386
 387         if ((shader->type == MESA_SHADER_VERTEX) &&
 388                         (compiler->gpu_id < 500) &&
 389                         shader->stream_output.num_outputs > 0) {
 390                 const_state->offsets.tfbo = constoff;
 391                 constoff += align(IR3_MAX_SO_BUFFERS * ptrsz, 4) / 4;
 392         }
 393
 394         const_state->offsets.immediate = constoff;
 395 }