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[mesa.git] / src / freedreno / ir3 / ir3_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27
28 #include "util/debug.h"
29 #include "util/u_math.h"
30
31 #include "ir3_nir.h"
32 #include "ir3_compiler.h"
33 #include "ir3_shader.h"
34
35 static const nir_shader_compiler_options options = {
36 .lower_fpow = true,
37 .lower_scmp = true,
38 .lower_flrp16 = true,
39 .lower_flrp32 = true,
40 .lower_flrp64 = true,
41 .lower_ffract = true,
42 .lower_fmod = true,
43 .lower_fdiv = true,
44 .lower_isign = true,
45 .lower_ldexp = true,
46 .lower_uadd_carry = true,
47 .lower_usub_borrow = true,
48 .lower_mul_high = true,
49 .lower_mul_2x32_64 = true,
50 .fuse_ffma = true,
51 .vertex_id_zero_based = true,
52 .lower_extract_byte = true,
53 .lower_extract_word = true,
54 .lower_all_io_to_elements = true,
55 .lower_helper_invocation = true,
56 .lower_bitfield_insert_to_shifts = true,
57 .lower_bitfield_extract_to_shifts = true,
58 .lower_pack_half_2x16 = true,
59 .lower_pack_snorm_4x8 = true,
60 .lower_pack_snorm_2x16 = true,
61 .lower_pack_unorm_4x8 = true,
62 .lower_pack_unorm_2x16 = true,
63 .lower_unpack_half_2x16 = true,
64 .lower_unpack_snorm_4x8 = true,
65 .lower_unpack_snorm_2x16 = true,
66 .lower_unpack_unorm_4x8 = true,
67 .lower_unpack_unorm_2x16 = true,
68 .lower_pack_split = true,
69 .use_interpolated_input_intrinsics = true,
70 .lower_rotate = true,
71 .lower_to_scalar = true,
72 .has_imul24 = true,
73 };
74
75 /* we don't want to lower vertex_id to _zero_based on newer gpus: */
76 static const nir_shader_compiler_options options_a6xx = {
77 .lower_fpow = true,
78 .lower_scmp = true,
79 .lower_flrp16 = true,
80 .lower_flrp32 = true,
81 .lower_flrp64 = true,
82 .lower_ffract = true,
83 .lower_fmod = true,
84 .lower_fdiv = true,
85 .lower_isign = true,
86 .lower_ldexp = true,
87 .lower_uadd_carry = true,
88 .lower_usub_borrow = true,
89 .lower_mul_high = true,
90 .lower_mul_2x32_64 = true,
91 .fuse_ffma = true,
92 .vertex_id_zero_based = false,
93 .lower_extract_byte = true,
94 .lower_extract_word = true,
95 .lower_all_io_to_elements = true,
96 .lower_helper_invocation = true,
97 .lower_bitfield_insert_to_shifts = true,
98 .lower_bitfield_extract_to_shifts = true,
99 .lower_pack_half_2x16 = true,
100 .lower_pack_snorm_4x8 = true,
101 .lower_pack_snorm_2x16 = true,
102 .lower_pack_unorm_4x8 = true,
103 .lower_pack_unorm_2x16 = true,
104 .lower_unpack_half_2x16 = true,
105 .lower_unpack_snorm_4x8 = true,
106 .lower_unpack_snorm_2x16 = true,
107 .lower_unpack_unorm_4x8 = true,
108 .lower_unpack_unorm_2x16 = true,
109 .lower_pack_split = true,
110 .use_interpolated_input_intrinsics = true,
111 .lower_rotate = true,
112 .vectorize_io = true,
113 .lower_to_scalar = true,
114 .has_imul24 = true,
115 .max_unroll_iterations = 32,
116 };
117
118 const nir_shader_compiler_options *
119 ir3_get_compiler_options(struct ir3_compiler *compiler)
120 {
121 if (compiler->gpu_id >= 600)
122 return &options_a6xx;
123 return &options;
124 }
125
126 #define OPT(nir, pass, ...) ({ \
127 bool this_progress = false; \
128 NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__); \
129 this_progress; \
130 })
131
132 #define OPT_V(nir, pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
133
134 static void
135 ir3_optimize_loop(nir_shader *s)
136 {
137 bool progress;
138 unsigned lower_flrp =
139 (s->options->lower_flrp16 ? 16 : 0) |
140 (s->options->lower_flrp32 ? 32 : 0) |
141 (s->options->lower_flrp64 ? 64 : 0);
142
143 do {
144 progress = false;
145
146 OPT_V(s, nir_lower_vars_to_ssa);
147 progress |= OPT(s, nir_opt_copy_prop_vars);
148 progress |= OPT(s, nir_opt_dead_write_vars);
149 progress |= OPT(s, nir_lower_alu_to_scalar, NULL, NULL);
150 progress |= OPT(s, nir_lower_phis_to_scalar);
151
152 progress |= OPT(s, nir_copy_prop);
153 progress |= OPT(s, nir_opt_dce);
154 progress |= OPT(s, nir_opt_cse);
155 static int gcm = -1;
156 if (gcm == -1)
157 gcm = env_var_as_unsigned("GCM", 0);
158 if (gcm == 1)
159 progress |= OPT(s, nir_opt_gcm, true);
160 else if (gcm == 2)
161 progress |= OPT(s, nir_opt_gcm, false);
162 progress |= OPT(s, nir_opt_peephole_select, 16, true, true);
163 progress |= OPT(s, nir_opt_intrinsics);
164 progress |= OPT(s, nir_opt_algebraic);
165 progress |= OPT(s, nir_lower_alu);
166 progress |= OPT(s, nir_lower_pack);
167 progress |= OPT(s, nir_opt_constant_folding);
168
169 if (lower_flrp != 0) {
170 if (OPT(s, nir_lower_flrp,
171 lower_flrp,
172 false /* always_precise */,
173 s->options->lower_ffma)) {
174 OPT(s, nir_opt_constant_folding);
175 progress = true;
176 }
177
178 /* Nothing should rematerialize any flrps, so we only
179 * need to do this lowering once.
180 */
181 lower_flrp = 0;
182 }
183
184 progress |= OPT(s, nir_opt_dead_cf);
185 if (OPT(s, nir_opt_trivial_continues)) {
186 progress |= true;
187 /* If nir_opt_trivial_continues makes progress, then we need to clean
188 * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
189 * to make progress.
190 */
191 OPT(s, nir_copy_prop);
192 OPT(s, nir_opt_dce);
193 }
194 progress |= OPT(s, nir_opt_if, false);
195 progress |= OPT(s, nir_opt_remove_phis);
196 progress |= OPT(s, nir_opt_undef);
197 } while (progress);
198 }
199
200 static bool
201 should_split_wrmask(const nir_instr *instr, const void *data)
202 {
203 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
204
205 switch (intr->intrinsic) {
206 case nir_intrinsic_store_ssbo:
207 case nir_intrinsic_store_shared:
208 case nir_intrinsic_store_global:
209 return true;
210 default:
211 return false;
212 }
213 }
214
215 void
216 ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s)
217 {
218 struct nir_lower_tex_options tex_options = {
219 .lower_rect = 0,
220 .lower_tg4_offsets = true,
221 };
222
223 if (shader->compiler->gpu_id >= 400) {
224 /* a4xx seems to have *no* sam.p */
225 tex_options.lower_txp = ~0; /* lower all txp */
226 } else {
227 /* a3xx just needs to avoid sam.p for 3d tex */
228 tex_options.lower_txp = (1 << GLSL_SAMPLER_DIM_3D);
229 }
230
231 if (ir3_shader_debug & IR3_DBG_DISASM) {
232 debug_printf("----------------------\n");
233 nir_print_shader(s, stdout);
234 debug_printf("----------------------\n");
235 }
236
237 OPT_V(s, nir_lower_regs_to_ssa);
238 OPT_V(s, nir_lower_wrmasks, should_split_wrmask, s);
239
240 OPT_V(s, ir3_nir_apply_trig_workarounds);
241
242 if (shader->type == MESA_SHADER_FRAGMENT)
243 OPT_V(s, nir_lower_fb_read);
244
245 OPT_V(s, nir_lower_tex, &tex_options);
246 OPT_V(s, nir_lower_load_const_to_scalar);
247 if (shader->compiler->gpu_id < 500)
248 OPT_V(s, ir3_nir_lower_tg4_to_tex);
249
250 ir3_optimize_loop(s);
251
252 /* do idiv lowering after first opt loop to get a chance to propagate
253 * constants for divide by immed power-of-two:
254 */
255 const bool idiv_progress = OPT(s, nir_lower_idiv, nir_lower_idiv_fast);
256
257 if (idiv_progress)
258 ir3_optimize_loop(s);
259
260 OPT_V(s, nir_remove_dead_variables, nir_var_function_temp, NULL);
261
262 if (ir3_shader_debug & IR3_DBG_DISASM) {
263 debug_printf("----------------------\n");
264 nir_print_shader(s, stdout);
265 debug_printf("----------------------\n");
266 }
267
268 nir_sweep(s);
269 }
270
271 void
272 ir3_nir_lower_variant(struct ir3_shader_variant *so, nir_shader *s)
273 {
274 if (ir3_shader_debug & IR3_DBG_DISASM) {
275 debug_printf("----------------------\n");
276 nir_print_shader(s, stdout);
277 debug_printf("----------------------\n");
278 }
279
280 bool progress = false;
281
282 if (so->key.has_gs || so->key.tessellation) {
283 switch (so->shader->type) {
284 case MESA_SHADER_VERTEX:
285 NIR_PASS_V(s, ir3_nir_lower_to_explicit_output, so, so->key.tessellation);
286 progress = true;
287 break;
288 case MESA_SHADER_TESS_CTRL:
289 NIR_PASS_V(s, ir3_nir_lower_tess_ctrl, so, so->key.tessellation);
290 NIR_PASS_V(s, ir3_nir_lower_to_explicit_input);
291 progress = true;
292 break;
293 case MESA_SHADER_TESS_EVAL:
294 NIR_PASS_V(s, ir3_nir_lower_tess_eval, so->key.tessellation);
295 if (so->key.has_gs)
296 NIR_PASS_V(s, ir3_nir_lower_to_explicit_output, so, so->key.tessellation);
297 progress = true;
298 break;
299 case MESA_SHADER_GEOMETRY:
300 NIR_PASS_V(s, ir3_nir_lower_to_explicit_input);
301 progress = true;
302 break;
303 default:
304 break;
305 }
306 }
307
308 if (s->info.stage == MESA_SHADER_VERTEX) {
309 if (so->key.ucp_enables)
310 progress |= OPT(s, nir_lower_clip_vs, so->key.ucp_enables, false, false, NULL);
311 if (so->key.vclamp_color)
312 progress |= OPT(s, nir_lower_clamp_color_outputs);
313 } else if (s->info.stage == MESA_SHADER_FRAGMENT) {
314 if (so->key.ucp_enables)
315 progress |= OPT(s, nir_lower_clip_fs, so->key.ucp_enables, false);
316 if (so->key.fclamp_color)
317 progress |= OPT(s, nir_lower_clamp_color_outputs);
318 }
319 if (so->key.color_two_side) {
320 OPT_V(s, nir_lower_two_sided_color);
321 progress = true;
322 }
323
324 struct nir_lower_tex_options tex_options = { };
325
326 switch (so->shader->type) {
327 case MESA_SHADER_FRAGMENT:
328 tex_options.saturate_s = so->key.fsaturate_s;
329 tex_options.saturate_t = so->key.fsaturate_t;
330 tex_options.saturate_r = so->key.fsaturate_r;
331 break;
332 case MESA_SHADER_VERTEX:
333 tex_options.saturate_s = so->key.vsaturate_s;
334 tex_options.saturate_t = so->key.vsaturate_t;
335 tex_options.saturate_r = so->key.vsaturate_r;
336 break;
337 default:
338 /* TODO */
339 break;
340 }
341
342 if (tex_options.saturate_s || tex_options.saturate_t ||
343 tex_options.saturate_r) {
344 progress |= OPT(s, nir_lower_tex, &tex_options);
345 }
346
347 progress |= OPT(s, ir3_nir_analyze_ubo_ranges, so);
348
349 /* UBO offset lowering has to come after we've decided what will
350 * be left as load_ubo
351 */
352 OPT_V(s, ir3_nir_lower_io_offsets, so->shader->compiler->gpu_id);
353
354 if (progress)
355 ir3_optimize_loop(s);
356
357 /* Do late algebraic optimization to turn add(a, neg(b)) back into
358 * subs, then the mandatory cleanup after algebraic. Note that it may
359 * produce fnegs, and if so then we need to keep running to squash
360 * fneg(fneg(a)).
361 */
362 bool more_late_algebraic = true;
363 while (more_late_algebraic) {
364 more_late_algebraic = OPT(s, nir_opt_algebraic_late);
365 OPT_V(s, nir_opt_constant_folding);
366 OPT_V(s, nir_copy_prop);
367 OPT_V(s, nir_opt_dce);
368 OPT_V(s, nir_opt_cse);
369 }
370
371 OPT_V(s, nir_opt_sink, nir_move_const_undef);
372
373 if (ir3_shader_debug & IR3_DBG_DISASM) {
374 debug_printf("----------------------\n");
375 nir_print_shader(s, stdout);
376 debug_printf("----------------------\n");
377 }
378
379 nir_sweep(s);
380
381 /* Binning pass variants re-use the const_state of the corresponding
382 * draw pass shader, so that same const emit can be re-used for both
383 * passes:
384 */
385 if (!so->binning_pass)
386 ir3_setup_const_state(s, so, ir3_const_state(so));
387 }
388
389 static void
390 ir3_nir_scan_driver_consts(nir_shader *shader,
391 struct ir3_const_state *layout)
392 {
393 nir_foreach_function (function, shader) {
394 if (!function->impl)
395 continue;
396
397 nir_foreach_block (block, function->impl) {
398 nir_foreach_instr (instr, block) {
399 if (instr->type != nir_instr_type_intrinsic)
400 continue;
401
402 nir_intrinsic_instr *intr =
403 nir_instr_as_intrinsic(instr);
404 unsigned idx;
405
406 switch (intr->intrinsic) {
407 case nir_intrinsic_get_buffer_size:
408 idx = nir_src_as_uint(intr->src[0]);
409 if (layout->ssbo_size.mask & (1 << idx))
410 break;
411 layout->ssbo_size.mask |= (1 << idx);
412 layout->ssbo_size.off[idx] =
413 layout->ssbo_size.count;
414 layout->ssbo_size.count += 1; /* one const per */
415 break;
416 case nir_intrinsic_image_atomic_add:
417 case nir_intrinsic_image_atomic_imin:
418 case nir_intrinsic_image_atomic_umin:
419 case nir_intrinsic_image_atomic_imax:
420 case nir_intrinsic_image_atomic_umax:
421 case nir_intrinsic_image_atomic_and:
422 case nir_intrinsic_image_atomic_or:
423 case nir_intrinsic_image_atomic_xor:
424 case nir_intrinsic_image_atomic_exchange:
425 case nir_intrinsic_image_atomic_comp_swap:
426 case nir_intrinsic_image_store:
427 case nir_intrinsic_image_size:
428 idx = nir_src_as_uint(intr->src[0]);
429 if (layout->image_dims.mask & (1 << idx))
430 break;
431 layout->image_dims.mask |= (1 << idx);
432 layout->image_dims.off[idx] =
433 layout->image_dims.count;
434 layout->image_dims.count += 3; /* three const per */
435 break;
436 case nir_intrinsic_load_base_vertex:
437 case nir_intrinsic_load_first_vertex:
438 layout->num_driver_params =
439 MAX2(layout->num_driver_params, IR3_DP_VTXID_BASE + 1);
440 break;
441 case nir_intrinsic_load_base_instance:
442 layout->num_driver_params =
443 MAX2(layout->num_driver_params, IR3_DP_INSTID_BASE + 1);
444 break;
445 case nir_intrinsic_load_user_clip_plane:
446 layout->num_driver_params =
447 MAX2(layout->num_driver_params, IR3_DP_UCP7_W + 1);
448 break;
449 case nir_intrinsic_load_num_work_groups:
450 layout->num_driver_params =
451 MAX2(layout->num_driver_params, IR3_DP_NUM_WORK_GROUPS_Z + 1);
452 break;
453 case nir_intrinsic_load_local_group_size:
454 layout->num_driver_params =
455 MAX2(layout->num_driver_params, IR3_DP_LOCAL_GROUP_SIZE_Z + 1);
456 break;
457 default:
458 break;
459 }
460 }
461 }
462 }
463 }
464
465 /* Sets up the variant-dependent constant state for the ir3_shader. Note
466 * that it is also used from ir3_nir_analyze_ubo_ranges() to figure out the
467 * maximum number of driver params that would eventually be used, to leave
468 * space for this function to allocate the driver params.
469 */
470 void
471 ir3_setup_const_state(nir_shader *nir, struct ir3_shader_variant *v,
472 struct ir3_const_state *const_state)
473 {
474 struct ir3_compiler *compiler = v->shader->compiler;
475
476 memset(&const_state->offsets, ~0, sizeof(const_state->offsets));
477
478 ir3_nir_scan_driver_consts(nir, const_state);
479
480 if ((compiler->gpu_id < 500) &&
481 (v->shader->stream_output.num_outputs > 0)) {
482 const_state->num_driver_params =
483 MAX2(const_state->num_driver_params, IR3_DP_VTXCNT_MAX + 1);
484 }
485
486 const_state->num_ubos = nir->info.num_ubos;
487
488 /* num_driver_params is scalar, align to vec4: */
489 const_state->num_driver_params = align(const_state->num_driver_params, 4);
490
491 debug_assert((const_state->ubo_state.size % 16) == 0);
492 unsigned constoff = const_state->ubo_state.size / 16;
493 unsigned ptrsz = ir3_pointer_size(compiler);
494
495 if (const_state->num_ubos > 0) {
496 const_state->offsets.ubo = constoff;
497 constoff += align(const_state->num_ubos * ptrsz, 4) / 4;
498 }
499
500 if (const_state->ssbo_size.count > 0) {
501 unsigned cnt = const_state->ssbo_size.count;
502 const_state->offsets.ssbo_sizes = constoff;
503 constoff += align(cnt, 4) / 4;
504 }
505
506 if (const_state->image_dims.count > 0) {
507 unsigned cnt = const_state->image_dims.count;
508 const_state->offsets.image_dims = constoff;
509 constoff += align(cnt, 4) / 4;
510 }
511
512 if (const_state->num_driver_params > 0)
513 const_state->offsets.driver_param = constoff;
514 constoff += const_state->num_driver_params / 4;
515
516 if ((v->type == MESA_SHADER_VERTEX) &&
517 (compiler->gpu_id < 500) &&
518 v->shader->stream_output.num_outputs > 0) {
519 const_state->offsets.tfbo = constoff;
520 constoff += align(IR3_MAX_SO_BUFFERS * ptrsz, 4) / 4;
521 }
522
523 switch (v->type) {
524 case MESA_SHADER_VERTEX:
525 const_state->offsets.primitive_param = constoff;
526 constoff += 1;
527 break;
528 case MESA_SHADER_TESS_CTRL:
529 case MESA_SHADER_TESS_EVAL:
530 constoff = align(constoff - 1, 4) + 3;
531 const_state->offsets.primitive_param = constoff;
532 const_state->offsets.primitive_map = constoff + 5;
533 constoff += 5 + DIV_ROUND_UP(nir->num_inputs, 4);
534 break;
535 case MESA_SHADER_GEOMETRY:
536 const_state->offsets.primitive_param = constoff;
537 const_state->offsets.primitive_map = constoff + 1;
538 constoff += 1 + DIV_ROUND_UP(nir->num_inputs, 4);
539 break;
540 default:
541 break;
542 }
543
544 const_state->offsets.immediate = constoff;
545
546 assert(constoff <= compiler->max_const);
547 }