b4b62ef99b385e88ccff453148c772f8dfab0166
[mesa.git] / src / freedreno / ir3 / ir3_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27
28 #include "util/debug.h"
29 #include "util/u_math.h"
30
31 #include "ir3_nir.h"
32 #include "ir3_compiler.h"
33 #include "ir3_shader.h"
34
35 static const nir_shader_compiler_options options = {
36 .lower_fpow = true,
37 .lower_scmp = true,
38 .lower_flrp16 = true,
39 .lower_flrp32 = true,
40 .lower_flrp64 = true,
41 .lower_ffract = true,
42 .lower_fmod = true,
43 .lower_fdiv = true,
44 .lower_isign = true,
45 .lower_ldexp = true,
46 .lower_uadd_carry = true,
47 .lower_usub_borrow = true,
48 .lower_mul_high = true,
49 .lower_mul_2x32_64 = true,
50 .fuse_ffma = true,
51 .vertex_id_zero_based = true,
52 .lower_extract_byte = true,
53 .lower_extract_word = true,
54 .lower_all_io_to_elements = true,
55 .lower_helper_invocation = true,
56 .lower_bitfield_insert_to_shifts = true,
57 .lower_bitfield_extract_to_shifts = true,
58 .lower_pack_half_2x16 = true,
59 .lower_pack_snorm_4x8 = true,
60 .lower_pack_snorm_2x16 = true,
61 .lower_pack_unorm_4x8 = true,
62 .lower_pack_unorm_2x16 = true,
63 .lower_unpack_half_2x16 = true,
64 .lower_unpack_snorm_4x8 = true,
65 .lower_unpack_snorm_2x16 = true,
66 .lower_unpack_unorm_4x8 = true,
67 .lower_unpack_unorm_2x16 = true,
68 .lower_pack_split = true,
69 .use_interpolated_input_intrinsics = true,
70 .lower_rotate = true,
71 .lower_to_scalar = true,
72 .has_imul24 = true,
73 .lower_wpos_pntc = true,
74 };
75
76 /* we don't want to lower vertex_id to _zero_based on newer gpus: */
77 static const nir_shader_compiler_options options_a6xx = {
78 .lower_fpow = true,
79 .lower_scmp = true,
80 .lower_flrp16 = true,
81 .lower_flrp32 = true,
82 .lower_flrp64 = true,
83 .lower_ffract = true,
84 .lower_fmod = true,
85 .lower_fdiv = true,
86 .lower_isign = true,
87 .lower_ldexp = true,
88 .lower_uadd_carry = true,
89 .lower_usub_borrow = true,
90 .lower_mul_high = true,
91 .lower_mul_2x32_64 = true,
92 .fuse_ffma = true,
93 .vertex_id_zero_based = false,
94 .lower_extract_byte = true,
95 .lower_extract_word = true,
96 .lower_all_io_to_elements = true,
97 .lower_helper_invocation = true,
98 .lower_bitfield_insert_to_shifts = true,
99 .lower_bitfield_extract_to_shifts = true,
100 .lower_pack_half_2x16 = true,
101 .lower_pack_snorm_4x8 = true,
102 .lower_pack_snorm_2x16 = true,
103 .lower_pack_unorm_4x8 = true,
104 .lower_pack_unorm_2x16 = true,
105 .lower_unpack_half_2x16 = true,
106 .lower_unpack_snorm_4x8 = true,
107 .lower_unpack_snorm_2x16 = true,
108 .lower_unpack_unorm_4x8 = true,
109 .lower_unpack_unorm_2x16 = true,
110 .lower_pack_split = true,
111 .use_interpolated_input_intrinsics = true,
112 .lower_rotate = true,
113 .vectorize_io = true,
114 .lower_to_scalar = true,
115 .has_imul24 = true,
116 .max_unroll_iterations = 32,
117 .lower_wpos_pntc = true,
118 };
119
120 const nir_shader_compiler_options *
121 ir3_get_compiler_options(struct ir3_compiler *compiler)
122 {
123 if (compiler->gpu_id >= 600)
124 return &options_a6xx;
125 return &options;
126 }
127
128 #define OPT(nir, pass, ...) ({ \
129 bool this_progress = false; \
130 NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__); \
131 this_progress; \
132 })
133
134 #define OPT_V(nir, pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
135
136 static void
137 ir3_optimize_loop(nir_shader *s)
138 {
139 bool progress;
140 unsigned lower_flrp =
141 (s->options->lower_flrp16 ? 16 : 0) |
142 (s->options->lower_flrp32 ? 32 : 0) |
143 (s->options->lower_flrp64 ? 64 : 0);
144
145 do {
146 progress = false;
147
148 OPT_V(s, nir_lower_vars_to_ssa);
149 progress |= OPT(s, nir_opt_copy_prop_vars);
150 progress |= OPT(s, nir_opt_dead_write_vars);
151 progress |= OPT(s, nir_lower_alu_to_scalar, NULL, NULL);
152 progress |= OPT(s, nir_lower_phis_to_scalar);
153
154 progress |= OPT(s, nir_copy_prop);
155 progress |= OPT(s, nir_opt_dce);
156 progress |= OPT(s, nir_opt_cse);
157 static int gcm = -1;
158 if (gcm == -1)
159 gcm = env_var_as_unsigned("GCM", 0);
160 if (gcm == 1)
161 progress |= OPT(s, nir_opt_gcm, true);
162 else if (gcm == 2)
163 progress |= OPT(s, nir_opt_gcm, false);
164 progress |= OPT(s, nir_opt_peephole_select, 16, true, true);
165 progress |= OPT(s, nir_opt_intrinsics);
166 progress |= OPT(s, nir_opt_algebraic);
167 progress |= OPT(s, nir_lower_alu);
168 progress |= OPT(s, nir_lower_pack);
169 progress |= OPT(s, nir_opt_constant_folding);
170
171 if (lower_flrp != 0) {
172 if (OPT(s, nir_lower_flrp,
173 lower_flrp,
174 false /* always_precise */,
175 s->options->lower_ffma)) {
176 OPT(s, nir_opt_constant_folding);
177 progress = true;
178 }
179
180 /* Nothing should rematerialize any flrps, so we only
181 * need to do this lowering once.
182 */
183 lower_flrp = 0;
184 }
185
186 progress |= OPT(s, nir_opt_dead_cf);
187 if (OPT(s, nir_opt_trivial_continues)) {
188 progress |= true;
189 /* If nir_opt_trivial_continues makes progress, then we need to clean
190 * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
191 * to make progress.
192 */
193 OPT(s, nir_copy_prop);
194 OPT(s, nir_opt_dce);
195 }
196 progress |= OPT(s, nir_opt_if, false);
197 progress |= OPT(s, nir_opt_loop_unroll, nir_var_all);
198 progress |= OPT(s, nir_opt_remove_phis);
199 progress |= OPT(s, nir_opt_undef);
200 } while (progress);
201 }
202
203 static bool
204 should_split_wrmask(const nir_instr *instr, const void *data)
205 {
206 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
207
208 switch (intr->intrinsic) {
209 case nir_intrinsic_store_ssbo:
210 case nir_intrinsic_store_shared:
211 case nir_intrinsic_store_global:
212 return true;
213 default:
214 return false;
215 }
216 }
217
218 void
219 ir3_finalize_nir(struct ir3_compiler *compiler, nir_shader *s)
220 {
221 struct nir_lower_tex_options tex_options = {
222 .lower_rect = 0,
223 .lower_tg4_offsets = true,
224 };
225
226 if (compiler->gpu_id >= 400) {
227 /* a4xx seems to have *no* sam.p */
228 tex_options.lower_txp = ~0; /* lower all txp */
229 } else {
230 /* a3xx just needs to avoid sam.p for 3d tex */
231 tex_options.lower_txp = (1 << GLSL_SAMPLER_DIM_3D);
232 }
233
234 if (ir3_shader_debug & IR3_DBG_DISASM) {
235 debug_printf("----------------------\n");
236 nir_print_shader(s, stdout);
237 debug_printf("----------------------\n");
238 }
239
240 if (s->info.stage == MESA_SHADER_GEOMETRY)
241 NIR_PASS_V(s, ir3_nir_lower_gs);
242
243 NIR_PASS_V(s, nir_lower_io_arrays_to_elements_no_indirects, false);
244
245 NIR_PASS_V(s, nir_lower_amul, ir3_glsl_type_size);
246
247 OPT_V(s, nir_lower_regs_to_ssa);
248 OPT_V(s, nir_lower_wrmasks, should_split_wrmask, s);
249
250 OPT_V(s, nir_lower_tex, &tex_options);
251 OPT_V(s, nir_lower_load_const_to_scalar);
252 if (compiler->gpu_id < 500)
253 OPT_V(s, ir3_nir_lower_tg4_to_tex);
254
255 ir3_optimize_loop(s);
256
257 /* do idiv lowering after first opt loop to get a chance to propagate
258 * constants for divide by immed power-of-two:
259 */
260 const bool idiv_progress = OPT(s, nir_lower_idiv, nir_lower_idiv_fast);
261
262 if (idiv_progress)
263 ir3_optimize_loop(s);
264
265 OPT_V(s, nir_remove_dead_variables, nir_var_function_temp, NULL);
266
267 if (ir3_shader_debug & IR3_DBG_DISASM) {
268 debug_printf("----------------------\n");
269 nir_print_shader(s, stdout);
270 debug_printf("----------------------\n");
271 }
272
273 nir_sweep(s);
274 }
275
276 /**
277 * Late passes that need to be done after pscreen->finalize_nir()
278 */
279 void
280 ir3_nir_post_finalize(struct ir3_compiler *compiler, nir_shader *s)
281 {
282 NIR_PASS_V(s, nir_lower_io, nir_var_shader_in | nir_var_shader_out,
283 ir3_glsl_type_size, (nir_lower_io_options)0);
284
285 if (s->info.stage == MESA_SHADER_FRAGMENT) {
286 /* NOTE: lower load_barycentric_at_sample first, since it
287 * produces load_barycentric_at_offset:
288 */
289 NIR_PASS_V(s, ir3_nir_lower_load_barycentric_at_sample);
290 NIR_PASS_V(s, ir3_nir_lower_load_barycentric_at_offset);
291 NIR_PASS_V(s, ir3_nir_move_varying_inputs);
292 NIR_PASS_V(s, nir_lower_fb_read);
293 }
294
295 if (compiler->gpu_id >= 600 &&
296 s->info.stage == MESA_SHADER_FRAGMENT &&
297 !(ir3_shader_debug & IR3_DBG_NOFP16)) {
298 NIR_PASS_V(s, nir_lower_mediump_outputs);
299 }
300
301 /* we cannot ensure that ir3_finalize_nir() is only called once, so
302 * we also need to do trig workarounds here:
303 */
304 OPT_V(s, ir3_nir_apply_trig_workarounds);
305
306 ir3_optimize_loop(s);
307 }
308
309 static bool
310 ir3_nir_lower_layer_id(nir_shader *nir)
311 {
312 unsigned layer_id_loc = ~0;
313 nir_foreach_shader_in_variable(var, nir) {
314 if (var->data.location == VARYING_SLOT_LAYER) {
315 layer_id_loc = var->data.driver_location;
316 break;
317 }
318 }
319
320 assert(layer_id_loc != ~0);
321
322 bool progress = false;
323 nir_builder b;
324
325 nir_foreach_function(func, nir) {
326 nir_builder_init(&b, func->impl);
327
328 nir_foreach_block(block, func->impl) {
329 nir_foreach_instr_safe(instr, block) {
330 if (instr->type != nir_instr_type_intrinsic)
331 continue;
332
333 nir_intrinsic_instr *intrin =
334 nir_instr_as_intrinsic(instr);
335
336 if (intrin->intrinsic != nir_intrinsic_load_input)
337 continue;
338
339 unsigned base = nir_intrinsic_base(intrin);
340 if (base != layer_id_loc)
341 continue;
342
343 b.cursor = nir_before_instr(&intrin->instr);
344 nir_ssa_def *zero = nir_imm_int(&b, 0);
345 nir_ssa_def_rewrite_uses(&intrin->dest.ssa,
346 nir_src_for_ssa(zero));
347 nir_instr_remove(&intrin->instr);
348 progress = true;
349 }
350 }
351
352 if (progress) {
353 nir_metadata_preserve(func->impl,
354 nir_metadata_block_index |
355 nir_metadata_dominance);
356 } else {
357 nir_metadata_preserve(func->impl, nir_metadata_all);
358 }
359 }
360
361 return progress;
362 }
363
364 void
365 ir3_nir_lower_variant(struct ir3_shader_variant *so, nir_shader *s)
366 {
367 if (ir3_shader_debug & IR3_DBG_DISASM) {
368 debug_printf("----------------------\n");
369 nir_print_shader(s, stdout);
370 debug_printf("----------------------\n");
371 }
372
373 bool progress = false;
374
375 if (so->key.has_gs || so->key.tessellation) {
376 switch (so->shader->type) {
377 case MESA_SHADER_VERTEX:
378 NIR_PASS_V(s, ir3_nir_lower_to_explicit_output, so, so->key.tessellation);
379 progress = true;
380 break;
381 case MESA_SHADER_TESS_CTRL:
382 NIR_PASS_V(s, ir3_nir_lower_tess_ctrl, so, so->key.tessellation);
383 NIR_PASS_V(s, ir3_nir_lower_to_explicit_input, so->shader->compiler);
384 progress = true;
385 break;
386 case MESA_SHADER_TESS_EVAL:
387 NIR_PASS_V(s, ir3_nir_lower_tess_eval, so->key.tessellation);
388 if (so->key.has_gs)
389 NIR_PASS_V(s, ir3_nir_lower_to_explicit_output, so, so->key.tessellation);
390 progress = true;
391 break;
392 case MESA_SHADER_GEOMETRY:
393 NIR_PASS_V(s, ir3_nir_lower_to_explicit_input, so->shader->compiler);
394 progress = true;
395 break;
396 default:
397 break;
398 }
399 }
400
401 if (s->info.stage == MESA_SHADER_VERTEX) {
402 if (so->key.ucp_enables)
403 progress |= OPT(s, nir_lower_clip_vs, so->key.ucp_enables, false, false, NULL);
404 if (so->key.vclamp_color)
405 progress |= OPT(s, nir_lower_clamp_color_outputs);
406 } else if (s->info.stage == MESA_SHADER_FRAGMENT) {
407 if (so->key.ucp_enables)
408 progress |= OPT(s, nir_lower_clip_fs, so->key.ucp_enables, false);
409 if (so->key.fclamp_color)
410 progress |= OPT(s, nir_lower_clamp_color_outputs);
411 if (so->key.layer_zero && (s->info.inputs_read & VARYING_BIT_LAYER))
412 progress |= OPT(s, ir3_nir_lower_layer_id);
413 }
414 if (so->key.color_two_side) {
415 OPT_V(s, nir_lower_two_sided_color, true);
416 progress = true;
417 }
418
419 struct nir_lower_tex_options tex_options = { };
420
421 switch (so->shader->type) {
422 case MESA_SHADER_FRAGMENT:
423 tex_options.saturate_s = so->key.fsaturate_s;
424 tex_options.saturate_t = so->key.fsaturate_t;
425 tex_options.saturate_r = so->key.fsaturate_r;
426 break;
427 case MESA_SHADER_VERTEX:
428 tex_options.saturate_s = so->key.vsaturate_s;
429 tex_options.saturate_t = so->key.vsaturate_t;
430 tex_options.saturate_r = so->key.vsaturate_r;
431 break;
432 default:
433 /* TODO */
434 break;
435 }
436
437 if (tex_options.saturate_s || tex_options.saturate_t ||
438 tex_options.saturate_r) {
439 progress |= OPT(s, nir_lower_tex, &tex_options);
440 }
441
442 if (!so->binning_pass)
443 OPT_V(s, ir3_nir_analyze_ubo_ranges, so);
444
445 progress |= OPT(s, ir3_nir_lower_ubo_loads, so);
446
447 /* UBO offset lowering has to come after we've decided what will
448 * be left as load_ubo
449 */
450 OPT_V(s, ir3_nir_lower_io_offsets, so->shader->compiler->gpu_id);
451
452 if (progress)
453 ir3_optimize_loop(s);
454
455 /* Do late algebraic optimization to turn add(a, neg(b)) back into
456 * subs, then the mandatory cleanup after algebraic. Note that it may
457 * produce fnegs, and if so then we need to keep running to squash
458 * fneg(fneg(a)).
459 */
460 bool more_late_algebraic = true;
461 while (more_late_algebraic) {
462 more_late_algebraic = OPT(s, nir_opt_algebraic_late);
463 OPT_V(s, nir_opt_constant_folding);
464 OPT_V(s, nir_copy_prop);
465 OPT_V(s, nir_opt_dce);
466 OPT_V(s, nir_opt_cse);
467 }
468
469 OPT_V(s, nir_opt_sink, nir_move_const_undef);
470
471 if (ir3_shader_debug & IR3_DBG_DISASM) {
472 debug_printf("----------------------\n");
473 nir_print_shader(s, stdout);
474 debug_printf("----------------------\n");
475 }
476
477 nir_sweep(s);
478
479 /* Binning pass variants re-use the const_state of the corresponding
480 * draw pass shader, so that same const emit can be re-used for both
481 * passes:
482 */
483 if (!so->binning_pass)
484 ir3_setup_const_state(s, so, ir3_const_state(so));
485 }
486
487 static void
488 ir3_nir_scan_driver_consts(nir_shader *shader,
489 struct ir3_const_state *layout)
490 {
491 nir_foreach_function (function, shader) {
492 if (!function->impl)
493 continue;
494
495 nir_foreach_block (block, function->impl) {
496 nir_foreach_instr (instr, block) {
497 if (instr->type != nir_instr_type_intrinsic)
498 continue;
499
500 nir_intrinsic_instr *intr =
501 nir_instr_as_intrinsic(instr);
502 unsigned idx;
503
504 switch (intr->intrinsic) {
505 case nir_intrinsic_get_buffer_size:
506 if (ir3_bindless_resource(intr->src[0]))
507 break;
508 idx = nir_src_as_uint(intr->src[0]);
509 if (layout->ssbo_size.mask & (1 << idx))
510 break;
511 layout->ssbo_size.mask |= (1 << idx);
512 layout->ssbo_size.off[idx] =
513 layout->ssbo_size.count;
514 layout->ssbo_size.count += 1; /* one const per */
515 break;
516 case nir_intrinsic_image_atomic_add:
517 case nir_intrinsic_image_atomic_imin:
518 case nir_intrinsic_image_atomic_umin:
519 case nir_intrinsic_image_atomic_imax:
520 case nir_intrinsic_image_atomic_umax:
521 case nir_intrinsic_image_atomic_and:
522 case nir_intrinsic_image_atomic_or:
523 case nir_intrinsic_image_atomic_xor:
524 case nir_intrinsic_image_atomic_exchange:
525 case nir_intrinsic_image_atomic_comp_swap:
526 case nir_intrinsic_image_store:
527 case nir_intrinsic_image_size:
528 idx = nir_src_as_uint(intr->src[0]);
529 if (layout->image_dims.mask & (1 << idx))
530 break;
531 layout->image_dims.mask |= (1 << idx);
532 layout->image_dims.off[idx] =
533 layout->image_dims.count;
534 layout->image_dims.count += 3; /* three const per */
535 break;
536 case nir_intrinsic_load_base_vertex:
537 case nir_intrinsic_load_first_vertex:
538 layout->num_driver_params =
539 MAX2(layout->num_driver_params, IR3_DP_VTXID_BASE + 1);
540 break;
541 case nir_intrinsic_load_base_instance:
542 layout->num_driver_params =
543 MAX2(layout->num_driver_params, IR3_DP_INSTID_BASE + 1);
544 break;
545 case nir_intrinsic_load_user_clip_plane:
546 idx = nir_intrinsic_ucp_id(intr);
547 layout->num_driver_params =
548 MAX2(layout->num_driver_params, IR3_DP_UCP0_X + (idx + 1) * 4);
549 break;
550 case nir_intrinsic_load_num_work_groups:
551 layout->num_driver_params =
552 MAX2(layout->num_driver_params, IR3_DP_NUM_WORK_GROUPS_Z + 1);
553 break;
554 case nir_intrinsic_load_local_group_size:
555 layout->num_driver_params =
556 MAX2(layout->num_driver_params, IR3_DP_LOCAL_GROUP_SIZE_Z + 1);
557 break;
558 default:
559 break;
560 }
561 }
562 }
563 }
564 }
565
566 /* Sets up the variant-dependent constant state for the ir3_shader. Note
567 * that it is also used from ir3_nir_analyze_ubo_ranges() to figure out the
568 * maximum number of driver params that would eventually be used, to leave
569 * space for this function to allocate the driver params.
570 */
571 void
572 ir3_setup_const_state(nir_shader *nir, struct ir3_shader_variant *v,
573 struct ir3_const_state *const_state)
574 {
575 struct ir3_compiler *compiler = v->shader->compiler;
576
577 memset(&const_state->offsets, ~0, sizeof(const_state->offsets));
578
579 ir3_nir_scan_driver_consts(nir, const_state);
580
581 if ((compiler->gpu_id < 500) &&
582 (v->shader->stream_output.num_outputs > 0)) {
583 const_state->num_driver_params =
584 MAX2(const_state->num_driver_params, IR3_DP_VTXCNT_MAX + 1);
585 }
586
587 const_state->num_ubos = nir->info.num_ubos;
588
589 /* num_driver_params is scalar, align to vec4: */
590 const_state->num_driver_params = align(const_state->num_driver_params, 4);
591
592 debug_assert((const_state->ubo_state.size % 16) == 0);
593 unsigned constoff = const_state->ubo_state.size / 16;
594 unsigned ptrsz = ir3_pointer_size(compiler);
595
596 if (const_state->num_ubos > 0) {
597 const_state->offsets.ubo = constoff;
598 constoff += align(const_state->num_ubos * ptrsz, 4) / 4;
599 }
600
601 if (const_state->ssbo_size.count > 0) {
602 unsigned cnt = const_state->ssbo_size.count;
603 const_state->offsets.ssbo_sizes = constoff;
604 constoff += align(cnt, 4) / 4;
605 }
606
607 if (const_state->image_dims.count > 0) {
608 unsigned cnt = const_state->image_dims.count;
609 const_state->offsets.image_dims = constoff;
610 constoff += align(cnt, 4) / 4;
611 }
612
613 if (const_state->num_driver_params > 0) {
614 /* offset cannot be 0 for vs params loaded by CP_DRAW_INDIRECT_MULTI */
615 if (v->type == MESA_SHADER_VERTEX && compiler->gpu_id >= 600)
616 constoff = MAX2(constoff, 1);
617 const_state->offsets.driver_param = constoff;
618 }
619 constoff += const_state->num_driver_params / 4;
620
621 if ((v->type == MESA_SHADER_VERTEX) &&
622 (compiler->gpu_id < 500) &&
623 v->shader->stream_output.num_outputs > 0) {
624 const_state->offsets.tfbo = constoff;
625 constoff += align(IR3_MAX_SO_BUFFERS * ptrsz, 4) / 4;
626 }
627
628 switch (v->type) {
629 case MESA_SHADER_VERTEX:
630 const_state->offsets.primitive_param = constoff;
631 constoff += 1;
632 break;
633 case MESA_SHADER_TESS_CTRL:
634 case MESA_SHADER_TESS_EVAL:
635 constoff = align(constoff - 1, 4) + 3;
636 const_state->offsets.primitive_param = constoff;
637 const_state->offsets.primitive_map = constoff + 5;
638 constoff += 5 + DIV_ROUND_UP(nir->num_inputs, 4);
639 break;
640 case MESA_SHADER_GEOMETRY:
641 const_state->offsets.primitive_param = constoff;
642 const_state->offsets.primitive_map = constoff + 1;
643 constoff += 1 + DIV_ROUND_UP(nir->num_inputs, 4);
644 break;
645 default:
646 break;
647 }
648
649 const_state->offsets.immediate = constoff;
650
651 assert(constoff <= ir3_max_const(v));
652 }