src/freedreno/ir3/ir3_nir.c

   1 /*
   2  * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27
  28 #include "util/debug.h"
  29
  30 #include "ir3_nir.h"
  31 #include "ir3_compiler.h"
  32 #include "ir3_shader.h"
  33
  34 static const nir_shader_compiler_options options = {
  35                 .lower_fpow = true,
  36                 .lower_scmp = true,
  37                 .lower_flrp32 = true,
  38                 .lower_flrp64 = true,
  39                 .lower_ffract = true,
  40                 .lower_fmod32 = true,
  41                 .lower_fmod64 = true,
  42                 .lower_fdiv = true,
  43                 .lower_isign = true,
  44                 .lower_ldexp = true,
  45                 .lower_uadd_carry = true,
  46                 .lower_mul_high = true,
  47                 .fuse_ffma = true,
  48                 .native_integers = true,
  49                 .vertex_id_zero_based = true,
  50                 .lower_extract_byte = true,
  51                 .lower_extract_word = true,
  52                 .lower_all_io_to_temps = true,
  53                 .lower_helper_invocation = true,
  54 };
  55
  56 /* we don't want to lower vertex_id to _zero_based on newer gpus: */
  57 static const nir_shader_compiler_options options_a6xx = {
  58                 .lower_fpow = true,
  59                 .lower_scmp = true,
  60                 .lower_flrp32 = true,
  61                 .lower_flrp64 = true,
  62                 .lower_ffract = true,
  63                 .lower_fmod32 = true,
  64                 .lower_fmod64 = true,
  65                 .lower_fdiv = true,
  66                 .lower_isign = true,
  67                 .lower_ldexp = true,
  68                 .lower_uadd_carry = true,
  69                 .lower_mul_high = true,
  70                 .fuse_ffma = true,
  71                 .native_integers = true,
  72                 .vertex_id_zero_based = false,
  73                 .lower_extract_byte = true,
  74                 .lower_extract_word = true,
  75                 .lower_all_io_to_temps = true,
  76                 .lower_helper_invocation = true,
  77 };
  78
  79 const nir_shader_compiler_options *
  80 ir3_get_compiler_options(struct ir3_compiler *compiler)
  81 {
  82         if (compiler->gpu_id >= 600)
  83                 return &options_a6xx;
  84         return &options;
  85 }
  86
  87 /* for given shader key, are any steps handled in nir? */
  88 bool
  89 ir3_key_lowers_nir(const struct ir3_shader_key *key)
  90 {
  91         return key->fsaturate_s | key->fsaturate_t | key->fsaturate_r |
  92                         key->vsaturate_s | key->vsaturate_t | key->vsaturate_r |
  93                         key->ucp_enables | key->color_two_side |
  94                         key->fclamp_color | key->vclamp_color;
  95 }
  96
  97 #define OPT(nir, pass, ...) ({                             \
  98    bool this_progress = false;                             \
  99    NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__);      \
 100    this_progress;                                          \
 101 })
 102
 103 #define OPT_V(nir, pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
 104
 105 static void
 106 ir3_optimize_loop(nir_shader *s)
 107 {
 108         bool progress;
 109         do {
 110                 progress = false;
 111
 112                 OPT_V(s, nir_lower_vars_to_ssa);
 113                 progress |= OPT(s, nir_opt_copy_prop_vars);
 114                 progress |= OPT(s, nir_opt_dead_write_vars);
 115                 progress |= OPT(s, nir_lower_alu_to_scalar);
 116                 progress |= OPT(s, nir_lower_phis_to_scalar);
 117
 118                 progress |= OPT(s, nir_copy_prop);
 119                 progress |= OPT(s, nir_opt_dce);
 120                 progress |= OPT(s, nir_opt_cse);
 121                 static int gcm = -1;
 122                 if (gcm == -1)
 123                         gcm = env_var_as_unsigned("GCM", 0);
 124                 if (gcm == 1)
 125                         progress |= OPT(s, nir_opt_gcm, true);
 126                 else if (gcm == 2)
 127                         progress |= OPT(s, nir_opt_gcm, false);
 128                 progress |= OPT(s, nir_opt_peephole_select, 16, true, true);
 129                 progress |= OPT(s, nir_opt_intrinsics);
 130                 progress |= OPT(s, nir_opt_algebraic);
 131                 progress |= OPT(s, nir_opt_constant_folding);
 132                 progress |= OPT(s, nir_opt_dead_cf);
 133                 if (OPT(s, nir_opt_trivial_continues)) {
 134                         progress |= true;
 135                         /* If nir_opt_trivial_continues makes progress, then we need to clean
 136                          * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
 137                          * to make progress.
 138                          */
 139                         OPT(s, nir_copy_prop);
 140                         OPT(s, nir_opt_dce);
 141                 }
 142                 progress |= OPT(s, nir_opt_if);
 143                 progress |= OPT(s, nir_opt_remove_phis);
 144                 progress |= OPT(s, nir_opt_undef);
 145
 146         } while (progress);
 147 }
 148
 149 struct nir_shader *
 150 ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
 151                 const struct ir3_shader_key *key)
 152 {
 153         struct nir_lower_tex_options tex_options = {
 154                         .lower_rect = 0,
 155                         .lower_tg4_offsets = true,
 156         };
 157
 158         if (key) {
 159                 switch (shader->type) {
 160                 case MESA_SHADER_FRAGMENT:
 161                         tex_options.saturate_s = key->fsaturate_s;
 162                         tex_options.saturate_t = key->fsaturate_t;
 163                         tex_options.saturate_r = key->fsaturate_r;
 164                         break;
 165                 case MESA_SHADER_VERTEX:
 166                         tex_options.saturate_s = key->vsaturate_s;
 167                         tex_options.saturate_t = key->vsaturate_t;
 168                         tex_options.saturate_r = key->vsaturate_r;
 169                         break;
 170                 default:
 171                         /* TODO */
 172                         break;
 173                 }
 174         }
 175
 176         if (shader->compiler->gpu_id >= 400) {
 177                 /* a4xx seems to have *no* sam.p */
 178                 tex_options.lower_txp = ~0;  /* lower all txp */
 179         } else {
 180                 /* a3xx just needs to avoid sam.p for 3d tex */
 181                 tex_options.lower_txp = (1 << GLSL_SAMPLER_DIM_3D);
 182         }
 183
 184         if (ir3_shader_debug & IR3_DBG_DISASM) {
 185                 debug_printf("----------------------\n");
 186                 nir_print_shader(s, stdout);
 187                 debug_printf("----------------------\n");
 188         }
 189
 190         OPT_V(s, nir_opt_global_to_local);
 191         OPT_V(s, nir_lower_regs_to_ssa);
 192         OPT_V(s, ir3_nir_lower_io_offsets);
 193
 194         if (key) {
 195                 if (s->info.stage == MESA_SHADER_VERTEX) {
 196                         OPT_V(s, nir_lower_clip_vs, key->ucp_enables, false);
 197                         if (key->vclamp_color)
 198                                 OPT_V(s, nir_lower_clamp_color_outputs);
 199                 } else if (s->info.stage == MESA_SHADER_FRAGMENT) {
 200                         OPT_V(s, nir_lower_clip_fs, key->ucp_enables);
 201                         if (key->fclamp_color)
 202                                 OPT_V(s, nir_lower_clamp_color_outputs);
 203                 }
 204                 if (key->color_two_side) {
 205                         OPT_V(s, nir_lower_two_sided_color);
 206                 }
 207         } else {
 208                 /* only want to do this the first time (when key is null)
 209                  * and not again on any potential 2nd variant lowering pass:
 210                  */
 211                 OPT_V(s, ir3_nir_apply_trig_workarounds);
 212         }
 213
 214         OPT_V(s, nir_lower_tex, &tex_options);
 215         OPT_V(s, nir_lower_load_const_to_scalar);
 216         if (shader->compiler->gpu_id < 500)
 217                 OPT_V(s, ir3_nir_lower_tg4_to_tex);
 218
 219         ir3_optimize_loop(s);
 220
 221         /* do idiv lowering after first opt loop to give a chance for
 222          * divide by immed power-of-two to be caught first:
 223          */
 224         if (OPT(s, nir_lower_idiv))
 225                 ir3_optimize_loop(s);
 226
 227         OPT_V(s, nir_remove_dead_variables, nir_var_function_temp);
 228
 229         OPT_V(s, nir_move_load_const);
 230
 231         if (ir3_shader_debug & IR3_DBG_DISASM) {
 232                 debug_printf("----------------------\n");
 233                 nir_print_shader(s, stdout);
 234                 debug_printf("----------------------\n");
 235         }
 236
 237         nir_sweep(s);
 238
 239         return s;
 240 }
 241
 242 void
 243 ir3_nir_scan_driver_consts(nir_shader *shader,
 244                 struct ir3_driver_const_layout *layout)
 245 {
 246         nir_foreach_function(function, shader) {
 247                 if (!function->impl)
 248                         continue;
 249
 250                 nir_foreach_block(block, function->impl) {
 251                         nir_foreach_instr(instr, block) {
 252                                 if (instr->type != nir_instr_type_intrinsic)
 253                                         continue;
 254
 255                                 nir_intrinsic_instr *intr =
 256                                         nir_instr_as_intrinsic(instr);
 257                                 unsigned idx;
 258
 259                                 switch (intr->intrinsic) {
 260                                 case nir_intrinsic_get_buffer_size:
 261                                         idx = nir_src_as_const_value(intr->src[0])->u32[0];
 262                                         if (layout->ssbo_size.mask & (1 << idx))
 263                                                 break;
 264                                         layout->ssbo_size.mask |= (1 << idx);
 265                                         layout->ssbo_size.off[idx] =
 266                                                 layout->ssbo_size.count;
 267                                         layout->ssbo_size.count += 1; /* one const per */
 268                                         break;
 269                                 case nir_intrinsic_image_deref_atomic_add:
 270                                 case nir_intrinsic_image_deref_atomic_min:
 271                                 case nir_intrinsic_image_deref_atomic_max:
 272                                 case nir_intrinsic_image_deref_atomic_and:
 273                                 case nir_intrinsic_image_deref_atomic_or:
 274                                 case nir_intrinsic_image_deref_atomic_xor:
 275                                 case nir_intrinsic_image_deref_atomic_exchange:
 276                                 case nir_intrinsic_image_deref_atomic_comp_swap:
 277                                 case nir_intrinsic_image_deref_store:
 278                                 case nir_intrinsic_image_deref_size:
 279                                         idx = nir_intrinsic_get_var(intr, 0)->data.driver_location;
 280                                         if (layout->image_dims.mask & (1 << idx))
 281                                                 break;
 282                                         layout->image_dims.mask |= (1 << idx);
 283                                         layout->image_dims.off[idx] =
 284                                                 layout->image_dims.count;
 285                                         layout->image_dims.count += 3; /* three const per */
 286                                         break;
 287                                 default:
 288                                         break;
 289                                 }
 290                         }
 291                 }
 292         }
 293 }