src/freedreno/ir3/ir3_nir.c

   1 /*
   2  * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27
  28 #include "util/debug.h"
  29
  30 #include "ir3_nir.h"
  31 #include "ir3_compiler.h"
  32 #include "ir3_shader.h"
  33
  34 static const nir_shader_compiler_options options = {
  35                 .lower_fpow = true,
  36                 .lower_scmp = true,
  37                 .lower_flrp32 = true,
  38                 .lower_flrp64 = true,
  39                 .lower_ffract = true,
  40                 .lower_fmod32 = true,
  41                 .lower_fmod64 = true,
  42                 .lower_fdiv = true,
  43                 .lower_isign = true,
  44                 .lower_ldexp = true,
  45                 .lower_uadd_carry = true,
  46                 .lower_mul_high = true,
  47                 .fuse_ffma = true,
  48                 .native_integers = true,
  49                 .vertex_id_zero_based = true,
  50                 .lower_extract_byte = true,
  51                 .lower_extract_word = true,
  52                 .lower_all_io_to_temps = true,
  53                 .lower_helper_invocation = true,
  54                 .lower_bitfield_insert_to_shifts = true,
  55                 .lower_bitfield_extract_to_shifts = true,
  56                 .lower_bfm = true,
  57 };
  58
  59 /* we don't want to lower vertex_id to _zero_based on newer gpus: */
  60 static const nir_shader_compiler_options options_a6xx = {
  61                 .lower_fpow = true,
  62                 .lower_scmp = true,
  63                 .lower_flrp32 = true,
  64                 .lower_flrp64 = true,
  65                 .lower_ffract = true,
  66                 .lower_fmod32 = true,
  67                 .lower_fmod64 = true,
  68                 .lower_fdiv = true,
  69                 .lower_isign = true,
  70                 .lower_ldexp = true,
  71                 .lower_uadd_carry = true,
  72                 .lower_mul_high = true,
  73                 .fuse_ffma = true,
  74                 .native_integers = true,
  75                 .vertex_id_zero_based = false,
  76                 .lower_extract_byte = true,
  77                 .lower_extract_word = true,
  78                 .lower_all_io_to_temps = true,
  79                 .lower_helper_invocation = true,
  80                 .lower_bitfield_insert_to_shifts = true,
  81                 .lower_bitfield_extract_to_shifts = true,
  82                 .lower_bfm = true,
  83 };
  84
  85 const nir_shader_compiler_options *
  86 ir3_get_compiler_options(struct ir3_compiler *compiler)
  87 {
  88         if (compiler->gpu_id >= 600)
  89                 return &options_a6xx;
  90         return &options;
  91 }
  92
  93 /* for given shader key, are any steps handled in nir? */
  94 bool
  95 ir3_key_lowers_nir(const struct ir3_shader_key *key)
  96 {
  97         return key->fsaturate_s | key->fsaturate_t | key->fsaturate_r |
  98                         key->vsaturate_s | key->vsaturate_t | key->vsaturate_r |
  99                         key->ucp_enables | key->color_two_side |
 100                         key->fclamp_color | key->vclamp_color;
 101 }
 102
 103 #define OPT(nir, pass, ...) ({                             \
 104    bool this_progress = false;                             \
 105    NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__);      \
 106    this_progress;                                          \
 107 })
 108
 109 #define OPT_V(nir, pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
 110
 111 static void
 112 ir3_optimize_loop(nir_shader *s)
 113 {
 114         bool progress;
 115         do {
 116                 progress = false;
 117
 118                 OPT_V(s, nir_lower_vars_to_ssa);
 119                 progress |= OPT(s, nir_opt_copy_prop_vars);
 120                 progress |= OPT(s, nir_opt_dead_write_vars);
 121                 progress |= OPT(s, nir_lower_alu_to_scalar);
 122                 progress |= OPT(s, nir_lower_phis_to_scalar);
 123
 124                 progress |= OPT(s, nir_copy_prop);
 125                 progress |= OPT(s, nir_opt_dce);
 126                 progress |= OPT(s, nir_opt_cse);
 127                 static int gcm = -1;
 128                 if (gcm == -1)
 129                         gcm = env_var_as_unsigned("GCM", 0);
 130                 if (gcm == 1)
 131                         progress |= OPT(s, nir_opt_gcm, true);
 132                 else if (gcm == 2)
 133                         progress |= OPT(s, nir_opt_gcm, false);
 134                 progress |= OPT(s, nir_opt_peephole_select, 16, true, true);
 135                 progress |= OPT(s, nir_opt_intrinsics);
 136                 progress |= OPT(s, nir_opt_algebraic);
 137                 progress |= OPT(s, nir_opt_constant_folding);
 138                 progress |= OPT(s, nir_opt_dead_cf);
 139                 if (OPT(s, nir_opt_trivial_continues)) {
 140                         progress |= true;
 141                         /* If nir_opt_trivial_continues makes progress, then we need to clean
 142                          * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
 143                          * to make progress.
 144                          */
 145                         OPT(s, nir_copy_prop);
 146                         OPT(s, nir_opt_dce);
 147                 }
 148                 progress |= OPT(s, nir_opt_if);
 149                 progress |= OPT(s, nir_opt_remove_phis);
 150                 progress |= OPT(s, nir_opt_undef);
 151
 152         } while (progress);
 153 }
 154
 155 struct nir_shader *
 156 ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
 157                 const struct ir3_shader_key *key)
 158 {
 159         struct nir_lower_tex_options tex_options = {
 160                         .lower_rect = 0,
 161                         .lower_tg4_offsets = true,
 162         };
 163
 164         if (key) {
 165                 switch (shader->type) {
 166                 case MESA_SHADER_FRAGMENT:
 167                         tex_options.saturate_s = key->fsaturate_s;
 168                         tex_options.saturate_t = key->fsaturate_t;
 169                         tex_options.saturate_r = key->fsaturate_r;
 170                         break;
 171                 case MESA_SHADER_VERTEX:
 172                         tex_options.saturate_s = key->vsaturate_s;
 173                         tex_options.saturate_t = key->vsaturate_t;
 174                         tex_options.saturate_r = key->vsaturate_r;
 175                         break;
 176                 default:
 177                         /* TODO */
 178                         break;
 179                 }
 180         }
 181
 182         if (shader->compiler->gpu_id >= 400) {
 183                 /* a4xx seems to have *no* sam.p */
 184                 tex_options.lower_txp = ~0;  /* lower all txp */
 185         } else {
 186                 /* a3xx just needs to avoid sam.p for 3d tex */
 187                 tex_options.lower_txp = (1 << GLSL_SAMPLER_DIM_3D);
 188         }
 189
 190         if (ir3_shader_debug & IR3_DBG_DISASM) {
 191                 debug_printf("----------------------\n");
 192                 nir_print_shader(s, stdout);
 193                 debug_printf("----------------------\n");
 194         }
 195
 196         OPT_V(s, nir_opt_global_to_local);
 197         OPT_V(s, nir_lower_regs_to_ssa);
 198         OPT_V(s, ir3_nir_lower_io_offsets);
 199
 200         if (key) {
 201                 if (s->info.stage == MESA_SHADER_VERTEX) {
 202                         OPT_V(s, nir_lower_clip_vs, key->ucp_enables, false);
 203                         if (key->vclamp_color)
 204                                 OPT_V(s, nir_lower_clamp_color_outputs);
 205                 } else if (s->info.stage == MESA_SHADER_FRAGMENT) {
 206                         OPT_V(s, nir_lower_clip_fs, key->ucp_enables);
 207                         if (key->fclamp_color)
 208                                 OPT_V(s, nir_lower_clamp_color_outputs);
 209                 }
 210                 if (key->color_two_side) {
 211                         OPT_V(s, nir_lower_two_sided_color);
 212                 }
 213         } else {
 214                 /* only want to do this the first time (when key is null)
 215                  * and not again on any potential 2nd variant lowering pass:
 216                  */
 217                 OPT_V(s, ir3_nir_apply_trig_workarounds);
 218         }
 219
 220         OPT_V(s, nir_lower_tex, &tex_options);
 221         OPT_V(s, nir_lower_load_const_to_scalar);
 222         if (shader->compiler->gpu_id < 500)
 223                 OPT_V(s, ir3_nir_lower_tg4_to_tex);
 224
 225         ir3_optimize_loop(s);
 226
 227         /* do ubo load and idiv lowering after first opt loop to get a chance to
 228          * propagate constants for divide by immed power-of-two and constant ubo
 229          * block/offsets:
 230          */
 231         const bool ubo_progress = OPT(s, ir3_nir_analyze_ubo_ranges, shader);
 232         const bool idiv_progress = OPT(s, nir_lower_idiv);
 233         if (ubo_progress || idiv_progress)
 234                 ir3_optimize_loop(s);
 235
 236         OPT_V(s, nir_remove_dead_variables, nir_var_function_temp);
 237
 238         OPT_V(s, nir_move_load_const);
 239
 240         if (ir3_shader_debug & IR3_DBG_DISASM) {
 241                 debug_printf("----------------------\n");
 242                 nir_print_shader(s, stdout);
 243                 debug_printf("----------------------\n");
 244         }
 245
 246         nir_sweep(s);
 247
 248         return s;
 249 }
 250
 251 void
 252 ir3_nir_scan_driver_consts(nir_shader *shader,
 253                 struct ir3_driver_const_layout *layout)
 254 {
 255         nir_foreach_function(function, shader) {
 256                 if (!function->impl)
 257                         continue;
 258
 259                 nir_foreach_block(block, function->impl) {
 260                         nir_foreach_instr(instr, block) {
 261                                 if (instr->type != nir_instr_type_intrinsic)
 262                                         continue;
 263
 264                                 nir_intrinsic_instr *intr =
 265                                         nir_instr_as_intrinsic(instr);
 266                                 unsigned idx;
 267
 268                                 switch (intr->intrinsic) {
 269                                 case nir_intrinsic_get_buffer_size:
 270                                         idx = nir_src_as_const_value(intr->src[0])->u32[0];
 271                                         if (layout->ssbo_size.mask & (1 << idx))
 272                                                 break;
 273                                         layout->ssbo_size.mask |= (1 << idx);
 274                                         layout->ssbo_size.off[idx] =
 275                                                 layout->ssbo_size.count;
 276                                         layout->ssbo_size.count += 1; /* one const per */
 277                                         break;
 278                                 case nir_intrinsic_image_deref_atomic_add:
 279                                 case nir_intrinsic_image_deref_atomic_min:
 280                                 case nir_intrinsic_image_deref_atomic_max:
 281                                 case nir_intrinsic_image_deref_atomic_and:
 282                                 case nir_intrinsic_image_deref_atomic_or:
 283                                 case nir_intrinsic_image_deref_atomic_xor:
 284                                 case nir_intrinsic_image_deref_atomic_exchange:
 285                                 case nir_intrinsic_image_deref_atomic_comp_swap:
 286                                 case nir_intrinsic_image_deref_store:
 287                                 case nir_intrinsic_image_deref_size:
 288                                         idx = nir_intrinsic_get_var(intr, 0)->data.driver_location;
 289                                         if (layout->image_dims.mask & (1 << idx))
 290                                                 break;
 291                                         layout->image_dims.mask |= (1 << idx);
 292                                         layout->image_dims.off[idx] =
 293                                                 layout->image_dims.count;
 294                                         layout->image_dims.count += 3; /* three const per */
 295                                         break;
 296                                 default:
 297                                         break;
 298                                 }
 299                         }
 300                 }
 301         }
 302 }