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Added few more stubs so that control reaches to DestroyDevice().
[mesa.git] / src / freedreno / ir3 / ir3_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27
28 #include "util/debug.h"
29 #include "util/u_math.h"
30
31 #include "ir3_nir.h"
32 #include "ir3_compiler.h"
33 #include "ir3_shader.h"
34
35 static const nir_shader_compiler_options options = {
36 .lower_fpow = true,
37 .lower_scmp = true,
38 .lower_flrp16 = true,
39 .lower_flrp32 = true,
40 .lower_flrp64 = true,
41 .lower_ffract = true,
42 .lower_fmod = true,
43 .lower_fdiv = true,
44 .lower_isign = true,
45 .lower_ldexp = true,
46 .lower_uadd_carry = true,
47 .lower_usub_borrow = true,
48 .lower_mul_high = true,
49 .lower_mul_2x32_64 = true,
50 .fuse_ffma = true,
51 .vertex_id_zero_based = true,
52 .lower_extract_byte = true,
53 .lower_extract_word = true,
54 .lower_all_io_to_elements = true,
55 .lower_helper_invocation = true,
56 .lower_bitfield_insert_to_shifts = true,
57 .lower_bitfield_extract_to_shifts = true,
58 .lower_pack_half_2x16 = true,
59 .lower_pack_snorm_4x8 = true,
60 .lower_pack_snorm_2x16 = true,
61 .lower_pack_unorm_4x8 = true,
62 .lower_pack_unorm_2x16 = true,
63 .lower_unpack_half_2x16 = true,
64 .lower_unpack_snorm_4x8 = true,
65 .lower_unpack_snorm_2x16 = true,
66 .lower_unpack_unorm_4x8 = true,
67 .lower_unpack_unorm_2x16 = true,
68 .lower_pack_split = true,
69 .use_interpolated_input_intrinsics = true,
70 .lower_rotate = true,
71 .lower_to_scalar = true,
72 .has_imul24 = true,
73 .lower_wpos_pntc = true,
74 .lower_cs_local_index_from_id = true,
75
76 /* Only needed for the spirv_to_nir() pass done in ir3_cmdline.c
77 * but that should be harmless for GL since 64b is not
78 * supported there.
79 */
80 .lower_int64_options = (nir_lower_int64_options)~0,
81 };
82
83 /* we don't want to lower vertex_id to _zero_based on newer gpus: */
84 static const nir_shader_compiler_options options_a6xx = {
85 .lower_fpow = true,
86 .lower_scmp = true,
87 .lower_flrp16 = true,
88 .lower_flrp32 = true,
89 .lower_flrp64 = true,
90 .lower_ffract = true,
91 .lower_fmod = true,
92 .lower_fdiv = true,
93 .lower_isign = true,
94 .lower_ldexp = true,
95 .lower_uadd_carry = true,
96 .lower_usub_borrow = true,
97 .lower_mul_high = true,
98 .lower_mul_2x32_64 = true,
99 .fuse_ffma = true,
100 .vertex_id_zero_based = false,
101 .lower_extract_byte = true,
102 .lower_extract_word = true,
103 .lower_all_io_to_elements = true,
104 .lower_helper_invocation = true,
105 .lower_bitfield_insert_to_shifts = true,
106 .lower_bitfield_extract_to_shifts = true,
107 .lower_pack_half_2x16 = true,
108 .lower_pack_snorm_4x8 = true,
109 .lower_pack_snorm_2x16 = true,
110 .lower_pack_unorm_4x8 = true,
111 .lower_pack_unorm_2x16 = true,
112 .lower_unpack_half_2x16 = true,
113 .lower_unpack_snorm_4x8 = true,
114 .lower_unpack_snorm_2x16 = true,
115 .lower_unpack_unorm_4x8 = true,
116 .lower_unpack_unorm_2x16 = true,
117 .lower_pack_split = true,
118 .use_interpolated_input_intrinsics = true,
119 .lower_rotate = true,
120 .vectorize_io = true,
121 .lower_to_scalar = true,
122 .has_imul24 = true,
123 .max_unroll_iterations = 32,
124 .lower_wpos_pntc = true,
125 .lower_cs_local_index_from_id = true,
126
127 /* Only needed for the spirv_to_nir() pass done in ir3_cmdline.c
128 * but that should be harmless for GL since 64b is not
129 * supported there.
130 */
131 .lower_int64_options = (nir_lower_int64_options)~0,
132 };
133
134 const nir_shader_compiler_options *
135 ir3_get_compiler_options(struct ir3_compiler *compiler)
136 {
137 if (compiler->gpu_id >= 600)
138 return &options_a6xx;
139 return &options;
140 }
141
142 #define OPT(nir, pass, ...) ({ \
143 bool this_progress = false; \
144 NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__); \
145 this_progress; \
146 })
147
148 #define OPT_V(nir, pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
149
150 static void
151 ir3_optimize_loop(nir_shader *s)
152 {
153 bool progress;
154 unsigned lower_flrp =
155 (s->options->lower_flrp16 ? 16 : 0) |
156 (s->options->lower_flrp32 ? 32 : 0) |
157 (s->options->lower_flrp64 ? 64 : 0);
158
159 do {
160 progress = false;
161
162 OPT_V(s, nir_lower_vars_to_ssa);
163 progress |= OPT(s, nir_opt_copy_prop_vars);
164 progress |= OPT(s, nir_opt_dead_write_vars);
165 progress |= OPT(s, nir_lower_alu_to_scalar, NULL, NULL);
166 progress |= OPT(s, nir_lower_phis_to_scalar);
167
168 progress |= OPT(s, nir_copy_prop);
169 progress |= OPT(s, nir_opt_dce);
170 progress |= OPT(s, nir_opt_cse);
171 static int gcm = -1;
172 if (gcm == -1)
173 gcm = env_var_as_unsigned("GCM", 0);
174 if (gcm == 1)
175 progress |= OPT(s, nir_opt_gcm, true);
176 else if (gcm == 2)
177 progress |= OPT(s, nir_opt_gcm, false);
178 progress |= OPT(s, nir_opt_peephole_select, 16, true, true);
179 progress |= OPT(s, nir_opt_intrinsics);
180 progress |= OPT(s, nir_opt_algebraic);
181 progress |= OPT(s, nir_lower_alu);
182 progress |= OPT(s, nir_lower_pack);
183 progress |= OPT(s, nir_opt_constant_folding);
184
185 if (lower_flrp != 0) {
186 if (OPT(s, nir_lower_flrp,
187 lower_flrp,
188 false /* always_precise */)) {
189 OPT(s, nir_opt_constant_folding);
190 progress = true;
191 }
192
193 /* Nothing should rematerialize any flrps, so we only
194 * need to do this lowering once.
195 */
196 lower_flrp = 0;
197 }
198
199 progress |= OPT(s, nir_opt_dead_cf);
200 if (OPT(s, nir_opt_trivial_continues)) {
201 progress |= true;
202 /* If nir_opt_trivial_continues makes progress, then we need to clean
203 * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
204 * to make progress.
205 */
206 OPT(s, nir_copy_prop);
207 OPT(s, nir_opt_dce);
208 }
209 progress |= OPT(s, nir_opt_if, false);
210 progress |= OPT(s, nir_opt_loop_unroll, nir_var_all);
211 progress |= OPT(s, nir_opt_remove_phis);
212 progress |= OPT(s, nir_opt_undef);
213 } while (progress);
214 }
215
216 static bool
217 should_split_wrmask(const nir_instr *instr, const void *data)
218 {
219 nir_intrinsic_instr *intr = nir_instr_as_intrinsic(instr);
220
221 switch (intr->intrinsic) {
222 case nir_intrinsic_store_ssbo:
223 case nir_intrinsic_store_shared:
224 case nir_intrinsic_store_global:
225 return true;
226 default:
227 return false;
228 }
229 }
230
231 void
232 ir3_finalize_nir(struct ir3_compiler *compiler, nir_shader *s)
233 {
234 struct nir_lower_tex_options tex_options = {
235 .lower_rect = 0,
236 .lower_tg4_offsets = true,
237 };
238
239 if (compiler->gpu_id >= 400) {
240 /* a4xx seems to have *no* sam.p */
241 tex_options.lower_txp = ~0; /* lower all txp */
242 } else {
243 /* a3xx just needs to avoid sam.p for 3d tex */
244 tex_options.lower_txp = (1 << GLSL_SAMPLER_DIM_3D);
245 }
246
247 if (ir3_shader_debug & IR3_DBG_DISASM) {
248 debug_printf("----------------------\n");
249 nir_print_shader(s, stdout);
250 debug_printf("----------------------\n");
251 }
252
253 if (s->info.stage == MESA_SHADER_GEOMETRY)
254 NIR_PASS_V(s, ir3_nir_lower_gs);
255
256 NIR_PASS_V(s, nir_lower_io_arrays_to_elements_no_indirects, false);
257
258 NIR_PASS_V(s, nir_lower_amul, ir3_glsl_type_size);
259
260 OPT_V(s, nir_lower_regs_to_ssa);
261 OPT_V(s, nir_lower_wrmasks, should_split_wrmask, s);
262
263 OPT_V(s, nir_lower_tex, &tex_options);
264 OPT_V(s, nir_lower_load_const_to_scalar);
265 if (compiler->gpu_id < 500)
266 OPT_V(s, ir3_nir_lower_tg4_to_tex);
267
268 ir3_optimize_loop(s);
269
270 /* do idiv lowering after first opt loop to get a chance to propagate
271 * constants for divide by immed power-of-two:
272 */
273 const bool idiv_progress = OPT(s, nir_lower_idiv, nir_lower_idiv_fast);
274
275 if (idiv_progress)
276 ir3_optimize_loop(s);
277
278 OPT_V(s, nir_remove_dead_variables, nir_var_function_temp, NULL);
279
280 if (ir3_shader_debug & IR3_DBG_DISASM) {
281 debug_printf("----------------------\n");
282 nir_print_shader(s, stdout);
283 debug_printf("----------------------\n");
284 }
285
286 nir_sweep(s);
287 }
288
289 /**
290 * Late passes that need to be done after pscreen->finalize_nir()
291 */
292 void
293 ir3_nir_post_finalize(struct ir3_compiler *compiler, nir_shader *s)
294 {
295 NIR_PASS_V(s, nir_lower_io, nir_var_shader_in | nir_var_shader_out,
296 ir3_glsl_type_size, (nir_lower_io_options)0);
297
298 if (s->info.stage == MESA_SHADER_FRAGMENT) {
299 /* NOTE: lower load_barycentric_at_sample first, since it
300 * produces load_barycentric_at_offset:
301 */
302 NIR_PASS_V(s, ir3_nir_lower_load_barycentric_at_sample);
303 NIR_PASS_V(s, ir3_nir_lower_load_barycentric_at_offset);
304 NIR_PASS_V(s, ir3_nir_move_varying_inputs);
305 NIR_PASS_V(s, nir_lower_fb_read);
306 }
307
308 if (compiler->gpu_id >= 600 &&
309 s->info.stage == MESA_SHADER_FRAGMENT &&
310 !(ir3_shader_debug & IR3_DBG_NOFP16)) {
311 NIR_PASS_V(s, nir_lower_mediump_outputs);
312 }
313
314 /* we cannot ensure that ir3_finalize_nir() is only called once, so
315 * we also need to do trig workarounds here:
316 */
317 OPT_V(s, ir3_nir_apply_trig_workarounds);
318
319 ir3_optimize_loop(s);
320 }
321
322 static bool
323 ir3_nir_lower_layer_id(nir_shader *nir)
324 {
325 unsigned layer_id_loc = ~0;
326 nir_foreach_shader_in_variable(var, nir) {
327 if (var->data.location == VARYING_SLOT_LAYER) {
328 layer_id_loc = var->data.driver_location;
329 break;
330 }
331 }
332
333 assert(layer_id_loc != ~0);
334
335 bool progress = false;
336 nir_builder b;
337
338 nir_foreach_function(func, nir) {
339 nir_builder_init(&b, func->impl);
340
341 nir_foreach_block(block, func->impl) {
342 nir_foreach_instr_safe(instr, block) {
343 if (instr->type != nir_instr_type_intrinsic)
344 continue;
345
346 nir_intrinsic_instr *intrin =
347 nir_instr_as_intrinsic(instr);
348
349 if (intrin->intrinsic != nir_intrinsic_load_input)
350 continue;
351
352 unsigned base = nir_intrinsic_base(intrin);
353 if (base != layer_id_loc)
354 continue;
355
356 b.cursor = nir_before_instr(&intrin->instr);
357 nir_ssa_def *zero = nir_imm_int(&b, 0);
358 nir_ssa_def_rewrite_uses(&intrin->dest.ssa,
359 nir_src_for_ssa(zero));
360 nir_instr_remove(&intrin->instr);
361 progress = true;
362 }
363 }
364
365 if (progress) {
366 nir_metadata_preserve(func->impl,
367 nir_metadata_block_index |
368 nir_metadata_dominance);
369 } else {
370 nir_metadata_preserve(func->impl, nir_metadata_all);
371 }
372 }
373
374 return progress;
375 }
376
377 void
378 ir3_nir_lower_variant(struct ir3_shader_variant *so, nir_shader *s)
379 {
380 if (ir3_shader_debug & IR3_DBG_DISASM) {
381 debug_printf("----------------------\n");
382 nir_print_shader(s, stdout);
383 debug_printf("----------------------\n");
384 }
385
386 bool progress = false;
387
388 if (so->key.has_gs || so->key.tessellation) {
389 switch (so->shader->type) {
390 case MESA_SHADER_VERTEX:
391 NIR_PASS_V(s, ir3_nir_lower_to_explicit_output, so, so->key.tessellation);
392 progress = true;
393 break;
394 case MESA_SHADER_TESS_CTRL:
395 NIR_PASS_V(s, ir3_nir_lower_tess_ctrl, so, so->key.tessellation);
396 NIR_PASS_V(s, ir3_nir_lower_to_explicit_input, so->shader->compiler);
397 progress = true;
398 break;
399 case MESA_SHADER_TESS_EVAL:
400 NIR_PASS_V(s, ir3_nir_lower_tess_eval, so->key.tessellation);
401 if (so->key.has_gs)
402 NIR_PASS_V(s, ir3_nir_lower_to_explicit_output, so, so->key.tessellation);
403 progress = true;
404 break;
405 case MESA_SHADER_GEOMETRY:
406 NIR_PASS_V(s, ir3_nir_lower_to_explicit_input, so->shader->compiler);
407 progress = true;
408 break;
409 default:
410 break;
411 }
412 }
413
414 if (s->info.stage == MESA_SHADER_VERTEX) {
415 if (so->key.ucp_enables)
416 progress |= OPT(s, nir_lower_clip_vs, so->key.ucp_enables, false, false, NULL);
417 if (so->key.vclamp_color)
418 progress |= OPT(s, nir_lower_clamp_color_outputs);
419 } else if (s->info.stage == MESA_SHADER_FRAGMENT) {
420 if (so->key.ucp_enables)
421 progress |= OPT(s, nir_lower_clip_fs, so->key.ucp_enables, false);
422 if (so->key.fclamp_color)
423 progress |= OPT(s, nir_lower_clamp_color_outputs);
424 if (so->key.layer_zero && (s->info.inputs_read & VARYING_BIT_LAYER))
425 progress |= OPT(s, ir3_nir_lower_layer_id);
426 }
427 if (so->key.color_two_side) {
428 OPT_V(s, nir_lower_two_sided_color, true);
429 progress = true;
430 }
431
432 struct nir_lower_tex_options tex_options = { };
433
434 switch (so->shader->type) {
435 case MESA_SHADER_FRAGMENT:
436 tex_options.saturate_s = so->key.fsaturate_s;
437 tex_options.saturate_t = so->key.fsaturate_t;
438 tex_options.saturate_r = so->key.fsaturate_r;
439 break;
440 case MESA_SHADER_VERTEX:
441 tex_options.saturate_s = so->key.vsaturate_s;
442 tex_options.saturate_t = so->key.vsaturate_t;
443 tex_options.saturate_r = so->key.vsaturate_r;
444 break;
445 default:
446 /* TODO */
447 break;
448 }
449
450 if (tex_options.saturate_s || tex_options.saturate_t ||
451 tex_options.saturate_r) {
452 progress |= OPT(s, nir_lower_tex, &tex_options);
453 }
454
455 if (!so->binning_pass)
456 OPT_V(s, ir3_nir_analyze_ubo_ranges, so);
457
458 progress |= OPT(s, ir3_nir_lower_ubo_loads, so);
459
460 /* UBO offset lowering has to come after we've decided what will
461 * be left as load_ubo
462 */
463 if (so->shader->compiler->gpu_id >= 600)
464 OPT_V(s, nir_lower_ubo_vec4);
465
466 OPT_V(s, ir3_nir_lower_io_offsets, so->shader->compiler->gpu_id);
467
468 if (progress)
469 ir3_optimize_loop(s);
470
471 /* Do late algebraic optimization to turn add(a, neg(b)) back into
472 * subs, then the mandatory cleanup after algebraic. Note that it may
473 * produce fnegs, and if so then we need to keep running to squash
474 * fneg(fneg(a)).
475 */
476 bool more_late_algebraic = true;
477 while (more_late_algebraic) {
478 more_late_algebraic = OPT(s, nir_opt_algebraic_late);
479 OPT_V(s, nir_opt_constant_folding);
480 OPT_V(s, nir_copy_prop);
481 OPT_V(s, nir_opt_dce);
482 OPT_V(s, nir_opt_cse);
483 }
484
485 OPT_V(s, nir_opt_sink, nir_move_const_undef);
486
487 if (ir3_shader_debug & IR3_DBG_DISASM) {
488 debug_printf("----------------------\n");
489 nir_print_shader(s, stdout);
490 debug_printf("----------------------\n");
491 }
492
493 nir_sweep(s);
494
495 /* Binning pass variants re-use the const_state of the corresponding
496 * draw pass shader, so that same const emit can be re-used for both
497 * passes:
498 */
499 if (!so->binning_pass)
500 ir3_setup_const_state(s, so, ir3_const_state(so));
501 }
502
503 static void
504 ir3_nir_scan_driver_consts(nir_shader *shader,
505 struct ir3_const_state *layout)
506 {
507 nir_foreach_function (function, shader) {
508 if (!function->impl)
509 continue;
510
511 nir_foreach_block (block, function->impl) {
512 nir_foreach_instr (instr, block) {
513 if (instr->type != nir_instr_type_intrinsic)
514 continue;
515
516 nir_intrinsic_instr *intr =
517 nir_instr_as_intrinsic(instr);
518 unsigned idx;
519
520 switch (intr->intrinsic) {
521 case nir_intrinsic_get_buffer_size:
522 if (ir3_bindless_resource(intr->src[0]))
523 break;
524 idx = nir_src_as_uint(intr->src[0]);
525 if (layout->ssbo_size.mask & (1 << idx))
526 break;
527 layout->ssbo_size.mask |= (1 << idx);
528 layout->ssbo_size.off[idx] =
529 layout->ssbo_size.count;
530 layout->ssbo_size.count += 1; /* one const per */
531 break;
532 case nir_intrinsic_image_atomic_add:
533 case nir_intrinsic_image_atomic_imin:
534 case nir_intrinsic_image_atomic_umin:
535 case nir_intrinsic_image_atomic_imax:
536 case nir_intrinsic_image_atomic_umax:
537 case nir_intrinsic_image_atomic_and:
538 case nir_intrinsic_image_atomic_or:
539 case nir_intrinsic_image_atomic_xor:
540 case nir_intrinsic_image_atomic_exchange:
541 case nir_intrinsic_image_atomic_comp_swap:
542 case nir_intrinsic_image_store:
543 case nir_intrinsic_image_size:
544 idx = nir_src_as_uint(intr->src[0]);
545 if (layout->image_dims.mask & (1 << idx))
546 break;
547 layout->image_dims.mask |= (1 << idx);
548 layout->image_dims.off[idx] =
549 layout->image_dims.count;
550 layout->image_dims.count += 3; /* three const per */
551 break;
552 case nir_intrinsic_load_base_vertex:
553 case nir_intrinsic_load_first_vertex:
554 layout->num_driver_params =
555 MAX2(layout->num_driver_params, IR3_DP_VTXID_BASE + 1);
556 break;
557 case nir_intrinsic_load_base_instance:
558 layout->num_driver_params =
559 MAX2(layout->num_driver_params, IR3_DP_INSTID_BASE + 1);
560 break;
561 case nir_intrinsic_load_user_clip_plane:
562 idx = nir_intrinsic_ucp_id(intr);
563 layout->num_driver_params =
564 MAX2(layout->num_driver_params, IR3_DP_UCP0_X + (idx + 1) * 4);
565 break;
566 case nir_intrinsic_load_num_work_groups:
567 layout->num_driver_params =
568 MAX2(layout->num_driver_params, IR3_DP_NUM_WORK_GROUPS_Z + 1);
569 break;
570 case nir_intrinsic_load_local_group_size:
571 layout->num_driver_params =
572 MAX2(layout->num_driver_params, IR3_DP_LOCAL_GROUP_SIZE_Z + 1);
573 break;
574 default:
575 break;
576 }
577 }
578 }
579 }
580 }
581
582 /* Sets up the variant-dependent constant state for the ir3_shader. Note
583 * that it is also used from ir3_nir_analyze_ubo_ranges() to figure out the
584 * maximum number of driver params that would eventually be used, to leave
585 * space for this function to allocate the driver params.
586 */
587 void
588 ir3_setup_const_state(nir_shader *nir, struct ir3_shader_variant *v,
589 struct ir3_const_state *const_state)
590 {
591 struct ir3_compiler *compiler = v->shader->compiler;
592
593 memset(&const_state->offsets, ~0, sizeof(const_state->offsets));
594
595 ir3_nir_scan_driver_consts(nir, const_state);
596
597 if ((compiler->gpu_id < 500) &&
598 (v->shader->stream_output.num_outputs > 0)) {
599 const_state->num_driver_params =
600 MAX2(const_state->num_driver_params, IR3_DP_VTXCNT_MAX + 1);
601 }
602
603 const_state->num_ubos = nir->info.num_ubos;
604
605 /* num_driver_params is scalar, align to vec4: */
606 const_state->num_driver_params = align(const_state->num_driver_params, 4);
607
608 debug_assert((const_state->ubo_state.size % 16) == 0);
609 unsigned constoff = const_state->ubo_state.size / 16;
610 unsigned ptrsz = ir3_pointer_size(compiler);
611
612 if (const_state->num_ubos > 0) {
613 const_state->offsets.ubo = constoff;
614 constoff += align(const_state->num_ubos * ptrsz, 4) / 4;
615 }
616
617 if (const_state->ssbo_size.count > 0) {
618 unsigned cnt = const_state->ssbo_size.count;
619 const_state->offsets.ssbo_sizes = constoff;
620 constoff += align(cnt, 4) / 4;
621 }
622
623 if (const_state->image_dims.count > 0) {
624 unsigned cnt = const_state->image_dims.count;
625 const_state->offsets.image_dims = constoff;
626 constoff += align(cnt, 4) / 4;
627 }
628
629 if (const_state->num_driver_params > 0) {
630 /* offset cannot be 0 for vs params loaded by CP_DRAW_INDIRECT_MULTI */
631 if (v->type == MESA_SHADER_VERTEX && compiler->gpu_id >= 600)
632 constoff = MAX2(constoff, 1);
633 const_state->offsets.driver_param = constoff;
634 }
635 constoff += const_state->num_driver_params / 4;
636
637 if ((v->type == MESA_SHADER_VERTEX) &&
638 (compiler->gpu_id < 500) &&
639 v->shader->stream_output.num_outputs > 0) {
640 const_state->offsets.tfbo = constoff;
641 constoff += align(IR3_MAX_SO_BUFFERS * ptrsz, 4) / 4;
642 }
643
644 switch (v->type) {
645 case MESA_SHADER_VERTEX:
646 const_state->offsets.primitive_param = constoff;
647 constoff += 1;
648 break;
649 case MESA_SHADER_TESS_CTRL:
650 case MESA_SHADER_TESS_EVAL:
651 constoff = align(constoff - 1, 4) + 3;
652 const_state->offsets.primitive_param = constoff;
653 const_state->offsets.primitive_map = constoff + 5;
654 constoff += 5 + DIV_ROUND_UP(nir->num_inputs, 4);
655 break;
656 case MESA_SHADER_GEOMETRY:
657 const_state->offsets.primitive_param = constoff;
658 const_state->offsets.primitive_map = constoff + 1;
659 constoff += 1 + DIV_ROUND_UP(nir->num_inputs, 4);
660 break;
661 default:
662 break;
663 }
664
665 const_state->offsets.immediate = constoff;
666
667 assert(constoff <= ir3_max_const(v));
668 }