src/freedreno/ir3/ir3_nir.c

   1 /*
   2  * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27
  28 #include "util/debug.h"
  29 #include "util/u_math.h"
  30
  31 #include "ir3_nir.h"
  32 #include "ir3_compiler.h"
  33 #include "ir3_shader.h"
  34
  35 static void ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir);
  36
  37 static const nir_shader_compiler_options options = {
  38                 .lower_fpow = true,
  39                 .lower_scmp = true,
  40                 .lower_flrp32 = true,
  41                 .lower_flrp64 = true,
  42                 .lower_ffract = true,
  43                 .lower_fmod = true,
  44                 .lower_fdiv = true,
  45                 .lower_isign = true,
  46                 .lower_ldexp = true,
  47                 .lower_uadd_carry = true,
  48                 .lower_mul_high = true,
  49                 .fuse_ffma = true,
  50                 .vertex_id_zero_based = true,
  51                 .lower_extract_byte = true,
  52                 .lower_extract_word = true,
  53                 .lower_all_io_to_elements = true,
  54                 .lower_helper_invocation = true,
  55                 .lower_bitfield_insert_to_shifts = true,
  56                 .lower_bitfield_extract_to_shifts = true,
  57                 .use_interpolated_input_intrinsics = true,
  58                 .lower_rotate = true,
  59                 .lower_to_scalar = true,
  60 };
  61
  62 /* we don't want to lower vertex_id to _zero_based on newer gpus: */
  63 static const nir_shader_compiler_options options_a6xx = {
  64                 .lower_fpow = true,
  65                 .lower_scmp = true,
  66                 .lower_flrp32 = true,
  67                 .lower_flrp64 = true,
  68                 .lower_ffract = true,
  69                 .lower_fmod = true,
  70                 .lower_fdiv = true,
  71                 .lower_isign = true,
  72                 .lower_ldexp = true,
  73                 .lower_uadd_carry = true,
  74                 .lower_mul_high = true,
  75                 .fuse_ffma = true,
  76                 .vertex_id_zero_based = false,
  77                 .lower_extract_byte = true,
  78                 .lower_extract_word = true,
  79                 .lower_all_io_to_elements = true,
  80                 .lower_helper_invocation = true,
  81                 .lower_bitfield_insert_to_shifts = true,
  82                 .lower_bitfield_extract_to_shifts = true,
  83                 .use_interpolated_input_intrinsics = true,
  84                 .lower_rotate = true,
  85                 .vectorize_io = true,
  86                 .lower_to_scalar = true,
  87 };
  88
  89 const nir_shader_compiler_options *
  90 ir3_get_compiler_options(struct ir3_compiler *compiler)
  91 {
  92         if (compiler->gpu_id >= 600)
  93                 return &options_a6xx;
  94         return &options;
  95 }
  96
  97 /* for given shader key, are any steps handled in nir? */
  98 bool
  99 ir3_key_lowers_nir(const struct ir3_shader_key *key)
 100 {
 101         return key->fsaturate_s | key->fsaturate_t | key->fsaturate_r |
 102                         key->vsaturate_s | key->vsaturate_t | key->vsaturate_r |
 103                         key->ucp_enables | key->color_two_side |
 104                         key->fclamp_color | key->vclamp_color;
 105 }
 106
 107 #define OPT(nir, pass, ...) ({                             \
 108    bool this_progress = false;                             \
 109    NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__);      \
 110    this_progress;                                          \
 111 })
 112
 113 #define OPT_V(nir, pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
 114
 115 static void
 116 ir3_optimize_loop(nir_shader *s)
 117 {
 118         bool progress;
 119         unsigned lower_flrp =
 120                 (s->options->lower_flrp16 ? 16 : 0) |
 121                 (s->options->lower_flrp32 ? 32 : 0) |
 122                 (s->options->lower_flrp64 ? 64 : 0);
 123
 124         do {
 125                 progress = false;
 126
 127                 OPT_V(s, nir_lower_vars_to_ssa);
 128                 progress |= OPT(s, nir_opt_copy_prop_vars);
 129                 progress |= OPT(s, nir_opt_dead_write_vars);
 130                 progress |= OPT(s, nir_lower_alu_to_scalar, NULL, NULL);
 131                 progress |= OPT(s, nir_lower_phis_to_scalar);
 132
 133                 progress |= OPT(s, nir_copy_prop);
 134                 progress |= OPT(s, nir_opt_dce);
 135                 progress |= OPT(s, nir_opt_cse);
 136                 static int gcm = -1;
 137                 if (gcm == -1)
 138                         gcm = env_var_as_unsigned("GCM", 0);
 139                 if (gcm == 1)
 140                         progress |= OPT(s, nir_opt_gcm, true);
 141                 else if (gcm == 2)
 142                         progress |= OPT(s, nir_opt_gcm, false);
 143                 progress |= OPT(s, nir_opt_peephole_select, 16, true, true);
 144                 progress |= OPT(s, nir_opt_intrinsics);
 145                 progress |= OPT(s, nir_opt_algebraic);
 146                 progress |= OPT(s, nir_opt_constant_folding);
 147
 148                 if (lower_flrp != 0) {
 149                         if (OPT(s, nir_lower_flrp,
 150                                         lower_flrp,
 151                                         false /* always_precise */,
 152                                         s->options->lower_ffma)) {
 153                                 OPT(s, nir_opt_constant_folding);
 154                                 progress = true;
 155                         }
 156
 157                         /* Nothing should rematerialize any flrps, so we only
 158                          * need to do this lowering once.
 159                          */
 160                         lower_flrp = 0;
 161                 }
 162
 163                 progress |= OPT(s, nir_opt_dead_cf);
 164                 if (OPT(s, nir_opt_trivial_continues)) {
 165                         progress |= true;
 166                         /* If nir_opt_trivial_continues makes progress, then we need to clean
 167                          * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
 168                          * to make progress.
 169                          */
 170                         OPT(s, nir_copy_prop);
 171                         OPT(s, nir_opt_dce);
 172                 }
 173                 progress |= OPT(s, nir_opt_if, false);
 174                 progress |= OPT(s, nir_opt_remove_phis);
 175                 progress |= OPT(s, nir_opt_undef);
 176
 177         } while (progress);
 178 }
 179
 180 void
 181 ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
 182                 const struct ir3_shader_key *key)
 183 {
 184         struct nir_lower_tex_options tex_options = {
 185                         .lower_rect = 0,
 186                         .lower_tg4_offsets = true,
 187         };
 188
 189         if (key) {
 190                 switch (shader->type) {
 191                 case MESA_SHADER_FRAGMENT:
 192                         tex_options.saturate_s = key->fsaturate_s;
 193                         tex_options.saturate_t = key->fsaturate_t;
 194                         tex_options.saturate_r = key->fsaturate_r;
 195                         break;
 196                 case MESA_SHADER_VERTEX:
 197                         tex_options.saturate_s = key->vsaturate_s;
 198                         tex_options.saturate_t = key->vsaturate_t;
 199                         tex_options.saturate_r = key->vsaturate_r;
 200                         break;
 201                 default:
 202                         /* TODO */
 203                         break;
 204                 }
 205         }
 206
 207         if (shader->compiler->gpu_id >= 400) {
 208                 /* a4xx seems to have *no* sam.p */
 209                 tex_options.lower_txp = ~0;  /* lower all txp */
 210         } else {
 211                 /* a3xx just needs to avoid sam.p for 3d tex */
 212                 tex_options.lower_txp = (1 << GLSL_SAMPLER_DIM_3D);
 213         }
 214
 215         if (ir3_shader_debug & IR3_DBG_DISASM) {
 216                 debug_printf("----------------------\n");
 217                 nir_print_shader(s, stdout);
 218                 debug_printf("----------------------\n");
 219         }
 220
 221         OPT_V(s, nir_lower_regs_to_ssa);
 222         OPT_V(s, ir3_nir_lower_io_offsets);
 223
 224         if (key) {
 225                 if (s->info.stage == MESA_SHADER_VERTEX) {
 226                         OPT_V(s, nir_lower_clip_vs, key->ucp_enables, false);
 227                         if (key->vclamp_color)
 228                                 OPT_V(s, nir_lower_clamp_color_outputs);
 229                 } else if (s->info.stage == MESA_SHADER_FRAGMENT) {
 230                         OPT_V(s, nir_lower_clip_fs, key->ucp_enables);
 231                         if (key->fclamp_color)
 232                                 OPT_V(s, nir_lower_clamp_color_outputs);
 233                 }
 234                 if (key->color_two_side) {
 235                         OPT_V(s, nir_lower_two_sided_color);
 236                 }
 237         } else {
 238                 /* only want to do this the first time (when key is null)
 239                  * and not again on any potential 2nd variant lowering pass:
 240                  */
 241                 OPT_V(s, ir3_nir_apply_trig_workarounds);
 242
 243                 /* This wouldn't hurt to run multiple times, but there is
 244                  * no need to:
 245                  */
 246                 if (shader->type == MESA_SHADER_FRAGMENT)
 247                         OPT_V(s, nir_lower_fb_read);
 248         }
 249
 250         OPT_V(s, nir_lower_tex, &tex_options);
 251         OPT_V(s, nir_lower_load_const_to_scalar);
 252         if (shader->compiler->gpu_id < 500)
 253                 OPT_V(s, ir3_nir_lower_tg4_to_tex);
 254
 255         ir3_optimize_loop(s);
 256
 257         /* do ubo load and idiv lowering after first opt loop to get a chance to
 258          * propagate constants for divide by immed power-of-two and constant ubo
 259          * block/offsets:
 260          *
 261          * NOTE that UBO analysis pass should only be done once, before variants
 262          */
 263         const bool ubo_progress = !key && OPT(s, ir3_nir_analyze_ubo_ranges, shader);
 264         const bool idiv_progress = OPT(s, nir_lower_idiv);
 265         if (ubo_progress || idiv_progress)
 266                 ir3_optimize_loop(s);
 267
 268         /* Do late algebraic optimization to turn add(a, neg(b)) back into
 269         * subs, then the mandatory cleanup after algebraic.  Note that it may
 270         * produce fnegs, and if so then we need to keep running to squash
 271         * fneg(fneg(a)).
 272         */
 273         bool more_late_algebraic = true;
 274         while (more_late_algebraic) {
 275                 more_late_algebraic = OPT(s, nir_opt_algebraic_late);
 276                 OPT_V(s, nir_opt_constant_folding);
 277                 OPT_V(s, nir_copy_prop);
 278                 OPT_V(s, nir_opt_dce);
 279                 OPT_V(s, nir_opt_cse);
 280         }
 281
 282         OPT_V(s, nir_remove_dead_variables, nir_var_function_temp);
 283
 284         OPT_V(s, nir_opt_sink, nir_move_const_undef);
 285
 286         if (ir3_shader_debug & IR3_DBG_DISASM) {
 287                 debug_printf("----------------------\n");
 288                 nir_print_shader(s, stdout);
 289                 debug_printf("----------------------\n");
 290         }
 291
 292         nir_sweep(s);
 293
 294         /* The first time thru, when not creating variant, do the one-time
 295          * const_state layout setup.  This should be done after ubo range
 296          * analysis.
 297          */
 298         if (!key) {
 299                 ir3_setup_const_state(shader, s);
 300         }
 301 }
 302
 303 static void
 304 ir3_nir_scan_driver_consts(nir_shader *shader,
 305                 struct ir3_const_state *layout)
 306 {
 307         nir_foreach_function(function, shader) {
 308                 if (!function->impl)
 309                         continue;
 310
 311                 nir_foreach_block(block, function->impl) {
 312                         nir_foreach_instr(instr, block) {
 313                                 if (instr->type != nir_instr_type_intrinsic)
 314                                         continue;
 315
 316                                 nir_intrinsic_instr *intr =
 317                                         nir_instr_as_intrinsic(instr);
 318                                 unsigned idx;
 319
 320                                 switch (intr->intrinsic) {
 321                                 case nir_intrinsic_get_buffer_size:
 322                                         idx = nir_src_as_uint(intr->src[0]);
 323                                         if (layout->ssbo_size.mask & (1 << idx))
 324                                                 break;
 325                                         layout->ssbo_size.mask |= (1 << idx);
 326                                         layout->ssbo_size.off[idx] =
 327                                                 layout->ssbo_size.count;
 328                                         layout->ssbo_size.count += 1; /* one const per */
 329                                         break;
 330                                 case nir_intrinsic_image_deref_atomic_add:
 331                                 case nir_intrinsic_image_deref_atomic_imin:
 332                                 case nir_intrinsic_image_deref_atomic_umin:
 333                                 case nir_intrinsic_image_deref_atomic_imax:
 334                                 case nir_intrinsic_image_deref_atomic_umax:
 335                                 case nir_intrinsic_image_deref_atomic_and:
 336                                 case nir_intrinsic_image_deref_atomic_or:
 337                                 case nir_intrinsic_image_deref_atomic_xor:
 338                                 case nir_intrinsic_image_deref_atomic_exchange:
 339                                 case nir_intrinsic_image_deref_atomic_comp_swap:
 340                                 case nir_intrinsic_image_deref_store:
 341                                 case nir_intrinsic_image_deref_size:
 342                                         idx = nir_intrinsic_get_var(intr, 0)->data.driver_location;
 343                                         if (layout->image_dims.mask & (1 << idx))
 344                                                 break;
 345                                         layout->image_dims.mask |= (1 << idx);
 346                                         layout->image_dims.off[idx] =
 347                                                 layout->image_dims.count;
 348                                         layout->image_dims.count += 3; /* three const per */
 349                                         break;
 350                                 case nir_intrinsic_load_ubo:
 351                                         if (nir_src_is_const(intr->src[0])) {
 352                                                 layout->num_ubos = MAX2(layout->num_ubos,
 353                                                                 nir_src_as_uint(intr->src[0]) + 1);
 354                                         } else {
 355                                                 layout->num_ubos = shader->info.num_ubos;
 356                                         }
 357                                         break;
 358                                 case nir_intrinsic_load_base_vertex:
 359                                 case nir_intrinsic_load_first_vertex:
 360                                         layout->num_driver_params =
 361                                                 MAX2(layout->num_driver_params, IR3_DP_VTXID_BASE + 1);
 362                                         break;
 363                                 case nir_intrinsic_load_user_clip_plane:
 364                                         layout->num_driver_params =
 365                                                 MAX2(layout->num_driver_params, IR3_DP_UCP7_W + 1);
 366                                         break;
 367                                 case nir_intrinsic_load_num_work_groups:
 368                                         layout->num_driver_params =
 369                                                 MAX2(layout->num_driver_params, IR3_DP_NUM_WORK_GROUPS_Z + 1);
 370                                         break;
 371                                 case nir_intrinsic_load_local_group_size:
 372                                         layout->num_driver_params =
 373                                                 MAX2(layout->num_driver_params, IR3_DP_LOCAL_GROUP_SIZE_Z + 1);
 374                                         break;
 375                                 default:
 376                                         break;
 377                                 }
 378                         }
 379                 }
 380         }
 381 }
 382
 383 static void
 384 ir3_setup_const_state(struct ir3_shader *shader, nir_shader *nir)
 385 {
 386         struct ir3_compiler *compiler = shader->compiler;
 387         struct ir3_const_state *const_state = &shader->const_state;
 388
 389         memset(&const_state->offsets, ~0, sizeof(const_state->offsets));
 390
 391         ir3_nir_scan_driver_consts(nir, const_state);
 392
 393         if ((compiler->gpu_id < 500) &&
 394                         (shader->stream_output.num_outputs > 0)) {
 395                 const_state->num_driver_params =
 396                         MAX2(const_state->num_driver_params, IR3_DP_VTXCNT_MAX + 1);
 397         }
 398
 399         /* num_driver_params is scalar, align to vec4: */
 400         const_state->num_driver_params = align(const_state->num_driver_params, 4);
 401
 402         debug_assert((shader->ubo_state.size % 16) == 0);
 403         unsigned constoff = align(shader->ubo_state.size / 16, 8);
 404         unsigned ptrsz = ir3_pointer_size(compiler);
 405
 406         if (const_state->num_ubos > 0) {
 407                 const_state->offsets.ubo = constoff;
 408                 constoff += align(nir->info.num_ubos * ptrsz, 4) / 4;
 409         }
 410
 411         if (const_state->ssbo_size.count > 0) {
 412                 unsigned cnt = const_state->ssbo_size.count;
 413                 const_state->offsets.ssbo_sizes = constoff;
 414                 constoff += align(cnt, 4) / 4;
 415         }
 416
 417         if (const_state->image_dims.count > 0) {
 418                 unsigned cnt = const_state->image_dims.count;
 419                 const_state->offsets.image_dims = constoff;
 420                 constoff += align(cnt, 4) / 4;
 421         }
 422
 423         if (const_state->num_driver_params > 0)
 424                 const_state->offsets.driver_param = constoff;
 425         constoff += const_state->num_driver_params / 4;
 426
 427         if ((shader->type == MESA_SHADER_VERTEX) &&
 428                         (compiler->gpu_id < 500) &&
 429                         shader->stream_output.num_outputs > 0) {
 430                 const_state->offsets.tfbo = constoff;
 431                 constoff += align(IR3_MAX_SO_BUFFERS * ptrsz, 4) / 4;
 432         }
 433
 434         const_state->offsets.immediate = constoff;
 435 }