freedreno/a6xx: vertex_id is not _zero_based
[mesa.git] / src / freedreno / ir3 / ir3_nir.c
1 /*
2 * Copyright (C) 2015 Rob Clark <robclark@freedesktop.org>
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
21 * SOFTWARE.
22 *
23 * Authors:
24 * Rob Clark <robclark@freedesktop.org>
25 */
26
27
28 #include "util/debug.h"
29
30 #include "ir3_nir.h"
31 #include "ir3_compiler.h"
32 #include "ir3_shader.h"
33
34 static const nir_shader_compiler_options options = {
35 .lower_fpow = true,
36 .lower_scmp = true,
37 .lower_flrp32 = true,
38 .lower_flrp64 = true,
39 .lower_ffract = true,
40 .lower_fmod32 = true,
41 .lower_fmod64 = true,
42 .lower_fdiv = true,
43 .lower_isign = true,
44 .lower_ldexp = true,
45 .fuse_ffma = true,
46 .native_integers = true,
47 .vertex_id_zero_based = true,
48 .lower_extract_byte = true,
49 .lower_extract_word = true,
50 .lower_all_io_to_temps = true,
51 .lower_helper_invocation = true,
52 };
53
54 /* we don't want to lower vertex_id to _zero_based on newer gpus: */
55 static const nir_shader_compiler_options options_a6xx = {
56 .lower_fpow = true,
57 .lower_scmp = true,
58 .lower_flrp32 = true,
59 .lower_flrp64 = true,
60 .lower_ffract = true,
61 .lower_fmod32 = true,
62 .lower_fmod64 = true,
63 .lower_fdiv = true,
64 .lower_isign = true,
65 .lower_ldexp = true,
66 .fuse_ffma = true,
67 .native_integers = true,
68 .vertex_id_zero_based = false,
69 .lower_extract_byte = true,
70 .lower_extract_word = true,
71 .lower_all_io_to_temps = true,
72 .lower_helper_invocation = true,
73 };
74
75 const nir_shader_compiler_options *
76 ir3_get_compiler_options(struct ir3_compiler *compiler)
77 {
78 if (compiler->gpu_id >= 600)
79 return &options_a6xx;
80 return &options;
81 }
82
83 /* for given shader key, are any steps handled in nir? */
84 bool
85 ir3_key_lowers_nir(const struct ir3_shader_key *key)
86 {
87 return key->fsaturate_s | key->fsaturate_t | key->fsaturate_r |
88 key->vsaturate_s | key->vsaturate_t | key->vsaturate_r |
89 key->ucp_enables | key->color_two_side |
90 key->fclamp_color | key->vclamp_color;
91 }
92
93 #define OPT(nir, pass, ...) ({ \
94 bool this_progress = false; \
95 NIR_PASS(this_progress, nir, pass, ##__VA_ARGS__); \
96 this_progress; \
97 })
98
99 #define OPT_V(nir, pass, ...) NIR_PASS_V(nir, pass, ##__VA_ARGS__)
100
101 static void
102 ir3_optimize_loop(nir_shader *s)
103 {
104 bool progress;
105 do {
106 progress = false;
107
108 OPT_V(s, nir_lower_vars_to_ssa);
109 progress |= OPT(s, nir_opt_copy_prop_vars);
110 progress |= OPT(s, nir_opt_dead_write_vars);
111 progress |= OPT(s, nir_lower_alu_to_scalar);
112 progress |= OPT(s, nir_lower_phis_to_scalar);
113
114 progress |= OPT(s, nir_copy_prop);
115 progress |= OPT(s, nir_opt_dce);
116 progress |= OPT(s, nir_opt_cse);
117 static int gcm = -1;
118 if (gcm == -1)
119 gcm = env_var_as_unsigned("GCM", 0);
120 if (gcm == 1)
121 progress |= OPT(s, nir_opt_gcm, true);
122 else if (gcm == 2)
123 progress |= OPT(s, nir_opt_gcm, false);
124 progress |= OPT(s, nir_opt_peephole_select, 16, true, true);
125 progress |= OPT(s, nir_opt_intrinsics);
126 progress |= OPT(s, nir_opt_algebraic);
127 progress |= OPT(s, nir_opt_constant_folding);
128 progress |= OPT(s, nir_opt_dead_cf);
129 if (OPT(s, nir_opt_trivial_continues)) {
130 progress |= true;
131 /* If nir_opt_trivial_continues makes progress, then we need to clean
132 * things up if we want any hope of nir_opt_if or nir_opt_loop_unroll
133 * to make progress.
134 */
135 OPT(s, nir_copy_prop);
136 OPT(s, nir_opt_dce);
137 }
138 progress |= OPT(s, nir_opt_if);
139 progress |= OPT(s, nir_opt_remove_phis);
140 progress |= OPT(s, nir_opt_undef);
141
142 } while (progress);
143 }
144
145 struct nir_shader *
146 ir3_optimize_nir(struct ir3_shader *shader, nir_shader *s,
147 const struct ir3_shader_key *key)
148 {
149 struct nir_lower_tex_options tex_options = {
150 .lower_rect = 0,
151 };
152
153 if (key) {
154 switch (shader->type) {
155 case MESA_SHADER_FRAGMENT:
156 tex_options.saturate_s = key->fsaturate_s;
157 tex_options.saturate_t = key->fsaturate_t;
158 tex_options.saturate_r = key->fsaturate_r;
159 break;
160 case MESA_SHADER_VERTEX:
161 tex_options.saturate_s = key->vsaturate_s;
162 tex_options.saturate_t = key->vsaturate_t;
163 tex_options.saturate_r = key->vsaturate_r;
164 break;
165 default:
166 /* TODO */
167 break;
168 }
169 }
170
171 if (shader->compiler->gpu_id >= 400) {
172 /* a4xx seems to have *no* sam.p */
173 tex_options.lower_txp = ~0; /* lower all txp */
174 } else {
175 /* a3xx just needs to avoid sam.p for 3d tex */
176 tex_options.lower_txp = (1 << GLSL_SAMPLER_DIM_3D);
177 }
178
179 if (ir3_shader_debug & IR3_DBG_DISASM) {
180 debug_printf("----------------------\n");
181 nir_print_shader(s, stdout);
182 debug_printf("----------------------\n");
183 }
184
185 OPT_V(s, nir_opt_global_to_local);
186 OPT_V(s, nir_lower_regs_to_ssa);
187
188 if (key) {
189 if (s->info.stage == MESA_SHADER_VERTEX) {
190 OPT_V(s, nir_lower_clip_vs, key->ucp_enables, false);
191 if (key->vclamp_color)
192 OPT_V(s, nir_lower_clamp_color_outputs);
193 } else if (s->info.stage == MESA_SHADER_FRAGMENT) {
194 OPT_V(s, nir_lower_clip_fs, key->ucp_enables);
195 if (key->fclamp_color)
196 OPT_V(s, nir_lower_clamp_color_outputs);
197 }
198 if (key->color_two_side) {
199 OPT_V(s, nir_lower_two_sided_color);
200 }
201 } else {
202 /* only want to do this the first time (when key is null)
203 * and not again on any potential 2nd variant lowering pass:
204 */
205 OPT_V(s, ir3_nir_apply_trig_workarounds);
206 }
207
208 OPT_V(s, nir_lower_tex, &tex_options);
209 OPT_V(s, nir_lower_load_const_to_scalar);
210 if (shader->compiler->gpu_id < 500)
211 OPT_V(s, ir3_nir_lower_tg4_to_tex);
212
213 ir3_optimize_loop(s);
214
215 /* do idiv lowering after first opt loop to give a chance for
216 * divide by immed power-of-two to be caught first:
217 */
218 if (OPT(s, nir_lower_idiv))
219 ir3_optimize_loop(s);
220
221 OPT_V(s, nir_remove_dead_variables, nir_var_function_temp);
222
223 OPT_V(s, nir_move_load_const);
224
225 if (ir3_shader_debug & IR3_DBG_DISASM) {
226 debug_printf("----------------------\n");
227 nir_print_shader(s, stdout);
228 debug_printf("----------------------\n");
229 }
230
231 nir_sweep(s);
232
233 return s;
234 }
235
236 void
237 ir3_nir_scan_driver_consts(nir_shader *shader,
238 struct ir3_driver_const_layout *layout)
239 {
240 nir_foreach_function(function, shader) {
241 if (!function->impl)
242 continue;
243
244 nir_foreach_block(block, function->impl) {
245 nir_foreach_instr(instr, block) {
246 if (instr->type != nir_instr_type_intrinsic)
247 continue;
248
249 nir_intrinsic_instr *intr =
250 nir_instr_as_intrinsic(instr);
251 unsigned idx;
252
253 switch (intr->intrinsic) {
254 case nir_intrinsic_get_buffer_size:
255 idx = nir_src_as_const_value(intr->src[0])->u32[0];
256 if (layout->ssbo_size.mask & (1 << idx))
257 break;
258 layout->ssbo_size.mask |= (1 << idx);
259 layout->ssbo_size.off[idx] =
260 layout->ssbo_size.count;
261 layout->ssbo_size.count += 1; /* one const per */
262 break;
263 case nir_intrinsic_image_deref_atomic_add:
264 case nir_intrinsic_image_deref_atomic_min:
265 case nir_intrinsic_image_deref_atomic_max:
266 case nir_intrinsic_image_deref_atomic_and:
267 case nir_intrinsic_image_deref_atomic_or:
268 case nir_intrinsic_image_deref_atomic_xor:
269 case nir_intrinsic_image_deref_atomic_exchange:
270 case nir_intrinsic_image_deref_atomic_comp_swap:
271 case nir_intrinsic_image_deref_store:
272 case nir_intrinsic_image_deref_size:
273 idx = nir_intrinsic_get_var(intr, 0)->data.driver_location;
274 if (layout->image_dims.mask & (1 << idx))
275 break;
276 layout->image_dims.mask |= (1 << idx);
277 layout->image_dims.off[idx] =
278 layout->image_dims.count;
279 layout->image_dims.count += 3; /* three const per */
280 break;
281 default:
282 break;
283 }
284 }
285 }
286 }
287 }