2 * Copyright © 2019 Google, Inc.
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
25 #include "ir3_compiler.h"
26 #include "compiler/nir/nir_builder.h"
31 struct primitive_map
{
39 nir_variable
*vertex_count_var
;
40 nir_variable
*emitted_vertex_var
;
41 nir_variable
*vertex_flags_var
;
42 nir_variable
*vertex_flags_out
;
44 nir_variable
*output_vars
[32];
46 nir_ssa_def
*outer_levels
[4];
47 nir_ssa_def
*inner_levels
[2];
51 bitfield_extract(nir_builder
*b
, nir_ssa_def
*v
, uint32_t start
, uint32_t mask
)
53 return nir_iand(b
, nir_ushr(b
, v
, nir_imm_int(b
, start
)),
54 nir_imm_int(b
, mask
));
58 build_invocation_id(nir_builder
*b
, struct state
*state
)
60 return bitfield_extract(b
, state
->header
, 11, 31);
64 build_vertex_id(nir_builder
*b
, struct state
*state
)
66 return bitfield_extract(b
, state
->header
, 6, 31);
70 build_local_primitive_id(nir_builder
*b
, struct state
*state
)
72 return bitfield_extract(b
, state
->header
, 0, 63);
76 get_var(struct exec_list
*list
, int driver_location
)
78 nir_foreach_variable(v
, list
) {
79 if (v
->data
.driver_location
== driver_location
) {
88 build_local_offset(nir_builder
*b
, struct state
*state
,
89 nir_ssa_def
*vertex
, uint32_t base
, nir_ssa_def
*offset
)
91 nir_ssa_def
*primitive_stride
= nir_load_vs_primitive_stride_ir3(b
);
92 nir_ssa_def
*primitive_offset
=
93 nir_imul24(b
, build_local_primitive_id(b
, state
), primitive_stride
);
94 nir_ssa_def
*attr_offset
;
95 nir_ssa_def
*vertex_stride
;
97 switch (b
->shader
->info
.stage
) {
98 case MESA_SHADER_VERTEX
:
99 case MESA_SHADER_TESS_EVAL
:
100 vertex_stride
= nir_imm_int(b
, state
->map
.stride
* 4);
101 attr_offset
= nir_imm_int(b
, state
->map
.loc
[base
] * 4);
103 case MESA_SHADER_TESS_CTRL
:
104 case MESA_SHADER_GEOMETRY
:
105 vertex_stride
= nir_load_vs_vertex_stride_ir3(b
);
106 attr_offset
= nir_load_primitive_location_ir3(b
, base
);
109 unreachable("bad shader stage");
112 nir_ssa_def
*vertex_offset
= nir_imul24(b
, vertex
, vertex_stride
);
114 return nir_iadd(b
, nir_iadd(b
, primitive_offset
, vertex_offset
),
115 nir_iadd(b
, attr_offset
, offset
));
118 static nir_intrinsic_instr
*
119 replace_intrinsic(nir_builder
*b
, nir_intrinsic_instr
*intr
,
120 nir_intrinsic_op op
, nir_ssa_def
*src0
, nir_ssa_def
*src1
, nir_ssa_def
*src2
)
122 nir_intrinsic_instr
*new_intr
=
123 nir_intrinsic_instr_create(b
->shader
, op
);
125 new_intr
->src
[0] = nir_src_for_ssa(src0
);
127 new_intr
->src
[1] = nir_src_for_ssa(src1
);
129 new_intr
->src
[2] = nir_src_for_ssa(src2
);
131 new_intr
->num_components
= intr
->num_components
;
133 if (nir_intrinsic_infos
[op
].has_dest
)
134 nir_ssa_dest_init(&new_intr
->instr
, &new_intr
->dest
,
135 intr
->num_components
, 32, NULL
);
137 nir_builder_instr_insert(b
, &new_intr
->instr
);
139 if (nir_intrinsic_infos
[op
].has_dest
)
140 nir_ssa_def_rewrite_uses(&intr
->dest
.ssa
, nir_src_for_ssa(&new_intr
->dest
.ssa
));
142 nir_instr_remove(&intr
->instr
);
148 build_primitive_map(nir_shader
*shader
, struct primitive_map
*map
, struct exec_list
*list
)
150 nir_foreach_variable(var
, list
) {
151 switch (var
->data
.location
) {
152 case VARYING_SLOT_TESS_LEVEL_OUTER
:
153 case VARYING_SLOT_TESS_LEVEL_INNER
:
157 unsigned size
= glsl_count_attribute_slots(var
->type
, false) * 4;
159 assert(var
->data
.driver_location
< ARRAY_SIZE(map
->size
));
160 map
->size
[var
->data
.driver_location
] =
161 MAX2(map
->size
[var
->data
.driver_location
], size
);
165 for (uint32_t i
= 0; i
< ARRAY_SIZE(map
->size
); i
++) {
166 if (map
->size
[i
] == 0)
168 nir_variable
*var
= get_var(list
, i
);
175 map
->size
[i
] = map
->size
[i
] / glsl_get_length(var
->type
);
182 lower_vs_block(nir_block
*block
, nir_builder
*b
, struct state
*state
)
184 nir_foreach_instr_safe(instr
, block
) {
185 if (instr
->type
!= nir_instr_type_intrinsic
)
188 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
190 switch (intr
->intrinsic
) {
191 case nir_intrinsic_store_output
: {
192 // src[] = { value, offset }.
194 b
->cursor
= nir_instr_remove(&intr
->instr
);
196 nir_ssa_def
*vertex_id
= build_vertex_id(b
, state
);
197 nir_ssa_def
*offset
= build_local_offset(b
, state
, vertex_id
, nir_intrinsic_base(intr
),
199 nir_intrinsic_instr
*store
=
200 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_store_shared_ir3
);
202 nir_intrinsic_set_write_mask(store
, MASK(intr
->num_components
));
203 store
->src
[0] = nir_src_for_ssa(intr
->src
[0].ssa
);
204 store
->src
[1] = nir_src_for_ssa(offset
);
206 store
->num_components
= intr
->num_components
;
208 nir_builder_instr_insert(b
, &store
->instr
);
219 local_thread_id(nir_builder
*b
)
221 return bitfield_extract(b
, nir_load_gs_header_ir3(b
), 16, 1023);
225 ir3_nir_lower_to_explicit_io(nir_shader
*shader
, struct ir3_shader
*s
, unsigned topology
)
227 struct state state
= { };
229 build_primitive_map(shader
, &state
.map
, &shader
->outputs
);
230 memcpy(s
->output_loc
, state
.map
.loc
, sizeof(s
->output_loc
));
232 nir_function_impl
*impl
= nir_shader_get_entrypoint(shader
);
236 nir_builder_init(&b
, impl
);
237 b
.cursor
= nir_before_cf_list(&impl
->body
);
239 if (s
->type
== MESA_SHADER_VERTEX
&& topology
!= IR3_TESS_NONE
)
240 state
.header
= nir_load_tcs_header_ir3(&b
);
242 state
.header
= nir_load_gs_header_ir3(&b
);
244 nir_foreach_block_safe(block
, impl
)
245 lower_vs_block(block
, &b
, &state
);
247 nir_metadata_preserve(impl
, nir_metadata_block_index
|
248 nir_metadata_dominance
);
250 s
->output_size
= state
.map
.stride
;
254 build_per_vertex_offset(nir_builder
*b
, struct state
*state
,
255 nir_ssa_def
*vertex
, nir_ssa_def
*offset
, nir_variable
*var
)
257 nir_ssa_def
*primitive_id
= nir_load_primitive_id(b
);
258 nir_ssa_def
*patch_stride
= nir_load_hs_patch_stride_ir3(b
);
259 nir_ssa_def
*patch_offset
= nir_imul24(b
, primitive_id
, patch_stride
);
260 nir_ssa_def
*attr_offset
;
261 int loc
= var
->data
.driver_location
;
263 switch (b
->shader
->info
.stage
) {
264 case MESA_SHADER_TESS_CTRL
:
265 attr_offset
= nir_imm_int(b
, state
->map
.loc
[loc
]);
267 case MESA_SHADER_TESS_EVAL
:
268 attr_offset
= nir_load_primitive_location_ir3(b
, loc
);
271 unreachable("bad shader state");
274 nir_ssa_def
*attr_stride
= nir_imm_int(b
, state
->map
.size
[loc
]);
275 nir_ssa_def
*vertex_offset
= nir_imul24(b
, vertex
, attr_stride
);
277 return nir_iadd(b
, nir_iadd(b
, patch_offset
, attr_offset
),
278 nir_iadd(b
, vertex_offset
, nir_ishl(b
, offset
, nir_imm_int(b
, 2))));
282 build_patch_offset(nir_builder
*b
, struct state
*state
, nir_ssa_def
*offset
, nir_variable
*var
)
284 debug_assert(var
&& var
->data
.patch
);
286 return build_per_vertex_offset(b
, state
, nir_imm_int(b
, 0), offset
, var
);
290 build_tessfactor_base(nir_builder
*b
, gl_varying_slot slot
, struct state
*state
)
292 uint32_t inner_levels
, outer_levels
;
293 switch (state
->topology
) {
294 case IR3_TESS_TRIANGLES
:
302 case IR3_TESS_ISOLINES
:
310 const uint32_t patch_stride
= 1 + inner_levels
+ outer_levels
;
312 nir_ssa_def
*primitive_id
= nir_load_primitive_id(b
);
314 nir_ssa_def
*patch_offset
= nir_imul24(b
, primitive_id
, nir_imm_int(b
, patch_stride
));
318 case VARYING_SLOT_TESS_LEVEL_OUTER
:
319 /* There's some kind of header dword, tess levels start at index 1. */
322 case VARYING_SLOT_TESS_LEVEL_INNER
:
323 offset
= 1 + outer_levels
;
329 return nir_iadd(b
, patch_offset
, nir_imm_int(b
, offset
));
333 lower_tess_ctrl_block(nir_block
*block
, nir_builder
*b
, struct state
*state
)
335 nir_foreach_instr_safe(instr
, block
) {
336 if (instr
->type
!= nir_instr_type_intrinsic
)
339 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
341 switch (intr
->intrinsic
) {
342 case nir_intrinsic_load_invocation_id
:
343 b
->cursor
= nir_before_instr(&intr
->instr
);
345 nir_ssa_def
*invocation_id
= build_invocation_id(b
, state
);
346 nir_ssa_def_rewrite_uses(&intr
->dest
.ssa
,
347 nir_src_for_ssa(invocation_id
));
348 nir_instr_remove(&intr
->instr
);
351 case nir_intrinsic_barrier
:
352 /* Hull shaders dispatch 32 wide so an entire patch will always
353 * fit in a single warp and execute in lock-step. Consequently,
354 * we don't need to do anything for TCS barriers so just remove
355 * the intrinsic. Otherwise we'll emit an actual barrier
356 * instructions, which will deadlock.
358 nir_instr_remove(&intr
->instr
);
361 case nir_intrinsic_load_per_vertex_output
: {
362 // src[] = { vertex, offset }.
364 b
->cursor
= nir_before_instr(&intr
->instr
);
366 nir_ssa_def
*address
= nir_load_tess_param_base_ir3(b
);
367 nir_variable
*var
= get_var(&b
->shader
->outputs
, nir_intrinsic_base(intr
));
368 nir_ssa_def
*offset
= build_per_vertex_offset(b
, state
,
369 intr
->src
[0].ssa
, intr
->src
[1].ssa
, var
);
371 replace_intrinsic(b
, intr
, nir_intrinsic_load_global_ir3
, address
, offset
, NULL
);
375 case nir_intrinsic_store_per_vertex_output
: {
376 // src[] = { value, vertex, offset }.
378 b
->cursor
= nir_before_instr(&intr
->instr
);
380 nir_ssa_def
*value
= intr
->src
[0].ssa
;
381 nir_ssa_def
*address
= nir_load_tess_param_base_ir3(b
);
382 nir_variable
*var
= get_var(&b
->shader
->outputs
, nir_intrinsic_base(intr
));
383 nir_ssa_def
*offset
= build_per_vertex_offset(b
, state
,
384 intr
->src
[1].ssa
, intr
->src
[2].ssa
, var
);
386 nir_intrinsic_instr
*store
=
387 replace_intrinsic(b
, intr
, nir_intrinsic_store_global_ir3
, value
, address
,
388 nir_iadd(b
, offset
, nir_imm_int(b
, nir_intrinsic_component(intr
))));
390 nir_intrinsic_set_write_mask(store
, nir_intrinsic_write_mask(intr
));
395 case nir_intrinsic_load_per_vertex_input
: {
396 // src[] = { vertex, offset }.
398 b
->cursor
= nir_before_instr(&intr
->instr
);
400 nir_ssa_def
*offset
= build_local_offset(b
, state
,
401 intr
->src
[0].ssa
, // this is typically gl_InvocationID
402 nir_intrinsic_base(intr
),
405 replace_intrinsic(b
, intr
, nir_intrinsic_load_shared_ir3
, offset
, NULL
, NULL
);
409 case nir_intrinsic_load_tess_level_inner
:
410 case nir_intrinsic_load_tess_level_outer
: {
411 b
->cursor
= nir_before_instr(&intr
->instr
);
413 gl_varying_slot slot
;
414 if (intr
->intrinsic
== nir_intrinsic_load_tess_level_inner
)
415 slot
= VARYING_SLOT_TESS_LEVEL_INNER
;
417 slot
= VARYING_SLOT_TESS_LEVEL_OUTER
;
419 nir_ssa_def
*address
= nir_load_tess_factor_base_ir3(b
);
420 nir_ssa_def
*offset
= build_tessfactor_base(b
, slot
, state
);
422 replace_intrinsic(b
, intr
, nir_intrinsic_load_global_ir3
, address
, offset
, NULL
);
426 case nir_intrinsic_load_output
: {
427 // src[] = { offset }.
429 nir_variable
*var
= get_var(&b
->shader
->outputs
, nir_intrinsic_base(intr
));
431 b
->cursor
= nir_before_instr(&intr
->instr
);
433 nir_ssa_def
*address
= nir_load_tess_param_base_ir3(b
);
434 nir_ssa_def
*offset
= build_patch_offset(b
, state
, intr
->src
[0].ssa
, var
);
436 replace_intrinsic(b
, intr
, nir_intrinsic_load_global_ir3
, address
, offset
, NULL
);
440 case nir_intrinsic_store_output
: {
441 // src[] = { value, offset }.
443 /* write patch output to bo */
445 nir_variable
*var
= get_var(&b
->shader
->outputs
, nir_intrinsic_base(intr
));
447 nir_ssa_def
**levels
= NULL
;
448 if (var
->data
.location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
449 levels
= state
->outer_levels
;
450 else if (var
->data
.location
== VARYING_SLOT_TESS_LEVEL_INNER
)
451 levels
= state
->inner_levels
;
453 b
->cursor
= nir_before_instr(&intr
->instr
);
456 for (int i
= 0; i
< 4; i
++)
457 if (nir_intrinsic_write_mask(intr
) & (1 << i
))
458 levels
[i
] = nir_channel(b
, intr
->src
[0].ssa
, i
);
459 nir_instr_remove(&intr
->instr
);
461 nir_ssa_def
*address
= nir_load_tess_param_base_ir3(b
);
462 nir_ssa_def
*offset
= build_patch_offset(b
, state
, intr
->src
[1].ssa
, var
);
464 debug_assert(nir_intrinsic_component(intr
) == 0);
466 nir_intrinsic_instr
*store
=
467 replace_intrinsic(b
, intr
, nir_intrinsic_store_global_ir3
,
468 intr
->src
[0].ssa
, address
, offset
);
470 nir_intrinsic_set_write_mask(store
, nir_intrinsic_write_mask(intr
));
482 emit_tess_epilouge(nir_builder
*b
, struct state
*state
)
484 nir_ssa_def
*tessfactor_address
= nir_load_tess_factor_base_ir3(b
);
485 nir_ssa_def
*levels
[2];
487 /* Then emit the epilogue that actually writes out the tessellation levels
490 switch (state
->topology
) {
491 case IR3_TESS_TRIANGLES
:
492 levels
[0] = nir_vec4(b
, state
->outer_levels
[0], state
->outer_levels
[1],
493 state
->outer_levels
[2], state
->inner_levels
[0]);
497 levels
[0] = nir_vec4(b
, state
->outer_levels
[0], state
->outer_levels
[1],
498 state
->outer_levels
[2], state
->outer_levels
[3]);
499 levels
[1] = nir_vec2(b
, state
->inner_levels
[0], state
->inner_levels
[1]);
501 case IR3_TESS_ISOLINES
:
502 levels
[0] = nir_vec2(b
, state
->outer_levels
[0], state
->outer_levels
[1]);
509 nir_ssa_def
*offset
= build_tessfactor_base(b
, VARYING_SLOT_TESS_LEVEL_OUTER
, state
);
511 nir_intrinsic_instr
*store
=
512 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_store_global_ir3
);
514 store
->src
[0] = nir_src_for_ssa(levels
[0]);
515 store
->src
[1] = nir_src_for_ssa(tessfactor_address
);
516 store
->src
[2] = nir_src_for_ssa(offset
);
517 nir_builder_instr_insert(b
, &store
->instr
);
518 store
->num_components
= levels
[0]->num_components
;
519 nir_intrinsic_set_write_mask(store
, (1 << levels
[0]->num_components
) - 1);
522 store
= nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_store_global_ir3
);
523 offset
= nir_iadd(b
, offset
, nir_imm_int(b
, levels
[0]->num_components
));
525 store
->src
[0] = nir_src_for_ssa(levels
[1]);
526 store
->src
[1] = nir_src_for_ssa(tessfactor_address
);
527 store
->src
[2] = nir_src_for_ssa(offset
);
528 nir_builder_instr_insert(b
, &store
->instr
);
529 store
->num_components
= levels
[1]->num_components
;
530 nir_intrinsic_set_write_mask(store
, (1 << levels
[1]->num_components
) - 1);
533 /* Finally, Insert endpatch instruction, maybe signalling the tess engine
534 * that another primitive is ready?
537 nir_intrinsic_instr
*end_patch
=
538 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_end_patch_ir3
);
539 nir_builder_instr_insert(b
, &end_patch
->instr
);
543 ir3_nir_lower_tess_ctrl(nir_shader
*shader
, struct ir3_shader
*s
, unsigned topology
)
545 struct state state
= { .topology
= topology
};
547 if (shader_debug_enabled(shader
->info
.stage
)) {
548 fprintf(stderr
, "NIR (before tess lowering) for %s shader:\n",
549 _mesa_shader_stage_to_string(shader
->info
.stage
));
550 nir_print_shader(shader
, stderr
);
553 build_primitive_map(shader
, &state
.map
, &shader
->outputs
);
554 memcpy(s
->output_loc
, state
.map
.loc
, sizeof(s
->output_loc
));
555 s
->output_size
= state
.map
.stride
;
557 nir_function_impl
*impl
= nir_shader_get_entrypoint(shader
);
561 nir_builder_init(&b
, impl
);
562 b
.cursor
= nir_before_cf_list(&impl
->body
);
564 state
.header
= nir_load_tcs_header_ir3(&b
);
566 nir_foreach_block_safe(block
, impl
)
567 lower_tess_ctrl_block(block
, &b
, &state
);
569 /* Now move the body of the TCS into a conditional:
571 * if (gl_InvocationID < num_vertices)
577 nir_cf_extract(&body
, nir_before_cf_list(&impl
->body
),
578 nir_after_cf_list(&impl
->body
));
580 b
.cursor
= nir_after_cf_list(&impl
->body
);
582 /* Re-emit the header, since the old one got moved into the if branch */
583 state
.header
= nir_load_tcs_header_ir3(&b
);
584 nir_ssa_def
*iid
= build_invocation_id(&b
, &state
);
586 const uint32_t nvertices
= shader
->info
.tess
.tcs_vertices_out
;
587 nir_ssa_def
*cond
= nir_ult(&b
, iid
, nir_imm_int(&b
, nvertices
));
589 nir_if
*nif
= nir_push_if(&b
, cond
);
591 nir_cf_reinsert(&body
, b
.cursor
);
593 b
.cursor
= nir_after_cf_list(&nif
->then_list
);
595 /* Insert conditional exit for threads invocation id != 0 */
596 nir_ssa_def
*iid0_cond
= nir_ieq(&b
, iid
, nir_imm_int(&b
, 0));
597 nir_intrinsic_instr
*cond_end
=
598 nir_intrinsic_instr_create(shader
, nir_intrinsic_cond_end_ir3
);
599 cond_end
->src
[0] = nir_src_for_ssa(iid0_cond
);
600 nir_builder_instr_insert(&b
, &cond_end
->instr
);
602 emit_tess_epilouge(&b
, &state
);
606 nir_metadata_preserve(impl
, 0);
611 lower_tess_eval_block(nir_block
*block
, nir_builder
*b
, struct state
*state
)
613 nir_foreach_instr_safe(instr
, block
) {
614 if (instr
->type
!= nir_instr_type_intrinsic
)
617 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
619 switch (intr
->intrinsic
) {
620 case nir_intrinsic_load_tess_coord
: {
621 b
->cursor
= nir_after_instr(&intr
->instr
);
622 nir_ssa_def
*x
= nir_channel(b
, &intr
->dest
.ssa
, 0);
623 nir_ssa_def
*y
= nir_channel(b
, &intr
->dest
.ssa
, 1);
626 if (state
->topology
== IR3_TESS_TRIANGLES
)
627 z
= nir_fsub(b
, nir_fsub(b
, nir_imm_float(b
, 1.0f
), y
), x
);
629 z
= nir_imm_float(b
, 0.0f
);
631 nir_ssa_def
*coord
= nir_vec3(b
, x
, y
, z
);
633 nir_ssa_def_rewrite_uses_after(&intr
->dest
.ssa
,
634 nir_src_for_ssa(coord
),
639 case nir_intrinsic_load_per_vertex_input
: {
640 // src[] = { vertex, offset }.
642 b
->cursor
= nir_before_instr(&intr
->instr
);
644 nir_ssa_def
*address
= nir_load_tess_param_base_ir3(b
);
645 nir_variable
*var
= get_var(&b
->shader
->inputs
, nir_intrinsic_base(intr
));
646 nir_ssa_def
*offset
= build_per_vertex_offset(b
, state
,
647 intr
->src
[0].ssa
, intr
->src
[1].ssa
, var
);
649 replace_intrinsic(b
, intr
, nir_intrinsic_load_global_ir3
, address
, offset
, NULL
);
653 case nir_intrinsic_load_tess_level_inner
:
654 case nir_intrinsic_load_tess_level_outer
: {
655 b
->cursor
= nir_before_instr(&intr
->instr
);
657 gl_varying_slot slot
;
658 if (intr
->intrinsic
== nir_intrinsic_load_tess_level_inner
)
659 slot
= VARYING_SLOT_TESS_LEVEL_INNER
;
661 slot
= VARYING_SLOT_TESS_LEVEL_OUTER
;
663 nir_ssa_def
*address
= nir_load_tess_factor_base_ir3(b
);
664 nir_ssa_def
*offset
= build_tessfactor_base(b
, slot
, state
);
666 /* Loading across a vec4 (16b) memory boundary is problematic
667 * if we don't use components from the second vec4. The tess
668 * levels aren't guaranteed to be vec4 aligned and we don't
669 * know which levels are actually used, so we load each
670 * component individually.
672 nir_ssa_def
*levels
[4];
673 for (unsigned i
= 0; i
< intr
->num_components
; i
++) {
674 nir_intrinsic_instr
*new_intr
=
675 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_load_global_ir3
);
677 new_intr
->src
[0] = nir_src_for_ssa(address
);
678 new_intr
->src
[1] = nir_src_for_ssa(nir_iadd(b
, offset
, nir_imm_int(b
, i
)));
679 new_intr
->num_components
= 1;
680 nir_ssa_dest_init(&new_intr
->instr
, &new_intr
->dest
, 1, 32, NULL
);
681 nir_builder_instr_insert(b
, &new_intr
->instr
);
682 levels
[i
] = &new_intr
->dest
.ssa
;
685 nir_ssa_def
*v
= nir_vec(b
, levels
, intr
->num_components
);
687 nir_ssa_def_rewrite_uses(&intr
->dest
.ssa
, nir_src_for_ssa(v
));
689 nir_instr_remove(&intr
->instr
);
693 case nir_intrinsic_load_input
: {
694 // src[] = { offset }.
696 nir_variable
*var
= get_var(&b
->shader
->inputs
, nir_intrinsic_base(intr
));
698 debug_assert(var
->data
.patch
);
700 b
->cursor
= nir_before_instr(&intr
->instr
);
702 nir_ssa_def
*address
= nir_load_tess_param_base_ir3(b
);
703 nir_ssa_def
*offset
= build_patch_offset(b
, state
, intr
->src
[0].ssa
, var
);
705 replace_intrinsic(b
, intr
, nir_intrinsic_load_global_ir3
, address
, offset
, NULL
);
716 ir3_nir_lower_tess_eval(nir_shader
*shader
, unsigned topology
)
718 struct state state
= { .topology
= topology
};
720 if (shader_debug_enabled(shader
->info
.stage
)) {
721 fprintf(stderr
, "NIR (before tess lowering) for %s shader:\n",
722 _mesa_shader_stage_to_string(shader
->info
.stage
));
723 nir_print_shader(shader
, stderr
);
726 /* Build map of inputs so we have the sizes. */
727 build_primitive_map(shader
, &state
.map
, &shader
->inputs
);
729 nir_function_impl
*impl
= nir_shader_get_entrypoint(shader
);
733 nir_builder_init(&b
, impl
);
735 nir_foreach_block_safe(block
, impl
)
736 lower_tess_eval_block(block
, &b
, &state
);
738 nir_metadata_preserve(impl
, 0);
742 lower_gs_block(nir_block
*block
, nir_builder
*b
, struct state
*state
)
744 nir_intrinsic_instr
*outputs
[32] = {};
746 nir_foreach_instr_safe(instr
, block
) {
747 if (instr
->type
!= nir_instr_type_intrinsic
)
750 nir_intrinsic_instr
*intr
= nir_instr_as_intrinsic(instr
);
752 switch (intr
->intrinsic
) {
753 case nir_intrinsic_store_output
: {
754 // src[] = { value, offset }.
756 uint32_t loc
= nir_intrinsic_base(intr
);
761 case nir_intrinsic_end_primitive
: {
762 b
->cursor
= nir_before_instr(&intr
->instr
);
763 nir_store_var(b
, state
->vertex_flags_var
, nir_imm_int(b
, 4), 0x1);
764 nir_instr_remove(&intr
->instr
);
768 case nir_intrinsic_emit_vertex
: {
770 /* Load the vertex count */
771 b
->cursor
= nir_before_instr(&intr
->instr
);
772 nir_ssa_def
*count
= nir_load_var(b
, state
->vertex_count_var
);
774 nir_push_if(b
, nir_ieq(b
, count
, local_thread_id(b
)));
776 for (uint32_t i
= 0; i
< ARRAY_SIZE(outputs
); i
++) {
778 nir_store_var(b
, state
->output_vars
[i
],
779 outputs
[i
]->src
[0].ssa
,
780 (1 << outputs
[i
]->num_components
) - 1);
782 nir_instr_remove(&outputs
[i
]->instr
);
787 nir_instr_remove(&intr
->instr
);
789 nir_store_var(b
, state
->emitted_vertex_var
,
790 nir_iadd(b
, nir_load_var(b
, state
->emitted_vertex_var
), nir_imm_int(b
, 1)), 0x1);
792 nir_store_var(b
, state
->vertex_flags_out
,
793 nir_load_var(b
, state
->vertex_flags_var
), 0x1);
797 /* Increment the vertex count by 1 */
798 nir_store_var(b
, state
->vertex_count_var
,
799 nir_iadd(b
, count
, nir_imm_int(b
, 1)), 0x1); /* .x */
800 nir_store_var(b
, state
->vertex_flags_var
, nir_imm_int(b
, 0), 0x1);
805 case nir_intrinsic_load_per_vertex_input
: {
806 // src[] = { vertex, offset }.
808 b
->cursor
= nir_before_instr(&intr
->instr
);
810 nir_ssa_def
*offset
= build_local_offset(b
, state
,
811 intr
->src
[0].ssa
, // this is typically gl_InvocationID
812 nir_intrinsic_base(intr
),
815 replace_intrinsic(b
, intr
, nir_intrinsic_load_shared_ir3
, offset
, NULL
, NULL
);
819 case nir_intrinsic_load_invocation_id
: {
820 b
->cursor
= nir_before_instr(&intr
->instr
);
822 nir_ssa_def
*iid
= build_invocation_id(b
, state
);
823 nir_ssa_def_rewrite_uses(&intr
->dest
.ssa
, nir_src_for_ssa(iid
));
824 nir_instr_remove(&intr
->instr
);
835 emit_store_outputs(nir_builder
*b
, struct state
*state
)
837 /* This also stores the internally added vertex_flags output. */
839 for (uint32_t i
= 0; i
< ARRAY_SIZE(state
->output_vars
); i
++) {
840 if (!state
->output_vars
[i
])
843 nir_intrinsic_instr
*store
=
844 nir_intrinsic_instr_create(b
->shader
, nir_intrinsic_store_output
);
846 nir_intrinsic_set_base(store
, i
);
847 store
->src
[0] = nir_src_for_ssa(nir_load_var(b
, state
->output_vars
[i
]));
848 store
->src
[1] = nir_src_for_ssa(nir_imm_int(b
, 0));
849 store
->num_components
= store
->src
[0].ssa
->num_components
;
851 nir_builder_instr_insert(b
, &store
->instr
);
856 clean_up_split_vars(nir_shader
*shader
, struct exec_list
*list
)
858 uint32_t components
[32] = {};
860 nir_foreach_variable(var
, list
) {
862 ((1 << glsl_get_components(glsl_without_array(var
->type
))) - 1) << var
->data
.location_frac
;
863 components
[var
->data
.driver_location
] |= mask
;
866 nir_foreach_variable_safe(var
, list
) {
868 ((1 << glsl_get_components(glsl_without_array(var
->type
))) - 1) << var
->data
.location_frac
;
870 (components
[var
->data
.driver_location
] | mask
) != mask
;
872 exec_node_remove(&var
->node
);
877 ir3_nir_lower_gs(nir_shader
*shader
, struct ir3_shader
*s
)
879 struct state state
= { };
881 if (shader_debug_enabled(shader
->info
.stage
)) {
882 fprintf(stderr
, "NIR (before gs lowering):\n");
883 nir_print_shader(shader
, stderr
);
886 clean_up_split_vars(shader
, &shader
->inputs
);
887 clean_up_split_vars(shader
, &shader
->outputs
);
889 build_primitive_map(shader
, &state
.map
, &shader
->inputs
);
892 nir_foreach_variable(var
, &shader
->outputs
) {
893 uint32_t end
= var
->data
.driver_location
+ glsl_count_attribute_slots(var
->type
, false);
894 loc
= MAX2(loc
, end
);
897 state
.vertex_flags_out
= nir_variable_create(shader
, nir_var_shader_out
,
898 glsl_uint_type(), "vertex_flags");
899 state
.vertex_flags_out
->data
.driver_location
= loc
;
900 state
.vertex_flags_out
->data
.location
= VARYING_SLOT_GS_VERTEX_FLAGS_IR3
;
902 nir_function_impl
*impl
= nir_shader_get_entrypoint(shader
);
906 nir_builder_init(&b
, impl
);
907 b
.cursor
= nir_before_cf_list(&impl
->body
);
909 state
.header
= nir_load_gs_header_ir3(&b
);
911 nir_foreach_variable(var
, &shader
->outputs
) {
912 state
.output_vars
[var
->data
.driver_location
] =
913 nir_local_variable_create(impl
, var
->type
,
914 ralloc_asprintf(var
, "%s:gs-temp", var
->name
));
917 state
.vertex_count_var
=
918 nir_local_variable_create(impl
, glsl_uint_type(), "vertex_count");
919 state
.emitted_vertex_var
=
920 nir_local_variable_create(impl
, glsl_uint_type(), "emitted_vertex");
921 state
.vertex_flags_var
=
922 nir_local_variable_create(impl
, glsl_uint_type(), "vertex_flags");
923 state
.vertex_flags_out
= state
.output_vars
[state
.vertex_flags_out
->data
.driver_location
];
925 /* initialize to 0 */
926 b
.cursor
= nir_before_cf_list(&impl
->body
);
927 nir_store_var(&b
, state
.vertex_count_var
, nir_imm_int(&b
, 0), 0x1);
928 nir_store_var(&b
, state
.emitted_vertex_var
, nir_imm_int(&b
, 0), 0x1);
929 nir_store_var(&b
, state
.vertex_flags_var
, nir_imm_int(&b
, 4), 0x1);
931 nir_foreach_block_safe(block
, impl
)
932 lower_gs_block(block
, &b
, &state
);
934 set_foreach(impl
->end_block
->predecessors
, block_entry
) {
935 struct nir_block
*block
= (void *)block_entry
->key
;
936 b
.cursor
= nir_after_block_before_jump(block
);
938 nir_intrinsic_instr
*discard_if
=
939 nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_discard_if
);
941 nir_ssa_def
*cond
= nir_ieq(&b
, nir_load_var(&b
, state
.emitted_vertex_var
), nir_imm_int(&b
, 0));
943 discard_if
->src
[0] = nir_src_for_ssa(cond
);
945 nir_builder_instr_insert(&b
, &discard_if
->instr
);
947 emit_store_outputs(&b
, &state
);
950 nir_metadata_preserve(impl
, 0);
952 if (shader_debug_enabled(shader
->info
.stage
)) {
953 fprintf(stderr
, "NIR (after gs lowering):\n");
954 nir_print_shader(shader
, stderr
);