src/freedreno/ir3/ir3_shader.c

   1 /*
   2  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include "util/u_atomic.h"
  28 #include "util/u_string.h"
  29 #include "util/u_memory.h"
  30 #include "util/format/u_format.h"
  31
  32 #include "drm/freedreno_drmif.h"
  33
  34 #include "ir3_shader.h"
  35 #include "ir3_compiler.h"
  36 #include "ir3_nir.h"
  37
  38 int
  39 ir3_glsl_type_size(const struct glsl_type *type, bool bindless)
  40 {
  41         return glsl_count_attribute_slots(type, false);
  42 }
  43
  44 /* for vertex shader, the inputs are loaded into registers before the shader
  45  * is executed, so max_regs from the shader instructions might not properly
  46  * reflect the # of registers actually used, especially in case passthrough
  47  * varyings.
  48  *
  49  * Likewise, for fragment shader, we can have some regs which are passed
  50  * input values but never touched by the resulting shader (ie. as result
  51  * of dead code elimination or simply because we don't know how to turn
  52  * the reg off.
  53  */
  54 static void
  55 fixup_regfootprint(struct ir3_shader_variant *v)
  56 {
  57         unsigned i;
  58
  59         for (i = 0; i < v->inputs_count; i++) {
  60                 /* skip frag inputs fetch via bary.f since their reg's are
  61                  * not written by gpu before shader starts (and in fact the
  62                  * regid's might not even be valid)
  63                  */
  64                 if (v->inputs[i].bary)
  65                         continue;
  66
  67                 /* ignore high regs that are global to all threads in a warp
  68                  * (they exist by default) (a5xx+)
  69                  */
  70                 if (v->inputs[i].regid >= regid(48,0))
  71                         continue;
  72
  73                 if (v->inputs[i].compmask) {
  74                         unsigned n = util_last_bit(v->inputs[i].compmask) - 1;
  75                         int32_t regid = v->inputs[i].regid + n;
  76                         if (v->inputs[i].half) {
  77                                 if (!v->mergedregs) {
  78                                         v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
  79                                 } else {
  80                                         v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
  81                                 }
  82                         } else {
  83                                 v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
  84                         }
  85                 }
  86         }
  87
  88         for (i = 0; i < v->outputs_count; i++) {
  89                 /* for ex, VS shaders with tess don't have normal varying outs: */
  90                 if (!VALIDREG(v->outputs[i].regid))
  91                         continue;
  92                 int32_t regid = v->outputs[i].regid + 3;
  93                 if (v->outputs[i].half) {
  94                         if (!v->mergedregs) {
  95                                 v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
  96                         } else {
  97                                 v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
  98                         }
  99                 } else {
 100                         v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
 101                 }
 102         }
 103
 104         for (i = 0; i < v->num_sampler_prefetch; i++) {
 105                 unsigned n = util_last_bit(v->sampler_prefetch[i].wrmask) - 1;
 106                 int32_t regid = v->sampler_prefetch[i].dst + n;
 107                 if (v->sampler_prefetch[i].half_precision) {
 108                         if (!v->mergedregs) {
 109                                 v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
 110                         } else {
 111                                 v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
 112                         }
 113                 } else {
 114                         v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
 115                 }
 116         }
 117 }
 118
 119 /* wrapper for ir3_assemble() which does some info fixup based on
 120  * shader state.  Non-static since used by ir3_cmdline too.
 121  */
 122 void * ir3_shader_assemble(struct ir3_shader_variant *v)
 123 {
 124         unsigned gpu_id = v->shader->compiler->gpu_id;
 125         void *bin;
 126
 127         bin = ir3_assemble(v);
 128         if (!bin)
 129                 return NULL;
 130
 131         if (gpu_id >= 400) {
 132                 v->instrlen = v->info.sizedwords / (2 * 16);
 133         } else {
 134                 v->instrlen = v->info.sizedwords / (2 * 4);
 135         }
 136
 137         /* NOTE: if relative addressing is used, we set constlen in
 138          * the compiler (to worst-case value) since we don't know in
 139          * the assembler what the max addr reg value can be:
 140          */
 141         v->constlen = MAX2(v->constlen, v->info.max_const + 1);
 142
 143         fixup_regfootprint(v);
 144
 145         return bin;
 146 }
 147
 148 static void
 149 assemble_variant(struct ir3_shader_variant *v)
 150 {
 151         v->bin = ir3_shader_assemble(v);
 152
 153         if (shader_debug_enabled(v->shader->type)) {
 154                 fprintf(stdout, "Native code for unnamed %s shader %s:\n",
 155                         ir3_shader_stage(v), v->shader->nir->info.name);
 156                 if (v->shader->type == MESA_SHADER_FRAGMENT)
 157                         fprintf(stdout, "SIMD0\n");
 158                 ir3_shader_disasm(v, v->bin, stdout);
 159         }
 160
 161         /* no need to keep the ir around beyond this point: */
 162         ir3_destroy(v->ir);
 163         v->ir = NULL;
 164 }
 165
 166 /*
 167  * For creating normal shader variants, 'nonbinning' is NULL.  For
 168  * creating binning pass shader, it is link to corresponding normal
 169  * (non-binning) variant.
 170  */
 171 static struct ir3_shader_variant *
 172 create_variant(struct ir3_shader *shader, const struct ir3_shader_key *key,
 173                 struct ir3_shader_variant *nonbinning)
 174 {
 175         struct ir3_shader_variant *v = rzalloc_size(shader, sizeof(*v));
 176         int ret;
 177
 178         if (!v)
 179                 return NULL;
 180
 181         v->id = ++shader->variant_count;
 182         v->shader = shader;
 183         v->binning_pass = !!nonbinning;
 184         v->nonbinning = nonbinning;
 185         v->key = *key;
 186         v->type = shader->type;
 187         v->mergedregs = shader->compiler->gpu_id >= 600;
 188
 189         if (!v->binning_pass)
 190                 v->const_state = rzalloc_size(v, sizeof(*v->const_state));
 191
 192         ret = ir3_compile_shader_nir(shader->compiler, v);
 193         if (ret) {
 194                 debug_error("compile failed!");
 195                 goto fail;
 196         }
 197
 198         assemble_variant(v);
 199         if (!v->bin) {
 200                 debug_error("assemble failed!");
 201                 goto fail;
 202         }
 203
 204         return v;
 205
 206 fail:
 207         ralloc_free(v);
 208         return NULL;
 209 }
 210
 211 static inline struct ir3_shader_variant *
 212 shader_variant(struct ir3_shader *shader, const struct ir3_shader_key *key,
 213                 bool *created)
 214 {
 215         struct ir3_shader_variant *v;
 216
 217         *created = false;
 218
 219         for (v = shader->variants; v; v = v->next)
 220                 if (ir3_shader_key_equal(key, &v->key))
 221                         return v;
 222
 223         /* compile new variant if it doesn't exist already: */
 224         v = create_variant(shader, key, NULL);
 225         if (v) {
 226                 v->next = shader->variants;
 227                 shader->variants = v;
 228                 *created = true;
 229         }
 230
 231         return v;
 232 }
 233
 234 struct ir3_shader_variant *
 235 ir3_shader_get_variant(struct ir3_shader *shader, const struct ir3_shader_key *key,
 236                 bool binning_pass, bool *created)
 237 {
 238         mtx_lock(&shader->variants_lock);
 239         struct ir3_shader_variant *v =
 240                         shader_variant(shader, key, created);
 241
 242         if (v && binning_pass) {
 243                 if (!v->binning) {
 244                         v->binning = create_variant(shader, key, v);
 245                         *created = true;
 246                 }
 247                 mtx_unlock(&shader->variants_lock);
 248                 return v->binning;
 249         }
 250         mtx_unlock(&shader->variants_lock);
 251
 252         return v;
 253 }
 254
 255 void
 256 ir3_shader_destroy(struct ir3_shader *shader)
 257 {
 258         ralloc_free(shader->nir);
 259         mtx_destroy(&shader->variants_lock);
 260         ralloc_free(shader);
 261 }
 262
 263 /**
 264  * Creates a bitmask of the used bits of the shader key by this particular
 265  * shader.  Used by the gallium driver to skip state-dependent recompiles when
 266  * possible.
 267  */
 268 static void
 269 ir3_setup_used_key(struct ir3_shader *shader)
 270 {
 271         nir_shader *nir = shader->nir;
 272         struct shader_info *info = &nir->info;
 273         struct ir3_shader_key *key = &shader->key_mask;
 274
 275         /* This key flag is just used to make for a cheaper ir3_shader_key_equal
 276          * check in the common case.
 277          */
 278         key->has_per_samp = true;
 279
 280         if (info->stage == MESA_SHADER_FRAGMENT) {
 281                 key->fsaturate_s = ~0;
 282                 key->fsaturate_t = ~0;
 283                 key->fsaturate_r = ~0;
 284                 key->fastc_srgb = ~0;
 285                 key->fsamples = ~0;
 286
 287                 if (info->inputs_read & VARYING_BITS_COLOR) {
 288                         key->rasterflat = true;
 289                         key->color_two_side = true;
 290                 }
 291
 292                 if ((info->outputs_written & ~(FRAG_RESULT_DEPTH |
 293                                                                 FRAG_RESULT_STENCIL |
 294                                                                 FRAG_RESULT_SAMPLE_MASK)) != 0) {
 295                         key->fclamp_color = true;
 296                 }
 297
 298                 /* Only used for deciding on behavior of
 299                  * nir_intrinsic_load_barycentric_sample
 300                  */
 301                 key->msaa = info->fs.uses_sample_qualifier;
 302         } else {
 303                 key->tessellation = ~0;
 304                 key->has_gs = true;
 305
 306                 if (info->outputs_written & VARYING_BITS_COLOR)
 307                         key->vclamp_color = true;
 308
 309                 if (info->stage == MESA_SHADER_VERTEX) {
 310                         key->vsaturate_s = ~0;
 311                         key->vsaturate_t = ~0;
 312                         key->vsaturate_r = ~0;
 313                         key->vastc_srgb = ~0;
 314                         key->vsamples = ~0;
 315                 }
 316         }
 317 }
 318
 319 struct ir3_shader *
 320 ir3_shader_from_nir(struct ir3_compiler *compiler, nir_shader *nir,
 321                 unsigned reserved_user_consts, struct ir3_stream_output_info *stream_output)
 322 {
 323         struct ir3_shader *shader = rzalloc_size(NULL, sizeof(*shader));
 324
 325         mtx_init(&shader->variants_lock, mtx_plain);
 326         shader->compiler = compiler;
 327         shader->id = p_atomic_inc_return(&shader->compiler->shader_count);
 328         shader->type = nir->info.stage;
 329         if (stream_output)
 330                 memcpy(&shader->stream_output, stream_output, sizeof(shader->stream_output));
 331         shader->num_reserved_user_consts = reserved_user_consts;
 332
 333         if (nir->info.stage == MESA_SHADER_GEOMETRY)
 334                 NIR_PASS_V(nir, ir3_nir_lower_gs);
 335
 336         NIR_PASS_V(nir, nir_lower_io, nir_var_all, ir3_glsl_type_size,
 337                            (nir_lower_io_options)0);
 338
 339         if (compiler->gpu_id >= 600 &&
 340                         nir->info.stage == MESA_SHADER_FRAGMENT &&
 341                         !(ir3_shader_debug & IR3_DBG_NOFP16))
 342                 NIR_PASS_V(nir, nir_lower_mediump_outputs);
 343
 344         if (nir->info.stage == MESA_SHADER_FRAGMENT) {
 345                 /* NOTE: lower load_barycentric_at_sample first, since it
 346                  * produces load_barycentric_at_offset:
 347                  */
 348                 NIR_PASS_V(nir, ir3_nir_lower_load_barycentric_at_sample);
 349                 NIR_PASS_V(nir, ir3_nir_lower_load_barycentric_at_offset);
 350
 351                 NIR_PASS_V(nir, ir3_nir_move_varying_inputs);
 352         }
 353
 354         NIR_PASS_V(nir, nir_lower_io_arrays_to_elements_no_indirects, false);
 355
 356         NIR_PASS_V(nir, nir_lower_amul, ir3_glsl_type_size);
 357
 358         /* do first pass optimization, ignoring the key: */
 359         ir3_optimize_nir(shader, nir);
 360
 361         shader->nir = nir;
 362         if (ir3_shader_debug & IR3_DBG_DISASM) {
 363                 printf("dump nir%d: type=%d", shader->id, shader->type);
 364                 nir_print_shader(shader->nir, stdout);
 365         }
 366
 367         ir3_setup_used_key(shader);
 368
 369         return shader;
 370 }
 371
 372 static void dump_reg(FILE *out, const char *name, uint32_t r)
 373 {
 374         if (r != regid(63,0)) {
 375                 const char *reg_type = (r & HALF_REG_ID) ? "hr" : "r";
 376                 fprintf(out, "; %s: %s%d.%c\n", name, reg_type,
 377                                 (r & ~HALF_REG_ID) >> 2, "xyzw"[r & 0x3]);
 378         }
 379 }
 380
 381 static void dump_output(FILE *out, struct ir3_shader_variant *so,
 382                 unsigned slot, const char *name)
 383 {
 384         uint32_t regid;
 385         regid = ir3_find_output_regid(so, slot);
 386         dump_reg(out, name, regid);
 387 }
 388
 389 static const char *
 390 input_name(struct ir3_shader_variant *so, int i)
 391 {
 392         if (so->inputs[i].sysval) {
 393                 return gl_system_value_name(so->inputs[i].slot);
 394         } else if (so->type == MESA_SHADER_VERTEX) {
 395                 return gl_vert_attrib_name(so->inputs[i].slot);
 396         } else {
 397                 return gl_varying_slot_name(so->inputs[i].slot);
 398         }
 399 }
 400
 401 static const char *
 402 output_name(struct ir3_shader_variant *so, int i)
 403 {
 404         if (so->type == MESA_SHADER_FRAGMENT) {
 405                 return gl_frag_result_name(so->outputs[i].slot);
 406         } else {
 407                 switch (so->outputs[i].slot) {
 408                 case VARYING_SLOT_GS_HEADER_IR3:
 409                         return "GS_HEADER";
 410                 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
 411                         return "GS_VERTEX_FLAGS";
 412                 case VARYING_SLOT_TCS_HEADER_IR3:
 413                         return "TCS_HEADER";
 414                 default:
 415                         return gl_varying_slot_name(so->outputs[i].slot);
 416                 }
 417         }
 418 }
 419
 420 void
 421 ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin, FILE *out)
 422 {
 423         struct ir3 *ir = so->ir;
 424         struct ir3_register *reg;
 425         const char *type = ir3_shader_stage(so);
 426         uint8_t regid;
 427         unsigned i;
 428
 429         foreach_input_n (instr, i, ir) {
 430                 reg = instr->regs[0];
 431                 regid = reg->num;
 432                 fprintf(out, "@in(%sr%d.%c)\tin%d",
 433                                 (reg->flags & IR3_REG_HALF) ? "h" : "",
 434                                 (regid >> 2), "xyzw"[regid & 0x3], i);
 435
 436                 if (reg->wrmask > 0x1)
 437                         fprintf(out, " (wrmask=0x%x)", reg->wrmask);
 438                 fprintf(out, "\n");
 439         }
 440
 441         /* print pre-dispatch texture fetches: */
 442         for (i = 0; i < so->num_sampler_prefetch; i++) {
 443                 const struct ir3_sampler_prefetch *fetch = &so->sampler_prefetch[i];
 444                 fprintf(out, "@tex(%sr%d.%c)\tsrc=%u, samp=%u, tex=%u, wrmask=0x%x, cmd=%u\n",
 445                                 fetch->half_precision ? "h" : "",
 446                                 fetch->dst >> 2, "xyzw"[fetch->dst & 0x3],
 447                                 fetch->src, fetch->samp_id, fetch->tex_id,
 448                                 fetch->wrmask, fetch->cmd);
 449         }
 450
 451         foreach_output_n (instr, i, ir) {
 452                 reg = instr->regs[0];
 453                 regid = reg->num;
 454                 fprintf(out, "@out(%sr%d.%c)\tout%d",
 455                                 (reg->flags & IR3_REG_HALF) ? "h" : "",
 456                                 (regid >> 2), "xyzw"[regid & 0x3], i);
 457                 if (reg->wrmask > 0x1)
 458                         fprintf(out, " (wrmask=0x%x)", reg->wrmask);
 459                 fprintf(out, "\n");
 460         }
 461
 462         const struct ir3_const_state *const_state = ir3_const_state(so);
 463         for (i = 0; i < const_state->immediates_count; i++) {
 464                 fprintf(out, "@const(c%d.x)\t", const_state->offsets.immediate + i);
 465                 fprintf(out, "0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
 466                                 const_state->immediates[i].val[0],
 467                                 const_state->immediates[i].val[1],
 468                                 const_state->immediates[i].val[2],
 469                                 const_state->immediates[i].val[3]);
 470         }
 471
 472         disasm_a3xx(bin, so->info.sizedwords, 0, out, ir->compiler->gpu_id);
 473
 474         fprintf(out, "; %s: outputs:", type);
 475         for (i = 0; i < so->outputs_count; i++) {
 476                 uint8_t regid = so->outputs[i].regid;
 477                 const char *reg_type = so->outputs[i].half ? "hr" : "r";
 478                 fprintf(out, " %s%d.%c (%s)",
 479                                 reg_type, (regid >> 2), "xyzw"[regid & 0x3],
 480                                 output_name(so, i));
 481         }
 482         fprintf(out, "\n");
 483
 484         fprintf(out, "; %s: inputs:", type);
 485         for (i = 0; i < so->inputs_count; i++) {
 486                 uint8_t regid = so->inputs[i].regid;
 487                 fprintf(out, " r%d.%c (%s slot=%d cm=%x,il=%u,b=%u)",
 488                                 (regid >> 2), "xyzw"[regid & 0x3],
 489                                 input_name(so, i),
 490                                 so->inputs[i].slot,
 491                                 so->inputs[i].compmask,
 492                                 so->inputs[i].inloc,
 493                                 so->inputs[i].bary);
 494         }
 495         fprintf(out, "\n");
 496
 497         /* print generic shader info: */
 498         fprintf(out, "; %s prog %d/%d: %u instr, %u nops, %u non-nops, %u mov, %u cov, %u dwords\n",
 499                         type, so->shader->id, so->id,
 500                         so->info.instrs_count,
 501                         so->info.nops_count,
 502                         so->info.instrs_count - so->info.nops_count,
 503                         so->info.mov_count, so->info.cov_count,
 504                         so->info.sizedwords);
 505
 506         fprintf(out, "; %s prog %d/%d: %u last-baryf, %d half, %d full, %u constlen\n",
 507                         type, so->shader->id, so->id,
 508                         so->info.last_baryf,
 509                         so->info.max_half_reg + 1,
 510                         so->info.max_reg + 1,
 511                         so->constlen);
 512
 513         fprintf(out, "; %s prog %d/%d: %u sstall, %u (ss), %u (sy), %d max_sun, %d loops\n",
 514                         type, so->shader->id, so->id,
 515                         so->info.sstall,
 516                         so->info.ss,
 517                         so->info.sy,
 518                         so->max_sun,
 519                         so->loops);
 520
 521         /* print shader type specific info: */
 522         switch (so->type) {
 523         case MESA_SHADER_VERTEX:
 524                 dump_output(out, so, VARYING_SLOT_POS, "pos");
 525                 dump_output(out, so, VARYING_SLOT_PSIZ, "psize");
 526                 break;
 527         case MESA_SHADER_FRAGMENT:
 528                 dump_reg(out, "pos (ij_pixel)",
 529                         ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL));
 530                 dump_reg(out, "pos (ij_centroid)",
 531                         ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID));
 532                 dump_reg(out, "pos (ij_size)",
 533                         ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE));
 534                 dump_output(out, so, FRAG_RESULT_DEPTH, "posz");
 535                 if (so->color0_mrt) {
 536                         dump_output(out, so, FRAG_RESULT_COLOR, "color");
 537                 } else {
 538                         dump_output(out, so, FRAG_RESULT_DATA0, "data0");
 539                         dump_output(out, so, FRAG_RESULT_DATA1, "data1");
 540                         dump_output(out, so, FRAG_RESULT_DATA2, "data2");
 541                         dump_output(out, so, FRAG_RESULT_DATA3, "data3");
 542                         dump_output(out, so, FRAG_RESULT_DATA4, "data4");
 543                         dump_output(out, so, FRAG_RESULT_DATA5, "data5");
 544                         dump_output(out, so, FRAG_RESULT_DATA6, "data6");
 545                         dump_output(out, so, FRAG_RESULT_DATA7, "data7");
 546                 }
 547                 dump_reg(out, "fragcoord",
 548                         ir3_find_sysval_regid(so, SYSTEM_VALUE_FRAG_COORD));
 549                 dump_reg(out, "fragface",
 550                         ir3_find_sysval_regid(so, SYSTEM_VALUE_FRONT_FACE));
 551                 break;
 552         default:
 553                 /* TODO */
 554                 break;
 555         }
 556
 557         fprintf(out, "\n");
 558 }
 559
 560 uint64_t
 561 ir3_shader_outputs(const struct ir3_shader *so)
 562 {
 563         return so->nir->info.outputs_written;
 564 }