2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "util/u_atomic.h"
28 #include "util/u_string.h"
29 #include "util/u_math.h"
30 #include "util/u_memory.h"
31 #include "util/format/u_format.h"
33 #include "drm/freedreno_drmif.h"
35 #include "ir3_shader.h"
36 #include "ir3_compiler.h"
42 ir3_glsl_type_size(const struct glsl_type
*type
, bool bindless
)
44 return glsl_count_attribute_slots(type
, false);
47 /* for vertex shader, the inputs are loaded into registers before the shader
48 * is executed, so max_regs from the shader instructions might not properly
49 * reflect the # of registers actually used, especially in case passthrough
52 * Likewise, for fragment shader, we can have some regs which are passed
53 * input values but never touched by the resulting shader (ie. as result
54 * of dead code elimination or simply because we don't know how to turn
58 fixup_regfootprint(struct ir3_shader_variant
*v
)
62 for (i
= 0; i
< v
->inputs_count
; i
++) {
63 /* skip frag inputs fetch via bary.f since their reg's are
64 * not written by gpu before shader starts (and in fact the
65 * regid's might not even be valid)
67 if (v
->inputs
[i
].bary
)
70 /* ignore high regs that are global to all threads in a warp
71 * (they exist by default) (a5xx+)
73 if (v
->inputs
[i
].regid
>= regid(48,0))
76 if (v
->inputs
[i
].compmask
) {
77 unsigned n
= util_last_bit(v
->inputs
[i
].compmask
) - 1;
78 int32_t regid
= v
->inputs
[i
].regid
+ n
;
79 if (v
->inputs
[i
].half
) {
81 v
->info
.max_half_reg
= MAX2(v
->info
.max_half_reg
, regid
>> 2);
83 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 3);
86 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 2);
91 for (i
= 0; i
< v
->outputs_count
; i
++) {
92 /* for ex, VS shaders with tess don't have normal varying outs: */
93 if (!VALIDREG(v
->outputs
[i
].regid
))
95 int32_t regid
= v
->outputs
[i
].regid
+ 3;
96 if (v
->outputs
[i
].half
) {
98 v
->info
.max_half_reg
= MAX2(v
->info
.max_half_reg
, regid
>> 2);
100 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 3);
103 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 2);
107 for (i
= 0; i
< v
->num_sampler_prefetch
; i
++) {
108 unsigned n
= util_last_bit(v
->sampler_prefetch
[i
].wrmask
) - 1;
109 int32_t regid
= v
->sampler_prefetch
[i
].dst
+ n
;
110 if (v
->sampler_prefetch
[i
].half_precision
) {
111 if (!v
->mergedregs
) {
112 v
->info
.max_half_reg
= MAX2(v
->info
.max_half_reg
, regid
>> 2);
114 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 3);
117 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 2);
122 /* wrapper for ir3_assemble() which does some info fixup based on
123 * shader state. Non-static since used by ir3_cmdline too.
125 void * ir3_shader_assemble(struct ir3_shader_variant
*v
)
127 unsigned gpu_id
= v
->shader
->compiler
->gpu_id
;
130 bin
= ir3_assemble(v
);
135 v
->instrlen
= v
->info
.sizedwords
/ (2 * 16);
137 v
->instrlen
= v
->info
.sizedwords
/ (2 * 4);
140 /* NOTE: if relative addressing is used, we set constlen in
141 * the compiler (to worst-case value) since we don't know in
142 * the assembler what the max addr reg value can be:
144 v
->constlen
= MAX2(v
->constlen
, v
->info
.max_const
+ 1);
146 /* On a4xx and newer, constlen must be a multiple of 16 dwords even though
147 * uploads are in units of 4 dwords. Round it up here to make calculations
148 * regarding the shared constlen simpler.
151 v
->constlen
= align(v
->constlen
, 4);
153 fixup_regfootprint(v
);
159 assemble_variant(struct ir3_shader_variant
*v
)
161 v
->bin
= ir3_shader_assemble(v
);
163 if (shader_debug_enabled(v
->shader
->type
)) {
164 fprintf(stdout
, "Native code for unnamed %s shader %s:\n",
165 ir3_shader_stage(v
), v
->shader
->nir
->info
.name
);
166 if (v
->shader
->type
== MESA_SHADER_FRAGMENT
)
167 fprintf(stdout
, "SIMD0\n");
168 ir3_shader_disasm(v
, v
->bin
, stdout
);
171 /* no need to keep the ir around beyond this point: */
177 compile_variant(struct ir3_shader_variant
*v
)
179 int ret
= ir3_compile_shader_nir(v
->shader
->compiler
, v
);
181 _debug_printf("compile failed! (%s:%s)", v
->shader
->nir
->info
.name
,
182 v
->shader
->nir
->info
.label
);
188 _debug_printf("assemble failed! (%s:%s)", v
->shader
->nir
->info
.name
,
189 v
->shader
->nir
->info
.label
);
197 * For creating normal shader variants, 'nonbinning' is NULL. For
198 * creating binning pass shader, it is link to corresponding normal
199 * (non-binning) variant.
201 static struct ir3_shader_variant
*
202 alloc_variant(struct ir3_shader
*shader
, const struct ir3_shader_key
*key
,
203 struct ir3_shader_variant
*nonbinning
)
205 void *mem_ctx
= shader
;
206 /* hang the binning variant off it's non-binning counterpart instead
207 * of the shader, to simplify the error cleanup paths
210 mem_ctx
= nonbinning
;
211 struct ir3_shader_variant
*v
= rzalloc_size(mem_ctx
, sizeof(*v
));
216 v
->id
= ++shader
->variant_count
;
218 v
->binning_pass
= !!nonbinning
;
219 v
->nonbinning
= nonbinning
;
221 v
->type
= shader
->type
;
222 v
->mergedregs
= shader
->compiler
->gpu_id
>= 600;
224 if (!v
->binning_pass
)
225 v
->const_state
= rzalloc_size(v
, sizeof(*v
->const_state
));
231 needs_binning_variant(struct ir3_shader_variant
*v
)
233 if ((v
->type
== MESA_SHADER_VERTEX
) && ir3_has_binning_vs(&v
->key
))
238 static struct ir3_shader_variant
*
239 create_variant(struct ir3_shader
*shader
, const struct ir3_shader_key
*key
)
241 struct ir3_shader_variant
*v
= alloc_variant(shader
, key
, NULL
);
246 if (needs_binning_variant(v
)) {
247 v
->binning
= alloc_variant(shader
, key
, v
);
252 if (ir3_disk_cache_retrieve(shader
->compiler
, v
))
255 if (!shader
->nir_finalized
) {
256 ir3_nir_post_finalize(shader
->compiler
, shader
->nir
);
258 if (ir3_shader_debug
& IR3_DBG_DISASM
) {
259 printf("dump nir%d: type=%d", shader
->id
, shader
->type
);
260 nir_print_shader(shader
->nir
, stdout
);
263 shader
->nir_finalized
= true;
266 if (!compile_variant(v
))
269 if (needs_binning_variant(v
) && !compile_variant(v
->binning
))
272 ir3_disk_cache_store(shader
->compiler
, v
);
281 static inline struct ir3_shader_variant
*
282 shader_variant(struct ir3_shader
*shader
, const struct ir3_shader_key
*key
)
284 struct ir3_shader_variant
*v
;
286 for (v
= shader
->variants
; v
; v
= v
->next
)
287 if (ir3_shader_key_equal(key
, &v
->key
))
293 struct ir3_shader_variant
*
294 ir3_shader_get_variant(struct ir3_shader
*shader
, const struct ir3_shader_key
*key
,
295 bool binning_pass
, bool *created
)
297 mtx_lock(&shader
->variants_lock
);
298 struct ir3_shader_variant
*v
= shader_variant(shader
, key
);
301 /* compile new variant if it doesn't exist already: */
302 v
= create_variant(shader
, key
);
304 v
->next
= shader
->variants
;
305 shader
->variants
= v
;
310 if (v
&& binning_pass
) {
315 mtx_unlock(&shader
->variants_lock
);
321 ir3_shader_destroy(struct ir3_shader
*shader
)
323 ralloc_free(shader
->nir
);
324 mtx_destroy(&shader
->variants_lock
);
329 * Creates a bitmask of the used bits of the shader key by this particular
330 * shader. Used by the gallium driver to skip state-dependent recompiles when
334 ir3_setup_used_key(struct ir3_shader
*shader
)
336 nir_shader
*nir
= shader
->nir
;
337 struct shader_info
*info
= &nir
->info
;
338 struct ir3_shader_key
*key
= &shader
->key_mask
;
340 /* This key flag is just used to make for a cheaper ir3_shader_key_equal
341 * check in the common case.
343 key
->has_per_samp
= true;
345 key
->safe_constlen
= true;
347 key
->ucp_enables
= 0xff;
349 if (info
->stage
== MESA_SHADER_FRAGMENT
) {
350 key
->fsaturate_s
= ~0;
351 key
->fsaturate_t
= ~0;
352 key
->fsaturate_r
= ~0;
353 key
->fastc_srgb
= ~0;
356 if (info
->inputs_read
& VARYING_BITS_COLOR
) {
357 key
->rasterflat
= true;
358 key
->color_two_side
= true;
361 if (info
->inputs_read
& VARYING_BIT_LAYER
) {
362 key
->layer_zero
= true;
365 if ((info
->outputs_written
& ~(FRAG_RESULT_DEPTH
|
366 FRAG_RESULT_STENCIL
|
367 FRAG_RESULT_SAMPLE_MASK
)) != 0) {
368 key
->fclamp_color
= true;
371 /* Only used for deciding on behavior of
372 * nir_intrinsic_load_barycentric_sample
374 key
->msaa
= info
->fs
.uses_sample_qualifier
;
376 key
->tessellation
= ~0;
379 if (info
->outputs_written
& VARYING_BITS_COLOR
)
380 key
->vclamp_color
= true;
382 if (info
->stage
== MESA_SHADER_VERTEX
) {
383 key
->vsaturate_s
= ~0;
384 key
->vsaturate_t
= ~0;
385 key
->vsaturate_r
= ~0;
386 key
->vastc_srgb
= ~0;
393 /* Given an array of constlen's, decrease some of them so that the sum stays
394 * within "combined_limit" while trying to fairly share the reduction. Returns
395 * a bitfield of which stages should be trimmed.
398 trim_constlens(unsigned *constlens
,
399 unsigned first_stage
, unsigned last_stage
,
400 unsigned combined_limit
, unsigned safe_limit
)
402 unsigned cur_total
= 0;
403 for (unsigned i
= first_stage
; i
<= last_stage
; i
++) {
404 cur_total
+= constlens
[i
];
407 unsigned max_stage
= 0;
408 unsigned max_const
= 0;
409 uint32_t trimmed
= 0;
411 while (cur_total
> combined_limit
) {
412 for (unsigned i
= first_stage
; i
<= last_stage
; i
++) {
413 if (constlens
[i
] >= max_const
) {
415 max_const
= constlens
[i
];
419 assert(max_const
> safe_limit
);
420 trimmed
|= 1 << max_stage
;
421 cur_total
= cur_total
- max_const
+ safe_limit
;
422 constlens
[max_stage
] = safe_limit
;
428 /* Figures out which stages in the pipeline to use the "safe" constlen for, in
429 * order to satisfy all shared constlen limits.
432 ir3_trim_constlen(struct ir3_shader_variant
**variants
,
433 const struct ir3_compiler
*compiler
)
435 unsigned constlens
[MESA_SHADER_STAGES
] = {};
437 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
439 constlens
[i
] = variants
[i
]->constlen
;
442 uint32_t trimmed
= 0;
443 STATIC_ASSERT(MESA_SHADER_STAGES
<= 8 * sizeof(trimmed
));
445 /* There are two shared limits to take into account, the geometry limit on
446 * a6xx and the total limit. The frag limit on a6xx only matters for a
447 * single stage, so it's always satisfied with the first variant.
449 if (compiler
->gpu_id
>= 600) {
451 trim_constlens(constlens
, MESA_SHADER_VERTEX
, MESA_SHADER_GEOMETRY
,
452 compiler
->max_const_geom
, compiler
->max_const_safe
);
455 trim_constlens(constlens
, MESA_SHADER_VERTEX
, MESA_SHADER_FRAGMENT
,
456 compiler
->max_const_pipeline
, compiler
->max_const_safe
);
462 ir3_shader_from_nir(struct ir3_compiler
*compiler
, nir_shader
*nir
,
463 unsigned reserved_user_consts
, struct ir3_stream_output_info
*stream_output
)
465 struct ir3_shader
*shader
= rzalloc_size(NULL
, sizeof(*shader
));
467 mtx_init(&shader
->variants_lock
, mtx_plain
);
468 shader
->compiler
= compiler
;
469 shader
->id
= p_atomic_inc_return(&shader
->compiler
->shader_count
);
470 shader
->type
= nir
->info
.stage
;
472 memcpy(&shader
->stream_output
, stream_output
, sizeof(shader
->stream_output
));
473 shader
->num_reserved_user_consts
= reserved_user_consts
;
476 ir3_disk_cache_init_shader_key(compiler
, shader
);
478 ir3_setup_used_key(shader
);
483 static void dump_reg(FILE *out
, const char *name
, uint32_t r
)
485 if (r
!= regid(63,0)) {
486 const char *reg_type
= (r
& HALF_REG_ID
) ? "hr" : "r";
487 fprintf(out
, "; %s: %s%d.%c\n", name
, reg_type
,
488 (r
& ~HALF_REG_ID
) >> 2, "xyzw"[r
& 0x3]);
492 static void dump_output(FILE *out
, struct ir3_shader_variant
*so
,
493 unsigned slot
, const char *name
)
496 regid
= ir3_find_output_regid(so
, slot
);
497 dump_reg(out
, name
, regid
);
501 input_name(struct ir3_shader_variant
*so
, int i
)
503 if (so
->inputs
[i
].sysval
) {
504 return gl_system_value_name(so
->inputs
[i
].slot
);
505 } else if (so
->type
== MESA_SHADER_VERTEX
) {
506 return gl_vert_attrib_name(so
->inputs
[i
].slot
);
508 return gl_varying_slot_name(so
->inputs
[i
].slot
);
513 output_name(struct ir3_shader_variant
*so
, int i
)
515 if (so
->type
== MESA_SHADER_FRAGMENT
) {
516 return gl_frag_result_name(so
->outputs
[i
].slot
);
518 switch (so
->outputs
[i
].slot
) {
519 case VARYING_SLOT_GS_HEADER_IR3
:
521 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3
:
522 return "GS_VERTEX_FLAGS";
523 case VARYING_SLOT_TCS_HEADER_IR3
:
526 return gl_varying_slot_name(so
->outputs
[i
].slot
);
532 ir3_shader_disasm(struct ir3_shader_variant
*so
, uint32_t *bin
, FILE *out
)
534 struct ir3
*ir
= so
->ir
;
535 struct ir3_register
*reg
;
536 const char *type
= ir3_shader_stage(so
);
540 foreach_input_n (instr
, i
, ir
) {
541 reg
= instr
->regs
[0];
543 fprintf(out
, "@in(%sr%d.%c)\tin%d",
544 (reg
->flags
& IR3_REG_HALF
) ? "h" : "",
545 (regid
>> 2), "xyzw"[regid
& 0x3], i
);
547 if (reg
->wrmask
> 0x1)
548 fprintf(out
, " (wrmask=0x%x)", reg
->wrmask
);
552 /* print pre-dispatch texture fetches: */
553 for (i
= 0; i
< so
->num_sampler_prefetch
; i
++) {
554 const struct ir3_sampler_prefetch
*fetch
= &so
->sampler_prefetch
[i
];
555 fprintf(out
, "@tex(%sr%d.%c)\tsrc=%u, samp=%u, tex=%u, wrmask=0x%x, cmd=%u\n",
556 fetch
->half_precision
? "h" : "",
557 fetch
->dst
>> 2, "xyzw"[fetch
->dst
& 0x3],
558 fetch
->src
, fetch
->samp_id
, fetch
->tex_id
,
559 fetch
->wrmask
, fetch
->cmd
);
562 foreach_output_n (instr
, i
, ir
) {
563 reg
= instr
->regs
[0];
565 fprintf(out
, "@out(%sr%d.%c)\tout%d",
566 (reg
->flags
& IR3_REG_HALF
) ? "h" : "",
567 (regid
>> 2), "xyzw"[regid
& 0x3], i
);
568 if (reg
->wrmask
> 0x1)
569 fprintf(out
, " (wrmask=0x%x)", reg
->wrmask
);
573 const struct ir3_const_state
*const_state
= ir3_const_state(so
);
574 for (i
= 0; i
< DIV_ROUND_UP(const_state
->immediates_count
, 4); i
++) {
575 fprintf(out
, "@const(c%d.x)\t", const_state
->offsets
.immediate
+ i
);
576 fprintf(out
, "0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
577 const_state
->immediates
[i
* 4 + 0],
578 const_state
->immediates
[i
* 4 + 1],
579 const_state
->immediates
[i
* 4 + 2],
580 const_state
->immediates
[i
* 4 + 3]);
583 disasm_a3xx(bin
, so
->info
.sizedwords
, 0, out
, ir
->compiler
->gpu_id
);
585 fprintf(out
, "; %s: outputs:", type
);
586 for (i
= 0; i
< so
->outputs_count
; i
++) {
587 uint8_t regid
= so
->outputs
[i
].regid
;
588 const char *reg_type
= so
->outputs
[i
].half
? "hr" : "r";
589 fprintf(out
, " %s%d.%c (%s)",
590 reg_type
, (regid
>> 2), "xyzw"[regid
& 0x3],
595 fprintf(out
, "; %s: inputs:", type
);
596 for (i
= 0; i
< so
->inputs_count
; i
++) {
597 uint8_t regid
= so
->inputs
[i
].regid
;
598 fprintf(out
, " r%d.%c (%s slot=%d cm=%x,il=%u,b=%u)",
599 (regid
>> 2), "xyzw"[regid
& 0x3],
602 so
->inputs
[i
].compmask
,
608 /* print generic shader info: */
609 fprintf(out
, "; %s prog %d/%d: %u instr, %u nops, %u non-nops, %u mov, %u cov, %u dwords\n",
610 type
, so
->shader
->id
, so
->id
,
611 so
->info
.instrs_count
,
613 so
->info
.instrs_count
- so
->info
.nops_count
,
614 so
->info
.mov_count
, so
->info
.cov_count
,
615 so
->info
.sizedwords
);
617 fprintf(out
, "; %s prog %d/%d: %u last-baryf, %d half, %d full, %u constlen\n",
618 type
, so
->shader
->id
, so
->id
,
620 so
->info
.max_half_reg
+ 1,
621 so
->info
.max_reg
+ 1,
624 fprintf(out
, "; %s prog %d/%d: %u sstall, %u (ss), %u (sy), %d max_sun, %d loops\n",
625 type
, so
->shader
->id
, so
->id
,
632 /* print shader type specific info: */
634 case MESA_SHADER_VERTEX
:
635 dump_output(out
, so
, VARYING_SLOT_POS
, "pos");
636 dump_output(out
, so
, VARYING_SLOT_PSIZ
, "psize");
638 case MESA_SHADER_FRAGMENT
:
639 dump_reg(out
, "pos (ij_pixel)",
640 ir3_find_sysval_regid(so
, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
));
641 dump_reg(out
, "pos (ij_centroid)",
642 ir3_find_sysval_regid(so
, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID
));
643 dump_reg(out
, "pos (ij_size)",
644 ir3_find_sysval_regid(so
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE
));
645 dump_output(out
, so
, FRAG_RESULT_DEPTH
, "posz");
646 if (so
->color0_mrt
) {
647 dump_output(out
, so
, FRAG_RESULT_COLOR
, "color");
649 dump_output(out
, so
, FRAG_RESULT_DATA0
, "data0");
650 dump_output(out
, so
, FRAG_RESULT_DATA1
, "data1");
651 dump_output(out
, so
, FRAG_RESULT_DATA2
, "data2");
652 dump_output(out
, so
, FRAG_RESULT_DATA3
, "data3");
653 dump_output(out
, so
, FRAG_RESULT_DATA4
, "data4");
654 dump_output(out
, so
, FRAG_RESULT_DATA5
, "data5");
655 dump_output(out
, so
, FRAG_RESULT_DATA6
, "data6");
656 dump_output(out
, so
, FRAG_RESULT_DATA7
, "data7");
658 dump_reg(out
, "fragcoord",
659 ir3_find_sysval_regid(so
, SYSTEM_VALUE_FRAG_COORD
));
660 dump_reg(out
, "fragface",
661 ir3_find_sysval_regid(so
, SYSTEM_VALUE_FRONT_FACE
));
672 ir3_shader_outputs(const struct ir3_shader
*so
)
674 return so
->nir
->info
.outputs_written
;