2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
27 #include "util/u_atomic.h"
28 #include "util/u_string.h"
29 #include "util/u_math.h"
30 #include "util/u_memory.h"
31 #include "util/format/u_format.h"
33 #include "drm/freedreno_drmif.h"
35 #include "ir3_shader.h"
36 #include "ir3_compiler.h"
40 ir3_glsl_type_size(const struct glsl_type
*type
, bool bindless
)
42 return glsl_count_attribute_slots(type
, false);
45 /* for vertex shader, the inputs are loaded into registers before the shader
46 * is executed, so max_regs from the shader instructions might not properly
47 * reflect the # of registers actually used, especially in case passthrough
50 * Likewise, for fragment shader, we can have some regs which are passed
51 * input values but never touched by the resulting shader (ie. as result
52 * of dead code elimination or simply because we don't know how to turn
56 fixup_regfootprint(struct ir3_shader_variant
*v
)
60 for (i
= 0; i
< v
->inputs_count
; i
++) {
61 /* skip frag inputs fetch via bary.f since their reg's are
62 * not written by gpu before shader starts (and in fact the
63 * regid's might not even be valid)
65 if (v
->inputs
[i
].bary
)
68 /* ignore high regs that are global to all threads in a warp
69 * (they exist by default) (a5xx+)
71 if (v
->inputs
[i
].regid
>= regid(48,0))
74 if (v
->inputs
[i
].compmask
) {
75 unsigned n
= util_last_bit(v
->inputs
[i
].compmask
) - 1;
76 int32_t regid
= v
->inputs
[i
].regid
+ n
;
77 if (v
->inputs
[i
].half
) {
79 v
->info
.max_half_reg
= MAX2(v
->info
.max_half_reg
, regid
>> 2);
81 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 3);
84 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 2);
89 for (i
= 0; i
< v
->outputs_count
; i
++) {
90 /* for ex, VS shaders with tess don't have normal varying outs: */
91 if (!VALIDREG(v
->outputs
[i
].regid
))
93 int32_t regid
= v
->outputs
[i
].regid
+ 3;
94 if (v
->outputs
[i
].half
) {
96 v
->info
.max_half_reg
= MAX2(v
->info
.max_half_reg
, regid
>> 2);
98 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 3);
101 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 2);
105 for (i
= 0; i
< v
->num_sampler_prefetch
; i
++) {
106 unsigned n
= util_last_bit(v
->sampler_prefetch
[i
].wrmask
) - 1;
107 int32_t regid
= v
->sampler_prefetch
[i
].dst
+ n
;
108 if (v
->sampler_prefetch
[i
].half_precision
) {
109 if (!v
->mergedregs
) {
110 v
->info
.max_half_reg
= MAX2(v
->info
.max_half_reg
, regid
>> 2);
112 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 3);
115 v
->info
.max_reg
= MAX2(v
->info
.max_reg
, regid
>> 2);
120 /* wrapper for ir3_assemble() which does some info fixup based on
121 * shader state. Non-static since used by ir3_cmdline too.
123 void * ir3_shader_assemble(struct ir3_shader_variant
*v
)
125 unsigned gpu_id
= v
->shader
->compiler
->gpu_id
;
128 bin
= ir3_assemble(v
);
133 v
->instrlen
= v
->info
.sizedwords
/ (2 * 16);
135 v
->instrlen
= v
->info
.sizedwords
/ (2 * 4);
138 /* NOTE: if relative addressing is used, we set constlen in
139 * the compiler (to worst-case value) since we don't know in
140 * the assembler what the max addr reg value can be:
142 v
->constlen
= MAX2(v
->constlen
, v
->info
.max_const
+ 1);
144 /* On a4xx and newer, constlen must be a multiple of 16 dwords even though
145 * uploads are in units of 4 dwords. Round it up here to make calculations
146 * regarding the shared constlen simpler.
149 v
->constlen
= align(v
->constlen
, 4);
151 fixup_regfootprint(v
);
157 assemble_variant(struct ir3_shader_variant
*v
)
159 v
->bin
= ir3_shader_assemble(v
);
161 if (shader_debug_enabled(v
->shader
->type
)) {
162 fprintf(stdout
, "Native code for unnamed %s shader %s:\n",
163 ir3_shader_stage(v
), v
->shader
->nir
->info
.name
);
164 if (v
->shader
->type
== MESA_SHADER_FRAGMENT
)
165 fprintf(stdout
, "SIMD0\n");
166 ir3_shader_disasm(v
, v
->bin
, stdout
);
169 /* no need to keep the ir around beyond this point: */
175 * For creating normal shader variants, 'nonbinning' is NULL. For
176 * creating binning pass shader, it is link to corresponding normal
177 * (non-binning) variant.
179 static struct ir3_shader_variant
*
180 create_variant(struct ir3_shader
*shader
, const struct ir3_shader_key
*key
,
181 struct ir3_shader_variant
*nonbinning
)
183 struct ir3_shader_variant
*v
= rzalloc_size(shader
, sizeof(*v
));
189 v
->id
= ++shader
->variant_count
;
191 v
->binning_pass
= !!nonbinning
;
192 v
->nonbinning
= nonbinning
;
194 v
->type
= shader
->type
;
195 v
->mergedregs
= shader
->compiler
->gpu_id
>= 600;
197 if (!v
->binning_pass
)
198 v
->const_state
= rzalloc_size(v
, sizeof(*v
->const_state
));
200 ret
= ir3_compile_shader_nir(shader
->compiler
, v
);
202 debug_error("compile failed!");
208 debug_error("assemble failed!");
219 static inline struct ir3_shader_variant
*
220 shader_variant(struct ir3_shader
*shader
, const struct ir3_shader_key
*key
,
223 struct ir3_shader_variant
*v
;
227 for (v
= shader
->variants
; v
; v
= v
->next
)
228 if (ir3_shader_key_equal(key
, &v
->key
))
231 /* compile new variant if it doesn't exist already: */
232 v
= create_variant(shader
, key
, NULL
);
234 v
->next
= shader
->variants
;
235 shader
->variants
= v
;
242 struct ir3_shader_variant
*
243 ir3_shader_get_variant(struct ir3_shader
*shader
, const struct ir3_shader_key
*key
,
244 bool binning_pass
, bool *created
)
246 mtx_lock(&shader
->variants_lock
);
247 struct ir3_shader_variant
*v
=
248 shader_variant(shader
, key
, created
);
250 if (v
&& binning_pass
) {
252 v
->binning
= create_variant(shader
, key
, v
);
255 mtx_unlock(&shader
->variants_lock
);
258 mtx_unlock(&shader
->variants_lock
);
264 ir3_shader_destroy(struct ir3_shader
*shader
)
266 ralloc_free(shader
->nir
);
267 mtx_destroy(&shader
->variants_lock
);
272 * Creates a bitmask of the used bits of the shader key by this particular
273 * shader. Used by the gallium driver to skip state-dependent recompiles when
277 ir3_setup_used_key(struct ir3_shader
*shader
)
279 nir_shader
*nir
= shader
->nir
;
280 struct shader_info
*info
= &nir
->info
;
281 struct ir3_shader_key
*key
= &shader
->key_mask
;
283 /* This key flag is just used to make for a cheaper ir3_shader_key_equal
284 * check in the common case.
286 key
->has_per_samp
= true;
288 if (info
->stage
== MESA_SHADER_FRAGMENT
) {
289 key
->fsaturate_s
= ~0;
290 key
->fsaturate_t
= ~0;
291 key
->fsaturate_r
= ~0;
292 key
->fastc_srgb
= ~0;
295 if (info
->inputs_read
& VARYING_BITS_COLOR
) {
296 key
->rasterflat
= true;
297 key
->color_two_side
= true;
300 if ((info
->outputs_written
& ~(FRAG_RESULT_DEPTH
|
301 FRAG_RESULT_STENCIL
|
302 FRAG_RESULT_SAMPLE_MASK
)) != 0) {
303 key
->fclamp_color
= true;
306 /* Only used for deciding on behavior of
307 * nir_intrinsic_load_barycentric_sample
309 key
->msaa
= info
->fs
.uses_sample_qualifier
;
311 key
->tessellation
= ~0;
314 if (info
->outputs_written
& VARYING_BITS_COLOR
)
315 key
->vclamp_color
= true;
317 if (info
->stage
== MESA_SHADER_VERTEX
) {
318 key
->vsaturate_s
= ~0;
319 key
->vsaturate_t
= ~0;
320 key
->vsaturate_r
= ~0;
321 key
->vastc_srgb
= ~0;
328 ir3_shader_from_nir(struct ir3_compiler
*compiler
, nir_shader
*nir
,
329 unsigned reserved_user_consts
, struct ir3_stream_output_info
*stream_output
)
331 struct ir3_shader
*shader
= rzalloc_size(NULL
, sizeof(*shader
));
333 mtx_init(&shader
->variants_lock
, mtx_plain
);
334 shader
->compiler
= compiler
;
335 shader
->id
= p_atomic_inc_return(&shader
->compiler
->shader_count
);
336 shader
->type
= nir
->info
.stage
;
338 memcpy(&shader
->stream_output
, stream_output
, sizeof(shader
->stream_output
));
339 shader
->num_reserved_user_consts
= reserved_user_consts
;
341 if (nir
->info
.stage
== MESA_SHADER_GEOMETRY
)
342 NIR_PASS_V(nir
, ir3_nir_lower_gs
);
344 NIR_PASS_V(nir
, nir_lower_io
, nir_var_all
, ir3_glsl_type_size
,
345 (nir_lower_io_options
)0);
347 if (compiler
->gpu_id
>= 600 &&
348 nir
->info
.stage
== MESA_SHADER_FRAGMENT
&&
349 !(ir3_shader_debug
& IR3_DBG_NOFP16
))
350 NIR_PASS_V(nir
, nir_lower_mediump_outputs
);
352 if (nir
->info
.stage
== MESA_SHADER_FRAGMENT
) {
353 /* NOTE: lower load_barycentric_at_sample first, since it
354 * produces load_barycentric_at_offset:
356 NIR_PASS_V(nir
, ir3_nir_lower_load_barycentric_at_sample
);
357 NIR_PASS_V(nir
, ir3_nir_lower_load_barycentric_at_offset
);
359 NIR_PASS_V(nir
, ir3_nir_move_varying_inputs
);
362 NIR_PASS_V(nir
, nir_lower_io_arrays_to_elements_no_indirects
, false);
364 NIR_PASS_V(nir
, nir_lower_amul
, ir3_glsl_type_size
);
366 /* do first pass optimization, ignoring the key: */
367 ir3_optimize_nir(shader
, nir
);
370 if (ir3_shader_debug
& IR3_DBG_DISASM
) {
371 printf("dump nir%d: type=%d", shader
->id
, shader
->type
);
372 nir_print_shader(shader
->nir
, stdout
);
375 ir3_setup_used_key(shader
);
380 static void dump_reg(FILE *out
, const char *name
, uint32_t r
)
382 if (r
!= regid(63,0)) {
383 const char *reg_type
= (r
& HALF_REG_ID
) ? "hr" : "r";
384 fprintf(out
, "; %s: %s%d.%c\n", name
, reg_type
,
385 (r
& ~HALF_REG_ID
) >> 2, "xyzw"[r
& 0x3]);
389 static void dump_output(FILE *out
, struct ir3_shader_variant
*so
,
390 unsigned slot
, const char *name
)
393 regid
= ir3_find_output_regid(so
, slot
);
394 dump_reg(out
, name
, regid
);
398 input_name(struct ir3_shader_variant
*so
, int i
)
400 if (so
->inputs
[i
].sysval
) {
401 return gl_system_value_name(so
->inputs
[i
].slot
);
402 } else if (so
->type
== MESA_SHADER_VERTEX
) {
403 return gl_vert_attrib_name(so
->inputs
[i
].slot
);
405 return gl_varying_slot_name(so
->inputs
[i
].slot
);
410 output_name(struct ir3_shader_variant
*so
, int i
)
412 if (so
->type
== MESA_SHADER_FRAGMENT
) {
413 return gl_frag_result_name(so
->outputs
[i
].slot
);
415 switch (so
->outputs
[i
].slot
) {
416 case VARYING_SLOT_GS_HEADER_IR3
:
418 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3
:
419 return "GS_VERTEX_FLAGS";
420 case VARYING_SLOT_TCS_HEADER_IR3
:
423 return gl_varying_slot_name(so
->outputs
[i
].slot
);
429 ir3_shader_disasm(struct ir3_shader_variant
*so
, uint32_t *bin
, FILE *out
)
431 struct ir3
*ir
= so
->ir
;
432 struct ir3_register
*reg
;
433 const char *type
= ir3_shader_stage(so
);
437 foreach_input_n (instr
, i
, ir
) {
438 reg
= instr
->regs
[0];
440 fprintf(out
, "@in(%sr%d.%c)\tin%d",
441 (reg
->flags
& IR3_REG_HALF
) ? "h" : "",
442 (regid
>> 2), "xyzw"[regid
& 0x3], i
);
444 if (reg
->wrmask
> 0x1)
445 fprintf(out
, " (wrmask=0x%x)", reg
->wrmask
);
449 /* print pre-dispatch texture fetches: */
450 for (i
= 0; i
< so
->num_sampler_prefetch
; i
++) {
451 const struct ir3_sampler_prefetch
*fetch
= &so
->sampler_prefetch
[i
];
452 fprintf(out
, "@tex(%sr%d.%c)\tsrc=%u, samp=%u, tex=%u, wrmask=0x%x, cmd=%u\n",
453 fetch
->half_precision
? "h" : "",
454 fetch
->dst
>> 2, "xyzw"[fetch
->dst
& 0x3],
455 fetch
->src
, fetch
->samp_id
, fetch
->tex_id
,
456 fetch
->wrmask
, fetch
->cmd
);
459 foreach_output_n (instr
, i
, ir
) {
460 reg
= instr
->regs
[0];
462 fprintf(out
, "@out(%sr%d.%c)\tout%d",
463 (reg
->flags
& IR3_REG_HALF
) ? "h" : "",
464 (regid
>> 2), "xyzw"[regid
& 0x3], i
);
465 if (reg
->wrmask
> 0x1)
466 fprintf(out
, " (wrmask=0x%x)", reg
->wrmask
);
470 const struct ir3_const_state
*const_state
= ir3_const_state(so
);
471 for (i
= 0; i
< const_state
->immediates_count
; i
++) {
472 fprintf(out
, "@const(c%d.x)\t", const_state
->offsets
.immediate
+ i
);
473 fprintf(out
, "0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
474 const_state
->immediates
[i
].val
[0],
475 const_state
->immediates
[i
].val
[1],
476 const_state
->immediates
[i
].val
[2],
477 const_state
->immediates
[i
].val
[3]);
480 disasm_a3xx(bin
, so
->info
.sizedwords
, 0, out
, ir
->compiler
->gpu_id
);
482 fprintf(out
, "; %s: outputs:", type
);
483 for (i
= 0; i
< so
->outputs_count
; i
++) {
484 uint8_t regid
= so
->outputs
[i
].regid
;
485 const char *reg_type
= so
->outputs
[i
].half
? "hr" : "r";
486 fprintf(out
, " %s%d.%c (%s)",
487 reg_type
, (regid
>> 2), "xyzw"[regid
& 0x3],
492 fprintf(out
, "; %s: inputs:", type
);
493 for (i
= 0; i
< so
->inputs_count
; i
++) {
494 uint8_t regid
= so
->inputs
[i
].regid
;
495 fprintf(out
, " r%d.%c (%s slot=%d cm=%x,il=%u,b=%u)",
496 (regid
>> 2), "xyzw"[regid
& 0x3],
499 so
->inputs
[i
].compmask
,
505 /* print generic shader info: */
506 fprintf(out
, "; %s prog %d/%d: %u instr, %u nops, %u non-nops, %u mov, %u cov, %u dwords\n",
507 type
, so
->shader
->id
, so
->id
,
508 so
->info
.instrs_count
,
510 so
->info
.instrs_count
- so
->info
.nops_count
,
511 so
->info
.mov_count
, so
->info
.cov_count
,
512 so
->info
.sizedwords
);
514 fprintf(out
, "; %s prog %d/%d: %u last-baryf, %d half, %d full, %u constlen\n",
515 type
, so
->shader
->id
, so
->id
,
517 so
->info
.max_half_reg
+ 1,
518 so
->info
.max_reg
+ 1,
521 fprintf(out
, "; %s prog %d/%d: %u sstall, %u (ss), %u (sy), %d max_sun, %d loops\n",
522 type
, so
->shader
->id
, so
->id
,
529 /* print shader type specific info: */
531 case MESA_SHADER_VERTEX
:
532 dump_output(out
, so
, VARYING_SLOT_POS
, "pos");
533 dump_output(out
, so
, VARYING_SLOT_PSIZ
, "psize");
535 case MESA_SHADER_FRAGMENT
:
536 dump_reg(out
, "pos (ij_pixel)",
537 ir3_find_sysval_regid(so
, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL
));
538 dump_reg(out
, "pos (ij_centroid)",
539 ir3_find_sysval_regid(so
, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID
));
540 dump_reg(out
, "pos (ij_size)",
541 ir3_find_sysval_regid(so
, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE
));
542 dump_output(out
, so
, FRAG_RESULT_DEPTH
, "posz");
543 if (so
->color0_mrt
) {
544 dump_output(out
, so
, FRAG_RESULT_COLOR
, "color");
546 dump_output(out
, so
, FRAG_RESULT_DATA0
, "data0");
547 dump_output(out
, so
, FRAG_RESULT_DATA1
, "data1");
548 dump_output(out
, so
, FRAG_RESULT_DATA2
, "data2");
549 dump_output(out
, so
, FRAG_RESULT_DATA3
, "data3");
550 dump_output(out
, so
, FRAG_RESULT_DATA4
, "data4");
551 dump_output(out
, so
, FRAG_RESULT_DATA5
, "data5");
552 dump_output(out
, so
, FRAG_RESULT_DATA6
, "data6");
553 dump_output(out
, so
, FRAG_RESULT_DATA7
, "data7");
555 dump_reg(out
, "fragcoord",
556 ir3_find_sysval_regid(so
, SYSTEM_VALUE_FRAG_COORD
));
557 dump_reg(out
, "fragface",
558 ir3_find_sysval_regid(so
, SYSTEM_VALUE_FRONT_FACE
));
569 ir3_shader_outputs(const struct ir3_shader
*so
)
571 return so
->nir
->info
.outputs_written
;