src/freedreno/ir3/ir3_shader.c

   1 /*
   2  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #include "util/u_atomic.h"
  28 #include "util/u_string.h"
  29 #include "util/u_math.h"
  30 #include "util/u_memory.h"
  31 #include "util/format/u_format.h"
  32
  33 #include "drm/freedreno_drmif.h"
  34
  35 #include "ir3_shader.h"
  36 #include "ir3_compiler.h"
  37 #include "ir3_nir.h"
  38
  39 #include "disasm.h"
  40
  41 int
  42 ir3_glsl_type_size(const struct glsl_type *type, bool bindless)
  43 {
  44         return glsl_count_attribute_slots(type, false);
  45 }
  46
  47 /* for vertex shader, the inputs are loaded into registers before the shader
  48  * is executed, so max_regs from the shader instructions might not properly
  49  * reflect the # of registers actually used, especially in case passthrough
  50  * varyings.
  51  *
  52  * Likewise, for fragment shader, we can have some regs which are passed
  53  * input values but never touched by the resulting shader (ie. as result
  54  * of dead code elimination or simply because we don't know how to turn
  55  * the reg off.
  56  */
  57 static void
  58 fixup_regfootprint(struct ir3_shader_variant *v)
  59 {
  60         unsigned i;
  61
  62         for (i = 0; i < v->inputs_count; i++) {
  63                 /* skip frag inputs fetch via bary.f since their reg's are
  64                  * not written by gpu before shader starts (and in fact the
  65                  * regid's might not even be valid)
  66                  */
  67                 if (v->inputs[i].bary)
  68                         continue;
  69
  70                 /* ignore high regs that are global to all threads in a warp
  71                  * (they exist by default) (a5xx+)
  72                  */
  73                 if (v->inputs[i].regid >= regid(48,0))
  74                         continue;
  75
  76                 if (v->inputs[i].compmask) {
  77                         unsigned n = util_last_bit(v->inputs[i].compmask) - 1;
  78                         int32_t regid = v->inputs[i].regid + n;
  79                         if (v->inputs[i].half) {
  80                                 if (!v->mergedregs) {
  81                                         v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
  82                                 } else {
  83                                         v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
  84                                 }
  85                         } else {
  86                                 v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
  87                         }
  88                 }
  89         }
  90
  91         for (i = 0; i < v->outputs_count; i++) {
  92                 /* for ex, VS shaders with tess don't have normal varying outs: */
  93                 if (!VALIDREG(v->outputs[i].regid))
  94                         continue;
  95                 int32_t regid = v->outputs[i].regid + 3;
  96                 if (v->outputs[i].half) {
  97                         if (!v->mergedregs) {
  98                                 v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
  99                         } else {
 100                                 v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
 101                         }
 102                 } else {
 103                         v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
 104                 }
 105         }
 106
 107         for (i = 0; i < v->num_sampler_prefetch; i++) {
 108                 unsigned n = util_last_bit(v->sampler_prefetch[i].wrmask) - 1;
 109                 int32_t regid = v->sampler_prefetch[i].dst + n;
 110                 if (v->sampler_prefetch[i].half_precision) {
 111                         if (!v->mergedregs) {
 112                                 v->info.max_half_reg = MAX2(v->info.max_half_reg, regid >> 2);
 113                         } else {
 114                                 v->info.max_reg = MAX2(v->info.max_reg, regid >> 3);
 115                         }
 116                 } else {
 117                         v->info.max_reg = MAX2(v->info.max_reg, regid >> 2);
 118                 }
 119         }
 120 }
 121
 122 /* wrapper for ir3_assemble() which does some info fixup based on
 123  * shader state.  Non-static since used by ir3_cmdline too.
 124  */
 125 void * ir3_shader_assemble(struct ir3_shader_variant *v)
 126 {
 127         const struct ir3_compiler *compiler = v->shader->compiler;
 128         void *bin;
 129
 130         bin = ir3_assemble(v);
 131         if (!bin)
 132                 return NULL;
 133
 134         /* NOTE: if relative addressing is used, we set constlen in
 135          * the compiler (to worst-case value) since we don't know in
 136          * the assembler what the max addr reg value can be:
 137          */
 138         v->constlen = MAX2(v->constlen, v->info.max_const + 1);
 139
 140         /* On a4xx and newer, constlen must be a multiple of 16 dwords even though
 141          * uploads are in units of 4 dwords. Round it up here to make calculations
 142          * regarding the shared constlen simpler.
 143          */
 144         if (compiler->gpu_id >= 400)
 145                 v->constlen = align(v->constlen, 4);
 146
 147         fixup_regfootprint(v);
 148
 149         return bin;
 150 }
 151
 152 static void
 153 assemble_variant(struct ir3_shader_variant *v)
 154 {
 155         v->bin = ir3_shader_assemble(v);
 156
 157         if (shader_debug_enabled(v->shader->type)) {
 158                 fprintf(stdout, "Native code for unnamed %s shader %s:\n",
 159                         ir3_shader_stage(v), v->shader->nir->info.name);
 160                 if (v->shader->type == MESA_SHADER_FRAGMENT)
 161                         fprintf(stdout, "SIMD0\n");
 162                 ir3_shader_disasm(v, v->bin, stdout);
 163         }
 164
 165         /* no need to keep the ir around beyond this point: */
 166         ir3_destroy(v->ir);
 167         v->ir = NULL;
 168 }
 169
 170 static bool
 171 compile_variant(struct ir3_shader_variant *v)
 172 {
 173         int ret = ir3_compile_shader_nir(v->shader->compiler, v);
 174         if (ret) {
 175                 _debug_printf("compile failed! (%s:%s)", v->shader->nir->info.name,
 176                                 v->shader->nir->info.label);
 177                 return false;
 178         }
 179
 180         assemble_variant(v);
 181         if (!v->bin) {
 182                 _debug_printf("assemble failed! (%s:%s)", v->shader->nir->info.name,
 183                                 v->shader->nir->info.label);
 184                 return false;
 185         }
 186
 187         return true;
 188 }
 189
 190 /*
 191  * For creating normal shader variants, 'nonbinning' is NULL.  For
 192  * creating binning pass shader, it is link to corresponding normal
 193  * (non-binning) variant.
 194  */
 195 static struct ir3_shader_variant *
 196 alloc_variant(struct ir3_shader *shader, const struct ir3_shader_key *key,
 197                 struct ir3_shader_variant *nonbinning)
 198 {
 199         void *mem_ctx = shader;
 200         /* hang the binning variant off it's non-binning counterpart instead
 201          * of the shader, to simplify the error cleanup paths
 202          */
 203         if (nonbinning)
 204                 mem_ctx = nonbinning;
 205         struct ir3_shader_variant *v = rzalloc_size(mem_ctx, sizeof(*v));
 206
 207         if (!v)
 208                 return NULL;
 209
 210         v->id = ++shader->variant_count;
 211         v->shader = shader;
 212         v->binning_pass = !!nonbinning;
 213         v->nonbinning = nonbinning;
 214         v->key = *key;
 215         v->type = shader->type;
 216         v->mergedregs = shader->compiler->gpu_id >= 600;
 217
 218         if (!v->binning_pass)
 219                 v->const_state = rzalloc_size(v, sizeof(*v->const_state));
 220
 221         return v;
 222 }
 223
 224 static bool
 225 needs_binning_variant(struct ir3_shader_variant *v)
 226 {
 227         if ((v->type == MESA_SHADER_VERTEX) && ir3_has_binning_vs(&v->key))
 228                 return true;
 229         return false;
 230 }
 231
 232 static struct ir3_shader_variant *
 233 create_variant(struct ir3_shader *shader, const struct ir3_shader_key *key)
 234 {
 235         struct ir3_shader_variant *v = alloc_variant(shader, key, NULL);
 236
 237         if (!v)
 238                 goto fail;
 239
 240         if (needs_binning_variant(v)) {
 241                 v->binning = alloc_variant(shader, key, v);
 242                 if (!v->binning)
 243                         goto fail;
 244         }
 245
 246         if (ir3_disk_cache_retrieve(shader->compiler, v))
 247                 return v;
 248
 249         if (!shader->nir_finalized) {
 250                 ir3_nir_post_finalize(shader->compiler, shader->nir);
 251
 252                 if (ir3_shader_debug & IR3_DBG_DISASM) {
 253                         printf("dump nir%d: type=%d", shader->id, shader->type);
 254                         nir_print_shader(shader->nir, stdout);
 255                 }
 256
 257                 shader->nir_finalized = true;
 258         }
 259
 260         if (!compile_variant(v))
 261                 goto fail;
 262
 263         if (needs_binning_variant(v) && !compile_variant(v->binning))
 264                 goto fail;
 265
 266         ir3_disk_cache_store(shader->compiler, v);
 267
 268         return v;
 269
 270 fail:
 271         ralloc_free(v);
 272         return NULL;
 273 }
 274
 275 static inline struct ir3_shader_variant *
 276 shader_variant(struct ir3_shader *shader, const struct ir3_shader_key *key)
 277 {
 278         struct ir3_shader_variant *v;
 279
 280         for (v = shader->variants; v; v = v->next)
 281                 if (ir3_shader_key_equal(key, &v->key))
 282                         return v;
 283
 284         return NULL;
 285 }
 286
 287 struct ir3_shader_variant *
 288 ir3_shader_get_variant(struct ir3_shader *shader, const struct ir3_shader_key *key,
 289                 bool binning_pass, bool *created)
 290 {
 291         mtx_lock(&shader->variants_lock);
 292         struct ir3_shader_variant *v = shader_variant(shader, key);
 293
 294         if (!v) {
 295                 /* compile new variant if it doesn't exist already: */
 296                 v = create_variant(shader, key);
 297                 if (v) {
 298                         v->next = shader->variants;
 299                         shader->variants = v;
 300                         *created = true;
 301                 }
 302         }
 303
 304         if (v && binning_pass) {
 305                 v = v->binning;
 306                 assert(v);
 307         }
 308
 309         mtx_unlock(&shader->variants_lock);
 310
 311         return v;
 312 }
 313
 314 void
 315 ir3_shader_destroy(struct ir3_shader *shader)
 316 {
 317         ralloc_free(shader->nir);
 318         mtx_destroy(&shader->variants_lock);
 319         ralloc_free(shader);
 320 }
 321
 322 /**
 323  * Creates a bitmask of the used bits of the shader key by this particular
 324  * shader.  Used by the gallium driver to skip state-dependent recompiles when
 325  * possible.
 326  */
 327 static void
 328 ir3_setup_used_key(struct ir3_shader *shader)
 329 {
 330         nir_shader *nir = shader->nir;
 331         struct shader_info *info = &nir->info;
 332         struct ir3_shader_key *key = &shader->key_mask;
 333
 334         /* This key flag is just used to make for a cheaper ir3_shader_key_equal
 335          * check in the common case.
 336          */
 337         key->has_per_samp = true;
 338
 339         key->safe_constlen = true;
 340
 341         key->ucp_enables = 0xff;
 342
 343         if (info->stage == MESA_SHADER_FRAGMENT) {
 344                 key->fsaturate_s = ~0;
 345                 key->fsaturate_t = ~0;
 346                 key->fsaturate_r = ~0;
 347                 key->fastc_srgb = ~0;
 348                 key->fsamples = ~0;
 349
 350                 if (info->inputs_read & VARYING_BITS_COLOR) {
 351                         key->rasterflat = true;
 352                         key->color_two_side = true;
 353                 }
 354
 355                 if (info->inputs_read & VARYING_BIT_LAYER) {
 356                         key->layer_zero = true;
 357                 }
 358
 359                 if ((info->outputs_written & ~(FRAG_RESULT_DEPTH |
 360                                                                 FRAG_RESULT_STENCIL |
 361                                                                 FRAG_RESULT_SAMPLE_MASK)) != 0) {
 362                         key->fclamp_color = true;
 363                 }
 364
 365                 /* Only used for deciding on behavior of
 366                  * nir_intrinsic_load_barycentric_sample
 367                  */
 368                 key->msaa = info->fs.uses_sample_qualifier;
 369         } else {
 370                 key->tessellation = ~0;
 371                 key->has_gs = true;
 372
 373                 if (info->outputs_written & VARYING_BITS_COLOR)
 374                         key->vclamp_color = true;
 375
 376                 if (info->stage == MESA_SHADER_VERTEX) {
 377                         key->vsaturate_s = ~0;
 378                         key->vsaturate_t = ~0;
 379                         key->vsaturate_r = ~0;
 380                         key->vastc_srgb = ~0;
 381                         key->vsamples = ~0;
 382                 }
 383         }
 384 }
 385
 386
 387 /* Given an array of constlen's, decrease some of them so that the sum stays
 388  * within "combined_limit" while trying to fairly share the reduction. Returns
 389  * a bitfield of which stages should be trimmed.
 390  */
 391 static uint32_t
 392 trim_constlens(unsigned *constlens,
 393                            unsigned first_stage, unsigned last_stage,
 394                            unsigned combined_limit, unsigned safe_limit)
 395 {
 396    unsigned cur_total = 0;
 397    for (unsigned i = first_stage; i <= last_stage; i++) {
 398       cur_total += constlens[i];
 399    }
 400
 401    unsigned max_stage = 0;
 402    unsigned max_const = 0;
 403    uint32_t trimmed = 0;
 404
 405    while (cur_total > combined_limit) {
 406            for (unsigned i = first_stage; i <= last_stage; i++) {
 407                    if (constlens[i] >= max_const) {
 408                            max_stage = i;
 409                            max_const = constlens[i];
 410                    }
 411            }
 412
 413            assert(max_const > safe_limit);
 414            trimmed |= 1 << max_stage;
 415            cur_total = cur_total - max_const + safe_limit;
 416            constlens[max_stage] = safe_limit;
 417    }
 418
 419    return trimmed;
 420 }
 421
 422 /* Figures out which stages in the pipeline to use the "safe" constlen for, in
 423  * order to satisfy all shared constlen limits.
 424  */
 425 uint32_t
 426 ir3_trim_constlen(struct ir3_shader_variant **variants,
 427                                   const struct ir3_compiler *compiler)
 428 {
 429         unsigned constlens[MESA_SHADER_STAGES] = {};
 430
 431         for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
 432                 if (variants[i])
 433                         constlens[i] = variants[i]->constlen;
 434         }
 435
 436         uint32_t trimmed = 0;
 437         STATIC_ASSERT(MESA_SHADER_STAGES <= 8 * sizeof(trimmed));
 438
 439         /* There are two shared limits to take into account, the geometry limit on
 440          * a6xx and the total limit. The frag limit on a6xx only matters for a
 441          * single stage, so it's always satisfied with the first variant.
 442          */
 443         if (compiler->gpu_id >= 600) {
 444                 trimmed |=
 445                         trim_constlens(constlens, MESA_SHADER_VERTEX, MESA_SHADER_GEOMETRY,
 446                                                    compiler->max_const_geom, compiler->max_const_safe);
 447         }
 448         trimmed |=
 449                 trim_constlens(constlens, MESA_SHADER_VERTEX, MESA_SHADER_FRAGMENT,
 450                                            compiler->max_const_pipeline, compiler->max_const_safe);
 451
 452         return trimmed;
 453 }
 454
 455 struct ir3_shader *
 456 ir3_shader_from_nir(struct ir3_compiler *compiler, nir_shader *nir,
 457                 unsigned reserved_user_consts, struct ir3_stream_output_info *stream_output)
 458 {
 459         struct ir3_shader *shader = rzalloc_size(NULL, sizeof(*shader));
 460
 461         mtx_init(&shader->variants_lock, mtx_plain);
 462         shader->compiler = compiler;
 463         shader->id = p_atomic_inc_return(&shader->compiler->shader_count);
 464         shader->type = nir->info.stage;
 465         if (stream_output)
 466                 memcpy(&shader->stream_output, stream_output, sizeof(shader->stream_output));
 467         shader->num_reserved_user_consts = reserved_user_consts;
 468         shader->nir = nir;
 469
 470         ir3_disk_cache_init_shader_key(compiler, shader);
 471
 472         ir3_setup_used_key(shader);
 473
 474         return shader;
 475 }
 476
 477 static void dump_reg(FILE *out, const char *name, uint32_t r)
 478 {
 479         if (r != regid(63,0)) {
 480                 const char *reg_type = (r & HALF_REG_ID) ? "hr" : "r";
 481                 fprintf(out, "; %s: %s%d.%c\n", name, reg_type,
 482                                 (r & ~HALF_REG_ID) >> 2, "xyzw"[r & 0x3]);
 483         }
 484 }
 485
 486 static void dump_output(FILE *out, struct ir3_shader_variant *so,
 487                 unsigned slot, const char *name)
 488 {
 489         uint32_t regid;
 490         regid = ir3_find_output_regid(so, slot);
 491         dump_reg(out, name, regid);
 492 }
 493
 494 static const char *
 495 input_name(struct ir3_shader_variant *so, int i)
 496 {
 497         if (so->inputs[i].sysval) {
 498                 return gl_system_value_name(so->inputs[i].slot);
 499         } else if (so->type == MESA_SHADER_VERTEX) {
 500                 return gl_vert_attrib_name(so->inputs[i].slot);
 501         } else {
 502                 return gl_varying_slot_name(so->inputs[i].slot);
 503         }
 504 }
 505
 506 static const char *
 507 output_name(struct ir3_shader_variant *so, int i)
 508 {
 509         if (so->type == MESA_SHADER_FRAGMENT) {
 510                 return gl_frag_result_name(so->outputs[i].slot);
 511         } else {
 512                 switch (so->outputs[i].slot) {
 513                 case VARYING_SLOT_GS_HEADER_IR3:
 514                         return "GS_HEADER";
 515                 case VARYING_SLOT_GS_VERTEX_FLAGS_IR3:
 516                         return "GS_VERTEX_FLAGS";
 517                 case VARYING_SLOT_TCS_HEADER_IR3:
 518                         return "TCS_HEADER";
 519                 default:
 520                         return gl_varying_slot_name(so->outputs[i].slot);
 521                 }
 522         }
 523 }
 524
 525 void
 526 ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin, FILE *out)
 527 {
 528         struct ir3 *ir = so->ir;
 529         struct ir3_register *reg;
 530         const char *type = ir3_shader_stage(so);
 531         uint8_t regid;
 532         unsigned i;
 533
 534         foreach_input_n (instr, i, ir) {
 535                 reg = instr->regs[0];
 536                 regid = reg->num;
 537                 fprintf(out, "@in(%sr%d.%c)\tin%d",
 538                                 (reg->flags & IR3_REG_HALF) ? "h" : "",
 539                                 (regid >> 2), "xyzw"[regid & 0x3], i);
 540
 541                 if (reg->wrmask > 0x1)
 542                         fprintf(out, " (wrmask=0x%x)", reg->wrmask);
 543                 fprintf(out, "\n");
 544         }
 545
 546         /* print pre-dispatch texture fetches: */
 547         for (i = 0; i < so->num_sampler_prefetch; i++) {
 548                 const struct ir3_sampler_prefetch *fetch = &so->sampler_prefetch[i];
 549                 fprintf(out, "@tex(%sr%d.%c)\tsrc=%u, samp=%u, tex=%u, wrmask=0x%x, cmd=%u\n",
 550                                 fetch->half_precision ? "h" : "",
 551                                 fetch->dst >> 2, "xyzw"[fetch->dst & 0x3],
 552                                 fetch->src, fetch->samp_id, fetch->tex_id,
 553                                 fetch->wrmask, fetch->cmd);
 554         }
 555
 556         foreach_output_n (instr, i, ir) {
 557                 reg = instr->regs[0];
 558                 regid = reg->num;
 559                 fprintf(out, "@out(%sr%d.%c)\tout%d",
 560                                 (reg->flags & IR3_REG_HALF) ? "h" : "",
 561                                 (regid >> 2), "xyzw"[regid & 0x3], i);
 562                 if (reg->wrmask > 0x1)
 563                         fprintf(out, " (wrmask=0x%x)", reg->wrmask);
 564                 fprintf(out, "\n");
 565         }
 566
 567         const struct ir3_const_state *const_state = ir3_const_state(so);
 568         for (i = 0; i < DIV_ROUND_UP(const_state->immediates_count, 4); i++) {
 569                 fprintf(out, "@const(c%d.x)\t", const_state->offsets.immediate + i);
 570                 fprintf(out, "0x%08x, 0x%08x, 0x%08x, 0x%08x\n",
 571                                 const_state->immediates[i * 4 + 0],
 572                                 const_state->immediates[i * 4 + 1],
 573                                 const_state->immediates[i * 4 + 2],
 574                                 const_state->immediates[i * 4 + 3]);
 575         }
 576
 577         disasm_a3xx(bin, so->info.sizedwords, 0, out, ir->compiler->gpu_id);
 578
 579         fprintf(out, "; %s: outputs:", type);
 580         for (i = 0; i < so->outputs_count; i++) {
 581                 uint8_t regid = so->outputs[i].regid;
 582                 const char *reg_type = so->outputs[i].half ? "hr" : "r";
 583                 fprintf(out, " %s%d.%c (%s)",
 584                                 reg_type, (regid >> 2), "xyzw"[regid & 0x3],
 585                                 output_name(so, i));
 586         }
 587         fprintf(out, "\n");
 588
 589         fprintf(out, "; %s: inputs:", type);
 590         for (i = 0; i < so->inputs_count; i++) {
 591                 uint8_t regid = so->inputs[i].regid;
 592                 fprintf(out, " r%d.%c (%s slot=%d cm=%x,il=%u,b=%u)",
 593                                 (regid >> 2), "xyzw"[regid & 0x3],
 594                                 input_name(so, i),
 595                                 so->inputs[i].slot,
 596                                 so->inputs[i].compmask,
 597                                 so->inputs[i].inloc,
 598                                 so->inputs[i].bary);
 599         }
 600         fprintf(out, "\n");
 601
 602         /* print generic shader info: */
 603         fprintf(out, "; %s prog %d/%d: %u instr, %u nops, %u non-nops, %u mov, %u cov, %u dwords\n",
 604                         type, so->shader->id, so->id,
 605                         so->info.instrs_count,
 606                         so->info.nops_count,
 607                         so->info.instrs_count - so->info.nops_count,
 608                         so->info.mov_count, so->info.cov_count,
 609                         so->info.sizedwords);
 610
 611         fprintf(out, "; %s prog %d/%d: %u last-baryf, %d half, %d full, %u constlen\n",
 612                         type, so->shader->id, so->id,
 613                         so->info.last_baryf,
 614                         so->info.max_half_reg + 1,
 615                         so->info.max_reg + 1,
 616                         so->constlen);
 617
 618         fprintf(out, "; %s prog %d/%d: %u sstall, %u (ss), %u (sy), %d max_sun, %d loops\n",
 619                         type, so->shader->id, so->id,
 620                         so->info.sstall,
 621                         so->info.ss,
 622                         so->info.sy,
 623                         so->max_sun,
 624                         so->loops);
 625
 626         /* print shader type specific info: */
 627         switch (so->type) {
 628         case MESA_SHADER_VERTEX:
 629                 dump_output(out, so, VARYING_SLOT_POS, "pos");
 630                 dump_output(out, so, VARYING_SLOT_PSIZ, "psize");
 631                 break;
 632         case MESA_SHADER_FRAGMENT:
 633                 dump_reg(out, "pos (ij_pixel)",
 634                         ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PERSP_PIXEL));
 635                 dump_reg(out, "pos (ij_centroid)",
 636                         ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PERSP_CENTROID));
 637                 dump_reg(out, "pos (ij_size)",
 638                         ir3_find_sysval_regid(so, SYSTEM_VALUE_BARYCENTRIC_PERSP_SIZE));
 639                 dump_output(out, so, FRAG_RESULT_DEPTH, "posz");
 640                 if (so->color0_mrt) {
 641                         dump_output(out, so, FRAG_RESULT_COLOR, "color");
 642                 } else {
 643                         dump_output(out, so, FRAG_RESULT_DATA0, "data0");
 644                         dump_output(out, so, FRAG_RESULT_DATA1, "data1");
 645                         dump_output(out, so, FRAG_RESULT_DATA2, "data2");
 646                         dump_output(out, so, FRAG_RESULT_DATA3, "data3");
 647                         dump_output(out, so, FRAG_RESULT_DATA4, "data4");
 648                         dump_output(out, so, FRAG_RESULT_DATA5, "data5");
 649                         dump_output(out, so, FRAG_RESULT_DATA6, "data6");
 650                         dump_output(out, so, FRAG_RESULT_DATA7, "data7");
 651                 }
 652                 dump_reg(out, "fragcoord",
 653                         ir3_find_sysval_regid(so, SYSTEM_VALUE_FRAG_COORD));
 654                 dump_reg(out, "fragface",
 655                         ir3_find_sysval_regid(so, SYSTEM_VALUE_FRONT_FACE));
 656                 break;
 657         default:
 658                 /* TODO */
 659                 break;
 660         }
 661
 662         fprintf(out, "\n");
 663 }
 664
 665 uint64_t
 666 ir3_shader_outputs(const struct ir3_shader *so)
 667 {
 668         return so->nir->info.outputs_written;
 669 }