2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
32 #include "c11/threads.h"
33 #include "compiler/shader_enums.h"
34 #include "compiler/nir/nir.h"
35 #include "util/bitscan.h"
41 /* driver param indices: */
42 enum ir3_driver_param
{
43 /* compute shader driver params: */
44 IR3_DP_NUM_WORK_GROUPS_X
= 0,
45 IR3_DP_NUM_WORK_GROUPS_Y
= 1,
46 IR3_DP_NUM_WORK_GROUPS_Z
= 2,
47 IR3_DP_LOCAL_GROUP_SIZE_X
= 4,
48 IR3_DP_LOCAL_GROUP_SIZE_Y
= 5,
49 IR3_DP_LOCAL_GROUP_SIZE_Z
= 6,
50 /* NOTE: gl_NumWorkGroups should be vec4 aligned because
51 * glDispatchComputeIndirect() needs to load these from
52 * the info->indirect buffer. Keep that in mind when/if
53 * adding any addition CS driver params.
55 IR3_DP_CS_COUNT
= 8, /* must be aligned to vec4 */
57 /* vertex shader driver params: */
58 IR3_DP_VTXID_BASE
= 0,
59 IR3_DP_VTXCNT_MAX
= 1,
60 IR3_DP_INSTID_BASE
= 2,
61 /* user-clip-plane components, up to 8x vec4's: */
65 IR3_DP_VS_COUNT
= 36 /* must be aligned to vec4 */
68 #define IR3_MAX_SHADER_BUFFERS 32
69 #define IR3_MAX_SHADER_IMAGES 32
70 #define IR3_MAX_SO_BUFFERS 4
71 #define IR3_MAX_SO_STREAMS 4
72 #define IR3_MAX_SO_OUTPUTS 64
73 #define IR3_MAX_UBO_PUSH_RANGES 32
76 struct ir3_ubo_range
{
77 uint32_t offset
; /* start offset to push in the const register file */
78 uint32_t block
; /* Which constant block */
79 uint32_t start
, end
; /* range of block that's actually used */
80 uint16_t bindless_base
; /* For bindless, which base register is used */
84 struct ir3_ubo_analysis_state
{
85 struct ir3_ubo_range range
[IR3_MAX_UBO_PUSH_RANGES
];
89 uint32_t cmdstream_size
; /* for per-gen backend to stash required cmdstream size */
93 * Describes the layout of shader consts. This includes:
94 * + User consts + driver lowered UBO ranges
96 * + Image sizes/dimensions
97 * + Driver params (ie. IR3_DP_*)
98 * + TFBO addresses (for generations that do not have hardware streamout)
99 * + Lowered immediates
101 * For consts needed to pass internal values to shader which may or may not
102 * be required, rather than allocating worst-case const space, we scan the
103 * shader and allocate consts as-needed:
105 * + SSBO sizes: only needed if shader has a get_buffer_size intrinsic
108 * + Image dimensions: needed to calculate pixel offset, but only for
109 * images that have a image_store intrinsic
111 * Layout of constant registers, each section aligned to vec4. Note
112 * that pointer size (ubo, etc) changes depending on generation.
117 * if (vertex shader) {
118 * driver params (IR3_DP_*)
119 * if (stream_output.num_outputs > 0)
120 * stream-out addresses
121 * } else if (compute_shader) {
122 * driver params (IR3_DP_*)
126 * Immediates go last mostly because they are inserted in the CP pass
127 * after the nir -> ir3 frontend.
129 * Note UBO size in bytes should be aligned to vec4
131 struct ir3_const_state
{
133 unsigned num_driver_params
; /* scalar */
136 /* user const start at zero */
138 /* NOTE that a3xx might need a section for SSBO addresses too */
141 unsigned driver_param
;
143 unsigned primitive_param
;
144 unsigned primitive_map
;
149 uint32_t mask
; /* bitmask of SSBOs that have get_buffer_size */
150 uint32_t count
; /* number of consts allocated */
151 /* one const allocated per SSBO which has get_buffer_size,
152 * ssbo_sizes.off[ssbo_id] is offset from start of ssbo_sizes
155 uint32_t off
[IR3_MAX_SHADER_BUFFERS
];
159 uint32_t mask
; /* bitmask of images that have image_store */
160 uint32_t count
; /* number of consts allocated */
161 /* three const allocated per image which has image_store:
162 * + cpp (bytes per pixel)
164 * + array_pitch (z pitch)
166 uint32_t off
[IR3_MAX_SHADER_IMAGES
];
169 unsigned immediate_idx
;
170 unsigned immediates_count
;
171 unsigned immediates_size
;
176 /* State of ubo access lowered to push consts: */
177 struct ir3_ubo_analysis_state ubo_state
;
181 * A single output for vertex transform feedback.
183 struct ir3_stream_output
{
184 unsigned register_index
:6; /**< 0 to 63 (OUT index) */
185 unsigned start_component
:2; /** 0 to 3 */
186 unsigned num_components
:3; /** 1 to 4 */
187 unsigned output_buffer
:3; /**< 0 to PIPE_MAX_SO_BUFFERS */
188 unsigned dst_offset
:16; /**< offset into the buffer in dwords */
189 unsigned stream
:2; /**< 0 to 3 */
193 * Stream output for vertex transform feedback.
195 struct ir3_stream_output_info
{
196 unsigned num_outputs
;
197 /** stride for an entire vertex for each buffer in dwords */
198 uint16_t stride
[IR3_MAX_SO_BUFFERS
];
201 * Array of stream outputs, in the order they are to be written in.
202 * Selected components are tightly packed into the output buffer.
204 struct ir3_stream_output output
[IR3_MAX_SO_OUTPUTS
];
209 * Starting from a4xx, HW supports pre-dispatching texture sampling
210 * instructions prior to scheduling a shader stage, when the
211 * coordinate maps exactly to an output of the previous stage.
215 * There is a limit in the number of pre-dispatches allowed for any
218 #define IR3_MAX_SAMPLER_PREFETCH 4
221 * This is the output stream value for 'cmd', as used by blob. It may
222 * encode the return type (in 3 bits) but it hasn't been verified yet.
224 #define IR3_SAMPLER_PREFETCH_CMD 0x4
225 #define IR3_SAMPLER_BINDLESS_PREFETCH_CMD 0x6
228 * Stream output for texture sampling pre-dispatches.
230 struct ir3_sampler_prefetch
{
234 uint16_t samp_bindless_id
;
235 uint16_t tex_bindless_id
;
238 uint8_t half_precision
;
243 /* Configuration key used to identify a shader variant.. different
244 * shader variants can be used to implement features not supported
245 * in hw (two sided color), binning-pass vertex shader, etc.
247 * When adding to this struct, please update ir3_shader_variant()'s debug
250 struct ir3_shader_key
{
254 * Combined Vertex/Fragment shader parameters:
256 unsigned ucp_enables
: 8;
258 /* do we need to check {v,f}saturate_{s,t,r}? */
259 unsigned has_per_samp
: 1;
262 * Vertex shader variant parameters:
264 unsigned vclamp_color
: 1;
267 * Fragment shader variant parameters:
269 unsigned sample_shading
: 1;
271 unsigned color_two_side
: 1;
272 /* used when shader needs to handle flat varyings (a4xx)
273 * for front/back color inputs to frag shader:
275 unsigned rasterflat
: 1;
276 unsigned fclamp_color
: 1;
278 /* Indicates that this is a tessellation pipeline which requires a
279 * whole different kind of vertex shader. In case of
280 * tessellation, this field also tells us which kind of output
281 * topology the TES uses, which the TCS needs to know.
283 #define IR3_TESS_NONE 0
284 #define IR3_TESS_TRIANGLES 1
285 #define IR3_TESS_QUADS 2
286 #define IR3_TESS_ISOLINES 3
287 unsigned tessellation
: 2;
294 /* bitmask of sampler which needs coords clamped for vertex
297 uint16_t vsaturate_s
, vsaturate_t
, vsaturate_r
;
299 /* bitmask of sampler which needs coords clamped for frag
302 uint16_t fsaturate_s
, fsaturate_t
, fsaturate_r
;
304 /* bitmask of ms shifts */
305 uint32_t vsamples
, fsamples
;
307 /* bitmask of samplers which need astc srgb workaround: */
308 uint16_t vastc_srgb
, fastc_srgb
;
311 static inline unsigned
312 ir3_tess_mode(unsigned gl_tess_mode
)
314 switch (gl_tess_mode
) {
316 return IR3_TESS_ISOLINES
;
318 return IR3_TESS_TRIANGLES
;
320 return IR3_TESS_QUADS
;
322 unreachable("bad tessmode");
327 ir3_shader_key_equal(const struct ir3_shader_key
*a
, const struct ir3_shader_key
*b
)
329 /* slow-path if we need to check {v,f}saturate_{s,t,r} */
330 if (a
->has_per_samp
|| b
->has_per_samp
)
331 return memcmp(a
, b
, sizeof(struct ir3_shader_key
)) == 0;
332 return a
->global
== b
->global
;
335 /* will the two keys produce different lowering for a fragment shader? */
337 ir3_shader_key_changes_fs(struct ir3_shader_key
*key
, struct ir3_shader_key
*last_key
)
339 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
340 if ((last_key
->fsaturate_s
!= key
->fsaturate_s
) ||
341 (last_key
->fsaturate_t
!= key
->fsaturate_t
) ||
342 (last_key
->fsaturate_r
!= key
->fsaturate_r
) ||
343 (last_key
->fsamples
!= key
->fsamples
) ||
344 (last_key
->fastc_srgb
!= key
->fastc_srgb
))
348 if (last_key
->fclamp_color
!= key
->fclamp_color
)
351 if (last_key
->color_two_side
!= key
->color_two_side
)
354 if (last_key
->rasterflat
!= key
->rasterflat
)
357 if (last_key
->ucp_enables
!= key
->ucp_enables
)
363 /* will the two keys produce different lowering for a vertex shader? */
365 ir3_shader_key_changes_vs(struct ir3_shader_key
*key
, struct ir3_shader_key
*last_key
)
367 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
368 if ((last_key
->vsaturate_s
!= key
->vsaturate_s
) ||
369 (last_key
->vsaturate_t
!= key
->vsaturate_t
) ||
370 (last_key
->vsaturate_r
!= key
->vsaturate_r
) ||
371 (last_key
->vsamples
!= key
->vsamples
) ||
372 (last_key
->vastc_srgb
!= key
->vastc_srgb
))
376 if (last_key
->vclamp_color
!= key
->vclamp_color
)
379 if (last_key
->ucp_enables
!= key
->ucp_enables
)
386 * On a4xx+a5xx, Images share state with textures and SSBOs:
388 * + Uses texture (cat5) state/instruction (isam) to read
389 * + Uses SSBO state and instructions (cat6) to write and for atomics
391 * Starting with a6xx, Images and SSBOs are basically the same thing,
392 * with texture state and isam also used for SSBO reads.
394 * On top of that, gallium makes the SSBO (shader_buffers) state semi
395 * sparse, with the first half of the state space used for atomic
396 * counters lowered to atomic buffers. We could ignore this, but I
397 * don't think we could *really* handle the case of a single shader
398 * that used the max # of textures + images + SSBOs. And once we are
399 * offsetting images by num_ssbos (or visa versa) to map them into
400 * the same hardware state, the hardware state has become coupled to
401 * the shader state, so at this point we might as well just use a
402 * mapping table to remap things from image/SSBO idx to hw idx.
404 * To make things less (more?) confusing, for the hw "SSBO" state
405 * (since it is really both SSBO and Image) I'll use the name "IBO"
407 struct ir3_ibo_mapping
{
408 #define IBO_INVALID 0xff
409 /* Maps logical SSBO state to hw tex state: */
410 uint8_t ssbo_to_tex
[IR3_MAX_SHADER_BUFFERS
];
412 /* Maps logical Image state to hw tex state: */
413 uint8_t image_to_tex
[IR3_MAX_SHADER_IMAGES
];
415 /* Maps hw state back to logical SSBO or Image state:
417 * note IBO_SSBO ORd into values to indicate that the
418 * hw slot is used for SSBO state vs Image state.
420 #define IBO_SSBO 0x80
421 uint8_t tex_to_image
[32];
423 uint8_t num_tex
; /* including real textures */
424 uint8_t tex_base
; /* the number of real textures, ie. image/ssbo start here */
427 /* Represents half register in regid */
428 #define HALF_REG_ID 0x100
430 struct ir3_shader_variant
{
433 /* variant id (for debug) */
436 struct ir3_shader_key key
;
438 /* vertex shaders can have an extra version for hwbinning pass,
439 * which is pointed to by so->binning:
443 struct ir3_shader_variant
*binning
;
444 struct ir3_shader_variant
*nonbinning
;
447 struct ir3_info info
;
450 /* The actual binary shader instructions, size given by info.sizedwords: */
453 /* Levels of nesting of flow control:
455 unsigned branchstack
;
460 /* the instructions length is in units of instruction groups
461 * (4 instructions for a3xx, 16 instructions for a4xx.. each
462 * instruction is 2 dwords):
466 /* the constants length is in units of vec4's, and is the sum of
467 * the uniforms and the built-in compiler constants
471 struct ir3_const_state
*const_state
;
474 * + Let the frag shader determine the position/compmask for the
475 * varyings, since it is the place where we know if the varying
476 * is actually used, and if so, which components are used. So
477 * what the hw calls "outloc" is taken from the "inloc" of the
479 * + From the vert shader, we only need the output regid
482 bool frag_face
, color0_mrt
;
483 uint8_t fragcoord_compmask
;
485 /* NOTE: for input/outputs, slot is:
486 * gl_vert_attrib - for VS inputs
487 * gl_varying_slot - for VS output / FS input
488 * gl_frag_result - for FS output
491 /* varyings/outputs: */
492 unsigned outputs_count
;
497 } outputs
[32 + 2]; /* +POSITION +PSIZE */
498 bool writes_pos
, writes_smask
, writes_psize
;
500 /* Size in dwords of all outputs for VS, size of entire patch for HS. */
501 uint32_t output_size
;
503 /* Map from driver_location to byte offset in per-primitive storage */
504 unsigned output_loc
[32];
506 /* attributes (VS) / varyings (FS):
507 * Note that sysval's should come *after* normal inputs.
509 unsigned inputs_count
;
514 /* location of input (ie. offset passed to bary.f, etc). This
515 * matches the SP_VS_VPC_DST_REG.OUTLOCn value (a3xx and a4xx
516 * have the OUTLOCn value offset by 8, presumably to account
517 * for gl_Position/gl_PointSize)
520 /* vertex shader specific: */
521 bool sysval
: 1; /* slot is a gl_system_value */
522 /* fragment shader specific: */
523 bool bary
: 1; /* fetched varying (vs one loaded into reg) */
524 bool rasterflat
: 1; /* special handling for emit->rasterflat */
525 bool use_ldlv
: 1; /* internal to ir3_compiler_nir */
527 enum glsl_interp_mode interpolate
;
528 } inputs
[32 + 2]; /* +POSITION +FACE */
530 /* sum of input components (scalar). For frag shaders, it only counts
531 * the varying inputs:
535 /* For frag shaders, the total number of inputs (not scalar,
536 * ie. SP_VS_PARAM_REG.TOTALVSOUTVAR)
540 /* Remapping table to map Image and SSBO to hw state: */
541 struct ir3_ibo_mapping image_mapping
;
543 /* number of samplers/textures (which are currently 1:1): */
546 /* is there an implicit sampler to read framebuffer (FS only).. if
547 * so the sampler-idx is 'num_samp - 1' (ie. it is appended after
548 * the last "real" texture)
552 /* do we have one or more SSBO instructions: */
555 /* Which bindless resources are used, for filling out sp_xs_config */
561 /* do we need derivatives: */
564 bool need_fine_derivatives
;
566 /* do we have image write, etc (which prevents early-z): */
569 /* do we have kill, which also prevents early-z, but not necessarily
570 * early-lrz (as long as lrz-write is disabled, which must be handled
571 * outside of ir3. Unlike other no_earlyz cases, kill doesn't have
572 * side effects that prevent early-lrz discard.
578 /* Are we using split or merged register file? */
581 /* for astc srgb workaround, the number/base of additional
582 * alpha tex states we need, and index of original tex states
585 unsigned base
, count
;
586 unsigned orig_idx
[16];
589 /* shader variants form a linked list: */
590 struct ir3_shader_variant
*next
;
592 /* replicated here to avoid passing extra ptrs everywhere: */
593 gl_shader_stage type
;
594 struct ir3_shader
*shader
;
596 /* texture sampler pre-dispatches */
597 uint32_t num_sampler_prefetch
;
598 struct ir3_sampler_prefetch sampler_prefetch
[IR3_MAX_SAMPLER_PREFETCH
];
601 static inline const char *
602 ir3_shader_stage(struct ir3_shader_variant
*v
)
605 case MESA_SHADER_VERTEX
: return v
->binning_pass
? "BVERT" : "VERT";
606 case MESA_SHADER_TESS_CTRL
: return "TCS";
607 case MESA_SHADER_TESS_EVAL
: return "TES";
608 case MESA_SHADER_GEOMETRY
: return "GEOM";
609 case MESA_SHADER_FRAGMENT
: return "FRAG";
610 case MESA_SHADER_COMPUTE
: return "CL";
612 unreachable("invalid type");
619 gl_shader_stage type
;
621 /* shader id (for debug): */
623 uint32_t variant_count
;
625 /* Set by freedreno after shader_state_create, so we can emit debug info
626 * when recompiling a shader at draw time.
628 bool initial_variants_done
;
630 struct ir3_compiler
*compiler
;
632 unsigned num_reserved_user_consts
;
634 struct nir_shader
*nir
;
635 struct ir3_stream_output_info stream_output
;
637 struct ir3_shader_variant
*variants
;
640 /* Bitmask of bits of the shader key used by this shader. Used to avoid
641 * recompiles for GL NOS that doesn't actually apply to the shader.
643 struct ir3_shader_key key_mask
;
647 * In order to use the same cmdstream, in particular constlen setup and const
648 * emit, for both binning and draw pass (a6xx+), the binning pass re-uses it's
649 * corresponding draw pass shaders const_state.
651 static inline struct ir3_const_state
*
652 ir3_const_state(const struct ir3_shader_variant
*v
)
655 return v
->nonbinning
->const_state
;
656 return v
->const_state
;
659 void * ir3_shader_assemble(struct ir3_shader_variant
*v
);
660 struct ir3_shader_variant
* ir3_shader_get_variant(struct ir3_shader
*shader
,
661 const struct ir3_shader_key
*key
, bool binning_pass
, bool *created
);
662 struct ir3_shader
* ir3_shader_from_nir(struct ir3_compiler
*compiler
, nir_shader
*nir
,
663 unsigned reserved_user_consts
, struct ir3_stream_output_info
*stream_output
);
664 void ir3_shader_destroy(struct ir3_shader
*shader
);
665 void ir3_shader_disasm(struct ir3_shader_variant
*so
, uint32_t *bin
, FILE *out
);
666 uint64_t ir3_shader_outputs(const struct ir3_shader
*so
);
669 ir3_glsl_type_size(const struct glsl_type
*type
, bool bindless
);
675 /* clears shader-key flags which don't apply to the given shader.
678 ir3_key_clear_unused(struct ir3_shader_key
*key
, struct ir3_shader
*shader
)
680 uint32_t *key_bits
= (uint32_t *)key
;
681 uint32_t *key_mask
= (uint32_t *)&shader
->key_mask
;
682 STATIC_ASSERT(sizeof(*key
) % 4 == 0);
683 for (int i
= 0; i
< sizeof(*key
) >> 2; i
++)
684 key_bits
[i
] &= key_mask
[i
];
688 ir3_find_output(const struct ir3_shader_variant
*so
, gl_varying_slot slot
)
692 for (j
= 0; j
< so
->outputs_count
; j
++)
693 if (so
->outputs
[j
].slot
== slot
)
696 /* it seems optional to have a OUT.BCOLOR[n] for each OUT.COLOR[n]
697 * in the vertex shader.. but the fragment shader doesn't know this
698 * so it will always have both IN.COLOR[n] and IN.BCOLOR[n]. So
699 * at link time if there is no matching OUT.BCOLOR[n], we must map
700 * OUT.COLOR[n] to IN.BCOLOR[n]. And visa versa if there is only
701 * a OUT.BCOLOR[n] but no matching OUT.COLOR[n]
703 if (slot
== VARYING_SLOT_BFC0
) {
704 slot
= VARYING_SLOT_COL0
;
705 } else if (slot
== VARYING_SLOT_BFC1
) {
706 slot
= VARYING_SLOT_COL1
;
707 } else if (slot
== VARYING_SLOT_COL0
) {
708 slot
= VARYING_SLOT_BFC0
;
709 } else if (slot
== VARYING_SLOT_COL1
) {
710 slot
= VARYING_SLOT_BFC1
;
715 for (j
= 0; j
< so
->outputs_count
; j
++)
716 if (so
->outputs
[j
].slot
== slot
)
725 ir3_next_varying(const struct ir3_shader_variant
*so
, int i
)
727 while (++i
< so
->inputs_count
)
728 if (so
->inputs
[i
].compmask
&& so
->inputs
[i
].bary
)
733 struct ir3_shader_linkage
{
734 /* Maximum location either consumed by the fragment shader or produced by
735 * the last geometry stage, i.e. the size required for each vertex in the
740 /* Number of entries in var. */
743 /* Bitset of locations used, including ones which are only used by the FS.
747 /* Map from VS output to location. */
754 /* location for fixed-function gl_PrimitiveID passthrough */
759 ir3_link_add(struct ir3_shader_linkage
*l
, uint8_t regid_
, uint8_t compmask
, uint8_t loc
)
763 for (int j
= 0; j
< util_last_bit(compmask
); j
++) {
764 uint8_t comploc
= loc
+ j
;
765 l
->varmask
[comploc
/ 32] |= 1 << (comploc
% 32);
768 l
->max_loc
= MAX2(l
->max_loc
, loc
+ util_last_bit(compmask
));
770 if (regid_
!= regid(63, 0)) {
772 debug_assert(i
< ARRAY_SIZE(l
->var
));
774 l
->var
[i
].regid
= regid_
;
775 l
->var
[i
].compmask
= compmask
;
781 ir3_link_shaders(struct ir3_shader_linkage
*l
,
782 const struct ir3_shader_variant
*vs
,
783 const struct ir3_shader_variant
*fs
,
786 /* On older platforms, varmask isn't programmed at all, and it appears
787 * that the hardware generates a mask of used VPC locations using the VS
788 * output map, and hangs if a FS bary instruction references a location
789 * not in the list. This means that we need to have a dummy entry in the
790 * VS out map for things like gl_PointCoord which aren't written by the
791 * VS. Furthermore we can't use r63.x, so just pick a random register to
792 * use if there is no VS output.
794 const unsigned default_regid
= pack_vs_out
? regid(63, 0) : regid(0, 0);
797 l
->primid_loc
= 0xff;
799 while (l
->cnt
< ARRAY_SIZE(l
->var
)) {
800 j
= ir3_next_varying(fs
, j
);
802 if (j
>= fs
->inputs_count
)
805 if (fs
->inputs
[j
].inloc
>= fs
->total_in
)
808 k
= ir3_find_output(vs
, fs
->inputs
[j
].slot
);
810 if (k
< 0 && fs
->inputs
[j
].slot
== VARYING_SLOT_PRIMITIVE_ID
) {
811 l
->primid_loc
= fs
->inputs
[j
].inloc
;
814 ir3_link_add(l
, k
>= 0 ? vs
->outputs
[k
].regid
: default_regid
,
815 fs
->inputs
[j
].compmask
, fs
->inputs
[j
].inloc
);
819 static inline uint32_t
820 ir3_find_output_regid(const struct ir3_shader_variant
*so
, unsigned slot
)
823 for (j
= 0; j
< so
->outputs_count
; j
++)
824 if (so
->outputs
[j
].slot
== slot
) {
825 uint32_t regid
= so
->outputs
[j
].regid
;
826 if (so
->outputs
[j
].half
)
827 regid
|= HALF_REG_ID
;
833 #define VARYING_SLOT_GS_HEADER_IR3 (VARYING_SLOT_MAX + 0)
834 #define VARYING_SLOT_GS_VERTEX_FLAGS_IR3 (VARYING_SLOT_MAX + 1)
835 #define VARYING_SLOT_TCS_HEADER_IR3 (VARYING_SLOT_MAX + 2)
838 static inline uint32_t
839 ir3_find_sysval_regid(const struct ir3_shader_variant
*so
, unsigned slot
)
842 for (j
= 0; j
< so
->inputs_count
; j
++)
843 if (so
->inputs
[j
].sysval
&& (so
->inputs
[j
].slot
== slot
))
844 return so
->inputs
[j
].regid
;
848 /* calculate register footprint in terms of half-regs (ie. one full
849 * reg counts as two half-regs).
851 static inline uint32_t
852 ir3_shader_halfregs(const struct ir3_shader_variant
*v
)
854 return (2 * (v
->info
.max_reg
+ 1)) + (v
->info
.max_half_reg
+ 1);
857 static inline uint32_t
858 ir3_shader_nibo(const struct ir3_shader_variant
*v
)
860 /* The dummy variant used in binning mode won't have an actual shader. */
864 return v
->shader
->nir
->info
.num_ssbos
+ v
->shader
->nir
->info
.num_images
;
867 #endif /* IR3_SHADER_H_ */