src/freedreno/ir3/ir3_shader.h

   1 /*
   2  * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
  20  * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
  21  * SOFTWARE.
  22  *
  23  * Authors:
  24  *    Rob Clark <robclark@freedesktop.org>
  25  */
  26
  27 #ifndef IR3_SHADER_H_
  28 #define IR3_SHADER_H_
  29
  30 #include <stdio.h>
  31
  32 #include "compiler/shader_enums.h"
  33 #include "compiler/nir/nir.h"
  34 #include "util/bitscan.h"
  35
  36 #include "ir3.h"
  37
  38 struct glsl_type;
  39
  40 /* driver param indices: */
  41 enum ir3_driver_param {
  42         /* compute shader driver params: */
  43         IR3_DP_NUM_WORK_GROUPS_X = 0,
  44         IR3_DP_NUM_WORK_GROUPS_Y = 1,
  45         IR3_DP_NUM_WORK_GROUPS_Z = 2,
  46         IR3_DP_LOCAL_GROUP_SIZE_X = 4,
  47         IR3_DP_LOCAL_GROUP_SIZE_Y = 5,
  48         IR3_DP_LOCAL_GROUP_SIZE_Z = 6,
  49         /* NOTE: gl_NumWorkGroups should be vec4 aligned because
  50          * glDispatchComputeIndirect() needs to load these from
  51          * the info->indirect buffer.  Keep that in mind when/if
  52          * adding any addition CS driver params.
  53          */
  54         IR3_DP_CS_COUNT   = 8,   /* must be aligned to vec4 */
  55
  56         /* vertex shader driver params: */
  57         IR3_DP_VTXID_BASE = 0,
  58         IR3_DP_VTXCNT_MAX = 1,
  59         /* user-clip-plane components, up to 8x vec4's: */
  60         IR3_DP_UCP0_X     = 4,
  61         /* .... */
  62         IR3_DP_UCP7_W     = 35,
  63         IR3_DP_VS_COUNT   = 36   /* must be aligned to vec4 */
  64 };
  65
  66 #define IR3_MAX_SHADER_BUFFERS   32
  67 #define IR3_MAX_SHADER_IMAGES    32
  68 #define IR3_MAX_SO_BUFFERS        4
  69 #define IR3_MAX_SO_OUTPUTS       64
  70
  71 /**
  72  * For consts needed to pass internal values to shader which may or may not
  73  * be required, rather than allocating worst-case const space, we scan the
  74  * shader and allocate consts as-needed:
  75  *
  76  *   + SSBO sizes: only needed if shader has a get_buffer_size intrinsic
  77  *     for a given SSBO
  78  *
  79  *   + Image dimensions: needed to calculate pixel offset, but only for
  80  *     images that have a image_store intrinsic
  81  */
  82 struct ir3_driver_const_layout {
  83         struct {
  84                 uint32_t mask;  /* bitmask of SSBOs that have get_buffer_size */
  85                 uint32_t count; /* number of consts allocated */
  86                 /* one const allocated per SSBO which has get_buffer_size,
  87                  * ssbo_sizes.off[ssbo_id] is offset from start of ssbo_sizes
  88                  * consts:
  89                  */
  90                 uint32_t off[IR3_MAX_SHADER_BUFFERS];
  91         } ssbo_size;
  92
  93         struct {
  94                 uint32_t mask;  /* bitmask of images that have image_store */
  95                 uint32_t count; /* number of consts allocated */
  96                 /* three const allocated per image which has image_store:
  97                  *  + cpp         (bytes per pixel)
  98                  *  + pitch       (y pitch)
  99                  *  + array_pitch (z pitch)
 100                  */
 101                 uint32_t off[IR3_MAX_SHADER_IMAGES];
 102         } image_dims;
 103 };
 104
 105 /**
 106  * A single output for vertex transform feedback.
 107  */
 108 struct ir3_stream_output {
 109         unsigned register_index:6;  /**< 0 to 63 (OUT index) */
 110         unsigned start_component:2; /** 0 to 3 */
 111         unsigned num_components:3;  /** 1 to 4 */
 112         unsigned output_buffer:3;   /**< 0 to PIPE_MAX_SO_BUFFERS */
 113         unsigned dst_offset:16;     /**< offset into the buffer in dwords */
 114         unsigned stream:2;          /**< 0 to 3 */
 115 };
 116
 117 /**
 118  * Stream output for vertex transform feedback.
 119  */
 120 struct ir3_stream_output_info {
 121         unsigned num_outputs;
 122         /** stride for an entire vertex for each buffer in dwords */
 123         uint16_t stride[IR3_MAX_SO_BUFFERS];
 124
 125         /**
 126          * Array of stream outputs, in the order they are to be written in.
 127          * Selected components are tightly packed into the output buffer.
 128          */
 129         struct ir3_stream_output output[IR3_MAX_SO_OUTPUTS];
 130 };
 131
 132 /* Configuration key used to identify a shader variant.. different
 133  * shader variants can be used to implement features not supported
 134  * in hw (two sided color), binning-pass vertex shader, etc.
 135  */
 136 struct ir3_shader_key {
 137         union {
 138                 struct {
 139                         /*
 140                          * Combined Vertex/Fragment shader parameters:
 141                          */
 142                         unsigned ucp_enables : 8;
 143
 144                         /* do we need to check {v,f}saturate_{s,t,r}? */
 145                         unsigned has_per_samp : 1;
 146
 147                         /*
 148                          * Vertex shader variant parameters:
 149                          */
 150                         unsigned vclamp_color : 1;
 151
 152                         /*
 153                          * Fragment shader variant parameters:
 154                          */
 155                         unsigned color_two_side : 1;
 156                         unsigned half_precision : 1;
 157                         /* used when shader needs to handle flat varyings (a4xx)
 158                          * for front/back color inputs to frag shader:
 159                          */
 160                         unsigned rasterflat : 1;
 161                         unsigned fclamp_color : 1;
 162                 };
 163                 uint32_t global;
 164         };
 165
 166         /* bitmask of sampler which needs coords clamped for vertex
 167          * shader:
 168          */
 169         uint16_t vsaturate_s, vsaturate_t, vsaturate_r;
 170
 171         /* bitmask of sampler which needs coords clamped for frag
 172          * shader:
 173          */
 174         uint16_t fsaturate_s, fsaturate_t, fsaturate_r;
 175
 176         /* bitmask of ms shifts */
 177         uint32_t vsamples, fsamples;
 178
 179         /* bitmask of samplers which need astc srgb workaround: */
 180         uint16_t vastc_srgb, fastc_srgb;
 181 };
 182
 183 static inline bool
 184 ir3_shader_key_equal(struct ir3_shader_key *a, struct ir3_shader_key *b)
 185 {
 186         /* slow-path if we need to check {v,f}saturate_{s,t,r} */
 187         if (a->has_per_samp || b->has_per_samp)
 188                 return memcmp(a, b, sizeof(struct ir3_shader_key)) == 0;
 189         return a->global == b->global;
 190 }
 191
 192 /* will the two keys produce different lowering for a fragment shader? */
 193 static inline bool
 194 ir3_shader_key_changes_fs(struct ir3_shader_key *key, struct ir3_shader_key *last_key)
 195 {
 196         if (last_key->has_per_samp || key->has_per_samp) {
 197                 if ((last_key->fsaturate_s != key->fsaturate_s) ||
 198                                 (last_key->fsaturate_t != key->fsaturate_t) ||
 199                                 (last_key->fsaturate_r != key->fsaturate_r) ||
 200                                 (last_key->fsamples != key->fsamples) ||
 201                                 (last_key->fastc_srgb != key->fastc_srgb))
 202                         return true;
 203         }
 204
 205         if (last_key->fclamp_color != key->fclamp_color)
 206                 return true;
 207
 208         if (last_key->color_two_side != key->color_two_side)
 209                 return true;
 210
 211         if (last_key->half_precision != key->half_precision)
 212                 return true;
 213
 214         if (last_key->rasterflat != key->rasterflat)
 215                 return true;
 216
 217         if (last_key->ucp_enables != key->ucp_enables)
 218                 return true;
 219
 220         return false;
 221 }
 222
 223 /* will the two keys produce different lowering for a vertex shader? */
 224 static inline bool
 225 ir3_shader_key_changes_vs(struct ir3_shader_key *key, struct ir3_shader_key *last_key)
 226 {
 227         if (last_key->has_per_samp || key->has_per_samp) {
 228                 if ((last_key->vsaturate_s != key->vsaturate_s) ||
 229                                 (last_key->vsaturate_t != key->vsaturate_t) ||
 230                                 (last_key->vsaturate_r != key->vsaturate_r) ||
 231                                 (last_key->vsamples != key->vsamples) ||
 232                                 (last_key->vastc_srgb != key->vastc_srgb))
 233                         return true;
 234         }
 235
 236         if (last_key->vclamp_color != key->vclamp_color)
 237                 return true;
 238
 239         if (last_key->ucp_enables != key->ucp_enables)
 240                 return true;
 241
 242         return false;
 243 }
 244
 245 /* clears shader-key flags which don't apply to the given shader
 246  * stage
 247  */
 248 static inline void
 249 ir3_normalize_key(struct ir3_shader_key *key, gl_shader_stage type)
 250 {
 251         switch (type) {
 252         case MESA_SHADER_FRAGMENT:
 253                 if (key->has_per_samp) {
 254                         key->vsaturate_s = 0;
 255                         key->vsaturate_t = 0;
 256                         key->vsaturate_r = 0;
 257                         key->vastc_srgb = 0;
 258                         key->vsamples = 0;
 259                 }
 260                 break;
 261         case MESA_SHADER_VERTEX:
 262                 key->color_two_side = false;
 263                 key->half_precision = false;
 264                 key->rasterflat = false;
 265                 if (key->has_per_samp) {
 266                         key->fsaturate_s = 0;
 267                         key->fsaturate_t = 0;
 268                         key->fsaturate_r = 0;
 269                         key->fastc_srgb = 0;
 270                         key->fsamples = 0;
 271                 }
 272                 break;
 273         default:
 274                 /* TODO */
 275                 break;
 276         }
 277
 278 }
 279
 280 struct ir3_shader_variant {
 281         struct fd_bo *bo;
 282
 283         /* variant id (for debug) */
 284         uint32_t id;
 285
 286         struct ir3_shader_key key;
 287
 288         /* vertex shaders can have an extra version for hwbinning pass,
 289          * which is pointed to by so->binning:
 290          */
 291         bool binning_pass;
 292         struct ir3_shader_variant *binning;
 293
 294         struct ir3_driver_const_layout const_layout;
 295         struct ir3_info info;
 296         struct ir3 *ir;
 297
 298         /* the instructions length is in units of instruction groups
 299          * (4 instructions for a3xx, 16 instructions for a4xx.. each
 300          * instruction is 2 dwords):
 301          */
 302         unsigned instrlen;
 303
 304         /* the constants length is in units of vec4's, and is the sum of
 305          * the uniforms and the built-in compiler constants
 306          */
 307         unsigned constlen;
 308
 309         /* number of uniforms (in vec4), not including built-in compiler
 310          * constants, etc.
 311          */
 312         unsigned num_uniforms;
 313
 314         unsigned num_ubos;
 315
 316         /* About Linkage:
 317          *   + Let the frag shader determine the position/compmask for the
 318          *     varyings, since it is the place where we know if the varying
 319          *     is actually used, and if so, which components are used.  So
 320          *     what the hw calls "outloc" is taken from the "inloc" of the
 321          *     frag shader.
 322          *   + From the vert shader, we only need the output regid
 323          */
 324
 325         bool frag_coord, frag_face, color0_mrt;
 326
 327         /* NOTE: for input/outputs, slot is:
 328          *   gl_vert_attrib  - for VS inputs
 329          *   gl_varying_slot - for VS output / FS input
 330          *   gl_frag_result  - for FS output
 331          */
 332
 333         /* varyings/outputs: */
 334         unsigned outputs_count;
 335         struct {
 336                 uint8_t slot;
 337                 uint8_t regid;
 338         } outputs[16 + 2];  /* +POSITION +PSIZE */
 339         bool writes_pos, writes_psize;
 340
 341         /* attributes (VS) / varyings (FS):
 342          * Note that sysval's should come *after* normal inputs.
 343          */
 344         unsigned inputs_count;
 345         struct {
 346                 uint8_t slot;
 347                 uint8_t regid;
 348                 uint8_t compmask;
 349                 uint8_t ncomp;
 350                 /* location of input (ie. offset passed to bary.f, etc).  This
 351                  * matches the SP_VS_VPC_DST_REG.OUTLOCn value (a3xx and a4xx
 352                  * have the OUTLOCn value offset by 8, presumably to account
 353                  * for gl_Position/gl_PointSize)
 354                  */
 355                 uint8_t inloc;
 356                 /* vertex shader specific: */
 357                 bool    sysval     : 1;   /* slot is a gl_system_value */
 358                 /* fragment shader specific: */
 359                 bool    bary       : 1;   /* fetched varying (vs one loaded into reg) */
 360                 bool    rasterflat : 1;   /* special handling for emit->rasterflat */
 361                 enum glsl_interp_mode interpolate;
 362         } inputs[16 + 2];  /* +POSITION +FACE */
 363
 364         /* sum of input components (scalar).  For frag shaders, it only counts
 365          * the varying inputs:
 366          */
 367         unsigned total_in;
 368
 369         /* For frag shaders, the total number of inputs (not scalar,
 370          * ie. SP_VS_PARAM_REG.TOTALVSOUTVAR)
 371          */
 372         unsigned varying_in;
 373
 374         /* number of samplers/textures (which are currently 1:1): */
 375         int num_samp;
 376
 377         /* do we have one or more SSBO instructions: */
 378         bool has_ssbo;
 379
 380         /* do we have kill instructions: */
 381         bool has_kill;
 382
 383         /* Layout of constant registers, each section (in vec4). Pointer size
 384          * is 32b (a3xx, a4xx), or 64b (a5xx+), which effects the size of the
 385          * UBO and stream-out consts.
 386          */
 387         struct {
 388                 /* user const start at zero */
 389                 unsigned ubo;
 390                 /* NOTE that a3xx might need a section for SSBO addresses too */
 391                 unsigned ssbo_sizes;
 392                 unsigned image_dims;
 393                 unsigned driver_param;
 394                 unsigned tfbo;
 395                 unsigned immediate;
 396         } constbase;
 397
 398         unsigned immediates_count;
 399         unsigned immediates_size;
 400         struct {
 401                 uint32_t val[4];
 402         } *immediates;
 403
 404         /* for astc srgb workaround, the number/base of additional
 405          * alpha tex states we need, and index of original tex states
 406          */
 407         struct {
 408                 unsigned base, count;
 409                 unsigned orig_idx[16];
 410         } astc_srgb;
 411
 412         /* shader variants form a linked list: */
 413         struct ir3_shader_variant *next;
 414
 415         /* replicated here to avoid passing extra ptrs everywhere: */
 416         gl_shader_stage type;
 417         struct ir3_shader *shader;
 418 };
 419
 420 struct ir3_shader {
 421         gl_shader_stage type;
 422
 423         /* shader id (for debug): */
 424         uint32_t id;
 425         uint32_t variant_count;
 426
 427         /* so we know when we can disable TGSI related hacks: */
 428         bool from_tgsi;
 429
 430         struct ir3_compiler *compiler;
 431
 432         struct nir_shader *nir;
 433         struct ir3_stream_output_info stream_output;
 434
 435         struct ir3_shader_variant *variants;
 436 };
 437
 438 void * ir3_shader_assemble(struct ir3_shader_variant *v, uint32_t gpu_id);
 439 struct ir3_shader_variant * ir3_shader_get_variant(struct ir3_shader *shader,
 440                 struct ir3_shader_key *key, bool binning_pass, bool *created);
 441 struct ir3_shader * ir3_shader_from_nir(struct ir3_compiler *compiler, nir_shader *nir);
 442 void ir3_shader_destroy(struct ir3_shader *shader);
 443 void ir3_shader_disasm(struct ir3_shader_variant *so, uint32_t *bin, FILE *out);
 444 uint64_t ir3_shader_outputs(const struct ir3_shader *so);
 445
 446 int
 447 ir3_glsl_type_size(const struct glsl_type *type);
 448
 449 static inline const char *
 450 ir3_shader_stage(struct ir3_shader *shader)
 451 {
 452         switch (shader->type) {
 453         case MESA_SHADER_VERTEX:     return "VERT";
 454         case MESA_SHADER_FRAGMENT:   return "FRAG";
 455         case MESA_SHADER_COMPUTE:    return "CL";
 456         default:
 457                 unreachable("invalid type");
 458                 return NULL;
 459         }
 460 }
 461
 462 /*
 463  * Helper/util:
 464  */
 465
 466 static inline int
 467 ir3_find_output(const struct ir3_shader_variant *so, gl_varying_slot slot)
 468 {
 469         int j;
 470
 471         for (j = 0; j < so->outputs_count; j++)
 472                 if (so->outputs[j].slot == slot)
 473                         return j;
 474
 475         /* it seems optional to have a OUT.BCOLOR[n] for each OUT.COLOR[n]
 476          * in the vertex shader.. but the fragment shader doesn't know this
 477          * so  it will always have both IN.COLOR[n] and IN.BCOLOR[n].  So
 478          * at link time if there is no matching OUT.BCOLOR[n], we must map
 479          * OUT.COLOR[n] to IN.BCOLOR[n].  And visa versa if there is only
 480          * a OUT.BCOLOR[n] but no matching OUT.COLOR[n]
 481          */
 482         if (slot == VARYING_SLOT_BFC0) {
 483                 slot = VARYING_SLOT_COL0;
 484         } else if (slot == VARYING_SLOT_BFC1) {
 485                 slot = VARYING_SLOT_COL1;
 486         } else if (slot == VARYING_SLOT_COL0) {
 487                 slot = VARYING_SLOT_BFC0;
 488         } else if (slot == VARYING_SLOT_COL1) {
 489                 slot = VARYING_SLOT_BFC1;
 490         } else {
 491                 return 0;
 492         }
 493
 494         for (j = 0; j < so->outputs_count; j++)
 495                 if (so->outputs[j].slot == slot)
 496                         return j;
 497
 498         debug_assert(0);
 499
 500         return 0;
 501 }
 502
 503 static inline int
 504 ir3_next_varying(const struct ir3_shader_variant *so, int i)
 505 {
 506         while (++i < so->inputs_count)
 507                 if (so->inputs[i].compmask && so->inputs[i].bary)
 508                         break;
 509         return i;
 510 }
 511
 512 struct ir3_shader_linkage {
 513         uint8_t max_loc;
 514         uint8_t cnt;
 515         struct {
 516                 uint8_t regid;
 517                 uint8_t compmask;
 518                 uint8_t loc;
 519         } var[32];
 520 };
 521
 522 static inline void
 523 ir3_link_add(struct ir3_shader_linkage *l, uint8_t regid, uint8_t compmask, uint8_t loc)
 524 {
 525         int i = l->cnt++;
 526
 527         debug_assert(i < ARRAY_SIZE(l->var));
 528
 529         l->var[i].regid    = regid;
 530         l->var[i].compmask = compmask;
 531         l->var[i].loc      = loc;
 532         l->max_loc = MAX2(l->max_loc, loc + util_last_bit(compmask));
 533 }
 534
 535 static inline void
 536 ir3_link_shaders(struct ir3_shader_linkage *l,
 537                 const struct ir3_shader_variant *vs,
 538                 const struct ir3_shader_variant *fs)
 539 {
 540         int j = -1, k;
 541
 542         while (l->cnt < ARRAY_SIZE(l->var)) {
 543                 j = ir3_next_varying(fs, j);
 544
 545                 if (j >= fs->inputs_count)
 546                         break;
 547
 548                 if (fs->inputs[j].inloc >= fs->total_in)
 549                         continue;
 550
 551                 k = ir3_find_output(vs, fs->inputs[j].slot);
 552
 553                 ir3_link_add(l, vs->outputs[k].regid,
 554                         fs->inputs[j].compmask, fs->inputs[j].inloc);
 555         }
 556 }
 557
 558 static inline uint32_t
 559 ir3_find_output_regid(const struct ir3_shader_variant *so, unsigned slot)
 560 {
 561         int j;
 562         for (j = 0; j < so->outputs_count; j++)
 563                 if (so->outputs[j].slot == slot)
 564                         return so->outputs[j].regid;
 565         return regid(63, 0);
 566 }
 567
 568 static inline uint32_t
 569 ir3_find_sysval_regid(const struct ir3_shader_variant *so, unsigned slot)
 570 {
 571         int j;
 572         for (j = 0; j < so->inputs_count; j++)
 573                 if (so->inputs[j].sysval && (so->inputs[j].slot == slot))
 574                         return so->inputs[j].regid;
 575         return regid(63, 0);
 576 }
 577
 578 /* calculate register footprint in terms of half-regs (ie. one full
 579  * reg counts as two half-regs).
 580  */
 581 static inline uint32_t
 582 ir3_shader_halfregs(const struct ir3_shader_variant *v)
 583 {
 584         return (2 * (v->info.max_reg + 1)) + (v->info.max_half_reg + 1);
 585 }
 586
 587 #endif /* IR3_SHADER_H_ */