2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
32 #include "compiler/shader_enums.h"
33 #include "compiler/nir/nir.h"
34 #include "util/bitscan.h"
40 /* driver param indices: */
41 enum ir3_driver_param
{
42 /* compute shader driver params: */
43 IR3_DP_NUM_WORK_GROUPS_X
= 0,
44 IR3_DP_NUM_WORK_GROUPS_Y
= 1,
45 IR3_DP_NUM_WORK_GROUPS_Z
= 2,
46 IR3_DP_LOCAL_GROUP_SIZE_X
= 4,
47 IR3_DP_LOCAL_GROUP_SIZE_Y
= 5,
48 IR3_DP_LOCAL_GROUP_SIZE_Z
= 6,
49 /* NOTE: gl_NumWorkGroups should be vec4 aligned because
50 * glDispatchComputeIndirect() needs to load these from
51 * the info->indirect buffer. Keep that in mind when/if
52 * adding any addition CS driver params.
54 IR3_DP_CS_COUNT
= 8, /* must be aligned to vec4 */
56 /* vertex shader driver params: */
57 IR3_DP_VTXID_BASE
= 0,
58 IR3_DP_VTXCNT_MAX
= 1,
59 /* user-clip-plane components, up to 8x vec4's: */
63 IR3_DP_VS_COUNT
= 36 /* must be aligned to vec4 */
66 #define IR3_MAX_SHADER_BUFFERS 32
67 #define IR3_MAX_SHADER_IMAGES 32
68 #define IR3_MAX_SO_BUFFERS 4
69 #define IR3_MAX_SO_OUTPUTS 64
70 #define IR3_MAX_CONSTANT_BUFFERS 32
74 * For consts needed to pass internal values to shader which may or may not
75 * be required, rather than allocating worst-case const space, we scan the
76 * shader and allocate consts as-needed:
78 * + SSBO sizes: only needed if shader has a get_buffer_size intrinsic
81 * + Image dimensions: needed to calculate pixel offset, but only for
82 * images that have a image_store intrinsic
84 struct ir3_driver_const_layout
{
86 uint32_t mask
; /* bitmask of SSBOs that have get_buffer_size */
87 uint32_t count
; /* number of consts allocated */
88 /* one const allocated per SSBO which has get_buffer_size,
89 * ssbo_sizes.off[ssbo_id] is offset from start of ssbo_sizes
92 uint32_t off
[IR3_MAX_SHADER_BUFFERS
];
96 uint32_t mask
; /* bitmask of images that have image_store */
97 uint32_t count
; /* number of consts allocated */
98 /* three const allocated per image which has image_store:
99 * + cpp (bytes per pixel)
101 * + array_pitch (z pitch)
103 uint32_t off
[IR3_MAX_SHADER_IMAGES
];
108 * A single output for vertex transform feedback.
110 struct ir3_stream_output
{
111 unsigned register_index
:6; /**< 0 to 63 (OUT index) */
112 unsigned start_component
:2; /** 0 to 3 */
113 unsigned num_components
:3; /** 1 to 4 */
114 unsigned output_buffer
:3; /**< 0 to PIPE_MAX_SO_BUFFERS */
115 unsigned dst_offset
:16; /**< offset into the buffer in dwords */
116 unsigned stream
:2; /**< 0 to 3 */
120 * Stream output for vertex transform feedback.
122 struct ir3_stream_output_info
{
123 unsigned num_outputs
;
124 /** stride for an entire vertex for each buffer in dwords */
125 uint16_t stride
[IR3_MAX_SO_BUFFERS
];
128 * Array of stream outputs, in the order they are to be written in.
129 * Selected components are tightly packed into the output buffer.
131 struct ir3_stream_output output
[IR3_MAX_SO_OUTPUTS
];
134 /* Configuration key used to identify a shader variant.. different
135 * shader variants can be used to implement features not supported
136 * in hw (two sided color), binning-pass vertex shader, etc.
138 struct ir3_shader_key
{
142 * Combined Vertex/Fragment shader parameters:
144 unsigned ucp_enables
: 8;
146 /* do we need to check {v,f}saturate_{s,t,r}? */
147 unsigned has_per_samp
: 1;
150 * Vertex shader variant parameters:
152 unsigned vclamp_color
: 1;
155 * Fragment shader variant parameters:
157 unsigned sample_shading
: 1;
159 unsigned color_two_side
: 1;
160 unsigned half_precision
: 1;
161 /* used when shader needs to handle flat varyings (a4xx)
162 * for front/back color inputs to frag shader:
164 unsigned rasterflat
: 1;
165 unsigned fclamp_color
: 1;
170 /* bitmask of sampler which needs coords clamped for vertex
173 uint16_t vsaturate_s
, vsaturate_t
, vsaturate_r
;
175 /* bitmask of sampler which needs coords clamped for frag
178 uint16_t fsaturate_s
, fsaturate_t
, fsaturate_r
;
180 /* bitmask of ms shifts */
181 uint32_t vsamples
, fsamples
;
183 /* bitmask of samplers which need astc srgb workaround: */
184 uint16_t vastc_srgb
, fastc_srgb
;
188 ir3_shader_key_equal(struct ir3_shader_key
*a
, struct ir3_shader_key
*b
)
190 /* slow-path if we need to check {v,f}saturate_{s,t,r} */
191 if (a
->has_per_samp
|| b
->has_per_samp
)
192 return memcmp(a
, b
, sizeof(struct ir3_shader_key
)) == 0;
193 return a
->global
== b
->global
;
196 /* will the two keys produce different lowering for a fragment shader? */
198 ir3_shader_key_changes_fs(struct ir3_shader_key
*key
, struct ir3_shader_key
*last_key
)
200 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
201 if ((last_key
->fsaturate_s
!= key
->fsaturate_s
) ||
202 (last_key
->fsaturate_t
!= key
->fsaturate_t
) ||
203 (last_key
->fsaturate_r
!= key
->fsaturate_r
) ||
204 (last_key
->fsamples
!= key
->fsamples
) ||
205 (last_key
->fastc_srgb
!= key
->fastc_srgb
))
209 if (last_key
->fclamp_color
!= key
->fclamp_color
)
212 if (last_key
->color_two_side
!= key
->color_two_side
)
215 if (last_key
->half_precision
!= key
->half_precision
)
218 if (last_key
->rasterflat
!= key
->rasterflat
)
221 if (last_key
->ucp_enables
!= key
->ucp_enables
)
227 /* will the two keys produce different lowering for a vertex shader? */
229 ir3_shader_key_changes_vs(struct ir3_shader_key
*key
, struct ir3_shader_key
*last_key
)
231 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
232 if ((last_key
->vsaturate_s
!= key
->vsaturate_s
) ||
233 (last_key
->vsaturate_t
!= key
->vsaturate_t
) ||
234 (last_key
->vsaturate_r
!= key
->vsaturate_r
) ||
235 (last_key
->vsamples
!= key
->vsamples
) ||
236 (last_key
->vastc_srgb
!= key
->vastc_srgb
))
240 if (last_key
->vclamp_color
!= key
->vclamp_color
)
243 if (last_key
->ucp_enables
!= key
->ucp_enables
)
249 /* clears shader-key flags which don't apply to the given shader
253 ir3_normalize_key(struct ir3_shader_key
*key
, gl_shader_stage type
)
256 case MESA_SHADER_FRAGMENT
:
257 if (key
->has_per_samp
) {
258 key
->vsaturate_s
= 0;
259 key
->vsaturate_t
= 0;
260 key
->vsaturate_r
= 0;
265 case MESA_SHADER_VERTEX
:
266 key
->color_two_side
= false;
267 key
->half_precision
= false;
268 key
->rasterflat
= false;
269 if (key
->has_per_samp
) {
270 key
->fsaturate_s
= 0;
271 key
->fsaturate_t
= 0;
272 key
->fsaturate_r
= 0;
284 * On a4xx+a5xx, Images share state with textures and SSBOs:
286 * + Uses texture (cat5) state/instruction (isam) to read
287 * + Uses SSBO state and instructions (cat6) to write and for atomics
289 * Starting with a6xx, Images and SSBOs are basically the same thing,
290 * with texture state and isam also used for SSBO reads.
292 * On top of that, gallium makes the SSBO (shader_buffers) state semi
293 * sparse, with the first half of the state space used for atomic
294 * counters lowered to atomic buffers. We could ignore this, but I
295 * don't think we could *really* handle the case of a single shader
296 * that used the max # of textures + images + SSBOs. And once we are
297 * offsetting images by num_ssbos (or visa versa) to map them into
298 * the same hardware state, the hardware state has become coupled to
299 * the shader state, so at this point we might as well just use a
300 * mapping table to remap things from image/SSBO idx to hw idx.
302 * To make things less (more?) confusing, for the hw "SSBO" state
303 * (since it is really both SSBO and Image) I'll use the name "IBO"
305 struct ir3_ibo_mapping
{
306 #define IBO_INVALID 0xff
307 /* Maps logical SSBO state to hw state: */
308 uint8_t ssbo_to_ibo
[IR3_MAX_SHADER_BUFFERS
];
309 uint8_t ssbo_to_tex
[IR3_MAX_SHADER_BUFFERS
];
311 /* Maps logical Image state to hw state: */
312 uint8_t image_to_ibo
[IR3_MAX_SHADER_IMAGES
];
313 uint8_t image_to_tex
[IR3_MAX_SHADER_IMAGES
];
315 /* Maps hw state back to logical SSBO or Image state:
317 * note IBO_SSBO ORd into values to indicate that the
318 * hw slot is used for SSBO state vs Image state.
320 #define IBO_SSBO 0x80
321 uint8_t ibo_to_image
[32];
322 uint8_t tex_to_image
[32];
325 uint8_t num_tex
; /* including real textures */
326 uint8_t tex_base
; /* the number of real textures, ie. image/ssbo start here */
329 struct ir3_shader_variant
{
332 /* variant id (for debug) */
335 struct ir3_shader_key key
;
337 /* vertex shaders can have an extra version for hwbinning pass,
338 * which is pointed to by so->binning:
341 struct ir3_shader_variant
*binning
;
343 struct ir3_driver_const_layout const_layout
;
344 struct ir3_info info
;
347 /* Levels of nesting of flow control:
349 unsigned branchstack
;
353 /* the instructions length is in units of instruction groups
354 * (4 instructions for a3xx, 16 instructions for a4xx.. each
355 * instruction is 2 dwords):
359 /* the constants length is in units of vec4's, and is the sum of
360 * the uniforms and the built-in compiler constants
364 /* number of uniforms (in vec4), not including built-in compiler
367 unsigned num_uniforms
;
372 * + Let the frag shader determine the position/compmask for the
373 * varyings, since it is the place where we know if the varying
374 * is actually used, and if so, which components are used. So
375 * what the hw calls "outloc" is taken from the "inloc" of the
377 * + From the vert shader, we only need the output regid
380 bool frag_coord
, frag_face
, color0_mrt
;
382 /* NOTE: for input/outputs, slot is:
383 * gl_vert_attrib - for VS inputs
384 * gl_varying_slot - for VS output / FS input
385 * gl_frag_result - for FS output
388 /* varyings/outputs: */
389 unsigned outputs_count
;
393 } outputs
[16 + 2]; /* +POSITION +PSIZE */
394 bool writes_pos
, writes_smask
, writes_psize
;
396 /* attributes (VS) / varyings (FS):
397 * Note that sysval's should come *after* normal inputs.
399 unsigned inputs_count
;
405 /* location of input (ie. offset passed to bary.f, etc). This
406 * matches the SP_VS_VPC_DST_REG.OUTLOCn value (a3xx and a4xx
407 * have the OUTLOCn value offset by 8, presumably to account
408 * for gl_Position/gl_PointSize)
411 /* vertex shader specific: */
412 bool sysval
: 1; /* slot is a gl_system_value */
413 /* fragment shader specific: */
414 bool bary
: 1; /* fetched varying (vs one loaded into reg) */
415 bool rasterflat
: 1; /* special handling for emit->rasterflat */
416 enum glsl_interp_mode interpolate
;
417 } inputs
[16 + 2]; /* +POSITION +FACE */
419 /* sum of input components (scalar). For frag shaders, it only counts
420 * the varying inputs:
424 /* For frag shaders, the total number of inputs (not scalar,
425 * ie. SP_VS_PARAM_REG.TOTALVSOUTVAR)
429 /* Remapping table to map Image and SSBO to hw state: */
430 struct ir3_ibo_mapping image_mapping
;
432 /* number of samplers/textures (which are currently 1:1): */
435 /* do we have one or more SSBO instructions: */
438 /* do we need derivatives: */
441 /* do we have kill, image write, etc (which prevents early-z): */
446 /* Layout of constant registers, each section (in vec4). Pointer size
447 * is 32b (a3xx, a4xx), or 64b (a5xx+), which effects the size of the
448 * UBO and stream-out consts.
451 /* user const start at zero */
453 /* NOTE that a3xx might need a section for SSBO addresses too */
456 unsigned driver_param
;
461 unsigned immediates_count
;
462 unsigned immediates_size
;
467 /* for astc srgb workaround, the number/base of additional
468 * alpha tex states we need, and index of original tex states
471 unsigned base
, count
;
472 unsigned orig_idx
[16];
475 /* shader variants form a linked list: */
476 struct ir3_shader_variant
*next
;
478 /* replicated here to avoid passing extra ptrs everywhere: */
479 gl_shader_stage type
;
480 struct ir3_shader
*shader
;
483 struct ir3_ubo_range
{
484 uint32_t offset
; /* start offset of this block in const register file */
485 uint32_t start
, end
; /* range of block that's actually used */
488 struct ir3_ubo_analysis_state
490 struct ir3_ubo_range range
[IR3_MAX_CONSTANT_BUFFERS
];
492 uint32_t lower_count
;
497 gl_shader_stage type
;
499 /* shader id (for debug): */
501 uint32_t variant_count
;
503 /* so we know when we can disable TGSI related hacks: */
506 struct ir3_compiler
*compiler
;
508 struct ir3_ubo_analysis_state ubo_state
;
510 struct nir_shader
*nir
;
511 struct ir3_stream_output_info stream_output
;
513 struct ir3_shader_variant
*variants
;
516 void * ir3_shader_assemble(struct ir3_shader_variant
*v
, uint32_t gpu_id
);
517 struct ir3_shader_variant
* ir3_shader_get_variant(struct ir3_shader
*shader
,
518 struct ir3_shader_key
*key
, bool binning_pass
, bool *created
);
519 struct ir3_shader
* ir3_shader_from_nir(struct ir3_compiler
*compiler
, nir_shader
*nir
);
520 void ir3_shader_destroy(struct ir3_shader
*shader
);
521 void ir3_shader_disasm(struct ir3_shader_variant
*so
, uint32_t *bin
, FILE *out
);
522 uint64_t ir3_shader_outputs(const struct ir3_shader
*so
);
525 ir3_glsl_type_size(const struct glsl_type
*type
, bool bindless
);
527 static inline const char *
528 ir3_shader_stage(struct ir3_shader
*shader
)
530 switch (shader
->type
) {
531 case MESA_SHADER_VERTEX
: return "VERT";
532 case MESA_SHADER_FRAGMENT
: return "FRAG";
533 case MESA_SHADER_COMPUTE
: return "CL";
535 unreachable("invalid type");
545 ir3_find_output(const struct ir3_shader_variant
*so
, gl_varying_slot slot
)
549 for (j
= 0; j
< so
->outputs_count
; j
++)
550 if (so
->outputs
[j
].slot
== slot
)
553 /* it seems optional to have a OUT.BCOLOR[n] for each OUT.COLOR[n]
554 * in the vertex shader.. but the fragment shader doesn't know this
555 * so it will always have both IN.COLOR[n] and IN.BCOLOR[n]. So
556 * at link time if there is no matching OUT.BCOLOR[n], we must map
557 * OUT.COLOR[n] to IN.BCOLOR[n]. And visa versa if there is only
558 * a OUT.BCOLOR[n] but no matching OUT.COLOR[n]
560 if (slot
== VARYING_SLOT_BFC0
) {
561 slot
= VARYING_SLOT_COL0
;
562 } else if (slot
== VARYING_SLOT_BFC1
) {
563 slot
= VARYING_SLOT_COL1
;
564 } else if (slot
== VARYING_SLOT_COL0
) {
565 slot
= VARYING_SLOT_BFC0
;
566 } else if (slot
== VARYING_SLOT_COL1
) {
567 slot
= VARYING_SLOT_BFC1
;
572 for (j
= 0; j
< so
->outputs_count
; j
++)
573 if (so
->outputs
[j
].slot
== slot
)
582 ir3_next_varying(const struct ir3_shader_variant
*so
, int i
)
584 while (++i
< so
->inputs_count
)
585 if (so
->inputs
[i
].compmask
&& so
->inputs
[i
].bary
)
590 struct ir3_shader_linkage
{
601 ir3_link_add(struct ir3_shader_linkage
*l
, uint8_t regid
, uint8_t compmask
, uint8_t loc
)
605 debug_assert(i
< ARRAY_SIZE(l
->var
));
607 l
->var
[i
].regid
= regid
;
608 l
->var
[i
].compmask
= compmask
;
610 l
->max_loc
= MAX2(l
->max_loc
, loc
+ util_last_bit(compmask
));
614 ir3_link_shaders(struct ir3_shader_linkage
*l
,
615 const struct ir3_shader_variant
*vs
,
616 const struct ir3_shader_variant
*fs
)
620 while (l
->cnt
< ARRAY_SIZE(l
->var
)) {
621 j
= ir3_next_varying(fs
, j
);
623 if (j
>= fs
->inputs_count
)
626 if (fs
->inputs
[j
].inloc
>= fs
->total_in
)
629 k
= ir3_find_output(vs
, fs
->inputs
[j
].slot
);
631 ir3_link_add(l
, vs
->outputs
[k
].regid
,
632 fs
->inputs
[j
].compmask
, fs
->inputs
[j
].inloc
);
636 static inline uint32_t
637 ir3_find_output_regid(const struct ir3_shader_variant
*so
, unsigned slot
)
640 for (j
= 0; j
< so
->outputs_count
; j
++)
641 if (so
->outputs
[j
].slot
== slot
)
642 return so
->outputs
[j
].regid
;
646 static inline uint32_t
647 ir3_find_sysval_regid(const struct ir3_shader_variant
*so
, unsigned slot
)
650 for (j
= 0; j
< so
->inputs_count
; j
++)
651 if (so
->inputs
[j
].sysval
&& (so
->inputs
[j
].slot
== slot
))
652 return so
->inputs
[j
].regid
;
656 /* calculate register footprint in terms of half-regs (ie. one full
657 * reg counts as two half-regs).
659 static inline uint32_t
660 ir3_shader_halfregs(const struct ir3_shader_variant
*v
)
662 return (2 * (v
->info
.max_reg
+ 1)) + (v
->info
.max_half_reg
+ 1);
665 #endif /* IR3_SHADER_H_ */