2 * Copyright (C) 2014 Rob Clark <robclark@freedesktop.org>
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
20 * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE
24 * Rob Clark <robclark@freedesktop.org>
32 #include "c11/threads.h"
33 #include "compiler/shader_enums.h"
34 #include "compiler/nir/nir.h"
35 #include "util/bitscan.h"
41 /* driver param indices: */
42 enum ir3_driver_param
{
43 /* compute shader driver params: */
44 IR3_DP_NUM_WORK_GROUPS_X
= 0,
45 IR3_DP_NUM_WORK_GROUPS_Y
= 1,
46 IR3_DP_NUM_WORK_GROUPS_Z
= 2,
47 IR3_DP_LOCAL_GROUP_SIZE_X
= 4,
48 IR3_DP_LOCAL_GROUP_SIZE_Y
= 5,
49 IR3_DP_LOCAL_GROUP_SIZE_Z
= 6,
50 /* NOTE: gl_NumWorkGroups should be vec4 aligned because
51 * glDispatchComputeIndirect() needs to load these from
52 * the info->indirect buffer. Keep that in mind when/if
53 * adding any addition CS driver params.
55 IR3_DP_CS_COUNT
= 8, /* must be aligned to vec4 */
57 /* vertex shader driver params: */
58 IR3_DP_VTXID_BASE
= 0,
59 IR3_DP_VTXCNT_MAX
= 1,
60 IR3_DP_INSTID_BASE
= 2,
61 /* user-clip-plane components, up to 8x vec4's: */
65 IR3_DP_VS_COUNT
= 36 /* must be aligned to vec4 */
68 #define IR3_MAX_SHADER_BUFFERS 32
69 #define IR3_MAX_SHADER_IMAGES 32
70 #define IR3_MAX_SO_BUFFERS 4
71 #define IR3_MAX_SO_STREAMS 4
72 #define IR3_MAX_SO_OUTPUTS 64
73 #define IR3_MAX_UBO_PUSH_RANGES 32
76 struct ir3_ubo_range
{
77 uint32_t offset
; /* start offset to push in the const register file */
78 uint32_t block
; /* Which constant block */
79 uint32_t start
, end
; /* range of block that's actually used */
80 uint16_t bindless_base
; /* For bindless, which base register is used */
84 struct ir3_ubo_analysis_state
{
85 struct ir3_ubo_range range
[IR3_MAX_UBO_PUSH_RANGES
];
89 uint32_t cmdstream_size
; /* for per-gen backend to stash required cmdstream size */
93 * Describes the layout of shader consts. This includes:
94 * + User consts + driver lowered UBO ranges
96 * + Image sizes/dimensions
97 * + Driver params (ie. IR3_DP_*)
98 * + TFBO addresses (for generations that do not have hardware streamout)
99 * + Lowered immediates
101 * For consts needed to pass internal values to shader which may or may not
102 * be required, rather than allocating worst-case const space, we scan the
103 * shader and allocate consts as-needed:
105 * + SSBO sizes: only needed if shader has a get_buffer_size intrinsic
108 * + Image dimensions: needed to calculate pixel offset, but only for
109 * images that have a image_store intrinsic
111 * Layout of constant registers, each section aligned to vec4. Note
112 * that pointer size (ubo, etc) changes depending on generation.
117 * if (vertex shader) {
118 * driver params (IR3_DP_*)
119 * if (stream_output.num_outputs > 0)
120 * stream-out addresses
121 * } else if (compute_shader) {
122 * driver params (IR3_DP_*)
126 * Immediates go last mostly because they are inserted in the CP pass
127 * after the nir -> ir3 frontend.
129 * Note UBO size in bytes should be aligned to vec4
131 struct ir3_const_state
{
133 unsigned num_reserved_user_consts
;
134 unsigned num_driver_params
; /* scalar */
137 /* user const start at zero */
139 /* NOTE that a3xx might need a section for SSBO addresses too */
142 unsigned driver_param
;
144 unsigned primitive_param
;
145 unsigned primitive_map
;
150 uint32_t mask
; /* bitmask of SSBOs that have get_buffer_size */
151 uint32_t count
; /* number of consts allocated */
152 /* one const allocated per SSBO which has get_buffer_size,
153 * ssbo_sizes.off[ssbo_id] is offset from start of ssbo_sizes
156 uint32_t off
[IR3_MAX_SHADER_BUFFERS
];
160 uint32_t mask
; /* bitmask of images that have image_store */
161 uint32_t count
; /* number of consts allocated */
162 /* three const allocated per image which has image_store:
163 * + cpp (bytes per pixel)
165 * + array_pitch (z pitch)
167 uint32_t off
[IR3_MAX_SHADER_IMAGES
];
170 unsigned immediate_idx
;
171 unsigned immediates_count
;
172 unsigned immediates_size
;
177 /* State of ubo access lowered to push consts: */
178 struct ir3_ubo_analysis_state ubo_state
;
182 * A single output for vertex transform feedback.
184 struct ir3_stream_output
{
185 unsigned register_index
:6; /**< 0 to 63 (OUT index) */
186 unsigned start_component
:2; /** 0 to 3 */
187 unsigned num_components
:3; /** 1 to 4 */
188 unsigned output_buffer
:3; /**< 0 to PIPE_MAX_SO_BUFFERS */
189 unsigned dst_offset
:16; /**< offset into the buffer in dwords */
190 unsigned stream
:2; /**< 0 to 3 */
194 * Stream output for vertex transform feedback.
196 struct ir3_stream_output_info
{
197 unsigned num_outputs
;
198 /** stride for an entire vertex for each buffer in dwords */
199 uint16_t stride
[IR3_MAX_SO_BUFFERS
];
202 * Array of stream outputs, in the order they are to be written in.
203 * Selected components are tightly packed into the output buffer.
205 struct ir3_stream_output output
[IR3_MAX_SO_OUTPUTS
];
210 * Starting from a4xx, HW supports pre-dispatching texture sampling
211 * instructions prior to scheduling a shader stage, when the
212 * coordinate maps exactly to an output of the previous stage.
216 * There is a limit in the number of pre-dispatches allowed for any
219 #define IR3_MAX_SAMPLER_PREFETCH 4
222 * This is the output stream value for 'cmd', as used by blob. It may
223 * encode the return type (in 3 bits) but it hasn't been verified yet.
225 #define IR3_SAMPLER_PREFETCH_CMD 0x4
226 #define IR3_SAMPLER_BINDLESS_PREFETCH_CMD 0x6
229 * Stream output for texture sampling pre-dispatches.
231 struct ir3_sampler_prefetch
{
235 uint16_t samp_bindless_id
;
236 uint16_t tex_bindless_id
;
239 uint8_t half_precision
;
244 /* Configuration key used to identify a shader variant.. different
245 * shader variants can be used to implement features not supported
246 * in hw (two sided color), binning-pass vertex shader, etc.
248 * When adding to this struct, please update ir3_shader_variant()'s debug
251 struct ir3_shader_key
{
255 * Combined Vertex/Fragment shader parameters:
257 unsigned ucp_enables
: 8;
259 /* do we need to check {v,f}saturate_{s,t,r}? */
260 unsigned has_per_samp
: 1;
263 * Vertex shader variant parameters:
265 unsigned vclamp_color
: 1;
268 * Fragment shader variant parameters:
270 unsigned sample_shading
: 1;
272 unsigned color_two_side
: 1;
273 /* used when shader needs to handle flat varyings (a4xx)
274 * for front/back color inputs to frag shader:
276 unsigned rasterflat
: 1;
277 unsigned fclamp_color
: 1;
279 /* Indicates that this is a tessellation pipeline which requires a
280 * whole different kind of vertex shader. In case of
281 * tessellation, this field also tells us which kind of output
282 * topology the TES uses, which the TCS needs to know.
284 #define IR3_TESS_NONE 0
285 #define IR3_TESS_TRIANGLES 1
286 #define IR3_TESS_QUADS 2
287 #define IR3_TESS_ISOLINES 3
288 unsigned tessellation
: 2;
295 /* bitmask of sampler which needs coords clamped for vertex
298 uint16_t vsaturate_s
, vsaturate_t
, vsaturate_r
;
300 /* bitmask of sampler which needs coords clamped for frag
303 uint16_t fsaturate_s
, fsaturate_t
, fsaturate_r
;
305 /* bitmask of ms shifts */
306 uint32_t vsamples
, fsamples
;
308 /* bitmask of samplers which need astc srgb workaround: */
309 uint16_t vastc_srgb
, fastc_srgb
;
312 static inline unsigned
313 ir3_tess_mode(unsigned gl_tess_mode
)
315 switch (gl_tess_mode
) {
317 return IR3_TESS_ISOLINES
;
319 return IR3_TESS_TRIANGLES
;
321 return IR3_TESS_QUADS
;
323 unreachable("bad tessmode");
328 ir3_shader_key_equal(const struct ir3_shader_key
*a
, const struct ir3_shader_key
*b
)
330 /* slow-path if we need to check {v,f}saturate_{s,t,r} */
331 if (a
->has_per_samp
|| b
->has_per_samp
)
332 return memcmp(a
, b
, sizeof(struct ir3_shader_key
)) == 0;
333 return a
->global
== b
->global
;
336 /* will the two keys produce different lowering for a fragment shader? */
338 ir3_shader_key_changes_fs(struct ir3_shader_key
*key
, struct ir3_shader_key
*last_key
)
340 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
341 if ((last_key
->fsaturate_s
!= key
->fsaturate_s
) ||
342 (last_key
->fsaturate_t
!= key
->fsaturate_t
) ||
343 (last_key
->fsaturate_r
!= key
->fsaturate_r
) ||
344 (last_key
->fsamples
!= key
->fsamples
) ||
345 (last_key
->fastc_srgb
!= key
->fastc_srgb
))
349 if (last_key
->fclamp_color
!= key
->fclamp_color
)
352 if (last_key
->color_two_side
!= key
->color_two_side
)
355 if (last_key
->rasterflat
!= key
->rasterflat
)
358 if (last_key
->ucp_enables
!= key
->ucp_enables
)
364 /* will the two keys produce different lowering for a vertex shader? */
366 ir3_shader_key_changes_vs(struct ir3_shader_key
*key
, struct ir3_shader_key
*last_key
)
368 if (last_key
->has_per_samp
|| key
->has_per_samp
) {
369 if ((last_key
->vsaturate_s
!= key
->vsaturate_s
) ||
370 (last_key
->vsaturate_t
!= key
->vsaturate_t
) ||
371 (last_key
->vsaturate_r
!= key
->vsaturate_r
) ||
372 (last_key
->vsamples
!= key
->vsamples
) ||
373 (last_key
->vastc_srgb
!= key
->vastc_srgb
))
377 if (last_key
->vclamp_color
!= key
->vclamp_color
)
380 if (last_key
->ucp_enables
!= key
->ucp_enables
)
387 * On a4xx+a5xx, Images share state with textures and SSBOs:
389 * + Uses texture (cat5) state/instruction (isam) to read
390 * + Uses SSBO state and instructions (cat6) to write and for atomics
392 * Starting with a6xx, Images and SSBOs are basically the same thing,
393 * with texture state and isam also used for SSBO reads.
395 * On top of that, gallium makes the SSBO (shader_buffers) state semi
396 * sparse, with the first half of the state space used for atomic
397 * counters lowered to atomic buffers. We could ignore this, but I
398 * don't think we could *really* handle the case of a single shader
399 * that used the max # of textures + images + SSBOs. And once we are
400 * offsetting images by num_ssbos (or visa versa) to map them into
401 * the same hardware state, the hardware state has become coupled to
402 * the shader state, so at this point we might as well just use a
403 * mapping table to remap things from image/SSBO idx to hw idx.
405 * To make things less (more?) confusing, for the hw "SSBO" state
406 * (since it is really both SSBO and Image) I'll use the name "IBO"
408 struct ir3_ibo_mapping
{
409 #define IBO_INVALID 0xff
410 /* Maps logical SSBO state to hw tex state: */
411 uint8_t ssbo_to_tex
[IR3_MAX_SHADER_BUFFERS
];
413 /* Maps logical Image state to hw tex state: */
414 uint8_t image_to_tex
[IR3_MAX_SHADER_IMAGES
];
416 /* Maps hw state back to logical SSBO or Image state:
418 * note IBO_SSBO ORd into values to indicate that the
419 * hw slot is used for SSBO state vs Image state.
421 #define IBO_SSBO 0x80
422 uint8_t tex_to_image
[32];
424 uint8_t num_tex
; /* including real textures */
425 uint8_t tex_base
; /* the number of real textures, ie. image/ssbo start here */
428 /* Represents half register in regid */
429 #define HALF_REG_ID 0x100
431 struct ir3_shader_variant
{
434 /* variant id (for debug) */
437 struct ir3_shader_key key
;
439 /* vertex shaders can have an extra version for hwbinning pass,
440 * which is pointed to by so->binning:
444 struct ir3_shader_variant
*binning
;
445 struct ir3_shader_variant
*nonbinning
;
448 struct ir3_info info
;
451 /* The actual binary shader instructions, size given by info.sizedwords: */
454 /* Levels of nesting of flow control:
456 unsigned branchstack
;
461 /* the instructions length is in units of instruction groups
462 * (4 instructions for a3xx, 16 instructions for a4xx.. each
463 * instruction is 2 dwords):
467 /* the constants length is in units of vec4's, and is the sum of
468 * the uniforms and the built-in compiler constants
473 * + Let the frag shader determine the position/compmask for the
474 * varyings, since it is the place where we know if the varying
475 * is actually used, and if so, which components are used. So
476 * what the hw calls "outloc" is taken from the "inloc" of the
478 * + From the vert shader, we only need the output regid
481 bool frag_face
, color0_mrt
;
482 uint8_t fragcoord_compmask
;
484 /* NOTE: for input/outputs, slot is:
485 * gl_vert_attrib - for VS inputs
486 * gl_varying_slot - for VS output / FS input
487 * gl_frag_result - for FS output
490 /* varyings/outputs: */
491 unsigned outputs_count
;
496 } outputs
[32 + 2]; /* +POSITION +PSIZE */
497 bool writes_pos
, writes_smask
, writes_psize
;
499 /* attributes (VS) / varyings (FS):
500 * Note that sysval's should come *after* normal inputs.
502 unsigned inputs_count
;
507 /* location of input (ie. offset passed to bary.f, etc). This
508 * matches the SP_VS_VPC_DST_REG.OUTLOCn value (a3xx and a4xx
509 * have the OUTLOCn value offset by 8, presumably to account
510 * for gl_Position/gl_PointSize)
513 /* vertex shader specific: */
514 bool sysval
: 1; /* slot is a gl_system_value */
515 /* fragment shader specific: */
516 bool bary
: 1; /* fetched varying (vs one loaded into reg) */
517 bool rasterflat
: 1; /* special handling for emit->rasterflat */
518 bool use_ldlv
: 1; /* internal to ir3_compiler_nir */
520 enum glsl_interp_mode interpolate
;
521 } inputs
[32 + 2]; /* +POSITION +FACE */
523 /* sum of input components (scalar). For frag shaders, it only counts
524 * the varying inputs:
528 /* For frag shaders, the total number of inputs (not scalar,
529 * ie. SP_VS_PARAM_REG.TOTALVSOUTVAR)
533 /* Remapping table to map Image and SSBO to hw state: */
534 struct ir3_ibo_mapping image_mapping
;
536 /* number of samplers/textures (which are currently 1:1): */
539 /* is there an implicit sampler to read framebuffer (FS only).. if
540 * so the sampler-idx is 'num_samp - 1' (ie. it is appended after
541 * the last "real" texture)
545 /* do we have one or more SSBO instructions: */
548 /* Which bindless resources are used, for filling out sp_xs_config */
554 /* do we need derivatives: */
557 bool need_fine_derivatives
;
559 /* do we have image write, etc (which prevents early-z): */
562 /* do we have kill, which also prevents early-z, but not necessarily
563 * early-lrz (as long as lrz-write is disabled, which must be handled
564 * outside of ir3. Unlike other no_earlyz cases, kill doesn't have
565 * side effects that prevent early-lrz discard.
571 /* Are we using split or merged register file? */
574 /* for astc srgb workaround, the number/base of additional
575 * alpha tex states we need, and index of original tex states
578 unsigned base
, count
;
579 unsigned orig_idx
[16];
582 /* shader variants form a linked list: */
583 struct ir3_shader_variant
*next
;
585 /* replicated here to avoid passing extra ptrs everywhere: */
586 gl_shader_stage type
;
587 struct ir3_shader
*shader
;
589 /* texture sampler pre-dispatches */
590 uint32_t num_sampler_prefetch
;
591 struct ir3_sampler_prefetch sampler_prefetch
[IR3_MAX_SAMPLER_PREFETCH
];
594 static inline const char *
595 ir3_shader_stage(struct ir3_shader_variant
*v
)
598 case MESA_SHADER_VERTEX
: return v
->binning_pass
? "BVERT" : "VERT";
599 case MESA_SHADER_TESS_CTRL
: return "TCS";
600 case MESA_SHADER_TESS_EVAL
: return "TES";
601 case MESA_SHADER_GEOMETRY
: return "GEOM";
602 case MESA_SHADER_FRAGMENT
: return "FRAG";
603 case MESA_SHADER_COMPUTE
: return "CL";
605 unreachable("invalid type");
612 gl_shader_stage type
;
614 /* shader id (for debug): */
616 uint32_t variant_count
;
618 /* Set by freedreno after shader_state_create, so we can emit debug info
619 * when recompiling a shader at draw time.
621 bool initial_variants_done
;
623 struct ir3_compiler
*compiler
;
625 struct ir3_const_state const_state
;
627 struct nir_shader
*nir
;
628 struct ir3_stream_output_info stream_output
;
630 struct ir3_shader_variant
*variants
;
633 uint32_t output_size
; /* Size in dwords of all outputs for VS, size of entire patch for HS. */
635 /* Map from driver_location to byte offset in per-primitive storage */
636 unsigned output_loc
[32];
638 /* Bitmask of bits of the shader key used by this shader. Used to avoid
639 * recompiles for GL NOS that doesn't actually apply to the shader.
641 struct ir3_shader_key key_mask
;
644 static inline struct ir3_const_state
*
645 ir3_const_state(const struct ir3_shader_variant
*v
)
647 return &v
->shader
->const_state
;
650 void * ir3_shader_assemble(struct ir3_shader_variant
*v
);
651 struct ir3_shader_variant
* ir3_shader_get_variant(struct ir3_shader
*shader
,
652 const struct ir3_shader_key
*key
, bool binning_pass
, bool *created
);
653 struct ir3_shader
* ir3_shader_from_nir(struct ir3_compiler
*compiler
, nir_shader
*nir
,
654 unsigned reserved_user_consts
, struct ir3_stream_output_info
*stream_output
);
655 void ir3_shader_destroy(struct ir3_shader
*shader
);
656 void ir3_shader_disasm(struct ir3_shader_variant
*so
, uint32_t *bin
, FILE *out
);
657 uint64_t ir3_shader_outputs(const struct ir3_shader
*so
);
660 ir3_glsl_type_size(const struct glsl_type
*type
, bool bindless
);
666 /* clears shader-key flags which don't apply to the given shader.
669 ir3_key_clear_unused(struct ir3_shader_key
*key
, struct ir3_shader
*shader
)
671 uint32_t *key_bits
= (uint32_t *)key
;
672 uint32_t *key_mask
= (uint32_t *)&shader
->key_mask
;
673 STATIC_ASSERT(sizeof(*key
) % 4 == 0);
674 for (int i
= 0; i
< sizeof(*key
) >> 2; i
++)
675 key_bits
[i
] &= key_mask
[i
];
679 ir3_find_output(const struct ir3_shader_variant
*so
, gl_varying_slot slot
)
683 for (j
= 0; j
< so
->outputs_count
; j
++)
684 if (so
->outputs
[j
].slot
== slot
)
687 /* it seems optional to have a OUT.BCOLOR[n] for each OUT.COLOR[n]
688 * in the vertex shader.. but the fragment shader doesn't know this
689 * so it will always have both IN.COLOR[n] and IN.BCOLOR[n]. So
690 * at link time if there is no matching OUT.BCOLOR[n], we must map
691 * OUT.COLOR[n] to IN.BCOLOR[n]. And visa versa if there is only
692 * a OUT.BCOLOR[n] but no matching OUT.COLOR[n]
694 if (slot
== VARYING_SLOT_BFC0
) {
695 slot
= VARYING_SLOT_COL0
;
696 } else if (slot
== VARYING_SLOT_BFC1
) {
697 slot
= VARYING_SLOT_COL1
;
698 } else if (slot
== VARYING_SLOT_COL0
) {
699 slot
= VARYING_SLOT_BFC0
;
700 } else if (slot
== VARYING_SLOT_COL1
) {
701 slot
= VARYING_SLOT_BFC1
;
706 for (j
= 0; j
< so
->outputs_count
; j
++)
707 if (so
->outputs
[j
].slot
== slot
)
716 ir3_next_varying(const struct ir3_shader_variant
*so
, int i
)
718 while (++i
< so
->inputs_count
)
719 if (so
->inputs
[i
].compmask
&& so
->inputs
[i
].bary
)
724 struct ir3_shader_linkage
{
725 /* Maximum location either consumed by the fragment shader or produced by
726 * the last geometry stage, i.e. the size required for each vertex in the
731 /* Number of entries in var. */
734 /* Bitset of locations used, including ones which are only used by the FS.
738 /* Map from VS output to location. */
745 /* location for fixed-function gl_PrimitiveID passthrough */
750 ir3_link_add(struct ir3_shader_linkage
*l
, uint8_t regid_
, uint8_t compmask
, uint8_t loc
)
754 for (int j
= 0; j
< util_last_bit(compmask
); j
++) {
755 uint8_t comploc
= loc
+ j
;
756 l
->varmask
[comploc
/ 32] |= 1 << (comploc
% 32);
759 l
->max_loc
= MAX2(l
->max_loc
, loc
+ util_last_bit(compmask
));
761 if (regid_
!= regid(63, 0)) {
763 debug_assert(i
< ARRAY_SIZE(l
->var
));
765 l
->var
[i
].regid
= regid_
;
766 l
->var
[i
].compmask
= compmask
;
772 ir3_link_shaders(struct ir3_shader_linkage
*l
,
773 const struct ir3_shader_variant
*vs
,
774 const struct ir3_shader_variant
*fs
,
777 /* On older platforms, varmask isn't programmed at all, and it appears
778 * that the hardware generates a mask of used VPC locations using the VS
779 * output map, and hangs if a FS bary instruction references a location
780 * not in the list. This means that we need to have a dummy entry in the
781 * VS out map for things like gl_PointCoord which aren't written by the
782 * VS. Furthermore we can't use r63.x, so just pick a random register to
783 * use if there is no VS output.
785 const unsigned default_regid
= pack_vs_out
? regid(63, 0) : regid(0, 0);
788 l
->primid_loc
= 0xff;
790 while (l
->cnt
< ARRAY_SIZE(l
->var
)) {
791 j
= ir3_next_varying(fs
, j
);
793 if (j
>= fs
->inputs_count
)
796 if (fs
->inputs
[j
].inloc
>= fs
->total_in
)
799 k
= ir3_find_output(vs
, fs
->inputs
[j
].slot
);
801 if (k
< 0 && fs
->inputs
[j
].slot
== VARYING_SLOT_PRIMITIVE_ID
) {
802 l
->primid_loc
= fs
->inputs
[j
].inloc
;
805 ir3_link_add(l
, k
>= 0 ? vs
->outputs
[k
].regid
: default_regid
,
806 fs
->inputs
[j
].compmask
, fs
->inputs
[j
].inloc
);
810 static inline uint32_t
811 ir3_find_output_regid(const struct ir3_shader_variant
*so
, unsigned slot
)
814 for (j
= 0; j
< so
->outputs_count
; j
++)
815 if (so
->outputs
[j
].slot
== slot
) {
816 uint32_t regid
= so
->outputs
[j
].regid
;
817 if (so
->outputs
[j
].half
)
818 regid
|= HALF_REG_ID
;
824 #define VARYING_SLOT_GS_HEADER_IR3 (VARYING_SLOT_MAX + 0)
825 #define VARYING_SLOT_GS_VERTEX_FLAGS_IR3 (VARYING_SLOT_MAX + 1)
826 #define VARYING_SLOT_TCS_HEADER_IR3 (VARYING_SLOT_MAX + 2)
829 static inline uint32_t
830 ir3_find_sysval_regid(const struct ir3_shader_variant
*so
, unsigned slot
)
833 for (j
= 0; j
< so
->inputs_count
; j
++)
834 if (so
->inputs
[j
].sysval
&& (so
->inputs
[j
].slot
== slot
))
835 return so
->inputs
[j
].regid
;
839 /* calculate register footprint in terms of half-regs (ie. one full
840 * reg counts as two half-regs).
842 static inline uint32_t
843 ir3_shader_halfregs(const struct ir3_shader_variant
*v
)
845 return (2 * (v
->info
.max_reg
+ 1)) + (v
->info
.max_half_reg
+ 1);
848 static inline uint32_t
849 ir3_shader_nibo(const struct ir3_shader_variant
*v
)
851 /* The dummy variant used in binning mode won't have an actual shader. */
855 return v
->shader
->nir
->info
.num_ssbos
+ v
->shader
->nir
->info
.num_images
;
858 #endif /* IR3_SHADER_H_ */