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[mesa.git] / src / freedreno / registers / a3xx.xml.h
1 #ifndef A3XX_XML
2 #define A3XX_XML
3
4 /* Autogenerated file, DO NOT EDIT manually!
5
6 This file was generated by the rules-ng-ng headergen tool in this git repository:
7 http://github.com/freedreno/envytools/
8 git clone https://github.com/freedreno/envytools.git
9
10 The rules-ng-ng source files this header was generated from are:
11 - /home/robclark/src/envytools/rnndb/adreno.xml ( 501 bytes, from 2018-07-03 19:37:13)
12 - /home/robclark/src/envytools/rnndb/freedreno_copyright.xml ( 1572 bytes, from 2018-07-03 19:37:13)
13 - /home/robclark/src/envytools/rnndb/adreno/a2xx.xml ( 79608 bytes, from 2019-01-21 14:36:17)
14 - /home/robclark/src/envytools/rnndb/adreno/adreno_common.xml ( 14239 bytes, from 2018-12-05 15:25:53)
15 - /home/robclark/src/envytools/rnndb/adreno/adreno_pm4.xml ( 43561 bytes, from 2019-06-10 13:39:33)
16 - /home/robclark/src/envytools/rnndb/adreno/a3xx.xml ( 84030 bytes, from 2019-07-01 13:05:23)
17 - /home/robclark/src/envytools/rnndb/adreno/a4xx.xml ( 112086 bytes, from 2018-07-03 19:37:13)
18 - /home/robclark/src/envytools/rnndb/adreno/a5xx.xml ( 147548 bytes, from 2019-06-10 13:39:33)
19 - /home/robclark/src/envytools/rnndb/adreno/a6xx.xml ( 152605 bytes, from 2019-07-01 13:13:03)
20 - /home/robclark/src/envytools/rnndb/adreno/a6xx_gmu.xml ( 10431 bytes, from 2018-09-14 13:03:07)
21 - /home/robclark/src/envytools/rnndb/adreno/ocmem.xml ( 1773 bytes, from 2018-07-03 19:37:13)
22
23 Copyright (C) 2013-2019 by the following authors:
24 - Rob Clark <robdclark@gmail.com> (robclark)
25 - Ilia Mirkin <imirkin@alum.mit.edu> (imirkin)
26
27 Permission is hereby granted, free of charge, to any person obtaining
28 a copy of this software and associated documentation files (the
29 "Software"), to deal in the Software without restriction, including
30 without limitation the rights to use, copy, modify, merge, publish,
31 distribute, sublicense, and/or sell copies of the Software, and to
32 permit persons to whom the Software is furnished to do so, subject to
33 the following conditions:
34
35 The above copyright notice and this permission notice (including the
36 next paragraph) shall be included in all copies or substantial
37 portions of the Software.
38
39 THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
40 EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
41 MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
42 IN NO EVENT SHALL THE COPYRIGHT OWNER(S) AND/OR ITS SUPPLIERS BE
43 LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER IN AN ACTION
44 OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN CONNECTION
45 WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE.
46 */
47
48
49 enum a3xx_tile_mode {
50 LINEAR = 0,
51 TILE_4X4 = 1,
52 TILE_32X32 = 2,
53 TILE_4X2 = 3,
54 };
55
56 enum a3xx_state_block_id {
57 HLSQ_BLOCK_ID_TP_TEX = 2,
58 HLSQ_BLOCK_ID_TP_MIPMAP = 3,
59 HLSQ_BLOCK_ID_SP_VS = 4,
60 HLSQ_BLOCK_ID_SP_FS = 6,
61 };
62
63 enum a3xx_cache_opcode {
64 INVALIDATE = 1,
65 };
66
67 enum a3xx_vtx_fmt {
68 VFMT_32_FLOAT = 0,
69 VFMT_32_32_FLOAT = 1,
70 VFMT_32_32_32_FLOAT = 2,
71 VFMT_32_32_32_32_FLOAT = 3,
72 VFMT_16_FLOAT = 4,
73 VFMT_16_16_FLOAT = 5,
74 VFMT_16_16_16_FLOAT = 6,
75 VFMT_16_16_16_16_FLOAT = 7,
76 VFMT_32_FIXED = 8,
77 VFMT_32_32_FIXED = 9,
78 VFMT_32_32_32_FIXED = 10,
79 VFMT_32_32_32_32_FIXED = 11,
80 VFMT_16_SINT = 16,
81 VFMT_16_16_SINT = 17,
82 VFMT_16_16_16_SINT = 18,
83 VFMT_16_16_16_16_SINT = 19,
84 VFMT_16_UINT = 20,
85 VFMT_16_16_UINT = 21,
86 VFMT_16_16_16_UINT = 22,
87 VFMT_16_16_16_16_UINT = 23,
88 VFMT_16_SNORM = 24,
89 VFMT_16_16_SNORM = 25,
90 VFMT_16_16_16_SNORM = 26,
91 VFMT_16_16_16_16_SNORM = 27,
92 VFMT_16_UNORM = 28,
93 VFMT_16_16_UNORM = 29,
94 VFMT_16_16_16_UNORM = 30,
95 VFMT_16_16_16_16_UNORM = 31,
96 VFMT_32_UINT = 32,
97 VFMT_32_32_UINT = 33,
98 VFMT_32_32_32_UINT = 34,
99 VFMT_32_32_32_32_UINT = 35,
100 VFMT_32_SINT = 36,
101 VFMT_32_32_SINT = 37,
102 VFMT_32_32_32_SINT = 38,
103 VFMT_32_32_32_32_SINT = 39,
104 VFMT_8_UINT = 40,
105 VFMT_8_8_UINT = 41,
106 VFMT_8_8_8_UINT = 42,
107 VFMT_8_8_8_8_UINT = 43,
108 VFMT_8_UNORM = 44,
109 VFMT_8_8_UNORM = 45,
110 VFMT_8_8_8_UNORM = 46,
111 VFMT_8_8_8_8_UNORM = 47,
112 VFMT_8_SINT = 48,
113 VFMT_8_8_SINT = 49,
114 VFMT_8_8_8_SINT = 50,
115 VFMT_8_8_8_8_SINT = 51,
116 VFMT_8_SNORM = 52,
117 VFMT_8_8_SNORM = 53,
118 VFMT_8_8_8_SNORM = 54,
119 VFMT_8_8_8_8_SNORM = 55,
120 VFMT_10_10_10_2_UINT = 56,
121 VFMT_10_10_10_2_UNORM = 57,
122 VFMT_10_10_10_2_SINT = 58,
123 VFMT_10_10_10_2_SNORM = 59,
124 VFMT_2_10_10_10_UINT = 60,
125 VFMT_2_10_10_10_UNORM = 61,
126 VFMT_2_10_10_10_SINT = 62,
127 VFMT_2_10_10_10_SNORM = 63,
128 };
129
130 enum a3xx_tex_fmt {
131 TFMT_5_6_5_UNORM = 4,
132 TFMT_5_5_5_1_UNORM = 5,
133 TFMT_4_4_4_4_UNORM = 7,
134 TFMT_Z16_UNORM = 9,
135 TFMT_X8Z24_UNORM = 10,
136 TFMT_Z32_FLOAT = 11,
137 TFMT_UV_64X32 = 16,
138 TFMT_VU_64X32 = 17,
139 TFMT_Y_64X32 = 18,
140 TFMT_NV12_64X32 = 19,
141 TFMT_UV_LINEAR = 20,
142 TFMT_VU_LINEAR = 21,
143 TFMT_Y_LINEAR = 22,
144 TFMT_NV12_LINEAR = 23,
145 TFMT_I420_Y = 24,
146 TFMT_I420_U = 26,
147 TFMT_I420_V = 27,
148 TFMT_ATC_RGB = 32,
149 TFMT_ATC_RGBA_EXPLICIT = 33,
150 TFMT_ETC1 = 34,
151 TFMT_ATC_RGBA_INTERPOLATED = 35,
152 TFMT_DXT1 = 36,
153 TFMT_DXT3 = 37,
154 TFMT_DXT5 = 38,
155 TFMT_2_10_10_10_UNORM = 40,
156 TFMT_10_10_10_2_UNORM = 41,
157 TFMT_9_9_9_E5_FLOAT = 42,
158 TFMT_11_11_10_FLOAT = 43,
159 TFMT_A8_UNORM = 44,
160 TFMT_L8_UNORM = 45,
161 TFMT_L8_A8_UNORM = 47,
162 TFMT_8_UNORM = 48,
163 TFMT_8_8_UNORM = 49,
164 TFMT_8_8_8_UNORM = 50,
165 TFMT_8_8_8_8_UNORM = 51,
166 TFMT_8_SNORM = 52,
167 TFMT_8_8_SNORM = 53,
168 TFMT_8_8_8_SNORM = 54,
169 TFMT_8_8_8_8_SNORM = 55,
170 TFMT_8_UINT = 56,
171 TFMT_8_8_UINT = 57,
172 TFMT_8_8_8_UINT = 58,
173 TFMT_8_8_8_8_UINT = 59,
174 TFMT_8_SINT = 60,
175 TFMT_8_8_SINT = 61,
176 TFMT_8_8_8_SINT = 62,
177 TFMT_8_8_8_8_SINT = 63,
178 TFMT_16_FLOAT = 64,
179 TFMT_16_16_FLOAT = 65,
180 TFMT_16_16_16_16_FLOAT = 67,
181 TFMT_16_UINT = 68,
182 TFMT_16_16_UINT = 69,
183 TFMT_16_16_16_16_UINT = 71,
184 TFMT_16_SINT = 72,
185 TFMT_16_16_SINT = 73,
186 TFMT_16_16_16_16_SINT = 75,
187 TFMT_16_UNORM = 76,
188 TFMT_16_16_UNORM = 77,
189 TFMT_16_16_16_16_UNORM = 79,
190 TFMT_16_SNORM = 80,
191 TFMT_16_16_SNORM = 81,
192 TFMT_16_16_16_16_SNORM = 83,
193 TFMT_32_FLOAT = 84,
194 TFMT_32_32_FLOAT = 85,
195 TFMT_32_32_32_32_FLOAT = 87,
196 TFMT_32_UINT = 88,
197 TFMT_32_32_UINT = 89,
198 TFMT_32_32_32_32_UINT = 91,
199 TFMT_32_SINT = 92,
200 TFMT_32_32_SINT = 93,
201 TFMT_32_32_32_32_SINT = 95,
202 TFMT_2_10_10_10_UINT = 96,
203 TFMT_10_10_10_2_UINT = 97,
204 TFMT_ETC2_RG11_SNORM = 112,
205 TFMT_ETC2_RG11_UNORM = 113,
206 TFMT_ETC2_R11_SNORM = 114,
207 TFMT_ETC2_R11_UNORM = 115,
208 TFMT_ETC2_RGBA8 = 116,
209 TFMT_ETC2_RGB8A1 = 117,
210 TFMT_ETC2_RGB8 = 118,
211 };
212
213 enum a3xx_tex_fetchsize {
214 TFETCH_DISABLE = 0,
215 TFETCH_1_BYTE = 1,
216 TFETCH_2_BYTE = 2,
217 TFETCH_4_BYTE = 3,
218 TFETCH_8_BYTE = 4,
219 TFETCH_16_BYTE = 5,
220 };
221
222 enum a3xx_color_fmt {
223 RB_R5G6B5_UNORM = 0,
224 RB_R5G5B5A1_UNORM = 1,
225 RB_R4G4B4A4_UNORM = 3,
226 RB_R8G8B8_UNORM = 4,
227 RB_R8G8B8A8_UNORM = 8,
228 RB_R8G8B8A8_SNORM = 9,
229 RB_R8G8B8A8_UINT = 10,
230 RB_R8G8B8A8_SINT = 11,
231 RB_R8G8_UNORM = 12,
232 RB_R8G8_SNORM = 13,
233 RB_R8_UINT = 14,
234 RB_R8_SINT = 15,
235 RB_R10G10B10A2_UNORM = 16,
236 RB_A2R10G10B10_UNORM = 17,
237 RB_R10G10B10A2_UINT = 18,
238 RB_A2R10G10B10_UINT = 19,
239 RB_A8_UNORM = 20,
240 RB_R8_UNORM = 21,
241 RB_R16_FLOAT = 24,
242 RB_R16G16_FLOAT = 25,
243 RB_R16G16B16A16_FLOAT = 27,
244 RB_R11G11B10_FLOAT = 28,
245 RB_R16_SNORM = 32,
246 RB_R16G16_SNORM = 33,
247 RB_R16G16B16A16_SNORM = 35,
248 RB_R16_UNORM = 36,
249 RB_R16G16_UNORM = 37,
250 RB_R16G16B16A16_UNORM = 39,
251 RB_R16_SINT = 40,
252 RB_R16G16_SINT = 41,
253 RB_R16G16B16A16_SINT = 43,
254 RB_R16_UINT = 44,
255 RB_R16G16_UINT = 45,
256 RB_R16G16B16A16_UINT = 47,
257 RB_R32_FLOAT = 48,
258 RB_R32G32_FLOAT = 49,
259 RB_R32G32B32A32_FLOAT = 51,
260 RB_R32_SINT = 52,
261 RB_R32G32_SINT = 53,
262 RB_R32G32B32A32_SINT = 55,
263 RB_R32_UINT = 56,
264 RB_R32G32_UINT = 57,
265 RB_R32G32B32A32_UINT = 59,
266 };
267
268 enum a3xx_cp_perfcounter_select {
269 CP_ALWAYS_COUNT = 0,
270 CP_AHB_PFPTRANS_WAIT = 3,
271 CP_AHB_NRTTRANS_WAIT = 6,
272 CP_CSF_NRT_READ_WAIT = 8,
273 CP_CSF_I1_FIFO_FULL = 9,
274 CP_CSF_I2_FIFO_FULL = 10,
275 CP_CSF_ST_FIFO_FULL = 11,
276 CP_RESERVED_12 = 12,
277 CP_CSF_RING_ROQ_FULL = 13,
278 CP_CSF_I1_ROQ_FULL = 14,
279 CP_CSF_I2_ROQ_FULL = 15,
280 CP_CSF_ST_ROQ_FULL = 16,
281 CP_RESERVED_17 = 17,
282 CP_MIU_TAG_MEM_FULL = 18,
283 CP_MIU_NRT_WRITE_STALLED = 22,
284 CP_MIU_NRT_READ_STALLED = 23,
285 CP_ME_REGS_RB_DONE_FIFO_FULL = 26,
286 CP_ME_REGS_VS_EVENT_FIFO_FULL = 27,
287 CP_ME_REGS_PS_EVENT_FIFO_FULL = 28,
288 CP_ME_REGS_CF_EVENT_FIFO_FULL = 29,
289 CP_ME_MICRO_RB_STARVED = 30,
290 CP_AHB_RBBM_DWORD_SENT = 40,
291 CP_ME_BUSY_CLOCKS = 41,
292 CP_ME_WAIT_CONTEXT_AVAIL = 42,
293 CP_PFP_TYPE0_PACKET = 43,
294 CP_PFP_TYPE3_PACKET = 44,
295 CP_CSF_RB_WPTR_NEQ_RPTR = 45,
296 CP_CSF_I1_SIZE_NEQ_ZERO = 46,
297 CP_CSF_I2_SIZE_NEQ_ZERO = 47,
298 CP_CSF_RBI1I2_FETCHING = 48,
299 };
300
301 enum a3xx_gras_tse_perfcounter_select {
302 GRAS_TSEPERF_INPUT_PRIM = 0,
303 GRAS_TSEPERF_INPUT_NULL_PRIM = 1,
304 GRAS_TSEPERF_TRIVAL_REJ_PRIM = 2,
305 GRAS_TSEPERF_CLIPPED_PRIM = 3,
306 GRAS_TSEPERF_NEW_PRIM = 4,
307 GRAS_TSEPERF_ZERO_AREA_PRIM = 5,
308 GRAS_TSEPERF_FACENESS_CULLED_PRIM = 6,
309 GRAS_TSEPERF_ZERO_PIXEL_PRIM = 7,
310 GRAS_TSEPERF_OUTPUT_NULL_PRIM = 8,
311 GRAS_TSEPERF_OUTPUT_VISIBLE_PRIM = 9,
312 GRAS_TSEPERF_PRE_CLIP_PRIM = 10,
313 GRAS_TSEPERF_POST_CLIP_PRIM = 11,
314 GRAS_TSEPERF_WORKING_CYCLES = 12,
315 GRAS_TSEPERF_PC_STARVE = 13,
316 GRAS_TSERASPERF_STALL = 14,
317 };
318
319 enum a3xx_gras_ras_perfcounter_select {
320 GRAS_RASPERF_16X16_TILES = 0,
321 GRAS_RASPERF_8X8_TILES = 1,
322 GRAS_RASPERF_4X4_TILES = 2,
323 GRAS_RASPERF_WORKING_CYCLES = 3,
324 GRAS_RASPERF_STALL_CYCLES_BY_RB = 4,
325 GRAS_RASPERF_STALL_CYCLES_BY_VSC = 5,
326 GRAS_RASPERF_STARVE_CYCLES_BY_TSE = 6,
327 };
328
329 enum a3xx_hlsq_perfcounter_select {
330 HLSQ_PERF_SP_VS_CONSTANT = 0,
331 HLSQ_PERF_SP_VS_INSTRUCTIONS = 1,
332 HLSQ_PERF_SP_FS_CONSTANT = 2,
333 HLSQ_PERF_SP_FS_INSTRUCTIONS = 3,
334 HLSQ_PERF_TP_STATE = 4,
335 HLSQ_PERF_QUADS = 5,
336 HLSQ_PERF_PIXELS = 6,
337 HLSQ_PERF_VERTICES = 7,
338 HLSQ_PERF_FS8_THREADS = 8,
339 HLSQ_PERF_FS16_THREADS = 9,
340 HLSQ_PERF_FS32_THREADS = 10,
341 HLSQ_PERF_VS8_THREADS = 11,
342 HLSQ_PERF_VS16_THREADS = 12,
343 HLSQ_PERF_SP_VS_DATA_BYTES = 13,
344 HLSQ_PERF_SP_FS_DATA_BYTES = 14,
345 HLSQ_PERF_ACTIVE_CYCLES = 15,
346 HLSQ_PERF_STALL_CYCLES_SP_STATE = 16,
347 HLSQ_PERF_STALL_CYCLES_SP_VS = 17,
348 HLSQ_PERF_STALL_CYCLES_SP_FS = 18,
349 HLSQ_PERF_STALL_CYCLES_UCHE = 19,
350 HLSQ_PERF_RBBM_LOAD_CYCLES = 20,
351 HLSQ_PERF_DI_TO_VS_START_SP0 = 21,
352 HLSQ_PERF_DI_TO_FS_START_SP0 = 22,
353 HLSQ_PERF_VS_START_TO_DONE_SP0 = 23,
354 HLSQ_PERF_FS_START_TO_DONE_SP0 = 24,
355 HLSQ_PERF_SP_STATE_COPY_CYCLES_VS = 25,
356 HLSQ_PERF_SP_STATE_COPY_CYCLES_FS = 26,
357 HLSQ_PERF_UCHE_LATENCY_CYCLES = 27,
358 HLSQ_PERF_UCHE_LATENCY_COUNT = 28,
359 };
360
361 enum a3xx_pc_perfcounter_select {
362 PC_PCPERF_VISIBILITY_STREAMS = 0,
363 PC_PCPERF_TOTAL_INSTANCES = 1,
364 PC_PCPERF_PRIMITIVES_PC_VPC = 2,
365 PC_PCPERF_PRIMITIVES_KILLED_BY_VS = 3,
366 PC_PCPERF_PRIMITIVES_VISIBLE_BY_VS = 4,
367 PC_PCPERF_DRAWCALLS_KILLED_BY_VS = 5,
368 PC_PCPERF_DRAWCALLS_VISIBLE_BY_VS = 6,
369 PC_PCPERF_VERTICES_TO_VFD = 7,
370 PC_PCPERF_REUSED_VERTICES = 8,
371 PC_PCPERF_CYCLES_STALLED_BY_VFD = 9,
372 PC_PCPERF_CYCLES_STALLED_BY_TSE = 10,
373 PC_PCPERF_CYCLES_STALLED_BY_VBIF = 11,
374 PC_PCPERF_CYCLES_IS_WORKING = 12,
375 };
376
377 enum a3xx_rb_perfcounter_select {
378 RB_RBPERF_ACTIVE_CYCLES_ANY = 0,
379 RB_RBPERF_ACTIVE_CYCLES_ALL = 1,
380 RB_RBPERF_STARVE_CYCLES_BY_SP = 2,
381 RB_RBPERF_STARVE_CYCLES_BY_RAS = 3,
382 RB_RBPERF_STARVE_CYCLES_BY_MARB = 4,
383 RB_RBPERF_STALL_CYCLES_BY_MARB = 5,
384 RB_RBPERF_STALL_CYCLES_BY_HLSQ = 6,
385 RB_RBPERF_RB_MARB_DATA = 7,
386 RB_RBPERF_SP_RB_QUAD = 8,
387 RB_RBPERF_RAS_EARLY_Z_QUADS = 9,
388 RB_RBPERF_GMEM_CH0_READ = 10,
389 RB_RBPERF_GMEM_CH1_READ = 11,
390 RB_RBPERF_GMEM_CH0_WRITE = 12,
391 RB_RBPERF_GMEM_CH1_WRITE = 13,
392 RB_RBPERF_CP_CONTEXT_DONE = 14,
393 RB_RBPERF_CP_CACHE_FLUSH = 15,
394 RB_RBPERF_CP_ZPASS_DONE = 16,
395 };
396
397 enum a3xx_rbbm_perfcounter_select {
398 RBBM_ALAWYS_ON = 0,
399 RBBM_VBIF_BUSY = 1,
400 RBBM_TSE_BUSY = 2,
401 RBBM_RAS_BUSY = 3,
402 RBBM_PC_DCALL_BUSY = 4,
403 RBBM_PC_VSD_BUSY = 5,
404 RBBM_VFD_BUSY = 6,
405 RBBM_VPC_BUSY = 7,
406 RBBM_UCHE_BUSY = 8,
407 RBBM_VSC_BUSY = 9,
408 RBBM_HLSQ_BUSY = 10,
409 RBBM_ANY_RB_BUSY = 11,
410 RBBM_ANY_TEX_BUSY = 12,
411 RBBM_ANY_USP_BUSY = 13,
412 RBBM_ANY_MARB_BUSY = 14,
413 RBBM_ANY_ARB_BUSY = 15,
414 RBBM_AHB_STATUS_BUSY = 16,
415 RBBM_AHB_STATUS_STALLED = 17,
416 RBBM_AHB_STATUS_TXFR = 18,
417 RBBM_AHB_STATUS_TXFR_SPLIT = 19,
418 RBBM_AHB_STATUS_TXFR_ERROR = 20,
419 RBBM_AHB_STATUS_LONG_STALL = 21,
420 RBBM_RBBM_STATUS_MASKED = 22,
421 };
422
423 enum a3xx_sp_perfcounter_select {
424 SP_LM_LOAD_INSTRUCTIONS = 0,
425 SP_LM_STORE_INSTRUCTIONS = 1,
426 SP_LM_ATOMICS = 2,
427 SP_UCHE_LOAD_INSTRUCTIONS = 3,
428 SP_UCHE_STORE_INSTRUCTIONS = 4,
429 SP_UCHE_ATOMICS = 5,
430 SP_VS_TEX_INSTRUCTIONS = 6,
431 SP_VS_CFLOW_INSTRUCTIONS = 7,
432 SP_VS_EFU_INSTRUCTIONS = 8,
433 SP_VS_FULL_ALU_INSTRUCTIONS = 9,
434 SP_VS_HALF_ALU_INSTRUCTIONS = 10,
435 SP_FS_TEX_INSTRUCTIONS = 11,
436 SP_FS_CFLOW_INSTRUCTIONS = 12,
437 SP_FS_EFU_INSTRUCTIONS = 13,
438 SP_FS_FULL_ALU_INSTRUCTIONS = 14,
439 SP_FS_HALF_ALU_INSTRUCTIONS = 15,
440 SP_FS_BARY_INSTRUCTIONS = 16,
441 SP_VS_INSTRUCTIONS = 17,
442 SP_FS_INSTRUCTIONS = 18,
443 SP_ADDR_LOCK_COUNT = 19,
444 SP_UCHE_READ_TRANS = 20,
445 SP_UCHE_WRITE_TRANS = 21,
446 SP_EXPORT_VPC_TRANS = 22,
447 SP_EXPORT_RB_TRANS = 23,
448 SP_PIXELS_KILLED = 24,
449 SP_ICL1_REQUESTS = 25,
450 SP_ICL1_MISSES = 26,
451 SP_ICL0_REQUESTS = 27,
452 SP_ICL0_MISSES = 28,
453 SP_ALU_ACTIVE_CYCLES = 29,
454 SP_EFU_ACTIVE_CYCLES = 30,
455 SP_STALL_CYCLES_BY_VPC = 31,
456 SP_STALL_CYCLES_BY_TP = 32,
457 SP_STALL_CYCLES_BY_UCHE = 33,
458 SP_STALL_CYCLES_BY_RB = 34,
459 SP_ACTIVE_CYCLES_ANY = 35,
460 SP_ACTIVE_CYCLES_ALL = 36,
461 };
462
463 enum a3xx_tp_perfcounter_select {
464 TPL1_TPPERF_L1_REQUESTS = 0,
465 TPL1_TPPERF_TP0_L1_REQUESTS = 1,
466 TPL1_TPPERF_TP0_L1_MISSES = 2,
467 TPL1_TPPERF_TP1_L1_REQUESTS = 3,
468 TPL1_TPPERF_TP1_L1_MISSES = 4,
469 TPL1_TPPERF_TP2_L1_REQUESTS = 5,
470 TPL1_TPPERF_TP2_L1_MISSES = 6,
471 TPL1_TPPERF_TP3_L1_REQUESTS = 7,
472 TPL1_TPPERF_TP3_L1_MISSES = 8,
473 TPL1_TPPERF_OUTPUT_TEXELS_POINT = 9,
474 TPL1_TPPERF_OUTPUT_TEXELS_BILINEAR = 10,
475 TPL1_TPPERF_OUTPUT_TEXELS_MIP = 11,
476 TPL1_TPPERF_OUTPUT_TEXELS_ANISO = 12,
477 TPL1_TPPERF_BILINEAR_OPS = 13,
478 TPL1_TPPERF_QUADSQUADS_OFFSET = 14,
479 TPL1_TPPERF_QUADQUADS_SHADOW = 15,
480 TPL1_TPPERF_QUADS_ARRAY = 16,
481 TPL1_TPPERF_QUADS_PROJECTION = 17,
482 TPL1_TPPERF_QUADS_GRADIENT = 18,
483 TPL1_TPPERF_QUADS_1D2D = 19,
484 TPL1_TPPERF_QUADS_3DCUBE = 20,
485 TPL1_TPPERF_ZERO_LOD = 21,
486 TPL1_TPPERF_OUTPUT_TEXELS = 22,
487 TPL1_TPPERF_ACTIVE_CYCLES_ANY = 23,
488 TPL1_TPPERF_ACTIVE_CYCLES_ALL = 24,
489 TPL1_TPPERF_STALL_CYCLES_BY_ARB = 25,
490 TPL1_TPPERF_LATENCY = 26,
491 TPL1_TPPERF_LATENCY_TRANS = 27,
492 };
493
494 enum a3xx_vfd_perfcounter_select {
495 VFD_PERF_UCHE_BYTE_FETCHED = 0,
496 VFD_PERF_UCHE_TRANS = 1,
497 VFD_PERF_VPC_BYPASS_COMPONENTS = 2,
498 VFD_PERF_FETCH_INSTRUCTIONS = 3,
499 VFD_PERF_DECODE_INSTRUCTIONS = 4,
500 VFD_PERF_ACTIVE_CYCLES = 5,
501 VFD_PERF_STALL_CYCLES_UCHE = 6,
502 VFD_PERF_STALL_CYCLES_HLSQ = 7,
503 VFD_PERF_STALL_CYCLES_VPC_BYPASS = 8,
504 VFD_PERF_STALL_CYCLES_VPC_ALLOC = 9,
505 };
506
507 enum a3xx_vpc_perfcounter_select {
508 VPC_PERF_SP_LM_PRIMITIVES = 0,
509 VPC_PERF_COMPONENTS_FROM_SP = 1,
510 VPC_PERF_SP_LM_COMPONENTS = 2,
511 VPC_PERF_ACTIVE_CYCLES = 3,
512 VPC_PERF_STALL_CYCLES_LM = 4,
513 VPC_PERF_STALL_CYCLES_RAS = 5,
514 };
515
516 enum a3xx_uche_perfcounter_select {
517 UCHE_UCHEPERF_VBIF_READ_BEATS_TP = 0,
518 UCHE_UCHEPERF_VBIF_READ_BEATS_VFD = 1,
519 UCHE_UCHEPERF_VBIF_READ_BEATS_HLSQ = 2,
520 UCHE_UCHEPERF_VBIF_READ_BEATS_MARB = 3,
521 UCHE_UCHEPERF_VBIF_READ_BEATS_SP = 4,
522 UCHE_UCHEPERF_READ_REQUESTS_TP = 8,
523 UCHE_UCHEPERF_READ_REQUESTS_VFD = 9,
524 UCHE_UCHEPERF_READ_REQUESTS_HLSQ = 10,
525 UCHE_UCHEPERF_READ_REQUESTS_MARB = 11,
526 UCHE_UCHEPERF_READ_REQUESTS_SP = 12,
527 UCHE_UCHEPERF_WRITE_REQUESTS_MARB = 13,
528 UCHE_UCHEPERF_WRITE_REQUESTS_SP = 14,
529 UCHE_UCHEPERF_TAG_CHECK_FAILS = 15,
530 UCHE_UCHEPERF_EVICTS = 16,
531 UCHE_UCHEPERF_FLUSHES = 17,
532 UCHE_UCHEPERF_VBIF_LATENCY_CYCLES = 18,
533 UCHE_UCHEPERF_VBIF_LATENCY_SAMPLES = 19,
534 UCHE_UCHEPERF_ACTIVE_CYCLES = 20,
535 };
536
537 enum a3xx_intp_mode {
538 SMOOTH = 0,
539 FLAT = 1,
540 ZERO = 2,
541 ONE = 3,
542 };
543
544 enum a3xx_repl_mode {
545 S = 1,
546 T = 2,
547 ONE_T = 3,
548 };
549
550 enum a3xx_tex_filter {
551 A3XX_TEX_NEAREST = 0,
552 A3XX_TEX_LINEAR = 1,
553 A3XX_TEX_ANISO = 2,
554 };
555
556 enum a3xx_tex_clamp {
557 A3XX_TEX_REPEAT = 0,
558 A3XX_TEX_CLAMP_TO_EDGE = 1,
559 A3XX_TEX_MIRROR_REPEAT = 2,
560 A3XX_TEX_CLAMP_TO_BORDER = 3,
561 A3XX_TEX_MIRROR_CLAMP = 4,
562 };
563
564 enum a3xx_tex_aniso {
565 A3XX_TEX_ANISO_1 = 0,
566 A3XX_TEX_ANISO_2 = 1,
567 A3XX_TEX_ANISO_4 = 2,
568 A3XX_TEX_ANISO_8 = 3,
569 A3XX_TEX_ANISO_16 = 4,
570 };
571
572 enum a3xx_tex_swiz {
573 A3XX_TEX_X = 0,
574 A3XX_TEX_Y = 1,
575 A3XX_TEX_Z = 2,
576 A3XX_TEX_W = 3,
577 A3XX_TEX_ZERO = 4,
578 A3XX_TEX_ONE = 5,
579 };
580
581 enum a3xx_tex_type {
582 A3XX_TEX_1D = 0,
583 A3XX_TEX_2D = 1,
584 A3XX_TEX_CUBE = 2,
585 A3XX_TEX_3D = 3,
586 };
587
588 enum a3xx_tex_msaa {
589 A3XX_TPL1_MSAA1X = 0,
590 A3XX_TPL1_MSAA2X = 1,
591 A3XX_TPL1_MSAA4X = 2,
592 A3XX_TPL1_MSAA8X = 3,
593 };
594
595 #define A3XX_INT0_RBBM_GPU_IDLE 0x00000001
596 #define A3XX_INT0_RBBM_AHB_ERROR 0x00000002
597 #define A3XX_INT0_RBBM_REG_TIMEOUT 0x00000004
598 #define A3XX_INT0_RBBM_ME_MS_TIMEOUT 0x00000008
599 #define A3XX_INT0_RBBM_PFP_MS_TIMEOUT 0x00000010
600 #define A3XX_INT0_RBBM_ATB_BUS_OVERFLOW 0x00000020
601 #define A3XX_INT0_VFD_ERROR 0x00000040
602 #define A3XX_INT0_CP_SW_INT 0x00000080
603 #define A3XX_INT0_CP_T0_PACKET_IN_IB 0x00000100
604 #define A3XX_INT0_CP_OPCODE_ERROR 0x00000200
605 #define A3XX_INT0_CP_RESERVED_BIT_ERROR 0x00000400
606 #define A3XX_INT0_CP_HW_FAULT 0x00000800
607 #define A3XX_INT0_CP_DMA 0x00001000
608 #define A3XX_INT0_CP_IB2_INT 0x00002000
609 #define A3XX_INT0_CP_IB1_INT 0x00004000
610 #define A3XX_INT0_CP_RB_INT 0x00008000
611 #define A3XX_INT0_CP_REG_PROTECT_FAULT 0x00010000
612 #define A3XX_INT0_CP_RB_DONE_TS 0x00020000
613 #define A3XX_INT0_CP_VS_DONE_TS 0x00040000
614 #define A3XX_INT0_CP_PS_DONE_TS 0x00080000
615 #define A3XX_INT0_CACHE_FLUSH_TS 0x00100000
616 #define A3XX_INT0_CP_AHB_ERROR_HALT 0x00200000
617 #define A3XX_INT0_MISC_HANG_DETECT 0x01000000
618 #define A3XX_INT0_UCHE_OOB_ACCESS 0x02000000
619 #define REG_A3XX_RBBM_HW_VERSION 0x00000000
620
621 #define REG_A3XX_RBBM_HW_RELEASE 0x00000001
622
623 #define REG_A3XX_RBBM_HW_CONFIGURATION 0x00000002
624
625 #define REG_A3XX_RBBM_CLOCK_CTL 0x00000010
626
627 #define REG_A3XX_RBBM_SP_HYST_CNT 0x00000012
628
629 #define REG_A3XX_RBBM_SW_RESET_CMD 0x00000018
630
631 #define REG_A3XX_RBBM_AHB_CTL0 0x00000020
632
633 #define REG_A3XX_RBBM_AHB_CTL1 0x00000021
634
635 #define REG_A3XX_RBBM_AHB_CMD 0x00000022
636
637 #define REG_A3XX_RBBM_AHB_ERROR_STATUS 0x00000027
638
639 #define REG_A3XX_RBBM_GPR0_CTL 0x0000002e
640
641 #define REG_A3XX_RBBM_STATUS 0x00000030
642 #define A3XX_RBBM_STATUS_HI_BUSY 0x00000001
643 #define A3XX_RBBM_STATUS_CP_ME_BUSY 0x00000002
644 #define A3XX_RBBM_STATUS_CP_PFP_BUSY 0x00000004
645 #define A3XX_RBBM_STATUS_CP_NRT_BUSY 0x00004000
646 #define A3XX_RBBM_STATUS_VBIF_BUSY 0x00008000
647 #define A3XX_RBBM_STATUS_TSE_BUSY 0x00010000
648 #define A3XX_RBBM_STATUS_RAS_BUSY 0x00020000
649 #define A3XX_RBBM_STATUS_RB_BUSY 0x00040000
650 #define A3XX_RBBM_STATUS_PC_DCALL_BUSY 0x00080000
651 #define A3XX_RBBM_STATUS_PC_VSD_BUSY 0x00100000
652 #define A3XX_RBBM_STATUS_VFD_BUSY 0x00200000
653 #define A3XX_RBBM_STATUS_VPC_BUSY 0x00400000
654 #define A3XX_RBBM_STATUS_UCHE_BUSY 0x00800000
655 #define A3XX_RBBM_STATUS_SP_BUSY 0x01000000
656 #define A3XX_RBBM_STATUS_TPL1_BUSY 0x02000000
657 #define A3XX_RBBM_STATUS_MARB_BUSY 0x04000000
658 #define A3XX_RBBM_STATUS_VSC_BUSY 0x08000000
659 #define A3XX_RBBM_STATUS_ARB_BUSY 0x10000000
660 #define A3XX_RBBM_STATUS_HLSQ_BUSY 0x20000000
661 #define A3XX_RBBM_STATUS_GPU_BUSY_NOHC 0x40000000
662 #define A3XX_RBBM_STATUS_GPU_BUSY 0x80000000
663
664 #define REG_A3XX_RBBM_NQWAIT_UNTIL 0x00000040
665
666 #define REG_A3XX_RBBM_WAIT_IDLE_CLOCKS_CTL 0x00000033
667
668 #define REG_A3XX_RBBM_INTERFACE_HANG_INT_CTL 0x00000050
669
670 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL0 0x00000051
671
672 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL1 0x00000054
673
674 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL2 0x00000057
675
676 #define REG_A3XX_RBBM_INTERFACE_HANG_MASK_CTL3 0x0000005a
677
678 #define REG_A3XX_RBBM_INT_SET_CMD 0x00000060
679
680 #define REG_A3XX_RBBM_INT_CLEAR_CMD 0x00000061
681
682 #define REG_A3XX_RBBM_INT_0_MASK 0x00000063
683
684 #define REG_A3XX_RBBM_INT_0_STATUS 0x00000064
685
686 #define REG_A3XX_RBBM_PERFCTR_CTL 0x00000080
687 #define A3XX_RBBM_PERFCTR_CTL_ENABLE 0x00000001
688
689 #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD0 0x00000081
690
691 #define REG_A3XX_RBBM_PERFCTR_LOAD_CMD1 0x00000082
692
693 #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_LO 0x00000084
694
695 #define REG_A3XX_RBBM_PERFCTR_LOAD_VALUE_HI 0x00000085
696
697 #define REG_A3XX_RBBM_PERFCOUNTER0_SELECT 0x00000086
698
699 #define REG_A3XX_RBBM_PERFCOUNTER1_SELECT 0x00000087
700
701 #define REG_A3XX_RBBM_GPU_BUSY_MASKED 0x00000088
702
703 #define REG_A3XX_RBBM_PERFCTR_CP_0_LO 0x00000090
704
705 #define REG_A3XX_RBBM_PERFCTR_CP_0_HI 0x00000091
706
707 #define REG_A3XX_RBBM_PERFCTR_RBBM_0_LO 0x00000092
708
709 #define REG_A3XX_RBBM_PERFCTR_RBBM_0_HI 0x00000093
710
711 #define REG_A3XX_RBBM_PERFCTR_RBBM_1_LO 0x00000094
712
713 #define REG_A3XX_RBBM_PERFCTR_RBBM_1_HI 0x00000095
714
715 #define REG_A3XX_RBBM_PERFCTR_PC_0_LO 0x00000096
716
717 #define REG_A3XX_RBBM_PERFCTR_PC_0_HI 0x00000097
718
719 #define REG_A3XX_RBBM_PERFCTR_PC_1_LO 0x00000098
720
721 #define REG_A3XX_RBBM_PERFCTR_PC_1_HI 0x00000099
722
723 #define REG_A3XX_RBBM_PERFCTR_PC_2_LO 0x0000009a
724
725 #define REG_A3XX_RBBM_PERFCTR_PC_2_HI 0x0000009b
726
727 #define REG_A3XX_RBBM_PERFCTR_PC_3_LO 0x0000009c
728
729 #define REG_A3XX_RBBM_PERFCTR_PC_3_HI 0x0000009d
730
731 #define REG_A3XX_RBBM_PERFCTR_VFD_0_LO 0x0000009e
732
733 #define REG_A3XX_RBBM_PERFCTR_VFD_0_HI 0x0000009f
734
735 #define REG_A3XX_RBBM_PERFCTR_VFD_1_LO 0x000000a0
736
737 #define REG_A3XX_RBBM_PERFCTR_VFD_1_HI 0x000000a1
738
739 #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_LO 0x000000a2
740
741 #define REG_A3XX_RBBM_PERFCTR_HLSQ_0_HI 0x000000a3
742
743 #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_LO 0x000000a4
744
745 #define REG_A3XX_RBBM_PERFCTR_HLSQ_1_HI 0x000000a5
746
747 #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_LO 0x000000a6
748
749 #define REG_A3XX_RBBM_PERFCTR_HLSQ_2_HI 0x000000a7
750
751 #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_LO 0x000000a8
752
753 #define REG_A3XX_RBBM_PERFCTR_HLSQ_3_HI 0x000000a9
754
755 #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_LO 0x000000aa
756
757 #define REG_A3XX_RBBM_PERFCTR_HLSQ_4_HI 0x000000ab
758
759 #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_LO 0x000000ac
760
761 #define REG_A3XX_RBBM_PERFCTR_HLSQ_5_HI 0x000000ad
762
763 #define REG_A3XX_RBBM_PERFCTR_VPC_0_LO 0x000000ae
764
765 #define REG_A3XX_RBBM_PERFCTR_VPC_0_HI 0x000000af
766
767 #define REG_A3XX_RBBM_PERFCTR_VPC_1_LO 0x000000b0
768
769 #define REG_A3XX_RBBM_PERFCTR_VPC_1_HI 0x000000b1
770
771 #define REG_A3XX_RBBM_PERFCTR_TSE_0_LO 0x000000b2
772
773 #define REG_A3XX_RBBM_PERFCTR_TSE_0_HI 0x000000b3
774
775 #define REG_A3XX_RBBM_PERFCTR_TSE_1_LO 0x000000b4
776
777 #define REG_A3XX_RBBM_PERFCTR_TSE_1_HI 0x000000b5
778
779 #define REG_A3XX_RBBM_PERFCTR_RAS_0_LO 0x000000b6
780
781 #define REG_A3XX_RBBM_PERFCTR_RAS_0_HI 0x000000b7
782
783 #define REG_A3XX_RBBM_PERFCTR_RAS_1_LO 0x000000b8
784
785 #define REG_A3XX_RBBM_PERFCTR_RAS_1_HI 0x000000b9
786
787 #define REG_A3XX_RBBM_PERFCTR_UCHE_0_LO 0x000000ba
788
789 #define REG_A3XX_RBBM_PERFCTR_UCHE_0_HI 0x000000bb
790
791 #define REG_A3XX_RBBM_PERFCTR_UCHE_1_LO 0x000000bc
792
793 #define REG_A3XX_RBBM_PERFCTR_UCHE_1_HI 0x000000bd
794
795 #define REG_A3XX_RBBM_PERFCTR_UCHE_2_LO 0x000000be
796
797 #define REG_A3XX_RBBM_PERFCTR_UCHE_2_HI 0x000000bf
798
799 #define REG_A3XX_RBBM_PERFCTR_UCHE_3_LO 0x000000c0
800
801 #define REG_A3XX_RBBM_PERFCTR_UCHE_3_HI 0x000000c1
802
803 #define REG_A3XX_RBBM_PERFCTR_UCHE_4_LO 0x000000c2
804
805 #define REG_A3XX_RBBM_PERFCTR_UCHE_4_HI 0x000000c3
806
807 #define REG_A3XX_RBBM_PERFCTR_UCHE_5_LO 0x000000c4
808
809 #define REG_A3XX_RBBM_PERFCTR_UCHE_5_HI 0x000000c5
810
811 #define REG_A3XX_RBBM_PERFCTR_TP_0_LO 0x000000c6
812
813 #define REG_A3XX_RBBM_PERFCTR_TP_0_HI 0x000000c7
814
815 #define REG_A3XX_RBBM_PERFCTR_TP_1_LO 0x000000c8
816
817 #define REG_A3XX_RBBM_PERFCTR_TP_1_HI 0x000000c9
818
819 #define REG_A3XX_RBBM_PERFCTR_TP_2_LO 0x000000ca
820
821 #define REG_A3XX_RBBM_PERFCTR_TP_2_HI 0x000000cb
822
823 #define REG_A3XX_RBBM_PERFCTR_TP_3_LO 0x000000cc
824
825 #define REG_A3XX_RBBM_PERFCTR_TP_3_HI 0x000000cd
826
827 #define REG_A3XX_RBBM_PERFCTR_TP_4_LO 0x000000ce
828
829 #define REG_A3XX_RBBM_PERFCTR_TP_4_HI 0x000000cf
830
831 #define REG_A3XX_RBBM_PERFCTR_TP_5_LO 0x000000d0
832
833 #define REG_A3XX_RBBM_PERFCTR_TP_5_HI 0x000000d1
834
835 #define REG_A3XX_RBBM_PERFCTR_SP_0_LO 0x000000d2
836
837 #define REG_A3XX_RBBM_PERFCTR_SP_0_HI 0x000000d3
838
839 #define REG_A3XX_RBBM_PERFCTR_SP_1_LO 0x000000d4
840
841 #define REG_A3XX_RBBM_PERFCTR_SP_1_HI 0x000000d5
842
843 #define REG_A3XX_RBBM_PERFCTR_SP_2_LO 0x000000d6
844
845 #define REG_A3XX_RBBM_PERFCTR_SP_2_HI 0x000000d7
846
847 #define REG_A3XX_RBBM_PERFCTR_SP_3_LO 0x000000d8
848
849 #define REG_A3XX_RBBM_PERFCTR_SP_3_HI 0x000000d9
850
851 #define REG_A3XX_RBBM_PERFCTR_SP_4_LO 0x000000da
852
853 #define REG_A3XX_RBBM_PERFCTR_SP_4_HI 0x000000db
854
855 #define REG_A3XX_RBBM_PERFCTR_SP_5_LO 0x000000dc
856
857 #define REG_A3XX_RBBM_PERFCTR_SP_5_HI 0x000000dd
858
859 #define REG_A3XX_RBBM_PERFCTR_SP_6_LO 0x000000de
860
861 #define REG_A3XX_RBBM_PERFCTR_SP_6_HI 0x000000df
862
863 #define REG_A3XX_RBBM_PERFCTR_SP_7_LO 0x000000e0
864
865 #define REG_A3XX_RBBM_PERFCTR_SP_7_HI 0x000000e1
866
867 #define REG_A3XX_RBBM_PERFCTR_RB_0_LO 0x000000e2
868
869 #define REG_A3XX_RBBM_PERFCTR_RB_0_HI 0x000000e3
870
871 #define REG_A3XX_RBBM_PERFCTR_RB_1_LO 0x000000e4
872
873 #define REG_A3XX_RBBM_PERFCTR_RB_1_HI 0x000000e5
874
875 #define REG_A3XX_RBBM_PERFCTR_PWR_0_LO 0x000000ea
876
877 #define REG_A3XX_RBBM_PERFCTR_PWR_0_HI 0x000000eb
878
879 #define REG_A3XX_RBBM_PERFCTR_PWR_1_LO 0x000000ec
880
881 #define REG_A3XX_RBBM_PERFCTR_PWR_1_HI 0x000000ed
882
883 #define REG_A3XX_RBBM_RBBM_CTL 0x00000100
884
885 #define REG_A3XX_RBBM_DEBUG_BUS_CTL 0x00000111
886
887 #define REG_A3XX_RBBM_DEBUG_BUS_DATA_STATUS 0x00000112
888
889 #define REG_A3XX_CP_PFP_UCODE_ADDR 0x000001c9
890
891 #define REG_A3XX_CP_PFP_UCODE_DATA 0x000001ca
892
893 #define REG_A3XX_CP_ROQ_ADDR 0x000001cc
894
895 #define REG_A3XX_CP_ROQ_DATA 0x000001cd
896
897 #define REG_A3XX_CP_MERCIU_ADDR 0x000001d1
898
899 #define REG_A3XX_CP_MERCIU_DATA 0x000001d2
900
901 #define REG_A3XX_CP_MERCIU_DATA2 0x000001d3
902
903 #define REG_A3XX_CP_MEQ_ADDR 0x000001da
904
905 #define REG_A3XX_CP_MEQ_DATA 0x000001db
906
907 #define REG_A3XX_CP_WFI_PEND_CTR 0x000001f5
908
909 #define REG_A3XX_RBBM_PM_OVERRIDE2 0x0000039d
910
911 #define REG_A3XX_CP_PERFCOUNTER_SELECT 0x00000445
912
913 #define REG_A3XX_CP_HW_FAULT 0x0000045c
914
915 #define REG_A3XX_CP_PROTECT_CTRL 0x0000045e
916
917 #define REG_A3XX_CP_PROTECT_STATUS 0x0000045f
918
919 static inline uint32_t REG_A3XX_CP_PROTECT(uint32_t i0) { return 0x00000460 + 0x1*i0; }
920
921 static inline uint32_t REG_A3XX_CP_PROTECT_REG(uint32_t i0) { return 0x00000460 + 0x1*i0; }
922
923 #define REG_A3XX_CP_AHB_FAULT 0x0000054d
924
925 #define REG_A3XX_SQ_GPR_MANAGEMENT 0x00000d00
926
927 #define REG_A3XX_SQ_INST_STORE_MANAGMENT 0x00000d02
928
929 #define REG_A3XX_TP0_CHICKEN 0x00000e1e
930
931 #define REG_A3XX_SP_GLOBAL_MEM_SIZE 0x00000e22
932
933 #define REG_A3XX_SP_GLOBAL_MEM_ADDR 0x00000e23
934
935 #define REG_A3XX_GRAS_CL_CLIP_CNTL 0x00002040
936 #define A3XX_GRAS_CL_CLIP_CNTL_IJ_PERSP_CENTER 0x00001000
937 #define A3XX_GRAS_CL_CLIP_CNTL_CLIP_DISABLE 0x00010000
938 #define A3XX_GRAS_CL_CLIP_CNTL_ZFAR_CLIP_DISABLE 0x00020000
939 #define A3XX_GRAS_CL_CLIP_CNTL_VP_CLIP_CODE_IGNORE 0x00080000
940 #define A3XX_GRAS_CL_CLIP_CNTL_VP_XFORM_DISABLE 0x00100000
941 #define A3XX_GRAS_CL_CLIP_CNTL_PERSP_DIVISION_DISABLE 0x00200000
942 #define A3XX_GRAS_CL_CLIP_CNTL_ZERO_GB_SCALE_Z 0x00400000
943 #define A3XX_GRAS_CL_CLIP_CNTL_ZCOORD 0x00800000
944 #define A3XX_GRAS_CL_CLIP_CNTL_WCOORD 0x01000000
945 #define A3XX_GRAS_CL_CLIP_CNTL_ZCLIP_DISABLE 0x02000000
946 #define A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__MASK 0x1c000000
947 #define A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT 26
948 static inline uint32_t A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES(uint32_t val)
949 {
950 return ((val) << A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__SHIFT) & A3XX_GRAS_CL_CLIP_CNTL_NUM_USER_CLIP_PLANES__MASK;
951 }
952
953 #define REG_A3XX_GRAS_CL_GB_CLIP_ADJ 0x00002044
954 #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK 0x000003ff
955 #define A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT 0
956 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ(uint32_t val)
957 {
958 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_HORZ__MASK;
959 }
960 #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK 0x000ffc00
961 #define A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT 10
962 static inline uint32_t A3XX_GRAS_CL_GB_CLIP_ADJ_VERT(uint32_t val)
963 {
964 return ((val) << A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__SHIFT) & A3XX_GRAS_CL_GB_CLIP_ADJ_VERT__MASK;
965 }
966
967 #define REG_A3XX_GRAS_CL_VPORT_XOFFSET 0x00002048
968 #define A3XX_GRAS_CL_VPORT_XOFFSET__MASK 0xffffffff
969 #define A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT 0
970 static inline uint32_t A3XX_GRAS_CL_VPORT_XOFFSET(float val)
971 {
972 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_XOFFSET__MASK;
973 }
974
975 #define REG_A3XX_GRAS_CL_VPORT_XSCALE 0x00002049
976 #define A3XX_GRAS_CL_VPORT_XSCALE__MASK 0xffffffff
977 #define A3XX_GRAS_CL_VPORT_XSCALE__SHIFT 0
978 static inline uint32_t A3XX_GRAS_CL_VPORT_XSCALE(float val)
979 {
980 return ((fui(val)) << A3XX_GRAS_CL_VPORT_XSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_XSCALE__MASK;
981 }
982
983 #define REG_A3XX_GRAS_CL_VPORT_YOFFSET 0x0000204a
984 #define A3XX_GRAS_CL_VPORT_YOFFSET__MASK 0xffffffff
985 #define A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT 0
986 static inline uint32_t A3XX_GRAS_CL_VPORT_YOFFSET(float val)
987 {
988 return ((fui(val)) << A3XX_GRAS_CL_VPORT_YOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_YOFFSET__MASK;
989 }
990
991 #define REG_A3XX_GRAS_CL_VPORT_YSCALE 0x0000204b
992 #define A3XX_GRAS_CL_VPORT_YSCALE__MASK 0xffffffff
993 #define A3XX_GRAS_CL_VPORT_YSCALE__SHIFT 0
994 static inline uint32_t A3XX_GRAS_CL_VPORT_YSCALE(float val)
995 {
996 return ((fui(val)) << A3XX_GRAS_CL_VPORT_YSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_YSCALE__MASK;
997 }
998
999 #define REG_A3XX_GRAS_CL_VPORT_ZOFFSET 0x0000204c
1000 #define A3XX_GRAS_CL_VPORT_ZOFFSET__MASK 0xffffffff
1001 #define A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT 0
1002 static inline uint32_t A3XX_GRAS_CL_VPORT_ZOFFSET(float val)
1003 {
1004 return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZOFFSET__SHIFT) & A3XX_GRAS_CL_VPORT_ZOFFSET__MASK;
1005 }
1006
1007 #define REG_A3XX_GRAS_CL_VPORT_ZSCALE 0x0000204d
1008 #define A3XX_GRAS_CL_VPORT_ZSCALE__MASK 0xffffffff
1009 #define A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT 0
1010 static inline uint32_t A3XX_GRAS_CL_VPORT_ZSCALE(float val)
1011 {
1012 return ((fui(val)) << A3XX_GRAS_CL_VPORT_ZSCALE__SHIFT) & A3XX_GRAS_CL_VPORT_ZSCALE__MASK;
1013 }
1014
1015 #define REG_A3XX_GRAS_SU_POINT_MINMAX 0x00002068
1016 #define A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK 0x0000ffff
1017 #define A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT 0
1018 static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MIN(float val)
1019 {
1020 return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MIN__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MIN__MASK;
1021 }
1022 #define A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK 0xffff0000
1023 #define A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT 16
1024 static inline uint32_t A3XX_GRAS_SU_POINT_MINMAX_MAX(float val)
1025 {
1026 return ((((uint32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_MINMAX_MAX__SHIFT) & A3XX_GRAS_SU_POINT_MINMAX_MAX__MASK;
1027 }
1028
1029 #define REG_A3XX_GRAS_SU_POINT_SIZE 0x00002069
1030 #define A3XX_GRAS_SU_POINT_SIZE__MASK 0xffffffff
1031 #define A3XX_GRAS_SU_POINT_SIZE__SHIFT 0
1032 static inline uint32_t A3XX_GRAS_SU_POINT_SIZE(float val)
1033 {
1034 return ((((int32_t)(val * 16.0))) << A3XX_GRAS_SU_POINT_SIZE__SHIFT) & A3XX_GRAS_SU_POINT_SIZE__MASK;
1035 }
1036
1037 #define REG_A3XX_GRAS_SU_POLY_OFFSET_SCALE 0x0000206c
1038 #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK 0x00ffffff
1039 #define A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT 0
1040 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL(float val)
1041 {
1042 return ((((int32_t)(val * 1048576.0))) << A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_SCALE_VAL__MASK;
1043 }
1044
1045 #define REG_A3XX_GRAS_SU_POLY_OFFSET_OFFSET 0x0000206d
1046 #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK 0xffffffff
1047 #define A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT 0
1048 static inline uint32_t A3XX_GRAS_SU_POLY_OFFSET_OFFSET(float val)
1049 {
1050 return ((((int32_t)(val * 64.0))) << A3XX_GRAS_SU_POLY_OFFSET_OFFSET__SHIFT) & A3XX_GRAS_SU_POLY_OFFSET_OFFSET__MASK;
1051 }
1052
1053 #define REG_A3XX_GRAS_SU_MODE_CONTROL 0x00002070
1054 #define A3XX_GRAS_SU_MODE_CONTROL_CULL_FRONT 0x00000001
1055 #define A3XX_GRAS_SU_MODE_CONTROL_CULL_BACK 0x00000002
1056 #define A3XX_GRAS_SU_MODE_CONTROL_FRONT_CW 0x00000004
1057 #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK 0x000007f8
1058 #define A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT 3
1059 static inline uint32_t A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH(float val)
1060 {
1061 return ((((int32_t)(val * 4.0))) << A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__SHIFT) & A3XX_GRAS_SU_MODE_CONTROL_LINEHALFWIDTH__MASK;
1062 }
1063 #define A3XX_GRAS_SU_MODE_CONTROL_POLY_OFFSET 0x00000800
1064
1065 #define REG_A3XX_GRAS_SC_CONTROL 0x00002072
1066 #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK 0x000000f0
1067 #define A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT 4
1068 static inline uint32_t A3XX_GRAS_SC_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
1069 {
1070 return ((val) << A3XX_GRAS_SC_CONTROL_RENDER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RENDER_MODE__MASK;
1071 }
1072 #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK 0x00000f00
1073 #define A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT 8
1074 static inline uint32_t A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES(enum a3xx_msaa_samples val)
1075 {
1076 return ((val) << A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__SHIFT) & A3XX_GRAS_SC_CONTROL_MSAA_SAMPLES__MASK;
1077 }
1078 #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK 0x0000f000
1079 #define A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT 12
1080 static inline uint32_t A3XX_GRAS_SC_CONTROL_RASTER_MODE(uint32_t val)
1081 {
1082 return ((val) << A3XX_GRAS_SC_CONTROL_RASTER_MODE__SHIFT) & A3XX_GRAS_SC_CONTROL_RASTER_MODE__MASK;
1083 }
1084
1085 #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_TL 0x00002074
1086 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
1087 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK 0x00007fff
1088 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT 0
1089 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X(uint32_t val)
1090 {
1091 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_X__MASK;
1092 }
1093 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK 0x7fff0000
1094 #define A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT 16
1095 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y(uint32_t val)
1096 {
1097 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_TL_Y__MASK;
1098 }
1099
1100 #define REG_A3XX_GRAS_SC_SCREEN_SCISSOR_BR 0x00002075
1101 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
1102 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK 0x00007fff
1103 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT 0
1104 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X(uint32_t val)
1105 {
1106 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_X__MASK;
1107 }
1108 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK 0x7fff0000
1109 #define A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT 16
1110 static inline uint32_t A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y(uint32_t val)
1111 {
1112 return ((val) << A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_SCREEN_SCISSOR_BR_Y__MASK;
1113 }
1114
1115 #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_TL 0x00002079
1116 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_WINDOW_OFFSET_DISABLE 0x80000000
1117 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK 0x00007fff
1118 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT 0
1119 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X(uint32_t val)
1120 {
1121 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_X__MASK;
1122 }
1123 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK 0x7fff0000
1124 #define A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT 16
1125 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(uint32_t val)
1126 {
1127 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_TL_Y__MASK;
1128 }
1129
1130 #define REG_A3XX_GRAS_SC_WINDOW_SCISSOR_BR 0x0000207a
1131 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_WINDOW_OFFSET_DISABLE 0x80000000
1132 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK 0x00007fff
1133 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT 0
1134 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X(uint32_t val)
1135 {
1136 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_X__MASK;
1137 }
1138 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK 0x7fff0000
1139 #define A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT 16
1140 static inline uint32_t A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(uint32_t val)
1141 {
1142 return ((val) << A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__SHIFT) & A3XX_GRAS_SC_WINDOW_SCISSOR_BR_Y__MASK;
1143 }
1144
1145 #define REG_A3XX_RB_MODE_CONTROL 0x000020c0
1146 #define A3XX_RB_MODE_CONTROL_GMEM_BYPASS 0x00000080
1147 #define A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK 0x00000700
1148 #define A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT 8
1149 static inline uint32_t A3XX_RB_MODE_CONTROL_RENDER_MODE(enum a3xx_render_mode val)
1150 {
1151 return ((val) << A3XX_RB_MODE_CONTROL_RENDER_MODE__SHIFT) & A3XX_RB_MODE_CONTROL_RENDER_MODE__MASK;
1152 }
1153 #define A3XX_RB_MODE_CONTROL_MRT__MASK 0x00003000
1154 #define A3XX_RB_MODE_CONTROL_MRT__SHIFT 12
1155 static inline uint32_t A3XX_RB_MODE_CONTROL_MRT(uint32_t val)
1156 {
1157 return ((val) << A3XX_RB_MODE_CONTROL_MRT__SHIFT) & A3XX_RB_MODE_CONTROL_MRT__MASK;
1158 }
1159 #define A3XX_RB_MODE_CONTROL_MARB_CACHE_SPLIT_MODE 0x00008000
1160 #define A3XX_RB_MODE_CONTROL_PACKER_TIMER_ENABLE 0x00010000
1161
1162 #define REG_A3XX_RB_RENDER_CONTROL 0x000020c1
1163 #define A3XX_RB_RENDER_CONTROL_DUAL_COLOR_IN_ENABLE 0x00000001
1164 #define A3XX_RB_RENDER_CONTROL_YUV_IN_ENABLE 0x00000002
1165 #define A3XX_RB_RENDER_CONTROL_COV_VALUE_INPUT_ENABLE 0x00000004
1166 #define A3XX_RB_RENDER_CONTROL_FACENESS 0x00000008
1167 #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK 0x00000ff0
1168 #define A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT 4
1169 static inline uint32_t A3XX_RB_RENDER_CONTROL_BIN_WIDTH(uint32_t val)
1170 {
1171 assert(!(val & 0x1f));
1172 return ((val >> 5) << A3XX_RB_RENDER_CONTROL_BIN_WIDTH__SHIFT) & A3XX_RB_RENDER_CONTROL_BIN_WIDTH__MASK;
1173 }
1174 #define A3XX_RB_RENDER_CONTROL_DISABLE_COLOR_PIPE 0x00001000
1175 #define A3XX_RB_RENDER_CONTROL_ENABLE_GMEM 0x00002000
1176 #define A3XX_RB_RENDER_CONTROL_XCOORD 0x00004000
1177 #define A3XX_RB_RENDER_CONTROL_YCOORD 0x00008000
1178 #define A3XX_RB_RENDER_CONTROL_ZCOORD 0x00010000
1179 #define A3XX_RB_RENDER_CONTROL_WCOORD 0x00020000
1180 #define A3XX_RB_RENDER_CONTROL_I_CLAMP_ENABLE 0x00080000
1181 #define A3XX_RB_RENDER_CONTROL_COV_VALUE_OUTPUT_ENABLE 0x00100000
1182 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST 0x00400000
1183 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK 0x07000000
1184 #define A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT 24
1185 static inline uint32_t A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC(enum adreno_compare_func val)
1186 {
1187 return ((val) << A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__SHIFT) & A3XX_RB_RENDER_CONTROL_ALPHA_TEST_FUNC__MASK;
1188 }
1189 #define A3XX_RB_RENDER_CONTROL_ALPHA_TO_COVERAGE 0x40000000
1190 #define A3XX_RB_RENDER_CONTROL_ALPHA_TO_ONE 0x80000000
1191
1192 #define REG_A3XX_RB_MSAA_CONTROL 0x000020c2
1193 #define A3XX_RB_MSAA_CONTROL_DISABLE 0x00000400
1194 #define A3XX_RB_MSAA_CONTROL_SAMPLES__MASK 0x0000f000
1195 #define A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT 12
1196 static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLES(enum a3xx_msaa_samples val)
1197 {
1198 return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLES__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLES__MASK;
1199 }
1200 #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK 0xffff0000
1201 #define A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT 16
1202 static inline uint32_t A3XX_RB_MSAA_CONTROL_SAMPLE_MASK(uint32_t val)
1203 {
1204 return ((val) << A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__SHIFT) & A3XX_RB_MSAA_CONTROL_SAMPLE_MASK__MASK;
1205 }
1206
1207 #define REG_A3XX_RB_ALPHA_REF 0x000020c3
1208 #define A3XX_RB_ALPHA_REF_UINT__MASK 0x0000ff00
1209 #define A3XX_RB_ALPHA_REF_UINT__SHIFT 8
1210 static inline uint32_t A3XX_RB_ALPHA_REF_UINT(uint32_t val)
1211 {
1212 return ((val) << A3XX_RB_ALPHA_REF_UINT__SHIFT) & A3XX_RB_ALPHA_REF_UINT__MASK;
1213 }
1214 #define A3XX_RB_ALPHA_REF_FLOAT__MASK 0xffff0000
1215 #define A3XX_RB_ALPHA_REF_FLOAT__SHIFT 16
1216 static inline uint32_t A3XX_RB_ALPHA_REF_FLOAT(float val)
1217 {
1218 return ((util_float_to_half(val)) << A3XX_RB_ALPHA_REF_FLOAT__SHIFT) & A3XX_RB_ALPHA_REF_FLOAT__MASK;
1219 }
1220
1221 static inline uint32_t REG_A3XX_RB_MRT(uint32_t i0) { return 0x000020c4 + 0x4*i0; }
1222
1223 static inline uint32_t REG_A3XX_RB_MRT_CONTROL(uint32_t i0) { return 0x000020c4 + 0x4*i0; }
1224 #define A3XX_RB_MRT_CONTROL_READ_DEST_ENABLE 0x00000008
1225 #define A3XX_RB_MRT_CONTROL_BLEND 0x00000010
1226 #define A3XX_RB_MRT_CONTROL_BLEND2 0x00000020
1227 #define A3XX_RB_MRT_CONTROL_ROP_CODE__MASK 0x00000f00
1228 #define A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT 8
1229 static inline uint32_t A3XX_RB_MRT_CONTROL_ROP_CODE(enum a3xx_rop_code val)
1230 {
1231 return ((val) << A3XX_RB_MRT_CONTROL_ROP_CODE__SHIFT) & A3XX_RB_MRT_CONTROL_ROP_CODE__MASK;
1232 }
1233 #define A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK 0x00003000
1234 #define A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT 12
1235 static inline uint32_t A3XX_RB_MRT_CONTROL_DITHER_MODE(enum adreno_rb_dither_mode val)
1236 {
1237 return ((val) << A3XX_RB_MRT_CONTROL_DITHER_MODE__SHIFT) & A3XX_RB_MRT_CONTROL_DITHER_MODE__MASK;
1238 }
1239 #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK 0x0f000000
1240 #define A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT 24
1241 static inline uint32_t A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE(uint32_t val)
1242 {
1243 return ((val) << A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__SHIFT) & A3XX_RB_MRT_CONTROL_COMPONENT_ENABLE__MASK;
1244 }
1245
1246 static inline uint32_t REG_A3XX_RB_MRT_BUF_INFO(uint32_t i0) { return 0x000020c5 + 0x4*i0; }
1247 #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK 0x0000003f
1248 #define A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT 0
1249 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT(enum a3xx_color_fmt val)
1250 {
1251 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_FORMAT__MASK;
1252 }
1253 #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK 0x000000c0
1254 #define A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT 6
1255 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(enum a3xx_tile_mode val)
1256 {
1257 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE__MASK;
1258 }
1259 #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK 0x00000c00
1260 #define A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT 10
1261 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_SWAP(enum a3xx_color_swap val)
1262 {
1263 return ((val) << A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_SWAP__MASK;
1264 }
1265 #define A3XX_RB_MRT_BUF_INFO_COLOR_SRGB 0x00004000
1266 #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK 0xfffe0000
1267 #define A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT 17
1268 static inline uint32_t A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH(uint32_t val)
1269 {
1270 assert(!(val & 0x1f));
1271 return ((val >> 5) << A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__SHIFT) & A3XX_RB_MRT_BUF_INFO_COLOR_BUF_PITCH__MASK;
1272 }
1273
1274 static inline uint32_t REG_A3XX_RB_MRT_BUF_BASE(uint32_t i0) { return 0x000020c6 + 0x4*i0; }
1275 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK 0xfffffff0
1276 #define A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT 4
1277 static inline uint32_t A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE(uint32_t val)
1278 {
1279 assert(!(val & 0x1f));
1280 return ((val >> 5) << A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__SHIFT) & A3XX_RB_MRT_BUF_BASE_COLOR_BUF_BASE__MASK;
1281 }
1282
1283 static inline uint32_t REG_A3XX_RB_MRT_BLEND_CONTROL(uint32_t i0) { return 0x000020c7 + 0x4*i0; }
1284 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK 0x0000001f
1285 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT 0
1286 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR(enum adreno_rb_blend_factor val)
1287 {
1288 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_SRC_FACTOR__MASK;
1289 }
1290 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK 0x000000e0
1291 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT 5
1292 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
1293 {
1294 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_BLEND_OPCODE__MASK;
1295 }
1296 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK 0x00001f00
1297 #define A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT 8
1298 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR(enum adreno_rb_blend_factor val)
1299 {
1300 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_RGB_DEST_FACTOR__MASK;
1301 }
1302 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK 0x001f0000
1303 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT 16
1304 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR(enum adreno_rb_blend_factor val)
1305 {
1306 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_SRC_FACTOR__MASK;
1307 }
1308 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK 0x00e00000
1309 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT 21
1310 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE(enum a3xx_rb_blend_opcode val)
1311 {
1312 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_BLEND_OPCODE__MASK;
1313 }
1314 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK 0x1f000000
1315 #define A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT 24
1316 static inline uint32_t A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR(enum adreno_rb_blend_factor val)
1317 {
1318 return ((val) << A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__SHIFT) & A3XX_RB_MRT_BLEND_CONTROL_ALPHA_DEST_FACTOR__MASK;
1319 }
1320 #define A3XX_RB_MRT_BLEND_CONTROL_CLAMP_ENABLE 0x20000000
1321
1322 #define REG_A3XX_RB_BLEND_RED 0x000020e4
1323 #define A3XX_RB_BLEND_RED_UINT__MASK 0x000000ff
1324 #define A3XX_RB_BLEND_RED_UINT__SHIFT 0
1325 static inline uint32_t A3XX_RB_BLEND_RED_UINT(uint32_t val)
1326 {
1327 return ((val) << A3XX_RB_BLEND_RED_UINT__SHIFT) & A3XX_RB_BLEND_RED_UINT__MASK;
1328 }
1329 #define A3XX_RB_BLEND_RED_FLOAT__MASK 0xffff0000
1330 #define A3XX_RB_BLEND_RED_FLOAT__SHIFT 16
1331 static inline uint32_t A3XX_RB_BLEND_RED_FLOAT(float val)
1332 {
1333 return ((util_float_to_half(val)) << A3XX_RB_BLEND_RED_FLOAT__SHIFT) & A3XX_RB_BLEND_RED_FLOAT__MASK;
1334 }
1335
1336 #define REG_A3XX_RB_BLEND_GREEN 0x000020e5
1337 #define A3XX_RB_BLEND_GREEN_UINT__MASK 0x000000ff
1338 #define A3XX_RB_BLEND_GREEN_UINT__SHIFT 0
1339 static inline uint32_t A3XX_RB_BLEND_GREEN_UINT(uint32_t val)
1340 {
1341 return ((val) << A3XX_RB_BLEND_GREEN_UINT__SHIFT) & A3XX_RB_BLEND_GREEN_UINT__MASK;
1342 }
1343 #define A3XX_RB_BLEND_GREEN_FLOAT__MASK 0xffff0000
1344 #define A3XX_RB_BLEND_GREEN_FLOAT__SHIFT 16
1345 static inline uint32_t A3XX_RB_BLEND_GREEN_FLOAT(float val)
1346 {
1347 return ((util_float_to_half(val)) << A3XX_RB_BLEND_GREEN_FLOAT__SHIFT) & A3XX_RB_BLEND_GREEN_FLOAT__MASK;
1348 }
1349
1350 #define REG_A3XX_RB_BLEND_BLUE 0x000020e6
1351 #define A3XX_RB_BLEND_BLUE_UINT__MASK 0x000000ff
1352 #define A3XX_RB_BLEND_BLUE_UINT__SHIFT 0
1353 static inline uint32_t A3XX_RB_BLEND_BLUE_UINT(uint32_t val)
1354 {
1355 return ((val) << A3XX_RB_BLEND_BLUE_UINT__SHIFT) & A3XX_RB_BLEND_BLUE_UINT__MASK;
1356 }
1357 #define A3XX_RB_BLEND_BLUE_FLOAT__MASK 0xffff0000
1358 #define A3XX_RB_BLEND_BLUE_FLOAT__SHIFT 16
1359 static inline uint32_t A3XX_RB_BLEND_BLUE_FLOAT(float val)
1360 {
1361 return ((util_float_to_half(val)) << A3XX_RB_BLEND_BLUE_FLOAT__SHIFT) & A3XX_RB_BLEND_BLUE_FLOAT__MASK;
1362 }
1363
1364 #define REG_A3XX_RB_BLEND_ALPHA 0x000020e7
1365 #define A3XX_RB_BLEND_ALPHA_UINT__MASK 0x000000ff
1366 #define A3XX_RB_BLEND_ALPHA_UINT__SHIFT 0
1367 static inline uint32_t A3XX_RB_BLEND_ALPHA_UINT(uint32_t val)
1368 {
1369 return ((val) << A3XX_RB_BLEND_ALPHA_UINT__SHIFT) & A3XX_RB_BLEND_ALPHA_UINT__MASK;
1370 }
1371 #define A3XX_RB_BLEND_ALPHA_FLOAT__MASK 0xffff0000
1372 #define A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT 16
1373 static inline uint32_t A3XX_RB_BLEND_ALPHA_FLOAT(float val)
1374 {
1375 return ((util_float_to_half(val)) << A3XX_RB_BLEND_ALPHA_FLOAT__SHIFT) & A3XX_RB_BLEND_ALPHA_FLOAT__MASK;
1376 }
1377
1378 #define REG_A3XX_RB_CLEAR_COLOR_DW0 0x000020e8
1379
1380 #define REG_A3XX_RB_CLEAR_COLOR_DW1 0x000020e9
1381
1382 #define REG_A3XX_RB_CLEAR_COLOR_DW2 0x000020ea
1383
1384 #define REG_A3XX_RB_CLEAR_COLOR_DW3 0x000020eb
1385
1386 #define REG_A3XX_RB_COPY_CONTROL 0x000020ec
1387 #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK 0x00000003
1388 #define A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT 0
1389 static inline uint32_t A3XX_RB_COPY_CONTROL_MSAA_RESOLVE(enum a3xx_msaa_samples val)
1390 {
1391 return ((val) << A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__SHIFT) & A3XX_RB_COPY_CONTROL_MSAA_RESOLVE__MASK;
1392 }
1393 #define A3XX_RB_COPY_CONTROL_DEPTHCLEAR 0x00000008
1394 #define A3XX_RB_COPY_CONTROL_MODE__MASK 0x00000070
1395 #define A3XX_RB_COPY_CONTROL_MODE__SHIFT 4
1396 static inline uint32_t A3XX_RB_COPY_CONTROL_MODE(enum adreno_rb_copy_control_mode val)
1397 {
1398 return ((val) << A3XX_RB_COPY_CONTROL_MODE__SHIFT) & A3XX_RB_COPY_CONTROL_MODE__MASK;
1399 }
1400 #define A3XX_RB_COPY_CONTROL_MSAA_SRGB_DOWNSAMPLE 0x00000080
1401 #define A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK 0x00000f00
1402 #define A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT 8
1403 static inline uint32_t A3XX_RB_COPY_CONTROL_FASTCLEAR(uint32_t val)
1404 {
1405 return ((val) << A3XX_RB_COPY_CONTROL_FASTCLEAR__SHIFT) & A3XX_RB_COPY_CONTROL_FASTCLEAR__MASK;
1406 }
1407 #define A3XX_RB_COPY_CONTROL_DEPTH32_RESOLVE 0x00001000
1408 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK 0xffffc000
1409 #define A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT 14
1410 static inline uint32_t A3XX_RB_COPY_CONTROL_GMEM_BASE(uint32_t val)
1411 {
1412 assert(!(val & 0x3fff));
1413 return ((val >> 14) << A3XX_RB_COPY_CONTROL_GMEM_BASE__SHIFT) & A3XX_RB_COPY_CONTROL_GMEM_BASE__MASK;
1414 }
1415
1416 #define REG_A3XX_RB_COPY_DEST_BASE 0x000020ed
1417 #define A3XX_RB_COPY_DEST_BASE_BASE__MASK 0xfffffff0
1418 #define A3XX_RB_COPY_DEST_BASE_BASE__SHIFT 4
1419 static inline uint32_t A3XX_RB_COPY_DEST_BASE_BASE(uint32_t val)
1420 {
1421 assert(!(val & 0x1f));
1422 return ((val >> 5) << A3XX_RB_COPY_DEST_BASE_BASE__SHIFT) & A3XX_RB_COPY_DEST_BASE_BASE__MASK;
1423 }
1424
1425 #define REG_A3XX_RB_COPY_DEST_PITCH 0x000020ee
1426 #define A3XX_RB_COPY_DEST_PITCH_PITCH__MASK 0xffffffff
1427 #define A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT 0
1428 static inline uint32_t A3XX_RB_COPY_DEST_PITCH_PITCH(uint32_t val)
1429 {
1430 assert(!(val & 0x1f));
1431 return ((val >> 5) << A3XX_RB_COPY_DEST_PITCH_PITCH__SHIFT) & A3XX_RB_COPY_DEST_PITCH_PITCH__MASK;
1432 }
1433
1434 #define REG_A3XX_RB_COPY_DEST_INFO 0x000020ef
1435 #define A3XX_RB_COPY_DEST_INFO_TILE__MASK 0x00000003
1436 #define A3XX_RB_COPY_DEST_INFO_TILE__SHIFT 0
1437 static inline uint32_t A3XX_RB_COPY_DEST_INFO_TILE(enum a3xx_tile_mode val)
1438 {
1439 return ((val) << A3XX_RB_COPY_DEST_INFO_TILE__SHIFT) & A3XX_RB_COPY_DEST_INFO_TILE__MASK;
1440 }
1441 #define A3XX_RB_COPY_DEST_INFO_FORMAT__MASK 0x000000fc
1442 #define A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT 2
1443 static inline uint32_t A3XX_RB_COPY_DEST_INFO_FORMAT(enum a3xx_color_fmt val)
1444 {
1445 return ((val) << A3XX_RB_COPY_DEST_INFO_FORMAT__SHIFT) & A3XX_RB_COPY_DEST_INFO_FORMAT__MASK;
1446 }
1447 #define A3XX_RB_COPY_DEST_INFO_SWAP__MASK 0x00000300
1448 #define A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT 8
1449 static inline uint32_t A3XX_RB_COPY_DEST_INFO_SWAP(enum a3xx_color_swap val)
1450 {
1451 return ((val) << A3XX_RB_COPY_DEST_INFO_SWAP__SHIFT) & A3XX_RB_COPY_DEST_INFO_SWAP__MASK;
1452 }
1453 #define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK 0x00000c00
1454 #define A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT 10
1455 static inline uint32_t A3XX_RB_COPY_DEST_INFO_DITHER_MODE(enum adreno_rb_dither_mode val)
1456 {
1457 return ((val) << A3XX_RB_COPY_DEST_INFO_DITHER_MODE__SHIFT) & A3XX_RB_COPY_DEST_INFO_DITHER_MODE__MASK;
1458 }
1459 #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK 0x0003c000
1460 #define A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT 14
1461 static inline uint32_t A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE(uint32_t val)
1462 {
1463 return ((val) << A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__SHIFT) & A3XX_RB_COPY_DEST_INFO_COMPONENT_ENABLE__MASK;
1464 }
1465 #define A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK 0x001c0000
1466 #define A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT 18
1467 static inline uint32_t A3XX_RB_COPY_DEST_INFO_ENDIAN(enum adreno_rb_surface_endian val)
1468 {
1469 return ((val) << A3XX_RB_COPY_DEST_INFO_ENDIAN__SHIFT) & A3XX_RB_COPY_DEST_INFO_ENDIAN__MASK;
1470 }
1471
1472 #define REG_A3XX_RB_DEPTH_CONTROL 0x00002100
1473 #define A3XX_RB_DEPTH_CONTROL_FRAG_WRITES_Z 0x00000001
1474 #define A3XX_RB_DEPTH_CONTROL_Z_ENABLE 0x00000002
1475 #define A3XX_RB_DEPTH_CONTROL_Z_WRITE_ENABLE 0x00000004
1476 #define A3XX_RB_DEPTH_CONTROL_EARLY_Z_DISABLE 0x00000008
1477 #define A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK 0x00000070
1478 #define A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT 4
1479 static inline uint32_t A3XX_RB_DEPTH_CONTROL_ZFUNC(enum adreno_compare_func val)
1480 {
1481 return ((val) << A3XX_RB_DEPTH_CONTROL_ZFUNC__SHIFT) & A3XX_RB_DEPTH_CONTROL_ZFUNC__MASK;
1482 }
1483 #define A3XX_RB_DEPTH_CONTROL_Z_CLAMP_ENABLE 0x00000080
1484 #define A3XX_RB_DEPTH_CONTROL_Z_TEST_ENABLE 0x80000000
1485
1486 #define REG_A3XX_RB_DEPTH_CLEAR 0x00002101
1487
1488 #define REG_A3XX_RB_DEPTH_INFO 0x00002102
1489 #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK 0x00000003
1490 #define A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT 0
1491 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_FORMAT(enum adreno_rb_depth_format val)
1492 {
1493 return ((val) << A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_FORMAT__MASK;
1494 }
1495 #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK 0xfffff800
1496 #define A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT 11
1497 static inline uint32_t A3XX_RB_DEPTH_INFO_DEPTH_BASE(uint32_t val)
1498 {
1499 assert(!(val & 0xfff));
1500 return ((val >> 12) << A3XX_RB_DEPTH_INFO_DEPTH_BASE__SHIFT) & A3XX_RB_DEPTH_INFO_DEPTH_BASE__MASK;
1501 }
1502
1503 #define REG_A3XX_RB_DEPTH_PITCH 0x00002103
1504 #define A3XX_RB_DEPTH_PITCH__MASK 0xffffffff
1505 #define A3XX_RB_DEPTH_PITCH__SHIFT 0
1506 static inline uint32_t A3XX_RB_DEPTH_PITCH(uint32_t val)
1507 {
1508 assert(!(val & 0x7));
1509 return ((val >> 3) << A3XX_RB_DEPTH_PITCH__SHIFT) & A3XX_RB_DEPTH_PITCH__MASK;
1510 }
1511
1512 #define REG_A3XX_RB_STENCIL_CONTROL 0x00002104
1513 #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE 0x00000001
1514 #define A3XX_RB_STENCIL_CONTROL_STENCIL_ENABLE_BF 0x00000002
1515 #define A3XX_RB_STENCIL_CONTROL_STENCIL_READ 0x00000004
1516 #define A3XX_RB_STENCIL_CONTROL_FUNC__MASK 0x00000700
1517 #define A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT 8
1518 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC(enum adreno_compare_func val)
1519 {
1520 return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC__MASK;
1521 }
1522 #define A3XX_RB_STENCIL_CONTROL_FAIL__MASK 0x00003800
1523 #define A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT 11
1524 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL(enum adreno_stencil_op val)
1525 {
1526 return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL__MASK;
1527 }
1528 #define A3XX_RB_STENCIL_CONTROL_ZPASS__MASK 0x0001c000
1529 #define A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT 14
1530 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS(enum adreno_stencil_op val)
1531 {
1532 return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS__MASK;
1533 }
1534 #define A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK 0x000e0000
1535 #define A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT 17
1536 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL(enum adreno_stencil_op val)
1537 {
1538 return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL__MASK;
1539 }
1540 #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK 0x00700000
1541 #define A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT 20
1542 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FUNC_BF(enum adreno_compare_func val)
1543 {
1544 return ((val) << A3XX_RB_STENCIL_CONTROL_FUNC_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FUNC_BF__MASK;
1545 }
1546 #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK 0x03800000
1547 #define A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT 23
1548 static inline uint32_t A3XX_RB_STENCIL_CONTROL_FAIL_BF(enum adreno_stencil_op val)
1549 {
1550 return ((val) << A3XX_RB_STENCIL_CONTROL_FAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_FAIL_BF__MASK;
1551 }
1552 #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK 0x1c000000
1553 #define A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT 26
1554 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZPASS_BF(enum adreno_stencil_op val)
1555 {
1556 return ((val) << A3XX_RB_STENCIL_CONTROL_ZPASS_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZPASS_BF__MASK;
1557 }
1558 #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK 0xe0000000
1559 #define A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT 29
1560 static inline uint32_t A3XX_RB_STENCIL_CONTROL_ZFAIL_BF(enum adreno_stencil_op val)
1561 {
1562 return ((val) << A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__SHIFT) & A3XX_RB_STENCIL_CONTROL_ZFAIL_BF__MASK;
1563 }
1564
1565 #define REG_A3XX_RB_STENCIL_CLEAR 0x00002105
1566
1567 #define REG_A3XX_RB_STENCIL_INFO 0x00002106
1568 #define A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK 0xfffff800
1569 #define A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT 11
1570 static inline uint32_t A3XX_RB_STENCIL_INFO_STENCIL_BASE(uint32_t val)
1571 {
1572 assert(!(val & 0xfff));
1573 return ((val >> 12) << A3XX_RB_STENCIL_INFO_STENCIL_BASE__SHIFT) & A3XX_RB_STENCIL_INFO_STENCIL_BASE__MASK;
1574 }
1575
1576 #define REG_A3XX_RB_STENCIL_PITCH 0x00002107
1577 #define A3XX_RB_STENCIL_PITCH__MASK 0xffffffff
1578 #define A3XX_RB_STENCIL_PITCH__SHIFT 0
1579 static inline uint32_t A3XX_RB_STENCIL_PITCH(uint32_t val)
1580 {
1581 assert(!(val & 0x7));
1582 return ((val >> 3) << A3XX_RB_STENCIL_PITCH__SHIFT) & A3XX_RB_STENCIL_PITCH__MASK;
1583 }
1584
1585 #define REG_A3XX_RB_STENCILREFMASK 0x00002108
1586 #define A3XX_RB_STENCILREFMASK_STENCILREF__MASK 0x000000ff
1587 #define A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT 0
1588 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILREF(uint32_t val)
1589 {
1590 return ((val) << A3XX_RB_STENCILREFMASK_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILREF__MASK;
1591 }
1592 #define A3XX_RB_STENCILREFMASK_STENCILMASK__MASK 0x0000ff00
1593 #define A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT 8
1594 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILMASK(uint32_t val)
1595 {
1596 return ((val) << A3XX_RB_STENCILREFMASK_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILMASK__MASK;
1597 }
1598 #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK 0x00ff0000
1599 #define A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT 16
1600 static inline uint32_t A3XX_RB_STENCILREFMASK_STENCILWRITEMASK(uint32_t val)
1601 {
1602 return ((val) << A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_STENCILWRITEMASK__MASK;
1603 }
1604
1605 #define REG_A3XX_RB_STENCILREFMASK_BF 0x00002109
1606 #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK 0x000000ff
1607 #define A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT 0
1608 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILREF(uint32_t val)
1609 {
1610 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILREF__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILREF__MASK;
1611 }
1612 #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK 0x0000ff00
1613 #define A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT 8
1614 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILMASK(uint32_t val)
1615 {
1616 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILMASK__MASK;
1617 }
1618 #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK 0x00ff0000
1619 #define A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT 16
1620 static inline uint32_t A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK(uint32_t val)
1621 {
1622 return ((val) << A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__SHIFT) & A3XX_RB_STENCILREFMASK_BF_STENCILWRITEMASK__MASK;
1623 }
1624
1625 #define REG_A3XX_RB_LRZ_VSC_CONTROL 0x0000210c
1626 #define A3XX_RB_LRZ_VSC_CONTROL_BINNING_ENABLE 0x00000002
1627
1628 #define REG_A3XX_RB_WINDOW_OFFSET 0x0000210e
1629 #define A3XX_RB_WINDOW_OFFSET_X__MASK 0x0000ffff
1630 #define A3XX_RB_WINDOW_OFFSET_X__SHIFT 0
1631 static inline uint32_t A3XX_RB_WINDOW_OFFSET_X(uint32_t val)
1632 {
1633 return ((val) << A3XX_RB_WINDOW_OFFSET_X__SHIFT) & A3XX_RB_WINDOW_OFFSET_X__MASK;
1634 }
1635 #define A3XX_RB_WINDOW_OFFSET_Y__MASK 0xffff0000
1636 #define A3XX_RB_WINDOW_OFFSET_Y__SHIFT 16
1637 static inline uint32_t A3XX_RB_WINDOW_OFFSET_Y(uint32_t val)
1638 {
1639 return ((val) << A3XX_RB_WINDOW_OFFSET_Y__SHIFT) & A3XX_RB_WINDOW_OFFSET_Y__MASK;
1640 }
1641
1642 #define REG_A3XX_RB_SAMPLE_COUNT_CONTROL 0x00002110
1643 #define A3XX_RB_SAMPLE_COUNT_CONTROL_RESET 0x00000001
1644 #define A3XX_RB_SAMPLE_COUNT_CONTROL_COPY 0x00000002
1645
1646 #define REG_A3XX_RB_SAMPLE_COUNT_ADDR 0x00002111
1647
1648 #define REG_A3XX_RB_Z_CLAMP_MIN 0x00002114
1649
1650 #define REG_A3XX_RB_Z_CLAMP_MAX 0x00002115
1651
1652 #define REG_A3XX_VGT_BIN_BASE 0x000021e1
1653
1654 #define REG_A3XX_VGT_BIN_SIZE 0x000021e2
1655
1656 #define REG_A3XX_PC_VSTREAM_CONTROL 0x000021e4
1657 #define A3XX_PC_VSTREAM_CONTROL_SIZE__MASK 0x003f0000
1658 #define A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT 16
1659 static inline uint32_t A3XX_PC_VSTREAM_CONTROL_SIZE(uint32_t val)
1660 {
1661 return ((val) << A3XX_PC_VSTREAM_CONTROL_SIZE__SHIFT) & A3XX_PC_VSTREAM_CONTROL_SIZE__MASK;
1662 }
1663 #define A3XX_PC_VSTREAM_CONTROL_N__MASK 0x07c00000
1664 #define A3XX_PC_VSTREAM_CONTROL_N__SHIFT 22
1665 static inline uint32_t A3XX_PC_VSTREAM_CONTROL_N(uint32_t val)
1666 {
1667 return ((val) << A3XX_PC_VSTREAM_CONTROL_N__SHIFT) & A3XX_PC_VSTREAM_CONTROL_N__MASK;
1668 }
1669
1670 #define REG_A3XX_PC_VERTEX_REUSE_BLOCK_CNTL 0x000021ea
1671
1672 #define REG_A3XX_PC_PRIM_VTX_CNTL 0x000021ec
1673 #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK 0x0000001f
1674 #define A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT 0
1675 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC(uint32_t val)
1676 {
1677 return ((val) << A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_STRIDE_IN_VPC__MASK;
1678 }
1679 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK 0x000000e0
1680 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT 5
1681 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE(enum adreno_pa_su_sc_draw val)
1682 {
1683 return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_FRONT_PTYPE__MASK;
1684 }
1685 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK 0x00000700
1686 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT 8
1687 static inline uint32_t A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE(enum adreno_pa_su_sc_draw val)
1688 {
1689 return ((val) << A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__SHIFT) & A3XX_PC_PRIM_VTX_CNTL_POLYMODE_BACK_PTYPE__MASK;
1690 }
1691 #define A3XX_PC_PRIM_VTX_CNTL_POLYMODE_ENABLE 0x00001000
1692 #define A3XX_PC_PRIM_VTX_CNTL_PRIMITIVE_RESTART 0x00100000
1693 #define A3XX_PC_PRIM_VTX_CNTL_PROVOKING_VTX_LAST 0x02000000
1694 #define A3XX_PC_PRIM_VTX_CNTL_PSIZE 0x04000000
1695
1696 #define REG_A3XX_PC_RESTART_INDEX 0x000021ed
1697
1698 #define REG_A3XX_HLSQ_CONTROL_0_REG 0x00002200
1699 #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK 0x00000030
1700 #define A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT 4
1701 static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE(enum a3xx_threadsize val)
1702 {
1703 return ((val) << A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_FSTHREADSIZE__MASK;
1704 }
1705 #define A3XX_HLSQ_CONTROL_0_REG_FSSUPERTHREADENABLE 0x00000040
1706 #define A3XX_HLSQ_CONTROL_0_REG_COMPUTEMODE 0x00000100
1707 #define A3XX_HLSQ_CONTROL_0_REG_SPSHADERRESTART 0x00000200
1708 #define A3XX_HLSQ_CONTROL_0_REG_RESERVED2 0x00000400
1709 #define A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__MASK 0x00fff000
1710 #define A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__SHIFT 12
1711 static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC(uint32_t val)
1712 {
1713 return ((val) << A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CYCLETIMEOUTLIMITVPC__MASK;
1714 }
1715 #define A3XX_HLSQ_CONTROL_0_REG_FSONLYTEX 0x02000000
1716 #define A3XX_HLSQ_CONTROL_0_REG_CHUNKDISABLE 0x04000000
1717 #define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK 0x08000000
1718 #define A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT 27
1719 static inline uint32_t A3XX_HLSQ_CONTROL_0_REG_CONSTMODE(uint32_t val)
1720 {
1721 return ((val) << A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__SHIFT) & A3XX_HLSQ_CONTROL_0_REG_CONSTMODE__MASK;
1722 }
1723 #define A3XX_HLSQ_CONTROL_0_REG_LAZYUPDATEDISABLE 0x10000000
1724 #define A3XX_HLSQ_CONTROL_0_REG_SPCONSTFULLUPDATE 0x20000000
1725 #define A3XX_HLSQ_CONTROL_0_REG_TPFULLUPDATE 0x40000000
1726 #define A3XX_HLSQ_CONTROL_0_REG_SINGLECONTEXT 0x80000000
1727
1728 #define REG_A3XX_HLSQ_CONTROL_1_REG 0x00002201
1729 #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK 0x000000c0
1730 #define A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT 6
1731 static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE(enum a3xx_threadsize val)
1732 {
1733 return ((val) << A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_VSTHREADSIZE__MASK;
1734 }
1735 #define A3XX_HLSQ_CONTROL_1_REG_VSSUPERTHREADENABLE 0x00000100
1736 #define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__MASK 0x00ff0000
1737 #define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__SHIFT 16
1738 static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID(uint32_t val)
1739 {
1740 return ((val) << A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDXYREGID__MASK;
1741 }
1742 #define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__MASK 0xff000000
1743 #define A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__SHIFT 24
1744 static inline uint32_t A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID(uint32_t val)
1745 {
1746 return ((val) << A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__SHIFT) & A3XX_HLSQ_CONTROL_1_REG_FRAGCOORDZWREGID__MASK;
1747 }
1748
1749 #define REG_A3XX_HLSQ_CONTROL_2_REG 0x00002202
1750 #define A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__MASK 0x000003fc
1751 #define A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__SHIFT 2
1752 static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID(uint32_t val)
1753 {
1754 return ((val) << A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_FACENESSREGID__MASK;
1755 }
1756 #define A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__MASK 0x03fc0000
1757 #define A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__SHIFT 18
1758 static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID(uint32_t val)
1759 {
1760 return ((val) << A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_COVVALUEREGID__MASK;
1761 }
1762 #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK 0xfc000000
1763 #define A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT 26
1764 static inline uint32_t A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD(uint32_t val)
1765 {
1766 return ((val) << A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__SHIFT) & A3XX_HLSQ_CONTROL_2_REG_PRIMALLOCTHRESHOLD__MASK;
1767 }
1768
1769 #define REG_A3XX_HLSQ_CONTROL_3_REG 0x00002203
1770 #define A3XX_HLSQ_CONTROL_3_REG_REGID__MASK 0x000000ff
1771 #define A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT 0
1772 static inline uint32_t A3XX_HLSQ_CONTROL_3_REG_REGID(uint32_t val)
1773 {
1774 return ((val) << A3XX_HLSQ_CONTROL_3_REG_REGID__SHIFT) & A3XX_HLSQ_CONTROL_3_REG_REGID__MASK;
1775 }
1776
1777 #define REG_A3XX_HLSQ_VS_CONTROL_REG 0x00002204
1778 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK 0x000003ff
1779 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT 0
1780 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH(uint32_t val)
1781 {
1782 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTLENGTH__MASK;
1783 }
1784 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x001ff000
1785 #define A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12
1786 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val)
1787 {
1788 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_CONSTSTARTOFFSET__MASK;
1789 }
1790 #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
1791 #define A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT 24
1792 static inline uint32_t A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH(uint32_t val)
1793 {
1794 return ((val) << A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_VS_CONTROL_REG_INSTRLENGTH__MASK;
1795 }
1796
1797 #define REG_A3XX_HLSQ_FS_CONTROL_REG 0x00002205
1798 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK 0x000003ff
1799 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT 0
1800 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH(uint32_t val)
1801 {
1802 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTLENGTH__MASK;
1803 }
1804 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK 0x001ff000
1805 #define A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT 12
1806 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET(uint32_t val)
1807 {
1808 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_CONSTSTARTOFFSET__MASK;
1809 }
1810 #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK 0xff000000
1811 #define A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT 24
1812 static inline uint32_t A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH(uint32_t val)
1813 {
1814 return ((val) << A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__SHIFT) & A3XX_HLSQ_FS_CONTROL_REG_INSTRLENGTH__MASK;
1815 }
1816
1817 #define REG_A3XX_HLSQ_CONST_VSPRESV_RANGE_REG 0x00002206
1818 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK 0x000001ff
1819 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT 0
1820 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY(uint32_t val)
1821 {
1822 return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_STARTENTRY__MASK;
1823 }
1824 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK 0x01ff0000
1825 #define A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT 16
1826 static inline uint32_t A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
1827 {
1828 return ((val) << A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_VSPRESV_RANGE_REG_ENDENTRY__MASK;
1829 }
1830
1831 #define REG_A3XX_HLSQ_CONST_FSPRESV_RANGE_REG 0x00002207
1832 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK 0x000001ff
1833 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT 0
1834 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY(uint32_t val)
1835 {
1836 return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_STARTENTRY__MASK;
1837 }
1838 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK 0x01ff0000
1839 #define A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT 16
1840 static inline uint32_t A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY(uint32_t val)
1841 {
1842 return ((val) << A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__SHIFT) & A3XX_HLSQ_CONST_FSPRESV_RANGE_REG_ENDENTRY__MASK;
1843 }
1844
1845 #define REG_A3XX_HLSQ_CL_NDRANGE_0_REG 0x0000220a
1846 #define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK 0x00000003
1847 #define A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT 0
1848 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM(uint32_t val)
1849 {
1850 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_WORKDIM__MASK;
1851 }
1852 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK 0x00000ffc
1853 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT 2
1854 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0(uint32_t val)
1855 {
1856 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE0__MASK;
1857 }
1858 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK 0x003ff000
1859 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT 12
1860 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1(uint32_t val)
1861 {
1862 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE1__MASK;
1863 }
1864 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK 0xffc00000
1865 #define A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT 22
1866 static inline uint32_t A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2(uint32_t val)
1867 {
1868 return ((val) << A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__SHIFT) & A3XX_HLSQ_CL_NDRANGE_0_REG_LOCALSIZE2__MASK;
1869 }
1870
1871 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK(uint32_t i0) { return 0x0000220b + 0x2*i0; }
1872
1873 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_SIZE(uint32_t i0) { return 0x0000220b + 0x2*i0; }
1874
1875 static inline uint32_t REG_A3XX_HLSQ_CL_GLOBAL_WORK_OFFSET(uint32_t i0) { return 0x0000220c + 0x2*i0; }
1876
1877 #define REG_A3XX_HLSQ_CL_CONTROL_0_REG 0x00002211
1878
1879 #define REG_A3XX_HLSQ_CL_CONTROL_1_REG 0x00002212
1880
1881 #define REG_A3XX_HLSQ_CL_KERNEL_CONST_REG 0x00002214
1882
1883 static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP(uint32_t i0) { return 0x00002215 + 0x1*i0; }
1884
1885 static inline uint32_t REG_A3XX_HLSQ_CL_KERNEL_GROUP_RATIO(uint32_t i0) { return 0x00002215 + 0x1*i0; }
1886
1887 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Y_REG 0x00002216
1888
1889 #define REG_A3XX_HLSQ_CL_KERNEL_GROUP_Z_REG 0x00002217
1890
1891 #define REG_A3XX_HLSQ_CL_WG_OFFSET_REG 0x0000221a
1892
1893 #define REG_A3XX_VFD_CONTROL_0 0x00002240
1894 #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK 0x0003ffff
1895 #define A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT 0
1896 static inline uint32_t A3XX_VFD_CONTROL_0_TOTALATTRTOVS(uint32_t val)
1897 {
1898 return ((val) << A3XX_VFD_CONTROL_0_TOTALATTRTOVS__SHIFT) & A3XX_VFD_CONTROL_0_TOTALATTRTOVS__MASK;
1899 }
1900 #define A3XX_VFD_CONTROL_0_PACKETSIZE__MASK 0x003c0000
1901 #define A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT 18
1902 static inline uint32_t A3XX_VFD_CONTROL_0_PACKETSIZE(uint32_t val)
1903 {
1904 return ((val) << A3XX_VFD_CONTROL_0_PACKETSIZE__SHIFT) & A3XX_VFD_CONTROL_0_PACKETSIZE__MASK;
1905 }
1906 #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK 0x07c00000
1907 #define A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT 22
1908 static inline uint32_t A3XX_VFD_CONTROL_0_STRMDECINSTRCNT(uint32_t val)
1909 {
1910 return ((val) << A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMDECINSTRCNT__MASK;
1911 }
1912 #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK 0xf8000000
1913 #define A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT 27
1914 static inline uint32_t A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT(uint32_t val)
1915 {
1916 return ((val) << A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__SHIFT) & A3XX_VFD_CONTROL_0_STRMFETCHINSTRCNT__MASK;
1917 }
1918
1919 #define REG_A3XX_VFD_CONTROL_1 0x00002241
1920 #define A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK 0x0000000f
1921 #define A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT 0
1922 static inline uint32_t A3XX_VFD_CONTROL_1_MAXSTORAGE(uint32_t val)
1923 {
1924 return ((val) << A3XX_VFD_CONTROL_1_MAXSTORAGE__SHIFT) & A3XX_VFD_CONTROL_1_MAXSTORAGE__MASK;
1925 }
1926 #define A3XX_VFD_CONTROL_1_MAXTHRESHOLD__MASK 0x000000f0
1927 #define A3XX_VFD_CONTROL_1_MAXTHRESHOLD__SHIFT 4
1928 static inline uint32_t A3XX_VFD_CONTROL_1_MAXTHRESHOLD(uint32_t val)
1929 {
1930 return ((val) << A3XX_VFD_CONTROL_1_MAXTHRESHOLD__SHIFT) & A3XX_VFD_CONTROL_1_MAXTHRESHOLD__MASK;
1931 }
1932 #define A3XX_VFD_CONTROL_1_MINTHRESHOLD__MASK 0x00000f00
1933 #define A3XX_VFD_CONTROL_1_MINTHRESHOLD__SHIFT 8
1934 static inline uint32_t A3XX_VFD_CONTROL_1_MINTHRESHOLD(uint32_t val)
1935 {
1936 return ((val) << A3XX_VFD_CONTROL_1_MINTHRESHOLD__SHIFT) & A3XX_VFD_CONTROL_1_MINTHRESHOLD__MASK;
1937 }
1938 #define A3XX_VFD_CONTROL_1_REGID4VTX__MASK 0x00ff0000
1939 #define A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT 16
1940 static inline uint32_t A3XX_VFD_CONTROL_1_REGID4VTX(uint32_t val)
1941 {
1942 return ((val) << A3XX_VFD_CONTROL_1_REGID4VTX__SHIFT) & A3XX_VFD_CONTROL_1_REGID4VTX__MASK;
1943 }
1944 #define A3XX_VFD_CONTROL_1_REGID4INST__MASK 0xff000000
1945 #define A3XX_VFD_CONTROL_1_REGID4INST__SHIFT 24
1946 static inline uint32_t A3XX_VFD_CONTROL_1_REGID4INST(uint32_t val)
1947 {
1948 return ((val) << A3XX_VFD_CONTROL_1_REGID4INST__SHIFT) & A3XX_VFD_CONTROL_1_REGID4INST__MASK;
1949 }
1950
1951 #define REG_A3XX_VFD_INDEX_MIN 0x00002242
1952
1953 #define REG_A3XX_VFD_INDEX_MAX 0x00002243
1954
1955 #define REG_A3XX_VFD_INSTANCEID_OFFSET 0x00002244
1956
1957 #define REG_A3XX_VFD_INDEX_OFFSET 0x00002245
1958
1959 #define REG_A3XX_VFD_INDEX_OFFSET 0x00002245
1960
1961 static inline uint32_t REG_A3XX_VFD_FETCH(uint32_t i0) { return 0x00002246 + 0x2*i0; }
1962
1963 static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_0(uint32_t i0) { return 0x00002246 + 0x2*i0; }
1964 #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK 0x0000007f
1965 #define A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT 0
1966 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_FETCHSIZE(uint32_t val)
1967 {
1968 return ((val) << A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_FETCHSIZE__MASK;
1969 }
1970 #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK 0x0000ff80
1971 #define A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT 7
1972 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE(uint32_t val)
1973 {
1974 return ((val) << A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_BUFSTRIDE__MASK;
1975 }
1976 #define A3XX_VFD_FETCH_INSTR_0_INSTANCED 0x00010000
1977 #define A3XX_VFD_FETCH_INSTR_0_SWITCHNEXT 0x00020000
1978 #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK 0x00fc0000
1979 #define A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT 18
1980 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_INDEXCODE(uint32_t val)
1981 {
1982 return ((val) << A3XX_VFD_FETCH_INSTR_0_INDEXCODE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_INDEXCODE__MASK;
1983 }
1984 #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK 0xff000000
1985 #define A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT 24
1986 static inline uint32_t A3XX_VFD_FETCH_INSTR_0_STEPRATE(uint32_t val)
1987 {
1988 return ((val) << A3XX_VFD_FETCH_INSTR_0_STEPRATE__SHIFT) & A3XX_VFD_FETCH_INSTR_0_STEPRATE__MASK;
1989 }
1990
1991 static inline uint32_t REG_A3XX_VFD_FETCH_INSTR_1(uint32_t i0) { return 0x00002247 + 0x2*i0; }
1992
1993 static inline uint32_t REG_A3XX_VFD_DECODE(uint32_t i0) { return 0x00002266 + 0x1*i0; }
1994
1995 static inline uint32_t REG_A3XX_VFD_DECODE_INSTR(uint32_t i0) { return 0x00002266 + 0x1*i0; }
1996 #define A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK 0x0000000f
1997 #define A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT 0
1998 static inline uint32_t A3XX_VFD_DECODE_INSTR_WRITEMASK(uint32_t val)
1999 {
2000 return ((val) << A3XX_VFD_DECODE_INSTR_WRITEMASK__SHIFT) & A3XX_VFD_DECODE_INSTR_WRITEMASK__MASK;
2001 }
2002 #define A3XX_VFD_DECODE_INSTR_CONSTFILL 0x00000010
2003 #define A3XX_VFD_DECODE_INSTR_FORMAT__MASK 0x00000fc0
2004 #define A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT 6
2005 static inline uint32_t A3XX_VFD_DECODE_INSTR_FORMAT(enum a3xx_vtx_fmt val)
2006 {
2007 return ((val) << A3XX_VFD_DECODE_INSTR_FORMAT__SHIFT) & A3XX_VFD_DECODE_INSTR_FORMAT__MASK;
2008 }
2009 #define A3XX_VFD_DECODE_INSTR_REGID__MASK 0x000ff000
2010 #define A3XX_VFD_DECODE_INSTR_REGID__SHIFT 12
2011 static inline uint32_t A3XX_VFD_DECODE_INSTR_REGID(uint32_t val)
2012 {
2013 return ((val) << A3XX_VFD_DECODE_INSTR_REGID__SHIFT) & A3XX_VFD_DECODE_INSTR_REGID__MASK;
2014 }
2015 #define A3XX_VFD_DECODE_INSTR_INT 0x00100000
2016 #define A3XX_VFD_DECODE_INSTR_SWAP__MASK 0x00c00000
2017 #define A3XX_VFD_DECODE_INSTR_SWAP__SHIFT 22
2018 static inline uint32_t A3XX_VFD_DECODE_INSTR_SWAP(enum a3xx_color_swap val)
2019 {
2020 return ((val) << A3XX_VFD_DECODE_INSTR_SWAP__SHIFT) & A3XX_VFD_DECODE_INSTR_SWAP__MASK;
2021 }
2022 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK 0x1f000000
2023 #define A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT 24
2024 static inline uint32_t A3XX_VFD_DECODE_INSTR_SHIFTCNT(uint32_t val)
2025 {
2026 return ((val) << A3XX_VFD_DECODE_INSTR_SHIFTCNT__SHIFT) & A3XX_VFD_DECODE_INSTR_SHIFTCNT__MASK;
2027 }
2028 #define A3XX_VFD_DECODE_INSTR_LASTCOMPVALID 0x20000000
2029 #define A3XX_VFD_DECODE_INSTR_SWITCHNEXT 0x40000000
2030
2031 #define REG_A3XX_VFD_VS_THREADING_THRESHOLD 0x0000227e
2032 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK 0x0000000f
2033 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT 0
2034 static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD(uint32_t val)
2035 {
2036 return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_THRESHOLD__MASK;
2037 }
2038 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK 0x0000ff00
2039 #define A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT 8
2040 static inline uint32_t A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT(uint32_t val)
2041 {
2042 return ((val) << A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__SHIFT) & A3XX_VFD_VS_THREADING_THRESHOLD_REGID_VTXCNT__MASK;
2043 }
2044
2045 #define REG_A3XX_VPC_ATTR 0x00002280
2046 #define A3XX_VPC_ATTR_TOTALATTR__MASK 0x000001ff
2047 #define A3XX_VPC_ATTR_TOTALATTR__SHIFT 0
2048 static inline uint32_t A3XX_VPC_ATTR_TOTALATTR(uint32_t val)
2049 {
2050 return ((val) << A3XX_VPC_ATTR_TOTALATTR__SHIFT) & A3XX_VPC_ATTR_TOTALATTR__MASK;
2051 }
2052 #define A3XX_VPC_ATTR_PSIZE 0x00000200
2053 #define A3XX_VPC_ATTR_THRDASSIGN__MASK 0x0ffff000
2054 #define A3XX_VPC_ATTR_THRDASSIGN__SHIFT 12
2055 static inline uint32_t A3XX_VPC_ATTR_THRDASSIGN(uint32_t val)
2056 {
2057 return ((val) << A3XX_VPC_ATTR_THRDASSIGN__SHIFT) & A3XX_VPC_ATTR_THRDASSIGN__MASK;
2058 }
2059 #define A3XX_VPC_ATTR_LMSIZE__MASK 0xf0000000
2060 #define A3XX_VPC_ATTR_LMSIZE__SHIFT 28
2061 static inline uint32_t A3XX_VPC_ATTR_LMSIZE(uint32_t val)
2062 {
2063 return ((val) << A3XX_VPC_ATTR_LMSIZE__SHIFT) & A3XX_VPC_ATTR_LMSIZE__MASK;
2064 }
2065
2066 #define REG_A3XX_VPC_PACK 0x00002281
2067 #define A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK 0x0000ff00
2068 #define A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT 8
2069 static inline uint32_t A3XX_VPC_PACK_NUMFPNONPOSVAR(uint32_t val)
2070 {
2071 return ((val) << A3XX_VPC_PACK_NUMFPNONPOSVAR__SHIFT) & A3XX_VPC_PACK_NUMFPNONPOSVAR__MASK;
2072 }
2073 #define A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK 0x00ff0000
2074 #define A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT 16
2075 static inline uint32_t A3XX_VPC_PACK_NUMNONPOSVSVAR(uint32_t val)
2076 {
2077 return ((val) << A3XX_VPC_PACK_NUMNONPOSVSVAR__SHIFT) & A3XX_VPC_PACK_NUMNONPOSVSVAR__MASK;
2078 }
2079
2080 static inline uint32_t REG_A3XX_VPC_VARYING_INTERP(uint32_t i0) { return 0x00002282 + 0x1*i0; }
2081
2082 static inline uint32_t REG_A3XX_VPC_VARYING_INTERP_MODE(uint32_t i0) { return 0x00002282 + 0x1*i0; }
2083 #define A3XX_VPC_VARYING_INTERP_MODE_C0__MASK 0x00000003
2084 #define A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT 0
2085 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C0(enum a3xx_intp_mode val)
2086 {
2087 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C0__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C0__MASK;
2088 }
2089 #define A3XX_VPC_VARYING_INTERP_MODE_C1__MASK 0x0000000c
2090 #define A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT 2
2091 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C1(enum a3xx_intp_mode val)
2092 {
2093 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C1__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C1__MASK;
2094 }
2095 #define A3XX_VPC_VARYING_INTERP_MODE_C2__MASK 0x00000030
2096 #define A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT 4
2097 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C2(enum a3xx_intp_mode val)
2098 {
2099 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C2__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C2__MASK;
2100 }
2101 #define A3XX_VPC_VARYING_INTERP_MODE_C3__MASK 0x000000c0
2102 #define A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT 6
2103 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C3(enum a3xx_intp_mode val)
2104 {
2105 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C3__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C3__MASK;
2106 }
2107 #define A3XX_VPC_VARYING_INTERP_MODE_C4__MASK 0x00000300
2108 #define A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT 8
2109 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C4(enum a3xx_intp_mode val)
2110 {
2111 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C4__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C4__MASK;
2112 }
2113 #define A3XX_VPC_VARYING_INTERP_MODE_C5__MASK 0x00000c00
2114 #define A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT 10
2115 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C5(enum a3xx_intp_mode val)
2116 {
2117 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C5__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C5__MASK;
2118 }
2119 #define A3XX_VPC_VARYING_INTERP_MODE_C6__MASK 0x00003000
2120 #define A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT 12
2121 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C6(enum a3xx_intp_mode val)
2122 {
2123 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C6__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C6__MASK;
2124 }
2125 #define A3XX_VPC_VARYING_INTERP_MODE_C7__MASK 0x0000c000
2126 #define A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT 14
2127 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C7(enum a3xx_intp_mode val)
2128 {
2129 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C7__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C7__MASK;
2130 }
2131 #define A3XX_VPC_VARYING_INTERP_MODE_C8__MASK 0x00030000
2132 #define A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT 16
2133 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C8(enum a3xx_intp_mode val)
2134 {
2135 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C8__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C8__MASK;
2136 }
2137 #define A3XX_VPC_VARYING_INTERP_MODE_C9__MASK 0x000c0000
2138 #define A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT 18
2139 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_C9(enum a3xx_intp_mode val)
2140 {
2141 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_C9__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_C9__MASK;
2142 }
2143 #define A3XX_VPC_VARYING_INTERP_MODE_CA__MASK 0x00300000
2144 #define A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT 20
2145 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CA(enum a3xx_intp_mode val)
2146 {
2147 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CA__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CA__MASK;
2148 }
2149 #define A3XX_VPC_VARYING_INTERP_MODE_CB__MASK 0x00c00000
2150 #define A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT 22
2151 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CB(enum a3xx_intp_mode val)
2152 {
2153 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CB__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CB__MASK;
2154 }
2155 #define A3XX_VPC_VARYING_INTERP_MODE_CC__MASK 0x03000000
2156 #define A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT 24
2157 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CC(enum a3xx_intp_mode val)
2158 {
2159 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CC__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CC__MASK;
2160 }
2161 #define A3XX_VPC_VARYING_INTERP_MODE_CD__MASK 0x0c000000
2162 #define A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT 26
2163 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CD(enum a3xx_intp_mode val)
2164 {
2165 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CD__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CD__MASK;
2166 }
2167 #define A3XX_VPC_VARYING_INTERP_MODE_CE__MASK 0x30000000
2168 #define A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT 28
2169 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CE(enum a3xx_intp_mode val)
2170 {
2171 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CE__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CE__MASK;
2172 }
2173 #define A3XX_VPC_VARYING_INTERP_MODE_CF__MASK 0xc0000000
2174 #define A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT 30
2175 static inline uint32_t A3XX_VPC_VARYING_INTERP_MODE_CF(enum a3xx_intp_mode val)
2176 {
2177 return ((val) << A3XX_VPC_VARYING_INTERP_MODE_CF__SHIFT) & A3XX_VPC_VARYING_INTERP_MODE_CF__MASK;
2178 }
2179
2180 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL(uint32_t i0) { return 0x00002286 + 0x1*i0; }
2181
2182 static inline uint32_t REG_A3XX_VPC_VARYING_PS_REPL_MODE(uint32_t i0) { return 0x00002286 + 0x1*i0; }
2183 #define A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK 0x00000003
2184 #define A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT 0
2185 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C0(enum a3xx_repl_mode val)
2186 {
2187 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C0__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C0__MASK;
2188 }
2189 #define A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK 0x0000000c
2190 #define A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT 2
2191 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C1(enum a3xx_repl_mode val)
2192 {
2193 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C1__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C1__MASK;
2194 }
2195 #define A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK 0x00000030
2196 #define A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT 4
2197 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C2(enum a3xx_repl_mode val)
2198 {
2199 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C2__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C2__MASK;
2200 }
2201 #define A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK 0x000000c0
2202 #define A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT 6
2203 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C3(enum a3xx_repl_mode val)
2204 {
2205 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C3__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C3__MASK;
2206 }
2207 #define A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK 0x00000300
2208 #define A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT 8
2209 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C4(enum a3xx_repl_mode val)
2210 {
2211 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C4__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C4__MASK;
2212 }
2213 #define A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK 0x00000c00
2214 #define A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT 10
2215 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C5(enum a3xx_repl_mode val)
2216 {
2217 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C5__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C5__MASK;
2218 }
2219 #define A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK 0x00003000
2220 #define A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT 12
2221 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C6(enum a3xx_repl_mode val)
2222 {
2223 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C6__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C6__MASK;
2224 }
2225 #define A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK 0x0000c000
2226 #define A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT 14
2227 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C7(enum a3xx_repl_mode val)
2228 {
2229 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C7__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C7__MASK;
2230 }
2231 #define A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK 0x00030000
2232 #define A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT 16
2233 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C8(enum a3xx_repl_mode val)
2234 {
2235 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C8__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C8__MASK;
2236 }
2237 #define A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK 0x000c0000
2238 #define A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT 18
2239 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_C9(enum a3xx_repl_mode val)
2240 {
2241 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_C9__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_C9__MASK;
2242 }
2243 #define A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK 0x00300000
2244 #define A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT 20
2245 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CA(enum a3xx_repl_mode val)
2246 {
2247 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CA__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CA__MASK;
2248 }
2249 #define A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK 0x00c00000
2250 #define A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT 22
2251 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CB(enum a3xx_repl_mode val)
2252 {
2253 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CB__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CB__MASK;
2254 }
2255 #define A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK 0x03000000
2256 #define A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT 24
2257 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CC(enum a3xx_repl_mode val)
2258 {
2259 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CC__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CC__MASK;
2260 }
2261 #define A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK 0x0c000000
2262 #define A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT 26
2263 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CD(enum a3xx_repl_mode val)
2264 {
2265 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CD__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CD__MASK;
2266 }
2267 #define A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK 0x30000000
2268 #define A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT 28
2269 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CE(enum a3xx_repl_mode val)
2270 {
2271 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CE__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CE__MASK;
2272 }
2273 #define A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK 0xc0000000
2274 #define A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT 30
2275 static inline uint32_t A3XX_VPC_VARYING_PS_REPL_MODE_CF(enum a3xx_repl_mode val)
2276 {
2277 return ((val) << A3XX_VPC_VARYING_PS_REPL_MODE_CF__SHIFT) & A3XX_VPC_VARYING_PS_REPL_MODE_CF__MASK;
2278 }
2279
2280 #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_0 0x0000228a
2281
2282 #define REG_A3XX_VPC_VARY_CYLWRAP_ENABLE_1 0x0000228b
2283
2284 #define REG_A3XX_SP_SP_CTRL_REG 0x000022c0
2285 #define A3XX_SP_SP_CTRL_REG_RESOLVE 0x00010000
2286 #define A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK 0x00040000
2287 #define A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT 18
2288 static inline uint32_t A3XX_SP_SP_CTRL_REG_CONSTMODE(uint32_t val)
2289 {
2290 return ((val) << A3XX_SP_SP_CTRL_REG_CONSTMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_CONSTMODE__MASK;
2291 }
2292 #define A3XX_SP_SP_CTRL_REG_BINNING 0x00080000
2293 #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK 0x00300000
2294 #define A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT 20
2295 static inline uint32_t A3XX_SP_SP_CTRL_REG_SLEEPMODE(uint32_t val)
2296 {
2297 return ((val) << A3XX_SP_SP_CTRL_REG_SLEEPMODE__SHIFT) & A3XX_SP_SP_CTRL_REG_SLEEPMODE__MASK;
2298 }
2299 #define A3XX_SP_SP_CTRL_REG_L0MODE__MASK 0x00c00000
2300 #define A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT 22
2301 static inline uint32_t A3XX_SP_SP_CTRL_REG_L0MODE(uint32_t val)
2302 {
2303 return ((val) << A3XX_SP_SP_CTRL_REG_L0MODE__SHIFT) & A3XX_SP_SP_CTRL_REG_L0MODE__MASK;
2304 }
2305
2306 #define REG_A3XX_SP_VS_CTRL_REG0 0x000022c4
2307 #define A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK 0x00000001
2308 #define A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT 0
2309 static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
2310 {
2311 return ((val) << A3XX_SP_VS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADMODE__MASK;
2312 }
2313 #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002
2314 #define A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1
2315 static inline uint32_t A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val)
2316 {
2317 return ((val) << A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_VS_CTRL_REG0_INSTRBUFFERMODE__MASK;
2318 }
2319 #define A3XX_SP_VS_CTRL_REG0_CACHEINVALID 0x00000004
2320 #define A3XX_SP_VS_CTRL_REG0_ALUSCHMODE 0x00000008
2321 #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
2322 #define A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
2323 static inline uint32_t A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
2324 {
2325 return ((val) << A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
2326 }
2327 #define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
2328 #define A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
2329 static inline uint32_t A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
2330 {
2331 return ((val) << A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
2332 }
2333 #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK 0x00100000
2334 #define A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT 20
2335 static inline uint32_t A3XX_SP_VS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
2336 {
2337 return ((val) << A3XX_SP_VS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_VS_CTRL_REG0_THREADSIZE__MASK;
2338 }
2339 #define A3XX_SP_VS_CTRL_REG0_SUPERTHREADMODE 0x00200000
2340 #define A3XX_SP_VS_CTRL_REG0_LENGTH__MASK 0xff000000
2341 #define A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT 24
2342 static inline uint32_t A3XX_SP_VS_CTRL_REG0_LENGTH(uint32_t val)
2343 {
2344 return ((val) << A3XX_SP_VS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG0_LENGTH__MASK;
2345 }
2346
2347 #define REG_A3XX_SP_VS_CTRL_REG1 0x000022c5
2348 #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff
2349 #define A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT 0
2350 static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTLENGTH(uint32_t val)
2351 {
2352 return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTLENGTH__MASK;
2353 }
2354 #define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00
2355 #define A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10
2356 static inline uint32_t A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val)
2357 {
2358 return ((val) << A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_VS_CTRL_REG1_CONSTFOOTPRINT__MASK;
2359 }
2360 #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x7f000000
2361 #define A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 24
2362 static inline uint32_t A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
2363 {
2364 return ((val) << A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_VS_CTRL_REG1_INITIALOUTSTANDING__MASK;
2365 }
2366
2367 #define REG_A3XX_SP_VS_PARAM_REG 0x000022c6
2368 #define A3XX_SP_VS_PARAM_REG_POSREGID__MASK 0x000000ff
2369 #define A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT 0
2370 static inline uint32_t A3XX_SP_VS_PARAM_REG_POSREGID(uint32_t val)
2371 {
2372 return ((val) << A3XX_SP_VS_PARAM_REG_POSREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_POSREGID__MASK;
2373 }
2374 #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK 0x0000ff00
2375 #define A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT 8
2376 static inline uint32_t A3XX_SP_VS_PARAM_REG_PSIZEREGID(uint32_t val)
2377 {
2378 return ((val) << A3XX_SP_VS_PARAM_REG_PSIZEREGID__SHIFT) & A3XX_SP_VS_PARAM_REG_PSIZEREGID__MASK;
2379 }
2380 #define A3XX_SP_VS_PARAM_REG_POS2DMODE 0x00010000
2381 #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK 0x01f00000
2382 #define A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT 20
2383 static inline uint32_t A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR(uint32_t val)
2384 {
2385 return ((val) << A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__SHIFT) & A3XX_SP_VS_PARAM_REG_TOTALVSOUTVAR__MASK;
2386 }
2387
2388 static inline uint32_t REG_A3XX_SP_VS_OUT(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
2389
2390 static inline uint32_t REG_A3XX_SP_VS_OUT_REG(uint32_t i0) { return 0x000022c7 + 0x1*i0; }
2391 #define A3XX_SP_VS_OUT_REG_A_REGID__MASK 0x000000ff
2392 #define A3XX_SP_VS_OUT_REG_A_REGID__SHIFT 0
2393 static inline uint32_t A3XX_SP_VS_OUT_REG_A_REGID(uint32_t val)
2394 {
2395 return ((val) << A3XX_SP_VS_OUT_REG_A_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_A_REGID__MASK;
2396 }
2397 #define A3XX_SP_VS_OUT_REG_A_HALF 0x00000100
2398 #define A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK 0x00001e00
2399 #define A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT 9
2400 static inline uint32_t A3XX_SP_VS_OUT_REG_A_COMPMASK(uint32_t val)
2401 {
2402 return ((val) << A3XX_SP_VS_OUT_REG_A_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_A_COMPMASK__MASK;
2403 }
2404 #define A3XX_SP_VS_OUT_REG_B_REGID__MASK 0x00ff0000
2405 #define A3XX_SP_VS_OUT_REG_B_REGID__SHIFT 16
2406 static inline uint32_t A3XX_SP_VS_OUT_REG_B_REGID(uint32_t val)
2407 {
2408 return ((val) << A3XX_SP_VS_OUT_REG_B_REGID__SHIFT) & A3XX_SP_VS_OUT_REG_B_REGID__MASK;
2409 }
2410 #define A3XX_SP_VS_OUT_REG_B_HALF 0x01000000
2411 #define A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK 0x1e000000
2412 #define A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT 25
2413 static inline uint32_t A3XX_SP_VS_OUT_REG_B_COMPMASK(uint32_t val)
2414 {
2415 return ((val) << A3XX_SP_VS_OUT_REG_B_COMPMASK__SHIFT) & A3XX_SP_VS_OUT_REG_B_COMPMASK__MASK;
2416 }
2417
2418 static inline uint32_t REG_A3XX_SP_VS_VPC_DST(uint32_t i0) { return 0x000022d0 + 0x1*i0; }
2419
2420 static inline uint32_t REG_A3XX_SP_VS_VPC_DST_REG(uint32_t i0) { return 0x000022d0 + 0x1*i0; }
2421 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK 0x0000007f
2422 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT 0
2423 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC0(uint32_t val)
2424 {
2425 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC0__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC0__MASK;
2426 }
2427 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK 0x00007f00
2428 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT 8
2429 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC1(uint32_t val)
2430 {
2431 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC1__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC1__MASK;
2432 }
2433 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK 0x007f0000
2434 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT 16
2435 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC2(uint32_t val)
2436 {
2437 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC2__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC2__MASK;
2438 }
2439 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK 0x7f000000
2440 #define A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT 24
2441 static inline uint32_t A3XX_SP_VS_VPC_DST_REG_OUTLOC3(uint32_t val)
2442 {
2443 return ((val) << A3XX_SP_VS_VPC_DST_REG_OUTLOC3__SHIFT) & A3XX_SP_VS_VPC_DST_REG_OUTLOC3__MASK;
2444 }
2445
2446 #define REG_A3XX_SP_VS_OBJ_OFFSET_REG 0x000022d4
2447 #define A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK 0x0000ffff
2448 #define A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT 0
2449 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val)
2450 {
2451 return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK;
2452 }
2453 #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2454 #define A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
2455 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2456 {
2457 return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2458 }
2459 #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2460 #define A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
2461 static inline uint32_t A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2462 {
2463 return ((val) << A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_VS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2464 }
2465
2466 #define REG_A3XX_SP_VS_OBJ_START_REG 0x000022d5
2467
2468 #define REG_A3XX_SP_VS_PVT_MEM_PARAM_REG 0x000022d6
2469 #define A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK 0x000000ff
2470 #define A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT 0
2471 static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val)
2472 {
2473 return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK;
2474 }
2475 #define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK 0x00ffff00
2476 #define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT 8
2477 static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val)
2478 {
2479 return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK;
2480 }
2481 #define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK 0xff000000
2482 #define A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT 24
2483 static inline uint32_t A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val)
2484 {
2485 return ((val) << A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT) & A3XX_SP_VS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK;
2486 }
2487
2488 #define REG_A3XX_SP_VS_PVT_MEM_ADDR_REG 0x000022d7
2489 #define A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__MASK 0x0000001f
2490 #define A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT 0
2491 static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val)
2492 {
2493 return ((val) << A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_BURSTLEN__MASK;
2494 }
2495 #define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK 0xffffffe0
2496 #define A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT 5
2497 static inline uint32_t A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val)
2498 {
2499 assert(!(val & 0x1f));
2500 return ((val >> 5) << A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_VS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK;
2501 }
2502
2503 #define REG_A3XX_SP_VS_PVT_MEM_SIZE_REG 0x000022d8
2504
2505 #define REG_A3XX_SP_VS_LENGTH_REG 0x000022df
2506 #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff
2507 #define A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT 0
2508 static inline uint32_t A3XX_SP_VS_LENGTH_REG_SHADERLENGTH(uint32_t val)
2509 {
2510 return ((val) << A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_VS_LENGTH_REG_SHADERLENGTH__MASK;
2511 }
2512
2513 #define REG_A3XX_SP_FS_CTRL_REG0 0x000022e0
2514 #define A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK 0x00000001
2515 #define A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT 0
2516 static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADMODE(enum a3xx_threadmode val)
2517 {
2518 return ((val) << A3XX_SP_FS_CTRL_REG0_THREADMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADMODE__MASK;
2519 }
2520 #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK 0x00000002
2521 #define A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT 1
2522 static inline uint32_t A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE(enum a3xx_instrbuffermode val)
2523 {
2524 return ((val) << A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__SHIFT) & A3XX_SP_FS_CTRL_REG0_INSTRBUFFERMODE__MASK;
2525 }
2526 #define A3XX_SP_FS_CTRL_REG0_CACHEINVALID 0x00000004
2527 #define A3XX_SP_FS_CTRL_REG0_ALUSCHMODE 0x00000008
2528 #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK 0x000003f0
2529 #define A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT 4
2530 static inline uint32_t A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT(uint32_t val)
2531 {
2532 return ((val) << A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_HALFREGFOOTPRINT__MASK;
2533 }
2534 #define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK 0x0000fc00
2535 #define A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT 10
2536 static inline uint32_t A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT(uint32_t val)
2537 {
2538 return ((val) << A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG0_FULLREGFOOTPRINT__MASK;
2539 }
2540 #define A3XX_SP_FS_CTRL_REG0_FSBYPASSENABLE 0x00020000
2541 #define A3XX_SP_FS_CTRL_REG0_INOUTREGOVERLAP 0x00040000
2542 #define A3XX_SP_FS_CTRL_REG0_OUTORDERED 0x00080000
2543 #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK 0x00100000
2544 #define A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT 20
2545 static inline uint32_t A3XX_SP_FS_CTRL_REG0_THREADSIZE(enum a3xx_threadsize val)
2546 {
2547 return ((val) << A3XX_SP_FS_CTRL_REG0_THREADSIZE__SHIFT) & A3XX_SP_FS_CTRL_REG0_THREADSIZE__MASK;
2548 }
2549 #define A3XX_SP_FS_CTRL_REG0_SUPERTHREADMODE 0x00200000
2550 #define A3XX_SP_FS_CTRL_REG0_PIXLODENABLE 0x00400000
2551 #define A3XX_SP_FS_CTRL_REG0_COMPUTEMODE 0x00800000
2552 #define A3XX_SP_FS_CTRL_REG0_LENGTH__MASK 0xff000000
2553 #define A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT 24
2554 static inline uint32_t A3XX_SP_FS_CTRL_REG0_LENGTH(uint32_t val)
2555 {
2556 return ((val) << A3XX_SP_FS_CTRL_REG0_LENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG0_LENGTH__MASK;
2557 }
2558
2559 #define REG_A3XX_SP_FS_CTRL_REG1 0x000022e1
2560 #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK 0x000003ff
2561 #define A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT 0
2562 static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTLENGTH(uint32_t val)
2563 {
2564 return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTLENGTH__MASK;
2565 }
2566 #define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK 0x000ffc00
2567 #define A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT 10
2568 static inline uint32_t A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT(uint32_t val)
2569 {
2570 return ((val) << A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__SHIFT) & A3XX_SP_FS_CTRL_REG1_CONSTFOOTPRINT__MASK;
2571 }
2572 #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK 0x00f00000
2573 #define A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT 20
2574 static inline uint32_t A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING(uint32_t val)
2575 {
2576 return ((val) << A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__SHIFT) & A3XX_SP_FS_CTRL_REG1_INITIALOUTSTANDING__MASK;
2577 }
2578 #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK 0x7f000000
2579 #define A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT 24
2580 static inline uint32_t A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET(uint32_t val)
2581 {
2582 return ((val) << A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__SHIFT) & A3XX_SP_FS_CTRL_REG1_HALFPRECVAROFFSET__MASK;
2583 }
2584
2585 #define REG_A3XX_SP_FS_OBJ_OFFSET_REG 0x000022e2
2586 #define A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK 0x0000ffff
2587 #define A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT 0
2588 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET(uint32_t val)
2589 {
2590 return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_FIRSTEXECINSTROFFSET__MASK;
2591 }
2592 #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK 0x01ff0000
2593 #define A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT 16
2594 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET(uint32_t val)
2595 {
2596 return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_CONSTOBJECTOFFSET__MASK;
2597 }
2598 #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK 0xfe000000
2599 #define A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT 25
2600 static inline uint32_t A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET(uint32_t val)
2601 {
2602 return ((val) << A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__SHIFT) & A3XX_SP_FS_OBJ_OFFSET_REG_SHADEROBJOFFSET__MASK;
2603 }
2604
2605 #define REG_A3XX_SP_FS_OBJ_START_REG 0x000022e3
2606
2607 #define REG_A3XX_SP_FS_PVT_MEM_PARAM_REG 0x000022e4
2608 #define A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK 0x000000ff
2609 #define A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT 0
2610 static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM(uint32_t val)
2611 {
2612 return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_MEMSIZEPERITEM__MASK;
2613 }
2614 #define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK 0x00ffff00
2615 #define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT 8
2616 static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET(uint32_t val)
2617 {
2618 return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKOFFSET__MASK;
2619 }
2620 #define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK 0xff000000
2621 #define A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT 24
2622 static inline uint32_t A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD(uint32_t val)
2623 {
2624 return ((val) << A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__SHIFT) & A3XX_SP_FS_PVT_MEM_PARAM_REG_HWSTACKSIZEPERTHREAD__MASK;
2625 }
2626
2627 #define REG_A3XX_SP_FS_PVT_MEM_ADDR_REG 0x000022e5
2628 #define A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__MASK 0x0000001f
2629 #define A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT 0
2630 static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN(uint32_t val)
2631 {
2632 return ((val) << A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_BURSTLEN__MASK;
2633 }
2634 #define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK 0xffffffe0
2635 #define A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT 5
2636 static inline uint32_t A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS(uint32_t val)
2637 {
2638 assert(!(val & 0x1f));
2639 return ((val >> 5) << A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__SHIFT) & A3XX_SP_FS_PVT_MEM_ADDR_REG_SHADERSTARTADDRESS__MASK;
2640 }
2641
2642 #define REG_A3XX_SP_FS_PVT_MEM_SIZE_REG 0x000022e6
2643
2644 #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_0 0x000022e8
2645
2646 #define REG_A3XX_SP_FS_FLAT_SHAD_MODE_REG_1 0x000022e9
2647
2648 #define REG_A3XX_SP_FS_OUTPUT_REG 0x000022ec
2649 #define A3XX_SP_FS_OUTPUT_REG_MRT__MASK 0x00000003
2650 #define A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT 0
2651 static inline uint32_t A3XX_SP_FS_OUTPUT_REG_MRT(uint32_t val)
2652 {
2653 return ((val) << A3XX_SP_FS_OUTPUT_REG_MRT__SHIFT) & A3XX_SP_FS_OUTPUT_REG_MRT__MASK;
2654 }
2655 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_ENABLE 0x00000080
2656 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK 0x0000ff00
2657 #define A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT 8
2658 static inline uint32_t A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID(uint32_t val)
2659 {
2660 return ((val) << A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__SHIFT) & A3XX_SP_FS_OUTPUT_REG_DEPTH_REGID__MASK;
2661 }
2662
2663 static inline uint32_t REG_A3XX_SP_FS_MRT(uint32_t i0) { return 0x000022f0 + 0x1*i0; }
2664
2665 static inline uint32_t REG_A3XX_SP_FS_MRT_REG(uint32_t i0) { return 0x000022f0 + 0x1*i0; }
2666 #define A3XX_SP_FS_MRT_REG_REGID__MASK 0x000000ff
2667 #define A3XX_SP_FS_MRT_REG_REGID__SHIFT 0
2668 static inline uint32_t A3XX_SP_FS_MRT_REG_REGID(uint32_t val)
2669 {
2670 return ((val) << A3XX_SP_FS_MRT_REG_REGID__SHIFT) & A3XX_SP_FS_MRT_REG_REGID__MASK;
2671 }
2672 #define A3XX_SP_FS_MRT_REG_HALF_PRECISION 0x00000100
2673 #define A3XX_SP_FS_MRT_REG_SINT 0x00000400
2674 #define A3XX_SP_FS_MRT_REG_UINT 0x00000800
2675
2676 static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT(uint32_t i0) { return 0x000022f4 + 0x1*i0; }
2677
2678 static inline uint32_t REG_A3XX_SP_FS_IMAGE_OUTPUT_REG(uint32_t i0) { return 0x000022f4 + 0x1*i0; }
2679 #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK 0x0000003f
2680 #define A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT 0
2681 static inline uint32_t A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT(enum a3xx_color_fmt val)
2682 {
2683 return ((val) << A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__SHIFT) & A3XX_SP_FS_IMAGE_OUTPUT_REG_MRTFORMAT__MASK;
2684 }
2685
2686 #define REG_A3XX_SP_FS_LENGTH_REG 0x000022ff
2687 #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK 0xffffffff
2688 #define A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT 0
2689 static inline uint32_t A3XX_SP_FS_LENGTH_REG_SHADERLENGTH(uint32_t val)
2690 {
2691 return ((val) << A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__SHIFT) & A3XX_SP_FS_LENGTH_REG_SHADERLENGTH__MASK;
2692 }
2693
2694 #define REG_A3XX_PA_SC_AA_CONFIG 0x00002301
2695
2696 #define REG_A3XX_TPL1_TP_VS_TEX_OFFSET 0x00002340
2697 #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff
2698 #define A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0
2699 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val)
2700 {
2701 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_SAMPLEROFFSET__MASK;
2702 }
2703 #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00
2704 #define A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8
2705 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val)
2706 {
2707 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_MEMOBJOFFSET__MASK;
2708 }
2709 #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000
2710 #define A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT 16
2711 static inline uint32_t A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR(uint32_t val)
2712 {
2713 return ((val) << A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_VS_TEX_OFFSET_BASETABLEPTR__MASK;
2714 }
2715
2716 #define REG_A3XX_TPL1_TP_VS_BORDER_COLOR_BASE_ADDR 0x00002341
2717
2718 #define REG_A3XX_TPL1_TP_FS_TEX_OFFSET 0x00002342
2719 #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK 0x000000ff
2720 #define A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT 0
2721 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET(uint32_t val)
2722 {
2723 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_SAMPLEROFFSET__MASK;
2724 }
2725 #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK 0x0000ff00
2726 #define A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT 8
2727 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET(uint32_t val)
2728 {
2729 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_MEMOBJOFFSET__MASK;
2730 }
2731 #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK 0xffff0000
2732 #define A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT 16
2733 static inline uint32_t A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR(uint32_t val)
2734 {
2735 return ((val) << A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__SHIFT) & A3XX_TPL1_TP_FS_TEX_OFFSET_BASETABLEPTR__MASK;
2736 }
2737
2738 #define REG_A3XX_TPL1_TP_FS_BORDER_COLOR_BASE_ADDR 0x00002343
2739
2740 #define REG_A3XX_VBIF_CLKON 0x00003001
2741
2742 #define REG_A3XX_VBIF_FIXED_SORT_EN 0x0000300c
2743
2744 #define REG_A3XX_VBIF_FIXED_SORT_SEL0 0x0000300d
2745
2746 #define REG_A3XX_VBIF_FIXED_SORT_SEL1 0x0000300e
2747
2748 #define REG_A3XX_VBIF_ABIT_SORT 0x0000301c
2749
2750 #define REG_A3XX_VBIF_ABIT_SORT_CONF 0x0000301d
2751
2752 #define REG_A3XX_VBIF_GATE_OFF_WRREQ_EN 0x0000302a
2753
2754 #define REG_A3XX_VBIF_IN_RD_LIM_CONF0 0x0000302c
2755
2756 #define REG_A3XX_VBIF_IN_RD_LIM_CONF1 0x0000302d
2757
2758 #define REG_A3XX_VBIF_IN_WR_LIM_CONF0 0x00003030
2759
2760 #define REG_A3XX_VBIF_IN_WR_LIM_CONF1 0x00003031
2761
2762 #define REG_A3XX_VBIF_OUT_RD_LIM_CONF0 0x00003034
2763
2764 #define REG_A3XX_VBIF_OUT_WR_LIM_CONF0 0x00003035
2765
2766 #define REG_A3XX_VBIF_DDR_OUT_MAX_BURST 0x00003036
2767
2768 #define REG_A3XX_VBIF_ARB_CTL 0x0000303c
2769
2770 #define REG_A3XX_VBIF_ROUND_ROBIN_QOS_ARB 0x00003049
2771
2772 #define REG_A3XX_VBIF_OUT_AXI_AMEMTYPE_CONF0 0x00003058
2773
2774 #define REG_A3XX_VBIF_OUT_AXI_AOOO_EN 0x0000305e
2775
2776 #define REG_A3XX_VBIF_OUT_AXI_AOOO 0x0000305f
2777
2778 #define REG_A3XX_VBIF_PERF_CNT_EN 0x00003070
2779 #define A3XX_VBIF_PERF_CNT_EN_CNT0 0x00000001
2780 #define A3XX_VBIF_PERF_CNT_EN_CNT1 0x00000002
2781 #define A3XX_VBIF_PERF_CNT_EN_PWRCNT0 0x00000004
2782 #define A3XX_VBIF_PERF_CNT_EN_PWRCNT1 0x00000008
2783 #define A3XX_VBIF_PERF_CNT_EN_PWRCNT2 0x00000010
2784
2785 #define REG_A3XX_VBIF_PERF_CNT_CLR 0x00003071
2786 #define A3XX_VBIF_PERF_CNT_CLR_CNT0 0x00000001
2787 #define A3XX_VBIF_PERF_CNT_CLR_CNT1 0x00000002
2788 #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT0 0x00000004
2789 #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT1 0x00000008
2790 #define A3XX_VBIF_PERF_CNT_CLR_PWRCNT2 0x00000010
2791
2792 #define REG_A3XX_VBIF_PERF_CNT_SEL 0x00003072
2793
2794 #define REG_A3XX_VBIF_PERF_CNT0_LO 0x00003073
2795
2796 #define REG_A3XX_VBIF_PERF_CNT0_HI 0x00003074
2797
2798 #define REG_A3XX_VBIF_PERF_CNT1_LO 0x00003075
2799
2800 #define REG_A3XX_VBIF_PERF_CNT1_HI 0x00003076
2801
2802 #define REG_A3XX_VBIF_PERF_PWR_CNT0_LO 0x00003077
2803
2804 #define REG_A3XX_VBIF_PERF_PWR_CNT0_HI 0x00003078
2805
2806 #define REG_A3XX_VBIF_PERF_PWR_CNT1_LO 0x00003079
2807
2808 #define REG_A3XX_VBIF_PERF_PWR_CNT1_HI 0x0000307a
2809
2810 #define REG_A3XX_VBIF_PERF_PWR_CNT2_LO 0x0000307b
2811
2812 #define REG_A3XX_VBIF_PERF_PWR_CNT2_HI 0x0000307c
2813
2814 #define REG_A3XX_VSC_BIN_SIZE 0x00000c01
2815 #define A3XX_VSC_BIN_SIZE_WIDTH__MASK 0x0000001f
2816 #define A3XX_VSC_BIN_SIZE_WIDTH__SHIFT 0
2817 static inline uint32_t A3XX_VSC_BIN_SIZE_WIDTH(uint32_t val)
2818 {
2819 assert(!(val & 0x1f));
2820 return ((val >> 5) << A3XX_VSC_BIN_SIZE_WIDTH__SHIFT) & A3XX_VSC_BIN_SIZE_WIDTH__MASK;
2821 }
2822 #define A3XX_VSC_BIN_SIZE_HEIGHT__MASK 0x000003e0
2823 #define A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT 5
2824 static inline uint32_t A3XX_VSC_BIN_SIZE_HEIGHT(uint32_t val)
2825 {
2826 assert(!(val & 0x1f));
2827 return ((val >> 5) << A3XX_VSC_BIN_SIZE_HEIGHT__SHIFT) & A3XX_VSC_BIN_SIZE_HEIGHT__MASK;
2828 }
2829
2830 #define REG_A3XX_VSC_SIZE_ADDRESS 0x00000c02
2831
2832 static inline uint32_t REG_A3XX_VSC_PIPE(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
2833
2834 static inline uint32_t REG_A3XX_VSC_PIPE_CONFIG(uint32_t i0) { return 0x00000c06 + 0x3*i0; }
2835 #define A3XX_VSC_PIPE_CONFIG_X__MASK 0x000003ff
2836 #define A3XX_VSC_PIPE_CONFIG_X__SHIFT 0
2837 static inline uint32_t A3XX_VSC_PIPE_CONFIG_X(uint32_t val)
2838 {
2839 return ((val) << A3XX_VSC_PIPE_CONFIG_X__SHIFT) & A3XX_VSC_PIPE_CONFIG_X__MASK;
2840 }
2841 #define A3XX_VSC_PIPE_CONFIG_Y__MASK 0x000ffc00
2842 #define A3XX_VSC_PIPE_CONFIG_Y__SHIFT 10
2843 static inline uint32_t A3XX_VSC_PIPE_CONFIG_Y(uint32_t val)
2844 {
2845 return ((val) << A3XX_VSC_PIPE_CONFIG_Y__SHIFT) & A3XX_VSC_PIPE_CONFIG_Y__MASK;
2846 }
2847 #define A3XX_VSC_PIPE_CONFIG_W__MASK 0x00f00000
2848 #define A3XX_VSC_PIPE_CONFIG_W__SHIFT 20
2849 static inline uint32_t A3XX_VSC_PIPE_CONFIG_W(uint32_t val)
2850 {
2851 return ((val) << A3XX_VSC_PIPE_CONFIG_W__SHIFT) & A3XX_VSC_PIPE_CONFIG_W__MASK;
2852 }
2853 #define A3XX_VSC_PIPE_CONFIG_H__MASK 0x0f000000
2854 #define A3XX_VSC_PIPE_CONFIG_H__SHIFT 24
2855 static inline uint32_t A3XX_VSC_PIPE_CONFIG_H(uint32_t val)
2856 {
2857 return ((val) << A3XX_VSC_PIPE_CONFIG_H__SHIFT) & A3XX_VSC_PIPE_CONFIG_H__MASK;
2858 }
2859
2860 static inline uint32_t REG_A3XX_VSC_PIPE_DATA_ADDRESS(uint32_t i0) { return 0x00000c07 + 0x3*i0; }
2861
2862 static inline uint32_t REG_A3XX_VSC_PIPE_DATA_LENGTH(uint32_t i0) { return 0x00000c08 + 0x3*i0; }
2863
2864 #define REG_A3XX_VSC_BIN_CONTROL 0x00000c3c
2865 #define A3XX_VSC_BIN_CONTROL_BINNING_ENABLE 0x00000001
2866
2867 #define REG_A3XX_UNKNOWN_0C3D 0x00000c3d
2868
2869 #define REG_A3XX_PC_PERFCOUNTER0_SELECT 0x00000c48
2870
2871 #define REG_A3XX_PC_PERFCOUNTER1_SELECT 0x00000c49
2872
2873 #define REG_A3XX_PC_PERFCOUNTER2_SELECT 0x00000c4a
2874
2875 #define REG_A3XX_PC_PERFCOUNTER3_SELECT 0x00000c4b
2876
2877 #define REG_A3XX_GRAS_TSE_DEBUG_ECO 0x00000c81
2878
2879 #define REG_A3XX_GRAS_PERFCOUNTER0_SELECT 0x00000c88
2880
2881 #define REG_A3XX_GRAS_PERFCOUNTER1_SELECT 0x00000c89
2882
2883 #define REG_A3XX_GRAS_PERFCOUNTER2_SELECT 0x00000c8a
2884
2885 #define REG_A3XX_GRAS_PERFCOUNTER3_SELECT 0x00000c8b
2886
2887 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE(uint32_t i0) { return 0x00000ca0 + 0x4*i0; }
2888
2889 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_X(uint32_t i0) { return 0x00000ca0 + 0x4*i0; }
2890
2891 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Y(uint32_t i0) { return 0x00000ca1 + 0x4*i0; }
2892
2893 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_Z(uint32_t i0) { return 0x00000ca2 + 0x4*i0; }
2894
2895 static inline uint32_t REG_A3XX_GRAS_CL_USER_PLANE_W(uint32_t i0) { return 0x00000ca3 + 0x4*i0; }
2896
2897 #define REG_A3XX_RB_GMEM_BASE_ADDR 0x00000cc0
2898
2899 #define REG_A3XX_RB_DEBUG_ECO_CONTROLS_ADDR 0x00000cc1
2900
2901 #define REG_A3XX_RB_PERFCOUNTER0_SELECT 0x00000cc6
2902
2903 #define REG_A3XX_RB_PERFCOUNTER1_SELECT 0x00000cc7
2904
2905 #define REG_A3XX_RB_FRAME_BUFFER_DIMENSION 0x00000ce0
2906 #define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK 0x00003fff
2907 #define A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT 0
2908 static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH(uint32_t val)
2909 {
2910 return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_WIDTH__MASK;
2911 }
2912 #define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK 0x0fffc000
2913 #define A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT 14
2914 static inline uint32_t A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT(uint32_t val)
2915 {
2916 return ((val) << A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__SHIFT) & A3XX_RB_FRAME_BUFFER_DIMENSION_HEIGHT__MASK;
2917 }
2918
2919 #define REG_A3XX_HLSQ_PERFCOUNTER0_SELECT 0x00000e00
2920
2921 #define REG_A3XX_HLSQ_PERFCOUNTER1_SELECT 0x00000e01
2922
2923 #define REG_A3XX_HLSQ_PERFCOUNTER2_SELECT 0x00000e02
2924
2925 #define REG_A3XX_HLSQ_PERFCOUNTER3_SELECT 0x00000e03
2926
2927 #define REG_A3XX_HLSQ_PERFCOUNTER4_SELECT 0x00000e04
2928
2929 #define REG_A3XX_HLSQ_PERFCOUNTER5_SELECT 0x00000e05
2930
2931 #define REG_A3XX_UNKNOWN_0E43 0x00000e43
2932
2933 #define REG_A3XX_VFD_PERFCOUNTER0_SELECT 0x00000e44
2934
2935 #define REG_A3XX_VFD_PERFCOUNTER1_SELECT 0x00000e45
2936
2937 #define REG_A3XX_VPC_VPC_DEBUG_RAM_SEL 0x00000e61
2938
2939 #define REG_A3XX_VPC_VPC_DEBUG_RAM_READ 0x00000e62
2940
2941 #define REG_A3XX_VPC_PERFCOUNTER0_SELECT 0x00000e64
2942
2943 #define REG_A3XX_VPC_PERFCOUNTER1_SELECT 0x00000e65
2944
2945 #define REG_A3XX_UCHE_CACHE_MODE_CONTROL_REG 0x00000e82
2946
2947 #define REG_A3XX_UCHE_PERFCOUNTER0_SELECT 0x00000e84
2948
2949 #define REG_A3XX_UCHE_PERFCOUNTER1_SELECT 0x00000e85
2950
2951 #define REG_A3XX_UCHE_PERFCOUNTER2_SELECT 0x00000e86
2952
2953 #define REG_A3XX_UCHE_PERFCOUNTER3_SELECT 0x00000e87
2954
2955 #define REG_A3XX_UCHE_PERFCOUNTER4_SELECT 0x00000e88
2956
2957 #define REG_A3XX_UCHE_PERFCOUNTER5_SELECT 0x00000e89
2958
2959 #define REG_A3XX_UCHE_CACHE_INVALIDATE0_REG 0x00000ea0
2960 #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK 0x0fffffff
2961 #define A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT 0
2962 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR(uint32_t val)
2963 {
2964 return ((val) << A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE0_REG_ADDR__MASK;
2965 }
2966
2967 #define REG_A3XX_UCHE_CACHE_INVALIDATE1_REG 0x00000ea1
2968 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK 0x0fffffff
2969 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT 0
2970 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR(uint32_t val)
2971 {
2972 return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_ADDR__MASK;
2973 }
2974 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK 0x30000000
2975 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT 28
2976 static inline uint32_t A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE(enum a3xx_cache_opcode val)
2977 {
2978 return ((val) << A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__SHIFT) & A3XX_UCHE_CACHE_INVALIDATE1_REG_OPCODE__MASK;
2979 }
2980 #define A3XX_UCHE_CACHE_INVALIDATE1_REG_ENTIRE_CACHE 0x80000000
2981
2982 #define REG_A3XX_UNKNOWN_0EA6 0x00000ea6
2983
2984 #define REG_A3XX_SP_PERFCOUNTER0_SELECT 0x00000ec4
2985
2986 #define REG_A3XX_SP_PERFCOUNTER1_SELECT 0x00000ec5
2987
2988 #define REG_A3XX_SP_PERFCOUNTER2_SELECT 0x00000ec6
2989
2990 #define REG_A3XX_SP_PERFCOUNTER3_SELECT 0x00000ec7
2991
2992 #define REG_A3XX_SP_PERFCOUNTER4_SELECT 0x00000ec8
2993
2994 #define REG_A3XX_SP_PERFCOUNTER5_SELECT 0x00000ec9
2995
2996 #define REG_A3XX_SP_PERFCOUNTER6_SELECT 0x00000eca
2997
2998 #define REG_A3XX_SP_PERFCOUNTER7_SELECT 0x00000ecb
2999
3000 #define REG_A3XX_UNKNOWN_0EE0 0x00000ee0
3001
3002 #define REG_A3XX_UNKNOWN_0F03 0x00000f03
3003
3004 #define REG_A3XX_TP_PERFCOUNTER0_SELECT 0x00000f04
3005
3006 #define REG_A3XX_TP_PERFCOUNTER1_SELECT 0x00000f05
3007
3008 #define REG_A3XX_TP_PERFCOUNTER2_SELECT 0x00000f06
3009
3010 #define REG_A3XX_TP_PERFCOUNTER3_SELECT 0x00000f07
3011
3012 #define REG_A3XX_TP_PERFCOUNTER4_SELECT 0x00000f08
3013
3014 #define REG_A3XX_TP_PERFCOUNTER5_SELECT 0x00000f09
3015
3016 #define REG_A3XX_VGT_CL_INITIATOR 0x000021f0
3017
3018 #define REG_A3XX_VGT_EVENT_INITIATOR 0x000021f9
3019
3020 #define REG_A3XX_VGT_DRAW_INITIATOR 0x000021fc
3021 #define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK 0x0000003f
3022 #define A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT 0
3023 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE(enum pc_di_primtype val)
3024 {
3025 return ((val) << A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_PRIM_TYPE__MASK;
3026 }
3027 #define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK 0x000000c0
3028 #define A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT 6
3029 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT(enum pc_di_src_sel val)
3030 {
3031 return ((val) << A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__SHIFT) & A3XX_VGT_DRAW_INITIATOR_SOURCE_SELECT__MASK;
3032 }
3033 #define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK 0x00000600
3034 #define A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT 9
3035 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_VIS_CULL(enum pc_di_vis_cull_mode val)
3036 {
3037 return ((val) << A3XX_VGT_DRAW_INITIATOR_VIS_CULL__SHIFT) & A3XX_VGT_DRAW_INITIATOR_VIS_CULL__MASK;
3038 }
3039 #define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK 0x00000800
3040 #define A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT 11
3041 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE(enum pc_di_index_size val)
3042 {
3043 return ((val) << A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__SHIFT) & A3XX_VGT_DRAW_INITIATOR_INDEX_SIZE__MASK;
3044 }
3045 #define A3XX_VGT_DRAW_INITIATOR_NOT_EOP 0x00001000
3046 #define A3XX_VGT_DRAW_INITIATOR_SMALL_INDEX 0x00002000
3047 #define A3XX_VGT_DRAW_INITIATOR_PRE_DRAW_INITIATOR_ENABLE 0x00004000
3048 #define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK 0xff000000
3049 #define A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT 24
3050 static inline uint32_t A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES(uint32_t val)
3051 {
3052 return ((val) << A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__SHIFT) & A3XX_VGT_DRAW_INITIATOR_NUM_INSTANCES__MASK;
3053 }
3054
3055 #define REG_A3XX_VGT_IMMED_DATA 0x000021fd
3056
3057 #define REG_A3XX_TEX_SAMP_0 0x00000000
3058 #define A3XX_TEX_SAMP_0_CLAMPENABLE 0x00000001
3059 #define A3XX_TEX_SAMP_0_MIPFILTER_LINEAR 0x00000002
3060 #define A3XX_TEX_SAMP_0_XY_MAG__MASK 0x0000000c
3061 #define A3XX_TEX_SAMP_0_XY_MAG__SHIFT 2
3062 static inline uint32_t A3XX_TEX_SAMP_0_XY_MAG(enum a3xx_tex_filter val)
3063 {
3064 return ((val) << A3XX_TEX_SAMP_0_XY_MAG__SHIFT) & A3XX_TEX_SAMP_0_XY_MAG__MASK;
3065 }
3066 #define A3XX_TEX_SAMP_0_XY_MIN__MASK 0x00000030
3067 #define A3XX_TEX_SAMP_0_XY_MIN__SHIFT 4
3068 static inline uint32_t A3XX_TEX_SAMP_0_XY_MIN(enum a3xx_tex_filter val)
3069 {
3070 return ((val) << A3XX_TEX_SAMP_0_XY_MIN__SHIFT) & A3XX_TEX_SAMP_0_XY_MIN__MASK;
3071 }
3072 #define A3XX_TEX_SAMP_0_WRAP_S__MASK 0x000001c0
3073 #define A3XX_TEX_SAMP_0_WRAP_S__SHIFT 6
3074 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_S(enum a3xx_tex_clamp val)
3075 {
3076 return ((val) << A3XX_TEX_SAMP_0_WRAP_S__SHIFT) & A3XX_TEX_SAMP_0_WRAP_S__MASK;
3077 }
3078 #define A3XX_TEX_SAMP_0_WRAP_T__MASK 0x00000e00
3079 #define A3XX_TEX_SAMP_0_WRAP_T__SHIFT 9
3080 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_T(enum a3xx_tex_clamp val)
3081 {
3082 return ((val) << A3XX_TEX_SAMP_0_WRAP_T__SHIFT) & A3XX_TEX_SAMP_0_WRAP_T__MASK;
3083 }
3084 #define A3XX_TEX_SAMP_0_WRAP_R__MASK 0x00007000
3085 #define A3XX_TEX_SAMP_0_WRAP_R__SHIFT 12
3086 static inline uint32_t A3XX_TEX_SAMP_0_WRAP_R(enum a3xx_tex_clamp val)
3087 {
3088 return ((val) << A3XX_TEX_SAMP_0_WRAP_R__SHIFT) & A3XX_TEX_SAMP_0_WRAP_R__MASK;
3089 }
3090 #define A3XX_TEX_SAMP_0_ANISO__MASK 0x00038000
3091 #define A3XX_TEX_SAMP_0_ANISO__SHIFT 15
3092 static inline uint32_t A3XX_TEX_SAMP_0_ANISO(enum a3xx_tex_aniso val)
3093 {
3094 return ((val) << A3XX_TEX_SAMP_0_ANISO__SHIFT) & A3XX_TEX_SAMP_0_ANISO__MASK;
3095 }
3096 #define A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK 0x00700000
3097 #define A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT 20
3098 static inline uint32_t A3XX_TEX_SAMP_0_COMPARE_FUNC(enum adreno_compare_func val)
3099 {
3100 return ((val) << A3XX_TEX_SAMP_0_COMPARE_FUNC__SHIFT) & A3XX_TEX_SAMP_0_COMPARE_FUNC__MASK;
3101 }
3102 #define A3XX_TEX_SAMP_0_CUBEMAPSEAMLESSFILTOFF 0x01000000
3103 #define A3XX_TEX_SAMP_0_UNNORM_COORDS 0x80000000
3104
3105 #define REG_A3XX_TEX_SAMP_1 0x00000001
3106 #define A3XX_TEX_SAMP_1_LOD_BIAS__MASK 0x000007ff
3107 #define A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT 0
3108 static inline uint32_t A3XX_TEX_SAMP_1_LOD_BIAS(float val)
3109 {
3110 return ((((int32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_LOD_BIAS__SHIFT) & A3XX_TEX_SAMP_1_LOD_BIAS__MASK;
3111 }
3112 #define A3XX_TEX_SAMP_1_MAX_LOD__MASK 0x003ff000
3113 #define A3XX_TEX_SAMP_1_MAX_LOD__SHIFT 12
3114 static inline uint32_t A3XX_TEX_SAMP_1_MAX_LOD(float val)
3115 {
3116 return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MAX_LOD__SHIFT) & A3XX_TEX_SAMP_1_MAX_LOD__MASK;
3117 }
3118 #define A3XX_TEX_SAMP_1_MIN_LOD__MASK 0xffc00000
3119 #define A3XX_TEX_SAMP_1_MIN_LOD__SHIFT 22
3120 static inline uint32_t A3XX_TEX_SAMP_1_MIN_LOD(float val)
3121 {
3122 return ((((uint32_t)(val * 64.0))) << A3XX_TEX_SAMP_1_MIN_LOD__SHIFT) & A3XX_TEX_SAMP_1_MIN_LOD__MASK;
3123 }
3124
3125 #define REG_A3XX_TEX_CONST_0 0x00000000
3126 #define A3XX_TEX_CONST_0_TILE_MODE__MASK 0x00000003
3127 #define A3XX_TEX_CONST_0_TILE_MODE__SHIFT 0
3128 static inline uint32_t A3XX_TEX_CONST_0_TILE_MODE(enum a3xx_tile_mode val)
3129 {
3130 return ((val) << A3XX_TEX_CONST_0_TILE_MODE__SHIFT) & A3XX_TEX_CONST_0_TILE_MODE__MASK;
3131 }
3132 #define A3XX_TEX_CONST_0_SRGB 0x00000004
3133 #define A3XX_TEX_CONST_0_SWIZ_X__MASK 0x00000070
3134 #define A3XX_TEX_CONST_0_SWIZ_X__SHIFT 4
3135 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_X(enum a3xx_tex_swiz val)
3136 {
3137 return ((val) << A3XX_TEX_CONST_0_SWIZ_X__SHIFT) & A3XX_TEX_CONST_0_SWIZ_X__MASK;
3138 }
3139 #define A3XX_TEX_CONST_0_SWIZ_Y__MASK 0x00000380
3140 #define A3XX_TEX_CONST_0_SWIZ_Y__SHIFT 7
3141 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Y(enum a3xx_tex_swiz val)
3142 {
3143 return ((val) << A3XX_TEX_CONST_0_SWIZ_Y__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Y__MASK;
3144 }
3145 #define A3XX_TEX_CONST_0_SWIZ_Z__MASK 0x00001c00
3146 #define A3XX_TEX_CONST_0_SWIZ_Z__SHIFT 10
3147 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_Z(enum a3xx_tex_swiz val)
3148 {
3149 return ((val) << A3XX_TEX_CONST_0_SWIZ_Z__SHIFT) & A3XX_TEX_CONST_0_SWIZ_Z__MASK;
3150 }
3151 #define A3XX_TEX_CONST_0_SWIZ_W__MASK 0x0000e000
3152 #define A3XX_TEX_CONST_0_SWIZ_W__SHIFT 13
3153 static inline uint32_t A3XX_TEX_CONST_0_SWIZ_W(enum a3xx_tex_swiz val)
3154 {
3155 return ((val) << A3XX_TEX_CONST_0_SWIZ_W__SHIFT) & A3XX_TEX_CONST_0_SWIZ_W__MASK;
3156 }
3157 #define A3XX_TEX_CONST_0_MIPLVLS__MASK 0x000f0000
3158 #define A3XX_TEX_CONST_0_MIPLVLS__SHIFT 16
3159 static inline uint32_t A3XX_TEX_CONST_0_MIPLVLS(uint32_t val)
3160 {
3161 return ((val) << A3XX_TEX_CONST_0_MIPLVLS__SHIFT) & A3XX_TEX_CONST_0_MIPLVLS__MASK;
3162 }
3163 #define A3XX_TEX_CONST_0_MSAATEX__MASK 0x00300000
3164 #define A3XX_TEX_CONST_0_MSAATEX__SHIFT 20
3165 static inline uint32_t A3XX_TEX_CONST_0_MSAATEX(enum a3xx_tex_msaa val)
3166 {
3167 return ((val) << A3XX_TEX_CONST_0_MSAATEX__SHIFT) & A3XX_TEX_CONST_0_MSAATEX__MASK;
3168 }
3169 #define A3XX_TEX_CONST_0_FMT__MASK 0x1fc00000
3170 #define A3XX_TEX_CONST_0_FMT__SHIFT 22
3171 static inline uint32_t A3XX_TEX_CONST_0_FMT(enum a3xx_tex_fmt val)
3172 {
3173 return ((val) << A3XX_TEX_CONST_0_FMT__SHIFT) & A3XX_TEX_CONST_0_FMT__MASK;
3174 }
3175 #define A3XX_TEX_CONST_0_NOCONVERT 0x20000000
3176 #define A3XX_TEX_CONST_0_TYPE__MASK 0xc0000000
3177 #define A3XX_TEX_CONST_0_TYPE__SHIFT 30
3178 static inline uint32_t A3XX_TEX_CONST_0_TYPE(enum a3xx_tex_type val)
3179 {
3180 return ((val) << A3XX_TEX_CONST_0_TYPE__SHIFT) & A3XX_TEX_CONST_0_TYPE__MASK;
3181 }
3182
3183 #define REG_A3XX_TEX_CONST_1 0x00000001
3184 #define A3XX_TEX_CONST_1_HEIGHT__MASK 0x00003fff
3185 #define A3XX_TEX_CONST_1_HEIGHT__SHIFT 0
3186 static inline uint32_t A3XX_TEX_CONST_1_HEIGHT(uint32_t val)
3187 {
3188 return ((val) << A3XX_TEX_CONST_1_HEIGHT__SHIFT) & A3XX_TEX_CONST_1_HEIGHT__MASK;
3189 }
3190 #define A3XX_TEX_CONST_1_WIDTH__MASK 0x0fffc000
3191 #define A3XX_TEX_CONST_1_WIDTH__SHIFT 14
3192 static inline uint32_t A3XX_TEX_CONST_1_WIDTH(uint32_t val)
3193 {
3194 return ((val) << A3XX_TEX_CONST_1_WIDTH__SHIFT) & A3XX_TEX_CONST_1_WIDTH__MASK;
3195 }
3196 #define A3XX_TEX_CONST_1_FETCHSIZE__MASK 0xf0000000
3197 #define A3XX_TEX_CONST_1_FETCHSIZE__SHIFT 28
3198 static inline uint32_t A3XX_TEX_CONST_1_FETCHSIZE(enum a3xx_tex_fetchsize val)
3199 {
3200 return ((val) << A3XX_TEX_CONST_1_FETCHSIZE__SHIFT) & A3XX_TEX_CONST_1_FETCHSIZE__MASK;
3201 }
3202
3203 #define REG_A3XX_TEX_CONST_2 0x00000002
3204 #define A3XX_TEX_CONST_2_INDX__MASK 0x000001ff
3205 #define A3XX_TEX_CONST_2_INDX__SHIFT 0
3206 static inline uint32_t A3XX_TEX_CONST_2_INDX(uint32_t val)
3207 {
3208 return ((val) << A3XX_TEX_CONST_2_INDX__SHIFT) & A3XX_TEX_CONST_2_INDX__MASK;
3209 }
3210 #define A3XX_TEX_CONST_2_PITCH__MASK 0x3ffff000
3211 #define A3XX_TEX_CONST_2_PITCH__SHIFT 12
3212 static inline uint32_t A3XX_TEX_CONST_2_PITCH(uint32_t val)
3213 {
3214 return ((val) << A3XX_TEX_CONST_2_PITCH__SHIFT) & A3XX_TEX_CONST_2_PITCH__MASK;
3215 }
3216 #define A3XX_TEX_CONST_2_SWAP__MASK 0xc0000000
3217 #define A3XX_TEX_CONST_2_SWAP__SHIFT 30
3218 static inline uint32_t A3XX_TEX_CONST_2_SWAP(enum a3xx_color_swap val)
3219 {
3220 return ((val) << A3XX_TEX_CONST_2_SWAP__SHIFT) & A3XX_TEX_CONST_2_SWAP__MASK;
3221 }
3222
3223 #define REG_A3XX_TEX_CONST_3 0x00000003
3224 #define A3XX_TEX_CONST_3_LAYERSZ1__MASK 0x0001ffff
3225 #define A3XX_TEX_CONST_3_LAYERSZ1__SHIFT 0
3226 static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ1(uint32_t val)
3227 {
3228 assert(!(val & 0xfff));
3229 return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ1__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ1__MASK;
3230 }
3231 #define A3XX_TEX_CONST_3_DEPTH__MASK 0x0ffe0000
3232 #define A3XX_TEX_CONST_3_DEPTH__SHIFT 17
3233 static inline uint32_t A3XX_TEX_CONST_3_DEPTH(uint32_t val)
3234 {
3235 return ((val) << A3XX_TEX_CONST_3_DEPTH__SHIFT) & A3XX_TEX_CONST_3_DEPTH__MASK;
3236 }
3237 #define A3XX_TEX_CONST_3_LAYERSZ2__MASK 0xf0000000
3238 #define A3XX_TEX_CONST_3_LAYERSZ2__SHIFT 28
3239 static inline uint32_t A3XX_TEX_CONST_3_LAYERSZ2(uint32_t val)
3240 {
3241 assert(!(val & 0xfff));
3242 return ((val >> 12) << A3XX_TEX_CONST_3_LAYERSZ2__SHIFT) & A3XX_TEX_CONST_3_LAYERSZ2__MASK;
3243 }
3244
3245
3246 #endif /* A3XX_XML */