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freedreno/layout: layout simplifications and pitch from level 0 pitch
[mesa.git] / src / freedreno / registers / a4xx.xml
1 <?xml version="1.0" encoding="UTF-8"?>
2 <database xmlns="http://nouveau.freedesktop.org/"
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
5 <import file="freedreno_copyright.xml"/>
6 <import file="adreno/adreno_common.xml"/>
7 <import file="adreno/adreno_pm4.xml"/>
8
9 <enum name="a4xx_color_fmt">
10 <value name="RB4_A8_UNORM" value="0x01"/>
11 <value name="RB4_R8_UNORM" value="0x02"/>
12 <value name="RB4_R8_SNORM" value="0x03"/>
13 <value name="RB4_R8_UINT" value="0x04"/>
14 <value name="RB4_R8_SINT" value="0x05"/>
15
16 <value name="RB4_R4G4B4A4_UNORM" value="0x08"/>
17 <value name="RB4_R5G5B5A1_UNORM" value="0x0a"/>
18 <value name="RB4_R5G6B5_UNORM" value="0x0e"/>
19 <value name="RB4_R8G8_UNORM" value="0x0f"/>
20 <value name="RB4_R8G8_SNORM" value="0x10"/>
21 <value name="RB4_R8G8_UINT" value="0x11"/>
22 <value name="RB4_R8G8_SINT" value="0x12"/>
23 <value name="RB4_R16_UNORM" value="0x13"/>
24 <value name="RB4_R16_SNORM" value="0x14"/>
25 <value name="RB4_R16_FLOAT" value="0x15"/>
26 <value name="RB4_R16_UINT" value="0x16"/>
27 <value name="RB4_R16_SINT" value="0x17"/>
28
29 <value name="RB4_R8G8B8_UNORM" value="0x19"/>
30
31 <value name="RB4_R8G8B8A8_UNORM" value="0x1a"/>
32 <value name="RB4_R8G8B8A8_SNORM" value="0x1c"/>
33 <value name="RB4_R8G8B8A8_UINT" value="0x1d"/>
34 <value name="RB4_R8G8B8A8_SINT" value="0x1e"/>
35 <value name="RB4_R10G10B10A2_UNORM" value="0x1f"/>
36 <value name="RB4_R10G10B10A2_UINT" value="0x22"/>
37 <value name="RB4_R11G11B10_FLOAT" value="0x27"/>
38 <value name="RB4_R16G16_UNORM" value="0x28"/>
39 <value name="RB4_R16G16_SNORM" value="0x29"/>
40 <value name="RB4_R16G16_FLOAT" value="0x2a"/>
41 <value name="RB4_R16G16_UINT" value="0x2b"/>
42 <value name="RB4_R16G16_SINT" value="0x2c"/>
43 <value name="RB4_R32_FLOAT" value="0x2d"/>
44 <value name="RB4_R32_UINT" value="0x2e"/>
45 <value name="RB4_R32_SINT" value="0x2f"/>
46
47 <value name="RB4_R16G16B16A16_UNORM" value="0x34"/>
48 <value name="RB4_R16G16B16A16_SNORM" value="0x35"/>
49 <value name="RB4_R16G16B16A16_FLOAT" value="0x36"/>
50 <value name="RB4_R16G16B16A16_UINT" value="0x37"/>
51 <value name="RB4_R16G16B16A16_SINT" value="0x38"/>
52 <value name="RB4_R32G32_FLOAT" value="0x39"/>
53 <value name="RB4_R32G32_UINT" value="0x3a"/>
54 <value name="RB4_R32G32_SINT" value="0x3b"/>
55
56 <value name="RB4_R32G32B32A32_FLOAT" value="0x3c"/>
57 <value name="RB4_R32G32B32A32_UINT" value="0x3d"/>
58 <value name="RB4_R32G32B32A32_SINT" value="0x3e"/>
59
60 <value name="RB4_NONE" value="0xff"/>
61 </enum>
62
63 <enum name="a4xx_tile_mode">
64 <value name="TILE4_LINEAR" value="0"/>
65 <value name="TILE4_2" value="2"/>
66 <value name="TILE4_3" value="3"/>
67 </enum>
68
69 <enum name="a4xx_vtx_fmt" prefix="chipset">
70 <!-- hmm, shifted one compared to a3xx?!? -->
71 <value name="VFMT4_32_FLOAT" value="0x1"/>
72 <value name="VFMT4_32_32_FLOAT" value="0x2"/>
73 <value name="VFMT4_32_32_32_FLOAT" value="0x3"/>
74 <value name="VFMT4_32_32_32_32_FLOAT" value="0x4"/>
75
76 <value name="VFMT4_16_FLOAT" value="0x5"/>
77 <value name="VFMT4_16_16_FLOAT" value="0x6"/>
78 <value name="VFMT4_16_16_16_FLOAT" value="0x7"/>
79 <value name="VFMT4_16_16_16_16_FLOAT" value="0x8"/>
80
81 <value name="VFMT4_32_FIXED" value="0x9"/>
82 <value name="VFMT4_32_32_FIXED" value="0xa"/>
83 <value name="VFMT4_32_32_32_FIXED" value="0xb"/>
84 <value name="VFMT4_32_32_32_32_FIXED" value="0xc"/>
85
86 <value name="VFMT4_11_11_10_FLOAT" value="0xd"/>
87
88 <!-- beyond here it does not appear to be shifted -->
89 <value name="VFMT4_16_SINT" value="0x10"/>
90 <value name="VFMT4_16_16_SINT" value="0x11"/>
91 <value name="VFMT4_16_16_16_SINT" value="0x12"/>
92 <value name="VFMT4_16_16_16_16_SINT" value="0x13"/>
93 <value name="VFMT4_16_UINT" value="0x14"/>
94 <value name="VFMT4_16_16_UINT" value="0x15"/>
95 <value name="VFMT4_16_16_16_UINT" value="0x16"/>
96 <value name="VFMT4_16_16_16_16_UINT" value="0x17"/>
97 <value name="VFMT4_16_SNORM" value="0x18"/>
98 <value name="VFMT4_16_16_SNORM" value="0x19"/>
99 <value name="VFMT4_16_16_16_SNORM" value="0x1a"/>
100 <value name="VFMT4_16_16_16_16_SNORM" value="0x1b"/>
101 <value name="VFMT4_16_UNORM" value="0x1c"/>
102 <value name="VFMT4_16_16_UNORM" value="0x1d"/>
103 <value name="VFMT4_16_16_16_UNORM" value="0x1e"/>
104 <value name="VFMT4_16_16_16_16_UNORM" value="0x1f"/>
105
106 <value name="VFMT4_32_UINT" value="0x20"/>
107 <value name="VFMT4_32_32_UINT" value="0x21"/>
108 <value name="VFMT4_32_32_32_UINT" value="0x22"/>
109 <value name="VFMT4_32_32_32_32_UINT" value="0x23"/>
110 <value name="VFMT4_32_SINT" value="0x24"/>
111 <value name="VFMT4_32_32_SINT" value="0x25"/>
112 <value name="VFMT4_32_32_32_SINT" value="0x26"/>
113 <value name="VFMT4_32_32_32_32_SINT" value="0x27"/>
114
115 <value name="VFMT4_8_UINT" value="0x28"/>
116 <value name="VFMT4_8_8_UINT" value="0x29"/>
117 <value name="VFMT4_8_8_8_UINT" value="0x2a"/>
118 <value name="VFMT4_8_8_8_8_UINT" value="0x2b"/>
119 <value name="VFMT4_8_UNORM" value="0x2c"/>
120 <value name="VFMT4_8_8_UNORM" value="0x2d"/>
121 <value name="VFMT4_8_8_8_UNORM" value="0x2e"/>
122 <value name="VFMT4_8_8_8_8_UNORM" value="0x2f"/>
123 <value name="VFMT4_8_SINT" value="0x30"/>
124 <value name="VFMT4_8_8_SINT" value="0x31"/>
125 <value name="VFMT4_8_8_8_SINT" value="0x32"/>
126 <value name="VFMT4_8_8_8_8_SINT" value="0x33"/>
127 <value name="VFMT4_8_SNORM" value="0x34"/>
128 <value name="VFMT4_8_8_SNORM" value="0x35"/>
129 <value name="VFMT4_8_8_8_SNORM" value="0x36"/>
130 <value name="VFMT4_8_8_8_8_SNORM" value="0x37"/>
131
132 <value name="VFMT4_10_10_10_2_UINT" value="0x38"/>
133 <value name="VFMT4_10_10_10_2_UNORM" value="0x39"/>
134 <value name="VFMT4_10_10_10_2_SINT" value="0x3a"/>
135 <value name="VFMT4_10_10_10_2_SNORM" value="0x3b"/>
136 <value name="VFMT4_2_10_10_10_UINT" value="0x3c"/>
137 <value name="VFMT4_2_10_10_10_UNORM" value="0x3d"/>
138 <value name="VFMT4_2_10_10_10_SINT" value="0x3e"/>
139 <value name="VFMT4_2_10_10_10_SNORM" value="0x3f"/>
140
141 <value name="VFMT4_NONE" value="0xff"/>
142 </enum>
143
144 <enum name="a4xx_tex_fmt">
145 <!-- 0x00 .. 0x02 -->
146
147 <!-- 8-bit formats -->
148 <value name="TFMT4_A8_UNORM" value="0x03"/>
149 <value name="TFMT4_8_UNORM" value="0x04"/>
150 <value name="TFMT4_8_SNORM" value="0x05"/>
151 <value name="TFMT4_8_UINT" value="0x06"/>
152 <value name="TFMT4_8_SINT" value="0x07"/>
153
154 <!-- 16-bit formats -->
155 <value name="TFMT4_4_4_4_4_UNORM" value="0x08"/>
156 <value name="TFMT4_5_5_5_1_UNORM" value="0x09"/>
157 <!-- 0x0a -->
158 <value name="TFMT4_5_6_5_UNORM" value="0x0b"/>
159
160 <!-- 0x0c -->
161
162 <value name="TFMT4_L8_A8_UNORM" value="0x0d"/>
163 <value name="TFMT4_8_8_UNORM" value="0x0e"/>
164 <value name="TFMT4_8_8_SNORM" value="0x0f"/>
165 <value name="TFMT4_8_8_UINT" value="0x10"/>
166 <value name="TFMT4_8_8_SINT" value="0x11"/>
167
168 <value name="TFMT4_16_UNORM" value="0x12"/>
169 <value name="TFMT4_16_SNORM" value="0x13"/>
170 <value name="TFMT4_16_FLOAT" value="0x14"/>
171 <value name="TFMT4_16_UINT" value="0x15"/>
172 <value name="TFMT4_16_SINT" value="0x16"/>
173
174 <!-- 0x17 .. 0x1b -->
175
176 <!-- 32-bit formats -->
177 <value name="TFMT4_8_8_8_8_UNORM" value="0x1c"/>
178 <value name="TFMT4_8_8_8_8_SNORM" value="0x1d"/>
179 <value name="TFMT4_8_8_8_8_UINT" value="0x1e"/>
180 <value name="TFMT4_8_8_8_8_SINT" value="0x1f"/>
181
182 <value name="TFMT4_9_9_9_E5_FLOAT" value="0x20"/>
183 <value name="TFMT4_10_10_10_2_UNORM" value="0x21"/>
184 <value name="TFMT4_10_10_10_2_UINT" value="0x22"/>
185 <!-- 0x23 .. 0x24 -->
186 <value name="TFMT4_11_11_10_FLOAT" value="0x25"/>
187
188 <value name="TFMT4_16_16_UNORM" value="0x26"/>
189 <value name="TFMT4_16_16_SNORM" value="0x27"/>
190 <value name="TFMT4_16_16_FLOAT" value="0x28"/>
191 <value name="TFMT4_16_16_UINT" value="0x29"/>
192 <value name="TFMT4_16_16_SINT" value="0x2a"/>
193
194 <value name="TFMT4_32_FLOAT" value="0x2b"/>
195 <value name="TFMT4_32_UINT" value="0x2c"/>
196 <value name="TFMT4_32_SINT" value="0x2d"/>
197
198 <!-- 0x2e .. 0x32 -->
199
200 <!-- 64-bit formats -->
201 <value name="TFMT4_16_16_16_16_UNORM" value="0x33"/>
202 <value name="TFMT4_16_16_16_16_SNORM" value="0x34"/>
203 <value name="TFMT4_16_16_16_16_FLOAT" value="0x35"/>
204 <value name="TFMT4_16_16_16_16_UINT" value="0x36"/>
205 <value name="TFMT4_16_16_16_16_SINT" value="0x37"/>
206
207 <value name="TFMT4_32_32_FLOAT" value="0x38"/>
208 <value name="TFMT4_32_32_UINT" value="0x39"/>
209 <value name="TFMT4_32_32_SINT" value="0x3a"/>
210
211 <!-- 96-bit formats -->
212 <value name="TFMT4_32_32_32_FLOAT" value="0x3b"/>
213 <value name="TFMT4_32_32_32_UINT" value="0x3c"/>
214 <value name="TFMT4_32_32_32_SINT" value="0x3d"/>
215
216 <!-- 0x3e -->
217
218 <!-- 128-bit formats -->
219 <value name="TFMT4_32_32_32_32_FLOAT" value="0x3f"/>
220 <value name="TFMT4_32_32_32_32_UINT" value="0x40"/>
221 <value name="TFMT4_32_32_32_32_SINT" value="0x41"/>
222
223 <!-- 0x42 .. 0x46 -->
224 <value name="TFMT4_X8Z24_UNORM" value="0x47"/>
225 <!-- 0x48 .. 0x55 -->
226
227 <!-- compressed formats -->
228 <value name="TFMT4_DXT1" value="0x56"/>
229 <value name="TFMT4_DXT3" value="0x57"/>
230 <value name="TFMT4_DXT5" value="0x58"/>
231 <!-- 0x59 -->
232 <value name="TFMT4_RGTC1_UNORM" value="0x5a"/>
233 <value name="TFMT4_RGTC1_SNORM" value="0x5b"/>
234 <!-- 0x5c .. 0x5d -->
235 <value name="TFMT4_RGTC2_UNORM" value="0x5e"/>
236 <value name="TFMT4_RGTC2_SNORM" value="0x5f"/>
237 <!-- 0x60 -->
238 <value name="TFMT4_BPTC_UFLOAT" value="0x61"/>
239 <value name="TFMT4_BPTC_FLOAT" value="0x62"/>
240 <value name="TFMT4_BPTC" value="0x63"/>
241 <value name="TFMT4_ATC_RGB" value="0x64"/>
242 <value name="TFMT4_ATC_RGBA_EXPLICIT" value="0x65"/>
243 <value name="TFMT4_ATC_RGBA_INTERPOLATED" value="0x66"/>
244 <value name="TFMT4_ETC2_RG11_UNORM" value="0x67"/>
245 <value name="TFMT4_ETC2_RG11_SNORM" value="0x68"/>
246 <value name="TFMT4_ETC2_R11_UNORM" value="0x69"/>
247 <value name="TFMT4_ETC2_R11_SNORM" value="0x6a"/>
248 <value name="TFMT4_ETC1" value="0x6b"/>
249 <value name="TFMT4_ETC2_RGB8" value="0x6c"/>
250 <value name="TFMT4_ETC2_RGBA8" value="0x6d"/>
251 <value name="TFMT4_ETC2_RGB8A1" value="0x6e"/>
252 <value name="TFMT4_ASTC_4x4" value="0x6f"/>
253 <value name="TFMT4_ASTC_5x4" value="0x70"/>
254 <value name="TFMT4_ASTC_5x5" value="0x71"/>
255 <value name="TFMT4_ASTC_6x5" value="0x72"/>
256 <value name="TFMT4_ASTC_6x6" value="0x73"/>
257 <value name="TFMT4_ASTC_8x5" value="0x74"/>
258 <value name="TFMT4_ASTC_8x6" value="0x75"/>
259 <value name="TFMT4_ASTC_8x8" value="0x76"/>
260 <value name="TFMT4_ASTC_10x5" value="0x77"/>
261 <value name="TFMT4_ASTC_10x6" value="0x78"/>
262 <value name="TFMT4_ASTC_10x8" value="0x79"/>
263 <value name="TFMT4_ASTC_10x10" value="0x7a"/>
264 <value name="TFMT4_ASTC_12x10" value="0x7b"/>
265 <value name="TFMT4_ASTC_12x12" value="0x7c"/>
266 <!-- 0x7d .. 0x7f -->
267
268 <value name="TFMT4_NONE" value="0xff"/>
269 </enum>
270
271 <enum name="a4xx_depth_format">
272 <value name="DEPTH4_NONE" value="0"/>
273 <value name="DEPTH4_16" value="1"/>
274 <value name="DEPTH4_24_8" value="2"/>
275 <value name="DEPTH4_32" value="3"/>
276 </enum>
277
278 <!--
279 NOTE counters extracted from test-perf log with the following awful
280 script:
281 ##################
282 #!/bin/bash
283
284 log=$1
285
286 grep -F "counter
287 countable
288 group" $log | grep -v gl > shortlist.txt
289
290 countable=""
291 IFS=$'\n'; for line in $(cat shortlist.txt); do
292 # parse ######### group[$n]: $name
293 l=${line########### group}
294 if [ $l != $line ]; then
295 group=`echo $line | awk '{print $3}'`
296 echo "Group: $group"
297 continue
298 fi
299 # parse ######### counter[$n]: $name
300 l=${line########### counter}
301 if [ $l != $line ]; then
302 countable=`echo $line | awk '{print $3}'`
303 #echo " Countable: $countable"
304 continue
305 fi
306 # parse countable:
307 l=${line## countable:}
308 if [ $l != $line ]; then
309 val=`echo $line | awk '{print $2}'`
310 echo "<value value=\"$val\" name=\"$countable\"/>"
311 fi
312
313 done
314 ##################
315 -->
316 <enum name="a4xx_ccu_perfcounter_select">
317 <value value="0" name="CCU_BUSY_CYCLES"/>
318 <value value="2" name="CCU_RB_DEPTH_RETURN_STALL"/>
319 <value value="3" name="CCU_RB_COLOR_RETURN_STALL"/>
320 <value value="6" name="CCU_DEPTH_BLOCKS"/>
321 <value value="7" name="CCU_COLOR_BLOCKS"/>
322 <value value="8" name="CCU_DEPTH_BLOCK_HIT"/>
323 <value value="9" name="CCU_COLOR_BLOCK_HIT"/>
324 <value value="10" name="CCU_DEPTH_FLAG1_COUNT"/>
325 <value value="11" name="CCU_DEPTH_FLAG2_COUNT"/>
326 <value value="12" name="CCU_DEPTH_FLAG3_COUNT"/>
327 <value value="13" name="CCU_DEPTH_FLAG4_COUNT"/>
328 <value value="14" name="CCU_COLOR_FLAG1_COUNT"/>
329 <value value="15" name="CCU_COLOR_FLAG2_COUNT"/>
330 <value value="16" name="CCU_COLOR_FLAG3_COUNT"/>
331 <value value="17" name="CCU_COLOR_FLAG4_COUNT"/>
332 <value value="18" name="CCU_PARTIAL_BLOCK_READ"/>
333 </enum>
334
335 <!--
336 NOTE other than CP_ALWAYS_COUNT (which is the only one we use so far),
337 on a3xx the countable #'s from AMD_performance_monitor disagreed with
338 TRM. All these #'s for a4xx come from AMD_performance_monitor, so
339 perhaps they should be taken with a grain of salt
340 -->
341 <enum name="a4xx_cp_perfcounter_select">
342 <!-- first ctr at least seems same as a3xx, so we can measure freq -->
343 <value value="0" name="CP_ALWAYS_COUNT"/>
344 <value value="1" name="CP_BUSY"/>
345 <value value="2" name="CP_PFP_IDLE"/>
346 <value value="3" name="CP_PFP_BUSY_WORKING"/>
347 <value value="4" name="CP_PFP_STALL_CYCLES_ANY"/>
348 <value value="5" name="CP_PFP_STARVE_CYCLES_ANY"/>
349 <value value="6" name="CP_PFP_STARVED_PER_LOAD_ADDR"/>
350 <value value="7" name="CP_PFP_STALLED_PER_STORE_ADDR"/>
351 <value value="8" name="CP_PFP_PC_PROFILE"/>
352 <value value="9" name="CP_PFP_MATCH_PM4_PKT_PROFILE"/>
353 <value value="10" name="CP_PFP_COND_INDIRECT_DISCARDED"/>
354 <value value="11" name="CP_LONG_RESUMPTIONS"/>
355 <value value="12" name="CP_RESUME_CYCLES"/>
356 <value value="13" name="CP_RESUME_TO_BOUNDARY_CYCLES"/>
357 <value value="14" name="CP_LONG_PREEMPTIONS"/>
358 <value value="15" name="CP_PREEMPT_CYCLES"/>
359 <value value="16" name="CP_PREEMPT_TO_BOUNDARY_CYCLES"/>
360 <value value="17" name="CP_ME_FIFO_EMPTY_PFP_IDLE"/>
361 <value value="18" name="CP_ME_FIFO_EMPTY_PFP_BUSY"/>
362 <value value="19" name="CP_ME_FIFO_NOT_EMPTY_NOT_FULL"/>
363 <value value="20" name="CP_ME_FIFO_FULL_ME_BUSY"/>
364 <value value="21" name="CP_ME_FIFO_FULL_ME_NON_WORKING"/>
365 <value value="22" name="CP_ME_WAITING_FOR_PACKETS"/>
366 <value value="23" name="CP_ME_BUSY_WORKING"/>
367 <value value="24" name="CP_ME_STARVE_CYCLES_ANY"/>
368 <value value="25" name="CP_ME_STARVE_CYCLES_PER_PROFILE"/>
369 <value value="26" name="CP_ME_STALL_CYCLES_PER_PROFILE"/>
370 <value value="27" name="CP_ME_PC_PROFILE"/>
371 <value value="28" name="CP_RCIU_FIFO_EMPTY"/>
372 <value value="29" name="CP_RCIU_FIFO_NOT_EMPTY_NOT_FULL"/>
373 <value value="30" name="CP_RCIU_FIFO_FULL"/>
374 <value value="31" name="CP_RCIU_FIFO_FULL_NO_CONTEXT"/>
375 <value value="32" name="CP_RCIU_FIFO_FULL_AHB_MASTER"/>
376 <value value="33" name="CP_RCIU_FIFO_FULL_OTHER"/>
377 <value value="34" name="CP_AHB_IDLE"/>
378 <value value="35" name="CP_AHB_STALL_ON_GRANT_NO_SPLIT"/>
379 <value value="36" name="CP_AHB_STALL_ON_GRANT_SPLIT"/>
380 <value value="37" name="CP_AHB_STALL_ON_GRANT_SPLIT_PROFILE"/>
381 <value value="38" name="CP_AHB_BUSY_WORKING"/>
382 <value value="39" name="CP_AHB_BUSY_STALL_ON_HRDY"/>
383 <value value="40" name="CP_AHB_BUSY_STALL_ON_HRDY_PROFILE"/>
384 </enum>
385
386 <enum name="a4xx_gras_ras_perfcounter_select">
387 <value value="0" name="RAS_SUPER_TILES"/>
388 <value value="1" name="RAS_8X8_TILES"/>
389 <value value="2" name="RAS_4X4_TILES"/>
390 <value value="3" name="RAS_BUSY_CYCLES"/>
391 <value value="4" name="RAS_STALL_CYCLES_BY_RB"/>
392 <value value="5" name="RAS_STALL_CYCLES_BY_VSC"/>
393 <value value="6" name="RAS_STARVE_CYCLES_BY_TSE"/>
394 <value value="7" name="RAS_SUPERTILE_CYCLES"/>
395 <value value="8" name="RAS_TILE_CYCLES"/>
396 <value value="9" name="RAS_FULLY_COVERED_SUPER_TILES"/>
397 <value value="10" name="RAS_FULLY_COVERED_8X8_TILES"/>
398 <value value="11" name="RAS_4X4_PRIM"/>
399 <value value="12" name="RAS_8X4_4X8_PRIM"/>
400 <value value="13" name="RAS_8X8_PRIM"/>
401 </enum>
402
403 <enum name="a4xx_gras_tse_perfcounter_select">
404 <value value="0" name="TSE_INPUT_PRIM"/>
405 <value value="1" name="TSE_INPUT_NULL_PRIM"/>
406 <value value="2" name="TSE_TRIVAL_REJ_PRIM"/>
407 <value value="3" name="TSE_CLIPPED_PRIM"/>
408 <value value="4" name="TSE_NEW_PRIM"/>
409 <value value="5" name="TSE_ZERO_AREA_PRIM"/>
410 <value value="6" name="TSE_FACENESS_CULLED_PRIM"/>
411 <value value="7" name="TSE_ZERO_PIXEL_PRIM"/>
412 <value value="8" name="TSE_OUTPUT_NULL_PRIM"/>
413 <value value="9" name="TSE_OUTPUT_VISIBLE_PRIM"/>
414 <value value="10" name="TSE_PRE_CLIP_PRIM"/>
415 <value value="11" name="TSE_POST_CLIP_PRIM"/>
416 <value value="12" name="TSE_BUSY_CYCLES"/>
417 <value value="13" name="TSE_PC_STARVE"/>
418 <value value="14" name="TSE_RAS_STALL"/>
419 <value value="15" name="TSE_STALL_BARYPLANE_FIFO_FULL"/>
420 <value value="16" name="TSE_STALL_ZPLANE_FIFO_FULL"/>
421 </enum>
422
423 <enum name="a4xx_hlsq_perfcounter_select">
424 <value value="0" name="HLSQ_SP_VS_STAGE_CONSTANT"/>
425 <value value="1" name="HLSQ_SP_VS_STAGE_INSTRUCTIONS"/>
426 <value value="2" name="HLSQ_SP_FS_STAGE_CONSTANT"/>
427 <value value="3" name="HLSQ_SP_FS_STAGE_INSTRUCTIONS"/>
428 <value value="4" name="HLSQ_TP_STATE"/>
429 <value value="5" name="HLSQ_QUADS"/>
430 <value value="6" name="HLSQ_PIXELS"/>
431 <value value="7" name="HLSQ_VERTICES"/>
432 <value value="13" name="HLSQ_SP_VS_STAGE_DATA_BYTES"/>
433 <value value="14" name="HLSQ_SP_FS_STAGE_DATA_BYTES"/>
434 <value value="15" name="HLSQ_BUSY_CYCLES"/>
435 <value value="16" name="HLSQ_STALL_CYCLES_SP_STATE"/>
436 <value value="17" name="HLSQ_STALL_CYCLES_SP_VS_STAGE"/>
437 <value value="18" name="HLSQ_STALL_CYCLES_SP_FS_STAGE"/>
438 <value value="19" name="HLSQ_STALL_CYCLES_UCHE"/>
439 <value value="20" name="HLSQ_RBBM_LOAD_CYCLES"/>
440 <value value="21" name="HLSQ_DI_TO_VS_START_SP"/>
441 <value value="22" name="HLSQ_DI_TO_FS_START_SP"/>
442 <value value="23" name="HLSQ_VS_STAGE_START_TO_DONE_SP"/>
443 <value value="24" name="HLSQ_FS_STAGE_START_TO_DONE_SP"/>
444 <value value="25" name="HLSQ_SP_STATE_COPY_CYCLES_VS_STAGE"/>
445 <value value="26" name="HLSQ_SP_STATE_COPY_CYCLES_FS_STAGE"/>
446 <value value="27" name="HLSQ_UCHE_LATENCY_CYCLES"/>
447 <value value="28" name="HLSQ_UCHE_LATENCY_COUNT"/>
448 <value value="29" name="HLSQ_STARVE_CYCLES_VFD"/>
449 </enum>
450
451 <enum name="a4xx_pc_perfcounter_select">
452 <value value="0" name="PC_VIS_STREAMS_LOADED"/>
453 <value value="2" name="PC_VPC_PRIMITIVES"/>
454 <value value="3" name="PC_DEAD_PRIM"/>
455 <value value="4" name="PC_LIVE_PRIM"/>
456 <value value="5" name="PC_DEAD_DRAWCALLS"/>
457 <value value="6" name="PC_LIVE_DRAWCALLS"/>
458 <value value="7" name="PC_VERTEX_MISSES"/>
459 <value value="9" name="PC_STALL_CYCLES_VFD"/>
460 <value value="10" name="PC_STALL_CYCLES_TSE"/>
461 <value value="11" name="PC_STALL_CYCLES_UCHE"/>
462 <value value="12" name="PC_WORKING_CYCLES"/>
463 <value value="13" name="PC_IA_VERTICES"/>
464 <value value="14" name="PC_GS_PRIMITIVES"/>
465 <value value="15" name="PC_HS_INVOCATIONS"/>
466 <value value="16" name="PC_DS_INVOCATIONS"/>
467 <value value="17" name="PC_DS_PRIMITIVES"/>
468 <value value="20" name="PC_STARVE_CYCLES_FOR_INDEX"/>
469 <value value="21" name="PC_STARVE_CYCLES_FOR_TESS_FACTOR"/>
470 <value value="22" name="PC_STARVE_CYCLES_FOR_VIZ_STREAM"/>
471 <value value="23" name="PC_STALL_CYCLES_TESS"/>
472 <value value="24" name="PC_STARVE_CYCLES_FOR_POSITION"/>
473 <value value="25" name="PC_MODE0_DRAWCALL"/>
474 <value value="26" name="PC_MODE1_DRAWCALL"/>
475 <value value="27" name="PC_MODE2_DRAWCALL"/>
476 <value value="28" name="PC_MODE3_DRAWCALL"/>
477 <value value="29" name="PC_MODE4_DRAWCALL"/>
478 <value value="30" name="PC_PREDICATED_DEAD_DRAWCALL"/>
479 <value value="31" name="PC_STALL_CYCLES_BY_TSE_ONLY"/>
480 <value value="32" name="PC_STALL_CYCLES_BY_VPC_ONLY"/>
481 <value value="33" name="PC_VPC_POS_DATA_TRANSACTION"/>
482 <value value="34" name="PC_BUSY_CYCLES"/>
483 <value value="35" name="PC_STARVE_CYCLES_DI"/>
484 <value value="36" name="PC_STALL_CYCLES_VPC"/>
485 <value value="37" name="TESS_WORKING_CYCLES"/>
486 <value value="38" name="TESS_NUM_CYCLES_SETUP_WORKING"/>
487 <value value="39" name="TESS_NUM_CYCLES_PTGEN_WORKING"/>
488 <value value="40" name="TESS_NUM_CYCLES_CONNGEN_WORKING"/>
489 <value value="41" name="TESS_BUSY_CYCLES"/>
490 <value value="42" name="TESS_STARVE_CYCLES_PC"/>
491 <value value="43" name="TESS_STALL_CYCLES_PC"/>
492 </enum>
493
494 <enum name="a4xx_pwr_perfcounter_select">
495 <!-- NOTE not actually used.. see RBBM_RBBM_CTL.RESET_PWR_CTR0/1 -->
496 <value value="0" name="PWR_CORE_CLOCK_CYCLES"/>
497 <value value="1" name="PWR_BUSY_CLOCK_CYCLES"/>
498 </enum>
499
500 <enum name="a4xx_rb_perfcounter_select">
501 <value value="0" name="RB_BUSY_CYCLES"/>
502 <value value="1" name="RB_BUSY_CYCLES_BINNING"/>
503 <value value="2" name="RB_BUSY_CYCLES_RENDERING"/>
504 <value value="3" name="RB_BUSY_CYCLES_RESOLVE"/>
505 <value value="4" name="RB_STARVE_CYCLES_BY_SP"/>
506 <value value="5" name="RB_STARVE_CYCLES_BY_RAS"/>
507 <value value="6" name="RB_STARVE_CYCLES_BY_MARB"/>
508 <value value="7" name="RB_STALL_CYCLES_BY_MARB"/>
509 <value value="8" name="RB_STALL_CYCLES_BY_HLSQ"/>
510 <value value="9" name="RB_RB_RB_MARB_DATA"/>
511 <value value="10" name="RB_SP_RB_QUAD"/>
512 <value value="11" name="RB_RAS_RB_Z_QUADS"/>
513 <value value="12" name="RB_GMEM_CH0_READ"/>
514 <value value="13" name="RB_GMEM_CH1_READ"/>
515 <value value="14" name="RB_GMEM_CH0_WRITE"/>
516 <value value="15" name="RB_GMEM_CH1_WRITE"/>
517 <value value="16" name="RB_CP_CONTEXT_DONE"/>
518 <value value="17" name="RB_CP_CACHE_FLUSH"/>
519 <value value="18" name="RB_CP_ZPASS_DONE"/>
520 <value value="19" name="RB_STALL_FIFO0_FULL"/>
521 <value value="20" name="RB_STALL_FIFO1_FULL"/>
522 <value value="21" name="RB_STALL_FIFO2_FULL"/>
523 <value value="22" name="RB_STALL_FIFO3_FULL"/>
524 <value value="23" name="RB_RB_HLSQ_TRANSACTIONS"/>
525 <value value="24" name="RB_Z_READ"/>
526 <value value="25" name="RB_Z_WRITE"/>
527 <value value="26" name="RB_C_READ"/>
528 <value value="27" name="RB_C_WRITE"/>
529 <value value="28" name="RB_C_READ_LATENCY"/>
530 <value value="29" name="RB_Z_READ_LATENCY"/>
531 <value value="30" name="RB_STALL_BY_UCHE"/>
532 <value value="31" name="RB_MARB_UCHE_TRANSACTIONS"/>
533 <value value="32" name="RB_CACHE_STALL_MISS"/>
534 <value value="33" name="RB_CACHE_STALL_FIFO_FULL"/>
535 <value value="34" name="RB_8BIT_BLENDER_UNITS_ACTIVE"/>
536 <value value="35" name="RB_16BIT_BLENDER_UNITS_ACTIVE"/>
537 <value value="36" name="RB_SAMPLER_UNITS_ACTIVE"/>
538 <value value="38" name="RB_TOTAL_PASS"/>
539 <value value="39" name="RB_Z_PASS"/>
540 <value value="40" name="RB_Z_FAIL"/>
541 <value value="41" name="RB_S_FAIL"/>
542 <value value="42" name="RB_POWER0"/>
543 <value value="43" name="RB_POWER1"/>
544 <value value="44" name="RB_POWER2"/>
545 <value value="45" name="RB_POWER3"/>
546 <value value="46" name="RB_POWER4"/>
547 <value value="47" name="RB_POWER5"/>
548 <value value="48" name="RB_POWER6"/>
549 <value value="49" name="RB_POWER7"/>
550 </enum>
551
552 <enum name="a4xx_rbbm_perfcounter_select">
553 <value value="0" name="RBBM_ALWAYS_ON"/>
554 <value value="1" name="RBBM_VBIF_BUSY"/>
555 <value value="2" name="RBBM_TSE_BUSY"/>
556 <value value="3" name="RBBM_RAS_BUSY"/>
557 <value value="4" name="RBBM_PC_DCALL_BUSY"/>
558 <value value="5" name="RBBM_PC_VSD_BUSY"/>
559 <value value="6" name="RBBM_VFD_BUSY"/>
560 <value value="7" name="RBBM_VPC_BUSY"/>
561 <value value="8" name="RBBM_UCHE_BUSY"/>
562 <value value="9" name="RBBM_VSC_BUSY"/>
563 <value value="10" name="RBBM_HLSQ_BUSY"/>
564 <value value="11" name="RBBM_ANY_RB_BUSY"/>
565 <value value="12" name="RBBM_ANY_TPL1_BUSY"/>
566 <value value="13" name="RBBM_ANY_SP_BUSY"/>
567 <value value="14" name="RBBM_ANY_MARB_BUSY"/>
568 <value value="15" name="RBBM_ANY_ARB_BUSY"/>
569 <value value="16" name="RBBM_AHB_STATUS_BUSY"/>
570 <value value="17" name="RBBM_AHB_STATUS_STALLED"/>
571 <value value="18" name="RBBM_AHB_STATUS_TXFR"/>
572 <value value="19" name="RBBM_AHB_STATUS_TXFR_SPLIT"/>
573 <value value="20" name="RBBM_AHB_STATUS_TXFR_ERROR"/>
574 <value value="21" name="RBBM_AHB_STATUS_LONG_STALL"/>
575 <value value="22" name="RBBM_STATUS_MASKED"/>
576 <value value="23" name="RBBM_CP_BUSY_GFX_CORE_IDLE"/>
577 <value value="24" name="RBBM_TESS_BUSY"/>
578 <value value="25" name="RBBM_COM_BUSY"/>
579 <value value="32" name="RBBM_DCOM_BUSY"/>
580 <value value="33" name="RBBM_ANY_CCU_BUSY"/>
581 <value value="34" name="RBBM_DPM_BUSY"/>
582 </enum>
583
584 <enum name="a4xx_sp_perfcounter_select">
585 <value value="0" name="SP_LM_LOAD_INSTRUCTIONS"/>
586 <value value="1" name="SP_LM_STORE_INSTRUCTIONS"/>
587 <value value="2" name="SP_LM_ATOMICS"/>
588 <value value="3" name="SP_GM_LOAD_INSTRUCTIONS"/>
589 <value value="4" name="SP_GM_STORE_INSTRUCTIONS"/>
590 <value value="5" name="SP_GM_ATOMICS"/>
591 <value value="6" name="SP_VS_STAGE_TEX_INSTRUCTIONS"/>
592 <value value="7" name="SP_VS_STAGE_CFLOW_INSTRUCTIONS"/>
593 <value value="8" name="SP_VS_STAGE_EFU_INSTRUCTIONS"/>
594 <value value="9" name="SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/>
595 <value value="10" name="SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/>
596 <value value="11" name="SP_FS_STAGE_TEX_INSTRUCTIONS"/>
597 <value value="12" name="SP_FS_STAGE_CFLOW_INSTRUCTIONS"/>
598 <value value="13" name="SP_FS_STAGE_EFU_INSTRUCTIONS"/>
599 <value value="14" name="SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/>
600 <value value="15" name="SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/>
601 <value value="17" name="SP_VS_INSTRUCTIONS"/>
602 <value value="18" name="SP_FS_INSTRUCTIONS"/>
603 <value value="19" name="SP_ADDR_LOCK_COUNT"/>
604 <value value="20" name="SP_UCHE_READ_TRANS"/>
605 <value value="21" name="SP_UCHE_WRITE_TRANS"/>
606 <value value="22" name="SP_EXPORT_VPC_TRANS"/>
607 <value value="23" name="SP_EXPORT_RB_TRANS"/>
608 <value value="24" name="SP_PIXELS_KILLED"/>
609 <value value="25" name="SP_ICL1_REQUESTS"/>
610 <value value="26" name="SP_ICL1_MISSES"/>
611 <value value="27" name="SP_ICL0_REQUESTS"/>
612 <value value="28" name="SP_ICL0_MISSES"/>
613 <value value="29" name="SP_ALU_WORKING_CYCLES"/>
614 <value value="30" name="SP_EFU_WORKING_CYCLES"/>
615 <value value="31" name="SP_STALL_CYCLES_BY_VPC"/>
616 <value value="32" name="SP_STALL_CYCLES_BY_TP"/>
617 <value value="33" name="SP_STALL_CYCLES_BY_UCHE"/>
618 <value value="34" name="SP_STALL_CYCLES_BY_RB"/>
619 <value value="35" name="SP_BUSY_CYCLES"/>
620 <value value="36" name="SP_HS_INSTRUCTIONS"/>
621 <value value="37" name="SP_DS_INSTRUCTIONS"/>
622 <value value="38" name="SP_GS_INSTRUCTIONS"/>
623 <value value="39" name="SP_CS_INSTRUCTIONS"/>
624 <value value="40" name="SP_SCHEDULER_NON_WORKING"/>
625 <value value="41" name="SP_WAVE_CONTEXTS"/>
626 <value value="42" name="SP_WAVE_CONTEXT_CYCLES"/>
627 <value value="43" name="SP_POWER0"/>
628 <value value="44" name="SP_POWER1"/>
629 <value value="45" name="SP_POWER2"/>
630 <value value="46" name="SP_POWER3"/>
631 <value value="47" name="SP_POWER4"/>
632 <value value="48" name="SP_POWER5"/>
633 <value value="49" name="SP_POWER6"/>
634 <value value="50" name="SP_POWER7"/>
635 <value value="51" name="SP_POWER8"/>
636 <value value="52" name="SP_POWER9"/>
637 <value value="53" name="SP_POWER10"/>
638 <value value="54" name="SP_POWER11"/>
639 <value value="55" name="SP_POWER12"/>
640 <value value="56" name="SP_POWER13"/>
641 <value value="57" name="SP_POWER14"/>
642 <value value="58" name="SP_POWER15"/>
643 </enum>
644
645 <enum name="a4xx_tp_perfcounter_select">
646 <value value="0" name="TP_L1_REQUESTS"/>
647 <value value="1" name="TP_L1_MISSES"/>
648 <value value="8" name="TP_QUADS_OFFSET"/>
649 <value value="9" name="TP_QUAD_SHADOW"/>
650 <value value="10" name="TP_QUADS_ARRAY"/>
651 <value value="11" name="TP_QUADS_GRADIENT"/>
652 <value value="12" name="TP_QUADS_1D2D"/>
653 <value value="13" name="TP_QUADS_3DCUBE"/>
654 <value value="16" name="TP_BUSY_CYCLES"/>
655 <value value="17" name="TP_STALL_CYCLES_BY_ARB"/>
656 <value value="20" name="TP_STATE_CACHE_REQUESTS"/>
657 <value value="21" name="TP_STATE_CACHE_MISSES"/>
658 <value value="22" name="TP_POWER0"/>
659 <value value="23" name="TP_POWER1"/>
660 <value value="24" name="TP_POWER2"/>
661 <value value="25" name="TP_POWER3"/>
662 <value value="26" name="TP_POWER4"/>
663 <value value="27" name="TP_POWER5"/>
664 <value value="28" name="TP_POWER6"/>
665 <value value="29" name="TP_POWER7"/>
666 </enum>
667
668 <enum name="a4xx_uche_perfcounter_select">
669 <value value="0" name="UCHE_VBIF_READ_BEATS_TP"/>
670 <value value="1" name="UCHE_VBIF_READ_BEATS_VFD"/>
671 <value value="2" name="UCHE_VBIF_READ_BEATS_HLSQ"/>
672 <value value="3" name="UCHE_VBIF_READ_BEATS_MARB"/>
673 <value value="4" name="UCHE_VBIF_READ_BEATS_SP"/>
674 <value value="5" name="UCHE_READ_REQUESTS_TP"/>
675 <value value="6" name="UCHE_READ_REQUESTS_VFD"/>
676 <value value="7" name="UCHE_READ_REQUESTS_HLSQ"/>
677 <value value="8" name="UCHE_READ_REQUESTS_MARB"/>
678 <value value="9" name="UCHE_READ_REQUESTS_SP"/>
679 <value value="10" name="UCHE_WRITE_REQUESTS_MARB"/>
680 <value value="11" name="UCHE_WRITE_REQUESTS_SP"/>
681 <value value="12" name="UCHE_TAG_CHECK_FAILS"/>
682 <value value="13" name="UCHE_EVICTS"/>
683 <value value="14" name="UCHE_FLUSHES"/>
684 <value value="15" name="UCHE_VBIF_LATENCY_CYCLES"/>
685 <value value="16" name="UCHE_VBIF_LATENCY_SAMPLES"/>
686 <value value="17" name="UCHE_BUSY_CYCLES"/>
687 <value value="18" name="UCHE_VBIF_READ_BEATS_PC"/>
688 <value value="19" name="UCHE_READ_REQUESTS_PC"/>
689 <value value="20" name="UCHE_WRITE_REQUESTS_VPC"/>
690 <value value="21" name="UCHE_STALL_BY_VBIF"/>
691 <value value="22" name="UCHE_WRITE_REQUESTS_VSC"/>
692 <value value="23" name="UCHE_POWER0"/>
693 <value value="24" name="UCHE_POWER1"/>
694 <value value="25" name="UCHE_POWER2"/>
695 <value value="26" name="UCHE_POWER3"/>
696 <value value="27" name="UCHE_POWER4"/>
697 <value value="28" name="UCHE_POWER5"/>
698 <value value="29" name="UCHE_POWER6"/>
699 <value value="30" name="UCHE_POWER7"/>
700 </enum>
701
702 <enum name="a4xx_vbif_perfcounter_select">
703 <value value="0" name="AXI_READ_REQUESTS_ID_0"/>
704 <value value="1" name="AXI_READ_REQUESTS_ID_1"/>
705 <value value="2" name="AXI_READ_REQUESTS_ID_2"/>
706 <value value="3" name="AXI_READ_REQUESTS_ID_3"/>
707 <value value="4" name="AXI_READ_REQUESTS_ID_4"/>
708 <value value="5" name="AXI_READ_REQUESTS_ID_5"/>
709 <value value="6" name="AXI_READ_REQUESTS_ID_6"/>
710 <value value="7" name="AXI_READ_REQUESTS_ID_7"/>
711 <value value="8" name="AXI_READ_REQUESTS_ID_8"/>
712 <value value="9" name="AXI_READ_REQUESTS_ID_9"/>
713 <value value="10" name="AXI_READ_REQUESTS_ID_10"/>
714 <value value="11" name="AXI_READ_REQUESTS_ID_11"/>
715 <value value="12" name="AXI_READ_REQUESTS_ID_12"/>
716 <value value="13" name="AXI_READ_REQUESTS_ID_13"/>
717 <value value="14" name="AXI_READ_REQUESTS_ID_14"/>
718 <value value="15" name="AXI_READ_REQUESTS_ID_15"/>
719 <value value="16" name="AXI0_READ_REQUESTS_TOTAL"/>
720 <value value="17" name="AXI1_READ_REQUESTS_TOTAL"/>
721 <value value="18" name="AXI2_READ_REQUESTS_TOTAL"/>
722 <value value="19" name="AXI3_READ_REQUESTS_TOTAL"/>
723 <value value="20" name="AXI_READ_REQUESTS_TOTAL"/>
724 <value value="21" name="AXI_WRITE_REQUESTS_ID_0"/>
725 <value value="22" name="AXI_WRITE_REQUESTS_ID_1"/>
726 <value value="23" name="AXI_WRITE_REQUESTS_ID_2"/>
727 <value value="24" name="AXI_WRITE_REQUESTS_ID_3"/>
728 <value value="25" name="AXI_WRITE_REQUESTS_ID_4"/>
729 <value value="26" name="AXI_WRITE_REQUESTS_ID_5"/>
730 <value value="27" name="AXI_WRITE_REQUESTS_ID_6"/>
731 <value value="28" name="AXI_WRITE_REQUESTS_ID_7"/>
732 <value value="29" name="AXI_WRITE_REQUESTS_ID_8"/>
733 <value value="30" name="AXI_WRITE_REQUESTS_ID_9"/>
734 <value value="31" name="AXI_WRITE_REQUESTS_ID_10"/>
735 <value value="32" name="AXI_WRITE_REQUESTS_ID_11"/>
736 <value value="33" name="AXI_WRITE_REQUESTS_ID_12"/>
737 <value value="34" name="AXI_WRITE_REQUESTS_ID_13"/>
738 <value value="35" name="AXI_WRITE_REQUESTS_ID_14"/>
739 <value value="36" name="AXI_WRITE_REQUESTS_ID_15"/>
740 <value value="37" name="AXI0_WRITE_REQUESTS_TOTAL"/>
741 <value value="38" name="AXI1_WRITE_REQUESTS_TOTAL"/>
742 <value value="39" name="AXI2_WRITE_REQUESTS_TOTAL"/>
743 <value value="40" name="AXI3_WRITE_REQUESTS_TOTAL"/>
744 <value value="41" name="AXI_WRITE_REQUESTS_TOTAL"/>
745 <value value="42" name="AXI_TOTAL_REQUESTS"/>
746 <value value="43" name="AXI_READ_DATA_BEATS_ID_0"/>
747 <value value="44" name="AXI_READ_DATA_BEATS_ID_1"/>
748 <value value="45" name="AXI_READ_DATA_BEATS_ID_2"/>
749 <value value="46" name="AXI_READ_DATA_BEATS_ID_3"/>
750 <value value="47" name="AXI_READ_DATA_BEATS_ID_4"/>
751 <value value="48" name="AXI_READ_DATA_BEATS_ID_5"/>
752 <value value="49" name="AXI_READ_DATA_BEATS_ID_6"/>
753 <value value="50" name="AXI_READ_DATA_BEATS_ID_7"/>
754 <value value="51" name="AXI_READ_DATA_BEATS_ID_8"/>
755 <value value="52" name="AXI_READ_DATA_BEATS_ID_9"/>
756 <value value="53" name="AXI_READ_DATA_BEATS_ID_10"/>
757 <value value="54" name="AXI_READ_DATA_BEATS_ID_11"/>
758 <value value="55" name="AXI_READ_DATA_BEATS_ID_12"/>
759 <value value="56" name="AXI_READ_DATA_BEATS_ID_13"/>
760 <value value="57" name="AXI_READ_DATA_BEATS_ID_14"/>
761 <value value="58" name="AXI_READ_DATA_BEATS_ID_15"/>
762 <value value="59" name="AXI0_READ_DATA_BEATS_TOTAL"/>
763 <value value="60" name="AXI1_READ_DATA_BEATS_TOTAL"/>
764 <value value="61" name="AXI2_READ_DATA_BEATS_TOTAL"/>
765 <value value="62" name="AXI3_READ_DATA_BEATS_TOTAL"/>
766 <value value="63" name="AXI_READ_DATA_BEATS_TOTAL"/>
767 <value value="64" name="AXI_WRITE_DATA_BEATS_ID_0"/>
768 <value value="65" name="AXI_WRITE_DATA_BEATS_ID_1"/>
769 <value value="66" name="AXI_WRITE_DATA_BEATS_ID_2"/>
770 <value value="67" name="AXI_WRITE_DATA_BEATS_ID_3"/>
771 <value value="68" name="AXI_WRITE_DATA_BEATS_ID_4"/>
772 <value value="69" name="AXI_WRITE_DATA_BEATS_ID_5"/>
773 <value value="70" name="AXI_WRITE_DATA_BEATS_ID_6"/>
774 <value value="71" name="AXI_WRITE_DATA_BEATS_ID_7"/>
775 <value value="72" name="AXI_WRITE_DATA_BEATS_ID_8"/>
776 <value value="73" name="AXI_WRITE_DATA_BEATS_ID_9"/>
777 <value value="74" name="AXI_WRITE_DATA_BEATS_ID_10"/>
778 <value value="75" name="AXI_WRITE_DATA_BEATS_ID_11"/>
779 <value value="76" name="AXI_WRITE_DATA_BEATS_ID_12"/>
780 <value value="77" name="AXI_WRITE_DATA_BEATS_ID_13"/>
781 <value value="78" name="AXI_WRITE_DATA_BEATS_ID_14"/>
782 <value value="79" name="AXI_WRITE_DATA_BEATS_ID_15"/>
783 <value value="80" name="AXI0_WRITE_DATA_BEATS_TOTAL"/>
784 <value value="81" name="AXI1_WRITE_DATA_BEATS_TOTAL"/>
785 <value value="82" name="AXI2_WRITE_DATA_BEATS_TOTAL"/>
786 <value value="83" name="AXI3_WRITE_DATA_BEATS_TOTAL"/>
787 <value value="84" name="AXI_WRITE_DATA_BEATS_TOTAL"/>
788 <value value="85" name="AXI_DATA_BEATS_TOTAL"/>
789 <value value="86" name="CYCLES_HELD_OFF_ID_0"/>
790 <value value="87" name="CYCLES_HELD_OFF_ID_1"/>
791 <value value="88" name="CYCLES_HELD_OFF_ID_2"/>
792 <value value="89" name="CYCLES_HELD_OFF_ID_3"/>
793 <value value="90" name="CYCLES_HELD_OFF_ID_4"/>
794 <value value="91" name="CYCLES_HELD_OFF_ID_5"/>
795 <value value="92" name="CYCLES_HELD_OFF_ID_6"/>
796 <value value="93" name="CYCLES_HELD_OFF_ID_7"/>
797 <value value="94" name="CYCLES_HELD_OFF_ID_8"/>
798 <value value="95" name="CYCLES_HELD_OFF_ID_9"/>
799 <value value="96" name="CYCLES_HELD_OFF_ID_10"/>
800 <value value="97" name="CYCLES_HELD_OFF_ID_11"/>
801 <value value="98" name="CYCLES_HELD_OFF_ID_12"/>
802 <value value="99" name="CYCLES_HELD_OFF_ID_13"/>
803 <value value="100" name="CYCLES_HELD_OFF_ID_14"/>
804 <value value="101" name="CYCLES_HELD_OFF_ID_15"/>
805 <value value="102" name="AXI_READ_REQUEST_HELD_OFF"/>
806 <value value="103" name="AXI_WRITE_REQUEST_HELD_OFF"/>
807 <value value="104" name="AXI_REQUEST_HELD_OFF"/>
808 <value value="105" name="AXI_WRITE_DATA_HELD_OFF"/>
809 <value value="106" name="OCMEM_AXI_READ_REQUEST_HELD_OFF"/>
810 <value value="107" name="OCMEM_AXI_WRITE_REQUEST_HELD_OFF"/>
811 <value value="108" name="OCMEM_AXI_REQUEST_HELD_OFF"/>
812 <value value="109" name="OCMEM_AXI_WRITE_DATA_HELD_OFF"/>
813 <value value="110" name="ELAPSED_CYCLES_DDR"/>
814 <value value="111" name="ELAPSED_CYCLES_OCMEM"/>
815 </enum>
816
817 <enum name="a4xx_vfd_perfcounter_select">
818 <value value="0" name="VFD_UCHE_BYTE_FETCHED"/>
819 <value value="1" name="VFD_UCHE_TRANS"/>
820 <value value="3" name="VFD_FETCH_INSTRUCTIONS"/>
821 <value value="5" name="VFD_BUSY_CYCLES"/>
822 <value value="6" name="VFD_STALL_CYCLES_UCHE"/>
823 <value value="7" name="VFD_STALL_CYCLES_HLSQ"/>
824 <value value="8" name="VFD_STALL_CYCLES_VPC_BYPASS"/>
825 <value value="9" name="VFD_STALL_CYCLES_VPC_ALLOC"/>
826 <value value="13" name="VFD_MODE_0_FIBERS"/>
827 <value value="14" name="VFD_MODE_1_FIBERS"/>
828 <value value="15" name="VFD_MODE_2_FIBERS"/>
829 <value value="16" name="VFD_MODE_3_FIBERS"/>
830 <value value="17" name="VFD_MODE_4_FIBERS"/>
831 <value value="18" name="VFD_BFIFO_STALL"/>
832 <value value="19" name="VFD_NUM_VERTICES_TOTAL"/>
833 <value value="20" name="VFD_PACKER_FULL"/>
834 <value value="21" name="VFD_UCHE_REQUEST_FIFO_FULL"/>
835 <value value="22" name="VFD_STARVE_CYCLES_PC"/>
836 <value value="23" name="VFD_STARVE_CYCLES_UCHE"/>
837 </enum>
838
839 <enum name="a4xx_vpc_perfcounter_select">
840 <value value="2" name="VPC_SP_LM_COMPONENTS"/>
841 <value value="3" name="VPC_SP0_LM_BYTES"/>
842 <value value="4" name="VPC_SP1_LM_BYTES"/>
843 <value value="5" name="VPC_SP2_LM_BYTES"/>
844 <value value="6" name="VPC_SP3_LM_BYTES"/>
845 <value value="7" name="VPC_WORKING_CYCLES"/>
846 <value value="8" name="VPC_STALL_CYCLES_LM"/>
847 <value value="9" name="VPC_STARVE_CYCLES_RAS"/>
848 <value value="10" name="VPC_STREAMOUT_CYCLES"/>
849 <value value="12" name="VPC_UCHE_TRANSACTIONS"/>
850 <value value="13" name="VPC_STALL_CYCLES_UCHE"/>
851 <value value="14" name="VPC_BUSY_CYCLES"/>
852 <value value="15" name="VPC_STARVE_CYCLES_SP"/>
853 </enum>
854
855 <enum name="a4xx_vsc_perfcounter_select">
856 <value value="0" name="VSC_BUSY_CYCLES"/>
857 <value value="1" name="VSC_WORKING_CYCLES"/>
858 <value value="2" name="VSC_STALL_CYCLES_UCHE"/>
859 <value value="3" name="VSC_STARVE_CYCLES_RAS"/>
860 <value value="4" name="VSC_EOT_NUM"/>
861 </enum>
862
863 <domain name="A4XX" width="32">
864 <!-- RB registers -->
865 <reg32 offset="0x0cc0" name="RB_GMEM_BASE_ADDR"/>
866 <reg32 offset="0x0cc7" name="RB_PERFCTR_RB_SEL_0" type="a4xx_rb_perfcounter_select"/>
867 <reg32 offset="0x0cc8" name="RB_PERFCTR_RB_SEL_1" type="a4xx_rb_perfcounter_select"/>
868 <reg32 offset="0x0cc9" name="RB_PERFCTR_RB_SEL_2" type="a4xx_rb_perfcounter_select"/>
869 <reg32 offset="0x0cca" name="RB_PERFCTR_RB_SEL_3" type="a4xx_rb_perfcounter_select"/>
870 <reg32 offset="0x0ccb" name="RB_PERFCTR_RB_SEL_4" type="a4xx_rb_perfcounter_select"/>
871 <reg32 offset="0x0ccc" name="RB_PERFCTR_RB_SEL_5" type="a4xx_rb_perfcounter_select"/>
872 <reg32 offset="0x0ccd" name="RB_PERFCTR_RB_SEL_6" type="a4xx_rb_perfcounter_select"/>
873 <reg32 offset="0x0cce" name="RB_PERFCTR_RB_SEL_7" type="a4xx_rb_perfcounter_select"/>
874 <reg32 offset="0x0ccf" name="RB_PERFCTR_CCU_SEL_0" type="a4xx_ccu_perfcounter_select"/>
875 <reg32 offset="0x0cd0" name="RB_PERFCTR_CCU_SEL_1" type="a4xx_ccu_perfcounter_select"/>
876 <reg32 offset="0x0cd1" name="RB_PERFCTR_CCU_SEL_2" type="a4xx_ccu_perfcounter_select"/>
877 <reg32 offset="0x0cd2" name="RB_PERFCTR_CCU_SEL_3" type="a4xx_ccu_perfcounter_select"/>
878 <reg32 offset="0x0ce0" name="RB_FRAME_BUFFER_DIMENSION">
879 <bitfield name="WIDTH" low="0" high="13" type="uint"/>
880 <bitfield name="HEIGHT" low="16" high="29" type="uint"/>
881 </reg32>
882 <reg32 offset="0x20cc" name="RB_CLEAR_COLOR_DW0"/>
883 <reg32 offset="0x20cd" name="RB_CLEAR_COLOR_DW1"/>
884 <reg32 offset="0x20ce" name="RB_CLEAR_COLOR_DW2"/>
885 <reg32 offset="0x20cf" name="RB_CLEAR_COLOR_DW3"/>
886 <reg32 offset="0x20a0" name="RB_MODE_CONTROL">
887 <!--
888 for non-bypass mode, these are bin width/height.. although
889 possibly bigger bitfields to hold entire width/height for
890 gmem-bypass?? Either way, it appears to need to be multiple
891 of 32..
892 -->
893 <bitfield name="WIDTH" low="0" high="5" shr="5" type="uint"/>
894 <bitfield name="HEIGHT" low="8" high="13" shr="5" type="uint"/>
895 <bitfield name="ENABLE_GMEM" pos="16" type="boolean"/>
896 </reg32>
897 <reg32 offset="0x20a1" name="RB_RENDER_CONTROL">
898 <bitfield name="BINNING_PASS" pos="0" type="boolean"/>
899 <!-- nearly everything has bit3 set.. -->
900 <!-- bit5 set on resolve and tiling pass -->
901 <bitfield name="DISABLE_COLOR_PIPE" pos="5" type="boolean"/>
902 </reg32>
903 <reg32 offset="0x20a2" name="RB_MSAA_CONTROL">
904 <bitfield name="DISABLE" pos="12" type="boolean"/>
905 <bitfield name="SAMPLES" low="13" high="15" type="uint"/>
906 </reg32>
907 <reg32 offset="0x20a3" name="RB_RENDER_CONTROL2">
908 <bitfield name="COORD_MASK" low="0" high="3" type="hex"/>
909 <bitfield name="SAMPLEMASK" pos="4" type="boolean"/>
910 <bitfield name="FACENESS" pos="5" type="boolean"/>
911 <bitfield name="SAMPLEID" pos="6" type="boolean"/>
912 <bitfield name="MSAA_SAMPLES" low="7" high="9" type="uint"/>
913 <bitfield name="SAMPLEID_HR" pos="11" type="boolean"/>
914 <bitfield name="IJ_PERSP_PIXEL" pos="12" type="boolean"/>
915 <!-- the 2 below are just educated guesses -->
916 <bitfield name="IJ_PERSP_CENTROID" pos="13" type="boolean"/>
917 <bitfield name="IJ_PERSP_SAMPLE" pos="14" type="boolean"/>
918 <!-- needs to be enabled to get nopersp values,
919 perhaps other cases too? -->
920 <bitfield name="SIZE" pos="15" type="boolean"/>
921 </reg32>
922 <array offset="0x20a4" name="RB_MRT" stride="5" length="8">
923 <reg32 offset="0x0" name="CONTROL">
924 <bitfield name="READ_DEST_ENABLE" pos="3" type="boolean"/>
925 <!-- both these bits seem to get set when enabling GL_BLEND.. -->
926 <bitfield name="BLEND" pos="4" type="boolean"/>
927 <bitfield name="BLEND2" pos="5" type="boolean"/>
928 <bitfield name="ROP_ENABLE" pos="6" type="boolean"/>
929 <bitfield name="ROP_CODE" low="8" high="11" type="a3xx_rop_code"/>
930 <bitfield name="COMPONENT_ENABLE" low="24" high="27" type="hex"/>
931 </reg32>
932 <reg32 offset="0x1" name="BUF_INFO">
933 <bitfield name="COLOR_FORMAT" low="0" high="5" type="a4xx_color_fmt"/>
934 <!--
935 guestimate position of COLOR_TILE_MODE.. this works out if
936 common value is 2, like on a3xx..
937 -->
938 <bitfield name="COLOR_TILE_MODE" low="6" high="7" type="a4xx_tile_mode"/>
939 <bitfield name="DITHER_MODE" low="9" high="10" type="adreno_rb_dither_mode"/>
940 <bitfield name="COLOR_SWAP" low="11" high="12" type="a3xx_color_swap"/>
941 <bitfield name="COLOR_SRGB" pos="13" type="boolean"/>
942 <!-- note: possibly some # of lsb's aren't there: -->
943 <doc>
944 Pitch (actually, appears to be pitch in bytes, so really is a stride)
945 in GMEM, so pitch of the current tile.
946 </doc>
947 <bitfield name="COLOR_BUF_PITCH" low="14" high="31" shr="4" type="uint"/>
948 </reg32>
949 <reg32 offset="0x2" name="BASE"/>
950 <reg32 offset="0x3" name="CONTROL3">
951 <!-- probably missing some lsb's.. and guessing upper size -->
952 <!-- pitch * cpp * msaa: -->
953 <bitfield name="STRIDE" low="3" high="25" type="uint"/>
954 </reg32>
955 <reg32 offset="0x4" name="BLEND_CONTROL">
956 <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
957 <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>
958 <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>
959 <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>
960 <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>
961 <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>
962 </reg32>
963 </array>
964
965 <reg32 offset="0x20f0" name="RB_BLEND_RED">
966 <bitfield name="UINT" low="0" high="7" type="hex"/>
967 <bitfield name="SINT" low="8" high="15" type="hex"/>
968 <bitfield name="FLOAT" low="16" high="31" type="float"/>
969 </reg32>
970 <reg32 offset="0x20f1" name="RB_BLEND_RED_F32" type="float"/>
971
972 <reg32 offset="0x20f2" name="RB_BLEND_GREEN">
973 <bitfield name="UINT" low="0" high="7" type="hex"/>
974 <bitfield name="SINT" low="8" high="15" type="hex"/>
975 <bitfield name="FLOAT" low="16" high="31" type="float"/>
976 </reg32>
977 <reg32 offset="0x20f3" name="RB_BLEND_GREEN_F32" type="float"/>
978
979 <reg32 offset="0x20f4" name="RB_BLEND_BLUE">
980 <bitfield name="UINT" low="0" high="7" type="hex"/>
981 <bitfield name="SINT" low="8" high="15" type="hex"/>
982 <bitfield name="FLOAT" low="16" high="31" type="float"/>
983 </reg32>
984 <reg32 offset="0x20f5" name="RB_BLEND_BLUE_F32" type="float"/>
985
986 <reg32 offset="0x20f6" name="RB_BLEND_ALPHA">
987 <bitfield name="UINT" low="0" high="7" type="hex"/>
988 <bitfield name="SINT" low="8" high="15" type="hex"/>
989 <bitfield name="FLOAT" low="16" high="31" type="float"/>
990 </reg32>
991 <reg32 offset="0x20f7" name="RB_BLEND_ALPHA_F32" type="float"/>
992
993 <reg32 offset="0x20f8" name="RB_ALPHA_CONTROL">
994 <bitfield name="ALPHA_REF" low="0" high="7" type="hex"/>
995 <bitfield name="ALPHA_TEST" pos="8" type="boolean"/>
996 <bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/>
997 </reg32>
998 <reg32 offset="0x20f9" name="RB_FS_OUTPUT">
999 <!-- per-mrt enable bit -->
1000 <bitfield name="ENABLE_BLEND" low="0" high="7"/>
1001 <bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/>
1002 <!-- a guess? -->
1003 <bitfield name="SAMPLE_MASK" low="16" high="31"/>
1004 </reg32>
1005 <reg32 offset="0x20fa" name="RB_SAMPLE_COUNT_CONTROL">
1006 <bitfield name="COPY" pos="1" type="boolean"/>
1007 <bitfield name="ADDR" low="2" high="31" shr="2"/>
1008 </reg32>
1009 <!-- always 00000000 for binning pass, else 0000000f: -->
1010 <reg32 offset="0x20fb" name="RB_RENDER_COMPONENTS">
1011 <bitfield name="RT0" low="0" high="3"/>
1012 <bitfield name="RT1" low="4" high="7"/>
1013 <bitfield name="RT2" low="8" high="11"/>
1014 <bitfield name="RT3" low="12" high="15"/>
1015 <bitfield name="RT4" low="16" high="19"/>
1016 <bitfield name="RT5" low="20" high="23"/>
1017 <bitfield name="RT6" low="24" high="27"/>
1018 <bitfield name="RT7" low="28" high="31"/>
1019 </reg32>
1020
1021 <reg32 offset="0x20fc" name="RB_COPY_CONTROL">
1022 <!-- not sure # of bits -->
1023 <bitfield name="MSAA_RESOLVE" low="0" high="1" type="a3xx_msaa_samples"/>
1024 <bitfield name="MODE" low="4" high="6" type="adreno_rb_copy_control_mode"/>
1025 <bitfield name="FASTCLEAR" low="8" high="11" type="hex"/>
1026 <bitfield name="GMEM_BASE" low="14" high="31" shr="14" type="hex"/>
1027 </reg32>
1028 <reg32 offset="0x20fd" name="RB_COPY_DEST_BASE">
1029 <bitfield name="BASE" low="5" high="31" shr="5" type="hex"/>
1030 </reg32>
1031 <reg32 offset="0x20fe" name="RB_COPY_DEST_PITCH">
1032 <doc>actually, appears to be pitch in bytes, so really is a stride</doc>
1033 <!-- not actually sure about max pitch... -->
1034 <bitfield name="PITCH" low="0" high="31" shr="5" type="uint"/>
1035 </reg32>
1036 <reg32 offset="0x20ff" name="RB_COPY_DEST_INFO">
1037 <bitfield name="FORMAT" low="2" high="7" type="a4xx_color_fmt"/>
1038 <bitfield name="SWAP" low="8" high="9" type="a3xx_color_swap"/>
1039 <bitfield name="DITHER_MODE" low="10" high="11" type="adreno_rb_dither_mode"/>
1040 <bitfield name="COMPONENT_ENABLE" low="14" high="17" type="hex"/>
1041 <bitfield name="ENDIAN" low="18" high="20" type="adreno_rb_surface_endian"/>
1042 <bitfield name="TILE" low="24" high="25" type="a4xx_tile_mode"/>
1043 </reg32>
1044 <reg32 offset="0x2100" name="RB_FS_OUTPUT_REG">
1045 <!-- bit0 set except for binning pass.. -->
1046 <bitfield name="MRT" low="0" high="3" type="uint"/>
1047 <bitfield name="FRAG_WRITES_Z" pos="5" type="boolean"/>
1048 </reg32>
1049 <reg32 offset="0x2101" name="RB_DEPTH_CONTROL">
1050 <!--
1051 guessing that this matches a2xx with the stencil fields
1052 moved out into RB_STENCIL_CONTROL?
1053 -->
1054 <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
1055 <bitfield name="Z_ENABLE" pos="1" type="boolean"/>
1056 <bitfield name="Z_WRITE_ENABLE" pos="2" type="boolean"/>
1057 <bitfield name="ZFUNC" low="4" high="6" type="adreno_compare_func"/>
1058 <bitfield name="Z_CLAMP_ENABLE" pos="7" type="boolean"/>
1059 <bitfield name="EARLY_Z_DISABLE" pos="16" type="boolean"/>
1060 <bitfield name="FORCE_FRAGZ_TO_FS" pos="17" type="boolean"/>
1061 <doc>Z_TEST_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc>
1062 <bitfield name="Z_TEST_ENABLE" pos="31" type="boolean"/>
1063 </reg32>
1064 <reg32 offset="0x2102" name="RB_DEPTH_CLEAR"/>
1065 <reg32 offset="0x2103" name="RB_DEPTH_INFO">
1066 <bitfield name="DEPTH_FORMAT" low="0" high="1" type="a4xx_depth_format"/>
1067 <doc>
1068 DEPTH_BASE is offset in GMEM to depth/stencil buffer, ie
1069 bin_w * bin_h / 1024 (possible rounded up to multiple of
1070 something?? ie. 39 becomes 40, 78 becomes 80.. 75 becomes
1071 80.. so maybe it needs to be multiple of 8??
1072 </doc>
1073 <bitfield name="DEPTH_BASE" low="12" high="31" shr="12" type="hex"/>
1074 </reg32>
1075 <reg32 offset="0x2104" name="RB_DEPTH_PITCH" shr="5" type="uint">
1076 <doc>stride of depth/stencil buffer</doc>
1077 </reg32>
1078 <reg32 offset="0x2105" name="RB_DEPTH_PITCH2" shr="5" type="uint">
1079 <doc>???</doc>
1080 </reg32>
1081 <reg32 offset="0x2106" name="RB_STENCIL_CONTROL">
1082 <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
1083 <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>
1084 <!--
1085 set for stencil operations that require read from stencil
1086 buffer, but not for example for stencil clear (which does
1087 not require read).. so guessing this is analogous to
1088 READ_DEST_ENABLE for color buffer..
1089 -->
1090 <bitfield name="STENCIL_READ" pos="2" type="boolean"/>
1091 <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>
1092 <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>
1093 <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>
1094 <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>
1095 <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>
1096 <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
1097 <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
1098 <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
1099 </reg32>
1100 <reg32 offset="0x2107" name="RB_STENCIL_CONTROL2">
1101 <!--
1102 This seems to be set by blob if there is a stencil buffer
1103 at all in GMEM, regardless of whether it is enabled for
1104 a particular draw (ie. RB_STENCIL_CONTROL). Not really
1105 sure if that is required or just a quirk of the blob
1106 -->
1107 <bitfield name="STENCIL_BUFFER" pos="0" type="boolean"/>
1108 </reg32>
1109 <reg32 offset="0x2108" name="RB_STENCIL_INFO">
1110 <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
1111 <doc>Base address for stencil when not using interleaved depth/stencil</doc>
1112 <bitfield name="STENCIL_BASE" low="12" high="31" shr="12" type="hex"/>
1113 </reg32>
1114 <reg32 offset="0x2109" name="RB_STENCIL_PITCH" shr="5" type="uint">
1115 <doc>pitch of stencil buffer when not using interleaved depth/stencil</doc>
1116 </reg32>
1117
1118 <reg32 offset="0x210b" name="RB_STENCILREFMASK" type="adreno_rb_stencilrefmask"/>
1119 <reg32 offset="0x210c" name="RB_STENCILREFMASK_BF" type="adreno_rb_stencilrefmask"/>
1120 <reg32 offset="0x210d" name="RB_BIN_OFFSET" type="adreno_reg_xy"/>
1121 <array offset="0x2120" name="RB_VPORT_Z_CLAMP" stride="2" length="16">
1122 <reg32 offset="0x0" name="MIN"/>
1123 <reg32 offset="0x1" name="MAX"/>
1124 </array>
1125
1126 <!-- RBBM registers -->
1127 <reg32 offset="0x0000" name="RBBM_HW_VERSION"/>
1128 <reg32 offset="0x0002" name="RBBM_HW_CONFIGURATION"/>
1129 <array offset="0x4" name="RBBM_CLOCK_CTL_TP" stride="1" length="4">
1130 <reg32 offset="0x0" name="REG"/>
1131 </array>
1132 <array offset="0x8" name="RBBM_CLOCK_CTL2_TP" stride="1" length="4">
1133 <reg32 offset="0x0" name="REG"/>
1134 </array>
1135 <array offset="0xc" name="RBBM_CLOCK_HYST_TP" stride="1" length="4">
1136 <reg32 offset="0x0" name="REG"/>
1137 </array>
1138 <array offset="0x10" name="RBBM_CLOCK_DELAY_TP" stride="1" length="4">
1139 <reg32 offset="0x0" name="REG"/>
1140 </array>
1141 <reg32 offset="0x0014" name="RBBM_CLOCK_CTL_UCHE "/>
1142 <reg32 offset="0x0015" name="RBBM_CLOCK_CTL2_UCHE"/>
1143 <reg32 offset="0x0016" name="RBBM_CLOCK_CTL3_UCHE"/>
1144 <reg32 offset="0x0017" name="RBBM_CLOCK_CTL4_UCHE"/>
1145 <reg32 offset="0x0018" name="RBBM_CLOCK_HYST_UCHE"/>
1146 <reg32 offset="0x0019" name="RBBM_CLOCK_DELAY_UCHE"/>
1147 <reg32 offset="0x001a" name="RBBM_CLOCK_MODE_GPC"/>
1148 <reg32 offset="0x001b" name="RBBM_CLOCK_DELAY_GPC"/>
1149 <reg32 offset="0x001c" name="RBBM_CLOCK_HYST_GPC"/>
1150 <reg32 offset="0x001d" name="RBBM_CLOCK_CTL_TSE_RAS_RBBM"/>
1151 <reg32 offset="0x001e" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
1152 <reg32 offset="0x001f" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
1153 <reg32 offset="0x0020" name="RBBM_CLOCK_CTL"/>
1154 <reg32 offset="0x0021" name="RBBM_SP_HYST_CNT"/>
1155 <reg32 offset="0x0022" name="RBBM_SW_RESET_CMD"/>
1156 <reg32 offset="0x0023" name="RBBM_AHB_CTL0"/>
1157 <reg32 offset="0x0024" name="RBBM_AHB_CTL1"/>
1158 <reg32 offset="0x0025" name="RBBM_AHB_CMD"/>
1159 <reg32 offset="0x0026" name="RBBM_RB_SUB_BLOCK_SEL_CTL"/>
1160 <reg32 offset="0x0028" name="RBBM_RAM_ACC_63_32"/>
1161 <reg32 offset="0x002b" name="RBBM_WAIT_IDLE_CLOCKS_CTL"/>
1162 <reg32 offset="0x002f" name="RBBM_INTERFACE_HANG_INT_CTL"/>
1163 <reg32 offset="0x0034" name="RBBM_INTERFACE_HANG_MASK_CTL4"/>
1164 <reg32 offset="0x0036" name="RBBM_INT_CLEAR_CMD"/>
1165 <reg32 offset="0x0037" name="RBBM_INT_0_MASK"/>
1166 <reg32 offset="0x003e" name="RBBM_RBBM_CTL"/>
1167 <reg32 offset="0x003f" name="RBBM_AHB_DEBUG_CTL"/>
1168 <reg32 offset="0x0041" name="RBBM_VBIF_DEBUG_CTL"/>
1169 <reg32 offset="0x0042" name="RBBM_CLOCK_CTL2"/>
1170 <reg32 offset="0x0045" name="RBBM_BLOCK_SW_RESET_CMD"/>
1171 <reg32 offset="0x0047" name="RBBM_RESET_CYCLES"/>
1172 <reg32 offset="0x0049" name="RBBM_EXT_TRACE_BUS_CTL"/>
1173 <reg32 offset="0x004a" name="RBBM_CFG_DEBBUS_SEL_A"/>
1174 <reg32 offset="0x004b" name="RBBM_CFG_DEBBUS_SEL_B"/>
1175 <reg32 offset="0x004c" name="RBBM_CFG_DEBBUS_SEL_C"/>
1176 <reg32 offset="0x004d" name="RBBM_CFG_DEBBUS_SEL_D"/>
1177 <reg32 offset="0x0098" name="RBBM_POWER_CNTL_IP">
1178 <bitfield name="SW_COLLAPSE" pos="0" type="boolean"/>
1179 <bitfield name="SP_TP_PWR_ON" pos="20" type="boolean"/>
1180 </reg32>
1181 <reg32 offset="0x009c" name="RBBM_PERFCTR_CP_0_LO"/>
1182 <reg32 offset="0x009d" name="RBBM_PERFCTR_CP_0_HI"/>
1183 <reg32 offset="0x009e" name="RBBM_PERFCTR_CP_1_LO"/>
1184 <reg32 offset="0x009f" name="RBBM_PERFCTR_CP_1_HI"/>
1185 <reg32 offset="0x00a0" name="RBBM_PERFCTR_CP_2_LO"/>
1186 <reg32 offset="0x00a1" name="RBBM_PERFCTR_CP_2_HI"/>
1187 <reg32 offset="0x00a2" name="RBBM_PERFCTR_CP_3_LO"/>
1188 <reg32 offset="0x00a3" name="RBBM_PERFCTR_CP_3_HI"/>
1189 <reg32 offset="0x00a4" name="RBBM_PERFCTR_CP_4_LO"/>
1190 <reg32 offset="0x00a5" name="RBBM_PERFCTR_CP_4_HI"/>
1191 <reg32 offset="0x00a6" name="RBBM_PERFCTR_CP_5_LO"/>
1192 <reg32 offset="0x00a7" name="RBBM_PERFCTR_CP_5_HI"/>
1193 <reg32 offset="0x00a8" name="RBBM_PERFCTR_CP_6_LO"/>
1194 <reg32 offset="0x00a9" name="RBBM_PERFCTR_CP_6_HI"/>
1195 <reg32 offset="0x00aa" name="RBBM_PERFCTR_CP_7_LO"/>
1196 <reg32 offset="0x00ab" name="RBBM_PERFCTR_CP_7_HI"/>
1197 <reg32 offset="0x00ac" name="RBBM_PERFCTR_RBBM_0_LO"/>
1198 <reg32 offset="0x00ad" name="RBBM_PERFCTR_RBBM_0_HI"/>
1199 <reg32 offset="0x00ae" name="RBBM_PERFCTR_RBBM_1_LO"/>
1200 <reg32 offset="0x00af" name="RBBM_PERFCTR_RBBM_1_HI"/>
1201 <reg32 offset="0x00b0" name="RBBM_PERFCTR_RBBM_2_LO"/>
1202 <reg32 offset="0x00b1" name="RBBM_PERFCTR_RBBM_2_HI"/>
1203 <reg32 offset="0x00b2" name="RBBM_PERFCTR_RBBM_3_LO"/>
1204 <reg32 offset="0x00b3" name="RBBM_PERFCTR_RBBM_3_HI"/>
1205 <reg32 offset="0x00b4" name="RBBM_PERFCTR_PC_0_LO"/>
1206 <reg32 offset="0x00b5" name="RBBM_PERFCTR_PC_0_HI"/>
1207 <reg32 offset="0x00b6" name="RBBM_PERFCTR_PC_1_LO"/>
1208 <reg32 offset="0x00b7" name="RBBM_PERFCTR_PC_1_HI"/>
1209 <reg32 offset="0x00b8" name="RBBM_PERFCTR_PC_2_LO"/>
1210 <reg32 offset="0x00b9" name="RBBM_PERFCTR_PC_2_HI"/>
1211 <reg32 offset="0x00ba" name="RBBM_PERFCTR_PC_3_LO"/>
1212 <reg32 offset="0x00bb" name="RBBM_PERFCTR_PC_3_HI"/>
1213 <reg32 offset="0x00bc" name="RBBM_PERFCTR_PC_4_LO"/>
1214 <reg32 offset="0x00bd" name="RBBM_PERFCTR_PC_4_HI"/>
1215 <reg32 offset="0x00be" name="RBBM_PERFCTR_PC_5_LO"/>
1216 <reg32 offset="0x00bf" name="RBBM_PERFCTR_PC_5_HI"/>
1217 <reg32 offset="0x00c0" name="RBBM_PERFCTR_PC_6_LO"/>
1218 <reg32 offset="0x00c1" name="RBBM_PERFCTR_PC_6_HI"/>
1219 <reg32 offset="0x00c2" name="RBBM_PERFCTR_PC_7_LO"/>
1220 <reg32 offset="0x00c3" name="RBBM_PERFCTR_PC_7_HI"/>
1221 <reg32 offset="0x00c4" name="RBBM_PERFCTR_VFD_0_LO"/>
1222 <reg32 offset="0x00c5" name="RBBM_PERFCTR_VFD_0_HI"/>
1223 <reg32 offset="0x00c6" name="RBBM_PERFCTR_VFD_1_LO"/>
1224 <reg32 offset="0x00c7" name="RBBM_PERFCTR_VFD_1_HI"/>
1225 <reg32 offset="0x00c8" name="RBBM_PERFCTR_VFD_2_LO"/>
1226 <reg32 offset="0x00c9" name="RBBM_PERFCTR_VFD_2_HI"/>
1227 <reg32 offset="0x00ca" name="RBBM_PERFCTR_VFD_3_LO"/>
1228 <reg32 offset="0x00cb" name="RBBM_PERFCTR_VFD_3_HI"/>
1229 <reg32 offset="0x00cc" name="RBBM_PERFCTR_VFD_4_LO"/>
1230 <reg32 offset="0x00cd" name="RBBM_PERFCTR_VFD_4_HI"/>
1231 <reg32 offset="0x00ce" name="RBBM_PERFCTR_VFD_5_LO"/>
1232 <reg32 offset="0x00cf" name="RBBM_PERFCTR_VFD_5_HI"/>
1233 <reg32 offset="0x00d0" name="RBBM_PERFCTR_VFD_6_LO"/>
1234 <reg32 offset="0x00d1" name="RBBM_PERFCTR_VFD_6_HI"/>
1235 <reg32 offset="0x00d2" name="RBBM_PERFCTR_VFD_7_LO"/>
1236 <reg32 offset="0x00d3" name="RBBM_PERFCTR_VFD_7_HI"/>
1237 <reg32 offset="0x00d4" name="RBBM_PERFCTR_HLSQ_0_LO"/>
1238 <reg32 offset="0x00d5" name="RBBM_PERFCTR_HLSQ_0_HI"/>
1239 <reg32 offset="0x00d6" name="RBBM_PERFCTR_HLSQ_1_LO"/>
1240 <reg32 offset="0x00d7" name="RBBM_PERFCTR_HLSQ_1_HI"/>
1241 <reg32 offset="0x00d8" name="RBBM_PERFCTR_HLSQ_2_LO"/>
1242 <reg32 offset="0x00d9" name="RBBM_PERFCTR_HLSQ_2_HI"/>
1243 <reg32 offset="0x00da" name="RBBM_PERFCTR_HLSQ_3_LO"/>
1244 <reg32 offset="0x00db" name="RBBM_PERFCTR_HLSQ_3_HI"/>
1245 <reg32 offset="0x00dc" name="RBBM_PERFCTR_HLSQ_4_LO"/>
1246 <reg32 offset="0x00dd" name="RBBM_PERFCTR_HLSQ_4_HI"/>
1247 <reg32 offset="0x00de" name="RBBM_PERFCTR_HLSQ_5_LO"/>
1248 <reg32 offset="0x00df" name="RBBM_PERFCTR_HLSQ_5_HI"/>
1249 <reg32 offset="0x00e0" name="RBBM_PERFCTR_HLSQ_6_LO"/>
1250 <reg32 offset="0x00e1" name="RBBM_PERFCTR_HLSQ_6_HI"/>
1251 <reg32 offset="0x00e2" name="RBBM_PERFCTR_HLSQ_7_LO"/>
1252 <reg32 offset="0x00e3" name="RBBM_PERFCTR_HLSQ_7_HI"/>
1253 <reg32 offset="0x00e4" name="RBBM_PERFCTR_VPC_0_LO"/>
1254 <reg32 offset="0x00e5" name="RBBM_PERFCTR_VPC_0_HI"/>
1255 <reg32 offset="0x00e6" name="RBBM_PERFCTR_VPC_1_LO"/>
1256 <reg32 offset="0x00e7" name="RBBM_PERFCTR_VPC_1_HI"/>
1257 <reg32 offset="0x00e8" name="RBBM_PERFCTR_VPC_2_LO"/>
1258 <reg32 offset="0x00e9" name="RBBM_PERFCTR_VPC_2_HI"/>
1259 <reg32 offset="0x00ea" name="RBBM_PERFCTR_VPC_3_LO"/>
1260 <reg32 offset="0x00eb" name="RBBM_PERFCTR_VPC_3_HI"/>
1261 <reg32 offset="0x00ec" name="RBBM_PERFCTR_CCU_0_LO"/>
1262 <reg32 offset="0x00ed" name="RBBM_PERFCTR_CCU_0_HI"/>
1263 <reg32 offset="0x00ee" name="RBBM_PERFCTR_CCU_1_LO"/>
1264 <reg32 offset="0x00ef" name="RBBM_PERFCTR_CCU_1_HI"/>
1265 <reg32 offset="0x00f0" name="RBBM_PERFCTR_CCU_2_LO"/>
1266 <reg32 offset="0x00f1" name="RBBM_PERFCTR_CCU_2_HI"/>
1267 <reg32 offset="0x00f2" name="RBBM_PERFCTR_CCU_3_LO"/>
1268 <reg32 offset="0x00f3" name="RBBM_PERFCTR_CCU_3_HI"/>
1269 <reg32 offset="0x00f4" name="RBBM_PERFCTR_TSE_0_LO"/>
1270 <reg32 offset="0x00f5" name="RBBM_PERFCTR_TSE_0_HI"/>
1271 <reg32 offset="0x00f6" name="RBBM_PERFCTR_TSE_1_LO"/>
1272 <reg32 offset="0x00f7" name="RBBM_PERFCTR_TSE_1_HI"/>
1273 <reg32 offset="0x00f8" name="RBBM_PERFCTR_TSE_2_LO"/>
1274 <reg32 offset="0x00f9" name="RBBM_PERFCTR_TSE_2_HI"/>
1275 <reg32 offset="0x00fa" name="RBBM_PERFCTR_TSE_3_LO"/>
1276 <reg32 offset="0x00fb" name="RBBM_PERFCTR_TSE_3_HI"/>
1277 <reg32 offset="0x00fc" name="RBBM_PERFCTR_RAS_0_LO"/>
1278 <reg32 offset="0x00fd" name="RBBM_PERFCTR_RAS_0_HI"/>
1279 <reg32 offset="0x00fe" name="RBBM_PERFCTR_RAS_1_LO"/>
1280 <reg32 offset="0x00ff" name="RBBM_PERFCTR_RAS_1_HI"/>
1281 <reg32 offset="0x0100" name="RBBM_PERFCTR_RAS_2_LO"/>
1282 <reg32 offset="0x0101" name="RBBM_PERFCTR_RAS_2_HI"/>
1283 <reg32 offset="0x0102" name="RBBM_PERFCTR_RAS_3_LO"/>
1284 <reg32 offset="0x0103" name="RBBM_PERFCTR_RAS_3_HI"/>
1285 <reg32 offset="0x0104" name="RBBM_PERFCTR_UCHE_0_LO"/>
1286 <reg32 offset="0x0105" name="RBBM_PERFCTR_UCHE_0_HI"/>
1287 <reg32 offset="0x0106" name="RBBM_PERFCTR_UCHE_1_LO"/>
1288 <reg32 offset="0x0107" name="RBBM_PERFCTR_UCHE_1_HI"/>
1289 <reg32 offset="0x0108" name="RBBM_PERFCTR_UCHE_2_LO"/>
1290 <reg32 offset="0x0109" name="RBBM_PERFCTR_UCHE_2_HI"/>
1291 <reg32 offset="0x010a" name="RBBM_PERFCTR_UCHE_3_LO"/>
1292 <reg32 offset="0x010b" name="RBBM_PERFCTR_UCHE_3_HI"/>
1293 <reg32 offset="0x010c" name="RBBM_PERFCTR_UCHE_4_LO"/>
1294 <reg32 offset="0x010d" name="RBBM_PERFCTR_UCHE_4_HI"/>
1295 <reg32 offset="0x010e" name="RBBM_PERFCTR_UCHE_5_LO"/>
1296 <reg32 offset="0x010f" name="RBBM_PERFCTR_UCHE_5_HI"/>
1297 <reg32 offset="0x0110" name="RBBM_PERFCTR_UCHE_6_LO"/>
1298 <reg32 offset="0x0111" name="RBBM_PERFCTR_UCHE_6_HI"/>
1299 <reg32 offset="0x0112" name="RBBM_PERFCTR_UCHE_7_LO"/>
1300 <reg32 offset="0x0113" name="RBBM_PERFCTR_UCHE_7_HI"/>
1301 <reg32 offset="0x0114" name="RBBM_PERFCTR_TP_0_LO"/>
1302 <reg32 offset="0x0115" name="RBBM_PERFCTR_TP_0_HI"/>
1303 <reg32 offset="0x0116" name="RBBM_PERFCTR_TP_1_LO"/>
1304 <reg32 offset="0x0117" name="RBBM_PERFCTR_TP_1_HI"/>
1305 <reg32 offset="0x0118" name="RBBM_PERFCTR_TP_2_LO"/>
1306 <reg32 offset="0x0119" name="RBBM_PERFCTR_TP_2_HI"/>
1307 <reg32 offset="0x011a" name="RBBM_PERFCTR_TP_3_LO"/>
1308 <reg32 offset="0x011b" name="RBBM_PERFCTR_TP_3_HI"/>
1309 <reg32 offset="0x011c" name="RBBM_PERFCTR_TP_4_LO"/>
1310 <reg32 offset="0x011d" name="RBBM_PERFCTR_TP_4_HI"/>
1311 <reg32 offset="0x011e" name="RBBM_PERFCTR_TP_5_LO"/>
1312 <reg32 offset="0x011f" name="RBBM_PERFCTR_TP_5_HI"/>
1313 <reg32 offset="0x0120" name="RBBM_PERFCTR_TP_6_LO"/>
1314 <reg32 offset="0x0121" name="RBBM_PERFCTR_TP_6_HI"/>
1315 <reg32 offset="0x0122" name="RBBM_PERFCTR_TP_7_LO"/>
1316 <reg32 offset="0x0123" name="RBBM_PERFCTR_TP_7_HI"/>
1317 <reg32 offset="0x0124" name="RBBM_PERFCTR_SP_0_LO"/>
1318 <reg32 offset="0x0125" name="RBBM_PERFCTR_SP_0_HI"/>
1319 <reg32 offset="0x0126" name="RBBM_PERFCTR_SP_1_LO"/>
1320 <reg32 offset="0x0127" name="RBBM_PERFCTR_SP_1_HI"/>
1321 <reg32 offset="0x0128" name="RBBM_PERFCTR_SP_2_LO"/>
1322 <reg32 offset="0x0129" name="RBBM_PERFCTR_SP_2_HI"/>
1323 <reg32 offset="0x012a" name="RBBM_PERFCTR_SP_3_LO"/>
1324 <reg32 offset="0x012b" name="RBBM_PERFCTR_SP_3_HI"/>
1325 <reg32 offset="0x012c" name="RBBM_PERFCTR_SP_4_LO"/>
1326 <reg32 offset="0x012d" name="RBBM_PERFCTR_SP_4_HI"/>
1327 <reg32 offset="0x012e" name="RBBM_PERFCTR_SP_5_LO"/>
1328 <reg32 offset="0x012f" name="RBBM_PERFCTR_SP_5_HI"/>
1329 <reg32 offset="0x0130" name="RBBM_PERFCTR_SP_6_LO"/>
1330 <reg32 offset="0x0131" name="RBBM_PERFCTR_SP_6_HI"/>
1331 <reg32 offset="0x0132" name="RBBM_PERFCTR_SP_7_LO"/>
1332 <reg32 offset="0x0133" name="RBBM_PERFCTR_SP_7_HI"/>
1333 <reg32 offset="0x0134" name="RBBM_PERFCTR_SP_8_LO"/>
1334 <reg32 offset="0x0135" name="RBBM_PERFCTR_SP_8_HI"/>
1335 <reg32 offset="0x0136" name="RBBM_PERFCTR_SP_9_LO"/>
1336 <reg32 offset="0x0137" name="RBBM_PERFCTR_SP_9_HI"/>
1337 <reg32 offset="0x0138" name="RBBM_PERFCTR_SP_10_LO"/>
1338 <reg32 offset="0x0139" name="RBBM_PERFCTR_SP_10_HI"/>
1339 <reg32 offset="0x013a" name="RBBM_PERFCTR_SP_11_LO"/>
1340 <reg32 offset="0x013b" name="RBBM_PERFCTR_SP_11_HI"/>
1341 <reg32 offset="0x013c" name="RBBM_PERFCTR_RB_0_LO"/>
1342 <reg32 offset="0x013d" name="RBBM_PERFCTR_RB_0_HI"/>
1343 <reg32 offset="0x013e" name="RBBM_PERFCTR_RB_1_LO"/>
1344 <reg32 offset="0x013f" name="RBBM_PERFCTR_RB_1_HI"/>
1345 <reg32 offset="0x0140" name="RBBM_PERFCTR_RB_2_LO"/>
1346 <reg32 offset="0x0141" name="RBBM_PERFCTR_RB_2_HI"/>
1347 <reg32 offset="0x0142" name="RBBM_PERFCTR_RB_3_LO"/>
1348 <reg32 offset="0x0143" name="RBBM_PERFCTR_RB_3_HI"/>
1349 <reg32 offset="0x0144" name="RBBM_PERFCTR_RB_4_LO"/>
1350 <reg32 offset="0x0145" name="RBBM_PERFCTR_RB_4_HI"/>
1351 <reg32 offset="0x0146" name="RBBM_PERFCTR_RB_5_LO"/>
1352 <reg32 offset="0x0147" name="RBBM_PERFCTR_RB_5_HI"/>
1353 <reg32 offset="0x0148" name="RBBM_PERFCTR_RB_6_LO"/>
1354 <reg32 offset="0x0149" name="RBBM_PERFCTR_RB_6_HI"/>
1355 <reg32 offset="0x014a" name="RBBM_PERFCTR_RB_7_LO"/>
1356 <reg32 offset="0x014b" name="RBBM_PERFCTR_RB_7_HI"/>
1357 <reg32 offset="0x014c" name="RBBM_PERFCTR_VSC_0_LO"/>
1358 <reg32 offset="0x014d" name="RBBM_PERFCTR_VSC_0_HI"/>
1359 <reg32 offset="0x014e" name="RBBM_PERFCTR_VSC_1_LO"/>
1360 <reg32 offset="0x014f" name="RBBM_PERFCTR_VSC_1_HI"/>
1361 <reg32 offset="0x0166" name="RBBM_PERFCTR_PWR_0_LO"/>
1362 <reg32 offset="0x0167" name="RBBM_PERFCTR_PWR_0_HI"/>
1363 <reg32 offset="0x0168" name="RBBM_PERFCTR_PWR_1_LO"/>
1364 <reg32 offset="0x0169" name="RBBM_PERFCTR_PWR_1_HI"/>
1365 <reg32 offset="0x016e" name="RBBM_ALWAYSON_COUNTER_LO"/>
1366 <reg32 offset="0x016f" name="RBBM_ALWAYSON_COUNTER_HI"/>
1367 <array offset="0x0068" name="RBBM_CLOCK_CTL_SP" stride="1" length="4">
1368 <reg32 offset="0x0" name="REG"/>
1369 </array>
1370 <array offset="0x006c" name="RBBM_CLOCK_CTL2_SP" stride="1" length="4">
1371 <reg32 offset="0x0" name="REG"/>
1372 </array>
1373 <array offset="0x0070" name="RBBM_CLOCK_HYST_SP" stride="1" length="4">
1374 <reg32 offset="0x0" name="REG"/>
1375 </array>
1376 <array offset="0x0074" name="RBBM_CLOCK_DELAY_SP" stride="1" length="4">
1377 <reg32 offset="0x0" name="REG"/>
1378 </array>
1379 <array offset="0x0078" name="RBBM_CLOCK_CTL_RB" stride="1" length="4">
1380 <reg32 offset="0x0" name="REG"/>
1381 </array>
1382 <array offset="0x007c" name="RBBM_CLOCK_CTL2_RB" stride="1" length="4">
1383 <reg32 offset="0x0" name="REG"/>
1384 </array>
1385 <array offset="0x0082" name="RBBM_CLOCK_CTL_MARB_CCU" stride="1" length="4">
1386 <reg32 offset="0x0" name="REG"/>
1387 </array>
1388 <array offset="0x0086" name="RBBM_CLOCK_HYST_RB_MARB_CCU" stride="1" length="4">
1389 <reg32 offset="0x0" name="REG"/>
1390 </array>
1391 <reg32 offset="0x0080" name="RBBM_CLOCK_HYST_COM_DCOM"/>
1392 <reg32 offset="0x0081" name="RBBM_CLOCK_CTL_COM_DCOM"/>
1393 <reg32 offset="0x008a" name="RBBM_CLOCK_CTL_HLSQ"/>
1394 <reg32 offset="0x008b" name="RBBM_CLOCK_HYST_HLSQ"/>
1395 <reg32 offset="0x008c" name="RBBM_CLOCK_DELAY_HLSQ"/>
1396 <bitset name="A4XX_CGC_HLSQ">
1397 <bitfield name="EARLY_CYC" low="20" high="22" type="uint"/>
1398 </bitset>
1399 <reg32 offset="0x008d" name="RBBM_CLOCK_DELAY_COM_DCOM"/>
1400 <array offset="0x008e" name="RBBM_CLOCK_DELAY_RB_MARB_CCU_L1" stride="1" length="4">
1401 <reg32 offset="0x0" name="REG"/>
1402 </array>
1403 <bitset name="A4XX_INT0">
1404 <bitfield name="RBBM_GPU_IDLE" pos="0"/>
1405 <bitfield name="RBBM_AHB_ERROR" pos="1"/>
1406 <bitfield name="RBBM_REG_TIMEOUT" pos="2"/>
1407 <bitfield name="RBBM_ME_MS_TIMEOUT" pos="3"/>
1408 <bitfield name="RBBM_PFP_MS_TIMEOUT" pos="4"/>
1409 <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="5"/>
1410 <bitfield name="VFD_ERROR" pos="6"/>
1411 <bitfield name="CP_SW_INT" pos="7"/>
1412 <bitfield name="CP_T0_PACKET_IN_IB" pos="8"/>
1413 <bitfield name="CP_OPCODE_ERROR" pos="9"/>
1414 <bitfield name="CP_RESERVED_BIT_ERROR" pos="10"/>
1415 <bitfield name="CP_HW_FAULT" pos="11"/>
1416 <bitfield name="CP_DMA" pos="12"/>
1417 <bitfield name="CP_IB2_INT" pos="13"/>
1418 <bitfield name="CP_IB1_INT" pos="14"/>
1419 <bitfield name="CP_RB_INT" pos="15"/>
1420 <bitfield name="CP_REG_PROTECT_FAULT" pos="16"/>
1421 <bitfield name="CP_RB_DONE_TS" pos="17"/>
1422 <bitfield name="CP_VS_DONE_TS" pos="18"/>
1423 <bitfield name="CP_PS_DONE_TS" pos="19"/>
1424 <bitfield name="CACHE_FLUSH_TS" pos="20"/>
1425 <bitfield name="CP_AHB_ERROR_HALT" pos="21"/>
1426 <bitfield name="MISC_HANG_DETECT" pos="24"/>
1427 <bitfield name="UCHE_OOB_ACCESS" pos="25"/>
1428 </bitset>
1429
1430 <reg32 offset="0x0099" name="RBBM_SP_REGFILE_SLEEP_CNTL_0"/>
1431 <reg32 offset="0x009a" name="RBBM_SP_REGFILE_SLEEP_CNTL_1"/>
1432 <reg32 offset="0x0170" name="RBBM_PERFCTR_CTL"/>
1433 <reg32 offset="0x0171" name="RBBM_PERFCTR_LOAD_CMD0"/>
1434 <reg32 offset="0x0172" name="RBBM_PERFCTR_LOAD_CMD1"/>
1435 <reg32 offset="0x0173" name="RBBM_PERFCTR_LOAD_CMD2"/>
1436 <reg32 offset="0x0174" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
1437 <reg32 offset="0x0175" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
1438 <reg32 offset="0x0176" name="RBBM_PERFCTR_RBBM_SEL_0" type="a4xx_rbbm_perfcounter_select"/>
1439 <reg32 offset="0x0177" name="RBBM_PERFCTR_RBBM_SEL_1" type="a4xx_rbbm_perfcounter_select"/>
1440 <reg32 offset="0x0178" name="RBBM_PERFCTR_RBBM_SEL_2" type="a4xx_rbbm_perfcounter_select"/>
1441 <reg32 offset="0x0179" name="RBBM_PERFCTR_RBBM_SEL_3" type="a4xx_rbbm_perfcounter_select"/>
1442 <reg32 offset="0x017a" name="RBBM_GPU_BUSY_MASKED"/>
1443 <reg32 offset="0x017d" name="RBBM_INT_0_STATUS"/>
1444 <reg32 offset="0x0182" name="RBBM_CLOCK_STATUS"/>
1445 <reg32 offset="0x0189" name="RBBM_AHB_STATUS"/>
1446 <reg32 offset="0x018c" name="RBBM_AHB_ME_SPLIT_STATUS"/>
1447 <reg32 offset="0x018d" name="RBBM_AHB_PFP_SPLIT_STATUS"/>
1448 <reg32 offset="0x018f" name="RBBM_AHB_ERROR_STATUS"/>
1449 <reg32 offset="0x0191" name="RBBM_STATUS">
1450 <bitfield name="HI_BUSY" pos="0" type="boolean"/>
1451 <bitfield name="CP_ME_BUSY" pos="1" type="boolean"/>
1452 <bitfield name="CP_PFP_BUSY" pos="2" type="boolean"/>
1453 <bitfield name="CP_NRT_BUSY" pos="14" type="boolean"/>
1454 <bitfield name="VBIF_BUSY" pos="15" type="boolean"/>
1455 <bitfield name="TSE_BUSY" pos="16" type="boolean"/>
1456 <bitfield name="RAS_BUSY" pos="17" type="boolean"/>
1457 <bitfield name="RB_BUSY" pos="18" type="boolean"/>
1458 <bitfield name="PC_DCALL_BUSY" pos="19" type="boolean"/>
1459 <bitfield name="PC_VSD_BUSY" pos="20" type="boolean"/>
1460 <bitfield name="VFD_BUSY" pos="21" type="boolean"/>
1461 <bitfield name="VPC_BUSY" pos="22" type="boolean"/>
1462 <bitfield name="UCHE_BUSY" pos="23" type="boolean"/>
1463 <bitfield name="SP_BUSY" pos="24" type="boolean"/>
1464 <bitfield name="TPL1_BUSY" pos="25" type="boolean"/>
1465 <bitfield name="MARB_BUSY" pos="26" type="boolean"/>
1466 <bitfield name="VSC_BUSY" pos="27" type="boolean"/>
1467 <bitfield name="ARB_BUSY" pos="28" type="boolean"/>
1468 <bitfield name="HLSQ_BUSY" pos="29" type="boolean"/>
1469 <bitfield name="GPU_BUSY_NOHC" pos="30" type="boolean"/>
1470 <bitfield name="GPU_BUSY" pos="31" type="boolean"/>
1471 </reg32>
1472 <reg32 offset="0x019f" name="RBBM_INTERFACE_RRDY_STATUS5"/>
1473 <reg32 offset="0x01b0" name="RBBM_POWER_STATUS">
1474 <bitfield name="SP_TP_PWR_ON" pos="20" type="boolean"/>
1475 </reg32>
1476 <reg32 offset="0x01b8" name="RBBM_WAIT_IDLE_CLOCKS_CTL2"/>
1477
1478 <!-- CP registers -->
1479 <reg32 offset="0x0228" name="CP_SCRATCH_UMASK"/>
1480 <reg32 offset="0x0229" name="CP_SCRATCH_ADDR"/>
1481 <reg32 offset="0x0200" name="CP_RB_BASE"/>
1482 <reg32 offset="0x0201" name="CP_RB_CNTL"/>
1483 <reg32 offset="0x0205" name="CP_RB_WPTR"/>
1484 <reg32 offset="0x0203" name="CP_RB_RPTR_ADDR"/>
1485 <reg32 offset="0x0204" name="CP_RB_RPTR"/>
1486 <reg32 offset="0x0206" name="CP_IB1_BASE"/>
1487 <reg32 offset="0x0207" name="CP_IB1_BUFSZ"/>
1488 <reg32 offset="0x0208" name="CP_IB2_BASE"/>
1489 <reg32 offset="0x0209" name="CP_IB2_BUFSZ"/>
1490 <reg32 offset="0x020c" name="CP_ME_NRT_ADDR"/>
1491 <reg32 offset="0x020d" name="CP_ME_NRT_DATA"/>
1492 <reg32 offset="0x0217" name="CP_ME_RB_DONE_DATA"/>
1493 <reg32 offset="0x0219" name="CP_QUEUE_THRESH2"/>
1494 <reg32 offset="0x021b" name="CP_MERCIU_SIZE"/>
1495 <reg32 offset="0x021c" name="CP_ROQ_ADDR"/>
1496 <reg32 offset="0x021d" name="CP_ROQ_DATA"/>
1497 <reg32 offset="0x021e" name="CP_MEQ_ADDR"/>
1498 <reg32 offset="0x021f" name="CP_MEQ_DATA"/>
1499 <reg32 offset="0x0220" name="CP_MERCIU_ADDR"/>
1500 <reg32 offset="0x0221" name="CP_MERCIU_DATA"/>
1501 <reg32 offset="0x0222" name="CP_MERCIU_DATA2"/>
1502 <reg32 offset="0x0223" name="CP_PFP_UCODE_ADDR"/>
1503 <reg32 offset="0x0224" name="CP_PFP_UCODE_DATA"/>
1504 <reg32 offset="0x0225" name="CP_ME_RAM_WADDR"/>
1505 <reg32 offset="0x0226" name="CP_ME_RAM_RADDR"/>
1506 <reg32 offset="0x0227" name="CP_ME_RAM_DATA"/>
1507 <reg32 offset="0x022a" name="CP_PREEMPT"/>
1508 <reg32 offset="0x022c" name="CP_CNTL"/>
1509 <reg32 offset="0x022d" name="CP_ME_CNTL"/>
1510 <reg32 offset="0x022e" name="CP_DEBUG"/>
1511 <reg32 offset="0x0231" name="CP_DEBUG_ECO_CONTROL"/>
1512 <reg32 offset="0x0232" name="CP_DRAW_STATE_ADDR"/>
1513 <array offset="0x0240" name="CP_PROTECT" stride="1" length="16">
1514 <reg32 offset="0x0" name="REG" type="adreno_cp_protect"/>
1515 </array>
1516 <reg32 offset="0x0250" name="CP_PROTECT_CTRL"/>
1517 <reg32 offset="0x04c0" name="CP_ST_BASE"/>
1518 <reg32 offset="0x04ce" name="CP_STQ_AVAIL"/>
1519 <reg32 offset="0x04d0" name="CP_MERCIU_STAT"/>
1520 <reg32 offset="0x04d2" name="CP_WFI_PEND_CTR"/>
1521 <reg32 offset="0x04d8" name="CP_HW_FAULT"/>
1522 <reg32 offset="0x04da" name="CP_PROTECT_STATUS"/>
1523 <reg32 offset="0x04dd" name="CP_EVENTS_IN_FLIGHT"/>
1524 <reg32 offset="0x0500" name="CP_PERFCTR_CP_SEL_0" type="a4xx_cp_perfcounter_select"/>
1525 <reg32 offset="0x0501" name="CP_PERFCTR_CP_SEL_1" type="a4xx_cp_perfcounter_select"/>
1526 <reg32 offset="0x0502" name="CP_PERFCTR_CP_SEL_2" type="a4xx_cp_perfcounter_select"/>
1527 <reg32 offset="0x0503" name="CP_PERFCTR_CP_SEL_3" type="a4xx_cp_perfcounter_select"/>
1528 <reg32 offset="0x0504" name="CP_PERFCTR_CP_SEL_4" type="a4xx_cp_perfcounter_select"/>
1529 <reg32 offset="0x0505" name="CP_PERFCTR_CP_SEL_5" type="a4xx_cp_perfcounter_select"/>
1530 <reg32 offset="0x0506" name="CP_PERFCTR_CP_SEL_6" type="a4xx_cp_perfcounter_select"/>
1531 <reg32 offset="0x0507" name="CP_PERFCTR_CP_SEL_7" type="a4xx_cp_perfcounter_select"/>
1532 <reg32 offset="0x050b" name="CP_PERFCOMBINER_SELECT"/>
1533 <array offset="0x0578" name="CP_SCRATCH" stride="1" length="23">
1534 <reg32 offset="0x0" name="REG"/>
1535 </array>
1536
1537
1538 <!-- SP registers -->
1539 <reg32 offset="0x0ec0" name="SP_VS_STATUS"/>
1540 <reg32 offset="0x0ec3" name="SP_MODE_CONTROL"/>
1541
1542 <reg32 offset="0x0ec4" name="SP_PERFCTR_SP_SEL_0" type="a4xx_sp_perfcounter_select"/>
1543 <reg32 offset="0x0ec5" name="SP_PERFCTR_SP_SEL_1" type="a4xx_sp_perfcounter_select"/>
1544 <reg32 offset="0x0ec6" name="SP_PERFCTR_SP_SEL_2" type="a4xx_sp_perfcounter_select"/>
1545 <reg32 offset="0x0ec7" name="SP_PERFCTR_SP_SEL_3" type="a4xx_sp_perfcounter_select"/>
1546 <reg32 offset="0x0ec8" name="SP_PERFCTR_SP_SEL_4" type="a4xx_sp_perfcounter_select"/>
1547 <reg32 offset="0x0ec9" name="SP_PERFCTR_SP_SEL_5" type="a4xx_sp_perfcounter_select"/>
1548 <reg32 offset="0x0eca" name="SP_PERFCTR_SP_SEL_6" type="a4xx_sp_perfcounter_select"/>
1549 <reg32 offset="0x0ecb" name="SP_PERFCTR_SP_SEL_7" type="a4xx_sp_perfcounter_select"/>
1550 <reg32 offset="0x0ecc" name="SP_PERFCTR_SP_SEL_8" type="a4xx_sp_perfcounter_select"/>
1551 <reg32 offset="0x0ecd" name="SP_PERFCTR_SP_SEL_9" type="a4xx_sp_perfcounter_select"/>
1552 <reg32 offset="0x0ece" name="SP_PERFCTR_SP_SEL_10" type="a4xx_sp_perfcounter_select"/>
1553 <reg32 offset="0x0ecf" name="SP_PERFCTR_SP_SEL_11" type="a4xx_sp_perfcounter_select"/>
1554
1555 <reg32 offset="0x22c0" name="SP_SP_CTRL_REG">
1556 <bitfield name="BINNING_PASS" pos="19" type="boolean"/>
1557 </reg32>
1558 <reg32 offset="0x22c1" name="SP_INSTR_CACHE_CTRL">
1559 <!-- set when VS in buffer mode: -->
1560 <bitfield name="VS_BUFFER" pos="7" type="boolean"/>
1561 <!-- set when FS in buffer mode: -->
1562 <bitfield name="FS_BUFFER" pos="8" type="boolean"/>
1563 <!-- set when both VS or FS in buffer mode: -->
1564 <bitfield name="INSTR_BUFFER" pos="10" type="boolean"/>
1565 <!-- TODO other bits probably matter when other stages active? -->
1566 </reg32>
1567
1568 <bitset name="a4xx_sp_vs_fs_ctrl_reg0" inline="yes">
1569 <!--
1570 NOTE that SP_{VS,FS}_CTRL_REG1 are different, but so far REG0
1571 appears to be the same..
1572 -->
1573 <bitfield name="THREADMODE" pos="0" type="a3xx_threadmode"/>
1574 <!-- VARYING bit only for FS.. think it controls emitting (ei) flag? -->
1575 <bitfield name="VARYING" pos="1" type="boolean"/>
1576 <!-- maybe CACHEINVALID is two bits?? -->
1577 <bitfield name="CACHEINVALID" pos="2" type="boolean"/>
1578 <doc>
1579 The full/half register footprint is in units of four components,
1580 so if r0.x is used, that counts as all of r0.[xyzw] as used.
1581 There are separate full/half register footprint values as the
1582 full and half registers are independent (not overlapping).
1583 Presumably the thread scheduler hardware allocates the full/half
1584 register names from the actual physical register file and
1585 handles the register renaming.
1586 </doc>
1587 <bitfield name="HALFREGFOOTPRINT" low="4" high="9" type="uint"/>
1588 <bitfield name="FULLREGFOOTPRINT" low="10" high="15" type="uint"/>
1589 <!-- maybe INOUTREGOVERLAP is a bitflag? -->
1590 <bitfield name="INOUTREGOVERLAP" low="18" high="19" type="uint"/>
1591 <bitfield name="THREADSIZE" pos="20" type="a3xx_threadsize"/>
1592 <bitfield name="SUPERTHREADMODE" pos="21" type="boolean"/>
1593 <bitfield name="PIXLODENABLE" pos="22" type="boolean"/>
1594 </bitset>
1595
1596 <reg32 offset="0x22c4" name="SP_VS_CTRL_REG0" type="a4xx_sp_vs_fs_ctrl_reg0"/>
1597 <reg32 offset="0x22c5" name="SP_VS_CTRL_REG1">
1598 <bitfield name="CONSTLENGTH" low="0" high="7" type="uint"/>
1599 <bitfield name="INITIALOUTSTANDING" low="24" high="30" type="uint"/>
1600 </reg32>
1601 <reg32 offset="0x22c6" name="SP_VS_PARAM_REG">
1602 <bitfield name="POSREGID" low="0" high="7" type="a3xx_regid"/>
1603 <bitfield name="PSIZEREGID" low="8" high="15" type="a3xx_regid"/>
1604 <bitfield name="TOTALVSOUTVAR" low="20" high="31" type="uint"/>
1605 </reg32>
1606 <array offset="0x22c7" name="SP_VS_OUT" stride="1" length="16">
1607 <reg32 offset="0x0" name="REG">
1608 <bitfield name="A_REGID" low="0" high="8" type="a3xx_regid"/>
1609 <bitfield name="A_COMPMASK" low="9" high="12" type="hex"/>
1610 <bitfield name="B_REGID" low="16" high="24" type="a3xx_regid"/>
1611 <bitfield name="B_COMPMASK" low="25" high="28" type="hex"/>
1612 </reg32>
1613 </array>
1614 <array offset="0x22d8" name="SP_VS_VPC_DST" stride="1" length="8">
1615 <reg32 offset="0x0" name="REG">
1616 <doc>
1617 These seem to be offsets for storage of the varyings.
1618 Always seems to start from 8, possibly loc 0 and 4
1619 are for gl_Position and gl_PointSize?
1620 </doc>
1621 <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
1622 <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
1623 <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
1624 <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
1625 </reg32>
1626 </array>
1627
1628 <reg32 offset="0x22e0" name="SP_VS_OBJ_OFFSET_REG">
1629 <!-- always 00000000: -->
1630 <doc>
1631 From register spec:
1632 SP_FS_OBJ_OFFSET_REG.CONSTOBJECTSTARTOFFSET [16:24]: Constant object
1633 start offset in on chip RAM,
1634 128bit aligned
1635 </doc>
1636 <bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/>
1637 <bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/>
1638 </reg32>
1639 <reg32 offset="0x22e1" name="SP_VS_OBJ_START"/>
1640 <reg32 offset="0x22e2" name="SP_VS_PVT_MEM_PARAM"/>"
1641 <reg32 offset="0x22e3" name="SP_VS_PVT_MEM_ADDR"/>
1642 <reg32 offset="0x22e5" name="SP_VS_LENGTH_REG" type="uint"/>
1643 <reg32 offset="0x22e8" name="SP_FS_CTRL_REG0" type="a4xx_sp_vs_fs_ctrl_reg0"/>
1644 <reg32 offset="0x22e9" name="SP_FS_CTRL_REG1">
1645 <bitfield name="CONSTLENGTH" low="0" high="7" type="uint"/>
1646 <bitfield name="FACENESS" pos="19" type="boolean"/>
1647 <bitfield name="VARYING" pos="20" type="boolean"/>
1648 <bitfield name="FRAGCOORD" pos="21" type="boolean"/>
1649 </reg32>
1650 <reg32 offset="0x22ea" name="SP_FS_OBJ_OFFSET_REG">
1651 <bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/>
1652 <bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/>
1653 </reg32>
1654 <reg32 offset="0x22eb" name="SP_FS_OBJ_START"/>
1655 <reg32 offset="0x22ec" name="SP_FS_PVT_MEM_PARAM"/>"
1656 <reg32 offset="0x22ed" name="SP_FS_PVT_MEM_ADDR"/>
1657 <reg32 offset="0x22ef" name="SP_FS_LENGTH_REG" type="uint"/>
1658 <reg32 offset="0x22f0" name="SP_FS_OUTPUT_REG">
1659 <bitfield name="MRT" low="0" high="3" type="uint"/>
1660 <bitfield name="DEPTH_ENABLE" pos="7" type="boolean"/>
1661 <!-- TODO double check.. for now assume same as a3xx -->
1662 <bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/>
1663 <bitfield name="SAMPLEMASK_REGID" low="24" high="31" type="a3xx_regid"/>
1664 </reg32>
1665 <array offset="0x22f1" name="SP_FS_MRT" stride="1" length="8">
1666 <reg32 offset="0x0" name="REG">
1667 <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
1668 <bitfield name="HALF_PRECISION" pos="8" type="boolean"/>
1669 <bitfield name="MRTFORMAT" low="12" high="17" type="a4xx_color_fmt"/>
1670 <bitfield name="COLOR_SRGB" pos="18" type="boolean"/>
1671 </reg32>
1672 </array>
1673 <reg32 offset="0x2300" name="SP_CS_CTRL_REG0"/>
1674 <reg32 offset="0x2301" name="SP_CS_OBJ_OFFSET_REG"/>
1675 <reg32 offset="0x2302" name="SP_CS_OBJ_START"/>
1676 <reg32 offset="0x2303" name="SP_CS_PVT_MEM_PARAM"/>
1677 <reg32 offset="0x2304" name="SP_CS_PVT_MEM_ADDR"/>
1678 <reg32 offset="0x2305" name="SP_CS_PVT_MEM_SIZE"/>
1679 <reg32 offset="0x2306" name="SP_CS_LENGTH_REG" type="uint"/>
1680 <reg32 offset="0x230d" name="SP_HS_OBJ_OFFSET_REG">
1681 <bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/>
1682 <bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/>
1683 </reg32>
1684 <reg32 offset="0x230e" name="SP_HS_OBJ_START"/>
1685 <reg32 offset="0x230f" name="SP_HS_PVT_MEM_PARAM"/>"
1686 <reg32 offset="0x2310" name="SP_HS_PVT_MEM_ADDR"/>
1687 <reg32 offset="0x2312" name="SP_HS_LENGTH_REG" type="uint"/>
1688
1689 <reg32 offset="0x231a" name="SP_DS_PARAM_REG">
1690 <bitfield name="POSREGID" low="0" high="7" type="a3xx_regid"/>
1691 <bitfield name="TOTALGSOUTVAR" low="20" high="31" type="uint"/>
1692 </reg32>
1693 <array offset="0x231b" name="SP_DS_OUT" stride="1" length="16">
1694 <reg32 offset="0x0" name="REG">
1695 <bitfield name="A_REGID" low="0" high="8" type="a3xx_regid"/>
1696 <bitfield name="A_COMPMASK" low="9" high="12" type="hex"/>
1697 <bitfield name="B_REGID" low="16" high="24" type="a3xx_regid"/>
1698 <bitfield name="B_COMPMASK" low="25" high="28" type="hex"/>
1699 </reg32>
1700 </array>
1701 <array offset="0x232c" name="SP_DS_VPC_DST" stride="1" length="8">
1702 <reg32 offset="0x0" name="REG">
1703 <doc>
1704 These seem to be offsets for storage of the varyings.
1705 Always seems to start from 8, possibly loc 0 and 4
1706 are for gl_Position and gl_PointSize?
1707 </doc>
1708 <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
1709 <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
1710 <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
1711 <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
1712 </reg32>
1713 </array>
1714 <reg32 offset="0x2334" name="SP_DS_OBJ_OFFSET_REG">
1715 <bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/>
1716 <bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/>
1717 </reg32>
1718 <reg32 offset="0x2335" name="SP_DS_OBJ_START"/>
1719 <reg32 offset="0x2336" name="SP_DS_PVT_MEM_PARAM"/>"
1720 <reg32 offset="0x2337" name="SP_DS_PVT_MEM_ADDR"/>
1721 <reg32 offset="0x2339" name="SP_DS_LENGTH_REG" type="uint"/>
1722
1723 <reg32 offset="0x2341" name="SP_GS_PARAM_REG">
1724 <bitfield name="POSREGID" low="0" high="7" type="a3xx_regid"/>
1725 <bitfield name="PRIMREGID" low="8" high="15" type="a3xx_regid"/>
1726 <bitfield name="TOTALGSOUTVAR" low="20" high="31" type="uint"/>
1727 </reg32>
1728 <array offset="0x2342" name="SP_GS_OUT" stride="1" length="16">
1729 <reg32 offset="0x0" name="REG">
1730 <bitfield name="A_REGID" low="0" high="8" type="a3xx_regid"/>
1731 <bitfield name="A_COMPMASK" low="9" high="12" type="hex"/>
1732 <bitfield name="B_REGID" low="16" high="24" type="a3xx_regid"/>
1733 <bitfield name="B_COMPMASK" low="25" high="28" type="hex"/>
1734 </reg32>
1735 </array>
1736 <array offset="0x2353" name="SP_GS_VPC_DST" stride="1" length="8">
1737 <reg32 offset="0x0" name="REG">
1738 <doc>
1739 These seem to be offsets for storage of the varyings.
1740 Always seems to start from 8, possibly loc 0 and 4
1741 are for gl_Position and gl_PointSize?
1742 </doc>
1743 <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
1744 <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
1745 <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
1746 <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
1747 </reg32>
1748 </array>
1749 <reg32 offset="0x235b" name="SP_GS_OBJ_OFFSET_REG">
1750 <bitfield name="CONSTOBJECTOFFSET" low="16" high="24" type="uint"/>
1751 <bitfield name="SHADEROBJOFFSET" low="25" high="31" type="uint"/>
1752 </reg32>
1753 <reg32 offset="0x235c" name="SP_GS_OBJ_START"/>
1754 <reg32 offset="0x235d" name="SP_GS_PVT_MEM_PARAM"/>"
1755 <reg32 offset="0x235e" name="SP_GS_PVT_MEM_ADDR"/>
1756 <reg32 offset="0x2360" name="SP_GS_LENGTH_REG" type="uint"/>
1757
1758 <!-- VPC registers -->
1759 <reg32 offset="0x0e60" name="VPC_DEBUG_RAM_SEL"/>
1760 <reg32 offset="0x0e61" name="VPC_DEBUG_RAM_READ"/>
1761 <reg32 offset="0x0e64" name="VPC_DEBUG_ECO_CONTROL"/>
1762 <reg32 offset="0x0e65" name="VPC_PERFCTR_VPC_SEL_0" type="a4xx_vpc_perfcounter_select"/>
1763 <reg32 offset="0x0e66" name="VPC_PERFCTR_VPC_SEL_1" type="a4xx_vpc_perfcounter_select"/>
1764 <reg32 offset="0x0e67" name="VPC_PERFCTR_VPC_SEL_2" type="a4xx_vpc_perfcounter_select"/>
1765 <reg32 offset="0x0e68" name="VPC_PERFCTR_VPC_SEL_3" type="a4xx_vpc_perfcounter_select"/>
1766 <reg32 offset="0x2140" name="VPC_ATTR">
1767 <bitfield name="TOTALATTR" low="0" high="8" type="uint"/>
1768 <!-- PSIZE bit set if gl_PointSize written: -->
1769 <bitfield name="PSIZE" pos="9" type="boolean"/>
1770 <bitfield name="THRDASSIGN" low="12" high="13" type="uint"/>
1771 <bitfield name="ENABLE" pos="25" type="boolean"/>
1772 </reg32>
1773 <reg32 offset="0x2141" name="VPC_PACK">
1774 <bitfield name="NUMBYPASSVAR" low="0" high="7" type="uint"/>
1775 <bitfield name="NUMFPNONPOSVAR" low="8" high="15" type="uint"/>
1776 <bitfield name="NUMNONPOSVSVAR" low="16" high="23" type="uint"/>
1777 </reg32>
1778 <array offset="0x2142" name="VPC_VARYING_INTERP" stride="1" length="8">
1779 <reg32 offset="0x0" name="MODE"/>
1780 </array>
1781 <array offset="0x214a" name="VPC_VARYING_PS_REPL" stride="1" length="8">
1782 <reg32 offset="0x0" name="MODE"/>
1783 </array>
1784
1785 <reg32 offset="0x216e" name="VPC_SO_FLUSH_WADDR_3"/>
1786
1787 <!-- VSC registers -->
1788 <reg32 offset="0x0c00" name="VSC_BIN_SIZE">
1789 <bitfield name="WIDTH" low="0" high="4" shr="5" type="uint"/>
1790 <bitfield name="HEIGHT" low="5" high="9" shr="5" type="uint"/>
1791 </reg32>
1792 <reg32 offset="0x0c01" name="VSC_SIZE_ADDRESS"/>
1793 <reg32 offset="0x0c02" name="VSC_SIZE_ADDRESS2"/>
1794 <reg32 offset="0x0c03" name="VSC_DEBUG_ECO_CONTROL"/>
1795 <array offset="0x0c08" name="VSC_PIPE_CONFIG" stride="1" length="8">
1796 <reg32 offset="0x0" name="REG">
1797 <doc>
1798 Configures the mapping between VSC_PIPE buffer and
1799 bin, X/Y specify the bin index in the horiz/vert
1800 direction (0,0 is upper left, 0,1 is leftmost bin
1801 on second row, and so on). W/H specify the number
1802 of bins assigned to this VSC_PIPE in the horiz/vert
1803 dimension.
1804 </doc>
1805 <bitfield name="X" low="0" high="9" type="uint"/>
1806 <bitfield name="Y" low="10" high="19" type="uint"/>
1807 <bitfield name="W" low="20" high="23" type="uint"/>
1808 <bitfield name="H" low="24" high="27" type="uint"/>
1809 </reg32>
1810 </array>
1811 <array offset="0x0c10" name="VSC_PIPE_DATA_ADDRESS" stride="1" length="8">
1812 <reg32 offset="0x0" name="REG"/>
1813 </array>
1814 <array offset="0x0c18" name="VSC_PIPE_DATA_LENGTH" stride="1" length="8">
1815 <reg32 offset="0x0" name="REG"/>
1816 </array>
1817 <reg32 offset="0x0c41" name="VSC_PIPE_PARTIAL_POSN_1"/>
1818 <reg32 offset="0x0c50" name="VSC_PERFCTR_VSC_SEL_0" type="a4xx_vsc_perfcounter_select"/>
1819 <reg32 offset="0x0c51" name="VSC_PERFCTR_VSC_SEL_1" type="a4xx_vsc_perfcounter_select"/>
1820
1821 <!-- VFD registers -->
1822 <reg32 offset="0x0e40" name="VFD_DEBUG_CONTROL"/>
1823 <reg32 offset="0x0e43" name="VFD_PERFCTR_VFD_SEL_0" type="a4xx_vfd_perfcounter_select"/>
1824 <reg32 offset="0x0e44" name="VFD_PERFCTR_VFD_SEL_1" type="a4xx_vfd_perfcounter_select"/>
1825 <reg32 offset="0x0e45" name="VFD_PERFCTR_VFD_SEL_2" type="a4xx_vfd_perfcounter_select"/>
1826 <reg32 offset="0x0e46" name="VFD_PERFCTR_VFD_SEL_3" type="a4xx_vfd_perfcounter_select"/>
1827 <reg32 offset="0x0e47" name="VFD_PERFCTR_VFD_SEL_4" type="a4xx_vfd_perfcounter_select"/>
1828 <reg32 offset="0x0e48" name="VFD_PERFCTR_VFD_SEL_5" type="a4xx_vfd_perfcounter_select"/>
1829 <reg32 offset="0x0e49" name="VFD_PERFCTR_VFD_SEL_6" type="a4xx_vfd_perfcounter_select"/>
1830 <reg32 offset="0x0e4a" name="VFD_PERFCTR_VFD_SEL_7" type="a4xx_vfd_perfcounter_select"/>
1831 <reg32 offset="0x21d0" name="VGT_CL_INITIATOR"/>
1832 <reg32 offset="0x21d9" name="VGT_EVENT_INITIATOR"/>
1833 <reg32 offset="0x2200" name="VFD_CONTROL_0">
1834 <doc>
1835 TOTALATTRTOVS is # of attributes to vertex shader, in register
1836 slots (ie. vec4+vec3 -> 7)
1837 </doc>
1838 <bitfield name="TOTALATTRTOVS" low="0" high="7" type="uint"/>
1839 <doc>
1840 BYPASSATTROVS seems to count varyings that are just directly
1841 assigned from attributes (ie, "vFoo = aFoo;")
1842 </doc>
1843 <bitfield name="BYPASSATTROVS" low="9" high="16" type="uint"/>
1844 <doc>STRMDECINSTRCNT is # of VFD_DECODE_INSTR registers valid</doc>
1845 <bitfield name="STRMDECINSTRCNT" low="20" high="25" type="uint"/>
1846 <doc>STRMFETCHINSTRCNT is # of VFD_FETCH_INSTR registers valid</doc>
1847 <bitfield name="STRMFETCHINSTRCNT" low="26" high="31" type="uint"/>
1848 </reg32>
1849 <reg32 offset="0x2201" name="VFD_CONTROL_1">
1850 <doc>MAXSTORAGE could be # of attributes/vbo's</doc>
1851 <bitfield name="MAXSTORAGE" low="0" high="15" type="uint"/>
1852 <bitfield name="REGID4VTX" low="16" high="23" type="a3xx_regid"/>
1853 <bitfield name="REGID4INST" low="24" high="31" type="a3xx_regid"/>
1854 </reg32>
1855 <reg32 offset="0x2202" name="VFD_CONTROL_2"/>
1856 <reg32 offset="0x2203" name="VFD_CONTROL_3">
1857 <bitfield name="REGID_VTXCNT" low="8" high="15" type="a3xx_regid"/>
1858 <bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/>
1859 <bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/>
1860 </reg32>
1861 <reg32 offset="0x2204" name="VFD_CONTROL_4"/>
1862 <reg32 offset="0x2208" name="VFD_INDEX_OFFSET"/>
1863 <array offset="0x220a" name="VFD_FETCH" stride="4" length="32">
1864 <reg32 offset="0x0" name="INSTR_0">
1865 <bitfield name="FETCHSIZE" low="0" high="6" type="uint"/>
1866 <bitfield name="BUFSTRIDE" low="7" high="16" type="uint"/>
1867 <bitfield name="SWITCHNEXT" pos="19" type="boolean"/>
1868 <bitfield name="INSTANCED" pos="20" type="boolean"/>
1869 </reg32>
1870 <reg32 offset="0x1" name="INSTR_1"/>
1871 <reg32 offset="0x2" name="INSTR_2">
1872 <bitfield name="SIZE" low="0" high="31"/>
1873 </reg32>
1874 <reg32 offset="0x3" name="INSTR_3">
1875 <!-- might well be bigger.. -->
1876 <bitfield name="STEPRATE" low="0" high="8" type="uint"/>
1877 </reg32>
1878 </array>
1879 <array offset="0x228a" name="VFD_DECODE" stride="1" length="32">
1880 <reg32 offset="0x0" name="INSTR">
1881 <bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
1882 <!-- not sure if this is a bit flag and another flag above it, or?? -->
1883 <bitfield name="CONSTFILL" pos="4" type="boolean"/>
1884 <bitfield name="FORMAT" low="6" high="11" type="a4xx_vtx_fmt"/>
1885 <bitfield name="REGID" low="12" high="19" type="a3xx_regid"/>
1886 <bitfield name="INT" pos="20" type="boolean"/>
1887 <doc>SHIFTCNT appears to be size, ie. FLOAT_32_32_32 is 12, and BYTE_8 is 1</doc>
1888 <bitfield name="SWAP" low="22" high="23" type="a3xx_color_swap"/>
1889 <bitfield name="SHIFTCNT" low="24" high="28" type="uint"/>
1890 <bitfield name="LASTCOMPVALID" pos="29" type="boolean"/>
1891 <bitfield name="SWITCHNEXT" pos="30" type="boolean"/>
1892 </reg32>
1893 </array>
1894
1895 <!-- TPL1 registers -->
1896 <reg32 offset="0x0f00" name="TPL1_DEBUG_ECO_CONTROL"/>
1897 <!-- always 0000003a: -->
1898 <reg32 offset="0x0f03" name="TPL1_TP_MODE_CONTROL"/>
1899 <reg32 offset="0x0f04" name="TPL1_PERFCTR_TP_SEL_0" type="a4xx_tp_perfcounter_select"/>
1900 <reg32 offset="0x0f05" name="TPL1_PERFCTR_TP_SEL_1" type="a4xx_tp_perfcounter_select"/>
1901 <reg32 offset="0x0f06" name="TPL1_PERFCTR_TP_SEL_2" type="a4xx_tp_perfcounter_select"/>
1902 <reg32 offset="0x0f07" name="TPL1_PERFCTR_TP_SEL_3" type="a4xx_tp_perfcounter_select"/>
1903 <reg32 offset="0x0f08" name="TPL1_PERFCTR_TP_SEL_4" type="a4xx_tp_perfcounter_select"/>
1904 <reg32 offset="0x0f09" name="TPL1_PERFCTR_TP_SEL_5" type="a4xx_tp_perfcounter_select"/>
1905 <reg32 offset="0x0f0a" name="TPL1_PERFCTR_TP_SEL_6" type="a4xx_tp_perfcounter_select"/>
1906 <reg32 offset="0x0f0b" name="TPL1_PERFCTR_TP_SEL_7" type="a4xx_tp_perfcounter_select"/>
1907 <reg32 offset="0x2380" name="TPL1_TP_TEX_OFFSET"/>
1908 <reg32 offset="0x2381" name="TPL1_TP_TEX_COUNT">
1909 <bitfield name="VS" low="0" high="7" type="uint"/>
1910 <bitfield name="HS" low="8" high="15" type="uint"/>
1911 <bitfield name="DS" low="16" high="23" type="uint"/>
1912 <bitfield name="GS" low="24" high="31" type="uint"/>
1913 </reg32>
1914 <reg32 offset="0x2384" name="TPL1_TP_VS_BORDER_COLOR_BASE_ADDR"/>
1915 <reg32 offset="0x2387" name="TPL1_TP_HS_BORDER_COLOR_BASE_ADDR"/>
1916 <reg32 offset="0x238a" name="TPL1_TP_DS_BORDER_COLOR_BASE_ADDR"/>
1917 <reg32 offset="0x238d" name="TPL1_TP_GS_BORDER_COLOR_BASE_ADDR"/>
1918 <reg32 offset="0x23a0" name="TPL1_TP_FS_TEX_COUNT"/>
1919 <reg32 offset="0x23a1" name="TPL1_TP_FS_BORDER_COLOR_BASE_ADDR"/>
1920 <reg32 offset="0x23a4" name="TPL1_TP_CS_BORDER_COLOR_BASE_ADDR"/>
1921 <reg32 offset="0x23a5" name="TPL1_TP_CS_SAMPLER_BASE_ADDR"/>
1922 <reg32 offset="0x23a6" name="TPL1_TP_CS_TEXMEMOBJ_BASE_ADDR"/>
1923
1924 <!-- GRAS registers -->
1925 <reg32 offset="0x0c80" name="GRAS_TSE_STATUS"/>
1926 <reg32 offset="0x0c81" name="GRAS_DEBUG_ECO_CONTROL"/>
1927 <reg32 offset="0x0c88" name="GRAS_PERFCTR_TSE_SEL_0" type="a4xx_gras_tse_perfcounter_select"/>
1928 <reg32 offset="0x0c89" name="GRAS_PERFCTR_TSE_SEL_1" type="a4xx_gras_tse_perfcounter_select"/>
1929 <reg32 offset="0x0c8a" name="GRAS_PERFCTR_TSE_SEL_2" type="a4xx_gras_tse_perfcounter_select"/>
1930 <reg32 offset="0x0c8b" name="GRAS_PERFCTR_TSE_SEL_3" type="a4xx_gras_tse_perfcounter_select"/>
1931 <reg32 offset="0x0c8c" name="GRAS_PERFCTR_RAS_SEL_0" type="a4xx_gras_ras_perfcounter_select"/>
1932 <reg32 offset="0x0c8d" name="GRAS_PERFCTR_RAS_SEL_1" type="a4xx_gras_ras_perfcounter_select"/>
1933 <reg32 offset="0x0c8e" name="GRAS_PERFCTR_RAS_SEL_2" type="a4xx_gras_ras_perfcounter_select"/>
1934 <reg32 offset="0x0c8f" name="GRAS_PERFCTR_RAS_SEL_3" type="a4xx_gras_ras_perfcounter_select"/>
1935 <reg32 offset="0x2000" name="GRAS_CL_CLIP_CNTL">
1936 <bitfield name="CLIP_DISABLE" pos="15" type="boolean"/>
1937 <bitfield name="ZNEAR_CLIP_DISABLE" pos="16" type="boolean"/>
1938 <bitfield name="ZFAR_CLIP_DISABLE" pos="17" type="boolean"/>
1939 <bitfield name="ZERO_GB_SCALE_Z" pos="22" type="boolean"/>
1940 </reg32>
1941 <reg32 offset="0x2003" name="GRAS_CNTL">
1942 <bitfield name="IJ_PERSP" pos="0" type="boolean"/>
1943 <bitfield name="IJ_LINEAR" pos="1" type="boolean"/>
1944 </reg32>
1945 <reg32 offset="0x2004" name="GRAS_CL_GB_CLIP_ADJ">
1946 <bitfield name="HORZ" low="0" high="9" type="uint"/>
1947 <bitfield name="VERT" low="10" high="19" type="uint"/>
1948 </reg32>
1949 <reg32 offset="0x2008" name="GRAS_CL_VPORT_XOFFSET_0" type="float"/>
1950 <reg32 offset="0x2009" name="GRAS_CL_VPORT_XSCALE_0" type="float"/>
1951 <reg32 offset="0x200a" name="GRAS_CL_VPORT_YOFFSET_0" type="float"/>
1952 <reg32 offset="0x200b" name="GRAS_CL_VPORT_YSCALE_0" type="float"/>
1953 <reg32 offset="0x200c" name="GRAS_CL_VPORT_ZOFFSET_0" type="float"/>
1954 <reg32 offset="0x200d" name="GRAS_CL_VPORT_ZSCALE_0" type="float"/>
1955 <reg32 offset="0x2070" name="GRAS_SU_POINT_MINMAX">
1956 <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
1957 <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
1958 </reg32>
1959 <reg32 offset="0x2071" name="GRAS_SU_POINT_SIZE" type="fixed" radix="4"/>
1960 <reg32 offset="0x2073" name="GRAS_ALPHA_CONTROL">
1961 <bitfield name="ALPHA_TEST_ENABLE" pos="2" type="boolean"/>
1962 <bitfield name="FORCE_FRAGZ_TO_FS" pos="3" type="boolean"/>
1963 </reg32>
1964 <reg32 offset="0x2074" name="GRAS_SU_POLY_OFFSET_SCALE" type="float"/>
1965 <reg32 offset="0x2075" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float"/>
1966 <reg32 offset="0x2076" name="GRAS_SU_POLY_OFFSET_CLAMP" type="float"/>
1967 <reg32 offset="0x2077" name="GRAS_DEPTH_CONTROL">
1968 <!-- guestimating that this is GRAS based on addr -->
1969 <bitfield name="FORMAT" low="0" high="1" type="a4xx_depth_format"/>
1970 </reg32>
1971 <reg32 offset="0x2078" name="GRAS_SU_MODE_CONTROL">
1972 <bitfield name="CULL_FRONT" pos="0" type="boolean"/>
1973 <bitfield name="CULL_BACK" pos="1" type="boolean"/>
1974 <bitfield name="FRONT_CW" pos="2" type="boolean"/>
1975 <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
1976 <bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
1977 <bitfield name="MSAA_ENABLE" pos="13" type="boolean"/>
1978 <!-- bit20 set whenever RENDER_MODE = RB_RENDERING_PASS -->
1979 <bitfield name="RENDERING_PASS" pos="20" type="boolean"/>
1980 </reg32>
1981 <reg32 offset="0x207b" name="GRAS_SC_CONTROL">
1982 <!-- complete wild-ass-guess for sizes of these bitfields.. -->
1983 <bitfield name="RENDER_MODE" low="2" high="3" type="a3xx_render_mode"/>
1984 <bitfield name="MSAA_SAMPLES" low="7" high="9" type="uint"/>
1985 <bitfield name="MSAA_DISABLE" pos="11" type="boolean"/>
1986 <bitfield name="RASTER_MODE" low="12" high="15"/>
1987 </reg32>
1988 <reg32 offset="0x207c" name="GRAS_SC_SCREEN_SCISSOR_TL" type="adreno_reg_xy"/>
1989 <reg32 offset="0x207d" name="GRAS_SC_SCREEN_SCISSOR_BR" type="adreno_reg_xy"/>
1990 <reg32 offset="0x209c" name="GRAS_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/>
1991 <reg32 offset="0x209d" name="GRAS_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/>
1992 <reg32 offset="0x209e" name="GRAS_SC_EXTENT_WINDOW_BR" type="adreno_reg_xy"/>
1993 <reg32 offset="0x209f" name="GRAS_SC_EXTENT_WINDOW_TL" type="adreno_reg_xy"/>
1994
1995 <!-- UCHE registers -->
1996 <reg32 offset="0x0e80" name="UCHE_CACHE_MODE_CONTROL"/>
1997 <reg32 offset="0x0e83" name="UCHE_TRAP_BASE_LO"/>
1998 <reg32 offset="0x0e84" name="UCHE_TRAP_BASE_HI"/>
1999 <reg32 offset="0x0e88" name="UCHE_CACHE_STATUS"/>
2000 <reg32 offset="0x0e8a" name="UCHE_INVALIDATE0"/>
2001 <reg32 offset="0x0e8b" name="UCHE_INVALIDATE1"/>
2002 <reg32 offset="0x0e8c" name="UCHE_CACHE_WAYS_VFD"/>
2003 <reg32 offset="0x0e8e" name="UCHE_PERFCTR_UCHE_SEL_0" type="a4xx_uche_perfcounter_select"/>
2004 <reg32 offset="0x0e8f" name="UCHE_PERFCTR_UCHE_SEL_1" type="a4xx_uche_perfcounter_select"/>
2005 <reg32 offset="0x0e90" name="UCHE_PERFCTR_UCHE_SEL_2" type="a4xx_uche_perfcounter_select"/>
2006 <reg32 offset="0x0e91" name="UCHE_PERFCTR_UCHE_SEL_3" type="a4xx_uche_perfcounter_select"/>
2007 <reg32 offset="0x0e92" name="UCHE_PERFCTR_UCHE_SEL_4" type="a4xx_uche_perfcounter_select"/>
2008 <reg32 offset="0x0e93" name="UCHE_PERFCTR_UCHE_SEL_5" type="a4xx_uche_perfcounter_select"/>
2009 <reg32 offset="0x0e94" name="UCHE_PERFCTR_UCHE_SEL_6" type="a4xx_uche_perfcounter_select"/>
2010 <reg32 offset="0x0e95" name="UCHE_PERFCTR_UCHE_SEL_7" type="a4xx_uche_perfcounter_select"/>
2011
2012 <!-- HLSQ registers -->
2013 <reg32 offset="0x0e00" name="HLSQ_TIMEOUT_THRESHOLD"/>
2014 <reg32 offset="0x0e04" name="HLSQ_DEBUG_ECO_CONTROL"/>
2015 <!-- always 00000000: -->
2016 <reg32 offset="0x0e05" name="HLSQ_MODE_CONTROL"/>
2017 <reg32 offset="0x0e0e" name="HLSQ_PERF_PIPE_MASK"/>
2018 <reg32 offset="0x0e06" name="HLSQ_PERFCTR_HLSQ_SEL_0" type="a4xx_hlsq_perfcounter_select"/>
2019 <reg32 offset="0x0e07" name="HLSQ_PERFCTR_HLSQ_SEL_1" type="a4xx_hlsq_perfcounter_select"/>
2020 <reg32 offset="0x0e08" name="HLSQ_PERFCTR_HLSQ_SEL_2" type="a4xx_hlsq_perfcounter_select"/>
2021 <reg32 offset="0x0e09" name="HLSQ_PERFCTR_HLSQ_SEL_3" type="a4xx_hlsq_perfcounter_select"/>
2022 <reg32 offset="0x0e0a" name="HLSQ_PERFCTR_HLSQ_SEL_4" type="a4xx_hlsq_perfcounter_select"/>
2023 <reg32 offset="0x0e0b" name="HLSQ_PERFCTR_HLSQ_SEL_5" type="a4xx_hlsq_perfcounter_select"/>
2024 <reg32 offset="0x0e0c" name="HLSQ_PERFCTR_HLSQ_SEL_6" type="a4xx_hlsq_perfcounter_select"/>
2025 <reg32 offset="0x0e0d" name="HLSQ_PERFCTR_HLSQ_SEL_7" type="a4xx_hlsq_perfcounter_select"/>
2026 <reg32 offset="0x23c0" name="HLSQ_CONTROL_0_REG">
2027 <!-- I guess same as a3xx, but so far only seen 08000050 -->
2028 <bitfield name="FSTHREADSIZE" pos="4" type="a3xx_threadsize"/>
2029 <bitfield name="FSSUPERTHREADENABLE" pos="6" type="boolean"/>
2030 <bitfield name="SPSHADERRESTART" pos="9" type="boolean"/>
2031 <bitfield name="RESERVED2" pos="10" type="boolean"/>
2032 <bitfield name="CHUNKDISABLE" pos="26" type="boolean"/>
2033 <bitfield name="CONSTMODE" pos="27" type="uint"/>
2034 <bitfield name="LAZYUPDATEDISABLE" pos="28" type="boolean"/>
2035 <bitfield name="SPCONSTFULLUPDATE" pos="29" type="boolean"/>
2036 <bitfield name="TPFULLUPDATE" pos="30" type="boolean"/>
2037 <bitfield name="SINGLECONTEXT" pos="31" type="boolean"/>
2038 </reg32>
2039 <reg32 offset="0x23c1" name="HLSQ_CONTROL_1_REG">
2040 <bitfield name="VSTHREADSIZE" pos="6" type="a3xx_threadsize"/>
2041 <bitfield name="VSSUPERTHREADENABLE" pos="8" type="boolean"/>
2042 <bitfield name="RESERVED1" pos="9" type="boolean"/>
2043 <bitfield name="COORDREGID" low="16" high="23" type="a3xx_regid"/>
2044 <!-- set if gl_FragCoord.[zw] used in frag shader: -->
2045 <bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/>
2046 </reg32>
2047 <reg32 offset="0x23c2" name="HLSQ_CONTROL_2_REG">
2048 <bitfield name="PRIMALLOCTHRESHOLD" low="26" high="31" type="uint"/>
2049 <bitfield name="FACEREGID" low="2" high="9" type="a3xx_regid"/>
2050 <bitfield name="SAMPLEID_REGID" low="10" high="17" type="a3xx_regid"/>
2051 <bitfield name="SAMPLEMASK_REGID" low="18" high="25" type="a3xx_regid"/>
2052 </reg32>
2053 <reg32 offset="0x23c3" name="HLSQ_CONTROL_3_REG">
2054 <!-- register loaded with position (bary.f) -->
2055 <bitfield name="IJ_PERSP_PIXEL" low="0" high="7" type="a3xx_regid"/>
2056 <bitfield name="IJ_LINEAR_PIXEL" low="8" high="15" type="a3xx_regid"/>
2057 <bitfield name="IJ_PERSP_CENTROID" low="16" high="23" type="a3xx_regid"/>
2058 <bitfield name="IJ_LINEAR_CENTROID" low="24" high="31" type="a3xx_regid"/>
2059 </reg32>
2060 <!-- 0x23c4 3 regids, lowest one goes to 0 when *not* per-sample shading -->
2061 <reg32 offset="0x23c4" name="HLSQ_CONTROL_4_REG">
2062 <bitfield name="IJ_PERSP_SAMPLE" low="0" high="7" type="a3xx_regid"/>
2063 <bitfield name="IJ_LINEAR_SAMPLE" low="8" high="15" type="a3xx_regid"/>
2064 </reg32>
2065
2066 <bitset name="a4xx_xs_control_reg" inline="yes">
2067 <bitfield name="CONSTLENGTH" low="0" high="7" type="uint"/>
2068 <bitfield name="CONSTOBJECTOFFSET" low="8" high="14" type="uint"/>
2069 <bitfield name="SSBO_ENABLE" pos="15"/>
2070 <bitfield name="ENABLED" pos="16"/>
2071 <bitfield name="SHADEROBJOFFSET" low="17" high="23" type="uint"/>
2072 <bitfield name="INSTRLENGTH" low="24" high="31" type="uint"/>
2073 </bitset>
2074 <reg32 offset="0x23c5" name="HLSQ_VS_CONTROL_REG" type="a4xx_xs_control_reg"/>
2075 <reg32 offset="0x23c6" name="HLSQ_FS_CONTROL_REG" type="a4xx_xs_control_reg"/>
2076 <reg32 offset="0x23c7" name="HLSQ_HS_CONTROL_REG" type="a4xx_xs_control_reg"/>
2077 <reg32 offset="0x23c8" name="HLSQ_DS_CONTROL_REG" type="a4xx_xs_control_reg"/>
2078 <reg32 offset="0x23c9" name="HLSQ_GS_CONTROL_REG" type="a4xx_xs_control_reg"/>
2079 <reg32 offset="0x23ca" name="HLSQ_CS_CONTROL_REG" type="a4xx_xs_control_reg"/>
2080 <reg32 offset="0x23cd" name="HLSQ_CL_NDRANGE_0">
2081 <bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
2082 <!-- localsize is value minus one: -->
2083 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
2084 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
2085 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
2086 </reg32>
2087 <reg32 offset="0x23ce" name="HLSQ_CL_NDRANGE_1">
2088 <bitfield name="SIZE_X" low="0" high="31" type="uint"/>
2089 </reg32>
2090 <reg32 offset="0x23cf" name="HLSQ_CL_NDRANGE_2"/>
2091 <reg32 offset="0x23d0" name="HLSQ_CL_NDRANGE_3">
2092 <bitfield name="SIZE_Y" low="0" high="31" type="uint"/>
2093 </reg32>
2094 <reg32 offset="0x23d1" name="HLSQ_CL_NDRANGE_4"/>
2095 <reg32 offset="0x23d2" name="HLSQ_CL_NDRANGE_5">
2096 <bitfield name="SIZE_Z" low="0" high="31" type="uint"/>
2097 </reg32>
2098 <reg32 offset="0x23d3" name="HLSQ_CL_NDRANGE_6"/>
2099 <reg32 offset="0x23d4" name="HLSQ_CL_CONTROL_0">
2100 <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>
2101 <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>
2102 </reg32>
2103 <reg32 offset="0x23d5" name="HLSQ_CL_CONTROL_1"/>
2104 <reg32 offset="0x23d6" name="HLSQ_CL_KERNEL_CONST"/>
2105 <reg32 offset="0x23d7" name="HLSQ_CL_KERNEL_GROUP_X"/>
2106 <reg32 offset="0x23d8" name="HLSQ_CL_KERNEL_GROUP_Y"/>
2107 <reg32 offset="0x23d9" name="HLSQ_CL_KERNEL_GROUP_Z"/>
2108 <reg32 offset="0x23da" name="HLSQ_CL_WG_OFFSET"/>
2109 <reg32 offset="0x23db" name="HLSQ_UPDATE_CONTROL"/>
2110
2111 <!-- PC registers -->
2112 <reg32 offset="0x0d00" name="PC_BINNING_COMMAND">
2113 <bitfield name="BINNING_ENABLE" pos="0" type="boolean"/>
2114 </reg32>
2115 <reg32 offset="0x0d08" name="PC_TESSFACTOR_ADDR"/>
2116 <reg32 offset="0x0d0c" name="PC_DRAWCALL_SETUP_OVERRIDE"/>
2117 <reg32 offset="0x0d10" name="PC_PERFCTR_PC_SEL_0" type="a4xx_pc_perfcounter_select"/>
2118 <reg32 offset="0x0d11" name="PC_PERFCTR_PC_SEL_1" type="a4xx_pc_perfcounter_select"/>
2119 <reg32 offset="0x0d12" name="PC_PERFCTR_PC_SEL_2" type="a4xx_pc_perfcounter_select"/>
2120 <reg32 offset="0x0d13" name="PC_PERFCTR_PC_SEL_3" type="a4xx_pc_perfcounter_select"/>
2121 <reg32 offset="0x0d14" name="PC_PERFCTR_PC_SEL_4" type="a4xx_pc_perfcounter_select"/>
2122 <reg32 offset="0x0d15" name="PC_PERFCTR_PC_SEL_5" type="a4xx_pc_perfcounter_select"/>
2123 <reg32 offset="0x0d16" name="PC_PERFCTR_PC_SEL_6" type="a4xx_pc_perfcounter_select"/>
2124 <reg32 offset="0x0d17" name="PC_PERFCTR_PC_SEL_7" type="a4xx_pc_perfcounter_select"/>
2125 <reg32 offset="0x21c0" name="PC_BIN_BASE"/>
2126 <reg32 offset="0x21c2" name="PC_VSTREAM_CONTROL">
2127 <doc>SIZE is current pipe width * height (in tiles)</doc>
2128 <bitfield name="SIZE" low="16" high="21" type="uint"/>
2129 <doc>
2130 N is some sort of slot # between 0..(SIZE-1). In case
2131 multiple tiles use same pipe, each tile gets unique slot #
2132 </doc>
2133 <bitfield name="N" low="22" high="26" type="uint"/>
2134 </reg32>
2135 <reg32 offset="0x21c4" name="PC_PRIM_VTX_CNTL">
2136 <!-- bit0 set if there is >= 1 varying (actually used by FS) -->
2137 <bitfield name="VAROUT" low="0" high="3" type="uint">
2138 <doc>in groups of 4x vec4, blob only uses values
2139 0, 1, 2, 4, 6, 8</doc>
2140 </bitfield>
2141 <bitfield name="PRIMITIVE_RESTART" pos="20" type="boolean"/>
2142 <bitfield name="PROVOKING_VTX_LAST" pos="25" type="boolean"/>
2143 <!-- PSIZE bit set if gl_PointSize written: -->
2144 <bitfield name="PSIZE" pos="26" type="boolean"/>
2145 </reg32>
2146 <reg32 offset="0x21c5" name="PC_PRIM_VTX_CNTL2">
2147 <bitfield name="POLYMODE_FRONT_PTYPE" low="0" high="2" type="adreno_pa_su_sc_draw"/>
2148 <bitfield name="POLYMODE_BACK_PTYPE" low="3" high="5" type="adreno_pa_su_sc_draw"/>
2149 <bitfield name="POLYMODE_ENABLE" pos="6" type="boolean"/>
2150 </reg32>
2151 <reg32 offset="0x21c6" name="PC_RESTART_INDEX"/>
2152 <reg32 offset="0x21e5" name="PC_GS_PARAM">
2153 <bitfield name="MAX_VERTICES" low="0" high="9" type="uint"/><!-- +1, i.e. max is 1024 -->
2154 <bitfield name="INVOCATIONS" low="11" high="15" type="uint"/><!-- +1, i.e. max is 32 -->
2155 <bitfield name="PRIMTYPE" low="23" high="24" type="adreno_pa_su_sc_draw"/>
2156 <bitfield name="LAYER" pos="31" type="boolean"/>
2157 </reg32>
2158 <reg32 offset="0x21e7" name="PC_HS_PARAM">
2159 <bitfield name="VERTICES_OUT" low="0" high="5" type="uint"/>
2160 <bitfield name="SPACING" low="21" high="22" type="a4xx_tess_spacing"/>
2161 <bitfield name="CW" pos="23" type="boolean"/>
2162 <bitfield name="CONNECTED" pos="24" type="boolean"/>
2163 </reg32>
2164
2165 <!-- VBIF registers -->
2166 <reg32 offset="0x3000" name="VBIF_VERSION"/>
2167 <reg32 offset="0x3001" name="VBIF_CLKON">
2168 <bitfield name="FORCE_ON_TESTBUS" pos="0" type="boolean"/>
2169 </reg32>
2170 <reg32 offset="0x301c" name="VBIF_ABIT_SORT"/>
2171 <reg32 offset="0x301d" name="VBIF_ABIT_SORT_CONF"/>
2172 <reg32 offset="0x302a" name="VBIF_GATE_OFF_WRREQ_EN"/>
2173 <reg32 offset="0x302c" name="VBIF_IN_RD_LIM_CONF0"/>
2174 <reg32 offset="0x302d" name="VBIF_IN_RD_LIM_CONF1"/>
2175 <reg32 offset="0x3030" name="VBIF_IN_WR_LIM_CONF0"/>
2176 <reg32 offset="0x3031" name="VBIF_IN_WR_LIM_CONF1"/>
2177 <reg32 offset="0x3049" name="VBIF_ROUND_ROBIN_QOS_ARB"/>
2178 <reg32 offset="0x30c0" name="VBIF_PERF_CNT_EN0"/>
2179 <reg32 offset="0x30c1" name="VBIF_PERF_CNT_EN1"/>
2180 <reg32 offset="0x30c2" name="VBIF_PERF_CNT_EN2"/>
2181 <reg32 offset="0x30c3" name="VBIF_PERF_CNT_EN3"/>
2182 <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0" type="a4xx_vbif_perfcounter_select"/>
2183 <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1" type="a4xx_vbif_perfcounter_select"/>
2184 <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2" type="a4xx_vbif_perfcounter_select"/>
2185 <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3" type="a4xx_vbif_perfcounter_select"/>
2186 <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
2187 <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
2188 <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
2189 <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
2190 <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
2191 <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
2192 <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
2193 <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
2194 <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
2195 <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
2196 <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
2197
2198 <!--
2199 Unknown registers:
2200 (mostly related to DX11 features not used yet, I guess?)
2201 -->
2202
2203 <!-- always 00000006: -->
2204 <reg32 offset="0x0cc5" name="UNKNOWN_0CC5"/>
2205
2206 <!-- always 00000000: -->
2207 <reg32 offset="0x0cc6" name="UNKNOWN_0CC6"/>
2208
2209 <!-- always 00000001: -->
2210 <reg32 offset="0x0d01" name="UNKNOWN_0D01"/>
2211
2212 <!-- always 00000000: -->
2213 <reg32 offset="0x0e42" name="UNKNOWN_0E42"/>
2214
2215 <!-- always 00040000: -->
2216 <reg32 offset="0x0ec2" name="UNKNOWN_0EC2"/>
2217
2218 <!-- always 00000000: -->
2219 <reg32 offset="0x2001" name="UNKNOWN_2001"/>
2220
2221 <!-- always 00000000: -->
2222 <reg32 offset="0x209b" name="UNKNOWN_209B"/>
2223
2224 <!-- always 00000000: -->
2225 <reg32 offset="0x20ef" name="UNKNOWN_20EF"/>
2226
2227 <!-- always 00000000: -->
2228 <reg32 offset="0x2152" name="UNKNOWN_2152"/>
2229
2230 <!-- always 00000000: -->
2231 <reg32 offset="0x2153" name="UNKNOWN_2153"/>
2232
2233 <!-- always 00000000: -->
2234 <reg32 offset="0x2154" name="UNKNOWN_2154"/>
2235
2236 <!-- always 00000000: -->
2237 <reg32 offset="0x2155" name="UNKNOWN_2155"/>
2238
2239 <!-- always 00000000: -->
2240 <reg32 offset="0x2156" name="UNKNOWN_2156"/>
2241
2242 <!-- always 00000000: -->
2243 <reg32 offset="0x2157" name="UNKNOWN_2157"/>
2244
2245 <!-- always 0000000b: -->
2246 <reg32 offset="0x21c3" name="UNKNOWN_21C3"/>
2247
2248 <!-- always 00000001: -->
2249 <reg32 offset="0x21e6" name="UNKNOWN_21E6"/>
2250
2251 <!-- always 00000000: -->
2252 <reg32 offset="0x2209" name="UNKNOWN_2209"/>
2253
2254 <!-- always 00000000: -->
2255 <reg32 offset="0x22d7" name="UNKNOWN_22D7"/>
2256
2257 <!-- always 00fcfc00: -->
2258 <reg32 offset="0x2352" name="UNKNOWN_2352"/>
2259
2260 </domain>
2261
2262
2263 <domain name="A4XX_TEX_SAMP" width="32">
2264 <doc>Texture sampler dwords</doc>
2265 <enum name="a4xx_tex_filter">
2266 <value name="A4XX_TEX_NEAREST" value="0"/>
2267 <value name="A4XX_TEX_LINEAR" value="1"/>
2268 <value name="A4XX_TEX_ANISO" value="2"/>
2269 </enum>
2270 <enum name="a4xx_tex_clamp">
2271 <value name="A4XX_TEX_REPEAT" value="0"/>
2272 <value name="A4XX_TEX_CLAMP_TO_EDGE" value="1"/>
2273 <value name="A4XX_TEX_MIRROR_REPEAT" value="2"/>
2274 <value name="A4XX_TEX_CLAMP_TO_BORDER" value="3"/>
2275 <value name="A4XX_TEX_MIRROR_CLAMP" value="4"/>
2276 </enum>
2277 <enum name="a4xx_tex_aniso">
2278 <value name="A4XX_TEX_ANISO_1" value="0"/>
2279 <value name="A4XX_TEX_ANISO_2" value="1"/>
2280 <value name="A4XX_TEX_ANISO_4" value="2"/>
2281 <value name="A4XX_TEX_ANISO_8" value="3"/>
2282 <value name="A4XX_TEX_ANISO_16" value="4"/>
2283 </enum>
2284 <reg32 offset="0" name="0">
2285 <bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>
2286 <bitfield name="XY_MAG" low="1" high="2" type="a4xx_tex_filter"/>
2287 <bitfield name="XY_MIN" low="3" high="4" type="a4xx_tex_filter"/>
2288 <bitfield name="WRAP_S" low="5" high="7" type="a4xx_tex_clamp"/>
2289 <bitfield name="WRAP_T" low="8" high="10" type="a4xx_tex_clamp"/>
2290 <bitfield name="WRAP_R" low="11" high="13" type="a4xx_tex_clamp"/>
2291 <bitfield name="ANISO" low="14" high="16" type="a4xx_tex_aniso"/>
2292 <bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real -->
2293 </reg32>
2294 <reg32 offset="1" name="1">
2295 <bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/>
2296 <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/>
2297 <bitfield name="UNNORM_COORDS" pos="5" type="boolean"/>
2298 <bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/>
2299 <bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/>
2300 <bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/>
2301 </reg32>
2302 </domain>
2303
2304 <domain name="A4XX_TEX_CONST" width="32">
2305 <doc>Texture constant dwords</doc>
2306 <enum name="a4xx_tex_swiz">
2307 <!-- same as a2xx? -->
2308 <value name="A4XX_TEX_X" value="0"/>
2309 <value name="A4XX_TEX_Y" value="1"/>
2310 <value name="A4XX_TEX_Z" value="2"/>
2311 <value name="A4XX_TEX_W" value="3"/>
2312 <value name="A4XX_TEX_ZERO" value="4"/>
2313 <value name="A4XX_TEX_ONE" value="5"/>
2314 </enum>
2315 <enum name="a4xx_tex_type">
2316 <value name="A4XX_TEX_1D" value="0"/>
2317 <value name="A4XX_TEX_2D" value="1"/>
2318 <value name="A4XX_TEX_CUBE" value="2"/>
2319 <value name="A4XX_TEX_3D" value="3"/>
2320 </enum>
2321 <reg32 offset="0" name="0">
2322 <bitfield name="TILED" pos="0" type="boolean"/>
2323 <bitfield name="SRGB" pos="2" type="boolean"/>
2324 <bitfield name="SWIZ_X" low="4" high="6" type="a4xx_tex_swiz"/>
2325 <bitfield name="SWIZ_Y" low="7" high="9" type="a4xx_tex_swiz"/>
2326 <bitfield name="SWIZ_Z" low="10" high="12" type="a4xx_tex_swiz"/>
2327 <bitfield name="SWIZ_W" low="13" high="15" type="a4xx_tex_swiz"/>
2328 <bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
2329 <bitfield name="FMT" low="22" high="28" type="a4xx_tex_fmt"/>
2330 <bitfield name="TYPE" low="29" high="30" type="a4xx_tex_type"/>
2331 </reg32>
2332 <reg32 offset="1" name="1">
2333 <bitfield name="HEIGHT" low="0" high="14" type="uint"/>
2334 <bitfield name="WIDTH" low="15" high="29" type="uint"/>
2335 </reg32>
2336 <reg32 offset="2" name="2">
2337 <!-- minimum pitch (for mipmap levels): log2(pitchalign / 32) -->
2338 <bitfield name="PITCHALIGN" low="0" high="3" type="uint"/>
2339 <doc>Pitch in bytes (so actually stride)</doc>
2340 <bitfield name="PITCH" low="9" high="29" type="uint"/>
2341 <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
2342 </reg32>
2343 <reg32 offset="3" name="3">
2344 <bitfield name="LAYERSZ" low="0" high="13" shr="12" type="uint"/>
2345 <bitfield name="DEPTH" low="18" high="30" type="uint"/>
2346 </reg32>
2347 <reg32 offset="4" name="4">
2348 <!--
2349 like a3xx we seem to have two LAYERSZ's.. although this one
2350 seems too small to be useful, and when it overflows blob just
2351 sets it to zero..
2352 -->
2353 <bitfield name="LAYERSZ" low="0" high="3" shr="12" type="uint"/>
2354 <bitfield name="BASE" low="5" high="31" shr="5"/>
2355 </reg32>
2356 <reg32 offset="5" name="5"/>
2357 <reg32 offset="6" name="6"/>
2358 <reg32 offset="7" name="7"/>
2359 </domain>
2360
2361 <domain name="A4XX_SSBO_0" width="32">
2362 <reg32 offset="0" name="0">
2363 <bitfield name="BASE" low="5" high="31" shr="5"/>
2364 </reg32>
2365 <reg32 offset="1" name="1">
2366 <doc>Pitch in bytes (so actually stride)</doc>
2367 <bitfield name="PITCH" low="0" high="21" type="uint"/>
2368 </reg32>
2369 <reg32 offset="2" name="2">
2370 <bitfield name="ARRAY_PITCH" low="12" high="25" shr="12" type="uint"/>
2371 </reg32>
2372 <reg32 offset="3" name="3">
2373 <!-- bytes per pixel: -->
2374 <bitfield name="CPP" low="0" high="5" type="uint"/>
2375 </reg32>
2376 </domain>
2377
2378 <domain name="A4XX_SSBO_1" width="32">
2379 <reg32 offset="0" name="0">
2380 <bitfield name="CPP" low="0" high="4" type="uint"/>
2381 <bitfield name="FMT" low="8" high="15" type="a4xx_color_fmt"/>
2382 <bitfield name="WIDTH" low="16" high="31" type="uint"/>
2383 </reg32>
2384 <reg32 offset="1" name="1">
2385 <bitfield name="HEIGHT" low="0" high="15" type="uint"/>
2386 <bitfield name="DEPTH" low="16" high="31" type="uint"/>
2387 </reg32>
2388 </domain>
2389
2390 </database>