src/freedreno/registers/a6xx.xml

   1 <?xml version="1.0" encoding="UTF-8"?>
   2 <database xmlns="http://nouveau.freedesktop.org/"
   3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
   4 xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
   5 <import file="freedreno_copyright.xml"/>
   6 <import file="adreno/adreno_common.xml"/>
   7 <import file="adreno/adreno_pm4.xml"/>
   8
   9 <!-- these might be same as a5xx -->
  10 <enum name="a6xx_color_fmt">
  11         <value value="0x02" name="RB6_A8_UNORM"/>
  12         <value value="0x03" name="RB6_R8_UNORM"/>
  13         <value value="0x04" name="RB6_R8_SNORM"/>
  14         <value value="0x05" name="RB6_R8_UINT"/>
  15         <value value="0x06" name="RB6_R8_SINT"/>
  16         <value value="0x08" name="RB6_R4G4B4A4_UNORM"/>
  17         <value value="0x0a" name="RB6_R5G5B5A1_UNORM"/>
  18         <value value="0x0e" name="RB6_R5G6B5_UNORM"/>
  19         <value value="0x0f" name="RB6_R8G8_UNORM"/>
  20         <value value="0x10" name="RB6_R8G8_SNORM"/>
  21         <value value="0x11" name="RB6_R8G8_UINT"/>
  22         <value value="0x12" name="RB6_R8G8_SINT"/>
  23         <value value="0x15" name="RB6_R16_UNORM"/>
  24         <value value="0x16" name="RB6_R16_SNORM"/>
  25         <value value="0x17" name="RB6_R16_FLOAT"/>
  26         <value value="0x18" name="RB6_R16_UINT"/>
  27         <value value="0x19" name="RB6_R16_SINT"/>
  28         <value value="0x30" name="RB6_R8G8B8A8_UNORM"/>
  29         <value value="0x31" name="RB6_R8G8B8_UNORM"/>
  30         <value value="0x32" name="RB6_R8G8B8A8_SNORM"/>
  31         <value value="0x33" name="RB6_R8G8B8A8_UINT"/>
  32         <value value="0x34" name="RB6_R8G8B8A8_SINT"/>
  33         <value value="0x37" name="RB6_R10G10B10A2_UNORM"/>  <!-- GL_RGB10_A2 -->
  34         <value value="0x3a" name="RB6_R10G10B10A2_UINT"/>   <!-- GL_RGB10_A2UI -->
  35         <value value="0x42" name="RB6_R11G11B10_FLOAT"/>    <!-- GL_R11F_G11F_B10F -->
  36         <value value="0x43" name="RB6_R16G16_UNORM"/>
  37         <value value="0x44" name="RB6_R16G16_SNORM"/>
  38         <value value="0x45" name="RB6_R16G16_FLOAT"/>
  39         <value value="0x46" name="RB6_R16G16_UINT"/>
  40         <value value="0x47" name="RB6_R16G16_SINT"/>
  41         <value value="0x4a" name="RB6_R32_FLOAT"/>
  42         <value value="0x4b" name="RB6_R32_UINT"/>
  43         <value value="0x4c" name="RB6_R32_SINT"/>
  44         <value value="0x60" name="RB6_R16G16B16A16_UNORM"/>
  45         <value value="0x61" name="RB6_R16G16B16A16_SNORM"/>
  46         <value value="0x62" name="RB6_R16G16B16A16_FLOAT"/>
  47         <value value="0x63" name="RB6_R16G16B16A16_UINT"/>
  48         <value value="0x64" name="RB6_R16G16B16A16_SINT"/>
  49         <value value="0x67" name="RB6_R32G32_FLOAT"/>
  50         <value value="0x68" name="RB6_R32G32_UINT"/>
  51         <value value="0x69" name="RB6_R32G32_SINT"/>
  52         <value value="0x82" name="RB6_R32G32B32A32_FLOAT"/>
  53         <value value="0x83" name="RB6_R32G32B32A32_UINT"/>
  54         <value value="0x84" name="RB6_R32G32B32A32_SINT"/>
  55         <value value="0x91" name="RB6_Z24_UNORM_S8_UINT"/>
  56         <value value="0xa0" name="RB6_X8Z24_UNORM"/>
  57 </enum>
  58
  59 <!-- these might be same as a5xx -->
  60 <enum name="a6xx_tile_mode">
  61         <value name="TILE6_LINEAR" value="0"/>
  62         <value name="TILE6_2" value="2"/>
  63         <value name="TILE6_3" value="3"/>
  64 </enum>
  65
  66 <!-- these might be same as a5xx -->
  67 <enum name="a6xx_vtx_fmt" prefix="chipset">
  68         <value value="0x03" name="VFMT6_8_UNORM"/>
  69         <value value="0x04" name="VFMT6_8_SNORM"/>
  70         <value value="0x05" name="VFMT6_8_UINT"/>
  71         <value value="0x06" name="VFMT6_8_SINT"/>
  72
  73         <value value="0x0f" name="VFMT6_8_8_UNORM"/>
  74         <value value="0x10" name="VFMT6_8_8_SNORM"/>
  75         <value value="0x11" name="VFMT6_8_8_UINT"/>
  76         <value value="0x12" name="VFMT6_8_8_SINT"/>
  77
  78         <value value="0x15" name="VFMT6_16_UNORM"/>
  79         <value value="0x16" name="VFMT6_16_SNORM"/>
  80         <value value="0x17" name="VFMT6_16_FLOAT"/>
  81         <value value="0x18" name="VFMT6_16_UINT"/>
  82         <value value="0x19" name="VFMT6_16_SINT"/>
  83
  84         <value value="0x21" name="VFMT6_8_8_8_UNORM"/>
  85         <value value="0x22" name="VFMT6_8_8_8_SNORM"/>
  86         <value value="0x23" name="VFMT6_8_8_8_UINT"/>
  87         <value value="0x24" name="VFMT6_8_8_8_SINT"/>
  88
  89         <value value="0x30" name="VFMT6_8_8_8_8_UNORM"/>
  90         <value value="0x32" name="VFMT6_8_8_8_8_SNORM"/>
  91         <value value="0x33" name="VFMT6_8_8_8_8_UINT"/>
  92         <value value="0x34" name="VFMT6_8_8_8_8_SINT"/>
  93
  94         <value value="0x36" name="VFMT6_10_10_10_2_UNORM"/>
  95         <value value="0x39" name="VFMT6_10_10_10_2_SNORM"/>
  96         <value value="0x3a" name="VFMT6_10_10_10_2_UINT"/>
  97         <value value="0x3b" name="VFMT6_10_10_10_2_SINT"/>
  98
  99         <value value="0x42" name="VFMT6_11_11_10_FLOAT"/>
 100
 101         <value value="0x43" name="VFMT6_16_16_UNORM"/>
 102         <value value="0x44" name="VFMT6_16_16_SNORM"/>
 103         <value value="0x45" name="VFMT6_16_16_FLOAT"/>
 104         <value value="0x46" name="VFMT6_16_16_UINT"/>
 105         <value value="0x47" name="VFMT6_16_16_SINT"/>
 106
 107         <value value="0x48" name="VFMT6_32_UNORM"/>
 108         <value value="0x49" name="VFMT6_32_SNORM"/>
 109         <value value="0x4a" name="VFMT6_32_FLOAT"/>
 110         <value value="0x4b" name="VFMT6_32_UINT"/>
 111         <value value="0x4c" name="VFMT6_32_SINT"/>
 112         <value value="0x4d" name="VFMT6_32_FIXED"/>
 113
 114         <value value="0x58" name="VFMT6_16_16_16_UNORM"/>
 115         <value value="0x59" name="VFMT6_16_16_16_SNORM"/>
 116         <value value="0x5a" name="VFMT6_16_16_16_FLOAT"/>
 117         <value value="0x5b" name="VFMT6_16_16_16_UINT"/>
 118         <value value="0x5c" name="VFMT6_16_16_16_SINT"/>
 119
 120         <value value="0x60" name="VFMT6_16_16_16_16_UNORM"/>
 121         <value value="0x61" name="VFMT6_16_16_16_16_SNORM"/>
 122         <value value="0x62" name="VFMT6_16_16_16_16_FLOAT"/>
 123         <value value="0x63" name="VFMT6_16_16_16_16_UINT"/>
 124         <value value="0x64" name="VFMT6_16_16_16_16_SINT"/>
 125
 126         <value value="0x65" name="VFMT6_32_32_UNORM"/>
 127         <value value="0x66" name="VFMT6_32_32_SNORM"/>
 128         <value value="0x67" name="VFMT6_32_32_FLOAT"/>
 129         <value value="0x68" name="VFMT6_32_32_UINT"/>
 130         <value value="0x69" name="VFMT6_32_32_SINT"/>
 131         <value value="0x6a" name="VFMT6_32_32_FIXED"/>
 132
 133         <value value="0x70" name="VFMT6_32_32_32_UNORM"/>
 134         <value value="0x71" name="VFMT6_32_32_32_SNORM"/>
 135         <value value="0x72" name="VFMT6_32_32_32_UINT"/>
 136         <value value="0x73" name="VFMT6_32_32_32_SINT"/>
 137         <value value="0x74" name="VFMT6_32_32_32_FLOAT"/>
 138         <value value="0x75" name="VFMT6_32_32_32_FIXED"/>
 139
 140         <value value="0x80" name="VFMT6_32_32_32_32_UNORM"/>
 141         <value value="0x81" name="VFMT6_32_32_32_32_SNORM"/>
 142         <value value="0x82" name="VFMT6_32_32_32_32_FLOAT"/>
 143         <value value="0x83" name="VFMT6_32_32_32_32_UINT"/>
 144         <value value="0x84" name="VFMT6_32_32_32_32_SINT"/>
 145         <value value="0x85" name="VFMT6_32_32_32_32_FIXED"/>
 146 </enum>
 147
 148 <enum name="a6xx_tex_fmt">
 149         <value value="0x02" name="TFMT6_A8_UNORM"/>
 150         <value value="0x03" name="TFMT6_8_UNORM"/>
 151         <value value="0x04" name="TFMT6_8_SNORM"/>
 152         <value value="0x05" name="TFMT6_8_UINT"/>
 153         <value value="0x06" name="TFMT6_8_SINT"/>
 154         <value value="0x08" name="TFMT6_4_4_4_4_UNORM"/>
 155         <value value="0x0a" name="TFMT6_5_5_5_1_UNORM"/>
 156         <value value="0x0e" name="TFMT6_5_6_5_UNORM"/>
 157         <value value="0x0f" name="TFMT6_8_8_UNORM"/>
 158         <value value="0x10" name="TFMT6_8_8_SNORM"/>
 159         <value value="0x11" name="TFMT6_8_8_UINT"/>
 160         <value value="0x12" name="TFMT6_8_8_SINT"/>
 161         <value value="0x13" name="TFMT6_L8_A8_UNORM"/>
 162         <value value="0x15" name="TFMT6_16_UNORM"/>
 163         <value value="0x16" name="TFMT6_16_SNORM"/>
 164         <value value="0x17" name="TFMT6_16_FLOAT"/>
 165         <value value="0x18" name="TFMT6_16_UINT"/>
 166         <value value="0x19" name="TFMT6_16_SINT"/>
 167         <value value="0x30" name="TFMT6_8_8_8_8_UNORM"/>
 168         <value value="0x31" name="TFMT6_8_8_8_UNORM"/>
 169         <value value="0x32" name="TFMT6_8_8_8_8_SNORM"/>
 170         <value value="0x33" name="TFMT6_8_8_8_8_UINT"/>
 171         <value value="0x34" name="TFMT6_8_8_8_8_SINT"/>
 172         <value value="0x35" name="TFMT6_9_9_9_E5_FLOAT"/>
 173         <value value="0x36" name="TFMT6_10_10_10_2_UNORM"/>
 174         <value value="0x3a" name="TFMT6_10_10_10_2_UINT"/>
 175         <value value="0x42" name="TFMT6_11_11_10_FLOAT"/>
 176         <value value="0x43" name="TFMT6_16_16_UNORM"/>
 177         <value value="0x44" name="TFMT6_16_16_SNORM"/>
 178         <value value="0x45" name="TFMT6_16_16_FLOAT"/>
 179         <value value="0x46" name="TFMT6_16_16_UINT"/>
 180         <value value="0x47" name="TFMT6_16_16_SINT"/>
 181         <value value="0x4a" name="TFMT6_32_FLOAT"/>
 182         <value value="0x4b" name="TFMT6_32_UINT"/>
 183         <value value="0x4c" name="TFMT6_32_SINT"/>
 184         <value value="0x60" name="TFMT6_16_16_16_16_UNORM"/>
 185         <value value="0x61" name="TFMT6_16_16_16_16_SNORM"/>
 186         <value value="0x62" name="TFMT6_16_16_16_16_FLOAT"/>
 187         <value value="0x63" name="TFMT6_16_16_16_16_UINT"/>
 188         <value value="0x64" name="TFMT6_16_16_16_16_SINT"/>
 189         <value value="0x67" name="TFMT6_32_32_FLOAT"/>
 190         <value value="0x68" name="TFMT6_32_32_UINT"/>
 191         <value value="0x69" name="TFMT6_32_32_SINT"/>
 192         <value value="0x72" name="TFMT6_32_32_32_UINT"/>
 193         <value value="0x73" name="TFMT6_32_32_32_SINT"/>
 194         <value value="0x74" name="TFMT6_32_32_32_FLOAT"/>
 195         <value value="0x82" name="TFMT6_32_32_32_32_FLOAT"/>
 196         <value value="0x83" name="TFMT6_32_32_32_32_UINT"/>
 197         <value value="0x84" name="TFMT6_32_32_32_32_SINT"/>
 198         <value value="0x91" name="TFMT6_Z24_UNORM_S8_UINT"/>
 199         <value value="0xa0" name="TFMT6_X8Z24_UNORM"/>
 200
 201         <value value="0xab" name="TFMT6_ETC2_RG11_UNORM"/>
 202         <value value="0xac" name="TFMT6_ETC2_RG11_SNORM"/>
 203         <value value="0xad" name="TFMT6_ETC2_R11_UNORM"/>
 204         <value value="0xae" name="TFMT6_ETC2_R11_SNORM"/>
 205         <value value="0xaf" name="TFMT6_ETC1"/>
 206         <value value="0xb0" name="TFMT6_ETC2_RGB8"/>
 207         <value value="0xb1" name="TFMT6_ETC2_RGBA8"/>
 208         <value value="0xb2" name="TFMT6_ETC2_RGB8A1"/>
 209         <value value="0xb3" name="TFMT6_DXT1"/>
 210         <value value="0xb4" name="TFMT6_DXT3"/>
 211         <value value="0xb5" name="TFMT6_DXT5"/>
 212         <value value="0xb7" name="TFMT6_RGTC1_UNORM"/>
 213         <value value="0xb8" name="TFMT6_RGTC1_SNORM"/>
 214         <value value="0xbb" name="TFMT6_RGTC2_UNORM"/>
 215         <value value="0xbc" name="TFMT6_RGTC2_SNORM"/>
 216         <value value="0xbe" name="TFMT6_BPTC_UFLOAT"/>
 217         <value value="0xbf" name="TFMT6_BPTC_FLOAT"/>
 218         <value value="0xc0" name="TFMT6_BPTC"/>
 219         <value value="0xc1" name="TFMT6_ASTC_4x4"/>
 220         <value value="0xc2" name="TFMT6_ASTC_5x4"/>
 221         <value value="0xc3" name="TFMT6_ASTC_5x5"/>
 222         <value value="0xc4" name="TFMT6_ASTC_6x5"/>
 223         <value value="0xc5" name="TFMT6_ASTC_6x6"/>
 224         <value value="0xc6" name="TFMT6_ASTC_8x5"/>
 225         <value value="0xc7" name="TFMT6_ASTC_8x6"/>
 226         <value value="0xc8" name="TFMT6_ASTC_8x8"/>
 227         <value value="0xc9" name="TFMT6_ASTC_10x5"/>
 228         <value value="0xca" name="TFMT6_ASTC_10x6"/>
 229         <value value="0xcb" name="TFMT6_ASTC_10x8"/>
 230         <value value="0xcc" name="TFMT6_ASTC_10x10"/>
 231         <value value="0xcd" name="TFMT6_ASTC_12x10"/>
 232         <value value="0xce" name="TFMT6_ASTC_12x12"/>
 233 </enum>
 234
 235 <enum name="a6xx_tex_fetchsize">
 236         <value name="TFETCH6_1_BYTE"  value="0"/>
 237         <value name="TFETCH6_2_BYTE"  value="1"/>
 238         <value name="TFETCH6_4_BYTE"  value="2"/>
 239         <value name="TFETCH6_8_BYTE"  value="3"/>
 240         <value name="TFETCH6_16_BYTE" value="4"/>
 241 </enum>
 242
 243 <!-- probably same as a5xx -->
 244 <enum name="a6xx_depth_format">
 245         <value name="DEPTH6_NONE" value="0"/>
 246         <value name="DEPTH6_16" value="1"/>
 247         <value name="DEPTH6_24_8" value="2"/>
 248         <value name="DEPTH6_32" value="4"/>
 249 </enum>
 250
 251 <bitset name="a6x_cp_protect" inline="yes">
 252         <bitfield name="BASE_ADDR" low="0" high="17"/>
 253         <bitfield name="MASK_LEN" low="18" high="30"/>
 254         <bitfield name="READ" pos="31"/>
 255 </bitset>
 256
 257 <enum name="a6xx_shader_id">
 258         <value value="0x9" name="A6XX_TP0_TMO_DATA"/>
 259         <value value="0xa" name="A6XX_TP0_SMO_DATA"/>
 260         <value value="0xb" name="A6XX_TP0_MIPMAP_BASE_DATA"/>
 261         <value value="0x19" name="A6XX_TP1_TMO_DATA"/>
 262         <value value="0x1a" name="A6XX_TP1_SMO_DATA"/>
 263         <value value="0x1b" name="A6XX_TP1_MIPMAP_BASE_DATA"/>
 264         <value value="0x29" name="A6XX_SP_INST_DATA"/>
 265         <value value="0x2a" name="A6XX_SP_LB_0_DATA"/>
 266         <value value="0x2b" name="A6XX_SP_LB_1_DATA"/>
 267         <value value="0x2c" name="A6XX_SP_LB_2_DATA"/>
 268         <value value="0x2d" name="A6XX_SP_LB_3_DATA"/>
 269         <value value="0x2e" name="A6XX_SP_LB_4_DATA"/>
 270         <value value="0x2f" name="A6XX_SP_LB_5_DATA"/>
 271         <value value="0x30" name="A6XX_SP_CB_BINDLESS_DATA"/>
 272         <value value="0x31" name="A6XX_SP_CB_LEGACY_DATA"/>
 273         <value value="0x32" name="A6XX_SP_UAV_DATA"/>
 274         <value value="0x33" name="A6XX_SP_INST_TAG"/>
 275         <value value="0x34" name="A6XX_SP_CB_BINDLESS_TAG"/>
 276         <value value="0x35" name="A6XX_SP_TMO_UMO_TAG"/>
 277         <value value="0x36" name="A6XX_SP_SMO_TAG"/>
 278         <value value="0x37" name="A6XX_SP_STATE_DATA"/>
 279         <value value="0x49" name="A6XX_HLSQ_CHUNK_CVS_RAM"/>
 280         <value value="0x4a" name="A6XX_HLSQ_CHUNK_CPS_RAM"/>
 281         <value value="0x4b" name="A6XX_HLSQ_CHUNK_CVS_RAM_TAG"/>
 282         <value value="0x4c" name="A6XX_HLSQ_CHUNK_CPS_RAM_TAG"/>
 283         <value value="0x4d" name="A6XX_HLSQ_ICB_CVS_CB_BASE_TAG"/>
 284         <value value="0x4e" name="A6XX_HLSQ_ICB_CPS_CB_BASE_TAG"/>
 285         <value value="0x50" name="A6XX_HLSQ_CVS_MISC_RAM"/>
 286         <value value="0x51" name="A6XX_HLSQ_CPS_MISC_RAM"/>
 287         <value value="0x52" name="A6XX_HLSQ_INST_RAM"/>
 288         <value value="0x53" name="A6XX_HLSQ_GFX_CVS_CONST_RAM"/>
 289         <value value="0x54" name="A6XX_HLSQ_GFX_CPS_CONST_RAM"/>
 290         <value value="0x55" name="A6XX_HLSQ_CVS_MISC_RAM_TAG"/>
 291         <value value="0x56" name="A6XX_HLSQ_CPS_MISC_RAM_TAG"/>
 292         <value value="0x57" name="A6XX_HLSQ_INST_RAM_TAG"/>
 293         <value value="0x58" name="A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/>
 294         <value value="0x59" name="A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/>
 295         <value value="0x5a" name="A6XX_HLSQ_PWR_REST_RAM"/>
 296         <value value="0x5b" name="A6XX_HLSQ_PWR_REST_TAG"/>
 297         <value value="0x60" name="A6XX_HLSQ_DATAPATH_META"/>
 298         <value value="0x61" name="A6XX_HLSQ_FRONTEND_META"/>
 299         <value value="0x62" name="A6XX_HLSQ_INDIRECT_META"/>
 300         <value value="0x63" name="A6XX_HLSQ_BACKEND_META"/>
 301 </enum>
 302
 303 <enum name="a6xx_debugbus_id">
 304         <value value="0x1" name="A6XX_DBGBUS_CP"/>
 305         <value value="0x2" name="A6XX_DBGBUS_RBBM"/>
 306         <value value="0x3" name="A6XX_DBGBUS_VBIF"/>
 307         <value value="0x4" name="A6XX_DBGBUS_HLSQ"/>
 308         <value value="0x5" name="A6XX_DBGBUS_UCHE"/>
 309         <value value="0x6" name="A6XX_DBGBUS_DPM"/>
 310         <value value="0x7" name="A6XX_DBGBUS_TESS"/>
 311         <value value="0x8" name="A6XX_DBGBUS_PC"/>
 312         <value value="0x9" name="A6XX_DBGBUS_VFDP"/>
 313         <value value="0xa" name="A6XX_DBGBUS_VPC"/>
 314         <value value="0xb" name="A6XX_DBGBUS_TSE"/>
 315         <value value="0xc" name="A6XX_DBGBUS_RAS"/>
 316         <value value="0xd" name="A6XX_DBGBUS_VSC"/>
 317         <value value="0xe" name="A6XX_DBGBUS_COM"/>
 318         <value value="0x10" name="A6XX_DBGBUS_LRZ"/>
 319         <value value="0x11" name="A6XX_DBGBUS_A2D"/>
 320         <value value="0x12" name="A6XX_DBGBUS_CCUFCHE"/>
 321         <value value="0x13" name="A6XX_DBGBUS_GMU_CX"/>
 322         <value value="0x14" name="A6XX_DBGBUS_RBP"/>
 323         <value value="0x15" name="A6XX_DBGBUS_DCS"/>
 324         <value value="0x16" name="A6XX_DBGBUS_DBGC"/>
 325         <value value="0x17" name="A6XX_DBGBUS_CX"/>
 326         <value value="0x18" name="A6XX_DBGBUS_GMU_GX"/>
 327         <value value="0x19" name="A6XX_DBGBUS_TPFCHE"/>
 328         <value value="0x1a" name="A6XX_DBGBUS_GBIF_GX"/>
 329         <value value="0x1d" name="A6XX_DBGBUS_GPC"/>
 330         <value value="0x1e" name="A6XX_DBGBUS_LARC"/>
 331         <value value="0x1f" name="A6XX_DBGBUS_HLSQ_SPTP"/>
 332         <value value="0x20" name="A6XX_DBGBUS_RB_0"/>
 333         <value value="0x21" name="A6XX_DBGBUS_RB_1"/>
 334         <value value="0x24" name="A6XX_DBGBUS_UCHE_WRAPPER"/>
 335         <value value="0x28" name="A6XX_DBGBUS_CCU_0"/>
 336         <value value="0x29" name="A6XX_DBGBUS_CCU_1"/>
 337         <value value="0x38" name="A6XX_DBGBUS_VFD_0"/>
 338         <value value="0x39" name="A6XX_DBGBUS_VFD_1"/>
 339         <value value="0x3a" name="A6XX_DBGBUS_VFD_2"/>
 340         <value value="0x3b" name="A6XX_DBGBUS_VFD_3"/>
 341         <value value="0x40" name="A6XX_DBGBUS_SP_0"/>
 342         <value value="0x41" name="A6XX_DBGBUS_SP_1"/>
 343         <value value="0x48" name="A6XX_DBGBUS_TPL1_0"/>
 344         <value value="0x49" name="A6XX_DBGBUS_TPL1_1"/>
 345         <value value="0x4a" name="A6XX_DBGBUS_TPL1_2"/>
 346         <value value="0x4b" name="A6XX_DBGBUS_TPL1_3"/>
 347 </enum>
 348
 349 <enum name="a6xx_cp_perfcounter_select">
 350         <value value="0" name="PERF_CP_ALWAYS_COUNT"/>
 351         <value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/>
 352         <value value="2" name="PERF_CP_BUSY_CYCLES"/>
 353         <value value="3" name="PERF_CP_NUM_PREEMPTIONS"/>
 354         <value value="4" name="PERF_CP_PREEMPTION_REACTION_DELAY"/>
 355         <value value="5" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/>
 356         <value value="6" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/>
 357         <value value="7" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/>
 358         <value value="8" name="PERF_CP_PREDICATED_DRAWS_KILLED"/>
 359         <value value="9" name="PERF_CP_MODE_SWITCH"/>
 360         <value value="10" name="PERF_CP_ZPASS_DONE"/>
 361         <value value="11" name="PERF_CP_CONTEXT_DONE"/>
 362         <value value="12" name="PERF_CP_CACHE_FLUSH"/>
 363         <value value="13" name="PERF_CP_LONG_PREEMPTIONS"/>
 364         <value value="14" name="PERF_CP_SQE_I_CACHE_STARVE"/>
 365         <value value="15" name="PERF_CP_SQE_IDLE"/>
 366         <value value="16" name="PERF_CP_SQE_PM4_STARVE_RB_IB"/>
 367         <value value="17" name="PERF_CP_SQE_PM4_STARVE_SDS"/>
 368         <value value="18" name="PERF_CP_SQE_MRB_STARVE"/>
 369         <value value="19" name="PERF_CP_SQE_RRB_STARVE"/>
 370         <value value="20" name="PERF_CP_SQE_VSD_STARVE"/>
 371         <value value="21" name="PERF_CP_VSD_DECODE_STARVE"/>
 372         <value value="22" name="PERF_CP_SQE_PIPE_OUT_STALL"/>
 373         <value value="23" name="PERF_CP_SQE_SYNC_STALL"/>
 374         <value value="24" name="PERF_CP_SQE_PM4_WFI_STALL"/>
 375         <value value="25" name="PERF_CP_SQE_SYS_WFI_STALL"/>
 376         <value value="26" name="PERF_CP_SQE_T4_EXEC"/>
 377         <value value="27" name="PERF_CP_SQE_LOAD_STATE_EXEC"/>
 378         <value value="28" name="PERF_CP_SQE_SAVE_SDS_STATE"/>
 379         <value value="29" name="PERF_CP_SQE_DRAW_EXEC"/>
 380         <value value="30" name="PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/>
 381         <value value="31" name="PERF_CP_SQE_EXEC_PROFILED"/>
 382         <value value="32" name="PERF_CP_MEMORY_POOL_EMPTY"/>
 383         <value value="33" name="PERF_CP_MEMORY_POOL_SYNC_STALL"/>
 384         <value value="34" name="PERF_CP_MEMORY_POOL_ABOVE_THRESH"/>
 385         <value value="35" name="PERF_CP_AHB_WR_STALL_PRE_DRAWS"/>
 386         <value value="36" name="PERF_CP_AHB_STALL_SQE_GMU"/>
 387         <value value="37" name="PERF_CP_AHB_STALL_SQE_WR_OTHER"/>
 388         <value value="38" name="PERF_CP_AHB_STALL_SQE_RD_OTHER"/>
 389         <value value="39" name="PERF_CP_CLUSTER0_EMPTY"/>
 390         <value value="40" name="PERF_CP_CLUSTER1_EMPTY"/>
 391         <value value="41" name="PERF_CP_CLUSTER2_EMPTY"/>
 392         <value value="42" name="PERF_CP_CLUSTER3_EMPTY"/>
 393         <value value="43" name="PERF_CP_CLUSTER4_EMPTY"/>
 394         <value value="44" name="PERF_CP_CLUSTER5_EMPTY"/>
 395         <value value="45" name="PERF_CP_PM4_DATA"/>
 396         <value value="46" name="PERF_CP_PM4_HEADERS"/>
 397         <value value="47" name="PERF_CP_VBIF_READ_BEATS"/>
 398         <value value="48" name="PERF_CP_VBIF_WRITE_BEATS"/>
 399         <value value="49" name="PERF_CP_SQE_INSTR_COUNTER"/>
 400 </enum>
 401
 402 <enum name="a6xx_rbbm_perfcounter_select">
 403         <value value="0" name="PERF_RBBM_ALWAYS_COUNT"/>
 404         <value value="1" name="PERF_RBBM_ALWAYS_ON"/>
 405         <value value="2" name="PERF_RBBM_TSE_BUSY"/>
 406         <value value="3" name="PERF_RBBM_RAS_BUSY"/>
 407         <value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/>
 408         <value value="5" name="PERF_RBBM_PC_VSD_BUSY"/>
 409         <value value="6" name="PERF_RBBM_STATUS_MASKED"/>
 410         <value value="7" name="PERF_RBBM_COM_BUSY"/>
 411         <value value="8" name="PERF_RBBM_DCOM_BUSY"/>
 412         <value value="9" name="PERF_RBBM_VBIF_BUSY"/>
 413         <value value="10" name="PERF_RBBM_VSC_BUSY"/>
 414         <value value="11" name="PERF_RBBM_TESS_BUSY"/>
 415         <value value="12" name="PERF_RBBM_UCHE_BUSY"/>
 416         <value value="13" name="PERF_RBBM_HLSQ_BUSY"/>
 417 </enum>
 418
 419 <enum name="a6xx_pc_perfcounter_select">
 420         <value value="0" name="PERF_PC_BUSY_CYCLES"/>
 421         <value value="1" name="PERF_PC_WORKING_CYCLES"/>
 422         <value value="2" name="PERF_PC_STALL_CYCLES_VFD"/>
 423         <value value="3" name="PERF_PC_STALL_CYCLES_TSE"/>
 424         <value value="4" name="PERF_PC_STALL_CYCLES_VPC"/>
 425         <value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/>
 426         <value value="6" name="PERF_PC_STALL_CYCLES_TESS"/>
 427         <value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/>
 428         <value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/>
 429         <value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/>
 430         <value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/>
 431         <value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/>
 432         <value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/>
 433         <value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/>
 434         <value value="14" name="PERF_PC_STARVE_CYCLES_DI"/>
 435         <value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/>
 436         <value value="16" name="PERF_PC_INSTANCES"/>
 437         <value value="17" name="PERF_PC_VPC_PRIMITIVES"/>
 438         <value value="18" name="PERF_PC_DEAD_PRIM"/>
 439         <value value="19" name="PERF_PC_LIVE_PRIM"/>
 440         <value value="20" name="PERF_PC_VERTEX_HITS"/>
 441         <value value="21" name="PERF_PC_IA_VERTICES"/>
 442         <value value="22" name="PERF_PC_IA_PRIMITIVES"/>
 443         <value value="23" name="PERF_PC_GS_PRIMITIVES"/>
 444         <value value="24" name="PERF_PC_HS_INVOCATIONS"/>
 445         <value value="25" name="PERF_PC_DS_INVOCATIONS"/>
 446         <value value="26" name="PERF_PC_VS_INVOCATIONS"/>
 447         <value value="27" name="PERF_PC_GS_INVOCATIONS"/>
 448         <value value="28" name="PERF_PC_DS_PRIMITIVES"/>
 449         <value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/>
 450         <value value="30" name="PERF_PC_3D_DRAWCALLS"/>
 451         <value value="31" name="PERF_PC_2D_DRAWCALLS"/>
 452         <value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/>
 453         <value value="33" name="PERF_TESS_BUSY_CYCLES"/>
 454         <value value="34" name="PERF_TESS_WORKING_CYCLES"/>
 455         <value value="35" name="PERF_TESS_STALL_CYCLES_PC"/>
 456         <value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/>
 457         <value value="37" name="PERF_PC_TSE_TRANSACTION"/>
 458         <value value="38" name="PERF_PC_TSE_VERTEX"/>
 459         <value value="39" name="PERF_PC_TESS_PC_UV_TRANS"/>
 460         <value value="40" name="PERF_PC_TESS_PC_UV_PATCHES"/>
 461         <value value="41" name="PERF_PC_TESS_FACTOR_TRANS"/>
 462 </enum>
 463
 464 <enum name="a6xx_vfd_perfcounter_select">
 465         <value value="0" name="PERF_VFD_BUSY_CYCLES"/>
 466         <value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/>
 467         <value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/>
 468         <value value="3" name="PERF_VFD_STALL_CYCLES_SP_INFO"/>
 469         <value value="4" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/>
 470         <value value="5" name="PERF_VFD_STARVE_CYCLES_UCHE"/>
 471         <value value="6" name="PERF_VFD_RBUFFER_FULL"/>
 472         <value value="7" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/>
 473         <value value="8" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/>
 474         <value value="9" name="PERF_VFD_NUM_ATTRIBUTES"/>
 475         <value value="10" name="PERF_VFD_UPPER_SHADER_FIBERS"/>
 476         <value value="11" name="PERF_VFD_LOWER_SHADER_FIBERS"/>
 477         <value value="12" name="PERF_VFD_MODE_0_FIBERS"/>
 478         <value value="13" name="PERF_VFD_MODE_1_FIBERS"/>
 479         <value value="14" name="PERF_VFD_MODE_2_FIBERS"/>
 480         <value value="15" name="PERF_VFD_MODE_3_FIBERS"/>
 481         <value value="16" name="PERF_VFD_MODE_4_FIBERS"/>
 482         <value value="17" name="PERF_VFD_TOTAL_VERTICES"/>
 483         <value value="18" name="PERF_VFDP_STALL_CYCLES_VFD"/>
 484         <value value="19" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/>
 485         <value value="20" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/>
 486         <value value="21" name="PERF_VFDP_STARVE_CYCLES_PC"/>
 487         <value value="22" name="PERF_VFDP_VS_STAGE_WAVES"/>
 488 </enum>
 489
 490 <enum name="a6xx_hlsq_perfcounter_select">
 491         <value value="0" name="PERF_HLSQ_BUSY_CYCLES"/>
 492         <value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/>
 493         <value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/>
 494         <value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/>
 495         <value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/>
 496         <value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/>
 497         <value value="6" name="PERF_HLSQ_FS_STAGE_1X_WAVES"/>
 498         <value value="7" name="PERF_HLSQ_FS_STAGE_2X_WAVES"/>
 499         <value value="8" name="PERF_HLSQ_QUADS"/>
 500         <value value="9" name="PERF_HLSQ_CS_INVOCATIONS"/>
 501         <value value="10" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/>
 502         <value value="11" name="PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING"/>
 503         <value value="12" name="PERF_HLSQ_DUAL_FS_PROG_ACTIVE"/>
 504         <value value="13" name="PERF_HLSQ_DUAL_VS_PROG_ACTIVE"/>
 505         <value value="14" name="PERF_HLSQ_FS_BATCH_COUNT_ZERO"/>
 506         <value value="15" name="PERF_HLSQ_VS_BATCH_COUNT_ZERO"/>
 507         <value value="16" name="PERF_HLSQ_WAVE_PENDING_NO_QUAD"/>
 508         <value value="17" name="PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE"/>
 509         <value value="18" name="PERF_HLSQ_STALL_CYCLES_VPC"/>
 510         <value value="19" name="PERF_HLSQ_PIXELS"/>
 511         <value value="20" name="PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC"/>
 512 </enum>
 513
 514 <enum name="a6xx_vpc_perfcounter_select">
 515         <value value="0" name="PERF_VPC_BUSY_CYCLES"/>
 516         <value value="1" name="PERF_VPC_WORKING_CYCLES"/>
 517         <value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/>
 518         <value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/>
 519         <value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/>
 520         <value value="5" name="PERF_VPC_STALL_CYCLES_PC"/>
 521         <value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/>
 522         <value value="7" name="PERF_VPC_STARVE_CYCLES_SP"/>
 523         <value value="8" name="PERF_VPC_STARVE_CYCLES_LRZ"/>
 524         <value value="9" name="PERF_VPC_PC_PRIMITIVES"/>
 525         <value value="10" name="PERF_VPC_SP_COMPONENTS"/>
 526         <value value="11" name="PERF_VPC_STALL_CYCLES_VPCRAM_POS"/>
 527         <value value="12" name="PERF_VPC_LRZ_ASSIGN_PRIMITIVES"/>
 528         <value value="13" name="PERF_VPC_RB_VISIBLE_PRIMITIVES"/>
 529         <value value="14" name="PERF_VPC_LM_TRANSACTION"/>
 530         <value value="15" name="PERF_VPC_STREAMOUT_TRANSACTION"/>
 531         <value value="16" name="PERF_VPC_VS_BUSY_CYCLES"/>
 532         <value value="17" name="PERF_VPC_PS_BUSY_CYCLES"/>
 533         <value value="18" name="PERF_VPC_VS_WORKING_CYCLES"/>
 534         <value value="19" name="PERF_VPC_PS_WORKING_CYCLES"/>
 535         <value value="20" name="PERF_VPC_STARVE_CYCLES_RB"/>
 536         <value value="21" name="PERF_VPC_NUM_VPCRAM_READ_POS"/>
 537         <value value="22" name="PERF_VPC_WIT_FULL_CYCLES"/>
 538         <value value="23" name="PERF_VPC_VPCRAM_FULL_CYCLES"/>
 539         <value value="24" name="PERF_VPC_LM_FULL_WAIT_FOR_INTP_END"/>
 540         <value value="25" name="PERF_VPC_NUM_VPCRAM_WRITE"/>
 541         <value value="26" name="PERF_VPC_NUM_VPCRAM_READ_SO"/>
 542         <value value="27" name="PERF_VPC_NUM_ATTR_REQ_LM"/>
 543 </enum>
 544
 545 <enum name="a6xx_tse_perfcounter_select">
 546         <value value="0" name="PERF_TSE_BUSY_CYCLES"/>
 547         <value value="1" name="PERF_TSE_CLIPPING_CYCLES"/>
 548         <value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/>
 549         <value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/>
 550         <value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/>
 551         <value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/>
 552         <value value="6" name="PERF_TSE_INPUT_PRIM"/>
 553         <value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/>
 554         <value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/>
 555         <value value="9" name="PERF_TSE_CLIPPED_PRIM"/>
 556         <value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/>
 557         <value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/>
 558         <value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/>
 559         <value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/>
 560         <value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/>
 561         <value value="15" name="PERF_TSE_CINVOCATION"/>
 562         <value value="16" name="PERF_TSE_CPRIMITIVES"/>
 563         <value value="17" name="PERF_TSE_2D_INPUT_PRIM"/>
 564         <value value="18" name="PERF_TSE_2D_ALIVE_CYCLES"/>
 565         <value value="19" name="PERF_TSE_CLIP_PLANES"/>
 566 </enum>
 567
 568 <enum name="a6xx_ras_perfcounter_select">
 569         <value value="0" name="PERF_RAS_BUSY_CYCLES"/>
 570         <value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/>
 571         <value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/>
 572         <value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/>
 573         <value value="4" name="PERF_RAS_SUPER_TILES"/>
 574         <value value="5" name="PERF_RAS_8X4_TILES"/>
 575         <value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/>
 576         <value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/>
 577         <value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/>
 578         <value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/>
 579         <value value="10" name="PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES"/>
 580         <value value="11" name="PERF_RAS_LRZ_INTF_WORKING_CYCLES"/>
 581         <value value="12" name="PERF_RAS_BLOCKS"/>
 582 </enum>
 583
 584 <enum name="a6xx_uche_perfcounter_select">
 585         <value value="0" name="PERF_UCHE_BUSY_CYCLES"/>
 586         <value value="1" name="PERF_UCHE_STALL_CYCLES_ARBITER"/>
 587         <value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/>
 588         <value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/>
 589         <value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/>
 590         <value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/>
 591         <value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/>
 592         <value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/>
 593         <value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/>
 594         <value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/>
 595         <value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/>
 596         <value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/>
 597         <value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/>
 598         <value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/>
 599         <value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/>
 600         <value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/>
 601         <value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/>
 602         <value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/>
 603         <value value="18" name="PERF_UCHE_EVICTS"/>
 604         <value value="19" name="PERF_UCHE_BANK_REQ0"/>
 605         <value value="20" name="PERF_UCHE_BANK_REQ1"/>
 606         <value value="21" name="PERF_UCHE_BANK_REQ2"/>
 607         <value value="22" name="PERF_UCHE_BANK_REQ3"/>
 608         <value value="23" name="PERF_UCHE_BANK_REQ4"/>
 609         <value value="24" name="PERF_UCHE_BANK_REQ5"/>
 610         <value value="25" name="PERF_UCHE_BANK_REQ6"/>
 611         <value value="26" name="PERF_UCHE_BANK_REQ7"/>
 612         <value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/>
 613         <value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/>
 614         <value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/>
 615         <value value="30" name="PERF_UCHE_TPH_REF_FULL"/>
 616         <value value="31" name="PERF_UCHE_TPH_VICTIM_FULL"/>
 617         <value value="32" name="PERF_UCHE_TPH_EXT_FULL"/>
 618         <value value="33" name="PERF_UCHE_VBIF_STALL_WRITE_DATA"/>
 619         <value value="34" name="PERF_UCHE_DCMP_LATENCY_SAMPLES"/>
 620         <value value="35" name="PERF_UCHE_DCMP_LATENCY_CYCLES"/>
 621         <value value="36" name="PERF_UCHE_VBIF_READ_BEATS_PC"/>
 622         <value value="37" name="PERF_UCHE_READ_REQUESTS_PC"/>
 623         <value value="38" name="PERF_UCHE_RAM_READ_REQ"/>
 624         <value value="39" name="PERF_UCHE_RAM_WRITE_REQ"/>
 625 </enum>
 626
 627 <enum name="a6xx_tp_perfcounter_select">
 628         <value value="0" name="PERF_TP_BUSY_CYCLES"/>
 629         <value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/>
 630         <value value="2" name="PERF_TP_LATENCY_CYCLES"/>
 631         <value value="3" name="PERF_TP_LATENCY_TRANS"/>
 632         <value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/>
 633         <value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/>
 634         <value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/>
 635         <value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/>
 636         <value value="8" name="PERF_TP_SP_TP_TRANS"/>
 637         <value value="9" name="PERF_TP_TP_SP_TRANS"/>
 638         <value value="10" name="PERF_TP_OUTPUT_PIXELS"/>
 639         <value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/>
 640         <value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/>
 641         <value value="13" name="PERF_TP_QUADS_RECEIVED"/>
 642         <value value="14" name="PERF_TP_QUADS_OFFSET"/>
 643         <value value="15" name="PERF_TP_QUADS_SHADOW"/>
 644         <value value="16" name="PERF_TP_QUADS_ARRAY"/>
 645         <value value="17" name="PERF_TP_QUADS_GRADIENT"/>
 646         <value value="18" name="PERF_TP_QUADS_1D"/>
 647         <value value="19" name="PERF_TP_QUADS_2D"/>
 648         <value value="20" name="PERF_TP_QUADS_BUFFER"/>
 649         <value value="21" name="PERF_TP_QUADS_3D"/>
 650         <value value="22" name="PERF_TP_QUADS_CUBE"/>
 651         <value value="23" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/>
 652         <value value="24" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/>
 653         <value value="25" name="PERF_TP_OUTPUT_PIXELS_POINT"/>
 654         <value value="26" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/>
 655         <value value="27" name="PERF_TP_OUTPUT_PIXELS_MIP"/>
 656         <value value="28" name="PERF_TP_OUTPUT_PIXELS_ANISO"/>
 657         <value value="29" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/>
 658         <value value="30" name="PERF_TP_FLAG_CACHE_REQUESTS"/>
 659         <value value="31" name="PERF_TP_FLAG_CACHE_MISSES"/>
 660         <value value="32" name="PERF_TP_L1_5_L2_REQUESTS"/>
 661         <value value="33" name="PERF_TP_2D_OUTPUT_PIXELS"/>
 662         <value value="34" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/>
 663         <value value="35" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/>
 664         <value value="36" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/>
 665         <value value="37" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/>
 666         <value value="38" name="PERF_TP_TPA2TPC_TRANS"/>
 667         <value value="39" name="PERF_TP_L1_MISSES_ASTC_1TILE"/>
 668         <value value="40" name="PERF_TP_L1_MISSES_ASTC_2TILE"/>
 669         <value value="41" name="PERF_TP_L1_MISSES_ASTC_4TILE"/>
 670         <value value="42" name="PERF_TP_L1_5_L2_COMPRESS_REQS"/>
 671         <value value="43" name="PERF_TP_L1_5_L2_COMPRESS_MISS"/>
 672         <value value="44" name="PERF_TP_L1_BANK_CONFLICT"/>
 673         <value value="45" name="PERF_TP_L1_5_MISS_LATENCY_CYCLES"/>
 674         <value value="46" name="PERF_TP_L1_5_MISS_LATENCY_TRANS"/>
 675         <value value="47" name="PERF_TP_QUADS_CONSTANT_MULTIPLIED"/>
 676         <value value="48" name="PERF_TP_FRONTEND_WORKING_CYCLES"/>
 677         <value value="49" name="PERF_TP_L1_TAG_WORKING_CYCLES"/>
 678         <value value="50" name="PERF_TP_L1_DATA_WRITE_WORKING_CYCLES"/>
 679         <value value="51" name="PERF_TP_PRE_L1_DECOM_WORKING_CYCLES"/>
 680         <value value="52" name="PERF_TP_BACKEND_WORKING_CYCLES"/>
 681         <value value="53" name="PERF_TP_FLAG_CACHE_WORKING_CYCLES"/>
 682         <value value="54" name="PERF_TP_L1_5_CACHE_WORKING_CYCLES"/>
 683         <value value="55" name="PERF_TP_STARVE_CYCLES_SP"/>
 684         <value value="56" name="PERF_TP_STARVE_CYCLES_UCHE"/>
 685 </enum>
 686
 687 <enum name="a6xx_sp_perfcounter_select">
 688         <value value="0" name="PERF_SP_BUSY_CYCLES"/>
 689         <value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/>
 690         <value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/>
 691         <value value="3" name="PERF_SP_STALL_CYCLES_VPC"/>
 692         <value value="4" name="PERF_SP_STALL_CYCLES_TP"/>
 693         <value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/>
 694         <value value="6" name="PERF_SP_STALL_CYCLES_RB"/>
 695         <value value="7" name="PERF_SP_NON_EXECUTION_CYCLES"/>
 696         <value value="8" name="PERF_SP_WAVE_CONTEXTS"/>
 697         <value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/>
 698         <value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/>
 699         <value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/>
 700         <value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/>
 701         <value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/>
 702         <value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/>
 703         <value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/>
 704         <value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/>
 705         <value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/>
 706         <value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/>
 707         <value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/>
 708         <value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/>
 709         <value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/>
 710         <value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/>
 711         <value value="23" name="PERF_SP_WAVE_END_CYCLES"/>
 712         <value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/>
 713         <value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/>
 714         <value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/>
 715         <value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/>
 716         <value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/>
 717         <value value="29" name="PERF_SP_LM_ATOMICS"/>
 718         <value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/>
 719         <value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/>
 720         <value value="32" name="PERF_SP_GM_ATOMICS"/>
 721         <value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/>
 722         <value value="34" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/>
 723         <value value="35" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/>
 724         <value value="36" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/>
 725         <value value="37" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/>
 726         <value value="38" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/>
 727         <value value="39" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/>
 728         <value value="40" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/>
 729         <value value="41" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/>
 730         <value value="42" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/>
 731         <value value="43" name="PERF_SP_VS_INSTRUCTIONS"/>
 732         <value value="44" name="PERF_SP_FS_INSTRUCTIONS"/>
 733         <value value="45" name="PERF_SP_ADDR_LOCK_COUNT"/>
 734         <value value="46" name="PERF_SP_UCHE_READ_TRANS"/>
 735         <value value="47" name="PERF_SP_UCHE_WRITE_TRANS"/>
 736         <value value="48" name="PERF_SP_EXPORT_VPC_TRANS"/>
 737         <value value="49" name="PERF_SP_EXPORT_RB_TRANS"/>
 738         <value value="50" name="PERF_SP_PIXELS_KILLED"/>
 739         <value value="51" name="PERF_SP_ICL1_REQUESTS"/>
 740         <value value="52" name="PERF_SP_ICL1_MISSES"/>
 741         <value value="53" name="PERF_SP_HS_INSTRUCTIONS"/>
 742         <value value="54" name="PERF_SP_DS_INSTRUCTIONS"/>
 743         <value value="55" name="PERF_SP_GS_INSTRUCTIONS"/>
 744         <value value="56" name="PERF_SP_CS_INSTRUCTIONS"/>
 745         <value value="57" name="PERF_SP_GPR_READ"/>
 746         <value value="58" name="PERF_SP_GPR_WRITE"/>
 747         <value value="59" name="PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS"/>
 748         <value value="60" name="PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS"/>
 749         <value value="61" name="PERF_SP_LM_BANK_CONFLICTS"/>
 750         <value value="62" name="PERF_SP_TEX_CONTROL_WORKING_CYCLES"/>
 751         <value value="63" name="PERF_SP_LOAD_CONTROL_WORKING_CYCLES"/>
 752         <value value="64" name="PERF_SP_FLOW_CONTROL_WORKING_CYCLES"/>
 753         <value value="65" name="PERF_SP_LM_WORKING_CYCLES"/>
 754         <value value="66" name="PERF_SP_DISPATCHER_WORKING_CYCLES"/>
 755         <value value="67" name="PERF_SP_SEQUENCER_WORKING_CYCLES"/>
 756         <value value="68" name="PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP"/>
 757         <value value="69" name="PERF_SP_STARVE_CYCLES_HLSQ"/>
 758         <value value="70" name="PERF_SP_NON_EXECUTION_LS_CYCLES"/>
 759         <value value="71" name="PERF_SP_WORKING_EU"/>
 760         <value value="72" name="PERF_SP_ANY_EU_WORKING"/>
 761         <value value="73" name="PERF_SP_WORKING_EU_FS_STAGE"/>
 762         <value value="74" name="PERF_SP_ANY_EU_WORKING_FS_STAGE"/>
 763         <value value="75" name="PERF_SP_WORKING_EU_VS_STAGE"/>
 764         <value value="76" name="PERF_SP_ANY_EU_WORKING_VS_STAGE"/>
 765         <value value="77" name="PERF_SP_WORKING_EU_CS_STAGE"/>
 766         <value value="78" name="PERF_SP_ANY_EU_WORKING_CS_STAGE"/>
 767         <value value="79" name="PERF_SP_GPR_READ_PREFETCH"/>
 768         <value value="80" name="PERF_SP_GPR_READ_CONFLICT"/>
 769         <value value="81" name="PERF_SP_GPR_WRITE_CONFLICT"/>
 770         <value value="82" name="PERF_SP_GM_LOAD_LATENCY_CYCLES"/>
 771         <value value="83" name="PERF_SP_GM_LOAD_LATENCY_SAMPLES"/>
 772         <value value="84" name="PERF_SP_EXECUTABLE_WAVES"/>
 773 </enum>
 774
 775 <enum name="a6xx_rb_perfcounter_select">
 776         <value value="0" name="PERF_RB_BUSY_CYCLES"/>
 777         <value value="1" name="PERF_RB_STALL_CYCLES_HLSQ"/>
 778         <value value="2" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/>
 779         <value value="3" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/>
 780         <value value="4" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/>
 781         <value value="5" name="PERF_RB_STARVE_CYCLES_SP"/>
 782         <value value="6" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/>
 783         <value value="7" name="PERF_RB_STARVE_CYCLES_CCU"/>
 784         <value value="8" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/>
 785         <value value="9" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/>
 786         <value value="10" name="PERF_RB_Z_WORKLOAD"/>
 787         <value value="11" name="PERF_RB_HLSQ_ACTIVE"/>
 788         <value value="12" name="PERF_RB_Z_READ"/>
 789         <value value="13" name="PERF_RB_Z_WRITE"/>
 790         <value value="14" name="PERF_RB_C_READ"/>
 791         <value value="15" name="PERF_RB_C_WRITE"/>
 792         <value value="16" name="PERF_RB_TOTAL_PASS"/>
 793         <value value="17" name="PERF_RB_Z_PASS"/>
 794         <value value="18" name="PERF_RB_Z_FAIL"/>
 795         <value value="19" name="PERF_RB_S_FAIL"/>
 796         <value value="20" name="PERF_RB_BLENDED_FXP_COMPONENTS"/>
 797         <value value="21" name="PERF_RB_BLENDED_FP16_COMPONENTS"/>
 798         <value value="22" name="PERF_RB_PS_INVOCATIONS"/>
 799         <value value="23" name="PERF_RB_2D_ALIVE_CYCLES"/>
 800         <value value="24" name="PERF_RB_2D_STALL_CYCLES_A2D"/>
 801         <value value="25" name="PERF_RB_2D_STARVE_CYCLES_SRC"/>
 802         <value value="26" name="PERF_RB_2D_STARVE_CYCLES_SP"/>
 803         <value value="27" name="PERF_RB_2D_STARVE_CYCLES_DST"/>
 804         <value value="28" name="PERF_RB_2D_VALID_PIXELS"/>
 805         <value value="29" name="PERF_RB_3D_PIXELS"/>
 806         <value value="30" name="PERF_RB_BLENDER_WORKING_CYCLES"/>
 807         <value value="31" name="PERF_RB_ZPROC_WORKING_CYCLES"/>
 808         <value value="32" name="PERF_RB_CPROC_WORKING_CYCLES"/>
 809         <value value="33" name="PERF_RB_SAMPLER_WORKING_CYCLES"/>
 810         <value value="34" name="PERF_RB_STALL_CYCLES_CCU_COLOR_READ"/>
 811         <value value="35" name="PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE"/>
 812         <value value="36" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_READ"/>
 813         <value value="37" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE"/>
 814         <value value="38" name="PERF_RB_STALL_CYCLES_VPC"/>
 815         <value value="39" name="PERF_RB_2D_INPUT_TRANS"/>
 816         <value value="40" name="PERF_RB_2D_OUTPUT_RB_DST_TRANS"/>
 817         <value value="41" name="PERF_RB_2D_OUTPUT_RB_SRC_TRANS"/>
 818         <value value="42" name="PERF_RB_BLENDED_FP32_COMPONENTS"/>
 819         <value value="43" name="PERF_RB_COLOR_PIX_TILES"/>
 820         <value value="44" name="PERF_RB_STALL_CYCLES_CCU"/>
 821         <value value="45" name="PERF_RB_EARLY_Z_ARB3_GRANT"/>
 822         <value value="46" name="PERF_RB_LATE_Z_ARB3_GRANT"/>
 823         <value value="47" name="PERF_RB_EARLY_Z_SKIP_GRANT"/>
 824 </enum>
 825
 826 <enum name="a6xx_vsc_perfcounter_select">
 827         <value value="0" name="PERF_VSC_BUSY_CYCLES"/>
 828         <value value="1" name="PERF_VSC_WORKING_CYCLES"/>
 829         <value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/>
 830         <value value="3" name="PERF_VSC_EOT_NUM"/>
 831         <value value="4" name="PERF_VSC_INPUT_TILES"/>
 832 </enum>
 833
 834 <enum name="a6xx_ccu_perfcounter_select">
 835         <value value="0" name="PERF_CCU_BUSY_CYCLES"/>
 836         <value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/>
 837         <value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/>
 838         <value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/>
 839         <value value="4" name="PERF_CCU_DEPTH_BLOCKS"/>
 840         <value value="5" name="PERF_CCU_COLOR_BLOCKS"/>
 841         <value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/>
 842         <value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/>
 843         <value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/>
 844         <value value="9" name="PERF_CCU_GMEM_READ"/>
 845         <value value="10" name="PERF_CCU_GMEM_WRITE"/>
 846         <value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/>
 847         <value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/>
 848         <value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/>
 849         <value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/>
 850         <value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/>
 851         <value value="16" name="PERF_CCU_DEPTH_READ_FLAG5_COUNT"/>
 852         <value value="17" name="PERF_CCU_DEPTH_READ_FLAG6_COUNT"/>
 853         <value value="18" name="PERF_CCU_DEPTH_READ_FLAG8_COUNT"/>
 854         <value value="19" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/>
 855         <value value="20" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/>
 856         <value value="21" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/>
 857         <value value="22" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/>
 858         <value value="23" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/>
 859         <value value="24" name="PERF_CCU_COLOR_READ_FLAG5_COUNT"/>
 860         <value value="25" name="PERF_CCU_COLOR_READ_FLAG6_COUNT"/>
 861         <value value="26" name="PERF_CCU_COLOR_READ_FLAG8_COUNT"/>
 862         <value value="27" name="PERF_CCU_2D_RD_REQ"/>
 863         <value value="28" name="PERF_CCU_2D_WR_REQ"/>
 864 </enum>
 865
 866 <enum name="a6xx_lrz_perfcounter_select">
 867         <value value="0" name="PERF_LRZ_BUSY_CYCLES"/>
 868         <value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/>
 869         <value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/>
 870         <value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/>
 871         <value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/>
 872         <value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/>
 873         <value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/>
 874         <value value="7" name="PERF_LRZ_LRZ_READ"/>
 875         <value value="8" name="PERF_LRZ_LRZ_WRITE"/>
 876         <value value="9" name="PERF_LRZ_READ_LATENCY"/>
 877         <value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/>
 878         <value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/>
 879         <value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/>
 880         <value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/>
 881         <value value="14" name="PERF_LRZ_FULL_8X8_TILES"/>
 882         <value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/>
 883         <value value="16" name="PERF_LRZ_TILE_KILLED"/>
 884         <value value="17" name="PERF_LRZ_TOTAL_PIXEL"/>
 885         <value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/>
 886         <value value="19" name="PERF_LRZ_FULLY_COVERED_TILES"/>
 887         <value value="20" name="PERF_LRZ_PARTIAL_COVERED_TILES"/>
 888         <value value="21" name="PERF_LRZ_FEEDBACK_ACCEPT"/>
 889         <value value="22" name="PERF_LRZ_FEEDBACK_DISCARD"/>
 890         <value value="23" name="PERF_LRZ_FEEDBACK_STALL"/>
 891         <value value="24" name="PERF_LRZ_STALL_CYCLES_RB_ZPLANE"/>
 892         <value value="25" name="PERF_LRZ_STALL_CYCLES_RB_BPLANE"/>
 893         <value value="26" name="PERF_LRZ_STALL_CYCLES_VC"/>
 894         <value value="27" name="PERF_LRZ_RAS_MASK_TRANS"/>
 895 </enum>
 896
 897 <enum name="a6xx_cmp_perfcounter_select">
 898         <value value="0" name="PERF_CMPDECMP_STALL_CYCLES_ARB"/>
 899         <value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/>
 900         <value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/>
 901         <value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/>
 902         <value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/>
 903         <value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/>
 904         <value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/>
 905         <value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/>
 906         <value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/>
 907         <value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/>
 908         <value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/>
 909         <value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/>
 910         <value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/>
 911         <value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/>
 912         <value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/>
 913         <value value="15" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT"/>
 914         <value value="16" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT"/>
 915         <value value="17" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT"/>
 916         <value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/>
 917         <value value="19" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/>
 918         <value value="20" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/>
 919         <value value="21" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/>
 920         <value value="22" name="PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT"/>
 921         <value value="23" name="PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT"/>
 922         <value value="24" name="PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT"/>
 923         <value value="25" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/>
 924         <value value="26" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/>
 925         <value value="27" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/>
 926         <value value="28" name="PERF_CMPDECMP_2D_RD_DATA"/>
 927         <value value="29" name="PERF_CMPDECMP_2D_WR_DATA"/>
 928         <value value="30" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0"/>
 929         <value value="31" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1"/>
 930         <value value="32" name="PERF_CMPDECMP_2D_OUTPUT_TRANS"/>
 931         <value value="33" name="PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE"/>
 932         <value value="34" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT"/>
 933         <value value="35" name="PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT"/>
 934         <value value="36" name="PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT"/>
 935         <value value="37" name="PERF_CMPDECMP_2D_BUSY_CYCLES"/>
 936         <value value="38" name="PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES"/>
 937         <value value="39" name="PERF_CMPDECMP_2D_PIXELS"/>
 938 </enum>
 939
 940 <!--
 941 Used in a6xx_2d_blit_cntl.. the value mostly seems to correlate to the
 942 component type/size, so I think it relates to internal format used for
 943 blending?  The one exception is that 16b unorm and 32b float use the
 944 same value... maybe 16b unorm is uncommon enough that it was just easier
 945 to upconvert to 32b float internally?
 946
 947  8b unorm:  10
 948 16b unorm:   4
 949
 950 32b int:     7
 951 16b int:     6
 952  8b int:     5
 953
 954 32b float:   4
 955 16b float:   3
 956  -->
 957 <enum name="a6xx_2d_ifmt">
 958         <value value="0x10" name="R2D_UNORM8"/>
 959         <value value="0x7"  name="R2D_INT32"/>
 960         <value value="0x6"  name="R2D_INT16"/>
 961         <value value="0x5"  name="R2D_INT8"/>
 962         <value value="0x4"  name="R2D_FLOAT32"/>
 963         <value value="0x3"  name="R2D_FLOAT16"/>
 964 </enum>
 965
 966 <domain name="A6XX" width="32">
 967         <bitset name="A6XX_RBBM_INT_0_MASK">
 968                 <bitfield name="RBBM_GPU_IDLE" pos="0"/>
 969                 <bitfield name="CP_AHB_ERROR" pos="1"/>
 970                 <bitfield name="RBBM_ATB_ASYNCFIFO_OVERFLOW" pos="6"/>
 971                 <bitfield name="RBBM_GPC_ERROR" pos="7"/>
 972                 <bitfield name="CP_SW" pos="8"/>
 973                 <bitfield name="CP_HW_ERROR" pos="9"/>
 974                 <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10"/>
 975                 <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11"/>
 976                 <bitfield name="CP_CCU_RESOLVE_TS" pos="12"/>
 977                 <bitfield name="CP_IB2" pos="13"/>
 978                 <bitfield name="CP_IB1" pos="14"/>
 979                 <bitfield name="CP_RB" pos="15"/>
 980                 <bitfield name="CP_RB_DONE_TS" pos="17"/>
 981                 <bitfield name="CP_WT_DONE_TS" pos="18"/>
 982                 <bitfield name="CP_CACHE_FLUSH_TS" pos="20"/>
 983                 <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22"/>
 984                 <bitfield name="RBBM_HANG_DETECT" pos="23"/>
 985                 <bitfield name="UCHE_OOB_ACCESS" pos="24"/>
 986                 <bitfield name="UCHE_TRAP_INTR" pos="25"/>
 987                 <bitfield name="DEBBUS_INTR_0" pos="26"/>
 988                 <bitfield name="DEBBUS_INTR_1" pos="27"/>
 989                 <bitfield name="ISDB_CPU_IRQ" pos="30"/>
 990                 <bitfield name="ISDB_UNDER_DEBUG" pos="31"/>
 991         </bitset>
 992
 993         <bitset name="A6XX_CP_INT">
 994                 <bitfield name="CP_OPCODE_ERROR" pos="0"/>
 995                 <bitfield name="CP_UCODE_ERROR" pos="1"/>
 996                 <bitfield name="CP_HW_FAULT_ERROR" pos="2"/>
 997                 <bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4"/>
 998                 <bitfield name="CP_AHB_ERROR" pos="5"/>
 999                 <bitfield name="CP_VSD_PARITY_ERROR" pos="6"/>
1000                 <bitfield name="CP_ILLEGAL_INSTR_ERROR" pos="7"/>
1001         </bitset>
1002
1003         <reg32 offset="0x0800" name="CP_RB_BASE"/>
1004         <reg32 offset="0x0801" name="CP_RB_BASE_HI"/>
1005         <reg32 offset="0x0802" name="CP_RB_CNTL"/>
1006         <reg32 offset="0x0804" name="CP_RB_RPTR_ADDR_LO"/>
1007         <reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/>
1008         <reg32 offset="0x0806" name="CP_RB_RPTR"/>
1009         <reg32 offset="0x0807" name="CP_RB_WPTR"/>
1010         <reg32 offset="0x0808" name="CP_SQE_CNTL"/>
1011         <reg32 offset="0x0821" name="CP_HW_FAULT"/>
1012         <reg32 offset="0x0823" name="CP_INTERRUPT_STATUS"/>
1013         <reg32 offset="0x0824" name="CP_PROTECT_STATUS"/>
1014         <reg32 offset="0x0830" name="CP_SQE_INSTR_BASE_LO"/>
1015         <reg32 offset="0x0831" name="CP_SQE_INSTR_BASE_HI"/>
1016         <reg32 offset="0x0840" name="CP_MISC_CNTL"/>
1017         <reg32 offset="0x08C1" name="CP_ROQ_THRESHOLDS_1"/>
1018         <reg32 offset="0x08C2" name="CP_ROQ_THRESHOLDS_2"/>
1019         <reg32 offset="0x08C3" name="CP_MEM_POOL_SIZE"/>
1020         <reg32 offset="0x0841" name="CP_CHICKEN_DBG"/>
1021         <reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL"/>
1022         <reg32 offset="0x0843" name="CP_DBG_ECO_CNTL"/>
1023         <reg32 offset="0x084F" name="CP_PROTECT_CNTL"/>
1024
1025         <array offset="0x0883" name="CP_SCRATCH" stride="1" length="8">
1026                 <reg32 offset="0x0" name="REG" type="uint"/>
1027         </array>
1028         <array offset="0x0850" name="CP_PROTECT" stride="1" length="32">
1029                 <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/>
1030         </array>
1031
1032         <reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"/>
1033         <reg32 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO_LO"/>
1034         <reg32 offset="0x08A2" name="CP_CONTEXT_SWITCH_SMMU_INFO_HI"/>
1035         <reg32 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO"/>
1036         <reg32 offset="0x08A4" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI"/>
1037         <reg32 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO"/>
1038         <reg32 offset="0x08A6" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI"/>
1039         <reg32 offset="0x08A7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO"/>
1040         <reg32 offset="0x08A8" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI"/>
1041         <reg32 offset="0x08D0" name="CP_PERFCTR_CP_SEL_0"/>
1042         <reg32 offset="0x08D1" name="CP_PERFCTR_CP_SEL_1"/>
1043         <reg32 offset="0x08D2" name="CP_PERFCTR_CP_SEL_2"/>
1044         <reg32 offset="0x08D3" name="CP_PERFCTR_CP_SEL_3"/>
1045         <reg32 offset="0x08D4" name="CP_PERFCTR_CP_SEL_4"/>
1046         <reg32 offset="0x08D5" name="CP_PERFCTR_CP_SEL_5"/>
1047         <reg32 offset="0x08D6" name="CP_PERFCTR_CP_SEL_6"/>
1048         <reg32 offset="0x08D7" name="CP_PERFCTR_CP_SEL_7"/>
1049         <reg32 offset="0x08D8" name="CP_PERFCTR_CP_SEL_8"/>
1050         <reg32 offset="0x08D9" name="CP_PERFCTR_CP_SEL_9"/>
1051         <reg32 offset="0x08DA" name="CP_PERFCTR_CP_SEL_10"/>
1052         <reg32 offset="0x08DB" name="CP_PERFCTR_CP_SEL_11"/>
1053         <reg32 offset="0x08DC" name="CP_PERFCTR_CP_SEL_12"/>
1054         <reg32 offset="0x08DD" name="CP_PERFCTR_CP_SEL_13"/>
1055         <reg32 offset="0x0900" name="CP_CRASH_SCRIPT_BASE_LO"/>
1056         <reg32 offset="0x0901" name="CP_CRASH_SCRIPT_BASE_HI"/>
1057         <reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/>
1058         <reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/>
1059         <reg32 offset="0x0908" name="CP_SQE_STAT_ADDR"/>
1060         <reg32 offset="0x0909" name="CP_SQE_STAT_DATA"/>
1061         <reg32 offset="0x090A" name="CP_DRAW_STATE_ADDR"/>
1062         <reg32 offset="0x090B" name="CP_DRAW_STATE_DATA"/>
1063         <reg32 offset="0x090C" name="CP_ROQ_DBG_ADDR"/>
1064         <reg32 offset="0x090D" name="CP_ROQ_DBG_DATA"/>
1065         <reg32 offset="0x090E" name="CP_MEM_POOL_DBG_ADDR"/>
1066         <reg32 offset="0x090F" name="CP_MEM_POOL_DBG_DATA"/>
1067         <reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR"/>
1068         <reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA"/>
1069         <reg32 offset="0x0928" name="CP_IB1_BASE"/>
1070         <reg32 offset="0x0929" name="CP_IB1_BASE_HI"/>
1071         <reg32 offset="0x092A" name="CP_IB1_REM_SIZE"/>
1072         <reg32 offset="0x092B" name="CP_IB2_BASE"/>
1073         <reg32 offset="0x092C" name="CP_IB2_BASE_HI"/>
1074         <reg32 offset="0x092D" name="CP_IB2_REM_SIZE"/>
1075         <reg32 offset="0x0980" name="CP_ALWAYS_ON_COUNTER_LO"/>
1076         <reg32 offset="0x0981" name="CP_ALWAYS_ON_COUNTER_HI"/>
1077         <reg32 offset="0x098D" name="CP_AHB_CNTL"/>
1078         <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST"/>
1079         <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD"/>
1080         <reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL"/>
1081         <reg32 offset="0x0201" name="RBBM_INT_0_STATUS"/>
1082         <reg32 offset="0x0210" name="RBBM_STATUS">
1083                 <bitfield high="23" low="23" name="GPU_BUSY_IGN_AHB" />
1084                 <bitfield high="22" low="22" name="GPU_BUSY_IGN_AHB_CP" />
1085                 <bitfield high="21" low="21" name="HLSQ_BUSY" />
1086                 <bitfield high="20" low="20" name="VSC_BUSY" />
1087                 <bitfield high="19" low="19" name="TPL1_BUSY" />
1088                 <bitfield high="18" low="18" name="SP_BUSY" />
1089                 <bitfield high="17" low="17" name="UCHE_BUSY" />
1090                 <bitfield high="16" low="16" name="VPC_BUSY" />
1091                 <bitfield high="15" low="15" name="VFD_BUSY" />
1092                 <bitfield high="14" low="14" name="TESS_BUSY" />
1093                 <bitfield high="13" low="13" name="PC_VSD_BUSY" />
1094                 <bitfield high="12" low="12" name="PC_DCALL_BUSY" />
1095                 <bitfield high="11" low="11" name="COM_DCOM_BUSY" />
1096                 <bitfield high="10" low="10" name="LRZ_BUSY" />
1097                 <bitfield high="9" low="9" name="A2D_BUSY" />
1098                 <bitfield high="8" low="8" name="CCU_BUSY" />
1099                 <bitfield high="7" low="7" name="RB_BUSY" />
1100                 <bitfield high="6" low="6" name="RAS_BUSY" />
1101                 <bitfield high="5" low="5" name="TSE_BUSY" />
1102                 <bitfield high="4" low="4" name="VBIF_BUSY" />
1103                 <bitfield high="3" low="3" name="GFX_DBGC_BUSY" />
1104                 <bitfield high="2" low="2" name="CP_BUSY" />
1105                 <bitfield high="1" low="1" name="CP_AHB_BUSY_CP_MASTER" />
1106                 <bitfield high="0" low="0" name="CP_AHB_BUSY_CX_MASTER"/>
1107         </reg32>
1108         <reg32 offset="0x0213" name="RBBM_STATUS3"/>
1109         <reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS"/>
1110         <reg32 offset="0x0400" name="RBBM_PERFCTR_CP_0_LO"/>
1111         <reg32 offset="0x0401" name="RBBM_PERFCTR_CP_0_HI"/>
1112         <reg32 offset="0x0402" name="RBBM_PERFCTR_CP_1_LO"/>
1113         <reg32 offset="0x0403" name="RBBM_PERFCTR_CP_1_HI"/>
1114         <reg32 offset="0x0404" name="RBBM_PERFCTR_CP_2_LO"/>
1115         <reg32 offset="0x0405" name="RBBM_PERFCTR_CP_2_HI"/>
1116         <reg32 offset="0x0406" name="RBBM_PERFCTR_CP_3_LO"/>
1117         <reg32 offset="0x0407" name="RBBM_PERFCTR_CP_3_HI"/>
1118         <reg32 offset="0x0408" name="RBBM_PERFCTR_CP_4_LO"/>
1119         <reg32 offset="0x0409" name="RBBM_PERFCTR_CP_4_HI"/>
1120         <reg32 offset="0x040a" name="RBBM_PERFCTR_CP_5_LO"/>
1121         <reg32 offset="0x040b" name="RBBM_PERFCTR_CP_5_HI"/>
1122         <reg32 offset="0x040c" name="RBBM_PERFCTR_CP_6_LO"/>
1123         <reg32 offset="0x040d" name="RBBM_PERFCTR_CP_6_HI"/>
1124         <reg32 offset="0x040e" name="RBBM_PERFCTR_CP_7_LO"/>
1125         <reg32 offset="0x040f" name="RBBM_PERFCTR_CP_7_HI"/>
1126         <reg32 offset="0x0410" name="RBBM_PERFCTR_CP_8_LO"/>
1127         <reg32 offset="0x0411" name="RBBM_PERFCTR_CP_8_HI"/>
1128         <reg32 offset="0x0412" name="RBBM_PERFCTR_CP_9_LO"/>
1129         <reg32 offset="0x0413" name="RBBM_PERFCTR_CP_9_HI"/>
1130         <reg32 offset="0x0414" name="RBBM_PERFCTR_CP_10_LO"/>
1131         <reg32 offset="0x0415" name="RBBM_PERFCTR_CP_10_HI"/>
1132         <reg32 offset="0x0416" name="RBBM_PERFCTR_CP_11_LO"/>
1133         <reg32 offset="0x0417" name="RBBM_PERFCTR_CP_11_HI"/>
1134         <reg32 offset="0x0418" name="RBBM_PERFCTR_CP_12_LO"/>
1135         <reg32 offset="0x0419" name="RBBM_PERFCTR_CP_12_HI"/>
1136         <reg32 offset="0x041a" name="RBBM_PERFCTR_CP_13_LO"/>
1137         <reg32 offset="0x041b" name="RBBM_PERFCTR_CP_13_HI"/>
1138         <reg32 offset="0x041c" name="RBBM_PERFCTR_RBBM_0_LO"/>
1139         <reg32 offset="0x041d" name="RBBM_PERFCTR_RBBM_0_HI"/>
1140         <reg32 offset="0x041e" name="RBBM_PERFCTR_RBBM_1_LO"/>
1141         <reg32 offset="0x041f" name="RBBM_PERFCTR_RBBM_1_HI"/>
1142         <reg32 offset="0x0420" name="RBBM_PERFCTR_RBBM_2_LO"/>
1143         <reg32 offset="0x0421" name="RBBM_PERFCTR_RBBM_2_HI"/>
1144         <reg32 offset="0x0422" name="RBBM_PERFCTR_RBBM_3_LO"/>
1145         <reg32 offset="0x0423" name="RBBM_PERFCTR_RBBM_3_HI"/>
1146         <reg32 offset="0x0424" name="RBBM_PERFCTR_PC_0_LO"/>
1147         <reg32 offset="0x0425" name="RBBM_PERFCTR_PC_0_HI"/>
1148         <reg32 offset="0x0426" name="RBBM_PERFCTR_PC_1_LO"/>
1149         <reg32 offset="0x0427" name="RBBM_PERFCTR_PC_1_HI"/>
1150         <reg32 offset="0x0428" name="RBBM_PERFCTR_PC_2_LO"/>
1151         <reg32 offset="0x0429" name="RBBM_PERFCTR_PC_2_HI"/>
1152         <reg32 offset="0x042a" name="RBBM_PERFCTR_PC_3_LO"/>
1153         <reg32 offset="0x042b" name="RBBM_PERFCTR_PC_3_HI"/>
1154         <reg32 offset="0x042c" name="RBBM_PERFCTR_PC_4_LO"/>
1155         <reg32 offset="0x042d" name="RBBM_PERFCTR_PC_4_HI"/>
1156         <reg32 offset="0x042e" name="RBBM_PERFCTR_PC_5_LO"/>
1157         <reg32 offset="0x042f" name="RBBM_PERFCTR_PC_5_HI"/>
1158         <reg32 offset="0x0430" name="RBBM_PERFCTR_PC_6_LO"/>
1159         <reg32 offset="0x0431" name="RBBM_PERFCTR_PC_6_HI"/>
1160         <reg32 offset="0x0432" name="RBBM_PERFCTR_PC_7_LO"/>
1161         <reg32 offset="0x0433" name="RBBM_PERFCTR_PC_7_HI"/>
1162         <reg32 offset="0x0434" name="RBBM_PERFCTR_VFD_0_LO"/>
1163         <reg32 offset="0x0435" name="RBBM_PERFCTR_VFD_0_HI"/>
1164         <reg32 offset="0x0436" name="RBBM_PERFCTR_VFD_1_LO"/>
1165         <reg32 offset="0x0437" name="RBBM_PERFCTR_VFD_1_HI"/>
1166         <reg32 offset="0x0438" name="RBBM_PERFCTR_VFD_2_LO"/>
1167         <reg32 offset="0x0439" name="RBBM_PERFCTR_VFD_2_HI"/>
1168         <reg32 offset="0x043a" name="RBBM_PERFCTR_VFD_3_LO"/>
1169         <reg32 offset="0x043b" name="RBBM_PERFCTR_VFD_3_HI"/>
1170         <reg32 offset="0x043c" name="RBBM_PERFCTR_VFD_4_LO"/>
1171         <reg32 offset="0x043d" name="RBBM_PERFCTR_VFD_4_HI"/>
1172         <reg32 offset="0x043e" name="RBBM_PERFCTR_VFD_5_LO"/>
1173         <reg32 offset="0x043f" name="RBBM_PERFCTR_VFD_5_HI"/>
1174         <reg32 offset="0x0440" name="RBBM_PERFCTR_VFD_6_LO"/>
1175         <reg32 offset="0x0441" name="RBBM_PERFCTR_VFD_6_HI"/>
1176         <reg32 offset="0x0442" name="RBBM_PERFCTR_VFD_7_LO"/>
1177         <reg32 offset="0x0443" name="RBBM_PERFCTR_VFD_7_HI"/>
1178         <reg32 offset="0x0444" name="RBBM_PERFCTR_HLSQ_0_LO"/>
1179         <reg32 offset="0x0445" name="RBBM_PERFCTR_HLSQ_0_HI"/>
1180         <reg32 offset="0x0446" name="RBBM_PERFCTR_HLSQ_1_LO"/>
1181         <reg32 offset="0x0447" name="RBBM_PERFCTR_HLSQ_1_HI"/>
1182         <reg32 offset="0x0448" name="RBBM_PERFCTR_HLSQ_2_LO"/>
1183         <reg32 offset="0x0449" name="RBBM_PERFCTR_HLSQ_2_HI"/>
1184         <reg32 offset="0x044a" name="RBBM_PERFCTR_HLSQ_3_LO"/>
1185         <reg32 offset="0x044b" name="RBBM_PERFCTR_HLSQ_3_HI"/>
1186         <reg32 offset="0x044c" name="RBBM_PERFCTR_HLSQ_4_LO"/>
1187         <reg32 offset="0x044d" name="RBBM_PERFCTR_HLSQ_4_HI"/>
1188         <reg32 offset="0x044e" name="RBBM_PERFCTR_HLSQ_5_LO"/>
1189         <reg32 offset="0x044f" name="RBBM_PERFCTR_HLSQ_5_HI"/>
1190         <reg32 offset="0x0450" name="RBBM_PERFCTR_VPC_0_LO"/>
1191         <reg32 offset="0x0451" name="RBBM_PERFCTR_VPC_0_HI"/>
1192         <reg32 offset="0x0452" name="RBBM_PERFCTR_VPC_1_LO"/>
1193         <reg32 offset="0x0453" name="RBBM_PERFCTR_VPC_1_HI"/>
1194         <reg32 offset="0x0454" name="RBBM_PERFCTR_VPC_2_LO"/>
1195         <reg32 offset="0x0455" name="RBBM_PERFCTR_VPC_2_HI"/>
1196         <reg32 offset="0x0456" name="RBBM_PERFCTR_VPC_3_LO"/>
1197         <reg32 offset="0x0457" name="RBBM_PERFCTR_VPC_3_HI"/>
1198         <reg32 offset="0x0458" name="RBBM_PERFCTR_VPC_4_LO"/>
1199         <reg32 offset="0x0459" name="RBBM_PERFCTR_VPC_4_HI"/>
1200         <reg32 offset="0x045a" name="RBBM_PERFCTR_VPC_5_LO"/>
1201         <reg32 offset="0x045b" name="RBBM_PERFCTR_VPC_5_HI"/>
1202         <reg32 offset="0x045c" name="RBBM_PERFCTR_CCU_0_LO"/>
1203         <reg32 offset="0x045d" name="RBBM_PERFCTR_CCU_0_HI"/>
1204         <reg32 offset="0x045e" name="RBBM_PERFCTR_CCU_1_LO"/>
1205         <reg32 offset="0x045f" name="RBBM_PERFCTR_CCU_1_HI"/>
1206         <reg32 offset="0x0460" name="RBBM_PERFCTR_CCU_2_LO"/>
1207         <reg32 offset="0x0461" name="RBBM_PERFCTR_CCU_2_HI"/>
1208         <reg32 offset="0x0462" name="RBBM_PERFCTR_CCU_3_LO"/>
1209         <reg32 offset="0x0463" name="RBBM_PERFCTR_CCU_3_HI"/>
1210         <reg32 offset="0x0464" name="RBBM_PERFCTR_CCU_4_LO"/>
1211         <reg32 offset="0x0465" name="RBBM_PERFCTR_CCU_4_HI"/>
1212         <reg32 offset="0x0466" name="RBBM_PERFCTR_TSE_0_LO"/>
1213         <reg32 offset="0x0467" name="RBBM_PERFCTR_TSE_0_HI"/>
1214         <reg32 offset="0x0468" name="RBBM_PERFCTR_TSE_1_LO"/>
1215         <reg32 offset="0x0469" name="RBBM_PERFCTR_TSE_1_HI"/>
1216         <reg32 offset="0x046a" name="RBBM_PERFCTR_TSE_2_LO"/>
1217         <reg32 offset="0x046b" name="RBBM_PERFCTR_TSE_2_HI"/>
1218         <reg32 offset="0x046c" name="RBBM_PERFCTR_TSE_3_LO"/>
1219         <reg32 offset="0x046d" name="RBBM_PERFCTR_TSE_3_HI"/>
1220         <reg32 offset="0x046e" name="RBBM_PERFCTR_RAS_0_LO"/>
1221         <reg32 offset="0x046f" name="RBBM_PERFCTR_RAS_0_HI"/>
1222         <reg32 offset="0x0470" name="RBBM_PERFCTR_RAS_1_LO"/>
1223         <reg32 offset="0x0471" name="RBBM_PERFCTR_RAS_1_HI"/>
1224         <reg32 offset="0x0472" name="RBBM_PERFCTR_RAS_2_LO"/>
1225         <reg32 offset="0x0473" name="RBBM_PERFCTR_RAS_2_HI"/>
1226         <reg32 offset="0x0474" name="RBBM_PERFCTR_RAS_3_LO"/>
1227         <reg32 offset="0x0475" name="RBBM_PERFCTR_RAS_3_HI"/>
1228         <reg32 offset="0x0476" name="RBBM_PERFCTR_UCHE_0_LO"/>
1229         <reg32 offset="0x0477" name="RBBM_PERFCTR_UCHE_0_HI"/>
1230         <reg32 offset="0x0478" name="RBBM_PERFCTR_UCHE_1_LO"/>
1231         <reg32 offset="0x0479" name="RBBM_PERFCTR_UCHE_1_HI"/>
1232         <reg32 offset="0x047a" name="RBBM_PERFCTR_UCHE_2_LO"/>
1233         <reg32 offset="0x047b" name="RBBM_PERFCTR_UCHE_2_HI"/>
1234         <reg32 offset="0x047c" name="RBBM_PERFCTR_UCHE_3_LO"/>
1235         <reg32 offset="0x047d" name="RBBM_PERFCTR_UCHE_3_HI"/>
1236         <reg32 offset="0x047e" name="RBBM_PERFCTR_UCHE_4_LO"/>
1237         <reg32 offset="0x047f" name="RBBM_PERFCTR_UCHE_4_HI"/>
1238         <reg32 offset="0x0480" name="RBBM_PERFCTR_UCHE_5_LO"/>
1239         <reg32 offset="0x0481" name="RBBM_PERFCTR_UCHE_5_HI"/>
1240         <reg32 offset="0x0482" name="RBBM_PERFCTR_UCHE_6_LO"/>
1241         <reg32 offset="0x0483" name="RBBM_PERFCTR_UCHE_6_HI"/>
1242         <reg32 offset="0x0484" name="RBBM_PERFCTR_UCHE_7_LO"/>
1243         <reg32 offset="0x0485" name="RBBM_PERFCTR_UCHE_7_HI"/>
1244         <reg32 offset="0x0486" name="RBBM_PERFCTR_UCHE_8_LO"/>
1245         <reg32 offset="0x0487" name="RBBM_PERFCTR_UCHE_8_HI"/>
1246         <reg32 offset="0x0488" name="RBBM_PERFCTR_UCHE_9_LO"/>
1247         <reg32 offset="0x0489" name="RBBM_PERFCTR_UCHE_9_HI"/>
1248         <reg32 offset="0x048a" name="RBBM_PERFCTR_UCHE_10_LO"/>
1249         <reg32 offset="0x048b" name="RBBM_PERFCTR_UCHE_10_HI"/>
1250         <reg32 offset="0x048c" name="RBBM_PERFCTR_UCHE_11_LO"/>
1251         <reg32 offset="0x048d" name="RBBM_PERFCTR_UCHE_11_HI"/>
1252         <reg32 offset="0x048e" name="RBBM_PERFCTR_TP_0_LO"/>
1253         <reg32 offset="0x048f" name="RBBM_PERFCTR_TP_0_HI"/>
1254         <reg32 offset="0x0490" name="RBBM_PERFCTR_TP_1_LO"/>
1255         <reg32 offset="0x0491" name="RBBM_PERFCTR_TP_1_HI"/>
1256         <reg32 offset="0x0492" name="RBBM_PERFCTR_TP_2_LO"/>
1257         <reg32 offset="0x0493" name="RBBM_PERFCTR_TP_2_HI"/>
1258         <reg32 offset="0x0494" name="RBBM_PERFCTR_TP_3_LO"/>
1259         <reg32 offset="0x0495" name="RBBM_PERFCTR_TP_3_HI"/>
1260         <reg32 offset="0x0496" name="RBBM_PERFCTR_TP_4_LO"/>
1261         <reg32 offset="0x0497" name="RBBM_PERFCTR_TP_4_HI"/>
1262         <reg32 offset="0x0498" name="RBBM_PERFCTR_TP_5_LO"/>
1263         <reg32 offset="0x0499" name="RBBM_PERFCTR_TP_5_HI"/>
1264         <reg32 offset="0x049a" name="RBBM_PERFCTR_TP_6_LO"/>
1265         <reg32 offset="0x049b" name="RBBM_PERFCTR_TP_6_HI"/>
1266         <reg32 offset="0x049c" name="RBBM_PERFCTR_TP_7_LO"/>
1267         <reg32 offset="0x049d" name="RBBM_PERFCTR_TP_7_HI"/>
1268         <reg32 offset="0x049e" name="RBBM_PERFCTR_TP_8_LO"/>
1269         <reg32 offset="0x049f" name="RBBM_PERFCTR_TP_8_HI"/>
1270         <reg32 offset="0x04a0" name="RBBM_PERFCTR_TP_9_LO"/>
1271         <reg32 offset="0x04a1" name="RBBM_PERFCTR_TP_9_HI"/>
1272         <reg32 offset="0x04a2" name="RBBM_PERFCTR_TP_10_LO"/>
1273         <reg32 offset="0x04a3" name="RBBM_PERFCTR_TP_10_HI"/>
1274         <reg32 offset="0x04a4" name="RBBM_PERFCTR_TP_11_LO"/>
1275         <reg32 offset="0x04a5" name="RBBM_PERFCTR_TP_11_HI"/>
1276         <reg32 offset="0x04a6" name="RBBM_PERFCTR_SP_0_LO"/>
1277         <reg32 offset="0x04a7" name="RBBM_PERFCTR_SP_0_HI"/>
1278         <reg32 offset="0x04a8" name="RBBM_PERFCTR_SP_1_LO"/>
1279         <reg32 offset="0x04a9" name="RBBM_PERFCTR_SP_1_HI"/>
1280         <reg32 offset="0x04aa" name="RBBM_PERFCTR_SP_2_LO"/>
1281         <reg32 offset="0x04ab" name="RBBM_PERFCTR_SP_2_HI"/>
1282         <reg32 offset="0x04ac" name="RBBM_PERFCTR_SP_3_LO"/>
1283         <reg32 offset="0x04ad" name="RBBM_PERFCTR_SP_3_HI"/>
1284         <reg32 offset="0x04ae" name="RBBM_PERFCTR_SP_4_LO"/>
1285         <reg32 offset="0x04af" name="RBBM_PERFCTR_SP_4_HI"/>
1286         <reg32 offset="0x04b0" name="RBBM_PERFCTR_SP_5_LO"/>
1287         <reg32 offset="0x04b1" name="RBBM_PERFCTR_SP_5_HI"/>
1288         <reg32 offset="0x04b2" name="RBBM_PERFCTR_SP_6_LO"/>
1289         <reg32 offset="0x04b3" name="RBBM_PERFCTR_SP_6_HI"/>
1290         <reg32 offset="0x04b4" name="RBBM_PERFCTR_SP_7_LO"/>
1291         <reg32 offset="0x04b5" name="RBBM_PERFCTR_SP_7_HI"/>
1292         <reg32 offset="0x04b6" name="RBBM_PERFCTR_SP_8_LO"/>
1293         <reg32 offset="0x04b7" name="RBBM_PERFCTR_SP_8_HI"/>
1294         <reg32 offset="0x04b8" name="RBBM_PERFCTR_SP_9_LO"/>
1295         <reg32 offset="0x04b9" name="RBBM_PERFCTR_SP_9_HI"/>
1296         <reg32 offset="0x04ba" name="RBBM_PERFCTR_SP_10_LO"/>
1297         <reg32 offset="0x04bb" name="RBBM_PERFCTR_SP_10_HI"/>
1298         <reg32 offset="0x04bc" name="RBBM_PERFCTR_SP_11_LO"/>
1299         <reg32 offset="0x04bd" name="RBBM_PERFCTR_SP_11_HI"/>
1300         <reg32 offset="0x04be" name="RBBM_PERFCTR_SP_12_LO"/>
1301         <reg32 offset="0x04bf" name="RBBM_PERFCTR_SP_12_HI"/>
1302         <reg32 offset="0x04c0" name="RBBM_PERFCTR_SP_13_LO"/>
1303         <reg32 offset="0x04c1" name="RBBM_PERFCTR_SP_13_HI"/>
1304         <reg32 offset="0x04c2" name="RBBM_PERFCTR_SP_14_LO"/>
1305         <reg32 offset="0x04c3" name="RBBM_PERFCTR_SP_14_HI"/>
1306         <reg32 offset="0x04c4" name="RBBM_PERFCTR_SP_15_LO"/>
1307         <reg32 offset="0x04c5" name="RBBM_PERFCTR_SP_15_HI"/>
1308         <reg32 offset="0x04c6" name="RBBM_PERFCTR_SP_16_LO"/>
1309         <reg32 offset="0x04c7" name="RBBM_PERFCTR_SP_16_HI"/>
1310         <reg32 offset="0x04c8" name="RBBM_PERFCTR_SP_17_LO"/>
1311         <reg32 offset="0x04c9" name="RBBM_PERFCTR_SP_17_HI"/>
1312         <reg32 offset="0x04ca" name="RBBM_PERFCTR_SP_18_LO"/>
1313         <reg32 offset="0x04cb" name="RBBM_PERFCTR_SP_18_HI"/>
1314         <reg32 offset="0x04cc" name="RBBM_PERFCTR_SP_19_LO"/>
1315         <reg32 offset="0x04cd" name="RBBM_PERFCTR_SP_19_HI"/>
1316         <reg32 offset="0x04ce" name="RBBM_PERFCTR_SP_20_LO"/>
1317         <reg32 offset="0x04cf" name="RBBM_PERFCTR_SP_20_HI"/>
1318         <reg32 offset="0x04d0" name="RBBM_PERFCTR_SP_21_LO"/>
1319         <reg32 offset="0x04d1" name="RBBM_PERFCTR_SP_21_HI"/>
1320         <reg32 offset="0x04d2" name="RBBM_PERFCTR_SP_22_LO"/>
1321         <reg32 offset="0x04d3" name="RBBM_PERFCTR_SP_22_HI"/>
1322         <reg32 offset="0x04d4" name="RBBM_PERFCTR_SP_23_LO"/>
1323         <reg32 offset="0x04d5" name="RBBM_PERFCTR_SP_23_HI"/>
1324         <reg32 offset="0x04d6" name="RBBM_PERFCTR_RB_0_LO"/>
1325         <reg32 offset="0x04d7" name="RBBM_PERFCTR_RB_0_HI"/>
1326         <reg32 offset="0x04d8" name="RBBM_PERFCTR_RB_1_LO"/>
1327         <reg32 offset="0x04d9" name="RBBM_PERFCTR_RB_1_HI"/>
1328         <reg32 offset="0x04da" name="RBBM_PERFCTR_RB_2_LO"/>
1329         <reg32 offset="0x04db" name="RBBM_PERFCTR_RB_2_HI"/>
1330         <reg32 offset="0x04dc" name="RBBM_PERFCTR_RB_3_LO"/>
1331         <reg32 offset="0x04dd" name="RBBM_PERFCTR_RB_3_HI"/>
1332         <reg32 offset="0x04de" name="RBBM_PERFCTR_RB_4_LO"/>
1333         <reg32 offset="0x04df" name="RBBM_PERFCTR_RB_4_HI"/>
1334         <reg32 offset="0x04e0" name="RBBM_PERFCTR_RB_5_LO"/>
1335         <reg32 offset="0x04e1" name="RBBM_PERFCTR_RB_5_HI"/>
1336         <reg32 offset="0x04e2" name="RBBM_PERFCTR_RB_6_LO"/>
1337         <reg32 offset="0x04e3" name="RBBM_PERFCTR_RB_6_HI"/>
1338         <reg32 offset="0x04e4" name="RBBM_PERFCTR_RB_7_LO"/>
1339         <reg32 offset="0x04e5" name="RBBM_PERFCTR_RB_7_HI"/>
1340         <reg32 offset="0x04e6" name="RBBM_PERFCTR_VSC_0_LO"/>
1341         <reg32 offset="0x04e7" name="RBBM_PERFCTR_VSC_0_HI"/>
1342         <reg32 offset="0x04e8" name="RBBM_PERFCTR_VSC_1_LO"/>
1343         <reg32 offset="0x04e9" name="RBBM_PERFCTR_VSC_1_HI"/>
1344         <reg32 offset="0x04ea" name="RBBM_PERFCTR_LRZ_0_LO"/>
1345         <reg32 offset="0x04eb" name="RBBM_PERFCTR_LRZ_0_HI"/>
1346         <reg32 offset="0x04ec" name="RBBM_PERFCTR_LRZ_1_LO"/>
1347         <reg32 offset="0x04ed" name="RBBM_PERFCTR_LRZ_1_HI"/>
1348         <reg32 offset="0x04ee" name="RBBM_PERFCTR_LRZ_2_LO"/>
1349         <reg32 offset="0x04ef" name="RBBM_PERFCTR_LRZ_2_HI"/>
1350         <reg32 offset="0x04f0" name="RBBM_PERFCTR_LRZ_3_LO"/>
1351         <reg32 offset="0x04f1" name="RBBM_PERFCTR_LRZ_3_HI"/>
1352         <reg32 offset="0x04f2" name="RBBM_PERFCTR_CMP_0_LO"/>
1353         <reg32 offset="0x04f3" name="RBBM_PERFCTR_CMP_0_HI"/>
1354         <reg32 offset="0x04f4" name="RBBM_PERFCTR_CMP_1_LO"/>
1355         <reg32 offset="0x04f5" name="RBBM_PERFCTR_CMP_1_HI"/>
1356         <reg32 offset="0x04f6" name="RBBM_PERFCTR_CMP_2_LO"/>
1357         <reg32 offset="0x04f7" name="RBBM_PERFCTR_CMP_2_HI"/>
1358         <reg32 offset="0x04f8" name="RBBM_PERFCTR_CMP_3_LO"/>
1359         <reg32 offset="0x04f9" name="RBBM_PERFCTR_CMP_3_HI"/>
1360         <reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL"/>
1361         <reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0"/>
1362         <reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1"/>
1363         <reg32 offset="0x0503" name="RBBM_PERFCTR_LOAD_CMD2"/>
1364         <reg32 offset="0x0504" name="RBBM_PERFCTR_LOAD_CMD3"/>
1365         <reg32 offset="0x0505" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
1366         <reg32 offset="0x0506" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
1367         <reg32 offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL_0"/>
1368         <reg32 offset="0x0508" name="RBBM_PERFCTR_RBBM_SEL_1"/>
1369         <reg32 offset="0x0509" name="RBBM_PERFCTR_RBBM_SEL_2"/>
1370         <reg32 offset="0x050A" name="RBBM_PERFCTR_RBBM_SEL_3"/>
1371         <reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
1372         <reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
1373         <reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/>
1374         <reg32 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE_LO"/>
1375         <reg32 offset="0xF801" name="RBBM_SECVID_TSB_TRUSTED_BASE_HI"/>
1376         <reg32 offset="0xF802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/>
1377         <reg32 offset="0xF803" name="RBBM_SECVID_TSB_CNTL"/>
1378         <reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL"/>
1379         <reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL"/>
1380         <reg32 offset="0x0001f" name="RBBM_INTERFACE_HANG_INT_CNTL"/>
1381         <reg32 offset="0x00037" name="RBBM_INT_CLEAR_CMD"/>
1382         <reg32 offset="0x00038" name="RBBM_INT_0_MASK"/>
1383         <reg32 offset="0x00042" name="RBBM_SP_HYST_CNT"/>
1384         <reg32 offset="0x00043" name="RBBM_SW_RESET_CMD"/>
1385         <reg32 offset="0x00044" name="RBBM_RAC_THRESHOLD_CNT"/>
1386         <reg32 offset="0x00045" name="RBBM_BLOCK_SW_RESET_CMD"/>
1387         <reg32 offset="0x00046" name="RBBM_BLOCK_SW_RESET_CMD2"/>
1388         <reg32 offset="0x000ae" name="RBBM_CLOCK_CNTL"/>
1389         <reg32 offset="0x000b0" name="RBBM_CLOCK_CNTL_SP0"/>
1390         <reg32 offset="0x000b1" name="RBBM_CLOCK_CNTL_SP1"/>
1391         <reg32 offset="0x000b2" name="RBBM_CLOCK_CNTL_SP2"/>
1392         <reg32 offset="0x000b3" name="RBBM_CLOCK_CNTL_SP3"/>
1393         <reg32 offset="0x000b4" name="RBBM_CLOCK_CNTL2_SP0"/>
1394         <reg32 offset="0x000b5" name="RBBM_CLOCK_CNTL2_SP1"/>
1395         <reg32 offset="0x000b6" name="RBBM_CLOCK_CNTL2_SP2"/>
1396         <reg32 offset="0x000b7" name="RBBM_CLOCK_CNTL2_SP3"/>
1397         <reg32 offset="0x000b8" name="RBBM_CLOCK_DELAY_SP0"/>
1398         <reg32 offset="0x000b9" name="RBBM_CLOCK_DELAY_SP1"/>
1399         <reg32 offset="0x000ba" name="RBBM_CLOCK_DELAY_SP2"/>
1400         <reg32 offset="0x000bb" name="RBBM_CLOCK_DELAY_SP3"/>
1401         <reg32 offset="0x000bc" name="RBBM_CLOCK_HYST_SP0"/>
1402         <reg32 offset="0x000bd" name="RBBM_CLOCK_HYST_SP1"/>
1403         <reg32 offset="0x000be" name="RBBM_CLOCK_HYST_SP2"/>
1404         <reg32 offset="0x000bf" name="RBBM_CLOCK_HYST_SP3"/>
1405         <reg32 offset="0x000c0" name="RBBM_CLOCK_CNTL_TP0"/>
1406         <reg32 offset="0x000c1" name="RBBM_CLOCK_CNTL_TP1"/>
1407         <reg32 offset="0x000c2" name="RBBM_CLOCK_CNTL_TP2"/>
1408         <reg32 offset="0x000c3" name="RBBM_CLOCK_CNTL_TP3"/>
1409         <reg32 offset="0x000c4" name="RBBM_CLOCK_CNTL2_TP0"/>
1410         <reg32 offset="0x000c5" name="RBBM_CLOCK_CNTL2_TP1"/>
1411         <reg32 offset="0x000c6" name="RBBM_CLOCK_CNTL2_TP2"/>
1412         <reg32 offset="0x000c7" name="RBBM_CLOCK_CNTL2_TP3"/>
1413         <reg32 offset="0x000c8" name="RBBM_CLOCK_CNTL3_TP0"/>
1414         <reg32 offset="0x000c9" name="RBBM_CLOCK_CNTL3_TP1"/>
1415         <reg32 offset="0x000ca" name="RBBM_CLOCK_CNTL3_TP2"/>
1416         <reg32 offset="0x000cb" name="RBBM_CLOCK_CNTL3_TP3"/>
1417         <reg32 offset="0x000cc" name="RBBM_CLOCK_CNTL4_TP0"/>
1418         <reg32 offset="0x000cd" name="RBBM_CLOCK_CNTL4_TP1"/>
1419         <reg32 offset="0x000ce" name="RBBM_CLOCK_CNTL4_TP2"/>
1420         <reg32 offset="0x000cf" name="RBBM_CLOCK_CNTL4_TP3"/>
1421         <reg32 offset="0x000d0" name="RBBM_CLOCK_DELAY_TP0"/>
1422         <reg32 offset="0x000d1" name="RBBM_CLOCK_DELAY_TP1"/>
1423         <reg32 offset="0x000d2" name="RBBM_CLOCK_DELAY_TP2"/>
1424         <reg32 offset="0x000d3" name="RBBM_CLOCK_DELAY_TP3"/>
1425         <reg32 offset="0x000d4" name="RBBM_CLOCK_DELAY2_TP0"/>
1426         <reg32 offset="0x000d5" name="RBBM_CLOCK_DELAY2_TP1"/>
1427         <reg32 offset="0x000d6" name="RBBM_CLOCK_DELAY2_TP2"/>
1428         <reg32 offset="0x000d7" name="RBBM_CLOCK_DELAY2_TP3"/>
1429         <reg32 offset="0x000d8" name="RBBM_CLOCK_DELAY3_TP0"/>
1430         <reg32 offset="0x000d9" name="RBBM_CLOCK_DELAY3_TP1"/>
1431         <reg32 offset="0x000da" name="RBBM_CLOCK_DELAY3_TP2"/>
1432         <reg32 offset="0x000db" name="RBBM_CLOCK_DELAY3_TP3"/>
1433         <reg32 offset="0x000dc" name="RBBM_CLOCK_DELAY4_TP0"/>
1434         <reg32 offset="0x000dd" name="RBBM_CLOCK_DELAY4_TP1"/>
1435         <reg32 offset="0x000de" name="RBBM_CLOCK_DELAY4_TP2"/>
1436         <reg32 offset="0x000df" name="RBBM_CLOCK_DELAY4_TP3"/>
1437         <reg32 offset="0x000e0" name="RBBM_CLOCK_HYST_TP0"/>
1438         <reg32 offset="0x000e1" name="RBBM_CLOCK_HYST_TP1"/>
1439         <reg32 offset="0x000e2" name="RBBM_CLOCK_HYST_TP2"/>
1440         <reg32 offset="0x000e3" name="RBBM_CLOCK_HYST_TP3"/>
1441         <reg32 offset="0x000e4" name="RBBM_CLOCK_HYST2_TP0"/>
1442         <reg32 offset="0x000e5" name="RBBM_CLOCK_HYST2_TP1"/>
1443         <reg32 offset="0x000e6" name="RBBM_CLOCK_HYST2_TP2"/>
1444         <reg32 offset="0x000e7" name="RBBM_CLOCK_HYST2_TP3"/>
1445         <reg32 offset="0x000e8" name="RBBM_CLOCK_HYST3_TP0"/>
1446         <reg32 offset="0x000e9" name="RBBM_CLOCK_HYST3_TP1"/>
1447         <reg32 offset="0x000ea" name="RBBM_CLOCK_HYST3_TP2"/>
1448         <reg32 offset="0x000eb" name="RBBM_CLOCK_HYST3_TP3"/>
1449         <reg32 offset="0x000ec" name="RBBM_CLOCK_HYST4_TP0"/>
1450         <reg32 offset="0x000ed" name="RBBM_CLOCK_HYST4_TP1"/>
1451         <reg32 offset="0x000ee" name="RBBM_CLOCK_HYST4_TP2"/>
1452         <reg32 offset="0x000ef" name="RBBM_CLOCK_HYST4_TP3"/>
1453         <reg32 offset="0x000f0" name="RBBM_CLOCK_CNTL_RB0"/>
1454         <reg32 offset="0x000f1" name="RBBM_CLOCK_CNTL_RB1"/>
1455         <reg32 offset="0x000f2" name="RBBM_CLOCK_CNTL_RB2"/>
1456         <reg32 offset="0x000f3" name="RBBM_CLOCK_CNTL_RB3"/>
1457         <reg32 offset="0x000f4" name="RBBM_CLOCK_CNTL2_RB0"/>
1458         <reg32 offset="0x000f5" name="RBBM_CLOCK_CNTL2_RB1"/>
1459         <reg32 offset="0x000f6" name="RBBM_CLOCK_CNTL2_RB2"/>
1460         <reg32 offset="0x000f7" name="RBBM_CLOCK_CNTL2_RB3"/>
1461         <reg32 offset="0x000f8" name="RBBM_CLOCK_CNTL_CCU0"/>
1462         <reg32 offset="0x000f9" name="RBBM_CLOCK_CNTL_CCU1"/>
1463         <reg32 offset="0x000fa" name="RBBM_CLOCK_CNTL_CCU2"/>
1464         <reg32 offset="0x000fb" name="RBBM_CLOCK_CNTL_CCU3"/>
1465         <reg32 offset="0x00100" name="RBBM_CLOCK_HYST_RB_CCU0"/>
1466         <reg32 offset="0x00101" name="RBBM_CLOCK_HYST_RB_CCU1"/>
1467         <reg32 offset="0x00102" name="RBBM_CLOCK_HYST_RB_CCU2"/>
1468         <reg32 offset="0x00103" name="RBBM_CLOCK_HYST_RB_CCU3"/>
1469         <reg32 offset="0x00104" name="RBBM_CLOCK_CNTL_RAC"/>
1470         <reg32 offset="0x00105" name="RBBM_CLOCK_CNTL2_RAC"/>
1471         <reg32 offset="0x00106" name="RBBM_CLOCK_DELAY_RAC"/>
1472         <reg32 offset="0x00107" name="RBBM_CLOCK_HYST_RAC"/>
1473         <reg32 offset="0x00108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/>
1474         <reg32 offset="0x00109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
1475         <reg32 offset="0x0010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
1476         <reg32 offset="0x0010b" name="RBBM_CLOCK_CNTL_UCHE"/>
1477         <reg32 offset="0x0010c" name="RBBM_CLOCK_CNTL2_UCHE"/>
1478         <reg32 offset="0x0010d" name="RBBM_CLOCK_CNTL3_UCHE"/>
1479         <reg32 offset="0x0010e" name="RBBM_CLOCK_CNTL4_UCHE"/>
1480         <reg32 offset="0x0010f" name="RBBM_CLOCK_DELAY_UCHE"/>
1481         <reg32 offset="0x00110" name="RBBM_CLOCK_HYST_UCHE"/>
1482         <reg32 offset="0x00111" name="RBBM_CLOCK_MODE_VFD"/>
1483         <reg32 offset="0x00112" name="RBBM_CLOCK_DELAY_VFD"/>
1484         <reg32 offset="0x00113" name="RBBM_CLOCK_HYST_VFD"/>
1485         <reg32 offset="0x00114" name="RBBM_CLOCK_MODE_GPC"/>
1486         <reg32 offset="0x00115" name="RBBM_CLOCK_DELAY_GPC"/>
1487         <reg32 offset="0x00116" name="RBBM_CLOCK_HYST_GPC"/>
1488         <reg32 offset="0x00117" name="RBBM_CLOCK_DELAY_HLSQ_2"/>
1489         <reg32 offset="0x00118" name="RBBM_CLOCK_CNTL_GMU_GX"/>
1490         <reg32 offset="0x00119" name="RBBM_CLOCK_DELAY_GMU_GX"/>
1491         <reg32 offset="0x0011a" name="RBBM_CLOCK_HYST_GMU_GX"/>
1492         <reg32 offset="0x0011b" name="RBBM_CLOCK_MODE_HLSQ"/>
1493         <reg32 offset="0x0011c" name="RBBM_CLOCK_DELAY_HLSQ"/>
1494         <reg32 offset="0x0600" name="DBGC_CFG_DBGBUS_SEL_A"/>
1495         <reg32 offset="0x0601" name="DBGC_CFG_DBGBUS_SEL_B"/>
1496         <reg32 offset="0x0602" name="DBGC_CFG_DBGBUS_SEL_C"/>
1497         <reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D">
1498                 <bitfield high="7" low="0" name="PING_INDEX"/>
1499                 <bitfield high="15" low="8" name="PING_BLK_SEL"/>
1500         </reg32>
1501         <reg32 offset="0x0604" name="DBGC_CFG_DBGBUS_CNTLT">
1502                 <bitfield high="5" low="0" name="TRACEEN"/>
1503                 <bitfield high="14" low="12" name="GRANU"/>
1504                 <bitfield high="31" low="28" name="SEGT"/>
1505         </reg32>
1506         <reg32 offset="0x0605" name="DBGC_CFG_DBGBUS_CNTLM">
1507                 <bitfield high="27" low="24" name="ENABLE"/>
1508         </reg32>
1509         <reg32 offset="0x0608" name="DBGC_CFG_DBGBUS_IVTL_0"/>
1510         <reg32 offset="0x0609" name="DBGC_CFG_DBGBUS_IVTL_1"/>
1511         <reg32 offset="0x060a" name="DBGC_CFG_DBGBUS_IVTL_2"/>
1512         <reg32 offset="0x060b" name="DBGC_CFG_DBGBUS_IVTL_3"/>
1513         <reg32 offset="0x060c" name="DBGC_CFG_DBGBUS_MASKL_0"/>
1514         <reg32 offset="0x060d" name="DBGC_CFG_DBGBUS_MASKL_1"/>
1515         <reg32 offset="0x060e" name="DBGC_CFG_DBGBUS_MASKL_2"/>
1516         <reg32 offset="0x060f" name="DBGC_CFG_DBGBUS_MASKL_3"/>
1517         <reg32 offset="0x0610" name="DBGC_CFG_DBGBUS_BYTEL_0">
1518                 <bitfield high="3" low="0" name="BYTEL0"/>
1519                 <bitfield high="7" low="4" name="BYTEL1"/>
1520                 <bitfield high="11" low="8" name="BYTEL2"/>
1521                 <bitfield high="15" low="12" name="BYTEL3"/>
1522                 <bitfield high="19" low="16" name="BYTEL4"/>
1523                 <bitfield high="23" low="20" name="BYTEL5"/>
1524                 <bitfield high="27" low="24" name="BYTEL6"/>
1525                 <bitfield high="31" low="28" name="BYTEL7"/>
1526         </reg32>
1527         <reg32 offset="0x0611" name="DBGC_CFG_DBGBUS_BYTEL_1">
1528                 <bitfield high="3" low="0" name="BYTEL8"/>
1529                 <bitfield high="7" low="4" name="BYTEL9"/>
1530                 <bitfield high="11" low="8" name="BYTEL10"/>
1531                 <bitfield high="15" low="12" name="BYTEL11"/>
1532                 <bitfield high="19" low="16" name="BYTEL12"/>
1533                 <bitfield high="23" low="20" name="BYTEL13"/>
1534                 <bitfield high="27" low="24" name="BYTEL14"/>
1535                 <bitfield high="31" low="28" name="BYTEL15"/>
1536         </reg32>
1537         <reg32 offset="0x062f" name="DBGC_CFG_DBGBUS_TRACE_BUF1"/>
1538         <reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/>
1539         <reg32 offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL_0"/>
1540         <reg32 offset="0x0CD9" name="VSC_PERFCTR_VSC_SEL_1"/>
1541         <reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL"/>
1542         <reg32 offset="0x8610" name="GRAS_PERFCTR_TSE_SEL_0"/>
1543         <reg32 offset="0x8611" name="GRAS_PERFCTR_TSE_SEL_1"/>
1544         <reg32 offset="0x8612" name="GRAS_PERFCTR_TSE_SEL_2"/>
1545         <reg32 offset="0x8613" name="GRAS_PERFCTR_TSE_SEL_3"/>
1546         <reg32 offset="0x8614" name="GRAS_PERFCTR_RAS_SEL_0"/>
1547         <reg32 offset="0x8615" name="GRAS_PERFCTR_RAS_SEL_1"/>
1548         <reg32 offset="0x8616" name="GRAS_PERFCTR_RAS_SEL_2"/>
1549         <reg32 offset="0x8617" name="GRAS_PERFCTR_RAS_SEL_3"/>
1550         <reg32 offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL_0"/>
1551         <reg32 offset="0x8619" name="GRAS_PERFCTR_LRZ_SEL_1"/>
1552         <reg32 offset="0x861A" name="GRAS_PERFCTR_LRZ_SEL_2"/>
1553         <reg32 offset="0x861B" name="GRAS_PERFCTR_LRZ_SEL_3"/>
1554         <reg32 offset="0x8E05" name="RB_ADDR_MODE_CNTL"/>
1555         <reg32 offset="0x8E08" name="RB_NC_MODE_CNTL"/>
1556         <reg32 offset="0x8E10" name="RB_PERFCTR_RB_SEL_0"/>
1557         <reg32 offset="0x8E11" name="RB_PERFCTR_RB_SEL_1"/>
1558         <reg32 offset="0x8E12" name="RB_PERFCTR_RB_SEL_2"/>
1559         <reg32 offset="0x8E13" name="RB_PERFCTR_RB_SEL_3"/>
1560         <reg32 offset="0x8E14" name="RB_PERFCTR_RB_SEL_4"/>
1561         <reg32 offset="0x8E15" name="RB_PERFCTR_RB_SEL_5"/>
1562         <reg32 offset="0x8E16" name="RB_PERFCTR_RB_SEL_6"/>
1563         <reg32 offset="0x8E17" name="RB_PERFCTR_RB_SEL_7"/>
1564         <reg32 offset="0x8E18" name="RB_PERFCTR_CCU_SEL_0"/>
1565         <reg32 offset="0x8E19" name="RB_PERFCTR_CCU_SEL_1"/>
1566         <reg32 offset="0x8E1A" name="RB_PERFCTR_CCU_SEL_2"/>
1567         <reg32 offset="0x8E1B" name="RB_PERFCTR_CCU_SEL_3"/>
1568         <reg32 offset="0x8E1C" name="RB_PERFCTR_CCU_SEL_4"/>
1569         <reg32 offset="0x8E2C" name="RB_PERFCTR_CMP_SEL_0"/>
1570         <reg32 offset="0x8E2D" name="RB_PERFCTR_CMP_SEL_1"/>
1571         <reg32 offset="0x8E2E" name="RB_PERFCTR_CMP_SEL_2"/>
1572         <reg32 offset="0x8E2F" name="RB_PERFCTR_CMP_SEL_3"/>
1573         <reg32 offset="0x8E3D" name="RB_RB_SUB_BLOCK_SEL_CNTL_CD"/>
1574         <reg32 offset="0x8E50" name="RB_CONTEXT_SWITCH_GMEM_SAVE_RESTORE"/>
1575         <reg32 offset="0x9E00" name="PC_DBG_ECO_CNTL"/>
1576         <reg32 offset="0x9E01" name="PC_ADDR_MODE_CNTL"/>
1577         <reg32 offset="0x9E34" name="PC_PERFCTR_PC_SEL_0"/>
1578         <reg32 offset="0x9E35" name="PC_PERFCTR_PC_SEL_1"/>
1579         <reg32 offset="0x9E36" name="PC_PERFCTR_PC_SEL_2"/>
1580         <reg32 offset="0x9E37" name="PC_PERFCTR_PC_SEL_3"/>
1581         <reg32 offset="0x9E38" name="PC_PERFCTR_PC_SEL_4"/>
1582         <reg32 offset="0x9E39" name="PC_PERFCTR_PC_SEL_5"/>
1583         <reg32 offset="0x9E3A" name="PC_PERFCTR_PC_SEL_6"/>
1584         <reg32 offset="0x9E3B" name="PC_PERFCTR_PC_SEL_7"/>
1585         <reg32 offset="0xBE05" name="HLSQ_ADDR_MODE_CNTL"/>
1586         <reg32 offset="0xBE10" name="HLSQ_PERFCTR_HLSQ_SEL_0"/>
1587         <reg32 offset="0xBE11" name="HLSQ_PERFCTR_HLSQ_SEL_1"/>
1588         <reg32 offset="0xBE12" name="HLSQ_PERFCTR_HLSQ_SEL_2"/>
1589         <reg32 offset="0xBE13" name="HLSQ_PERFCTR_HLSQ_SEL_3"/>
1590         <reg32 offset="0xBE14" name="HLSQ_PERFCTR_HLSQ_SEL_4"/>
1591         <reg32 offset="0xBE15" name="HLSQ_PERFCTR_HLSQ_SEL_5"/>
1592         <reg32 offset="0xC800" name="HLSQ_DBG_AHB_READ_APERTURE"/>
1593         <reg32 offset="0xD000" name="HLSQ_DBG_READ_SEL"/>
1594         <reg32 offset="0xA601" name="VFD_ADDR_MODE_CNTL"/>
1595         <reg32 offset="0xA610" name="VFD_PERFCTR_VFD_SEL_0"/>
1596         <reg32 offset="0xA611" name="VFD_PERFCTR_VFD_SEL_1"/>
1597         <reg32 offset="0xA612" name="VFD_PERFCTR_VFD_SEL_2"/>
1598         <reg32 offset="0xA613" name="VFD_PERFCTR_VFD_SEL_3"/>
1599         <reg32 offset="0xA614" name="VFD_PERFCTR_VFD_SEL_4"/>
1600         <reg32 offset="0xA615" name="VFD_PERFCTR_VFD_SEL_5"/>
1601         <reg32 offset="0xA616" name="VFD_PERFCTR_VFD_SEL_6"/>
1602         <reg32 offset="0xA617" name="VFD_PERFCTR_VFD_SEL_7"/>
1603         <reg32 offset="0x9601" name="VPC_ADDR_MODE_CNTL"/>
1604         <reg32 offset="0x9604" name="VPC_PERFCTR_VPC_SEL_0"/>
1605         <reg32 offset="0x9605" name="VPC_PERFCTR_VPC_SEL_1"/>
1606         <reg32 offset="0x9606" name="VPC_PERFCTR_VPC_SEL_2"/>
1607         <reg32 offset="0x9607" name="VPC_PERFCTR_VPC_SEL_3"/>
1608         <reg32 offset="0x9608" name="VPC_PERFCTR_VPC_SEL_4"/>
1609         <reg32 offset="0x9609" name="VPC_PERFCTR_VPC_SEL_5"/>
1610         <reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL"/>
1611         <reg32 offset="0x0E01" name="UCHE_MODE_CNTL"/>
1612         <reg32 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX_LO"/>
1613         <reg32 offset="0x0E06" name="UCHE_WRITE_RANGE_MAX_HI"/>
1614         <reg32 offset="0x0E07" name="UCHE_WRITE_THRU_BASE_LO"/>
1615         <reg32 offset="0x0E08" name="UCHE_WRITE_THRU_BASE_HI"/>
1616         <reg32 offset="0x0E09" name="UCHE_TRAP_BASE_LO"/>
1617         <reg32 offset="0x0E0A" name="UCHE_TRAP_BASE_HI"/>
1618         <reg32 offset="0x0E0B" name="UCHE_GMEM_RANGE_MIN_LO"/>
1619         <reg32 offset="0x0E0C" name="UCHE_GMEM_RANGE_MIN_HI"/>
1620         <reg32 offset="0x0E0D" name="UCHE_GMEM_RANGE_MAX_LO"/>
1621         <reg32 offset="0x0E0E" name="UCHE_GMEM_RANGE_MAX_HI"/>
1622         <reg32 offset="0x0E17" name="UCHE_CACHE_WAYS"/>
1623         <reg32 offset="0x0E18" name="UCHE_FILTER_CNTL"/>
1624         <reg32 offset="0x0E19" name="UCHE_CLIENT_PF">
1625                 <bitfield high="7" low="0" name="PERFSEL"/>
1626         </reg32>
1627         <reg32 offset="0x0E1C" name="UCHE_PERFCTR_UCHE_SEL_0"/>
1628         <reg32 offset="0x0E1D" name="UCHE_PERFCTR_UCHE_SEL_1"/>
1629         <reg32 offset="0x0E1E" name="UCHE_PERFCTR_UCHE_SEL_2"/>
1630         <reg32 offset="0x0E1F" name="UCHE_PERFCTR_UCHE_SEL_3"/>
1631         <reg32 offset="0x0E20" name="UCHE_PERFCTR_UCHE_SEL_4"/>
1632         <reg32 offset="0x0E21" name="UCHE_PERFCTR_UCHE_SEL_5"/>
1633         <reg32 offset="0x0E22" name="UCHE_PERFCTR_UCHE_SEL_6"/>
1634         <reg32 offset="0x0E23" name="UCHE_PERFCTR_UCHE_SEL_7"/>
1635         <reg32 offset="0x0E24" name="UCHE_PERFCTR_UCHE_SEL_8"/>
1636         <reg32 offset="0x0E25" name="UCHE_PERFCTR_UCHE_SEL_9"/>
1637         <reg32 offset="0x0E26" name="UCHE_PERFCTR_UCHE_SEL_10"/>
1638         <reg32 offset="0x0E27" name="UCHE_PERFCTR_UCHE_SEL_11"/>
1639         <reg32 offset="0xAE01" name="SP_ADDR_MODE_CNTL"/>
1640         <reg32 offset="0xAE02" name="SP_NC_MODE_CNTL"/>
1641         <reg32 offset="0xAE10" name="SP_PERFCTR_SP_SEL_0"/>
1642         <reg32 offset="0xAE11" name="SP_PERFCTR_SP_SEL_1"/>
1643         <reg32 offset="0xAE12" name="SP_PERFCTR_SP_SEL_2"/>
1644         <reg32 offset="0xAE13" name="SP_PERFCTR_SP_SEL_3"/>
1645         <reg32 offset="0xAE14" name="SP_PERFCTR_SP_SEL_4"/>
1646         <reg32 offset="0xAE15" name="SP_PERFCTR_SP_SEL_5"/>
1647         <reg32 offset="0xAE16" name="SP_PERFCTR_SP_SEL_6"/>
1648         <reg32 offset="0xAE17" name="SP_PERFCTR_SP_SEL_7"/>
1649         <reg32 offset="0xAE18" name="SP_PERFCTR_SP_SEL_8"/>
1650         <reg32 offset="0xAE19" name="SP_PERFCTR_SP_SEL_9"/>
1651         <reg32 offset="0xAE1A" name="SP_PERFCTR_SP_SEL_10"/>
1652         <reg32 offset="0xAE1B" name="SP_PERFCTR_SP_SEL_11"/>
1653         <reg32 offset="0xAE1C" name="SP_PERFCTR_SP_SEL_12"/>
1654         <reg32 offset="0xAE1D" name="SP_PERFCTR_SP_SEL_13"/>
1655         <reg32 offset="0xAE1E" name="SP_PERFCTR_SP_SEL_14"/>
1656         <reg32 offset="0xAE1F" name="SP_PERFCTR_SP_SEL_15"/>
1657         <reg32 offset="0xAE20" name="SP_PERFCTR_SP_SEL_16"/>
1658         <reg32 offset="0xAE21" name="SP_PERFCTR_SP_SEL_17"/>
1659         <reg32 offset="0xAE22" name="SP_PERFCTR_SP_SEL_18"/>
1660         <reg32 offset="0xAE23" name="SP_PERFCTR_SP_SEL_19"/>
1661         <reg32 offset="0xAE24" name="SP_PERFCTR_SP_SEL_20"/>
1662         <reg32 offset="0xAE25" name="SP_PERFCTR_SP_SEL_21"/>
1663         <reg32 offset="0xAE26" name="SP_PERFCTR_SP_SEL_22"/>
1664         <reg32 offset="0xAE27" name="SP_PERFCTR_SP_SEL_23"/>
1665         <reg32 offset="0xB601" name="TPL1_ADDR_MODE_CNTL"/>
1666         <reg32 offset="0xB604" name="TPL1_NC_MODE_CNTL"/>
1667         <reg32 offset="0xB610" name="TPL1_PERFCTR_TP_SEL_0"/>
1668         <reg32 offset="0xB611" name="TPL1_PERFCTR_TP_SEL_1"/>
1669         <reg32 offset="0xB612" name="TPL1_PERFCTR_TP_SEL_2"/>
1670         <reg32 offset="0xB613" name="TPL1_PERFCTR_TP_SEL_3"/>
1671         <reg32 offset="0xB614" name="TPL1_PERFCTR_TP_SEL_4"/>
1672         <reg32 offset="0xB615" name="TPL1_PERFCTR_TP_SEL_5"/>
1673         <reg32 offset="0xB616" name="TPL1_PERFCTR_TP_SEL_6"/>
1674         <reg32 offset="0xB617" name="TPL1_PERFCTR_TP_SEL_7"/>
1675         <reg32 offset="0xB618" name="TPL1_PERFCTR_TP_SEL_8"/>
1676         <reg32 offset="0xB619" name="TPL1_PERFCTR_TP_SEL_9"/>
1677         <reg32 offset="0xB61A" name="TPL1_PERFCTR_TP_SEL_10"/>
1678         <reg32 offset="0xB61B" name="TPL1_PERFCTR_TP_SEL_11"/>
1679         <reg32 offset="0x3000" name="VBIF_VERSION"/>
1680         <reg32 offset="0x3001" name="VBIF_CLKON">
1681                 <bitfield pos="1" name="FORCE_ON_TESTBUS"/>
1682         </reg32>
1683         <reg32 offset="0x302A" name="VBIF_GATE_OFF_WRREQ_EN"/>
1684         <reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/>
1685         <reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/>
1686         <reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/>
1687         <reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/>
1688         <reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1">
1689                 <bitfield low="0" high="3" name="DATA_SEL"/>
1690         </reg32>
1691         <reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/>
1692         <reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1">
1693                 <bitfield low="0" high="8" name="DATA_SEL"/>
1694         </reg32>
1695         <reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/>
1696         <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0"/>
1697         <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1"/>
1698         <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2"/>
1699         <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3"/>
1700         <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
1701         <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
1702         <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
1703         <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
1704         <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
1705         <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
1706         <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
1707         <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
1708         <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
1709         <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
1710         <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
1711         <reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/>
1712         <reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/>
1713         <reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/>
1714         <reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/>
1715         <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
1716         <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>
1717
1718         <!-- move/rename these.. -->
1719
1720         <reg32 offset="0x88d4" name="RB_WINDOW_OFFSET2" type="adreno_reg_xy"/>
1721         <reg32 offset="0xb4d1" name="SP_WINDOW_OFFSET" type="adreno_reg_xy"/>
1722         <reg32 offset="0xb307" name="SP_TP_WINDOW_OFFSET" type="adreno_reg_xy"/>
1723
1724         <!-- same as RB_BIN_CONTROL -->
1725         <reg32 offset="0x80a1" name="GRAS_BIN_CONTROL">
1726                 <bitfield name="BINW" low="0" high="7" shr="5" type="uint"/>
1727                 <bitfield name="BINH" low="8" high="16" shr="4" type="uint"/>
1728                 <bitfield name="BINNING_PASS" pos="18" type="boolean"/>
1729                 <bitfield name="USE_VIZ" pos="21" type="boolean"/>
1730         </reg32>
1731
1732         <!--
1733                 from offset it seems it should be RB, but weird to duplicate
1734                 other regs from same block??
1735          -->
1736         <reg32 offset="0x88d3" name="RB_BIN_CONTROL2">
1737                 <bitfield name="BINW" low="0" high="7" shr="5" type="uint"/>
1738                 <bitfield name="BINH" low="8" high="16" shr="4" type="uint"/>
1739         </reg32>
1740
1741         <reg32 offset="0x0c02" name="VSC_BIN_SIZE">
1742                 <bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
1743                 <bitfield name="HEIGHT" low="8" high="16" shr="4" type="uint"/>
1744         </reg32>
1745         <reg32 offset="0x0c03" name="VSC_SIZE_ADDRESS_LO"/>
1746         <reg32 offset="0x0c04" name="VSC_SIZE_ADDRESS_HI"/>
1747         <reg32 offset="0x0c06" name="VSC_BIN_COUNT">
1748                 <bitfield name="NX" low="1" high="10" type="uint"/>
1749                 <bitfield name="NY" low="11" high="20" type="uint"/>
1750         </reg32>
1751         <array offset="0x0c10" name="VSC_PIPE_CONFIG" stride="1" length="32">
1752                 <reg32 offset="0x0" name="REG">
1753                         <doc>
1754                                 Configures the mapping between VSC_PIPE buffer and
1755                                 bin, X/Y specify the bin index in the horiz/vert
1756                                 direction (0,0 is upper left, 0,1 is leftmost bin
1757                                 on second row, and so on).  W/H specify the number
1758                                 of bins assigned to this VSC_PIPE in the horiz/vert
1759                                 dimension.
1760                         </doc>
1761                         <bitfield name="X" low="0" high="9" type="uint"/>
1762                         <bitfield name="Y" low="10" high="19" type="uint"/>
1763                         <bitfield name="W" low="20" high="25" type="uint"/>
1764                         <bitfield name="H" low="26" high="31" type="uint"/>
1765                 </reg32>
1766         </array>
1767         <!--
1768         compared to a5xx and earlier, we just program the address of the first
1769         visibility stream and hw adds (pipe_num * VSC_PIPE_DATA_PITCH)
1770
1771         TODO now there seem to be two buffers of VSC data (both referenced by
1772         CP_SET_BIN_DATA packet.  Not sure what this new DATA2 one is, but seems
1773         to have the larger pitch.
1774          -->
1775         <reg32 offset="0x0c30" name="VSC_PIPE_DATA2_ADDRESS_LO"/>
1776         <reg32 offset="0x0c31" name="VSC_PIPE_DATA2_ADDRESS_HI"/>
1777         <reg32 offset="0x0c32" name="VSC_PIPE_DATA2_PITCH"/>
1778         <reg32 offset="0x0c33" name="VSC_PIPE_DATA2_ARRAY_PITCH" shr="4" type="uint"/>
1779         <reg32 offset="0x0c34" name="VSC_PIPE_DATA_ADDRESS_LO"/>
1780         <reg32 offset="0x0c35" name="VSC_PIPE_DATA_ADDRESS_HI"/>
1781         <reg32 offset="0x0c36" name="VSC_PIPE_DATA_PITCH"/>
1782         <reg32 offset="0x0c37" name="VSC_PIPE_DATA_ARRAY_PITCH" shr="4" type="uint"/>
1783
1784         <!--
1785         note, also a range starting at 0x0c58, one or the other probably
1786         corresponds to the new "VSC_XXX" thing, whatever it is..
1787          -->
1788         <array offset="0x0c78" name="VSC_SIZE" stride="1" length="32">
1789                 <doc>
1790                         Has the size of data written to corresponding VSC pipe, ie.
1791                         same thing that is written out to VSC_SIZE_ADDRESS_LO/HI
1792                 </doc>
1793                 <reg32 offset="0x0" name="REG"/>
1794         </array>
1795
1796         <!-- always 0x03200000 ? -->
1797         <reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12"/>
1798
1799         <reg32 offset="0x8000" name="GRAS_UNKNOWN_8000"/>
1800         <reg32 offset="0x8001" name="GRAS_UNKNOWN_8001"/>
1801
1802         <!-- always 0x0 ? -->
1803         <reg32 offset="0x8004" name="GRAS_UNKNOWN_8004"/>
1804
1805         <reg32 offset="0x8005" name="GRAS_CNTL">
1806                 <!-- see also RB_RENDER_CONTROL0 -->
1807                 <bitfield name="VARYING" pos="0" type="boolean"/>
1808                 <!-- b1 set for interpolateAtCentroid() -->
1809                 <bitfield name="CENTROID" pos="1" type="boolean"/>
1810                 <!-- b2 set instead of b0 when running in per-sample mode -->
1811                 <bitfield name="PERSAMP_VARYING" pos="2" type="boolean"/>
1812                 <!--
1813                 b3 set for interpolateAt{Offset,Sample}() if not in per-sample
1814                 mode, and frag_face
1815                  -->
1816                 <bitfield name="SIZE" pos="3" type="boolean"/>
1817                 <!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
1818                 <bitfield name="SIZE_PERSAMP" pos="5" type="boolean"/>
1819                 <bitfield name="XCOORD" pos="6" type="boolean"/>
1820                 <bitfield name="YCOORD" pos="7" type="boolean"/>
1821                 <bitfield name="ZCOORD" pos="8" type="boolean"/>
1822                 <bitfield name="WCOORD" pos="9" type="boolean"/>
1823         </reg32>
1824         <reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ">
1825                 <bitfield name="HORZ" low="0" high="9" type="uint"/>
1826                 <bitfield name="VERT" low="10" high="19" type="uint"/>
1827         </reg32>
1828         <reg32 offset="0x8010" name="GRAS_CL_VPORT_XOFFSET_0" type="float"/>
1829         <reg32 offset="0x8011" name="GRAS_CL_VPORT_XSCALE_0" type="float"/>
1830         <reg32 offset="0x8012" name="GRAS_CL_VPORT_YOFFSET_0" type="float"/>
1831         <reg32 offset="0x8013" name="GRAS_CL_VPORT_YSCALE_0" type="float"/>
1832         <reg32 offset="0x8014" name="GRAS_CL_VPORT_ZOFFSET_0" type="float"/>
1833         <reg32 offset="0x8015" name="GRAS_CL_VPORT_ZSCALE_0" type="float"/>
1834
1835         <reg32 offset="0x8090" name="GRAS_SU_CNTL">
1836                 <bitfield name="CULL_FRONT" pos="0" type="boolean"/>
1837                 <bitfield name="CULL_BACK" pos="1" type="boolean"/>
1838                 <bitfield name="FRONT_CW" pos="2" type="boolean"/>
1839                 <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
1840                 <bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
1841                 <bitfield name="MSAA_ENABLE" pos="13" type="boolean"/>
1842                 <!-- probably LINEHALFWIDTH is the same as a4xx.. -->
1843         </reg32>
1844         <reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX">
1845                 <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
1846                 <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
1847         </reg32>
1848         <reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" type="fixed" radix="4"/>
1849
1850         <reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL">
1851                 <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
1852         </reg32>
1853         <reg32 offset="0x8095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float"/>
1854         <reg32 offset="0x8096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float"/>
1855         <reg32 offset="0x8097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float"/>
1856         <!-- duplicates RB_DEPTH_BUFFER_INFO: -->
1857         <reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO">
1858                 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
1859         </reg32>
1860
1861         <!-- always 0x0 -->
1862         <reg32 offset="0x8099" name="GRAS_UNKNOWN_8099"/>
1863
1864         <!-- always 0x0 ? -->
1865         <reg32 offset="0x809b" name="GRAS_UNKNOWN_809B"/>
1866
1867         <reg32 offset="0x80a0" name="GRAS_UNKNOWN_80A0"/>
1868
1869         <reg32 offset="0x80a2" name="GRAS_RAS_MSAA_CNTL">
1870                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1871         </reg32>
1872         <reg32 offset="0x80a3" name="GRAS_DEST_MSAA_CNTL">
1873                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1874                 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
1875         </reg32>
1876
1877         <!-- always 0x0 -->
1878         <reg32 offset="0x80a4" name="GRAS_UNKNOWN_80A4"/>
1879         <!-- always 0x0 -->
1880         <reg32 offset="0x80a5" name="GRAS_UNKNOWN_80A5"/>
1881         <!-- always 0x0 -->
1882         <reg32 offset="0x80a6" name="GRAS_UNKNOWN_80A6"/>
1883         <!-- always 0x0 -->
1884         <reg32 offset="0x80af" name="GRAS_UNKNOWN_80AF"/>
1885
1886         <reg32 offset="0x80b0" name="GRAS_SC_SCREEN_SCISSOR_TL_0" type="adreno_reg_xy"/>
1887         <reg32 offset="0x80b1" name="GRAS_SC_SCREEN_SCISSOR_BR_0" type="adreno_reg_xy"/>
1888         <reg32 offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR_TL_0" type="adreno_reg_xy"/>
1889         <reg32 offset="0x80d1" name="GRAS_SC_VIEWPORT_SCISSOR_BR_0" type="adreno_reg_xy"/>
1890         <reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="adreno_reg_xy"/>
1891         <reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="adreno_reg_xy"/>
1892
1893         <reg32 offset="0x8100" name="GRAS_LRZ_CNTL">
1894                 <!--
1895                 These bits seems to mostly fit.. but wouldn't hurt to have a 2nd
1896                 look when we get around to enabling lrz
1897                  -->
1898                 <bitfield name="ENABLE" pos="0" type="boolean"/>
1899                 <doc>LRZ write also disabled for blend/etc.</doc>
1900                 <bitfield name="LRZ_WRITE" pos="1" type="boolean"/>
1901                 <doc>update MAX instead of MIN value, ie. GL_GREATER/GL_GEQUAL</doc>
1902                 <bitfield name="GREATER" pos="2" type="boolean"/>
1903                 <!-- set at end of batch that had LRZ enabled (to flush/disable it?) -->
1904                 <bitfield name="UNK3" pos="3" type="boolean"/>
1905                 <!-- set when depth-test + depth-write enabled -->
1906                 <bitfield name="UNK4" pos="4" type="boolean"/>
1907         </reg32>
1908         <reg32 offset="0x8101" name="GRAS_UNKNOWN_8101"/>
1909         <reg32 offset="0x8102" name="GRAS_2D_BLIT_INFO">
1910                 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_color_fmt"/>
1911         </reg32>
1912         <reg32 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE_LO"/>
1913         <reg32 offset="0x8104" name="GRAS_LRZ_BUFFER_BASE_HI"/>
1914         <reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH">
1915                 <bitfield name="PITCH" low="0" high="10" shr="5" type="uint"/>
1916                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="5" type="uint"/> <!-- ??? -->
1917         </reg32>
1918         <reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO"/>
1919         <reg32 offset="0x8107" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI"/>
1920
1921         <reg32 offset="0x8109" name="GRAS_SAMPLE_CNTL">
1922                 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
1923         </reg32>
1924
1925         <reg32 offset="0x8110" name="GRAS_UNKNOWN_8110"/>
1926
1927         <enum name="a6xx_rotation">
1928           <value value="0x0" name="ROTATE_0"/>
1929           <value value="0x1" name="ROTATE_90"/>
1930           <value value="0x2" name="ROTATE_180"/>
1931           <value value="0x3" name="ROTATE_270"/>
1932         </enum>
1933
1934         <bitset name="a6xx_2d_blit_cntl" inline="yes">
1935                 <bitfield name="ROTATE" low="0" high="1" type="a6xx_rotation"/>
1936                 <bitfield name="HORIZONTAL_FLIP" low="2" high="2" type="boolean"/>
1937                 <bitfield name="SOLID_COLOR" low="4" high="4" type="boolean"/>
1938                 <bitfield name="COLOR_FORMAT" low="8" high="15" type="a6xx_color_fmt"/>
1939                 <bitfield name="SCISSOR" pos="16" type="boolean"/>
1940                 <!-- double check these:
1941                 <bitfield name="FLAGS" pos="18" type="boolean"/>
1942                 <bitfield name="TILE_MODE" low="20" high="21" type="a6xx_tile_mode"/>
1943                 <bitfield name="COLOR_SWAP" low="22" high="23" type="a3xx_color_swap"/>
1944                 -->
1945                 <bitfield name="IFMT" low="24" high="28" type="a6xx_2d_ifmt"/>
1946         </bitset>
1947
1948         <reg32 offset="0x8400" name="GRAS_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/>
1949
1950         <!-- could be the src coords are fixed point? -->
1951         <reg32 offset="0x8401" name="GRAS_2D_SRC_TL_X">
1952                 <bitfield name="X" low="8" high="31" type="int"/>
1953         </reg32>
1954         <reg32 offset="0x8402" name="GRAS_2D_SRC_BR_X">
1955                 <bitfield name="X" low="8" high="31" type="int"/>
1956         </reg32>
1957         <reg32 offset="0x8403" name="GRAS_2D_SRC_TL_Y">
1958                 <bitfield name="Y" low="8" high="31" type="int"/>
1959         </reg32>
1960         <reg32 offset="0x8404" name="GRAS_2D_SRC_BR_Y">
1961                 <bitfield name="Y" low="8" high="31" type="int"/>
1962         </reg32>
1963
1964         <reg32 offset="0x8405" name="GRAS_2D_DST_TL" type="adreno_reg_xy"/>
1965         <reg32 offset="0x8406" name="GRAS_2D_DST_BR" type="adreno_reg_xy"/>
1966
1967         <reg32 offset="0x840a" name="GRAS_RESOLVE_CNTL_1" type="adreno_reg_xy"/>
1968         <reg32 offset="0x840b" name="GRAS_RESOLVE_CNTL_2" type="adreno_reg_xy"/>
1969
1970         <!-- always 0x880 ? -->
1971         <reg32 offset="0x8600" name="GRAS_UNKNOWN_8600"/>
1972
1973         <!-- same as GRAS_BIN_CONTROL: -->
1974         <reg32 offset="0x8800" name="RB_BIN_CONTROL">
1975                 <bitfield name="BINW" low="0" high="7" shr="5" type="uint"/>
1976                 <bitfield name="BINH" low="8" high="16" shr="4" type="uint"/>
1977                 <bitfield name="BINNING_PASS" pos="18" type="boolean"/>
1978                 <bitfield name="USE_VIZ" pos="21" type="boolean"/>
1979         </reg32>
1980         <reg32 offset="0x8801" name="RB_RENDER_CNTL">
1981                 <!-- always set: ?? -->
1982                 <bitfield name="UNK4" pos="4" type="boolean"/>
1983                 <!-- set during binning pass: -->
1984                 <bitfield name="BINNING" pos="7" type="boolean"/>
1985                 <!-- bit seems to be set whenever depth buffer enabled: -->
1986                 <bitfield name="FLAG_DEPTH" pos="14" type="boolean"/>
1987                 <!-- bitmask of MRTs using UBWC flag buffer: -->
1988                 <bitfield name="FLAG_MRTS" low="16" high="23"/>
1989         </reg32>
1990         <reg32 offset="0x8802" name="RB_RAS_MSAA_CNTL">
1991                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1992         </reg32>
1993         <reg32 offset="0x8803" name="RB_DEST_MSAA_CNTL">
1994                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1995                 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
1996         </reg32>
1997
1998         <!-- always 0x0 ? -->
1999         <reg32 offset="0x8804" name="RB_UNKNOWN_8804"/>
2000         <!-- always 0x0 ? -->
2001         <reg32 offset="0x8805" name="RB_UNKNOWN_8805"/>
2002         <!-- always 0x0 ? -->
2003         <reg32 offset="0x8806" name="RB_UNKNOWN_8806"/>
2004
2005         <!--
2006         note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL
2007         name comes from kernel and is probably right)
2008          -->
2009         <reg32 offset="0x8809" name="RB_RENDER_CONTROL0">
2010                 <!-- see also GRAS_CNTL -->
2011                 <bitfield name="VARYING" pos="0" type="boolean"/>
2012                 <!-- b1 set for interpolateAtCentroid() -->
2013                 <bitfield name="CENTROID" pos="1" type="boolean"/>
2014                 <!-- b2 set instead of b0 when running in per-sample mode -->
2015                 <bitfield name="PERSAMP_VARYING" pos="2" type="boolean"/>
2016                 <!--
2017                 b3 set for interpolateAt{Offset,Sample}() if not in per-sample
2018                 mode, and frag_face
2019                  -->
2020                 <bitfield name="SIZE" pos="3" type="boolean"/>
2021                 <!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
2022                 <bitfield name="SIZE_PERSAMP" pos="5" type="boolean"/>
2023                 <bitfield name="XCOORD" pos="6" type="boolean"/>
2024                 <bitfield name="YCOORD" pos="7" type="boolean"/>
2025                 <bitfield name="ZCOORD" pos="8" type="boolean"/>
2026                 <bitfield name="WCOORD" pos="9" type="boolean"/>
2027                 <bitfield name="UNK10" pos="10" type="boolean"/>
2028         </reg32>
2029         <reg32 offset="0x880a" name="RB_RENDER_CONTROL1">
2030                 <!-- enable bits for various FS sysvalue regs: -->
2031                 <bitfield name="SAMPLEMASK" pos="0" type="boolean"/>
2032                 <bitfield name="FACENESS" pos="2" type="boolean"/>
2033                 <bitfield name="SAMPLEID" pos="3" type="boolean"/>
2034                 <!-- b4 and b5 set in per-sample mode: -->
2035                 <bitfield name="UNK4" pos="4" type="boolean"/>
2036                 <bitfield name="UNK5" pos="5" type="boolean"/>
2037                 <bitfield name="SIZE" pos="6" type="boolean"/>
2038         </reg32>
2039
2040         <reg32 offset="0x880b" name="RB_FS_OUTPUT_CNTL0">
2041                 <bitfield name="FRAG_WRITES_Z" pos="1" type="boolean"/>
2042                 <bitfield name="FRAG_WRITES_SAMPMASK" pos="2" type="boolean"/>
2043         </reg32>
2044         <reg32 offset="0x880c" name="RB_FS_OUTPUT_CNTL1">
2045                 <bitfield name="MRT" low="0" high="3" type="uint"/>
2046         </reg32>
2047         <reg32 offset="0x880d" name="RB_RENDER_COMPONENTS">
2048                 <bitfield name="RT0" low="0" high="3"/>
2049                 <bitfield name="RT1" low="4" high="7"/>
2050                 <bitfield name="RT2" low="8" high="11"/>
2051                 <bitfield name="RT3" low="12" high="15"/>
2052                 <bitfield name="RT4" low="16" high="19"/>
2053                 <bitfield name="RT5" low="20" high="23"/>
2054                 <bitfield name="RT6" low="24" high="27"/>
2055                 <bitfield name="RT7" low="28" high="31"/>
2056         </reg32>
2057         <reg32 offset="0x880e" name="RB_DITHER_CNTL">
2058                 <bitfield name="DITHER_MODE_MRT0" low="0"  high="1"  type="adreno_rb_dither_mode"/>
2059                 <bitfield name="DITHER_MODE_MRT1" low="2"  high="3"  type="adreno_rb_dither_mode"/>
2060                 <bitfield name="DITHER_MODE_MRT2" low="4"  high="5"  type="adreno_rb_dither_mode"/>
2061                 <bitfield name="DITHER_MODE_MRT3" low="6"  high="7"  type="adreno_rb_dither_mode"/>
2062                 <bitfield name="DITHER_MODE_MRT4" low="8"  high="9"  type="adreno_rb_dither_mode"/>
2063                 <bitfield name="DITHER_MODE_MRT5" low="10" high="11" type="adreno_rb_dither_mode"/>
2064                 <bitfield name="DITHER_MODE_MRT6" low="12" high="12" type="adreno_rb_dither_mode"/>
2065                 <bitfield name="DITHER_MODE_MRT7" low="14" high="15" type="adreno_rb_dither_mode"/>
2066         </reg32>
2067         <reg32 offset="0x880f" name="RB_SRGB_CNTL">
2068                 <!-- Same as SP_SRGB_CNTL -->
2069                 <bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
2070                 <bitfield name="SRGB_MRT1" pos="1" type="boolean"/>
2071                 <bitfield name="SRGB_MRT2" pos="2" type="boolean"/>
2072                 <bitfield name="SRGB_MRT3" pos="3" type="boolean"/>
2073                 <bitfield name="SRGB_MRT4" pos="4" type="boolean"/>
2074                 <bitfield name="SRGB_MRT5" pos="5" type="boolean"/>
2075                 <bitfield name="SRGB_MRT6" pos="6" type="boolean"/>
2076                 <bitfield name="SRGB_MRT7" pos="7" type="boolean"/>
2077         </reg32>
2078
2079         <reg32 offset="0x8810" name="RB_SAMPLE_CNTL">
2080                 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
2081         </reg32>
2082         <reg32 offset="0x8811" name="RB_UNKNOWN_8811"/>
2083
2084         <!-- always 0x0 ? -->
2085         <reg32 offset="0x8818" name="RB_UNKNOWN_8818"/>
2086         <reg32 offset="0x8819" name="RB_UNKNOWN_8819"/>
2087         <reg32 offset="0x881a" name="RB_UNKNOWN_881A"/>
2088         <reg32 offset="0x881b" name="RB_UNKNOWN_881B"/>
2089         <reg32 offset="0x881c" name="RB_UNKNOWN_881C"/>
2090         <reg32 offset="0x881d" name="RB_UNKNOWN_881D"/>
2091         <reg32 offset="0x881e" name="RB_UNKNOWN_881E"/>
2092
2093         <array offset="0x8820" name="RB_MRT" stride="8" length="8">
2094                 <reg32 offset="0x0" name="CONTROL">
2095                         <bitfield name="BLEND" pos="0" type="boolean"/>
2096                         <bitfield name="BLEND2" pos="1" type="boolean"/>
2097                         <bitfield name="ROP_ENABLE" pos="2" type="boolean"/>
2098                         <bitfield name="ROP_CODE" low="3" high="6" type="a3xx_rop_code"/>
2099                         <bitfield name="COMPONENT_ENABLE" low="7" high="10" type="hex"/>
2100                 </reg32>
2101                 <reg32 offset="0x1" name="BLEND_CONTROL">
2102                         <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
2103                         <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>
2104                         <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>
2105                         <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>
2106                         <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>
2107                         <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>
2108                 </reg32>
2109                 <reg32 offset="0x2" name="BUF_INFO">
2110                         <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_color_fmt"/>
2111                         <bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
2112                         <bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/>
2113                 </reg32>
2114                 <!--
2115                 at least in gmem, things seem to be aligned to pitch of 64..
2116                 maybe an artifact of tiled format used in gmem?
2117                  -->
2118                 <reg32 offset="0x3" name="PITCH" shr="6" type="uint"/>
2119                 <reg32 offset="0x4" name="ARRAY_PITCH" shr="6" type="uint"/>
2120                 <!--
2121                 Compared to a5xx and before, we configure both a GMEM base and
2122                 external base.  Not sure if this is to facilitate GMEM save/
2123                 restore for context switch, or just to simplify state setup to
2124                 not have to care about GMEM vs BYPASS mode.
2125                  -->
2126                 <reg32 offset="0x5" name="BASE_LO"/>
2127                 <reg32 offset="0x6" name="BASE_HI"/>
2128                 <reg32 offset="0x7" name="BASE_GMEM"/>
2129         </array>
2130
2131         <reg32 offset="0x8860" name="RB_BLEND_RED_F32" type="float"/>
2132         <reg32 offset="0x8861" name="RB_BLEND_GREEN_F32" type="float"/>
2133         <reg32 offset="0x8862" name="RB_BLEND_BLUE_F32" type="float"/>
2134         <reg32 offset="0x8863" name="RB_BLEND_ALPHA_F32" type="float"/>
2135         <reg32 offset="0x8864" name="RB_ALPHA_CONTROL">
2136                 <bitfield name="ALPHA_REF" low="0" high="7" type="hex"/>
2137                 <bitfield name="ALPHA_TEST" pos="8" type="boolean"/>
2138                 <bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/>
2139         </reg32>
2140         <reg32 offset="0x8865" name="RB_BLEND_CNTL">
2141                 <!-- per-mrt enable bit -->
2142                 <bitfield name="ENABLE_BLEND" low="0" high="7"/>
2143                 <bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/>
2144                 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
2145                 <bitfield name="SAMPLE_MASK" low="16" high="31"/>
2146         </reg32>
2147         <reg32 offset="0x8870" name="RB_DEPTH_PLANE_CNTL">
2148                 <bitfield name="FRAG_WRITES_Z" pos="0" type="boolean"/>
2149         </reg32>
2150
2151         <reg32 offset="0x8871" name="RB_DEPTH_CNTL">
2152                 <bitfield name="Z_ENABLE" pos="0" type="boolean"/>
2153                 <bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/>
2154                 <bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/>
2155                 <doc>Z_TEST_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER</doc>
2156                 <bitfield name="Z_TEST_ENABLE" pos="6" type="boolean"/>
2157         </reg32>
2158         <!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: -->
2159         <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO">
2160                 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
2161         </reg32>
2162 <!-- probably: -->
2163         <reg32 offset="0x8873" name="RB_DEPTH_BUFFER_PITCH" shr="6" type="uint">
2164                 <doc>stride of depth/stencil buffer</doc>
2165         </reg32>
2166         <reg32 offset="0x8874" name="RB_DEPTH_BUFFER_ARRAY_PITCH" shr="6" type="uint">
2167                 <doc>size of layer</doc>
2168         </reg32>
2169         <reg32 offset="0x8875" name="RB_DEPTH_BUFFER_BASE_LO"/>
2170         <reg32 offset="0x8876" name="RB_DEPTH_BUFFER_BASE_HI"/>
2171         <reg32 offset="0x8877" name="RB_DEPTH_BUFFER_BASE_GMEM"/>
2172
2173         <!-- always 0x0 ? -->
2174         <reg32 offset="0x8878" name="RB_UNKNOWN_8878"/>
2175         <!-- always 0x0 ? -->
2176         <reg32 offset="0x8879" name="RB_UNKNOWN_8879"/>
2177
2178         <reg32 offset="0x8880" name="RB_STENCIL_CONTROL">
2179                 <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
2180                 <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>
2181                 <!--
2182                         set for stencil operations that require read from stencil
2183                         buffer, but not for example for stencil clear (which does
2184                         not require read).. so guessing this is analogous to
2185                         READ_DEST_ENABLE for color buffer..
2186                  -->
2187                 <bitfield name="STENCIL_READ" pos="2" type="boolean"/>
2188                 <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>
2189                 <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>
2190                 <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>
2191                 <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>
2192                 <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>
2193                 <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
2194                 <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
2195                 <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
2196         </reg32>
2197         <reg32 offset="0x8881" name="RB_STENCIL_INFO">
2198                 <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
2199         </reg32>
2200         <reg32 offset="0x8882" name="RB_STENCIL_BUFFER_PITCH" shr="6" type="uint">
2201                 <doc>stride of stencil buffer</doc>
2202         </reg32>
2203         <reg32 offset="0x8883" name="RB_STENCIL_BUFFER_ARRAY_PITCH" shr="6" type="uint">
2204                 <doc>size of layer</doc>
2205         </reg32>
2206         <reg32 offset="0x8884" name="RB_STENCIL_BUFFER_BASE_LO"/>
2207         <reg32 offset="0x8885" name="RB_STENCIL_BUFFER_BASE_HI"/>
2208         <reg32 offset="0x8886" name="RB_STENCIL_BUFFER_BASE_GMEM"/>
2209         <reg32 offset="0x8887" name="RB_STENCILREF">
2210                 <bitfield name="REF" low="0" high="7"/>
2211                 <bitfield name="BFREF" low="8" high="15"/>
2212         </reg32>
2213         <reg32 offset="0x8888" name="RB_STENCILMASK">
2214                 <bitfield name="MASK" low="0" high="7"/>
2215                 <bitfield name="BFMASK" low="8" high="15"/>
2216         </reg32>
2217         <reg32 offset="0x8889" name="RB_STENCILWRMASK">
2218                 <bitfield name="WRMASK" low="0" high="7"/>
2219                 <bitfield name="BFWRMASK" low="8" high="15"/>
2220         </reg32>
2221         <reg32 offset="0x8890" name="RB_WINDOW_OFFSET" type="adreno_reg_xy"/>
2222         <reg32 offset="0x8891" name="RB_SAMPLE_COUNT_CONTROL">
2223                 <bitfield name="COPY" pos="1" type="boolean"/>
2224         </reg32>
2225
2226         <reg32 offset="0x8898" name="RB_LRZ_CNTL">
2227                 <bitfield name="ENABLE" pos="0" type="boolean"/>
2228         </reg32>
2229
2230         <reg32 offset="0x88d0" name="RB_UNKNOWN_88D0"/>
2231         <reg32 offset="0x88d1" name="RB_BLIT_SCISSOR_TL" type="adreno_reg_xy"/>
2232         <reg32 offset="0x88d2" name="RB_BLIT_SCISSOR_BR" type="adreno_reg_xy"/>
2233
2234         <reg32 offset="0x88d5" name="RB_MSAA_CNTL">
2235                 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
2236         </reg32>
2237         <reg32 offset="0x88d6" name="RB_BLIT_BASE_GMEM"/>
2238         <!-- s/DST_FORMAT/DST_INFO/ probably: -->
2239         <reg32 offset="0x88d7" name="RB_BLIT_DST_INFO">
2240                 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
2241                 <bitfield name="FLAGS" pos="2" type="boolean"/>
2242                 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
2243                 <bitfield name="COLOR_FORMAT" low="7" high="14" type="a6xx_color_fmt"/>
2244                 <bitfield name="COLOR_SWAP" low="5" high="6" type="a3xx_color_swap"/>
2245         </reg32>
2246         <reg32 offset="0x88d8" name="RB_BLIT_DST_LO"/>
2247         <reg32 offset="0x88d9" name="RB_BLIT_DST_HI"/>
2248         <reg32 offset="0x88da" name="RB_BLIT_DST_PITCH" shr="6" type="uint"/>
2249         <!-- array-pitch is size of layer -->
2250         <reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" shr="6" type="uint"/>
2251         <reg32 offset="0x88dc" name="RB_BLIT_FLAG_DST_LO"/>
2252         <reg32 offset="0x88dd" name="RB_BLIT_FLAG_DST_HI"/>
2253         <reg32 offset="0x88de" name="RB_BLIT_FLAG_DST_PITCH">
2254                 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2255                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
2256         </reg32>
2257
2258         <reg32 offset="0x88df" name="RB_BLIT_CLEAR_COLOR_DW0"/>
2259         <reg32 offset="0x88e0" name="RB_BLIT_CLEAR_COLOR_DW1"/>
2260         <reg32 offset="0x88e1" name="RB_BLIT_CLEAR_COLOR_DW2"/>
2261         <reg32 offset="0x88e2" name="RB_BLIT_CLEAR_COLOR_DW3"/>
2262
2263         <!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: -->
2264         <reg32 offset="0x88e3" name="RB_BLIT_INFO">
2265                 <bitfield name="UNK0" pos="0" type="boolean"/> <!-- s8 stencil restore/clear?  But also color restore? -->
2266                 <bitfield name="GMEM" pos="1" type="boolean"/> <!-- set for restore and clear to gmem? -->
2267                 <bitfield name="INTEGER" pos="2" type="boolean"/> <!-- probably -->
2268                 <bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? -->
2269                 <doc>
2270                         For clearing depth/stencil
2271                                 1 - depth
2272                                 2 - stencil
2273                                 3 - depth+stencil
2274                         For clearing color buffer:
2275                                 then probably a component mask, I always see 0xf
2276                 </doc>
2277                 <bitfield name="CLEAR_MASK" low="4" high="7"/>
2278         </reg32>
2279
2280         <!-- always 0x0 ? -->
2281         <reg32 offset="0x88f0" name="RB_UNKNOWN_88F0"/>
2282
2283         <reg32 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE_LO"/>
2284         <reg32 offset="0x8901" name="RB_DEPTH_FLAG_BUFFER_BASE_HI"/>
2285         <reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH">
2286                 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2287                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
2288         </reg32>
2289         <array offset="0x8903" name="RB_MRT_FLAG_BUFFER" stride="3" length="8">
2290                 <reg32 offset="0" name="ADDR_LO"/>
2291                 <reg32 offset="1" name="ADDR_HI"/>
2292                 <reg32 offset="2" name="PITCH">
2293                         <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2294                         <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/> <!-- ??? -->
2295                 </reg32>
2296         </array>
2297         <reg32 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR_LO"/>
2298         <reg32 offset="0x8928" name="RB_SAMPLE_COUNT_ADDR_HI"/>
2299
2300         <reg32 offset="0x8c00" name="RB_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/>
2301         <reg32 offset="0x8c01" name="RB_UNKNOWN_8C01"/>
2302
2303         <reg32 offset="0x8c17" name="RB_2D_DST_INFO">
2304                 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_color_fmt"/>
2305                 <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
2306                 <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
2307                 <!-- b12 seems to be set when UBWC "FLAGS" buffer enabled -->
2308                 <bitfield name="FLAGS" pos="12" type="boolean"/>
2309         </reg32>
2310         <reg32 offset="0x8c18" name="RB_2D_DST_LO"/>
2311         <reg32 offset="0x8c19" name="RB_2D_DST_HI"/>
2312         <reg32 offset="0x8c1a" name="RB_2D_DST_SIZE">
2313                 <bitfield name="PITCH" low="0" high="15" shr="6" type="uint"/>
2314         </reg32>
2315
2316         <reg32 offset="0x8c20" name="RB_2D_DST_FLAGS_LO"/>
2317         <reg32 offset="0x8c21" name="RB_2D_DST_FLAGS_HI"/>
2318         <reg32 offset="0x8c22" name="RB_2D_DST_FLAGS_PITCH">
2319                 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2320                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
2321         </reg32>
2322
2323         <!-- unlike a5xx, these are per channel values rather than packed -->
2324         <reg32 offset="0x8c2c" name="RB_2D_SRC_SOLID_C0"/>
2325         <reg32 offset="0x8c2d" name="RB_2D_SRC_SOLID_C1"/>
2326         <reg32 offset="0x8c2e" name="RB_2D_SRC_SOLID_C2"/>
2327         <reg32 offset="0x8c2f" name="RB_2D_SRC_SOLID_C3"/>
2328
2329         <!-- always 0x1 ? -->
2330         <reg32 offset="0x8e01" name="RB_UNKNOWN_8E01"/>
2331
2332         <reg32 offset="0x8e04" name="RB_UNKNOWN_8E04"/>
2333
2334         <reg32 offset="0x8e07" name="RB_CCU_CNTL"/>  <!-- always 7c400004 or 10000000 -->
2335
2336         <!-- always 0x00ffff00 ? */ -->
2337         <reg32 offset="0x9101" name="VPC_UNKNOWN_9101"/>
2338
2339         <reg32 offset="0x9104" name="VPC_GS_SIV_CNTL"/>
2340
2341         <reg32 offset="0x9107" name="VPC_UNKNOWN_9107"/>
2342         <reg32 offset="0x9108" name="VPC_UNKNOWN_9108"/>
2343
2344         <array offset="0x9200" name="VPC_VARYING_INTERP" stride="1" length="8">
2345                 <reg32 offset="0x0" name="MODE"/>
2346         </array>
2347         <array offset="0x9208" name="VPC_VARYING_PS_REPL" stride="1" length="8">
2348                 <reg32 offset="0x0" name="MODE"/>
2349         </array>
2350
2351         <!-- always 0x0 -->
2352         <reg32 offset="0x9210" name="VPC_UNKNOWN_9210"/>
2353         <reg32 offset="0x9211" name="VPC_UNKNOWN_9211"/>
2354
2355         <array offset="0x9212" name="VPC_VAR" stride="1" length="4">
2356                 <!-- one bit per varying component: -->
2357                 <reg32 offset="0" name="DISABLE"/>
2358         </array>
2359
2360         <reg32 offset="0x9216" name="VPC_SO_CNTL">
2361                 <!-- always 0x10000 when SO enabled.. -->
2362                 <bitfield name="ENABLE" pos="16" type="boolean"/>
2363         </reg32>
2364         <reg32 offset="0x9217" name="VPC_SO_PROG">
2365                 <bitfield name="A_BUF" low="0" high="1" type="uint"/>
2366                 <bitfield name="A_OFF" low="2" high="10" shr="2" type="uint"/>
2367                 <bitfield name="A_EN" pos="11" type="boolean"/>
2368                 <bitfield name="B_BUF" low="12" high="13" type="uint"/>
2369                 <bitfield name="B_OFF" low="14" high="22" shr="2" type="uint"/>
2370                 <bitfield name="B_EN" pos="23" type="boolean"/>
2371         </reg32>
2372         <array offset="0x921a" name="VPC_SO" stride="7" length="4">
2373                 <reg32 offset="0" name="BUFFER_BASE_LO"/>
2374                 <reg32 offset="1" name="BUFFER_BASE_HI"/>
2375                 <reg32 offset="2" name="BUFFER_SIZE"/>
2376                 <reg32 offset="3" name="NCOMP"/>  <!-- component count -->
2377                 <reg32 offset="4" name="BUFFER_OFFSET"/>
2378                 <reg32 offset="5" name="FLUSH_BASE_LO"/>
2379                 <reg32 offset="6" name="FLUSH_BASE_HI"/>
2380         </array>
2381
2382         <!-- always 0x0 ? -->
2383         <reg32 offset="0x9236" name="VPC_UNKNOWN_9236">
2384                 <bitfield name="POINT_COORD_INVERT" pos="0" type="uint"/>
2385         </reg32>
2386
2387         <!-- always 0x0 ? -->
2388         <reg32 offset="0x9300" name="VPC_UNKNOWN_9300"/>
2389
2390         <reg32 offset="0x9301" name="VPC_PACK">
2391                 <doc>
2392                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2393                         plus # of transform-feedback (streamout) varyings if using the
2394                         hw streamout (rather than stg instructions in shader)
2395                 </doc>
2396                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2397                 <bitfield name="NUMNONPOSVAR" low="8" high="15" type="uint"/>
2398                 <!--
2399                 This seems to be the OUTLOC for the psize output.  It could possibly
2400                 be the max-OUTLOC position, but it is only set when VS writes psize
2401                 (and blob always puts psize at highest OUTLOC)
2402                  -->
2403                 <bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
2404         </reg32>
2405
2406         <reg32 offset="0x9303" name="VPC_PACK_3">
2407                 <doc>
2408                   domain shader version
2409
2410                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2411                         plus # of transform-feedback (streamout) varyings if using the
2412                         hw streamout (rather than stg instructions in shader)
2413                 </doc>
2414                 <bitfield name="STRIDE_IN_VPC" low="0" high="7" type="uint"/>
2415                 <bitfield name="NUMNONPOSVAR" low="8" high="15" type="uint"/>
2416                 <!--
2417                 This seems to be the OUTLOC for the psize output.  It could possibly
2418                 be the max-OUTLOC position, but it is only set when VS writes psize
2419                 (and blob always puts psize at highest OUTLOC)
2420                  -->
2421                 <bitfield name="PSIZELOC" low="16" high="23" type="uint"/>
2422         </reg32>
2423
2424         <reg32 offset="0x9304" name="VPC_CNTL_0">
2425                 <bitfield name="NUMNONPOSVAR" low="0" high="7" type="uint"/>
2426                 <bitfield name="VARYING" pos="16" type="boolean"/>
2427         </reg32>
2428
2429         <reg32 offset="0x9305" name="VPC_SO_BUF_CNTL">
2430                 <bitfield name="BUF0" pos="0" type="boolean"/>
2431                 <bitfield name="BUF1" pos="3" type="boolean"/>
2432                 <bitfield name="BUF2" pos="6" type="boolean"/>
2433                 <bitfield name="BUF3" pos="9" type="boolean"/>
2434                 <bitfield name="ENABLE" pos="15" type="boolean"/>
2435         </reg32>
2436         <reg32 offset="0x9306" name="VPC_SO_OVERRIDE">
2437                 <bitfield name="SO_DISABLE" pos="0" type="boolean"/>
2438         </reg32>
2439
2440         <!-- always 0x0 ? -->
2441         <reg32 offset="0x9600" name="VPC_UNKNOWN_9600"/>
2442         <!-- always 0x0 ? -->
2443         <reg32 offset="0x9602" name="VPC_UNKNOWN_9602"/>
2444
2445         <reg32 offset="0x9800" name="PC_TESS_NUM_VERTEX"/>
2446
2447         <!-- always 0x0 ? -->
2448         <reg32 offset="0x9801" name="PC_UNKNOWN_9801"/>
2449
2450         <enum name="a6xx_tess_spacing">
2451           <value value="0x0" name="TESS_EQUAL"/>
2452           <value value="0x2" name="TESS_FRACTIONAL_ODD"/>
2453           <value value="0x3" name="TESS_FRACTIONAL_EVEN"/>
2454         </enum>
2455
2456         <reg32 offset="0x9802" name="PC_TESS_CNTL">
2457           <bitfield name="SPACING" low="0" high="1" type="a6xx_tess_spacing"/>
2458           <bitfield name="CCW" pos="2" type="boolean"/>
2459           <bitfield name="PRIMITIVES" pos="3" type="boolean"/>
2460         </reg32>
2461
2462         <!-- probably: -->
2463         <reg32 offset="0x9803" name="PC_RESTART_INDEX"/>
2464         <reg32 offset="0x9804" name="PC_MODE_CNTL"/>
2465
2466         <!-- always 0x1 ? -->
2467         <reg32 offset="0x9805" name="PC_UNKNOWN_9805"/>
2468         <reg32 offset="0x9806" name="PC_UNKNOWN_9806"/>
2469
2470         <reg32 offset="0x9980" name="PC_UNKNOWN_9980"/>
2471         <reg32 offset="0x9981" name="PC_UNKNOWN_9981"/>
2472
2473         <reg32 offset="0x9990" name="PC_UNKNOWN_9990"/>
2474
2475         <reg32 offset="0x9b00" name="PC_PRIMITIVE_CNTL_0">
2476                 <bitfield name="PRIMITIVE_RESTART" pos="0" type="boolean"/>
2477                 <!-- maybe?  b1 seems always set, so just assume it is for now: -->
2478                 <bitfield name="PROVOKING_VTX_LAST" pos="1" type="boolean"/>
2479         </reg32>
2480         <reg32 offset="0x9b01" name="PC_PRIMITIVE_CNTL_1">
2481                 <doc>
2482                         vertex shader
2483
2484                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2485                         plus # of transform-feedback (streamout) varyings if using the
2486                         hw streamout (rather than stg instructions in shader)
2487                 </doc>
2488                 <bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/>
2489                 <bitfield name="PSIZE" pos="8" type="boolean"/>
2490         </reg32>
2491
2492         <reg32 offset="0x9b03" name="PC_PRIMITIVE_CNTL_3">
2493                 <doc>
2494                         hull shader?
2495
2496                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2497                         plus # of transform-feedback (streamout) varyings if using the
2498                         hw streamout (rather than stg instructions in shader)
2499                 </doc>
2500                 <bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/>
2501                 <bitfield name="PSIZE" pos="8" type="boolean"/>
2502         </reg32>
2503         <reg32 offset="0x9b04" name="PC_PRIMITIVE_CNTL_4">
2504                 <doc>
2505                         domain shader
2506                         num of varyings plus four for gl_Position (plus one if gl_PointSize)
2507                         plus # of transform-feedback (streamout) varyings if using the
2508                         hw streamout (rather than stg instructions in shader)
2509                 </doc>
2510                 <bitfield name="STRIDE_IN_VPC" low="0" high="6" type="uint"/>
2511                 <bitfield name="PSIZE" pos="8" type="boolean"/>
2512         </reg32>
2513
2514         <!-- always 0x0 ? -->
2515         <reg32 offset="0x9b06" name="PC_UNKNOWN_9B06"/>
2516         <reg32 offset="0x9b07" name="PC_UNKNOWN_9B07"/>
2517
2518         <reg32 offset="0x9e08" name="PC_TESSFACTOR_ADDR_LO"/>
2519         <reg32 offset="0x9e09" name="PC_TESSFACTOR_ADDR_HI"/>
2520
2521         <!-- always 0x0 -->
2522         <reg32 offset="0x9e72" name="PC_UNKNOWN_9E72"/>
2523
2524         <reg32 offset="0xa000" name="VFD_CONTROL_0">
2525                 <bitfield name="VTXCNT" low="0" high="5" type="uint"/>
2526         </reg32>
2527         <reg32 offset="0xa001" name="VFD_CONTROL_1">
2528                 <bitfield name="REGID4VTX" low="0" high="7" type="a3xx_regid"/>
2529                 <bitfield name="REGID4INST" low="8" high="15" type="a3xx_regid"/>
2530                 <bitfield name="REGID4PRIMID" low="16" high="23" type="a3xx_regid"/>
2531         </reg32>
2532         <reg32 offset="0xa002" name="VFD_CONTROL_2">
2533                 <bitfield name="REGID_HSPATCHID" low="0" high="7" type="a3xx_regid"/>
2534                 <bitfield name="REGID_INVOCATIONID" low="8" high="15" type="a3xx_regid"/>
2535         </reg32>
2536         <reg32 offset="0xa003" name="VFD_CONTROL_3">
2537                 <bitfield name="REGID_DSPATCHID" low="8" high="15" type="a3xx_regid"/>
2538                 <bitfield name="REGID_TESSX" low="16" high="23" type="a3xx_regid"/>
2539                 <bitfield name="REGID_TESSY" low="24" high="31" type="a3xx_regid"/>
2540         </reg32>
2541         <reg32 offset="0xa004" name="VFD_CONTROL_4">
2542         </reg32>
2543         <reg32 offset="0xa005" name="VFD_CONTROL_5">
2544         </reg32>
2545         <reg32 offset="0xa006" name="VFD_CONTROL_6">
2546         </reg32>
2547
2548         <reg32 offset="0xa007" name="VFD_MODE_CNTL">
2549                 <bitfield name="BINNING_PASS" pos="0" type="boolean"/>
2550         </reg32>
2551
2552         <!-- always 0x0 ? -->
2553         <reg32 offset="0xa008" name="VFD_UNKNOWN_A008"/>
2554         <reg32 offset="0xa009" name="VFD_UNKNOWN_A009"/>
2555
2556         <reg32 offset="0xa00e" name="VFD_INDEX_OFFSET"/>
2557         <reg32 offset="0xa00f" name="VFD_INSTANCE_START_OFFSET"/>
2558         <array offset="0xa010" name="VFD_FETCH" stride="4" length="32">
2559                 <reg32 offset="0x0" name="BASE_LO"/>
2560                 <reg32 offset="0x1" name="BASE_HI"/>
2561                 <reg32 offset="0x2" name="SIZE" type="uint"/>
2562                 <reg32 offset="0x3" name="STRIDE" type="uint"/>
2563         </array>
2564         <array offset="0xa090" name="VFD_DECODE" stride="2" length="32">
2565                 <reg32 offset="0x0" name="INSTR">
2566                         <!-- IDX appears to index into VFD_FETCH[] -->
2567                         <bitfield name="IDX" low="0" high="4" type="uint"/>
2568                         <bitfield name="INSTANCED" pos="17" type="boolean"/>
2569                         <bitfield name="FORMAT" low="20" high="27" type="a6xx_vtx_fmt"/>
2570                         <bitfield name="SWAP" low="28" high="29" type="a3xx_color_swap"/>
2571                         <bitfield name="UNK30" pos="30" type="boolean"/>
2572                         <bitfield name="FLOAT" pos="31" type="boolean"/>
2573                 </reg32>
2574                 <reg32 offset="0x1" name="STEP_RATE"/>
2575         </array>
2576         <array offset="0xa0d0" name="VFD_DEST_CNTL" stride="1" length="32">
2577                 <reg32 offset="0x0" name="INSTR">
2578                         <bitfield name="WRITEMASK" low="0" high="3" type="hex"/>
2579                         <bitfield name="REGID" low="4" high="11" type="a3xx_regid"/>
2580                 </reg32>
2581         </array>
2582
2583         <!-- always 0x1 ? -->
2584         <reg32 offset="0xa0f8" name="SP_UNKNOWN_A0F8"/>
2585
2586         <reg32 offset="0xa802" name="SP_PRIMITIVE_CNTL">
2587                 <!-- # of VS outputs including pos/psize -->
2588                 <bitfield name="VSOUT" low="0" high="4" type="uint"/>
2589         </reg32>
2590         <array offset="0xa803" name="SP_VS_OUT" stride="1" length="16">
2591                 <reg32 offset="0x0" name="REG">
2592                         <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
2593                         <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
2594                         <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
2595                         <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
2596                 </reg32>
2597         </array>
2598         <!--
2599         Starting with a5xx, position/psize outputs from shader end up in the
2600         SP_VS_OUT map, with highest OUTLOCn position.  (Generally they are
2601         the last entries too, except when gl_PointCoord is used, blob inserts
2602         an extra varying after, but with a lower OUTLOC position.  If present,
2603         psize is last, preceded by position.
2604          -->
2605         <array offset="0xa813" name="SP_VS_VPC_DST" stride="1" length="8">
2606                 <reg32 offset="0x0" name="REG">
2607                         <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
2608                         <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
2609                         <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
2610                         <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
2611                 </reg32>
2612         </array>
2613
2614         <bitset name="a6xx_sp_xs_ctrl_reg0" inline="yes">
2615                 <!--
2616                 When b31 set we just see FULLREGFOOTPRINT set.  The pattern of
2617                 used registers is a bit odd too:
2618                         - used (half): 0-15 68-179 (cnt=128, max=179)
2619                         - used (full): 0-33 50-69 71 73 75 77 79 81 83 85 87 89-105 107 109 111 113 115 117 119 121 123 125 127>
2620                 whereas we usually see a (mostly) contiguous range of regs used.  But if
2621                 I merge the full and half ranges (ie. rN counts as hr(N*2) and hr(N*2+1)),
2622                 then:
2623                         - used (merged): 0-191 (cnt=192, max=191)
2624                 So I think if b31 is set, then the half precision registers overlap
2625                 the full precision registers.  (Which seems like a pretty sensible
2626                 feature, actually I'm not sure when you *wouldn't* want to use that,
2627                 since it gives register allocation more flexibility)
2628                  -->
2629                 <bitfield name="HALFREGFOOTPRINT" low="1" high="6" type="uint"/>
2630                 <bitfield name="FULLREGFOOTPRINT" low="7" high="12" type="uint"/>
2631                 <!-- seems to be nesting level for flow control:.. -->
2632                 <bitfield name="BRANCHSTACK" low="14" high="19" type="uint"/>
2633                 <bitfield name="THREADSIZE" pos="20" type="a3xx_threadsize"/>
2634                 <bitfield name="VARYING" pos="22" type="boolean"/>
2635                 <bitfield name="PIXLODENABLE" pos="26" type="boolean"/>
2636                 <bitfield name="MERGEDREGS" pos="31" type="boolean"/>
2637         </bitset>
2638
2639         <bitset name="a6xx_sp_xs_config" inline="yes">
2640                 <bitfield name="ENABLED" pos="8" type="boolean"/>
2641                 <!--
2642                 number of textures and samplers.. these might be swapped, with GL I
2643                 always see the same value for both.
2644                  -->
2645                 <bitfield name="NTEX" low="9" high="16" type="uint"/>
2646                 <bitfield name="NSAMP" low="17" high="21" type="uint"/>
2647                 <bitfield name="NIBO" low="22" high="29" type="uint"/>
2648         </bitset>
2649
2650         <reg32 offset="0xa800" name="SP_VS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2651         <reg32 offset="0xa81b" name="SP_UNKNOWN_A81B"/>
2652         <reg32 offset="0xa81c" name="SP_VS_OBJ_START_LO"/>
2653         <reg32 offset="0xa81d" name="SP_VS_OBJ_START_HI"/>
2654         <reg32 offset="0xa822" name="SP_VS_TEX_COUNT" type="uint"/>
2655         <reg32 offset="0xa823" name="SP_VS_CONFIG" type="a6xx_sp_xs_config"/>
2656         <reg32 offset="0xa824" name="SP_VS_INSTRLEN" type="uint"/>
2657
2658         <reg32 offset="0xa830" name="SP_HS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2659         <reg32 offset="0xa831" name="SP_HS_UNKNOWN_A831"/>
2660         <reg32 offset="0xa833" name="SP_HS_UNKNOWN_A833"/>
2661         <reg32 offset="0xa834" name="SP_HS_OBJ_START_LO"/>
2662         <reg32 offset="0xa835" name="SP_HS_OBJ_START_HI"/>
2663         <reg32 offset="0xa83a" name="SP_HS_TEX_COUNT" type="uint"/>
2664         <reg32 offset="0xa83b" name="SP_HS_CONFIG" type="a6xx_sp_xs_config"/>
2665         <reg32 offset="0xa83c" name="SP_HS_INSTRLEN" type="uint"/>
2666
2667         <reg32 offset="0xa840" name="SP_DS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2668         <reg32 offset="0xa842" name="SP_DS_PRIMITIVE_CNTL">
2669                 <!-- # of DS outputs including pos/psize -->
2670                 <bitfield name="DSOUT" low="0" high="4" type="uint"/>
2671         </reg32>
2672         <array offset="0xa843" name="SP_DS_OUT" stride="1" length="16">
2673                 <reg32 offset="0x0" name="REG">
2674                         <bitfield name="A_REGID" low="0" high="7" type="a3xx_regid"/>
2675                         <bitfield name="A_COMPMASK" low="8" high="11" type="hex"/>
2676                         <bitfield name="B_REGID" low="16" high="23" type="a3xx_regid"/>
2677                         <bitfield name="B_COMPMASK" low="24" high="27" type="hex"/>
2678                 </reg32>
2679         </array>
2680         <array offset="0xa853" name="SP_DS_VPC_DST" stride="1" length="8">
2681                 <reg32 offset="0x0" name="REG">
2682                         <bitfield name="OUTLOC0" low="0" high="7" type="uint"/>
2683                         <bitfield name="OUTLOC1" low="8" high="15" type="uint"/>
2684                         <bitfield name="OUTLOC2" low="16" high="23" type="uint"/>
2685                         <bitfield name="OUTLOC3" low="24" high="31" type="uint"/>
2686                 </reg32>
2687         </array>
2688
2689         <reg32 offset="0xa85b" name="SP_DS_UNKNOWN_A85B"/>
2690         <reg32 offset="0xa85c" name="SP_DS_OBJ_START_LO"/>
2691         <reg32 offset="0xa85d" name="SP_DS_OBJ_START_HI"/>
2692         <reg32 offset="0xa862" name="SP_DS_TEX_COUNT" type="uint"/>
2693         <reg32 offset="0xa863" name="SP_DS_CONFIG" type="a6xx_sp_xs_config"/>
2694         <reg32 offset="0xa864" name="SP_DS_INSTRLEN" type="uint"/>
2695
2696         <reg32 offset="0xa870" name="SP_GS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2697         <reg32 offset="0xa871" name="SP_GS_UNKNOWN_A871"/>
2698         <reg32 offset="0xa88d" name="SP_GS_OBJ_START_LO"/>
2699         <reg32 offset="0xa88e" name="SP_GS_OBJ_START_HI"/>
2700         <reg32 offset="0xa893" name="SP_GS_TEX_COUNT" type="uint"/>
2701         <reg32 offset="0xa894" name="SP_GS_CONFIG" type="a6xx_sp_xs_config"/>
2702         <reg32 offset="0xa895" name="SP_GS_INSTRLEN" type="uint"/>
2703
2704         <reg32 offset="0xa8a0" name="SP_VS_TEX_SAMP_LO"/>
2705         <reg32 offset="0xa8a1" name="SP_VS_TEX_SAMP_HI"/>
2706         <reg32 offset="0xa8a2" name="SP_HS_TEX_SAMP_LO"/>
2707         <reg32 offset="0xa8a3" name="SP_HS_TEX_SAMP_HI"/>
2708         <reg32 offset="0xa8a4" name="SP_DS_TEX_SAMP_LO"/>
2709         <reg32 offset="0xa8a5" name="SP_DS_TEX_SAMP_HI"/>
2710         <reg32 offset="0xa8a6" name="SP_GS_TEX_SAMP_LO"/>
2711         <reg32 offset="0xa8a7" name="SP_GS_TEX_SAMP_HI"/>
2712         <reg32 offset="0xa8a8" name="SP_VS_TEX_CONST_LO"/>
2713         <reg32 offset="0xa8a9" name="SP_VS_TEX_CONST_HI"/>
2714         <reg32 offset="0xa8aa" name="SP_HS_TEX_CONST_LO"/>
2715         <reg32 offset="0xa8ab" name="SP_HS_TEX_CONST_HI"/>
2716         <reg32 offset="0xa8ac" name="SP_DS_TEX_CONST_LO"/>
2717         <reg32 offset="0xa8ad" name="SP_DS_TEX_CONST_HI"/>
2718         <reg32 offset="0xa8ae" name="SP_GS_TEX_CONST_LO"/>
2719         <reg32 offset="0xa8af" name="SP_GS_TEX_CONST_HI"/>
2720
2721         <reg32 offset="0xa980" name="SP_FS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2722         <reg32 offset="0xa982" name="SP_UNKNOWN_A982"/>
2723         <reg32 offset="0xa983" name="SP_FS_OBJ_START_LO"/>
2724         <reg32 offset="0xa984" name="SP_FS_OBJ_START_HI"/>
2725
2726         <reg32 offset="0xa989" name="SP_BLEND_CNTL">
2727                 <bitfield name="ENABLED" pos="0" type="boolean"/>
2728                 <bitfield name="UNK8" pos="8" type="boolean"/>
2729                 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
2730         </reg32>
2731         <reg32 offset="0xa98a" name="SP_SRGB_CNTL">
2732                 <!-- Same as RB_SRGB_CNTL -->
2733                 <bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
2734                 <bitfield name="SRGB_MRT1" pos="1" type="boolean"/>
2735                 <bitfield name="SRGB_MRT2" pos="2" type="boolean"/>
2736                 <bitfield name="SRGB_MRT3" pos="3" type="boolean"/>
2737                 <bitfield name="SRGB_MRT4" pos="4" type="boolean"/>
2738                 <bitfield name="SRGB_MRT5" pos="5" type="boolean"/>
2739                 <bitfield name="SRGB_MRT6" pos="6" type="boolean"/>
2740                 <bitfield name="SRGB_MRT7" pos="7" type="boolean"/>
2741         </reg32>
2742         <reg32 offset="0xa98b" name="SP_FS_RENDER_COMPONENTS">
2743                 <bitfield name="RT0" low="0" high="3"/>
2744                 <bitfield name="RT1" low="4" high="7"/>
2745                 <bitfield name="RT2" low="8" high="11"/>
2746                 <bitfield name="RT3" low="12" high="15"/>
2747                 <bitfield name="RT4" low="16" high="19"/>
2748                 <bitfield name="RT5" low="20" high="23"/>
2749                 <bitfield name="RT6" low="24" high="27"/>
2750                 <bitfield name="RT7" low="28" high="31"/>
2751         </reg32>
2752         <reg32 offset="0xa98c" name="SP_FS_OUTPUT_CNTL0">
2753                 <bitfield name="DEPTH_REGID" low="8" high="15" type="a3xx_regid"/>
2754                 <bitfield name="SAMPMASK_REGID" low="16" high="23" type="a3xx_regid"/>
2755         </reg32>
2756         <reg32 offset="0xa98d" name="SP_FS_OUTPUT_CNTL1">
2757                 <bitfield name="MRT" low="0" high="3" type="uint"/>
2758         </reg32>
2759
2760         <array offset="0xa996" name="SP_FS_MRT" stride="1" length="8">
2761                 <reg32 offset="0" name="REG">
2762                         <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_color_fmt"/>
2763                         <bitfield name="COLOR_SINT" pos="8" type="boolean"/>
2764                         <bitfield name="COLOR_UINT" pos="9" type="boolean"/>
2765                 </reg32>
2766         </array>
2767
2768         <reg32 offset="0xa99e" name="SP_UNKNOWN_A99E"/>
2769
2770         <reg32 offset="0xa9a7" name="SP_FS_TEX_COUNT" type="uint"/>
2771
2772         <!-- always 0x0 ? -->
2773         <reg32 offset="0xa9a8" name="SP_UNKNOWN_A9A8"/>
2774
2775         <!-- set for compute shaders, always 0x41 -->
2776         <reg32 offset="0xa9b1" name="SP_CS_UNKNOWN_A9B1" type="uint"/>
2777
2778         <!-- set for compute shaders, always 0x0 -->
2779         <reg32 offset="0xa9b3" name="SP_CS_UNKNOWN_A9B3" type="uint"/>
2780
2781         <reg32 offset="0xa9ba" name="SP_CS_TEX_COUNT" type="uint"/>
2782
2783         <reg32 offset="0xa9e0" name="SP_FS_TEX_SAMP_LO"/>
2784         <reg32 offset="0xa9e1" name="SP_FS_TEX_SAMP_HI"/>
2785         <reg32 offset="0xa9e2" name="SP_CS_TEX_SAMP_LO"/>
2786         <reg32 offset="0xa9e3" name="SP_CS_TEX_SAMP_HI"/>
2787         <reg32 offset="0xa9e4" name="SP_FS_TEX_CONST_LO"/>
2788         <reg32 offset="0xa9e5" name="SP_FS_TEX_CONST_HI"/>
2789         <reg32 offset="0xa9e6" name="SP_CS_TEX_CONST_LO"/>
2790         <reg32 offset="0xa9e7" name="SP_CS_TEX_CONST_HI"/>
2791
2792         <array offset="0xa98e" name="SP_FS_OUTPUT" stride="1" length="8">
2793                 <doc>per MRT</doc>
2794                 <reg32 offset="0x0" name="REG">
2795                         <bitfield name="REGID" low="0" high="7" type="a3xx_regid"/>
2796                         <bitfield name="HALF_PRECISION" pos="8" type="boolean"/>
2797                 </reg32>
2798         </array>
2799
2800         <reg32 offset="0xa9b0" name="SP_CS_CTRL_REG0" type="a6xx_sp_xs_ctrl_reg0"/>
2801         <reg32 offset="0xa9b4" name="SP_CS_OBJ_START_LO"/>
2802         <reg32 offset="0xa9b5" name="SP_CS_OBJ_START_HI"/>
2803         <reg32 offset="0xa9bb" name="SP_CS_CONFIG" type="a6xx_sp_xs_config"/>
2804         <reg32 offset="0xa9bc" name="SP_CS_INSTRLEN" type="uint"/>
2805
2806         <!--
2807         IBO state for compute shader:
2808          -->
2809         <reg32 offset="0xa9f2" name="SP_CS_IBO_LO"/>
2810         <reg32 offset="0xa9f3" name="SP_CS_IBO_HI"/>
2811         <reg32 offset="0xaa00" name="SP_CS_IBO_COUNT" type="uint"/>
2812
2813         <!-- always 0x5 ? -->
2814         <reg32 offset="0xab00" name="SP_UNKNOWN_AB00"/>
2815
2816         <reg32 offset="0xab04" name="SP_FS_CONFIG" type="a6xx_sp_xs_config"/>
2817         <reg32 offset="0xab05" name="SP_FS_INSTRLEN" type="uint"/>
2818
2819         <!--
2820         Combined IBO state for 3d pipe, used for Image and SSBO write/atomic
2821         instructions VS/HS/DS/GS/FS.  See SP_CS_IBO_* for compute shaders.
2822          -->
2823         <reg32 offset="0xab1a" name="SP_IBO_LO"/>
2824         <reg32 offset="0xab1b" name="SP_IBO_HI"/>
2825         <reg32 offset="0xab20" name="SP_IBO_COUNT" type="uint"/>
2826
2827         <!--
2828         I believe this describes the src format, but haven't seen traces with
2829         src_format != dst_format
2830          -->
2831         <reg32 offset="0xacc0" name="SP_2D_SRC_FORMAT">
2832                 <bitfield name="NORM" pos="0" type="boolean"/>
2833                 <bitfield name="SINT" pos="1" type="boolean"/>
2834                 <bitfield name="UINT" pos="2" type="boolean"/>
2835                 <bitfield name="COLOR_FORMAT" low="3" high="10" type="a6xx_color_fmt"/>
2836         </reg32>
2837
2838         <!-- always 0x0 -->
2839         <reg32 offset="0xae00" name="SP_UNKNOWN_AE00"/>
2840
2841         <reg32 offset="0xae03" name="SP_UNKNOWN_AE03"/>
2842         <reg32 offset="0xae04" name="SP_UNKNOWN_AE04"/>
2843
2844         <!-- always 0x3f ? -->
2845         <reg32 offset="0xae0f" name="SP_UNKNOWN_AE0F"/>
2846
2847         <!-- always 0x0 ? -->
2848         <reg32 offset="0xb182" name="SP_UNKNOWN_B182"/>
2849         <reg32 offset="0xb183" name="SP_UNKNOWN_B183"/>
2850
2851         <!-- could be all the stuff below here is actually TPL1?? -->
2852
2853         <reg32 offset="0xb300" name="SP_TP_RAS_MSAA_CNTL">
2854                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
2855         </reg32>
2856         <reg32 offset="0xb301" name="SP_TP_DEST_MSAA_CNTL">
2857                 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
2858                 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
2859         </reg32>
2860
2861         <!-- looks to work in the same way as a5xx: -->
2862         <reg32 offset="0xb302" name="SP_TP_BORDER_COLOR_BASE_ADDR_LO"/>
2863         <reg32 offset="0xb303" name="SP_TP_BORDER_COLOR_BASE_ADDR_HI"/>
2864         <!-- always 0x0 ? -->
2865         <reg32 offset="0xb304" name="SP_TP_UNKNOWN_B304"/>
2866
2867         <reg32 offset="0xb309" name="SP_TP_UNKNOWN_B309"/>
2868
2869         <!--
2870         Equiv to corresponding RB_2D_SRC_* regs on a5xx.. which were either
2871         badly named or the functionality moved in a6xx.  But downstream kernel
2872         calls this "a6xx_sp_ps_tp_2d_cluster"
2873          -->
2874         <reg32 offset="0xb4c0" name="SP_PS_2D_SRC_INFO">
2875                 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_color_fmt"/>
2876                 <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
2877                 <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
2878                 <!-- b12 seems to be set when UBWC "FLAGS" buffer enabled -->
2879                 <bitfield name="FLAGS" pos="12" type="boolean"/>
2880                 <bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/>
2881                 <bitfield name="FILTER" pos="16" type="boolean"/>
2882         </reg32>
2883         <reg32 offset="0xb4c1" name="SP_PS_2D_SRC_SIZE">
2884                 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
2885                 <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
2886         </reg32>
2887         <reg32 offset="0xb4c2" name="SP_PS_2D_SRC_LO"/>
2888         <reg32 offset="0xb4c3" name="SP_PS_2D_SRC_HI"/>
2889         <reg32 offset="0xb4c4" name="SP_PS_2D_SRC_PITCH">
2890            <bitfield name="PITCH" low="9" high="24" shr="6" type="uint"/>
2891         </reg32>
2892
2893         <reg32 offset="0xb4ca" name="SP_PS_2D_SRC_FLAGS_LO"/>
2894         <reg32 offset="0xb4cb" name="SP_PS_2D_SRC_FLAGS_HI"/>
2895         <reg32 offset="0xb4cc" name="SP_PS_2D_SRC_FLAGS_PITCH">
2896                 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2897                 <bitfield name="ARRAY_PITCH" low="11" high="21" shr="7" type="uint"/>
2898         </reg32>
2899
2900         <!-- always 0x00100000 ? -->
2901         <reg32 offset="0xb600" name="SP_UNKNOWN_B600"/>
2902
2903         <!-- always 0x44 ? -->
2904         <reg32 offset="0xb605" name="SP_UNKNOWN_B605"/>
2905
2906         <bitset name="a6xx_hlsq_xs_cntl" inline="yes">
2907                 <bitfield name="CONSTLEN" low="0" high="7" shr="2" type="uint"/>
2908                 <bitfield name="ENABLED" pos="8" type="boolean"/>
2909         </bitset>
2910
2911         <reg32 offset="0xb800" name="HLSQ_VS_CNTL" type="a6xx_hlsq_xs_cntl"/>
2912         <reg32 offset="0xb801" name="HLSQ_HS_CNTL" type="a6xx_hlsq_xs_cntl"/>
2913         <reg32 offset="0xb802" name="HLSQ_DS_CNTL" type="a6xx_hlsq_xs_cntl"/>
2914         <reg32 offset="0xb803" name="HLSQ_GS_CNTL" type="a6xx_hlsq_xs_cntl"/>
2915
2916         <reg32 offset="0xb980" name="HLSQ_UNKNOWN_B980"/>
2917
2918         <reg32 offset="0xb982" name="HLSQ_CONTROL_1_REG">
2919                 <!-- always 0x7 ? -->
2920         </reg32>
2921         <reg32 offset="0xb983" name="HLSQ_CONTROL_2_REG">
2922                 <bitfield name="FACEREGID" low="0" high="7" type="a3xx_regid"/>
2923                 <!-- SAMPLEID is loaded into a half-precision register: -->
2924                 <bitfield name="SAMPLEID" low="8" high="15" type="a3xx_regid"/>
2925                 <bitfield name="SAMPLEMASK" low="16" high="23" type="a3xx_regid"/>
2926                 <!--
2927                 SIZE is the "size" of the primitive, ie. what the i/j coords need
2928                 to be divided by to scale to a single fragment.  It is probably
2929                 the longer of the two lines that form the tri (ie v0v1 and v0v2)?
2930                  -->
2931                 <bitfield name="SIZE" low="24" high="31" type="a3xx_regid"/>
2932         </reg32>
2933         <reg32 offset="0xb984" name="HLSQ_CONTROL_3_REG">
2934                 <!-- register loaded with position (bary.f) -->
2935                 <bitfield name="BARY_IJ_PIXEL" low="0" high="7" type="a3xx_regid"/>
2936                 <bitfield name="BARY_IJ_CENTROID" low="16" high="23" type="a3xx_regid"/>
2937         </reg32>
2938         <reg32 offset="0xb985" name="HLSQ_CONTROL_4_REG">
2939                 <bitfield name="BARY_IJ_PIXEL_PERSAMP" low="0" high="7" type="a3xx_regid"/>
2940                 <bitfield name="XYCOORDREGID" low="16" high="23" type="a3xx_regid"/>
2941                 <bitfield name="ZWCOORDREGID" low="24" high="31" type="a3xx_regid"/>
2942         </reg32>
2943         <reg32 offset="0xb986" name="HLSQ_CONTROL_5_REG">
2944                 <!-- unknown regid in low 8b -->
2945         </reg32>
2946         <reg32 offset="0xb987" name="HLSQ_CS_CNTL" type="a6xx_hlsq_xs_cntl"/>
2947
2948         <reg32 offset="0xb990" name="HLSQ_CS_NDRANGE_0">
2949                 <bitfield name="KERNELDIM" low="0" high="1" type="uint"/>
2950                 <!-- localsize is value minus one: -->
2951                 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
2952                 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
2953                 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
2954         </reg32>
2955         <reg32 offset="0xb991" name="HLSQ_CS_NDRANGE_1">
2956                 <bitfield name="GLOBALSIZE_X" low="0" high="31" type="uint"/>
2957         </reg32>
2958         <reg32 offset="0xb992" name="HLSQ_CS_NDRANGE_2">
2959                 <bitfield name="GLOBALOFF_X" low="0" high="31" type="uint"/>
2960         </reg32>
2961         <reg32 offset="0xb993" name="HLSQ_CS_NDRANGE_3">
2962                 <bitfield name="GLOBALSIZE_Y" low="0" high="31" type="uint"/>
2963         </reg32>
2964         <reg32 offset="0xb994" name="HLSQ_CS_NDRANGE_4">
2965                 <bitfield name="GLOBALOFF_Y" low="0" high="31" type="uint"/>
2966         </reg32>
2967         <reg32 offset="0xb995" name="HLSQ_CS_NDRANGE_5">
2968                 <bitfield name="GLOBALSIZE_Z" low="0" high="31" type="uint"/>
2969         </reg32>
2970         <reg32 offset="0xb996" name="HLSQ_CS_NDRANGE_6">
2971                 <bitfield name="GLOBALOFF_Z" low="0" high="31" type="uint"/>
2972         </reg32>
2973         <reg32 offset="0xb997" name="HLSQ_CS_CNTL_0">
2974                 <bitfield name="WGIDCONSTID" low="0" high="7" type="a3xx_regid"/>
2975                 <bitfield name="UNK0" low="8" high="15" type="a3xx_regid"/>
2976                 <bitfield name="UNK1" low="16" high="23" type="a3xx_regid"/>
2977                 <bitfield name="LOCALIDREGID" low="24" high="31" type="a3xx_regid"/>
2978         </reg32>
2979         <reg32 offset="0xb998" name="HLSQ_CS_UNKNOWN_B998"/> <!-- always 0x2fc -->
2980         <reg32 offset="0xb999" name="HLSQ_CS_KERNEL_GROUP_X"/>
2981         <reg32 offset="0xb99a" name="HLSQ_CS_KERNEL_GROUP_Y"/>
2982         <reg32 offset="0xb99b" name="HLSQ_CS_KERNEL_GROUP_Z"/>
2983
2984         <!-- probably: -->
2985         <reg32 offset="0xbb08" name="HLSQ_UPDATE_CNTL"/>
2986
2987         <reg32 offset="0xbb10" name="HLSQ_FS_CNTL" type="a6xx_hlsq_xs_cntl"/>
2988
2989         <!-- always 0x0 ? -->
2990         <reg32 offset="0xbb11" name="HLSQ_UNKNOWN_BB11"/>
2991
2992         <!-- always 0x80 ? -->
2993         <reg32 offset="0xbe00" name="HLSQ_UNKNOWN_BE00"/>
2994         <!-- always 0x0 ? -->
2995         <reg32 offset="0xbe01" name="HLSQ_UNKNOWN_BE01"/>
2996         <!-- always 0x0 ? -->
2997         <reg32 offset="0xbe04" name="HLSQ_UNKNOWN_BE04"/>
2998
2999 </domain>
3000
3001 <!-- Seems basically the same as a5xx, maybe move to common.xml.. -->
3002 <domain name="A6XX_TEX_SAMP" width="32">
3003         <doc>Texture sampler dwords</doc>
3004         <enum name="a6xx_tex_filter"> <!-- same as a4xx? -->
3005                 <value name="A6XX_TEX_NEAREST" value="0"/>
3006                 <value name="A6XX_TEX_LINEAR" value="1"/>
3007                 <value name="A6XX_TEX_ANISO" value="2"/>
3008         </enum>
3009         <enum name="a6xx_tex_clamp"> <!-- same as a4xx? -->
3010                 <value name="A6XX_TEX_REPEAT" value="0"/>
3011                 <value name="A6XX_TEX_CLAMP_TO_EDGE" value="1"/>
3012                 <value name="A6XX_TEX_MIRROR_REPEAT" value="2"/>
3013                 <value name="A6XX_TEX_CLAMP_TO_BORDER" value="3"/>
3014                 <value name="A6XX_TEX_MIRROR_CLAMP" value="4"/>
3015         </enum>
3016         <enum name="a6xx_tex_aniso"> <!-- same as a4xx? -->
3017                 <value name="A6XX_TEX_ANISO_1" value="0"/>
3018                 <value name="A6XX_TEX_ANISO_2" value="1"/>
3019                 <value name="A6XX_TEX_ANISO_4" value="2"/>
3020                 <value name="A6XX_TEX_ANISO_8" value="3"/>
3021                 <value name="A6XX_TEX_ANISO_16" value="4"/>
3022         </enum>
3023         <reg32 offset="0" name="0">
3024                 <bitfield name="MIPFILTER_LINEAR_NEAR" pos="0" type="boolean"/>
3025                 <bitfield name="XY_MAG" low="1" high="2" type="a6xx_tex_filter"/>
3026                 <bitfield name="XY_MIN" low="3" high="4" type="a6xx_tex_filter"/>
3027                 <bitfield name="WRAP_S" low="5" high="7" type="a6xx_tex_clamp"/>
3028                 <bitfield name="WRAP_T" low="8" high="10" type="a6xx_tex_clamp"/>
3029                 <bitfield name="WRAP_R" low="11" high="13" type="a6xx_tex_clamp"/>
3030                 <bitfield name="ANISO" low="14" high="16" type="a6xx_tex_aniso"/>
3031                 <bitfield name="LOD_BIAS" low="19" high="31" type="fixed" radix="8"/><!-- no idea how many bits for real -->
3032         </reg32>
3033         <reg32 offset="1" name="1">
3034                 <bitfield name="COMPARE_FUNC" low="1" high="3" type="adreno_compare_func"/>
3035                 <bitfield name="CUBEMAPSEAMLESSFILTOFF" pos="4" type="boolean"/>
3036                 <bitfield name="UNNORM_COORDS" pos="5" type="boolean"/>
3037                 <bitfield name="MIPFILTER_LINEAR_FAR" pos="6" type="boolean"/>
3038                 <bitfield name="MAX_LOD" low="8" high="19" type="ufixed" radix="8"/>
3039                 <bitfield name="MIN_LOD" low="20" high="31" type="ufixed" radix="8"/>
3040         </reg32>
3041         <reg32 offset="2" name="2">
3042                 <bitfield name="BCOLOR_OFFSET" low="0" high="31"/>
3043         </reg32>
3044         <reg32 offset="3" name="3"/>
3045 </domain>
3046
3047 <domain name="A6XX_TEX_CONST" width="32">
3048         <doc>Texture constant dwords</doc>
3049         <enum name="a6xx_tex_swiz"> <!-- same as a4xx? -->
3050                 <value name="A6XX_TEX_X" value="0"/>
3051                 <value name="A6XX_TEX_Y" value="1"/>
3052                 <value name="A6XX_TEX_Z" value="2"/>
3053                 <value name="A6XX_TEX_W" value="3"/>
3054                 <value name="A6XX_TEX_ZERO" value="4"/>
3055                 <value name="A6XX_TEX_ONE" value="5"/>
3056         </enum>
3057         <enum name="a6xx_tex_type"> <!-- same as a4xx? -->
3058                 <value name="A6XX_TEX_1D" value="0"/>
3059                 <value name="A6XX_TEX_2D" value="1"/>
3060                 <value name="A6XX_TEX_CUBE" value="2"/>
3061                 <value name="A6XX_TEX_3D" value="3"/>
3062         </enum>
3063         <reg32 offset="0" name="0">
3064                 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
3065                 <bitfield name="SRGB" pos="2" type="boolean"/>
3066                 <bitfield name="SWIZ_X" low="4" high="6" type="a6xx_tex_swiz"/>
3067                 <bitfield name="SWIZ_Y" low="7" high="9" type="a6xx_tex_swiz"/>
3068                 <bitfield name="SWIZ_Z" low="10" high="12" type="a6xx_tex_swiz"/>
3069                 <bitfield name="SWIZ_W" low="13" high="15" type="a6xx_tex_swiz"/>
3070                 <bitfield name="MIPLVLS" low="16" high="19" type="uint"/>
3071                 <bitfield name="SAMPLES" low="20" high="21" type="a3xx_msaa_samples"/>
3072                 <bitfield name="FMT" low="22" high="29" type="a6xx_tex_fmt"/>
3073                 <bitfield name="SWAP" low="30" high="31" type="a3xx_color_swap"/>
3074         </reg32>
3075         <reg32 offset="1" name="1">
3076                 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
3077                 <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
3078         </reg32>
3079         <reg32 offset="2" name="2">
3080                 <!--
3081                 b4 and b31 set for buffer/ssbo case, in which case low 15 bits
3082                 of size encoded in WIDTH, and high 15 bits encoded in HEIGHT
3083
3084                 b31 is probably the 'BUFFER' bit.. it is the one that changes
3085                 behavior of texture in dEQP-GLES31.functional.texture.texture_buffer.render.as_fragment_texture.buffer_size_131071
3086                  -->
3087                 <bitfield name="UNK4" pos="4" type="boolean"/>
3088                 <bitfield name="FETCHSIZE" low="0" high="3" type="a6xx_tex_fetchsize"/>
3089                 <doc>Pitch in bytes (so actually stride)</doc>
3090                 <bitfield name="PITCH" low="7" high="28" type="uint"/>
3091                 <bitfield name="TYPE" low="29" high="30" type="a6xx_tex_type"/>
3092                 <bitfield name="UNK31" pos="31" type="boolean"/>
3093         </reg32>
3094         <reg32 offset="3" name="3">
3095                 <!--
3096                 ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and
3097                 for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the
3098                 layer size at the point that it stops being reduced moving to
3099                 higher (smaller) mipmap levels
3100                  -->
3101                 <bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/>
3102                 <bitfield name="MIN_LAYERSZ" low="23" high="26" shr="12"/>
3103                 <bitfield name="UNK27" pos="27" type="boolean"/>
3104                 <bitfield name="FLAG" pos="28" type="boolean"/>
3105         </reg32>
3106         <reg32 offset="4" name="4">
3107                 <bitfield name="BASE_LO" low="5" high="31" shr="5"/>
3108         </reg32>
3109         <reg32 offset="5" name="5">
3110                 <bitfield name="BASE_HI" low="0" high="16"/>
3111                 <bitfield name="DEPTH" low="17" high="29" type="uint"/>
3112         </reg32>
3113         <reg32 offset="6" name="6"/>
3114         <reg32 offset="7" name="7">
3115                 <bitfield name="FLAG_LO" low="5" high="31" shr="5"/>
3116         </reg32>
3117         <reg32 offset="8" name="8">
3118                 <bitfield name="FLAG_HI" low="0" high="16"/>
3119         </reg32>
3120         <reg32 offset="9" name="9">
3121                 <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
3122         </reg32>
3123         <reg32 offset="10" name="10">
3124                 <!--
3125                 I see some other bits set by blob above FLAG_BUFFER_PITCH, but they
3126                 don't seem to be particularly sensible... or needed for UBWC to work
3127                  -->
3128                 <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
3129         </reg32>
3130         <reg32 offset="11" name="11"/>
3131         <reg32 offset="12" name="12"/>
3132         <reg32 offset="13" name="13"/>
3133         <reg32 offset="14" name="14"/>
3134         <reg32 offset="15" name="15"/>
3135 </domain>
3136
3137 <!--
3138 Note the "SSBO" state blocks are actually used for both images and SSBOs,
3139 naming is just because I r/e'd SSBOs first.  I should probably come up
3140 with a better name.
3141 -->
3142 <domain name="A6XX_IBO" width="32">
3143         <reg32 offset="0" name="0">
3144                 <!--
3145                 NOTE: same position as in TEX_CONST state.. I don't see other bits
3146                 used but if they are good chance position is same as TEX_CONST
3147                  -->
3148                 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
3149                 <bitfield name="FMT" low="22" high="29" type="a6xx_tex_fmt"/>
3150         </reg32>
3151         <reg32 offset="1" name="1">
3152                 <bitfield name="WIDTH" low="0" high="14" type="uint"/>
3153                 <bitfield name="HEIGHT" low="15" high="29" type="uint"/>
3154         </reg32>
3155         <reg32 offset="2" name="2">
3156                 <!--
3157                 b4 and b31 set for buffer/ssbo case, in which case low 15 bits
3158                 of size encoded in WIDTH, and high 15 bits encoded in HEIGHT
3159                  -->
3160                 <bitfield name="UNK4" pos="4" type="boolean"/>
3161                 <doc>Pitch in bytes (so actually stride)</doc>
3162                 <bitfield name="PITCH" low="7" high="28" type="uint"/>
3163                 <bitfield name="TYPE" low="29" high="30" type="a6xx_tex_type"/>
3164                 <bitfield name="UNK31" pos="31" type="boolean"/>
3165         </reg32>
3166         <reg32 offset="3" name="3">
3167                 <!--
3168                 ARRAY_PITCH is basically LAYERSZ for the first mipmap level, and
3169                 for 3d textures (laid out mipmap level first) MIN_LAYERSZ is the
3170                 layer size at the point that it stops being reduced moving to
3171                 higher (smaller) mipmap levels
3172                  -->
3173                 <bitfield name="ARRAY_PITCH" low="0" high="13" shr="12" type="uint"/>
3174                 <bitfield name="UNK27" pos="27" type="boolean"/>
3175                 <bitfield name="FLAG" pos="28" type="boolean"/>
3176         </reg32>
3177         <reg32 offset="4" name="4">
3178                 <bitfield name="BASE_LO" low="0" high="31"/>
3179         </reg32>
3180         <reg32 offset="5" name="5">
3181                 <bitfield name="BASE_HI" low="0" high="16"/>
3182                 <bitfield name="DEPTH" low="17" high="29" type="uint"/>
3183         </reg32>
3184         <reg32 offset="6" name="6">
3185         </reg32>
3186         <reg32 offset="7" name="7">
3187         </reg32>
3188         <reg32 offset="8" name="8">
3189         </reg32>
3190         <reg32 offset="9" name="9">
3191                 <bitfield name="FLAG_BUFFER_ARRAY_PITCH" low="0" high="16" shr="4" type="uint"/>
3192         </reg32>
3193         <reg32 offset="10" name="10">
3194                 <!--
3195                 I see some other bits set by blob above FLAG_BUFFER_PITCH, but they
3196                 don't seem to be particularly sensible... or needed for UBWC to work
3197                  -->
3198                 <bitfield name="FLAG_BUFFER_PITCH" low="0" high="6" shr="6" type="uint"/>
3199         </reg32>
3200 </domain>
3201
3202 <domain name="A6XX_UBO" width="32">
3203         <reg32 offset="0" name="0">
3204                 <bitfield name="BASE_LO" low="0" high="31"/>
3205         </reg32>
3206         <reg32 offset="1" name="1">
3207                 <bitfield name="BASE_HI" low="0" high="16"/>
3208                 <!-- size probably in high bits -->
3209         </reg32>
3210 </domain>
3211
3212 <domain name="CP_UNK_A6XX_55" width="32">
3213         <reg32 offset="0" name="0">
3214                 <bitfield name="BASE_LO" low="0" high="31"/>
3215         </reg32>
3216         <reg32 offset="1" name="1">
3217                 <bitfield name="BASE_HI" low="0" high="16"/>
3218         </reg32>
3219         <reg32 offset="2" name="2">
3220                 <bitfield name="SIZE" low="0" high="15"/>
3221         </reg32>
3222 </domain>
3223
3224 <domain name="A6XX_PDC" width="32">
3225         <reg32 offset="0x1140" name="GPU_ENABLE_PDC"/>
3226         <reg32 offset="0x1148" name="GPU_SEQ_START_ADDR"/>
3227         <reg32 offset="0x1540" name="GPU_TCS0_CONTROL"/>
3228         <reg32 offset="0x1541" name="GPU_TCS0_CMD_ENABLE_BANK"/>
3229         <reg32 offset="0x1542" name="GPU_TCS0_CMD_WAIT_FOR_CMPL_BANK"/>
3230         <reg32 offset="0x1543" name="GPU_TCS0_CMD0_MSGID"/>
3231         <reg32 offset="0x1544" name="GPU_TCS0_CMD0_ADDR"/>
3232         <reg32 offset="0x1545" name="GPU_TCS0_CMD0_DATA"/>
3233         <reg32 offset="0x1572" name="GPU_TCS1_CONTROL"/>
3234         <reg32 offset="0x1573" name="GPU_TCS1_CMD_ENABLE_BANK"/>
3235         <reg32 offset="0x1574" name="GPU_TCS1_CMD_WAIT_FOR_CMPL_BANK"/>
3236         <reg32 offset="0x1575" name="GPU_TCS1_CMD0_MSGID"/>
3237         <reg32 offset="0x1576" name="GPU_TCS1_CMD0_ADDR"/>
3238         <reg32 offset="0x1577" name="GPU_TCS1_CMD0_DATA"/>
3239         <reg32 offset="0x15A4" name="GPU_TCS2_CONTROL"/>
3240         <reg32 offset="0x15A5" name="GPU_TCS2_CMD_ENABLE_BANK"/>
3241         <reg32 offset="0x15A6" name="GPU_TCS2_CMD_WAIT_FOR_CMPL_BANK"/>
3242         <reg32 offset="0x15A7" name="GPU_TCS2_CMD0_MSGID"/>
3243         <reg32 offset="0x15A8" name="GPU_TCS2_CMD0_ADDR"/>
3244         <reg32 offset="0x15A9" name="GPU_TCS2_CMD0_DATA"/>
3245         <reg32 offset="0x15D6" name="GPU_TCS3_CONTROL"/>
3246         <reg32 offset="0x15D7" name="GPU_TCS3_CMD_ENABLE_BANK"/>
3247         <reg32 offset="0x15D8" name="GPU_TCS3_CMD_WAIT_FOR_CMPL_BANK"/>
3248         <reg32 offset="0x15D9" name="GPU_TCS3_CMD0_MSGID"/>
3249         <reg32 offset="0x15DA" name="GPU_TCS3_CMD0_ADDR"/>
3250         <reg32 offset="0x15DB" name="GPU_TCS3_CMD0_DATA"/>
3251 </domain>
3252
3253 <domain name="A6XX_PDC_GPU_SEQ" width="32">
3254         <reg32 offset="0x0" name="MEM_0"/>
3255 </domain>
3256
3257 <domain name="A6XX_CX_DBGC" width="32">
3258         <reg32 offset="0x0000" name="CFG_DBGBUS_SEL_A">
3259                 <bitfield high="7" low="0" name="PING_INDEX"/>
3260                 <bitfield high="15" low="8" name="PING_BLK_SEL"/>
3261         </reg32>
3262         <reg32 offset="0x0001" name="CFG_DBGBUS_SEL_B"/>
3263         <reg32 offset="0x0002" name="CFG_DBGBUS_SEL_C"/>
3264         <reg32 offset="0x0003" name="CFG_DBGBUS_SEL_D"/>
3265         <reg32 offset="0x0004" name="CFG_DBGBUS_CNTLT">
3266                 <bitfield high="5" low="0" name="TRACEEN"/>
3267                 <bitfield high="14" low="12" name="GRANU"/>
3268                 <bitfield high="31" low="28" name="SEGT"/>
3269         </reg32>
3270         <reg32 offset="0x0005" name="CFG_DBGBUS_CNTLM">
3271                 <bitfield high="27" low="24" name="ENABLE"/>
3272         </reg32>
3273         <reg32 offset="0x0008" name="CFG_DBGBUS_IVTL_0"/>
3274         <reg32 offset="0x0009" name="CFG_DBGBUS_IVTL_1"/>
3275         <reg32 offset="0x000a" name="CFG_DBGBUS_IVTL_2"/>
3276         <reg32 offset="0x000b" name="CFG_DBGBUS_IVTL_3"/>
3277         <reg32 offset="0x000c" name="CFG_DBGBUS_MASKL_0"/>
3278         <reg32 offset="0x000d" name="CFG_DBGBUS_MASKL_1"/>
3279         <reg32 offset="0x000e" name="CFG_DBGBUS_MASKL_2"/>
3280         <reg32 offset="0x000f" name="CFG_DBGBUS_MASKL_3"/>
3281         <reg32 offset="0x0010" name="CFG_DBGBUS_BYTEL_0">
3282                 <bitfield high="3" low="0" name="BYTEL0"/>
3283                 <bitfield high="7" low="4" name="BYTEL1"/>
3284                 <bitfield high="11" low="8" name="BYTEL2"/>
3285                 <bitfield high="15" low="12" name="BYTEL3"/>
3286                 <bitfield high="19" low="16" name="BYTEL4"/>
3287                 <bitfield high="23" low="20" name="BYTEL5"/>
3288                 <bitfield high="27" low="24" name="BYTEL6"/>
3289                 <bitfield high="31" low="28" name="BYTEL7"/>
3290         </reg32>
3291         <reg32 offset="0x0011" name="CFG_DBGBUS_BYTEL_1">
3292                 <bitfield high="3" low="0" name="BYTEL8"/>
3293                 <bitfield high="7" low="4" name="BYTEL9"/>
3294                 <bitfield high="11" low="8" name="BYTEL10"/>
3295                 <bitfield high="15" low="12" name="BYTEL11"/>
3296                 <bitfield high="19" low="16" name="BYTEL12"/>
3297                 <bitfield high="23" low="20" name="BYTEL13"/>
3298                 <bitfield high="27" low="24" name="BYTEL14"/>
3299                 <bitfield high="31" low="28" name="BYTEL15"/>
3300         </reg32>
3301
3302         <reg32 offset="0x002f" name="CFG_DBGBUS_TRACE_BUF1"/>
3303         <reg32 offset="0x0030" name="CFG_DBGBUS_TRACE_BUF2"/>
3304 </domain>
3305
3306 <domain name="A6XX_CX_MISC" width="32">
3307         <reg32 offset="0x0001" name="SYSTEM_CACHE_CNTL_0"/>
3308         <reg32 offset="0x0002" name="SYSTEM_CACHE_CNTL_1"/>
3309 </domain>
3310
3311 </database>