1e7eefb1befd4646d4bd2a400b271a82890db2e9
[mesa.git] / src / freedreno / registers / adreno / a6xx.xml
1 <?xml version="1.0" encoding="UTF-8"?>
2 <database xmlns="http://nouveau.freedesktop.org/"
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
5 <import file="freedreno_copyright.xml"/>
6 <import file="adreno/adreno_common.xml"/>
7 <import file="adreno/adreno_pm4.xml"/>
8
9 <!-- these might be same as a5xx -->
10 <enum name="a6xx_tile_mode">
11 <value name="TILE6_LINEAR" value="0"/>
12 <value name="TILE6_2" value="2"/>
13 <value name="TILE6_3" value="3"/>
14 </enum>
15
16 <enum name="a6xx_format">
17 <value value="0x02" name="FMT6_A8_UNORM"/>
18 <value value="0x03" name="FMT6_8_UNORM"/>
19 <value value="0x04" name="FMT6_8_SNORM"/>
20 <value value="0x05" name="FMT6_8_UINT"/>
21 <value value="0x06" name="FMT6_8_SINT"/>
22
23 <value value="0x08" name="FMT6_4_4_4_4_UNORM"/>
24 <value value="0x0a" name="FMT6_5_5_5_1_UNORM"/>
25 <value value="0x0c" name="FMT6_1_5_5_5_UNORM"/> <!-- read only -->
26 <value value="0x0e" name="FMT6_5_6_5_UNORM"/>
27
28 <value value="0x0f" name="FMT6_8_8_UNORM"/>
29 <value value="0x10" name="FMT6_8_8_SNORM"/>
30 <value value="0x11" name="FMT6_8_8_UINT"/>
31 <value value="0x12" name="FMT6_8_8_SINT"/>
32 <value value="0x13" name="FMT6_L8_A8_UNORM"/>
33
34 <value value="0x15" name="FMT6_16_UNORM"/>
35 <value value="0x16" name="FMT6_16_SNORM"/>
36 <value value="0x17" name="FMT6_16_FLOAT"/>
37 <value value="0x18" name="FMT6_16_UINT"/>
38 <value value="0x19" name="FMT6_16_SINT"/>
39
40 <value value="0x21" name="FMT6_8_8_8_UNORM"/>
41 <value value="0x22" name="FMT6_8_8_8_SNORM"/>
42 <value value="0x23" name="FMT6_8_8_8_UINT"/>
43 <value value="0x24" name="FMT6_8_8_8_SINT"/>
44
45 <value value="0x30" name="FMT6_8_8_8_8_UNORM"/>
46 <value value="0x31" name="FMT6_8_8_8_X8_UNORM"/> <!-- samples 1 for alpha -->
47 <value value="0x32" name="FMT6_8_8_8_8_SNORM"/>
48 <value value="0x33" name="FMT6_8_8_8_8_UINT"/>
49 <value value="0x34" name="FMT6_8_8_8_8_SINT"/>
50
51 <value value="0x35" name="FMT6_9_9_9_E5_FLOAT"/>
52
53 <value value="0x36" name="FMT6_10_10_10_2_UNORM"/>
54 <value value="0x37" name="FMT6_10_10_10_2_UNORM_DEST"/>
55 <value value="0x39" name="FMT6_10_10_10_2_SNORM"/>
56 <value value="0x3a" name="FMT6_10_10_10_2_UINT"/>
57 <value value="0x3b" name="FMT6_10_10_10_2_SINT"/>
58
59 <value value="0x42" name="FMT6_11_11_10_FLOAT"/>
60
61 <value value="0x43" name="FMT6_16_16_UNORM"/>
62 <value value="0x44" name="FMT6_16_16_SNORM"/>
63 <value value="0x45" name="FMT6_16_16_FLOAT"/>
64 <value value="0x46" name="FMT6_16_16_UINT"/>
65 <value value="0x47" name="FMT6_16_16_SINT"/>
66
67 <value value="0x48" name="FMT6_32_UNORM"/>
68 <value value="0x49" name="FMT6_32_SNORM"/>
69 <value value="0x4a" name="FMT6_32_FLOAT"/>
70 <value value="0x4b" name="FMT6_32_UINT"/>
71 <value value="0x4c" name="FMT6_32_SINT"/>
72 <value value="0x4d" name="FMT6_32_FIXED"/>
73
74 <value value="0x58" name="FMT6_16_16_16_UNORM"/>
75 <value value="0x59" name="FMT6_16_16_16_SNORM"/>
76 <value value="0x5a" name="FMT6_16_16_16_FLOAT"/>
77 <value value="0x5b" name="FMT6_16_16_16_UINT"/>
78 <value value="0x5c" name="FMT6_16_16_16_SINT"/>
79
80 <value value="0x60" name="FMT6_16_16_16_16_UNORM"/>
81 <value value="0x61" name="FMT6_16_16_16_16_SNORM"/>
82 <value value="0x62" name="FMT6_16_16_16_16_FLOAT"/>
83 <value value="0x63" name="FMT6_16_16_16_16_UINT"/>
84 <value value="0x64" name="FMT6_16_16_16_16_SINT"/>
85
86 <value value="0x65" name="FMT6_32_32_UNORM"/>
87 <value value="0x66" name="FMT6_32_32_SNORM"/>
88 <value value="0x67" name="FMT6_32_32_FLOAT"/>
89 <value value="0x68" name="FMT6_32_32_UINT"/>
90 <value value="0x69" name="FMT6_32_32_SINT"/>
91 <value value="0x6a" name="FMT6_32_32_FIXED"/>
92
93 <value value="0x70" name="FMT6_32_32_32_UNORM"/>
94 <value value="0x71" name="FMT6_32_32_32_SNORM"/>
95 <value value="0x72" name="FMT6_32_32_32_UINT"/>
96 <value value="0x73" name="FMT6_32_32_32_SINT"/>
97 <value value="0x74" name="FMT6_32_32_32_FLOAT"/>
98 <value value="0x75" name="FMT6_32_32_32_FIXED"/>
99
100 <value value="0x80" name="FMT6_32_32_32_32_UNORM"/>
101 <value value="0x81" name="FMT6_32_32_32_32_SNORM"/>
102 <value value="0x82" name="FMT6_32_32_32_32_FLOAT"/>
103 <value value="0x83" name="FMT6_32_32_32_32_UINT"/>
104 <value value="0x84" name="FMT6_32_32_32_32_SINT"/>
105 <value value="0x85" name="FMT6_32_32_32_32_FIXED"/>
106
107 <value value="0x8c" name="FMT6_G8R8B8R8_422_UNORM"/>
108 <value value="0x8d" name="FMT6_R8G8R8B8_422_UNORM"/>
109 <value value="0x8e" name="FMT6_R8_G8B8_2PLANE_420_UNORM"/>
110 <value value="0x90" name="FMT6_R8_G8_B8_3PLANE_420_UNORM"/>
111
112 <value value="0x91" name="FMT6_Z24_UNORM_S8_UINT_AS_R8G8B8A8"/>
113
114 <!-- used with the Y plane of FMT6_R8_G8B8_2PLANE_420_UNORM
115 which has different UBWC compression from regular 8_UNORM format -->
116 <value value="0x94" name="FMT6_8_PLANE_UNORM"/>
117
118 <value value="0xa0" name="FMT6_Z24_UNORM_S8_UINT"/>
119
120 <value value="0xab" name="FMT6_ETC2_RG11_UNORM"/>
121 <value value="0xac" name="FMT6_ETC2_RG11_SNORM"/>
122 <value value="0xad" name="FMT6_ETC2_R11_UNORM"/>
123 <value value="0xae" name="FMT6_ETC2_R11_SNORM"/>
124 <value value="0xaf" name="FMT6_ETC1"/>
125 <value value="0xb0" name="FMT6_ETC2_RGB8"/>
126 <value value="0xb1" name="FMT6_ETC2_RGBA8"/>
127 <value value="0xb2" name="FMT6_ETC2_RGB8A1"/>
128 <value value="0xb3" name="FMT6_DXT1"/>
129 <value value="0xb4" name="FMT6_DXT3"/>
130 <value value="0xb5" name="FMT6_DXT5"/>
131 <value value="0xb7" name="FMT6_RGTC1_UNORM"/>
132 <value value="0xb8" name="FMT6_RGTC1_SNORM"/>
133 <value value="0xbb" name="FMT6_RGTC2_UNORM"/>
134 <value value="0xbc" name="FMT6_RGTC2_SNORM"/>
135 <value value="0xbe" name="FMT6_BPTC_UFLOAT"/>
136 <value value="0xbf" name="FMT6_BPTC_FLOAT"/>
137 <value value="0xc0" name="FMT6_BPTC"/>
138 <value value="0xc1" name="FMT6_ASTC_4x4"/>
139 <value value="0xc2" name="FMT6_ASTC_5x4"/>
140 <value value="0xc3" name="FMT6_ASTC_5x5"/>
141 <value value="0xc4" name="FMT6_ASTC_6x5"/>
142 <value value="0xc5" name="FMT6_ASTC_6x6"/>
143 <value value="0xc6" name="FMT6_ASTC_8x5"/>
144 <value value="0xc7" name="FMT6_ASTC_8x6"/>
145 <value value="0xc8" name="FMT6_ASTC_8x8"/>
146 <value value="0xc9" name="FMT6_ASTC_10x5"/>
147 <value value="0xca" name="FMT6_ASTC_10x6"/>
148 <value value="0xcb" name="FMT6_ASTC_10x8"/>
149 <value value="0xcc" name="FMT6_ASTC_10x10"/>
150 <value value="0xcd" name="FMT6_ASTC_12x10"/>
151 <value value="0xce" name="FMT6_ASTC_12x12"/>
152
153 <!-- same as X8Z24_UNORM but for sampling stencil (integer, 2nd channel) -->
154 <value value="0xea" name="FMT6_S8Z24_UINT"/>
155
156 <!-- Not a hw enum, used internally in driver -->
157 <value value="0xff" name="FMT6_NONE"/>
158
159 </enum>
160
161 <!-- probably same as a5xx -->
162 <enum name="a6xx_polygon_mode">
163 <value name="POLYMODE6_POINTS" value="1"/>
164 <value name="POLYMODE6_LINES" value="2"/>
165 <value name="POLYMODE6_TRIANGLES" value="3"/>
166 </enum>
167
168 <enum name="a6xx_depth_format">
169 <value name="DEPTH6_NONE" value="0"/>
170 <value name="DEPTH6_16" value="1"/>
171 <value name="DEPTH6_24_8" value="2"/>
172 <value name="DEPTH6_32" value="4"/>
173 </enum>
174
175 <bitset name="a6x_cp_protect" inline="yes">
176 <bitfield name="BASE_ADDR" low="0" high="17"/>
177 <bitfield name="MASK_LEN" low="18" high="30"/>
178 <bitfield name="READ" pos="31" type="boolean"/>
179 </bitset>
180
181 <enum name="a6xx_shader_id">
182 <value value="0x9" name="A6XX_TP0_TMO_DATA"/>
183 <value value="0xa" name="A6XX_TP0_SMO_DATA"/>
184 <value value="0xb" name="A6XX_TP0_MIPMAP_BASE_DATA"/>
185 <value value="0x19" name="A6XX_TP1_TMO_DATA"/>
186 <value value="0x1a" name="A6XX_TP1_SMO_DATA"/>
187 <value value="0x1b" name="A6XX_TP1_MIPMAP_BASE_DATA"/>
188 <value value="0x29" name="A6XX_SP_INST_DATA"/>
189 <value value="0x2a" name="A6XX_SP_LB_0_DATA"/>
190 <value value="0x2b" name="A6XX_SP_LB_1_DATA"/>
191 <value value="0x2c" name="A6XX_SP_LB_2_DATA"/>
192 <value value="0x2d" name="A6XX_SP_LB_3_DATA"/>
193 <value value="0x2e" name="A6XX_SP_LB_4_DATA"/>
194 <value value="0x2f" name="A6XX_SP_LB_5_DATA"/>
195 <value value="0x30" name="A6XX_SP_CB_BINDLESS_DATA"/>
196 <value value="0x31" name="A6XX_SP_CB_LEGACY_DATA"/>
197 <value value="0x32" name="A6XX_SP_UAV_DATA"/>
198 <value value="0x33" name="A6XX_SP_INST_TAG"/>
199 <value value="0x34" name="A6XX_SP_CB_BINDLESS_TAG"/>
200 <value value="0x35" name="A6XX_SP_TMO_UMO_TAG"/>
201 <value value="0x36" name="A6XX_SP_SMO_TAG"/>
202 <value value="0x37" name="A6XX_SP_STATE_DATA"/>
203 <value value="0x49" name="A6XX_HLSQ_CHUNK_CVS_RAM"/>
204 <value value="0x4a" name="A6XX_HLSQ_CHUNK_CPS_RAM"/>
205 <value value="0x4b" name="A6XX_HLSQ_CHUNK_CVS_RAM_TAG"/>
206 <value value="0x4c" name="A6XX_HLSQ_CHUNK_CPS_RAM_TAG"/>
207 <value value="0x4d" name="A6XX_HLSQ_ICB_CVS_CB_BASE_TAG"/>
208 <value value="0x4e" name="A6XX_HLSQ_ICB_CPS_CB_BASE_TAG"/>
209 <value value="0x50" name="A6XX_HLSQ_CVS_MISC_RAM"/>
210 <value value="0x51" name="A6XX_HLSQ_CPS_MISC_RAM"/>
211 <value value="0x52" name="A6XX_HLSQ_INST_RAM"/>
212 <value value="0x53" name="A6XX_HLSQ_GFX_CVS_CONST_RAM"/>
213 <value value="0x54" name="A6XX_HLSQ_GFX_CPS_CONST_RAM"/>
214 <value value="0x55" name="A6XX_HLSQ_CVS_MISC_RAM_TAG"/>
215 <value value="0x56" name="A6XX_HLSQ_CPS_MISC_RAM_TAG"/>
216 <value value="0x57" name="A6XX_HLSQ_INST_RAM_TAG"/>
217 <value value="0x58" name="A6XX_HLSQ_GFX_CVS_CONST_RAM_TAG"/>
218 <value value="0x59" name="A6XX_HLSQ_GFX_CPS_CONST_RAM_TAG"/>
219 <value value="0x5a" name="A6XX_HLSQ_PWR_REST_RAM"/>
220 <value value="0x5b" name="A6XX_HLSQ_PWR_REST_TAG"/>
221 <value value="0x60" name="A6XX_HLSQ_DATAPATH_META"/>
222 <value value="0x61" name="A6XX_HLSQ_FRONTEND_META"/>
223 <value value="0x62" name="A6XX_HLSQ_INDIRECT_META"/>
224 <value value="0x63" name="A6XX_HLSQ_BACKEND_META"/>
225 </enum>
226
227 <enum name="a6xx_debugbus_id">
228 <value value="0x1" name="A6XX_DBGBUS_CP"/>
229 <value value="0x2" name="A6XX_DBGBUS_RBBM"/>
230 <value value="0x3" name="A6XX_DBGBUS_VBIF"/>
231 <value value="0x4" name="A6XX_DBGBUS_HLSQ"/>
232 <value value="0x5" name="A6XX_DBGBUS_UCHE"/>
233 <value value="0x6" name="A6XX_DBGBUS_DPM"/>
234 <value value="0x7" name="A6XX_DBGBUS_TESS"/>
235 <value value="0x8" name="A6XX_DBGBUS_PC"/>
236 <value value="0x9" name="A6XX_DBGBUS_VFDP"/>
237 <value value="0xa" name="A6XX_DBGBUS_VPC"/>
238 <value value="0xb" name="A6XX_DBGBUS_TSE"/>
239 <value value="0xc" name="A6XX_DBGBUS_RAS"/>
240 <value value="0xd" name="A6XX_DBGBUS_VSC"/>
241 <value value="0xe" name="A6XX_DBGBUS_COM"/>
242 <value value="0x10" name="A6XX_DBGBUS_LRZ"/>
243 <value value="0x11" name="A6XX_DBGBUS_A2D"/>
244 <value value="0x12" name="A6XX_DBGBUS_CCUFCHE"/>
245 <value value="0x13" name="A6XX_DBGBUS_GMU_CX"/>
246 <value value="0x14" name="A6XX_DBGBUS_RBP"/>
247 <value value="0x15" name="A6XX_DBGBUS_DCS"/>
248 <value value="0x16" name="A6XX_DBGBUS_DBGC"/>
249 <value value="0x17" name="A6XX_DBGBUS_CX"/>
250 <value value="0x18" name="A6XX_DBGBUS_GMU_GX"/>
251 <value value="0x19" name="A6XX_DBGBUS_TPFCHE"/>
252 <value value="0x1a" name="A6XX_DBGBUS_GBIF_GX"/>
253 <value value="0x1d" name="A6XX_DBGBUS_GPC"/>
254 <value value="0x1e" name="A6XX_DBGBUS_LARC"/>
255 <value value="0x1f" name="A6XX_DBGBUS_HLSQ_SPTP"/>
256 <value value="0x20" name="A6XX_DBGBUS_RB_0"/>
257 <value value="0x21" name="A6XX_DBGBUS_RB_1"/>
258 <value value="0x24" name="A6XX_DBGBUS_UCHE_WRAPPER"/>
259 <value value="0x28" name="A6XX_DBGBUS_CCU_0"/>
260 <value value="0x29" name="A6XX_DBGBUS_CCU_1"/>
261 <value value="0x38" name="A6XX_DBGBUS_VFD_0"/>
262 <value value="0x39" name="A6XX_DBGBUS_VFD_1"/>
263 <value value="0x3a" name="A6XX_DBGBUS_VFD_2"/>
264 <value value="0x3b" name="A6XX_DBGBUS_VFD_3"/>
265 <value value="0x40" name="A6XX_DBGBUS_SP_0"/>
266 <value value="0x41" name="A6XX_DBGBUS_SP_1"/>
267 <value value="0x48" name="A6XX_DBGBUS_TPL1_0"/>
268 <value value="0x49" name="A6XX_DBGBUS_TPL1_1"/>
269 <value value="0x4a" name="A6XX_DBGBUS_TPL1_2"/>
270 <value value="0x4b" name="A6XX_DBGBUS_TPL1_3"/>
271 </enum>
272
273 <enum name="a6xx_cp_perfcounter_select">
274 <value value="0" name="PERF_CP_ALWAYS_COUNT"/>
275 <value value="1" name="PERF_CP_BUSY_GFX_CORE_IDLE"/>
276 <value value="2" name="PERF_CP_BUSY_CYCLES"/>
277 <value value="3" name="PERF_CP_NUM_PREEMPTIONS"/>
278 <value value="4" name="PERF_CP_PREEMPTION_REACTION_DELAY"/>
279 <value value="5" name="PERF_CP_PREEMPTION_SWITCH_OUT_TIME"/>
280 <value value="6" name="PERF_CP_PREEMPTION_SWITCH_IN_TIME"/>
281 <value value="7" name="PERF_CP_DEAD_DRAWS_IN_BIN_RENDER"/>
282 <value value="8" name="PERF_CP_PREDICATED_DRAWS_KILLED"/>
283 <value value="9" name="PERF_CP_MODE_SWITCH"/>
284 <value value="10" name="PERF_CP_ZPASS_DONE"/>
285 <value value="11" name="PERF_CP_CONTEXT_DONE"/>
286 <value value="12" name="PERF_CP_CACHE_FLUSH"/>
287 <value value="13" name="PERF_CP_LONG_PREEMPTIONS"/>
288 <value value="14" name="PERF_CP_SQE_I_CACHE_STARVE"/>
289 <value value="15" name="PERF_CP_SQE_IDLE"/>
290 <value value="16" name="PERF_CP_SQE_PM4_STARVE_RB_IB"/>
291 <value value="17" name="PERF_CP_SQE_PM4_STARVE_SDS"/>
292 <value value="18" name="PERF_CP_SQE_MRB_STARVE"/>
293 <value value="19" name="PERF_CP_SQE_RRB_STARVE"/>
294 <value value="20" name="PERF_CP_SQE_VSD_STARVE"/>
295 <value value="21" name="PERF_CP_VSD_DECODE_STARVE"/>
296 <value value="22" name="PERF_CP_SQE_PIPE_OUT_STALL"/>
297 <value value="23" name="PERF_CP_SQE_SYNC_STALL"/>
298 <value value="24" name="PERF_CP_SQE_PM4_WFI_STALL"/>
299 <value value="25" name="PERF_CP_SQE_SYS_WFI_STALL"/>
300 <value value="26" name="PERF_CP_SQE_T4_EXEC"/>
301 <value value="27" name="PERF_CP_SQE_LOAD_STATE_EXEC"/>
302 <value value="28" name="PERF_CP_SQE_SAVE_SDS_STATE"/>
303 <value value="29" name="PERF_CP_SQE_DRAW_EXEC"/>
304 <value value="30" name="PERF_CP_SQE_CTXT_REG_BUNCH_EXEC"/>
305 <value value="31" name="PERF_CP_SQE_EXEC_PROFILED"/>
306 <value value="32" name="PERF_CP_MEMORY_POOL_EMPTY"/>
307 <value value="33" name="PERF_CP_MEMORY_POOL_SYNC_STALL"/>
308 <value value="34" name="PERF_CP_MEMORY_POOL_ABOVE_THRESH"/>
309 <value value="35" name="PERF_CP_AHB_WR_STALL_PRE_DRAWS"/>
310 <value value="36" name="PERF_CP_AHB_STALL_SQE_GMU"/>
311 <value value="37" name="PERF_CP_AHB_STALL_SQE_WR_OTHER"/>
312 <value value="38" name="PERF_CP_AHB_STALL_SQE_RD_OTHER"/>
313 <value value="39" name="PERF_CP_CLUSTER0_EMPTY"/>
314 <value value="40" name="PERF_CP_CLUSTER1_EMPTY"/>
315 <value value="41" name="PERF_CP_CLUSTER2_EMPTY"/>
316 <value value="42" name="PERF_CP_CLUSTER3_EMPTY"/>
317 <value value="43" name="PERF_CP_CLUSTER4_EMPTY"/>
318 <value value="44" name="PERF_CP_CLUSTER5_EMPTY"/>
319 <value value="45" name="PERF_CP_PM4_DATA"/>
320 <value value="46" name="PERF_CP_PM4_HEADERS"/>
321 <value value="47" name="PERF_CP_VBIF_READ_BEATS"/>
322 <value value="48" name="PERF_CP_VBIF_WRITE_BEATS"/>
323 <value value="49" name="PERF_CP_SQE_INSTR_COUNTER"/>
324 </enum>
325
326 <enum name="a6xx_rbbm_perfcounter_select">
327 <value value="0" name="PERF_RBBM_ALWAYS_COUNT"/>
328 <value value="1" name="PERF_RBBM_ALWAYS_ON"/>
329 <value value="2" name="PERF_RBBM_TSE_BUSY"/>
330 <value value="3" name="PERF_RBBM_RAS_BUSY"/>
331 <value value="4" name="PERF_RBBM_PC_DCALL_BUSY"/>
332 <value value="5" name="PERF_RBBM_PC_VSD_BUSY"/>
333 <value value="6" name="PERF_RBBM_STATUS_MASKED"/>
334 <value value="7" name="PERF_RBBM_COM_BUSY"/>
335 <value value="8" name="PERF_RBBM_DCOM_BUSY"/>
336 <value value="9" name="PERF_RBBM_VBIF_BUSY"/>
337 <value value="10" name="PERF_RBBM_VSC_BUSY"/>
338 <value value="11" name="PERF_RBBM_TESS_BUSY"/>
339 <value value="12" name="PERF_RBBM_UCHE_BUSY"/>
340 <value value="13" name="PERF_RBBM_HLSQ_BUSY"/>
341 </enum>
342
343 <enum name="a6xx_pc_perfcounter_select">
344 <value value="0" name="PERF_PC_BUSY_CYCLES"/>
345 <value value="1" name="PERF_PC_WORKING_CYCLES"/>
346 <value value="2" name="PERF_PC_STALL_CYCLES_VFD"/>
347 <value value="3" name="PERF_PC_STALL_CYCLES_TSE"/>
348 <value value="4" name="PERF_PC_STALL_CYCLES_VPC"/>
349 <value value="5" name="PERF_PC_STALL_CYCLES_UCHE"/>
350 <value value="6" name="PERF_PC_STALL_CYCLES_TESS"/>
351 <value value="7" name="PERF_PC_STALL_CYCLES_TSE_ONLY"/>
352 <value value="8" name="PERF_PC_STALL_CYCLES_VPC_ONLY"/>
353 <value value="9" name="PERF_PC_PASS1_TF_STALL_CYCLES"/>
354 <value value="10" name="PERF_PC_STARVE_CYCLES_FOR_INDEX"/>
355 <value value="11" name="PERF_PC_STARVE_CYCLES_FOR_TESS_FACTOR"/>
356 <value value="12" name="PERF_PC_STARVE_CYCLES_FOR_VIZ_STREAM"/>
357 <value value="13" name="PERF_PC_STARVE_CYCLES_FOR_POSITION"/>
358 <value value="14" name="PERF_PC_STARVE_CYCLES_DI"/>
359 <value value="15" name="PERF_PC_VIS_STREAMS_LOADED"/>
360 <value value="16" name="PERF_PC_INSTANCES"/>
361 <value value="17" name="PERF_PC_VPC_PRIMITIVES"/>
362 <value value="18" name="PERF_PC_DEAD_PRIM"/>
363 <value value="19" name="PERF_PC_LIVE_PRIM"/>
364 <value value="20" name="PERF_PC_VERTEX_HITS"/>
365 <value value="21" name="PERF_PC_IA_VERTICES"/>
366 <value value="22" name="PERF_PC_IA_PRIMITIVES"/>
367 <value value="23" name="PERF_PC_GS_PRIMITIVES"/>
368 <value value="24" name="PERF_PC_HS_INVOCATIONS"/>
369 <value value="25" name="PERF_PC_DS_INVOCATIONS"/>
370 <value value="26" name="PERF_PC_VS_INVOCATIONS"/>
371 <value value="27" name="PERF_PC_GS_INVOCATIONS"/>
372 <value value="28" name="PERF_PC_DS_PRIMITIVES"/>
373 <value value="29" name="PERF_PC_VPC_POS_DATA_TRANSACTION"/>
374 <value value="30" name="PERF_PC_3D_DRAWCALLS"/>
375 <value value="31" name="PERF_PC_2D_DRAWCALLS"/>
376 <value value="32" name="PERF_PC_NON_DRAWCALL_GLOBAL_EVENTS"/>
377 <value value="33" name="PERF_TESS_BUSY_CYCLES"/>
378 <value value="34" name="PERF_TESS_WORKING_CYCLES"/>
379 <value value="35" name="PERF_TESS_STALL_CYCLES_PC"/>
380 <value value="36" name="PERF_TESS_STARVE_CYCLES_PC"/>
381 <value value="37" name="PERF_PC_TSE_TRANSACTION"/>
382 <value value="38" name="PERF_PC_TSE_VERTEX"/>
383 <value value="39" name="PERF_PC_TESS_PC_UV_TRANS"/>
384 <value value="40" name="PERF_PC_TESS_PC_UV_PATCHES"/>
385 <value value="41" name="PERF_PC_TESS_FACTOR_TRANS"/>
386 </enum>
387
388 <enum name="a6xx_vfd_perfcounter_select">
389 <value value="0" name="PERF_VFD_BUSY_CYCLES"/>
390 <value value="1" name="PERF_VFD_STALL_CYCLES_UCHE"/>
391 <value value="2" name="PERF_VFD_STALL_CYCLES_VPC_ALLOC"/>
392 <value value="3" name="PERF_VFD_STALL_CYCLES_SP_INFO"/>
393 <value value="4" name="PERF_VFD_STALL_CYCLES_SP_ATTR"/>
394 <value value="5" name="PERF_VFD_STARVE_CYCLES_UCHE"/>
395 <value value="6" name="PERF_VFD_RBUFFER_FULL"/>
396 <value value="7" name="PERF_VFD_ATTR_INFO_FIFO_FULL"/>
397 <value value="8" name="PERF_VFD_DECODED_ATTRIBUTE_BYTES"/>
398 <value value="9" name="PERF_VFD_NUM_ATTRIBUTES"/>
399 <value value="10" name="PERF_VFD_UPPER_SHADER_FIBERS"/>
400 <value value="11" name="PERF_VFD_LOWER_SHADER_FIBERS"/>
401 <value value="12" name="PERF_VFD_MODE_0_FIBERS"/>
402 <value value="13" name="PERF_VFD_MODE_1_FIBERS"/>
403 <value value="14" name="PERF_VFD_MODE_2_FIBERS"/>
404 <value value="15" name="PERF_VFD_MODE_3_FIBERS"/>
405 <value value="16" name="PERF_VFD_MODE_4_FIBERS"/>
406 <value value="17" name="PERF_VFD_TOTAL_VERTICES"/>
407 <value value="18" name="PERF_VFDP_STALL_CYCLES_VFD"/>
408 <value value="19" name="PERF_VFDP_STALL_CYCLES_VFD_INDEX"/>
409 <value value="20" name="PERF_VFDP_STALL_CYCLES_VFD_PROG"/>
410 <value value="21" name="PERF_VFDP_STARVE_CYCLES_PC"/>
411 <value value="22" name="PERF_VFDP_VS_STAGE_WAVES"/>
412 </enum>
413
414 <enum name="a6xx_hlsq_perfcounter_select">
415 <value value="0" name="PERF_HLSQ_BUSY_CYCLES"/>
416 <value value="1" name="PERF_HLSQ_STALL_CYCLES_UCHE"/>
417 <value value="2" name="PERF_HLSQ_STALL_CYCLES_SP_STATE"/>
418 <value value="3" name="PERF_HLSQ_STALL_CYCLES_SP_FS_STAGE"/>
419 <value value="4" name="PERF_HLSQ_UCHE_LATENCY_CYCLES"/>
420 <value value="5" name="PERF_HLSQ_UCHE_LATENCY_COUNT"/>
421 <value value="6" name="PERF_HLSQ_FS_STAGE_1X_WAVES"/>
422 <value value="7" name="PERF_HLSQ_FS_STAGE_2X_WAVES"/>
423 <value value="8" name="PERF_HLSQ_QUADS"/>
424 <value value="9" name="PERF_HLSQ_CS_INVOCATIONS"/>
425 <value value="10" name="PERF_HLSQ_COMPUTE_DRAWCALLS"/>
426 <value value="11" name="PERF_HLSQ_FS_DATA_WAIT_PROGRAMMING"/>
427 <value value="12" name="PERF_HLSQ_DUAL_FS_PROG_ACTIVE"/>
428 <value value="13" name="PERF_HLSQ_DUAL_VS_PROG_ACTIVE"/>
429 <value value="14" name="PERF_HLSQ_FS_BATCH_COUNT_ZERO"/>
430 <value value="15" name="PERF_HLSQ_VS_BATCH_COUNT_ZERO"/>
431 <value value="16" name="PERF_HLSQ_WAVE_PENDING_NO_QUAD"/>
432 <value value="17" name="PERF_HLSQ_WAVE_PENDING_NO_PRIM_BASE"/>
433 <value value="18" name="PERF_HLSQ_STALL_CYCLES_VPC"/>
434 <value value="19" name="PERF_HLSQ_PIXELS"/>
435 <value value="20" name="PERF_HLSQ_DRAW_MODE_SWITCH_VSFS_SYNC"/>
436 </enum>
437
438 <enum name="a6xx_vpc_perfcounter_select">
439 <value value="0" name="PERF_VPC_BUSY_CYCLES"/>
440 <value value="1" name="PERF_VPC_WORKING_CYCLES"/>
441 <value value="2" name="PERF_VPC_STALL_CYCLES_UCHE"/>
442 <value value="3" name="PERF_VPC_STALL_CYCLES_VFD_WACK"/>
443 <value value="4" name="PERF_VPC_STALL_CYCLES_HLSQ_PRIM_ALLOC"/>
444 <value value="5" name="PERF_VPC_STALL_CYCLES_PC"/>
445 <value value="6" name="PERF_VPC_STALL_CYCLES_SP_LM"/>
446 <value value="7" name="PERF_VPC_STARVE_CYCLES_SP"/>
447 <value value="8" name="PERF_VPC_STARVE_CYCLES_LRZ"/>
448 <value value="9" name="PERF_VPC_PC_PRIMITIVES"/>
449 <value value="10" name="PERF_VPC_SP_COMPONENTS"/>
450 <value value="11" name="PERF_VPC_STALL_CYCLES_VPCRAM_POS"/>
451 <value value="12" name="PERF_VPC_LRZ_ASSIGN_PRIMITIVES"/>
452 <value value="13" name="PERF_VPC_RB_VISIBLE_PRIMITIVES"/>
453 <value value="14" name="PERF_VPC_LM_TRANSACTION"/>
454 <value value="15" name="PERF_VPC_STREAMOUT_TRANSACTION"/>
455 <value value="16" name="PERF_VPC_VS_BUSY_CYCLES"/>
456 <value value="17" name="PERF_VPC_PS_BUSY_CYCLES"/>
457 <value value="18" name="PERF_VPC_VS_WORKING_CYCLES"/>
458 <value value="19" name="PERF_VPC_PS_WORKING_CYCLES"/>
459 <value value="20" name="PERF_VPC_STARVE_CYCLES_RB"/>
460 <value value="21" name="PERF_VPC_NUM_VPCRAM_READ_POS"/>
461 <value value="22" name="PERF_VPC_WIT_FULL_CYCLES"/>
462 <value value="23" name="PERF_VPC_VPCRAM_FULL_CYCLES"/>
463 <value value="24" name="PERF_VPC_LM_FULL_WAIT_FOR_INTP_END"/>
464 <value value="25" name="PERF_VPC_NUM_VPCRAM_WRITE"/>
465 <value value="26" name="PERF_VPC_NUM_VPCRAM_READ_SO"/>
466 <value value="27" name="PERF_VPC_NUM_ATTR_REQ_LM"/>
467 </enum>
468
469 <enum name="a6xx_tse_perfcounter_select">
470 <value value="0" name="PERF_TSE_BUSY_CYCLES"/>
471 <value value="1" name="PERF_TSE_CLIPPING_CYCLES"/>
472 <value value="2" name="PERF_TSE_STALL_CYCLES_RAS"/>
473 <value value="3" name="PERF_TSE_STALL_CYCLES_LRZ_BARYPLANE"/>
474 <value value="4" name="PERF_TSE_STALL_CYCLES_LRZ_ZPLANE"/>
475 <value value="5" name="PERF_TSE_STARVE_CYCLES_PC"/>
476 <value value="6" name="PERF_TSE_INPUT_PRIM"/>
477 <value value="7" name="PERF_TSE_INPUT_NULL_PRIM"/>
478 <value value="8" name="PERF_TSE_TRIVAL_REJ_PRIM"/>
479 <value value="9" name="PERF_TSE_CLIPPED_PRIM"/>
480 <value value="10" name="PERF_TSE_ZERO_AREA_PRIM"/>
481 <value value="11" name="PERF_TSE_FACENESS_CULLED_PRIM"/>
482 <value value="12" name="PERF_TSE_ZERO_PIXEL_PRIM"/>
483 <value value="13" name="PERF_TSE_OUTPUT_NULL_PRIM"/>
484 <value value="14" name="PERF_TSE_OUTPUT_VISIBLE_PRIM"/>
485 <value value="15" name="PERF_TSE_CINVOCATION"/>
486 <value value="16" name="PERF_TSE_CPRIMITIVES"/>
487 <value value="17" name="PERF_TSE_2D_INPUT_PRIM"/>
488 <value value="18" name="PERF_TSE_2D_ALIVE_CYCLES"/>
489 <value value="19" name="PERF_TSE_CLIP_PLANES"/>
490 </enum>
491
492 <enum name="a6xx_ras_perfcounter_select">
493 <value value="0" name="PERF_RAS_BUSY_CYCLES"/>
494 <value value="1" name="PERF_RAS_SUPERTILE_ACTIVE_CYCLES"/>
495 <value value="2" name="PERF_RAS_STALL_CYCLES_LRZ"/>
496 <value value="3" name="PERF_RAS_STARVE_CYCLES_TSE"/>
497 <value value="4" name="PERF_RAS_SUPER_TILES"/>
498 <value value="5" name="PERF_RAS_8X4_TILES"/>
499 <value value="6" name="PERF_RAS_MASKGEN_ACTIVE"/>
500 <value value="7" name="PERF_RAS_FULLY_COVERED_SUPER_TILES"/>
501 <value value="8" name="PERF_RAS_FULLY_COVERED_8X4_TILES"/>
502 <value value="9" name="PERF_RAS_PRIM_KILLED_INVISILBE"/>
503 <value value="10" name="PERF_RAS_SUPERTILE_GEN_ACTIVE_CYCLES"/>
504 <value value="11" name="PERF_RAS_LRZ_INTF_WORKING_CYCLES"/>
505 <value value="12" name="PERF_RAS_BLOCKS"/>
506 </enum>
507
508 <enum name="a6xx_uche_perfcounter_select">
509 <value value="0" name="PERF_UCHE_BUSY_CYCLES"/>
510 <value value="1" name="PERF_UCHE_STALL_CYCLES_ARBITER"/>
511 <value value="2" name="PERF_UCHE_VBIF_LATENCY_CYCLES"/>
512 <value value="3" name="PERF_UCHE_VBIF_LATENCY_SAMPLES"/>
513 <value value="4" name="PERF_UCHE_VBIF_READ_BEATS_TP"/>
514 <value value="5" name="PERF_UCHE_VBIF_READ_BEATS_VFD"/>
515 <value value="6" name="PERF_UCHE_VBIF_READ_BEATS_HLSQ"/>
516 <value value="7" name="PERF_UCHE_VBIF_READ_BEATS_LRZ"/>
517 <value value="8" name="PERF_UCHE_VBIF_READ_BEATS_SP"/>
518 <value value="9" name="PERF_UCHE_READ_REQUESTS_TP"/>
519 <value value="10" name="PERF_UCHE_READ_REQUESTS_VFD"/>
520 <value value="11" name="PERF_UCHE_READ_REQUESTS_HLSQ"/>
521 <value value="12" name="PERF_UCHE_READ_REQUESTS_LRZ"/>
522 <value value="13" name="PERF_UCHE_READ_REQUESTS_SP"/>
523 <value value="14" name="PERF_UCHE_WRITE_REQUESTS_LRZ"/>
524 <value value="15" name="PERF_UCHE_WRITE_REQUESTS_SP"/>
525 <value value="16" name="PERF_UCHE_WRITE_REQUESTS_VPC"/>
526 <value value="17" name="PERF_UCHE_WRITE_REQUESTS_VSC"/>
527 <value value="18" name="PERF_UCHE_EVICTS"/>
528 <value value="19" name="PERF_UCHE_BANK_REQ0"/>
529 <value value="20" name="PERF_UCHE_BANK_REQ1"/>
530 <value value="21" name="PERF_UCHE_BANK_REQ2"/>
531 <value value="22" name="PERF_UCHE_BANK_REQ3"/>
532 <value value="23" name="PERF_UCHE_BANK_REQ4"/>
533 <value value="24" name="PERF_UCHE_BANK_REQ5"/>
534 <value value="25" name="PERF_UCHE_BANK_REQ6"/>
535 <value value="26" name="PERF_UCHE_BANK_REQ7"/>
536 <value value="27" name="PERF_UCHE_VBIF_READ_BEATS_CH0"/>
537 <value value="28" name="PERF_UCHE_VBIF_READ_BEATS_CH1"/>
538 <value value="29" name="PERF_UCHE_GMEM_READ_BEATS"/>
539 <value value="30" name="PERF_UCHE_TPH_REF_FULL"/>
540 <value value="31" name="PERF_UCHE_TPH_VICTIM_FULL"/>
541 <value value="32" name="PERF_UCHE_TPH_EXT_FULL"/>
542 <value value="33" name="PERF_UCHE_VBIF_STALL_WRITE_DATA"/>
543 <value value="34" name="PERF_UCHE_DCMP_LATENCY_SAMPLES"/>
544 <value value="35" name="PERF_UCHE_DCMP_LATENCY_CYCLES"/>
545 <value value="36" name="PERF_UCHE_VBIF_READ_BEATS_PC"/>
546 <value value="37" name="PERF_UCHE_READ_REQUESTS_PC"/>
547 <value value="38" name="PERF_UCHE_RAM_READ_REQ"/>
548 <value value="39" name="PERF_UCHE_RAM_WRITE_REQ"/>
549 </enum>
550
551 <enum name="a6xx_tp_perfcounter_select">
552 <value value="0" name="PERF_TP_BUSY_CYCLES"/>
553 <value value="1" name="PERF_TP_STALL_CYCLES_UCHE"/>
554 <value value="2" name="PERF_TP_LATENCY_CYCLES"/>
555 <value value="3" name="PERF_TP_LATENCY_TRANS"/>
556 <value value="4" name="PERF_TP_FLAG_CACHE_REQUEST_SAMPLES"/>
557 <value value="5" name="PERF_TP_FLAG_CACHE_REQUEST_LATENCY"/>
558 <value value="6" name="PERF_TP_L1_CACHELINE_REQUESTS"/>
559 <value value="7" name="PERF_TP_L1_CACHELINE_MISSES"/>
560 <value value="8" name="PERF_TP_SP_TP_TRANS"/>
561 <value value="9" name="PERF_TP_TP_SP_TRANS"/>
562 <value value="10" name="PERF_TP_OUTPUT_PIXELS"/>
563 <value value="11" name="PERF_TP_FILTER_WORKLOAD_16BIT"/>
564 <value value="12" name="PERF_TP_FILTER_WORKLOAD_32BIT"/>
565 <value value="13" name="PERF_TP_QUADS_RECEIVED"/>
566 <value value="14" name="PERF_TP_QUADS_OFFSET"/>
567 <value value="15" name="PERF_TP_QUADS_SHADOW"/>
568 <value value="16" name="PERF_TP_QUADS_ARRAY"/>
569 <value value="17" name="PERF_TP_QUADS_GRADIENT"/>
570 <value value="18" name="PERF_TP_QUADS_1D"/>
571 <value value="19" name="PERF_TP_QUADS_2D"/>
572 <value value="20" name="PERF_TP_QUADS_BUFFER"/>
573 <value value="21" name="PERF_TP_QUADS_3D"/>
574 <value value="22" name="PERF_TP_QUADS_CUBE"/>
575 <value value="23" name="PERF_TP_DIVERGENT_QUADS_RECEIVED"/>
576 <value value="24" name="PERF_TP_PRT_NON_RESIDENT_EVENTS"/>
577 <value value="25" name="PERF_TP_OUTPUT_PIXELS_POINT"/>
578 <value value="26" name="PERF_TP_OUTPUT_PIXELS_BILINEAR"/>
579 <value value="27" name="PERF_TP_OUTPUT_PIXELS_MIP"/>
580 <value value="28" name="PERF_TP_OUTPUT_PIXELS_ANISO"/>
581 <value value="29" name="PERF_TP_OUTPUT_PIXELS_ZERO_LOD"/>
582 <value value="30" name="PERF_TP_FLAG_CACHE_REQUESTS"/>
583 <value value="31" name="PERF_TP_FLAG_CACHE_MISSES"/>
584 <value value="32" name="PERF_TP_L1_5_L2_REQUESTS"/>
585 <value value="33" name="PERF_TP_2D_OUTPUT_PIXELS"/>
586 <value value="34" name="PERF_TP_2D_OUTPUT_PIXELS_POINT"/>
587 <value value="35" name="PERF_TP_2D_OUTPUT_PIXELS_BILINEAR"/>
588 <value value="36" name="PERF_TP_2D_FILTER_WORKLOAD_16BIT"/>
589 <value value="37" name="PERF_TP_2D_FILTER_WORKLOAD_32BIT"/>
590 <value value="38" name="PERF_TP_TPA2TPC_TRANS"/>
591 <value value="39" name="PERF_TP_L1_MISSES_ASTC_1TILE"/>
592 <value value="40" name="PERF_TP_L1_MISSES_ASTC_2TILE"/>
593 <value value="41" name="PERF_TP_L1_MISSES_ASTC_4TILE"/>
594 <value value="42" name="PERF_TP_L1_5_L2_COMPRESS_REQS"/>
595 <value value="43" name="PERF_TP_L1_5_L2_COMPRESS_MISS"/>
596 <value value="44" name="PERF_TP_L1_BANK_CONFLICT"/>
597 <value value="45" name="PERF_TP_L1_5_MISS_LATENCY_CYCLES"/>
598 <value value="46" name="PERF_TP_L1_5_MISS_LATENCY_TRANS"/>
599 <value value="47" name="PERF_TP_QUADS_CONSTANT_MULTIPLIED"/>
600 <value value="48" name="PERF_TP_FRONTEND_WORKING_CYCLES"/>
601 <value value="49" name="PERF_TP_L1_TAG_WORKING_CYCLES"/>
602 <value value="50" name="PERF_TP_L1_DATA_WRITE_WORKING_CYCLES"/>
603 <value value="51" name="PERF_TP_PRE_L1_DECOM_WORKING_CYCLES"/>
604 <value value="52" name="PERF_TP_BACKEND_WORKING_CYCLES"/>
605 <value value="53" name="PERF_TP_FLAG_CACHE_WORKING_CYCLES"/>
606 <value value="54" name="PERF_TP_L1_5_CACHE_WORKING_CYCLES"/>
607 <value value="55" name="PERF_TP_STARVE_CYCLES_SP"/>
608 <value value="56" name="PERF_TP_STARVE_CYCLES_UCHE"/>
609 </enum>
610
611 <enum name="a6xx_sp_perfcounter_select">
612 <value value="0" name="PERF_SP_BUSY_CYCLES"/>
613 <value value="1" name="PERF_SP_ALU_WORKING_CYCLES"/>
614 <value value="2" name="PERF_SP_EFU_WORKING_CYCLES"/>
615 <value value="3" name="PERF_SP_STALL_CYCLES_VPC"/>
616 <value value="4" name="PERF_SP_STALL_CYCLES_TP"/>
617 <value value="5" name="PERF_SP_STALL_CYCLES_UCHE"/>
618 <value value="6" name="PERF_SP_STALL_CYCLES_RB"/>
619 <value value="7" name="PERF_SP_NON_EXECUTION_CYCLES"/>
620 <value value="8" name="PERF_SP_WAVE_CONTEXTS"/>
621 <value value="9" name="PERF_SP_WAVE_CONTEXT_CYCLES"/>
622 <value value="10" name="PERF_SP_FS_STAGE_WAVE_CYCLES"/>
623 <value value="11" name="PERF_SP_FS_STAGE_WAVE_SAMPLES"/>
624 <value value="12" name="PERF_SP_VS_STAGE_WAVE_CYCLES"/>
625 <value value="13" name="PERF_SP_VS_STAGE_WAVE_SAMPLES"/>
626 <value value="14" name="PERF_SP_FS_STAGE_DURATION_CYCLES"/>
627 <value value="15" name="PERF_SP_VS_STAGE_DURATION_CYCLES"/>
628 <value value="16" name="PERF_SP_WAVE_CTRL_CYCLES"/>
629 <value value="17" name="PERF_SP_WAVE_LOAD_CYCLES"/>
630 <value value="18" name="PERF_SP_WAVE_EMIT_CYCLES"/>
631 <value value="19" name="PERF_SP_WAVE_NOP_CYCLES"/>
632 <value value="20" name="PERF_SP_WAVE_WAIT_CYCLES"/>
633 <value value="21" name="PERF_SP_WAVE_FETCH_CYCLES"/>
634 <value value="22" name="PERF_SP_WAVE_IDLE_CYCLES"/>
635 <value value="23" name="PERF_SP_WAVE_END_CYCLES"/>
636 <value value="24" name="PERF_SP_WAVE_LONG_SYNC_CYCLES"/>
637 <value value="25" name="PERF_SP_WAVE_SHORT_SYNC_CYCLES"/>
638 <value value="26" name="PERF_SP_WAVE_JOIN_CYCLES"/>
639 <value value="27" name="PERF_SP_LM_LOAD_INSTRUCTIONS"/>
640 <value value="28" name="PERF_SP_LM_STORE_INSTRUCTIONS"/>
641 <value value="29" name="PERF_SP_LM_ATOMICS"/>
642 <value value="30" name="PERF_SP_GM_LOAD_INSTRUCTIONS"/>
643 <value value="31" name="PERF_SP_GM_STORE_INSTRUCTIONS"/>
644 <value value="32" name="PERF_SP_GM_ATOMICS"/>
645 <value value="33" name="PERF_SP_VS_STAGE_TEX_INSTRUCTIONS"/>
646 <value value="34" name="PERF_SP_VS_STAGE_EFU_INSTRUCTIONS"/>
647 <value value="35" name="PERF_SP_VS_STAGE_FULL_ALU_INSTRUCTIONS"/>
648 <value value="36" name="PERF_SP_VS_STAGE_HALF_ALU_INSTRUCTIONS"/>
649 <value value="37" name="PERF_SP_FS_STAGE_TEX_INSTRUCTIONS"/>
650 <value value="38" name="PERF_SP_FS_STAGE_CFLOW_INSTRUCTIONS"/>
651 <value value="39" name="PERF_SP_FS_STAGE_EFU_INSTRUCTIONS"/>
652 <value value="40" name="PERF_SP_FS_STAGE_FULL_ALU_INSTRUCTIONS"/>
653 <value value="41" name="PERF_SP_FS_STAGE_HALF_ALU_INSTRUCTIONS"/>
654 <value value="42" name="PERF_SP_FS_STAGE_BARY_INSTRUCTIONS"/>
655 <value value="43" name="PERF_SP_VS_INSTRUCTIONS"/>
656 <value value="44" name="PERF_SP_FS_INSTRUCTIONS"/>
657 <value value="45" name="PERF_SP_ADDR_LOCK_COUNT"/>
658 <value value="46" name="PERF_SP_UCHE_READ_TRANS"/>
659 <value value="47" name="PERF_SP_UCHE_WRITE_TRANS"/>
660 <value value="48" name="PERF_SP_EXPORT_VPC_TRANS"/>
661 <value value="49" name="PERF_SP_EXPORT_RB_TRANS"/>
662 <value value="50" name="PERF_SP_PIXELS_KILLED"/>
663 <value value="51" name="PERF_SP_ICL1_REQUESTS"/>
664 <value value="52" name="PERF_SP_ICL1_MISSES"/>
665 <value value="53" name="PERF_SP_HS_INSTRUCTIONS"/>
666 <value value="54" name="PERF_SP_DS_INSTRUCTIONS"/>
667 <value value="55" name="PERF_SP_GS_INSTRUCTIONS"/>
668 <value value="56" name="PERF_SP_CS_INSTRUCTIONS"/>
669 <value value="57" name="PERF_SP_GPR_READ"/>
670 <value value="58" name="PERF_SP_GPR_WRITE"/>
671 <value value="59" name="PERF_SP_FS_STAGE_HALF_EFU_INSTRUCTIONS"/>
672 <value value="60" name="PERF_SP_VS_STAGE_HALF_EFU_INSTRUCTIONS"/>
673 <value value="61" name="PERF_SP_LM_BANK_CONFLICTS"/>
674 <value value="62" name="PERF_SP_TEX_CONTROL_WORKING_CYCLES"/>
675 <value value="63" name="PERF_SP_LOAD_CONTROL_WORKING_CYCLES"/>
676 <value value="64" name="PERF_SP_FLOW_CONTROL_WORKING_CYCLES"/>
677 <value value="65" name="PERF_SP_LM_WORKING_CYCLES"/>
678 <value value="66" name="PERF_SP_DISPATCHER_WORKING_CYCLES"/>
679 <value value="67" name="PERF_SP_SEQUENCER_WORKING_CYCLES"/>
680 <value value="68" name="PERF_SP_LOW_EFFICIENCY_STARVED_BY_TP"/>
681 <value value="69" name="PERF_SP_STARVE_CYCLES_HLSQ"/>
682 <value value="70" name="PERF_SP_NON_EXECUTION_LS_CYCLES"/>
683 <value value="71" name="PERF_SP_WORKING_EU"/>
684 <value value="72" name="PERF_SP_ANY_EU_WORKING"/>
685 <value value="73" name="PERF_SP_WORKING_EU_FS_STAGE"/>
686 <value value="74" name="PERF_SP_ANY_EU_WORKING_FS_STAGE"/>
687 <value value="75" name="PERF_SP_WORKING_EU_VS_STAGE"/>
688 <value value="76" name="PERF_SP_ANY_EU_WORKING_VS_STAGE"/>
689 <value value="77" name="PERF_SP_WORKING_EU_CS_STAGE"/>
690 <value value="78" name="PERF_SP_ANY_EU_WORKING_CS_STAGE"/>
691 <value value="79" name="PERF_SP_GPR_READ_PREFETCH"/>
692 <value value="80" name="PERF_SP_GPR_READ_CONFLICT"/>
693 <value value="81" name="PERF_SP_GPR_WRITE_CONFLICT"/>
694 <value value="82" name="PERF_SP_GM_LOAD_LATENCY_CYCLES"/>
695 <value value="83" name="PERF_SP_GM_LOAD_LATENCY_SAMPLES"/>
696 <value value="84" name="PERF_SP_EXECUTABLE_WAVES"/>
697 </enum>
698
699 <enum name="a6xx_rb_perfcounter_select">
700 <value value="0" name="PERF_RB_BUSY_CYCLES"/>
701 <value value="1" name="PERF_RB_STALL_CYCLES_HLSQ"/>
702 <value value="2" name="PERF_RB_STALL_CYCLES_FIFO0_FULL"/>
703 <value value="3" name="PERF_RB_STALL_CYCLES_FIFO1_FULL"/>
704 <value value="4" name="PERF_RB_STALL_CYCLES_FIFO2_FULL"/>
705 <value value="5" name="PERF_RB_STARVE_CYCLES_SP"/>
706 <value value="6" name="PERF_RB_STARVE_CYCLES_LRZ_TILE"/>
707 <value value="7" name="PERF_RB_STARVE_CYCLES_CCU"/>
708 <value value="8" name="PERF_RB_STARVE_CYCLES_Z_PLANE"/>
709 <value value="9" name="PERF_RB_STARVE_CYCLES_BARY_PLANE"/>
710 <value value="10" name="PERF_RB_Z_WORKLOAD"/>
711 <value value="11" name="PERF_RB_HLSQ_ACTIVE"/>
712 <value value="12" name="PERF_RB_Z_READ"/>
713 <value value="13" name="PERF_RB_Z_WRITE"/>
714 <value value="14" name="PERF_RB_C_READ"/>
715 <value value="15" name="PERF_RB_C_WRITE"/>
716 <value value="16" name="PERF_RB_TOTAL_PASS"/>
717 <value value="17" name="PERF_RB_Z_PASS"/>
718 <value value="18" name="PERF_RB_Z_FAIL"/>
719 <value value="19" name="PERF_RB_S_FAIL"/>
720 <value value="20" name="PERF_RB_BLENDED_FXP_COMPONENTS"/>
721 <value value="21" name="PERF_RB_BLENDED_FP16_COMPONENTS"/>
722 <value value="22" name="PERF_RB_PS_INVOCATIONS"/>
723 <value value="23" name="PERF_RB_2D_ALIVE_CYCLES"/>
724 <value value="24" name="PERF_RB_2D_STALL_CYCLES_A2D"/>
725 <value value="25" name="PERF_RB_2D_STARVE_CYCLES_SRC"/>
726 <value value="26" name="PERF_RB_2D_STARVE_CYCLES_SP"/>
727 <value value="27" name="PERF_RB_2D_STARVE_CYCLES_DST"/>
728 <value value="28" name="PERF_RB_2D_VALID_PIXELS"/>
729 <value value="29" name="PERF_RB_3D_PIXELS"/>
730 <value value="30" name="PERF_RB_BLENDER_WORKING_CYCLES"/>
731 <value value="31" name="PERF_RB_ZPROC_WORKING_CYCLES"/>
732 <value value="32" name="PERF_RB_CPROC_WORKING_CYCLES"/>
733 <value value="33" name="PERF_RB_SAMPLER_WORKING_CYCLES"/>
734 <value value="34" name="PERF_RB_STALL_CYCLES_CCU_COLOR_READ"/>
735 <value value="35" name="PERF_RB_STALL_CYCLES_CCU_COLOR_WRITE"/>
736 <value value="36" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_READ"/>
737 <value value="37" name="PERF_RB_STALL_CYCLES_CCU_DEPTH_WRITE"/>
738 <value value="38" name="PERF_RB_STALL_CYCLES_VPC"/>
739 <value value="39" name="PERF_RB_2D_INPUT_TRANS"/>
740 <value value="40" name="PERF_RB_2D_OUTPUT_RB_DST_TRANS"/>
741 <value value="41" name="PERF_RB_2D_OUTPUT_RB_SRC_TRANS"/>
742 <value value="42" name="PERF_RB_BLENDED_FP32_COMPONENTS"/>
743 <value value="43" name="PERF_RB_COLOR_PIX_TILES"/>
744 <value value="44" name="PERF_RB_STALL_CYCLES_CCU"/>
745 <value value="45" name="PERF_RB_EARLY_Z_ARB3_GRANT"/>
746 <value value="46" name="PERF_RB_LATE_Z_ARB3_GRANT"/>
747 <value value="47" name="PERF_RB_EARLY_Z_SKIP_GRANT"/>
748 </enum>
749
750 <enum name="a6xx_vsc_perfcounter_select">
751 <value value="0" name="PERF_VSC_BUSY_CYCLES"/>
752 <value value="1" name="PERF_VSC_WORKING_CYCLES"/>
753 <value value="2" name="PERF_VSC_STALL_CYCLES_UCHE"/>
754 <value value="3" name="PERF_VSC_EOT_NUM"/>
755 <value value="4" name="PERF_VSC_INPUT_TILES"/>
756 </enum>
757
758 <enum name="a6xx_ccu_perfcounter_select">
759 <value value="0" name="PERF_CCU_BUSY_CYCLES"/>
760 <value value="1" name="PERF_CCU_STALL_CYCLES_RB_DEPTH_RETURN"/>
761 <value value="2" name="PERF_CCU_STALL_CYCLES_RB_COLOR_RETURN"/>
762 <value value="3" name="PERF_CCU_STARVE_CYCLES_FLAG_RETURN"/>
763 <value value="4" name="PERF_CCU_DEPTH_BLOCKS"/>
764 <value value="5" name="PERF_CCU_COLOR_BLOCKS"/>
765 <value value="6" name="PERF_CCU_DEPTH_BLOCK_HIT"/>
766 <value value="7" name="PERF_CCU_COLOR_BLOCK_HIT"/>
767 <value value="8" name="PERF_CCU_PARTIAL_BLOCK_READ"/>
768 <value value="9" name="PERF_CCU_GMEM_READ"/>
769 <value value="10" name="PERF_CCU_GMEM_WRITE"/>
770 <value value="11" name="PERF_CCU_DEPTH_READ_FLAG0_COUNT"/>
771 <value value="12" name="PERF_CCU_DEPTH_READ_FLAG1_COUNT"/>
772 <value value="13" name="PERF_CCU_DEPTH_READ_FLAG2_COUNT"/>
773 <value value="14" name="PERF_CCU_DEPTH_READ_FLAG3_COUNT"/>
774 <value value="15" name="PERF_CCU_DEPTH_READ_FLAG4_COUNT"/>
775 <value value="16" name="PERF_CCU_DEPTH_READ_FLAG5_COUNT"/>
776 <value value="17" name="PERF_CCU_DEPTH_READ_FLAG6_COUNT"/>
777 <value value="18" name="PERF_CCU_DEPTH_READ_FLAG8_COUNT"/>
778 <value value="19" name="PERF_CCU_COLOR_READ_FLAG0_COUNT"/>
779 <value value="20" name="PERF_CCU_COLOR_READ_FLAG1_COUNT"/>
780 <value value="21" name="PERF_CCU_COLOR_READ_FLAG2_COUNT"/>
781 <value value="22" name="PERF_CCU_COLOR_READ_FLAG3_COUNT"/>
782 <value value="23" name="PERF_CCU_COLOR_READ_FLAG4_COUNT"/>
783 <value value="24" name="PERF_CCU_COLOR_READ_FLAG5_COUNT"/>
784 <value value="25" name="PERF_CCU_COLOR_READ_FLAG6_COUNT"/>
785 <value value="26" name="PERF_CCU_COLOR_READ_FLAG8_COUNT"/>
786 <value value="27" name="PERF_CCU_2D_RD_REQ"/>
787 <value value="28" name="PERF_CCU_2D_WR_REQ"/>
788 </enum>
789
790 <enum name="a6xx_lrz_perfcounter_select">
791 <value value="0" name="PERF_LRZ_BUSY_CYCLES"/>
792 <value value="1" name="PERF_LRZ_STARVE_CYCLES_RAS"/>
793 <value value="2" name="PERF_LRZ_STALL_CYCLES_RB"/>
794 <value value="3" name="PERF_LRZ_STALL_CYCLES_VSC"/>
795 <value value="4" name="PERF_LRZ_STALL_CYCLES_VPC"/>
796 <value value="5" name="PERF_LRZ_STALL_CYCLES_FLAG_PREFETCH"/>
797 <value value="6" name="PERF_LRZ_STALL_CYCLES_UCHE"/>
798 <value value="7" name="PERF_LRZ_LRZ_READ"/>
799 <value value="8" name="PERF_LRZ_LRZ_WRITE"/>
800 <value value="9" name="PERF_LRZ_READ_LATENCY"/>
801 <value value="10" name="PERF_LRZ_MERGE_CACHE_UPDATING"/>
802 <value value="11" name="PERF_LRZ_PRIM_KILLED_BY_MASKGEN"/>
803 <value value="12" name="PERF_LRZ_PRIM_KILLED_BY_LRZ"/>
804 <value value="13" name="PERF_LRZ_VISIBLE_PRIM_AFTER_LRZ"/>
805 <value value="14" name="PERF_LRZ_FULL_8X8_TILES"/>
806 <value value="15" name="PERF_LRZ_PARTIAL_8X8_TILES"/>
807 <value value="16" name="PERF_LRZ_TILE_KILLED"/>
808 <value value="17" name="PERF_LRZ_TOTAL_PIXEL"/>
809 <value value="18" name="PERF_LRZ_VISIBLE_PIXEL_AFTER_LRZ"/>
810 <value value="19" name="PERF_LRZ_FULLY_COVERED_TILES"/>
811 <value value="20" name="PERF_LRZ_PARTIAL_COVERED_TILES"/>
812 <value value="21" name="PERF_LRZ_FEEDBACK_ACCEPT"/>
813 <value value="22" name="PERF_LRZ_FEEDBACK_DISCARD"/>
814 <value value="23" name="PERF_LRZ_FEEDBACK_STALL"/>
815 <value value="24" name="PERF_LRZ_STALL_CYCLES_RB_ZPLANE"/>
816 <value value="25" name="PERF_LRZ_STALL_CYCLES_RB_BPLANE"/>
817 <value value="26" name="PERF_LRZ_STALL_CYCLES_VC"/>
818 <value value="27" name="PERF_LRZ_RAS_MASK_TRANS"/>
819 </enum>
820
821 <enum name="a6xx_cmp_perfcounter_select">
822 <value value="0" name="PERF_CMPDECMP_STALL_CYCLES_ARB"/>
823 <value value="1" name="PERF_CMPDECMP_VBIF_LATENCY_CYCLES"/>
824 <value value="2" name="PERF_CMPDECMP_VBIF_LATENCY_SAMPLES"/>
825 <value value="3" name="PERF_CMPDECMP_VBIF_READ_DATA_CCU"/>
826 <value value="4" name="PERF_CMPDECMP_VBIF_WRITE_DATA_CCU"/>
827 <value value="5" name="PERF_CMPDECMP_VBIF_READ_REQUEST"/>
828 <value value="6" name="PERF_CMPDECMP_VBIF_WRITE_REQUEST"/>
829 <value value="7" name="PERF_CMPDECMP_VBIF_READ_DATA"/>
830 <value value="8" name="PERF_CMPDECMP_VBIF_WRITE_DATA"/>
831 <value value="9" name="PERF_CMPDECMP_FLAG_FETCH_CYCLES"/>
832 <value value="10" name="PERF_CMPDECMP_FLAG_FETCH_SAMPLES"/>
833 <value value="11" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG1_COUNT"/>
834 <value value="12" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG2_COUNT"/>
835 <value value="13" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG3_COUNT"/>
836 <value value="14" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG4_COUNT"/>
837 <value value="15" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG5_COUNT"/>
838 <value value="16" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG6_COUNT"/>
839 <value value="17" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG8_COUNT"/>
840 <value value="18" name="PERF_CMPDECMP_COLOR_WRITE_FLAG1_COUNT"/>
841 <value value="19" name="PERF_CMPDECMP_COLOR_WRITE_FLAG2_COUNT"/>
842 <value value="20" name="PERF_CMPDECMP_COLOR_WRITE_FLAG3_COUNT"/>
843 <value value="21" name="PERF_CMPDECMP_COLOR_WRITE_FLAG4_COUNT"/>
844 <value value="22" name="PERF_CMPDECMP_COLOR_WRITE_FLAG5_COUNT"/>
845 <value value="23" name="PERF_CMPDECMP_COLOR_WRITE_FLAG6_COUNT"/>
846 <value value="24" name="PERF_CMPDECMP_COLOR_WRITE_FLAG8_COUNT"/>
847 <value value="25" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_REQ"/>
848 <value value="26" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_WR"/>
849 <value value="27" name="PERF_CMPDECMP_2D_STALL_CYCLES_VBIF_RETURN"/>
850 <value value="28" name="PERF_CMPDECMP_2D_RD_DATA"/>
851 <value value="29" name="PERF_CMPDECMP_2D_WR_DATA"/>
852 <value value="30" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH0"/>
853 <value value="31" name="PERF_CMPDECMP_VBIF_READ_DATA_UCHE_CH1"/>
854 <value value="32" name="PERF_CMPDECMP_2D_OUTPUT_TRANS"/>
855 <value value="33" name="PERF_CMPDECMP_VBIF_WRITE_DATA_UCHE"/>
856 <value value="34" name="PERF_CMPDECMP_DEPTH_WRITE_FLAG0_COUNT"/>
857 <value value="35" name="PERF_CMPDECMP_COLOR_WRITE_FLAG0_COUNT"/>
858 <value value="36" name="PERF_CMPDECMP_COLOR_WRITE_FLAGALPHA_COUNT"/>
859 <value value="37" name="PERF_CMPDECMP_2D_BUSY_CYCLES"/>
860 <value value="38" name="PERF_CMPDECMP_2D_REORDER_STARVE_CYCLES"/>
861 <value value="39" name="PERF_CMPDECMP_2D_PIXELS"/>
862 </enum>
863
864 <!--
865 Used in a6xx_2d_blit_cntl.. the value mostly seems to correlate to the
866 component type/size, so I think it relates to internal format used for
867 blending? The one exception is that 16b unorm and 32b float use the
868 same value... maybe 16b unorm is uncommon enough that it was just easier
869 to upconvert to 32b float internally?
870
871 8b unorm: 10 (sometimes 0, is the high bit part of something else?)
872 16b unorm: 4
873
874 32b int: 7
875 16b int: 6
876 8b int: 5
877
878 32b float: 4
879 16b float: 3
880 -->
881 <enum name="a6xx_2d_ifmt">
882 <value value="0x10" name="R2D_UNORM8"/>
883 <value value="0x7" name="R2D_INT32"/>
884 <value value="0x6" name="R2D_INT16"/>
885 <value value="0x5" name="R2D_INT8"/>
886 <value value="0x4" name="R2D_FLOAT32"/>
887 <value value="0x3" name="R2D_FLOAT16"/>
888 <value value="0x1" name="R2D_UNORM8_SRGB"/>
889 <value value="0x0" name="R2D_RAW"/>
890 </enum>
891
892 <enum name="a6xx_ztest_mode">
893 <doc>Allow early z-test and early-lrz (if applicable)</doc>
894 <value value="0x0" name="A6XX_EARLY_Z"/>
895 <doc>Disable early z-test and early-lrz test (if applicable)</doc>
896 <value value="0x1" name="A6XX_LATE_Z"/>
897 <doc>
898 A special mode that allows early-lrz test but disables
899 early-z test. Which might sound a bit funny, since
900 lrz-test happens before z-test. But as long as a couple
901 conditions are maintained this allows using lrz-test in
902 cases where fragment shader has kill/discard:
903
904 1) Disable lrz-write in cases where it is uncertain during
905 binning pass that a fragment will pass. Ie. if frag
906 shader has-kill, writes-z, or alpha/stencil test is
907 enabled. (For correctness, lrz-write must be disabled
908 when blend is enabled.) This is analogous to how a
909 z-prepass works.
910
911 2) Disable lrz-write and test if a depth-test direction
912 reversal is detected. Due to condition (1), the contents
913 of the lrz buffer are a conservative estimation of the
914 depth buffer during the draw pass. Meaning that geometry
915 that we know for certain will not be visible will not pass
916 lrz-test. But geometry which may be (or contributes to
917 blend) will pass the lrz-test.
918
919 This allows us to keep early-lrz-test in cases where the frag
920 shader does not write-z (ie. we know the z-value before FS)
921 and does not have side-effects (image/ssbo writes, etc), but
922 does have kill/discard. Which turns out to be a common
923 enough case that it is useful to keep early-lrz test against
924 the conservative lrz buffer to discard fragments that we
925 know will definitely not be visible.
926 </doc>
927 <value value="0x2" name="A6XX_EARLY_LRZ_LATE_Z"/>
928 </enum>
929
930 <domain name="A6XX" width="32">
931 <bitset name="A6XX_RBBM_INT_0_MASK" inline="no">
932 <bitfield name="RBBM_GPU_IDLE" pos="0" type="boolean"/>
933 <bitfield name="CP_AHB_ERROR" pos="1" type="boolean"/>
934 <bitfield name="RBBM_ATB_ASYNCFIFO_OVERFLOW" pos="6" type="boolean"/>
935 <bitfield name="RBBM_GPC_ERROR" pos="7" type="boolean"/>
936 <bitfield name="CP_SW" pos="8" type="boolean"/>
937 <bitfield name="CP_HW_ERROR" pos="9" type="boolean"/>
938 <bitfield name="CP_CCU_FLUSH_DEPTH_TS" pos="10" type="boolean"/>
939 <bitfield name="CP_CCU_FLUSH_COLOR_TS" pos="11" type="boolean"/>
940 <bitfield name="CP_CCU_RESOLVE_TS" pos="12" type="boolean"/>
941 <bitfield name="CP_IB2" pos="13" type="boolean"/>
942 <bitfield name="CP_IB1" pos="14" type="boolean"/>
943 <bitfield name="CP_RB" pos="15" type="boolean"/>
944 <bitfield name="CP_RB_DONE_TS" pos="17" type="boolean"/>
945 <bitfield name="CP_WT_DONE_TS" pos="18" type="boolean"/>
946 <bitfield name="CP_CACHE_FLUSH_TS" pos="20" type="boolean"/>
947 <bitfield name="RBBM_ATB_BUS_OVERFLOW" pos="22" type="boolean"/>
948 <bitfield name="RBBM_HANG_DETECT" pos="23" type="boolean"/>
949 <bitfield name="UCHE_OOB_ACCESS" pos="24" type="boolean"/>
950 <bitfield name="UCHE_TRAP_INTR" pos="25" type="boolean"/>
951 <bitfield name="DEBBUS_INTR_0" pos="26" type="boolean"/>
952 <bitfield name="DEBBUS_INTR_1" pos="27" type="boolean"/>
953 <bitfield name="ISDB_CPU_IRQ" pos="30" type="boolean"/>
954 <bitfield name="ISDB_UNDER_DEBUG" pos="31" type="boolean"/>
955 </bitset>
956
957 <bitset name="A6XX_CP_INT">
958 <bitfield name="CP_OPCODE_ERROR" pos="0" type="boolean"/>
959 <bitfield name="CP_UCODE_ERROR" pos="1" type="boolean"/>
960 <bitfield name="CP_HW_FAULT_ERROR" pos="2" type="boolean"/>
961 <bitfield name="CP_REGISTER_PROTECTION_ERROR" pos="4" type="boolean"/>
962 <bitfield name="CP_AHB_ERROR" pos="5" type="boolean"/>
963 <bitfield name="CP_VSD_PARITY_ERROR" pos="6" type="boolean"/>
964 <bitfield name="CP_ILLEGAL_INSTR_ERROR" pos="7" type="boolean"/>
965 </bitset>
966
967 <reg32 offset="0x0800" name="CP_RB_BASE"/>
968 <reg32 offset="0x0801" name="CP_RB_BASE_HI"/>
969 <reg32 offset="0x0802" name="CP_RB_CNTL"/>
970 <reg32 offset="0x0804" name="CP_RB_RPTR_ADDR_LO"/>
971 <reg32 offset="0x0805" name="CP_RB_RPTR_ADDR_HI"/>
972 <reg32 offset="0x0806" name="CP_RB_RPTR"/>
973 <reg32 offset="0x0807" name="CP_RB_WPTR"/>
974 <reg32 offset="0x0808" name="CP_SQE_CNTL"/>
975 <reg32 offset="0x0812" name="CP_CP2GMU_STATUS">
976 <bitfield name="IFPC" pos="0" type="boolean"/>
977 </reg32>
978 <reg32 offset="0x0821" name="CP_HW_FAULT"/>
979 <reg32 offset="0x0823" name="CP_INTERRUPT_STATUS"/>
980 <reg32 offset="0x0824" name="CP_PROTECT_STATUS"/>
981 <reg32 offset="0x0830" name="CP_SQE_INSTR_BASE_LO"/>
982 <reg32 offset="0x0831" name="CP_SQE_INSTR_BASE_HI"/>
983 <reg32 offset="0x0840" name="CP_MISC_CNTL"/>
984 <reg32 offset="0x0844" name="CP_APRIV_CNTL"/>
985 <!-- all the threshold values seem to be in units of quad-dwords: -->
986 <reg32 offset="0x08C1" name="CP_ROQ_THRESHOLDS_1">
987 <doc>
988 b0..7 seems to contain the size of buffered by not yet processed
989 RB level cmdstream.. it's possible that it is a low threshold
990 and b8..15 is a high threshold?
991
992 b16..23 identifies where IB1 data starts (and RB data ends?)
993
994 b24..31 identifies where IB2 data starts (and IB1 data ends)
995 </doc>
996 <bitfield name="RB_LO" low="0" high="7" shr="2"/>
997 <bitfield name="RB_HI" low="8" high="15" shr="2"/>
998 <bitfield name="IB1_START" low="16" high="23" shr="2"/>
999 <bitfield name="IB2_START" low="24" high="31" shr="2"/>
1000 </reg32>
1001 <reg32 offset="0x08C2" name="CP_ROQ_THRESHOLDS_2">
1002 <doc>
1003 low bits identify where CP_SET_DRAW_STATE stateobj
1004 processing starts (and IB2 data ends). I'm guessing
1005 b8 is part of this since (from downstream kgsl):
1006
1007 /* ROQ sizes are twice as big on a640/a680 than on a630 */
1008 if (adreno_is_a640(adreno_dev) || adreno_is_a680(adreno_dev)) {
1009 kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_2, 0x02000140);
1010 kgsl_regwrite(device, A6XX_CP_ROQ_THRESHOLDS_1, 0x8040362C);
1011 } ...
1012 </doc>
1013 <bitfield name="SDS_START" low="0" high="8" shr="2"/>
1014 <!-- total ROQ size: -->
1015 <bitfield name="ROQ_SIZE" low="16" high="31" shr="2"/>
1016 </reg32>
1017 <reg32 offset="0x08C3" name="CP_MEM_POOL_SIZE"/>
1018 <reg32 offset="0x0841" name="CP_CHICKEN_DBG"/>
1019 <reg32 offset="0x0842" name="CP_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1020 <reg32 offset="0x0843" name="CP_DBG_ECO_CNTL"/>
1021 <reg32 offset="0x084F" name="CP_PROTECT_CNTL"/>
1022
1023 <array offset="0x0883" name="CP_SCRATCH" stride="1" length="8">
1024 <reg32 offset="0x0" name="REG" type="uint"/>
1025 </array>
1026 <array offset="0x0850" name="CP_PROTECT" stride="1" length="32">
1027 <reg32 offset="0x0" name="REG" type="a6x_cp_protect"/>
1028 </array>
1029
1030 <reg32 offset="0x08A0" name="CP_CONTEXT_SWITCH_CNTL"/>
1031 <reg32 offset="0x08A1" name="CP_CONTEXT_SWITCH_SMMU_INFO_LO"/>
1032 <reg32 offset="0x08A2" name="CP_CONTEXT_SWITCH_SMMU_INFO_HI"/>
1033 <reg32 offset="0x08A3" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_LO"/>
1034 <reg32 offset="0x08A4" name="CP_CONTEXT_SWITCH_PRIV_NON_SECURE_RESTORE_ADDR_HI"/>
1035 <reg32 offset="0x08A5" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_LO"/>
1036 <reg32 offset="0x08A6" name="CP_CONTEXT_SWITCH_PRIV_SECURE_RESTORE_ADDR_HI"/>
1037 <reg32 offset="0x08A7" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_LO"/>
1038 <reg32 offset="0x08A8" name="CP_CONTEXT_SWITCH_NON_PRIV_RESTORE_ADDR_HI"/>
1039 <reg32 offset="0x08D0" name="CP_PERFCTR_CP_SEL_0"/>
1040 <reg32 offset="0x08D1" name="CP_PERFCTR_CP_SEL_1"/>
1041 <reg32 offset="0x08D2" name="CP_PERFCTR_CP_SEL_2"/>
1042 <reg32 offset="0x08D3" name="CP_PERFCTR_CP_SEL_3"/>
1043 <reg32 offset="0x08D4" name="CP_PERFCTR_CP_SEL_4"/>
1044 <reg32 offset="0x08D5" name="CP_PERFCTR_CP_SEL_5"/>
1045 <reg32 offset="0x08D6" name="CP_PERFCTR_CP_SEL_6"/>
1046 <reg32 offset="0x08D7" name="CP_PERFCTR_CP_SEL_7"/>
1047 <reg32 offset="0x08D8" name="CP_PERFCTR_CP_SEL_8"/>
1048 <reg32 offset="0x08D9" name="CP_PERFCTR_CP_SEL_9"/>
1049 <reg32 offset="0x08DA" name="CP_PERFCTR_CP_SEL_10"/>
1050 <reg32 offset="0x08DB" name="CP_PERFCTR_CP_SEL_11"/>
1051 <reg32 offset="0x08DC" name="CP_PERFCTR_CP_SEL_12"/>
1052 <reg32 offset="0x08DD" name="CP_PERFCTR_CP_SEL_13"/>
1053 <reg32 offset="0x0900" name="CP_CRASH_SCRIPT_BASE_LO"/>
1054 <reg32 offset="0x0901" name="CP_CRASH_SCRIPT_BASE_HI"/>
1055 <reg32 offset="0x0902" name="CP_CRASH_DUMP_CNTL"/>
1056 <reg32 offset="0x0903" name="CP_CRASH_DUMP_STATUS"/>
1057 <reg32 offset="0x0908" name="CP_SQE_STAT_ADDR"/>
1058 <reg32 offset="0x0909" name="CP_SQE_STAT_DATA"/>
1059 <reg32 offset="0x090A" name="CP_DRAW_STATE_ADDR"/>
1060 <reg32 offset="0x090B" name="CP_DRAW_STATE_DATA"/>
1061 <reg32 offset="0x090C" name="CP_ROQ_DBG_ADDR"/>
1062 <reg32 offset="0x090D" name="CP_ROQ_DBG_DATA"/>
1063 <reg32 offset="0x090E" name="CP_MEM_POOL_DBG_ADDR"/>
1064 <reg32 offset="0x090F" name="CP_MEM_POOL_DBG_DATA"/>
1065 <reg32 offset="0x0910" name="CP_SQE_UCODE_DBG_ADDR"/>
1066 <reg32 offset="0x0911" name="CP_SQE_UCODE_DBG_DATA"/>
1067 <reg32 offset="0x0928" name="CP_IB1_BASE"/>
1068 <reg32 offset="0x0929" name="CP_IB1_BASE_HI"/>
1069 <reg32 offset="0x092A" name="CP_IB1_REM_SIZE"/>
1070 <reg32 offset="0x092B" name="CP_IB2_BASE"/>
1071 <reg32 offset="0x092C" name="CP_IB2_BASE_HI"/>
1072 <reg32 offset="0x092D" name="CP_IB2_REM_SIZE"/>
1073 <!-- SDS == CP_SET_DRAW_STATE: -->
1074 <reg32 offset="0x092e" name="CP_SDS_BASE"/>
1075 <reg32 offset="0x092f" name="CP_SDS_BASE_HI"/>
1076 <reg32 offset="0x092e" name="CP_SDS_REM_SIZE"/>
1077 <reg32 offset="0x0931" name="CP_BIN_SIZE_ADDRESS"/>
1078 <reg32 offset="0x0932" name="CP_BIN_SIZE_ADDRESS_HI"/>
1079 <reg32 offset="0x0934" name="CP_BIN_DATA_ADDR"/>
1080 <reg32 offset="0x0935" name="CP_BIN_DATA_ADDR_HI"/>
1081 <!--
1082 There are probably similar registers for RB and SDS, teasing out SDS will
1083 take a slightly better test case..
1084 -->
1085 <reg32 offset="0x0949" name="CP_CSQ_IB1_STAT">
1086 <doc>number of remaining dwords incl current dword being consumed?</doc>
1087 <bitfield name="REM" low="16" high="31"/>
1088 </reg32>
1089 <reg32 offset="0x094a" name="CP_CSQ_IB2_STAT">
1090 <doc>number of remaining dwords incl current dword being consumed?</doc>
1091 <bitfield name="REM" low="16" high="31"/>
1092 </reg32>
1093 <reg32 offset="0x0980" name="CP_ALWAYS_ON_COUNTER_LO"/>
1094 <reg32 offset="0x0981" name="CP_ALWAYS_ON_COUNTER_HI"/>
1095 <reg32 offset="0x098D" name="CP_AHB_CNTL"/>
1096 <reg32 offset="0x0A00" name="CP_APERTURE_CNTL_HOST"/>
1097 <reg32 offset="0x0A03" name="CP_APERTURE_CNTL_CD"/>
1098 <reg32 offset="0x0C01" name="VSC_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1099 <reg32 offset="0x0201" name="RBBM_INT_0_STATUS" type="A6XX_RBBM_INT_0_MASK"/>
1100 <reg32 offset="0x0210" name="RBBM_STATUS">
1101 <bitfield pos="23" name="GPU_BUSY_IGN_AHB" type="boolean"/>
1102 <bitfield pos="22" name="GPU_BUSY_IGN_AHB_CP" type="boolean"/>
1103 <bitfield pos="21" name="HLSQ_BUSY" type="boolean"/>
1104 <bitfield pos="20" name="VSC_BUSY" type="boolean"/>
1105 <bitfield pos="19" name="TPL1_BUSY" type="boolean"/>
1106 <bitfield pos="18" name="SP_BUSY" type="boolean"/>
1107 <bitfield pos="17" name="UCHE_BUSY" type="boolean"/>
1108 <bitfield pos="16" name="VPC_BUSY" type="boolean"/>
1109 <bitfield pos="15" name="VFD_BUSY" type="boolean"/>
1110 <bitfield pos="14" name="TESS_BUSY" type="boolean"/>
1111 <bitfield pos="13" name="PC_VSD_BUSY" type="boolean"/>
1112 <bitfield pos="12" name="PC_DCALL_BUSY" type="boolean"/>
1113 <bitfield pos="11" name="COM_DCOM_BUSY" type="boolean"/>
1114 <bitfield pos="10" name="LRZ_BUSY" type="boolean"/>
1115 <bitfield pos="9" name="A2D_BUSY" type="boolean"/>
1116 <bitfield pos="8" name="CCU_BUSY" type="boolean"/>
1117 <bitfield pos="7" name="RB_BUSY" type="boolean"/>
1118 <bitfield pos="6" name="RAS_BUSY" type="boolean"/>
1119 <bitfield pos="5" name="TSE_BUSY" type="boolean"/>
1120 <bitfield pos="4" name="VBIF_BUSY" type="boolean"/>
1121 <bitfield pos="3" name="GFX_DBGC_BUSY" type="boolean"/>
1122 <bitfield pos="2" name="CP_BUSY" type="boolean"/>
1123 <bitfield pos="1" name="CP_AHB_BUSY_CP_MASTER" type="boolean"/>
1124 <bitfield pos="0" name="CP_AHB_BUSY_CX_MASTER" type="boolean"/>
1125 </reg32>
1126 <reg32 offset="0x0213" name="RBBM_STATUS3">
1127 <bitfield pos="24" name="SMMU_STALLED_ON_FAULT" type="boolean"/>
1128 </reg32>
1129 <reg32 offset="0x0215" name="RBBM_VBIF_GX_RESET_STATUS"/>
1130 <reg32 offset="0x0400" name="RBBM_PERFCTR_CP_0_LO"/>
1131 <reg32 offset="0x0401" name="RBBM_PERFCTR_CP_0_HI"/>
1132 <reg32 offset="0x0402" name="RBBM_PERFCTR_CP_1_LO"/>
1133 <reg32 offset="0x0403" name="RBBM_PERFCTR_CP_1_HI"/>
1134 <reg32 offset="0x0404" name="RBBM_PERFCTR_CP_2_LO"/>
1135 <reg32 offset="0x0405" name="RBBM_PERFCTR_CP_2_HI"/>
1136 <reg32 offset="0x0406" name="RBBM_PERFCTR_CP_3_LO"/>
1137 <reg32 offset="0x0407" name="RBBM_PERFCTR_CP_3_HI"/>
1138 <reg32 offset="0x0408" name="RBBM_PERFCTR_CP_4_LO"/>
1139 <reg32 offset="0x0409" name="RBBM_PERFCTR_CP_4_HI"/>
1140 <reg32 offset="0x040a" name="RBBM_PERFCTR_CP_5_LO"/>
1141 <reg32 offset="0x040b" name="RBBM_PERFCTR_CP_5_HI"/>
1142 <reg32 offset="0x040c" name="RBBM_PERFCTR_CP_6_LO"/>
1143 <reg32 offset="0x040d" name="RBBM_PERFCTR_CP_6_HI"/>
1144 <reg32 offset="0x040e" name="RBBM_PERFCTR_CP_7_LO"/>
1145 <reg32 offset="0x040f" name="RBBM_PERFCTR_CP_7_HI"/>
1146 <reg32 offset="0x0410" name="RBBM_PERFCTR_CP_8_LO"/>
1147 <reg32 offset="0x0411" name="RBBM_PERFCTR_CP_8_HI"/>
1148 <reg32 offset="0x0412" name="RBBM_PERFCTR_CP_9_LO"/>
1149 <reg32 offset="0x0413" name="RBBM_PERFCTR_CP_9_HI"/>
1150 <reg32 offset="0x0414" name="RBBM_PERFCTR_CP_10_LO"/>
1151 <reg32 offset="0x0415" name="RBBM_PERFCTR_CP_10_HI"/>
1152 <reg32 offset="0x0416" name="RBBM_PERFCTR_CP_11_LO"/>
1153 <reg32 offset="0x0417" name="RBBM_PERFCTR_CP_11_HI"/>
1154 <reg32 offset="0x0418" name="RBBM_PERFCTR_CP_12_LO"/>
1155 <reg32 offset="0x0419" name="RBBM_PERFCTR_CP_12_HI"/>
1156 <reg32 offset="0x041a" name="RBBM_PERFCTR_CP_13_LO"/>
1157 <reg32 offset="0x041b" name="RBBM_PERFCTR_CP_13_HI"/>
1158 <reg32 offset="0x041c" name="RBBM_PERFCTR_RBBM_0_LO"/>
1159 <reg32 offset="0x041d" name="RBBM_PERFCTR_RBBM_0_HI"/>
1160 <reg32 offset="0x041e" name="RBBM_PERFCTR_RBBM_1_LO"/>
1161 <reg32 offset="0x041f" name="RBBM_PERFCTR_RBBM_1_HI"/>
1162 <reg32 offset="0x0420" name="RBBM_PERFCTR_RBBM_2_LO"/>
1163 <reg32 offset="0x0421" name="RBBM_PERFCTR_RBBM_2_HI"/>
1164 <reg32 offset="0x0422" name="RBBM_PERFCTR_RBBM_3_LO"/>
1165 <reg32 offset="0x0423" name="RBBM_PERFCTR_RBBM_3_HI"/>
1166 <reg32 offset="0x0424" name="RBBM_PERFCTR_PC_0_LO"/>
1167 <reg32 offset="0x0425" name="RBBM_PERFCTR_PC_0_HI"/>
1168 <reg32 offset="0x0426" name="RBBM_PERFCTR_PC_1_LO"/>
1169 <reg32 offset="0x0427" name="RBBM_PERFCTR_PC_1_HI"/>
1170 <reg32 offset="0x0428" name="RBBM_PERFCTR_PC_2_LO"/>
1171 <reg32 offset="0x0429" name="RBBM_PERFCTR_PC_2_HI"/>
1172 <reg32 offset="0x042a" name="RBBM_PERFCTR_PC_3_LO"/>
1173 <reg32 offset="0x042b" name="RBBM_PERFCTR_PC_3_HI"/>
1174 <reg32 offset="0x042c" name="RBBM_PERFCTR_PC_4_LO"/>
1175 <reg32 offset="0x042d" name="RBBM_PERFCTR_PC_4_HI"/>
1176 <reg32 offset="0x042e" name="RBBM_PERFCTR_PC_5_LO"/>
1177 <reg32 offset="0x042f" name="RBBM_PERFCTR_PC_5_HI"/>
1178 <reg32 offset="0x0430" name="RBBM_PERFCTR_PC_6_LO"/>
1179 <reg32 offset="0x0431" name="RBBM_PERFCTR_PC_6_HI"/>
1180 <reg32 offset="0x0432" name="RBBM_PERFCTR_PC_7_LO"/>
1181 <reg32 offset="0x0433" name="RBBM_PERFCTR_PC_7_HI"/>
1182 <reg32 offset="0x0434" name="RBBM_PERFCTR_VFD_0_LO"/>
1183 <reg32 offset="0x0435" name="RBBM_PERFCTR_VFD_0_HI"/>
1184 <reg32 offset="0x0436" name="RBBM_PERFCTR_VFD_1_LO"/>
1185 <reg32 offset="0x0437" name="RBBM_PERFCTR_VFD_1_HI"/>
1186 <reg32 offset="0x0438" name="RBBM_PERFCTR_VFD_2_LO"/>
1187 <reg32 offset="0x0439" name="RBBM_PERFCTR_VFD_2_HI"/>
1188 <reg32 offset="0x043a" name="RBBM_PERFCTR_VFD_3_LO"/>
1189 <reg32 offset="0x043b" name="RBBM_PERFCTR_VFD_3_HI"/>
1190 <reg32 offset="0x043c" name="RBBM_PERFCTR_VFD_4_LO"/>
1191 <reg32 offset="0x043d" name="RBBM_PERFCTR_VFD_4_HI"/>
1192 <reg32 offset="0x043e" name="RBBM_PERFCTR_VFD_5_LO"/>
1193 <reg32 offset="0x043f" name="RBBM_PERFCTR_VFD_5_HI"/>
1194 <reg32 offset="0x0440" name="RBBM_PERFCTR_VFD_6_LO"/>
1195 <reg32 offset="0x0441" name="RBBM_PERFCTR_VFD_6_HI"/>
1196 <reg32 offset="0x0442" name="RBBM_PERFCTR_VFD_7_LO"/>
1197 <reg32 offset="0x0443" name="RBBM_PERFCTR_VFD_7_HI"/>
1198 <reg32 offset="0x0444" name="RBBM_PERFCTR_HLSQ_0_LO"/>
1199 <reg32 offset="0x0445" name="RBBM_PERFCTR_HLSQ_0_HI"/>
1200 <reg32 offset="0x0446" name="RBBM_PERFCTR_HLSQ_1_LO"/>
1201 <reg32 offset="0x0447" name="RBBM_PERFCTR_HLSQ_1_HI"/>
1202 <reg32 offset="0x0448" name="RBBM_PERFCTR_HLSQ_2_LO"/>
1203 <reg32 offset="0x0449" name="RBBM_PERFCTR_HLSQ_2_HI"/>
1204 <reg32 offset="0x044a" name="RBBM_PERFCTR_HLSQ_3_LO"/>
1205 <reg32 offset="0x044b" name="RBBM_PERFCTR_HLSQ_3_HI"/>
1206 <reg32 offset="0x044c" name="RBBM_PERFCTR_HLSQ_4_LO"/>
1207 <reg32 offset="0x044d" name="RBBM_PERFCTR_HLSQ_4_HI"/>
1208 <reg32 offset="0x044e" name="RBBM_PERFCTR_HLSQ_5_LO"/>
1209 <reg32 offset="0x044f" name="RBBM_PERFCTR_HLSQ_5_HI"/>
1210 <reg32 offset="0x0450" name="RBBM_PERFCTR_VPC_0_LO"/>
1211 <reg32 offset="0x0451" name="RBBM_PERFCTR_VPC_0_HI"/>
1212 <reg32 offset="0x0452" name="RBBM_PERFCTR_VPC_1_LO"/>
1213 <reg32 offset="0x0453" name="RBBM_PERFCTR_VPC_1_HI"/>
1214 <reg32 offset="0x0454" name="RBBM_PERFCTR_VPC_2_LO"/>
1215 <reg32 offset="0x0455" name="RBBM_PERFCTR_VPC_2_HI"/>
1216 <reg32 offset="0x0456" name="RBBM_PERFCTR_VPC_3_LO"/>
1217 <reg32 offset="0x0457" name="RBBM_PERFCTR_VPC_3_HI"/>
1218 <reg32 offset="0x0458" name="RBBM_PERFCTR_VPC_4_LO"/>
1219 <reg32 offset="0x0459" name="RBBM_PERFCTR_VPC_4_HI"/>
1220 <reg32 offset="0x045a" name="RBBM_PERFCTR_VPC_5_LO"/>
1221 <reg32 offset="0x045b" name="RBBM_PERFCTR_VPC_5_HI"/>
1222 <reg32 offset="0x045c" name="RBBM_PERFCTR_CCU_0_LO"/>
1223 <reg32 offset="0x045d" name="RBBM_PERFCTR_CCU_0_HI"/>
1224 <reg32 offset="0x045e" name="RBBM_PERFCTR_CCU_1_LO"/>
1225 <reg32 offset="0x045f" name="RBBM_PERFCTR_CCU_1_HI"/>
1226 <reg32 offset="0x0460" name="RBBM_PERFCTR_CCU_2_LO"/>
1227 <reg32 offset="0x0461" name="RBBM_PERFCTR_CCU_2_HI"/>
1228 <reg32 offset="0x0462" name="RBBM_PERFCTR_CCU_3_LO"/>
1229 <reg32 offset="0x0463" name="RBBM_PERFCTR_CCU_3_HI"/>
1230 <reg32 offset="0x0464" name="RBBM_PERFCTR_CCU_4_LO"/>
1231 <reg32 offset="0x0465" name="RBBM_PERFCTR_CCU_4_HI"/>
1232 <reg32 offset="0x0466" name="RBBM_PERFCTR_TSE_0_LO"/>
1233 <reg32 offset="0x0467" name="RBBM_PERFCTR_TSE_0_HI"/>
1234 <reg32 offset="0x0468" name="RBBM_PERFCTR_TSE_1_LO"/>
1235 <reg32 offset="0x0469" name="RBBM_PERFCTR_TSE_1_HI"/>
1236 <reg32 offset="0x046a" name="RBBM_PERFCTR_TSE_2_LO"/>
1237 <reg32 offset="0x046b" name="RBBM_PERFCTR_TSE_2_HI"/>
1238 <reg32 offset="0x046c" name="RBBM_PERFCTR_TSE_3_LO"/>
1239 <reg32 offset="0x046d" name="RBBM_PERFCTR_TSE_3_HI"/>
1240 <reg32 offset="0x046e" name="RBBM_PERFCTR_RAS_0_LO"/>
1241 <reg32 offset="0x046f" name="RBBM_PERFCTR_RAS_0_HI"/>
1242 <reg32 offset="0x0470" name="RBBM_PERFCTR_RAS_1_LO"/>
1243 <reg32 offset="0x0471" name="RBBM_PERFCTR_RAS_1_HI"/>
1244 <reg32 offset="0x0472" name="RBBM_PERFCTR_RAS_2_LO"/>
1245 <reg32 offset="0x0473" name="RBBM_PERFCTR_RAS_2_HI"/>
1246 <reg32 offset="0x0474" name="RBBM_PERFCTR_RAS_3_LO"/>
1247 <reg32 offset="0x0475" name="RBBM_PERFCTR_RAS_3_HI"/>
1248 <reg32 offset="0x0476" name="RBBM_PERFCTR_UCHE_0_LO"/>
1249 <reg32 offset="0x0477" name="RBBM_PERFCTR_UCHE_0_HI"/>
1250 <reg32 offset="0x0478" name="RBBM_PERFCTR_UCHE_1_LO"/>
1251 <reg32 offset="0x0479" name="RBBM_PERFCTR_UCHE_1_HI"/>
1252 <reg32 offset="0x047a" name="RBBM_PERFCTR_UCHE_2_LO"/>
1253 <reg32 offset="0x047b" name="RBBM_PERFCTR_UCHE_2_HI"/>
1254 <reg32 offset="0x047c" name="RBBM_PERFCTR_UCHE_3_LO"/>
1255 <reg32 offset="0x047d" name="RBBM_PERFCTR_UCHE_3_HI"/>
1256 <reg32 offset="0x047e" name="RBBM_PERFCTR_UCHE_4_LO"/>
1257 <reg32 offset="0x047f" name="RBBM_PERFCTR_UCHE_4_HI"/>
1258 <reg32 offset="0x0480" name="RBBM_PERFCTR_UCHE_5_LO"/>
1259 <reg32 offset="0x0481" name="RBBM_PERFCTR_UCHE_5_HI"/>
1260 <reg32 offset="0x0482" name="RBBM_PERFCTR_UCHE_6_LO"/>
1261 <reg32 offset="0x0483" name="RBBM_PERFCTR_UCHE_6_HI"/>
1262 <reg32 offset="0x0484" name="RBBM_PERFCTR_UCHE_7_LO"/>
1263 <reg32 offset="0x0485" name="RBBM_PERFCTR_UCHE_7_HI"/>
1264 <reg32 offset="0x0486" name="RBBM_PERFCTR_UCHE_8_LO"/>
1265 <reg32 offset="0x0487" name="RBBM_PERFCTR_UCHE_8_HI"/>
1266 <reg32 offset="0x0488" name="RBBM_PERFCTR_UCHE_9_LO"/>
1267 <reg32 offset="0x0489" name="RBBM_PERFCTR_UCHE_9_HI"/>
1268 <reg32 offset="0x048a" name="RBBM_PERFCTR_UCHE_10_LO"/>
1269 <reg32 offset="0x048b" name="RBBM_PERFCTR_UCHE_10_HI"/>
1270 <reg32 offset="0x048c" name="RBBM_PERFCTR_UCHE_11_LO"/>
1271 <reg32 offset="0x048d" name="RBBM_PERFCTR_UCHE_11_HI"/>
1272 <reg32 offset="0x048e" name="RBBM_PERFCTR_TP_0_LO"/>
1273 <reg32 offset="0x048f" name="RBBM_PERFCTR_TP_0_HI"/>
1274 <reg32 offset="0x0490" name="RBBM_PERFCTR_TP_1_LO"/>
1275 <reg32 offset="0x0491" name="RBBM_PERFCTR_TP_1_HI"/>
1276 <reg32 offset="0x0492" name="RBBM_PERFCTR_TP_2_LO"/>
1277 <reg32 offset="0x0493" name="RBBM_PERFCTR_TP_2_HI"/>
1278 <reg32 offset="0x0494" name="RBBM_PERFCTR_TP_3_LO"/>
1279 <reg32 offset="0x0495" name="RBBM_PERFCTR_TP_3_HI"/>
1280 <reg32 offset="0x0496" name="RBBM_PERFCTR_TP_4_LO"/>
1281 <reg32 offset="0x0497" name="RBBM_PERFCTR_TP_4_HI"/>
1282 <reg32 offset="0x0498" name="RBBM_PERFCTR_TP_5_LO"/>
1283 <reg32 offset="0x0499" name="RBBM_PERFCTR_TP_5_HI"/>
1284 <reg32 offset="0x049a" name="RBBM_PERFCTR_TP_6_LO"/>
1285 <reg32 offset="0x049b" name="RBBM_PERFCTR_TP_6_HI"/>
1286 <reg32 offset="0x049c" name="RBBM_PERFCTR_TP_7_LO"/>
1287 <reg32 offset="0x049d" name="RBBM_PERFCTR_TP_7_HI"/>
1288 <reg32 offset="0x049e" name="RBBM_PERFCTR_TP_8_LO"/>
1289 <reg32 offset="0x049f" name="RBBM_PERFCTR_TP_8_HI"/>
1290 <reg32 offset="0x04a0" name="RBBM_PERFCTR_TP_9_LO"/>
1291 <reg32 offset="0x04a1" name="RBBM_PERFCTR_TP_9_HI"/>
1292 <reg32 offset="0x04a2" name="RBBM_PERFCTR_TP_10_LO"/>
1293 <reg32 offset="0x04a3" name="RBBM_PERFCTR_TP_10_HI"/>
1294 <reg32 offset="0x04a4" name="RBBM_PERFCTR_TP_11_LO"/>
1295 <reg32 offset="0x04a5" name="RBBM_PERFCTR_TP_11_HI"/>
1296 <reg32 offset="0x04a6" name="RBBM_PERFCTR_SP_0_LO"/>
1297 <reg32 offset="0x04a7" name="RBBM_PERFCTR_SP_0_HI"/>
1298 <reg32 offset="0x04a8" name="RBBM_PERFCTR_SP_1_LO"/>
1299 <reg32 offset="0x04a9" name="RBBM_PERFCTR_SP_1_HI"/>
1300 <reg32 offset="0x04aa" name="RBBM_PERFCTR_SP_2_LO"/>
1301 <reg32 offset="0x04ab" name="RBBM_PERFCTR_SP_2_HI"/>
1302 <reg32 offset="0x04ac" name="RBBM_PERFCTR_SP_3_LO"/>
1303 <reg32 offset="0x04ad" name="RBBM_PERFCTR_SP_3_HI"/>
1304 <reg32 offset="0x04ae" name="RBBM_PERFCTR_SP_4_LO"/>
1305 <reg32 offset="0x04af" name="RBBM_PERFCTR_SP_4_HI"/>
1306 <reg32 offset="0x04b0" name="RBBM_PERFCTR_SP_5_LO"/>
1307 <reg32 offset="0x04b1" name="RBBM_PERFCTR_SP_5_HI"/>
1308 <reg32 offset="0x04b2" name="RBBM_PERFCTR_SP_6_LO"/>
1309 <reg32 offset="0x04b3" name="RBBM_PERFCTR_SP_6_HI"/>
1310 <reg32 offset="0x04b4" name="RBBM_PERFCTR_SP_7_LO"/>
1311 <reg32 offset="0x04b5" name="RBBM_PERFCTR_SP_7_HI"/>
1312 <reg32 offset="0x04b6" name="RBBM_PERFCTR_SP_8_LO"/>
1313 <reg32 offset="0x04b7" name="RBBM_PERFCTR_SP_8_HI"/>
1314 <reg32 offset="0x04b8" name="RBBM_PERFCTR_SP_9_LO"/>
1315 <reg32 offset="0x04b9" name="RBBM_PERFCTR_SP_9_HI"/>
1316 <reg32 offset="0x04ba" name="RBBM_PERFCTR_SP_10_LO"/>
1317 <reg32 offset="0x04bb" name="RBBM_PERFCTR_SP_10_HI"/>
1318 <reg32 offset="0x04bc" name="RBBM_PERFCTR_SP_11_LO"/>
1319 <reg32 offset="0x04bd" name="RBBM_PERFCTR_SP_11_HI"/>
1320 <reg32 offset="0x04be" name="RBBM_PERFCTR_SP_12_LO"/>
1321 <reg32 offset="0x04bf" name="RBBM_PERFCTR_SP_12_HI"/>
1322 <reg32 offset="0x04c0" name="RBBM_PERFCTR_SP_13_LO"/>
1323 <reg32 offset="0x04c1" name="RBBM_PERFCTR_SP_13_HI"/>
1324 <reg32 offset="0x04c2" name="RBBM_PERFCTR_SP_14_LO"/>
1325 <reg32 offset="0x04c3" name="RBBM_PERFCTR_SP_14_HI"/>
1326 <reg32 offset="0x04c4" name="RBBM_PERFCTR_SP_15_LO"/>
1327 <reg32 offset="0x04c5" name="RBBM_PERFCTR_SP_15_HI"/>
1328 <reg32 offset="0x04c6" name="RBBM_PERFCTR_SP_16_LO"/>
1329 <reg32 offset="0x04c7" name="RBBM_PERFCTR_SP_16_HI"/>
1330 <reg32 offset="0x04c8" name="RBBM_PERFCTR_SP_17_LO"/>
1331 <reg32 offset="0x04c9" name="RBBM_PERFCTR_SP_17_HI"/>
1332 <reg32 offset="0x04ca" name="RBBM_PERFCTR_SP_18_LO"/>
1333 <reg32 offset="0x04cb" name="RBBM_PERFCTR_SP_18_HI"/>
1334 <reg32 offset="0x04cc" name="RBBM_PERFCTR_SP_19_LO"/>
1335 <reg32 offset="0x04cd" name="RBBM_PERFCTR_SP_19_HI"/>
1336 <reg32 offset="0x04ce" name="RBBM_PERFCTR_SP_20_LO"/>
1337 <reg32 offset="0x04cf" name="RBBM_PERFCTR_SP_20_HI"/>
1338 <reg32 offset="0x04d0" name="RBBM_PERFCTR_SP_21_LO"/>
1339 <reg32 offset="0x04d1" name="RBBM_PERFCTR_SP_21_HI"/>
1340 <reg32 offset="0x04d2" name="RBBM_PERFCTR_SP_22_LO"/>
1341 <reg32 offset="0x04d3" name="RBBM_PERFCTR_SP_22_HI"/>
1342 <reg32 offset="0x04d4" name="RBBM_PERFCTR_SP_23_LO"/>
1343 <reg32 offset="0x04d5" name="RBBM_PERFCTR_SP_23_HI"/>
1344 <reg32 offset="0x04d6" name="RBBM_PERFCTR_RB_0_LO"/>
1345 <reg32 offset="0x04d7" name="RBBM_PERFCTR_RB_0_HI"/>
1346 <reg32 offset="0x04d8" name="RBBM_PERFCTR_RB_1_LO"/>
1347 <reg32 offset="0x04d9" name="RBBM_PERFCTR_RB_1_HI"/>
1348 <reg32 offset="0x04da" name="RBBM_PERFCTR_RB_2_LO"/>
1349 <reg32 offset="0x04db" name="RBBM_PERFCTR_RB_2_HI"/>
1350 <reg32 offset="0x04dc" name="RBBM_PERFCTR_RB_3_LO"/>
1351 <reg32 offset="0x04dd" name="RBBM_PERFCTR_RB_3_HI"/>
1352 <reg32 offset="0x04de" name="RBBM_PERFCTR_RB_4_LO"/>
1353 <reg32 offset="0x04df" name="RBBM_PERFCTR_RB_4_HI"/>
1354 <reg32 offset="0x04e0" name="RBBM_PERFCTR_RB_5_LO"/>
1355 <reg32 offset="0x04e1" name="RBBM_PERFCTR_RB_5_HI"/>
1356 <reg32 offset="0x04e2" name="RBBM_PERFCTR_RB_6_LO"/>
1357 <reg32 offset="0x04e3" name="RBBM_PERFCTR_RB_6_HI"/>
1358 <reg32 offset="0x04e4" name="RBBM_PERFCTR_RB_7_LO"/>
1359 <reg32 offset="0x04e5" name="RBBM_PERFCTR_RB_7_HI"/>
1360 <reg32 offset="0x04e6" name="RBBM_PERFCTR_VSC_0_LO"/>
1361 <reg32 offset="0x04e7" name="RBBM_PERFCTR_VSC_0_HI"/>
1362 <reg32 offset="0x04e8" name="RBBM_PERFCTR_VSC_1_LO"/>
1363 <reg32 offset="0x04e9" name="RBBM_PERFCTR_VSC_1_HI"/>
1364 <reg32 offset="0x04ea" name="RBBM_PERFCTR_LRZ_0_LO"/>
1365 <reg32 offset="0x04eb" name="RBBM_PERFCTR_LRZ_0_HI"/>
1366 <reg32 offset="0x04ec" name="RBBM_PERFCTR_LRZ_1_LO"/>
1367 <reg32 offset="0x04ed" name="RBBM_PERFCTR_LRZ_1_HI"/>
1368 <reg32 offset="0x04ee" name="RBBM_PERFCTR_LRZ_2_LO"/>
1369 <reg32 offset="0x04ef" name="RBBM_PERFCTR_LRZ_2_HI"/>
1370 <reg32 offset="0x04f0" name="RBBM_PERFCTR_LRZ_3_LO"/>
1371 <reg32 offset="0x04f1" name="RBBM_PERFCTR_LRZ_3_HI"/>
1372 <reg32 offset="0x04f2" name="RBBM_PERFCTR_CMP_0_LO"/>
1373 <reg32 offset="0x04f3" name="RBBM_PERFCTR_CMP_0_HI"/>
1374 <reg32 offset="0x04f4" name="RBBM_PERFCTR_CMP_1_LO"/>
1375 <reg32 offset="0x04f5" name="RBBM_PERFCTR_CMP_1_HI"/>
1376 <reg32 offset="0x04f6" name="RBBM_PERFCTR_CMP_2_LO"/>
1377 <reg32 offset="0x04f7" name="RBBM_PERFCTR_CMP_2_HI"/>
1378 <reg32 offset="0x04f8" name="RBBM_PERFCTR_CMP_3_LO"/>
1379 <reg32 offset="0x04f9" name="RBBM_PERFCTR_CMP_3_HI"/>
1380 <reg32 offset="0x0500" name="RBBM_PERFCTR_CNTL"/>
1381 <reg32 offset="0x0501" name="RBBM_PERFCTR_LOAD_CMD0"/>
1382 <reg32 offset="0x0502" name="RBBM_PERFCTR_LOAD_CMD1"/>
1383 <reg32 offset="0x0503" name="RBBM_PERFCTR_LOAD_CMD2"/>
1384 <reg32 offset="0x0504" name="RBBM_PERFCTR_LOAD_CMD3"/>
1385 <reg32 offset="0x0505" name="RBBM_PERFCTR_LOAD_VALUE_LO"/>
1386 <reg32 offset="0x0506" name="RBBM_PERFCTR_LOAD_VALUE_HI"/>
1387 <reg32 offset="0x0507" name="RBBM_PERFCTR_RBBM_SEL_0"/>
1388 <reg32 offset="0x0508" name="RBBM_PERFCTR_RBBM_SEL_1"/>
1389 <reg32 offset="0x0509" name="RBBM_PERFCTR_RBBM_SEL_2"/>
1390 <reg32 offset="0x050A" name="RBBM_PERFCTR_RBBM_SEL_3"/>
1391 <reg32 offset="0x050B" name="RBBM_PERFCTR_GPU_BUSY_MASKED"/>
1392 <reg32 offset="0x0533" name="RBBM_ISDB_CNT"/>
1393
1394 <!---
1395 This block of registers aren't tied to perf counters. They
1396 count various geometry stats, for example number of
1397 vertices in, number of primnitives assembled etc.
1398 -->
1399
1400 <reg32 offset="0x0540" name="RBBM_PRIMCTR_0_LO"/> <!-- vs vertices in -->
1401 <reg32 offset="0x0541" name="RBBM_PRIMCTR_0_HI"/>
1402 <reg32 offset="0x0542" name="RBBM_PRIMCTR_1_LO"/> <!-- vs primitives out -->
1403 <reg32 offset="0x0543" name="RBBM_PRIMCTR_1_HI"/>
1404 <reg32 offset="0x0544" name="RBBM_PRIMCTR_2_LO"/> <!-- hs vertices in -->
1405 <reg32 offset="0x0545" name="RBBM_PRIMCTR_2_HI"/>
1406 <reg32 offset="0x0546" name="RBBM_PRIMCTR_3_LO"/> <!-- hs patches out -->
1407 <reg32 offset="0x0547" name="RBBM_PRIMCTR_3_HI"/>
1408 <reg32 offset="0x0548" name="RBBM_PRIMCTR_4_LO"/> <!-- dss vertices in -->
1409 <reg32 offset="0x0549" name="RBBM_PRIMCTR_4_HI"/>
1410 <reg32 offset="0x054a" name="RBBM_PRIMCTR_5_LO"/> <!-- ds primitives out -->
1411 <reg32 offset="0x054b" name="RBBM_PRIMCTR_5_HI"/>
1412 <reg32 offset="0x054c" name="RBBM_PRIMCTR_6_LO"/> <!-- gs primitives in -->
1413 <reg32 offset="0x054d" name="RBBM_PRIMCTR_6_HI"/>
1414 <reg32 offset="0x054e" name="RBBM_PRIMCTR_7_LO"/> <!-- gs primitives out -->
1415 <reg32 offset="0x054f" name="RBBM_PRIMCTR_7_HI"/>
1416 <reg32 offset="0x0550" name="RBBM_PRIMCTR_8_LO"/> <!-- gs primitives out -->
1417 <reg32 offset="0x0551" name="RBBM_PRIMCTR_8_HI"/>
1418 <reg32 offset="0x0552" name="RBBM_PRIMCTR_9_LO"/> <!-- raster primitives in -->
1419 <reg32 offset="0x0553" name="RBBM_PRIMCTR_9_HI"/>
1420 <reg32 offset="0x0554" name="RBBM_PRIMCTR_10_LO"/>
1421 <reg32 offset="0x0555" name="RBBM_PRIMCTR_10_HI"/>
1422
1423 <reg32 offset="0xF400" name="RBBM_SECVID_TRUST_CNTL"/>
1424 <reg32 offset="0xF800" name="RBBM_SECVID_TSB_TRUSTED_BASE_LO"/>
1425 <reg32 offset="0xF801" name="RBBM_SECVID_TSB_TRUSTED_BASE_HI"/>
1426 <reg32 offset="0xF802" name="RBBM_SECVID_TSB_TRUSTED_SIZE"/>
1427 <reg32 offset="0xF803" name="RBBM_SECVID_TSB_CNTL"/>
1428 <reg32 offset="0xF810" name="RBBM_SECVID_TSB_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1429 <reg32 offset="0x00010" name="RBBM_VBIF_CLIENT_QOS_CNTL"/>
1430 <reg32 offset="0x00011" name="RBBM_GBIF_CLIENT_QOS_CNTL"/>
1431 <reg32 offset="0x0001c" name="RBBM_WAIT_FOR_GPU_IDLE_CMD">
1432 <bitfield pos="0" name="WAIT_GPU_IDLE" type="boolean"/>
1433 </reg32>
1434 <reg32 offset="0x0001f" name="RBBM_INTERFACE_HANG_INT_CNTL"/>
1435 <reg32 offset="0x00037" name="RBBM_INT_CLEAR_CMD" type="A6XX_RBBM_INT_0_MASK"/>
1436 <reg32 offset="0x00038" name="RBBM_INT_0_MASK"/>
1437 <reg32 offset="0x00042" name="RBBM_SP_HYST_CNT"/>
1438 <reg32 offset="0x00043" name="RBBM_SW_RESET_CMD"/>
1439 <reg32 offset="0x00044" name="RBBM_RAC_THRESHOLD_CNT"/>
1440 <reg32 offset="0x00045" name="RBBM_BLOCK_SW_RESET_CMD"/>
1441 <reg32 offset="0x00046" name="RBBM_BLOCK_SW_RESET_CMD2"/>
1442 <reg32 offset="0x000ae" name="RBBM_CLOCK_CNTL"/>
1443 <reg32 offset="0x000b0" name="RBBM_CLOCK_CNTL_SP0"/>
1444 <reg32 offset="0x000b1" name="RBBM_CLOCK_CNTL_SP1"/>
1445 <reg32 offset="0x000b2" name="RBBM_CLOCK_CNTL_SP2"/>
1446 <reg32 offset="0x000b3" name="RBBM_CLOCK_CNTL_SP3"/>
1447 <reg32 offset="0x000b4" name="RBBM_CLOCK_CNTL2_SP0"/>
1448 <reg32 offset="0x000b5" name="RBBM_CLOCK_CNTL2_SP1"/>
1449 <reg32 offset="0x000b6" name="RBBM_CLOCK_CNTL2_SP2"/>
1450 <reg32 offset="0x000b7" name="RBBM_CLOCK_CNTL2_SP3"/>
1451 <reg32 offset="0x000b8" name="RBBM_CLOCK_DELAY_SP0"/>
1452 <reg32 offset="0x000b9" name="RBBM_CLOCK_DELAY_SP1"/>
1453 <reg32 offset="0x000ba" name="RBBM_CLOCK_DELAY_SP2"/>
1454 <reg32 offset="0x000bb" name="RBBM_CLOCK_DELAY_SP3"/>
1455 <reg32 offset="0x000bc" name="RBBM_CLOCK_HYST_SP0"/>
1456 <reg32 offset="0x000bd" name="RBBM_CLOCK_HYST_SP1"/>
1457 <reg32 offset="0x000be" name="RBBM_CLOCK_HYST_SP2"/>
1458 <reg32 offset="0x000bf" name="RBBM_CLOCK_HYST_SP3"/>
1459 <reg32 offset="0x000c0" name="RBBM_CLOCK_CNTL_TP0"/>
1460 <reg32 offset="0x000c1" name="RBBM_CLOCK_CNTL_TP1"/>
1461 <reg32 offset="0x000c2" name="RBBM_CLOCK_CNTL_TP2"/>
1462 <reg32 offset="0x000c3" name="RBBM_CLOCK_CNTL_TP3"/>
1463 <reg32 offset="0x000c4" name="RBBM_CLOCK_CNTL2_TP0"/>
1464 <reg32 offset="0x000c5" name="RBBM_CLOCK_CNTL2_TP1"/>
1465 <reg32 offset="0x000c6" name="RBBM_CLOCK_CNTL2_TP2"/>
1466 <reg32 offset="0x000c7" name="RBBM_CLOCK_CNTL2_TP3"/>
1467 <reg32 offset="0x000c8" name="RBBM_CLOCK_CNTL3_TP0"/>
1468 <reg32 offset="0x000c9" name="RBBM_CLOCK_CNTL3_TP1"/>
1469 <reg32 offset="0x000ca" name="RBBM_CLOCK_CNTL3_TP2"/>
1470 <reg32 offset="0x000cb" name="RBBM_CLOCK_CNTL3_TP3"/>
1471 <reg32 offset="0x000cc" name="RBBM_CLOCK_CNTL4_TP0"/>
1472 <reg32 offset="0x000cd" name="RBBM_CLOCK_CNTL4_TP1"/>
1473 <reg32 offset="0x000ce" name="RBBM_CLOCK_CNTL4_TP2"/>
1474 <reg32 offset="0x000cf" name="RBBM_CLOCK_CNTL4_TP3"/>
1475 <reg32 offset="0x000d0" name="RBBM_CLOCK_DELAY_TP0"/>
1476 <reg32 offset="0x000d1" name="RBBM_CLOCK_DELAY_TP1"/>
1477 <reg32 offset="0x000d2" name="RBBM_CLOCK_DELAY_TP2"/>
1478 <reg32 offset="0x000d3" name="RBBM_CLOCK_DELAY_TP3"/>
1479 <reg32 offset="0x000d4" name="RBBM_CLOCK_DELAY2_TP0"/>
1480 <reg32 offset="0x000d5" name="RBBM_CLOCK_DELAY2_TP1"/>
1481 <reg32 offset="0x000d6" name="RBBM_CLOCK_DELAY2_TP2"/>
1482 <reg32 offset="0x000d7" name="RBBM_CLOCK_DELAY2_TP3"/>
1483 <reg32 offset="0x000d8" name="RBBM_CLOCK_DELAY3_TP0"/>
1484 <reg32 offset="0x000d9" name="RBBM_CLOCK_DELAY3_TP1"/>
1485 <reg32 offset="0x000da" name="RBBM_CLOCK_DELAY3_TP2"/>
1486 <reg32 offset="0x000db" name="RBBM_CLOCK_DELAY3_TP3"/>
1487 <reg32 offset="0x000dc" name="RBBM_CLOCK_DELAY4_TP0"/>
1488 <reg32 offset="0x000dd" name="RBBM_CLOCK_DELAY4_TP1"/>
1489 <reg32 offset="0x000de" name="RBBM_CLOCK_DELAY4_TP2"/>
1490 <reg32 offset="0x000df" name="RBBM_CLOCK_DELAY4_TP3"/>
1491 <reg32 offset="0x000e0" name="RBBM_CLOCK_HYST_TP0"/>
1492 <reg32 offset="0x000e1" name="RBBM_CLOCK_HYST_TP1"/>
1493 <reg32 offset="0x000e2" name="RBBM_CLOCK_HYST_TP2"/>
1494 <reg32 offset="0x000e3" name="RBBM_CLOCK_HYST_TP3"/>
1495 <reg32 offset="0x000e4" name="RBBM_CLOCK_HYST2_TP0"/>
1496 <reg32 offset="0x000e5" name="RBBM_CLOCK_HYST2_TP1"/>
1497 <reg32 offset="0x000e6" name="RBBM_CLOCK_HYST2_TP2"/>
1498 <reg32 offset="0x000e7" name="RBBM_CLOCK_HYST2_TP3"/>
1499 <reg32 offset="0x000e8" name="RBBM_CLOCK_HYST3_TP0"/>
1500 <reg32 offset="0x000e9" name="RBBM_CLOCK_HYST3_TP1"/>
1501 <reg32 offset="0x000ea" name="RBBM_CLOCK_HYST3_TP2"/>
1502 <reg32 offset="0x000eb" name="RBBM_CLOCK_HYST3_TP3"/>
1503 <reg32 offset="0x000ec" name="RBBM_CLOCK_HYST4_TP0"/>
1504 <reg32 offset="0x000ed" name="RBBM_CLOCK_HYST4_TP1"/>
1505 <reg32 offset="0x000ee" name="RBBM_CLOCK_HYST4_TP2"/>
1506 <reg32 offset="0x000ef" name="RBBM_CLOCK_HYST4_TP3"/>
1507 <reg32 offset="0x000f0" name="RBBM_CLOCK_CNTL_RB0"/>
1508 <reg32 offset="0x000f1" name="RBBM_CLOCK_CNTL_RB1"/>
1509 <reg32 offset="0x000f2" name="RBBM_CLOCK_CNTL_RB2"/>
1510 <reg32 offset="0x000f3" name="RBBM_CLOCK_CNTL_RB3"/>
1511 <reg32 offset="0x000f4" name="RBBM_CLOCK_CNTL2_RB0"/>
1512 <reg32 offset="0x000f5" name="RBBM_CLOCK_CNTL2_RB1"/>
1513 <reg32 offset="0x000f6" name="RBBM_CLOCK_CNTL2_RB2"/>
1514 <reg32 offset="0x000f7" name="RBBM_CLOCK_CNTL2_RB3"/>
1515 <reg32 offset="0x000f8" name="RBBM_CLOCK_CNTL_CCU0"/>
1516 <reg32 offset="0x000f9" name="RBBM_CLOCK_CNTL_CCU1"/>
1517 <reg32 offset="0x000fa" name="RBBM_CLOCK_CNTL_CCU2"/>
1518 <reg32 offset="0x000fb" name="RBBM_CLOCK_CNTL_CCU3"/>
1519 <reg32 offset="0x00100" name="RBBM_CLOCK_HYST_RB_CCU0"/>
1520 <reg32 offset="0x00101" name="RBBM_CLOCK_HYST_RB_CCU1"/>
1521 <reg32 offset="0x00102" name="RBBM_CLOCK_HYST_RB_CCU2"/>
1522 <reg32 offset="0x00103" name="RBBM_CLOCK_HYST_RB_CCU3"/>
1523 <reg32 offset="0x00104" name="RBBM_CLOCK_CNTL_RAC"/>
1524 <reg32 offset="0x00105" name="RBBM_CLOCK_CNTL2_RAC"/>
1525 <reg32 offset="0x00106" name="RBBM_CLOCK_DELAY_RAC"/>
1526 <reg32 offset="0x00107" name="RBBM_CLOCK_HYST_RAC"/>
1527 <reg32 offset="0x00108" name="RBBM_CLOCK_CNTL_TSE_RAS_RBBM"/>
1528 <reg32 offset="0x00109" name="RBBM_CLOCK_DELAY_TSE_RAS_RBBM"/>
1529 <reg32 offset="0x0010a" name="RBBM_CLOCK_HYST_TSE_RAS_RBBM"/>
1530 <reg32 offset="0x0010b" name="RBBM_CLOCK_CNTL_UCHE"/>
1531 <reg32 offset="0x0010c" name="RBBM_CLOCK_CNTL2_UCHE"/>
1532 <reg32 offset="0x0010d" name="RBBM_CLOCK_CNTL3_UCHE"/>
1533 <reg32 offset="0x0010e" name="RBBM_CLOCK_CNTL4_UCHE"/>
1534 <reg32 offset="0x0010f" name="RBBM_CLOCK_DELAY_UCHE"/>
1535 <reg32 offset="0x00110" name="RBBM_CLOCK_HYST_UCHE"/>
1536 <reg32 offset="0x00111" name="RBBM_CLOCK_MODE_VFD"/>
1537 <reg32 offset="0x00112" name="RBBM_CLOCK_DELAY_VFD"/>
1538 <reg32 offset="0x00113" name="RBBM_CLOCK_HYST_VFD"/>
1539 <reg32 offset="0x00114" name="RBBM_CLOCK_MODE_GPC"/>
1540 <reg32 offset="0x00115" name="RBBM_CLOCK_DELAY_GPC"/>
1541 <reg32 offset="0x00116" name="RBBM_CLOCK_HYST_GPC"/>
1542 <reg32 offset="0x00117" name="RBBM_CLOCK_DELAY_HLSQ_2"/>
1543 <reg32 offset="0x00118" name="RBBM_CLOCK_CNTL_GMU_GX"/>
1544 <reg32 offset="0x00119" name="RBBM_CLOCK_DELAY_GMU_GX"/>
1545 <reg32 offset="0x0011a" name="RBBM_CLOCK_HYST_GMU_GX"/>
1546 <reg32 offset="0x0011b" name="RBBM_CLOCK_MODE_HLSQ"/>
1547 <reg32 offset="0x0011c" name="RBBM_CLOCK_DELAY_HLSQ"/>
1548 <reg32 offset="0x0011d" name="RBBM_CLOCK_HYST_HLSQ"/>
1549 <reg32 offset="0x00120" name="RBBM_CLOCK_CNTL_TEX_FCHE"/>
1550 <reg32 offset="0x00121" name="RBBM_CLOCK_DELAY_TEX_FCHE"/>
1551 <reg32 offset="0x00122" name="RBBM_CLOCK_HYST_TEX_FCHE"/>
1552
1553 <reg32 offset="0x0600" name="DBGC_CFG_DBGBUS_SEL_A"/>
1554 <reg32 offset="0x0601" name="DBGC_CFG_DBGBUS_SEL_B"/>
1555 <reg32 offset="0x0602" name="DBGC_CFG_DBGBUS_SEL_C"/>
1556 <reg32 offset="0x0603" name="DBGC_CFG_DBGBUS_SEL_D">
1557 <bitfield high="7" low="0" name="PING_INDEX"/>
1558 <bitfield high="15" low="8" name="PING_BLK_SEL"/>
1559 </reg32>
1560 <reg32 offset="0x0604" name="DBGC_CFG_DBGBUS_CNTLT">
1561 <bitfield high="5" low="0" name="TRACEEN"/>
1562 <bitfield high="14" low="12" name="GRANU"/>
1563 <bitfield high="31" low="28" name="SEGT"/>
1564 </reg32>
1565 <reg32 offset="0x0605" name="DBGC_CFG_DBGBUS_CNTLM">
1566 <bitfield high="27" low="24" name="ENABLE"/>
1567 </reg32>
1568 <reg32 offset="0x0608" name="DBGC_CFG_DBGBUS_IVTL_0"/>
1569 <reg32 offset="0x0609" name="DBGC_CFG_DBGBUS_IVTL_1"/>
1570 <reg32 offset="0x060a" name="DBGC_CFG_DBGBUS_IVTL_2"/>
1571 <reg32 offset="0x060b" name="DBGC_CFG_DBGBUS_IVTL_3"/>
1572 <reg32 offset="0x060c" name="DBGC_CFG_DBGBUS_MASKL_0"/>
1573 <reg32 offset="0x060d" name="DBGC_CFG_DBGBUS_MASKL_1"/>
1574 <reg32 offset="0x060e" name="DBGC_CFG_DBGBUS_MASKL_2"/>
1575 <reg32 offset="0x060f" name="DBGC_CFG_DBGBUS_MASKL_3"/>
1576 <reg32 offset="0x0610" name="DBGC_CFG_DBGBUS_BYTEL_0">
1577 <bitfield high="3" low="0" name="BYTEL0"/>
1578 <bitfield high="7" low="4" name="BYTEL1"/>
1579 <bitfield high="11" low="8" name="BYTEL2"/>
1580 <bitfield high="15" low="12" name="BYTEL3"/>
1581 <bitfield high="19" low="16" name="BYTEL4"/>
1582 <bitfield high="23" low="20" name="BYTEL5"/>
1583 <bitfield high="27" low="24" name="BYTEL6"/>
1584 <bitfield high="31" low="28" name="BYTEL7"/>
1585 </reg32>
1586 <reg32 offset="0x0611" name="DBGC_CFG_DBGBUS_BYTEL_1">
1587 <bitfield high="3" low="0" name="BYTEL8"/>
1588 <bitfield high="7" low="4" name="BYTEL9"/>
1589 <bitfield high="11" low="8" name="BYTEL10"/>
1590 <bitfield high="15" low="12" name="BYTEL11"/>
1591 <bitfield high="19" low="16" name="BYTEL12"/>
1592 <bitfield high="23" low="20" name="BYTEL13"/>
1593 <bitfield high="27" low="24" name="BYTEL14"/>
1594 <bitfield high="31" low="28" name="BYTEL15"/>
1595 </reg32>
1596 <reg32 offset="0x062f" name="DBGC_CFG_DBGBUS_TRACE_BUF1"/>
1597 <reg32 offset="0x0630" name="DBGC_CFG_DBGBUS_TRACE_BUF2"/>
1598 <reg32 offset="0x0CD8" name="VSC_PERFCTR_VSC_SEL_0"/>
1599 <reg32 offset="0x0CD9" name="VSC_PERFCTR_VSC_SEL_1"/>
1600 <reg32 offset="0xBE05" name="HLSQ_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1601 <reg32 offset="0xBE10" name="HLSQ_PERFCTR_HLSQ_SEL_0"/>
1602 <reg32 offset="0xBE11" name="HLSQ_PERFCTR_HLSQ_SEL_1"/>
1603 <reg32 offset="0xBE12" name="HLSQ_PERFCTR_HLSQ_SEL_2"/>
1604 <reg32 offset="0xBE13" name="HLSQ_PERFCTR_HLSQ_SEL_3"/>
1605 <reg32 offset="0xBE14" name="HLSQ_PERFCTR_HLSQ_SEL_4"/>
1606 <reg32 offset="0xBE15" name="HLSQ_PERFCTR_HLSQ_SEL_5"/>
1607 <reg32 offset="0xC800" name="HLSQ_DBG_AHB_READ_APERTURE"/>
1608 <reg32 offset="0xD000" name="HLSQ_DBG_READ_SEL"/>
1609 <reg32 offset="0xA601" name="VFD_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1610 <reg32 offset="0xA610" name="VFD_PERFCTR_VFD_SEL_0"/>
1611 <reg32 offset="0xA611" name="VFD_PERFCTR_VFD_SEL_1"/>
1612 <reg32 offset="0xA612" name="VFD_PERFCTR_VFD_SEL_2"/>
1613 <reg32 offset="0xA613" name="VFD_PERFCTR_VFD_SEL_3"/>
1614 <reg32 offset="0xA614" name="VFD_PERFCTR_VFD_SEL_4"/>
1615 <reg32 offset="0xA615" name="VFD_PERFCTR_VFD_SEL_5"/>
1616 <reg32 offset="0xA616" name="VFD_PERFCTR_VFD_SEL_6"/>
1617 <reg32 offset="0xA617" name="VFD_PERFCTR_VFD_SEL_7"/>
1618 <reg32 offset="0x0E00" name="UCHE_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1619 <reg32 offset="0x0E01" name="UCHE_MODE_CNTL"/>
1620 <reg32 offset="0x0E05" name="UCHE_WRITE_RANGE_MAX_LO"/>
1621 <reg32 offset="0x0E06" name="UCHE_WRITE_RANGE_MAX_HI"/>
1622 <reg32 offset="0x0E07" name="UCHE_WRITE_THRU_BASE_LO"/>
1623 <reg32 offset="0x0E08" name="UCHE_WRITE_THRU_BASE_HI"/>
1624 <reg32 offset="0x0E09" name="UCHE_TRAP_BASE_LO"/>
1625 <reg32 offset="0x0E0A" name="UCHE_TRAP_BASE_HI"/>
1626 <reg32 offset="0x0E0B" name="UCHE_GMEM_RANGE_MIN_LO"/>
1627 <reg32 offset="0x0E0C" name="UCHE_GMEM_RANGE_MIN_HI"/>
1628 <reg32 offset="0x0E0D" name="UCHE_GMEM_RANGE_MAX_LO"/>
1629 <reg32 offset="0x0E0E" name="UCHE_GMEM_RANGE_MAX_HI"/>
1630 <reg32 offset="0x0E17" name="UCHE_CACHE_WAYS"/>
1631 <reg32 offset="0x0E18" name="UCHE_FILTER_CNTL"/>
1632 <reg32 offset="0x0E19" name="UCHE_CLIENT_PF">
1633 <bitfield high="7" low="0" name="PERFSEL"/>
1634 </reg32>
1635 <reg32 offset="0x0E1C" name="UCHE_PERFCTR_UCHE_SEL_0"/>
1636 <reg32 offset="0x0E1D" name="UCHE_PERFCTR_UCHE_SEL_1"/>
1637 <reg32 offset="0x0E1E" name="UCHE_PERFCTR_UCHE_SEL_2"/>
1638 <reg32 offset="0x0E1F" name="UCHE_PERFCTR_UCHE_SEL_3"/>
1639 <reg32 offset="0x0E20" name="UCHE_PERFCTR_UCHE_SEL_4"/>
1640 <reg32 offset="0x0E21" name="UCHE_PERFCTR_UCHE_SEL_5"/>
1641 <reg32 offset="0x0E22" name="UCHE_PERFCTR_UCHE_SEL_6"/>
1642 <reg32 offset="0x0E23" name="UCHE_PERFCTR_UCHE_SEL_7"/>
1643 <reg32 offset="0x0E24" name="UCHE_PERFCTR_UCHE_SEL_8"/>
1644 <reg32 offset="0x0E25" name="UCHE_PERFCTR_UCHE_SEL_9"/>
1645 <reg32 offset="0x0E26" name="UCHE_PERFCTR_UCHE_SEL_10"/>
1646 <reg32 offset="0x0E27" name="UCHE_PERFCTR_UCHE_SEL_11"/>
1647 <reg32 offset="0xAE01" name="SP_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1648 <reg32 offset="0xAE02" name="SP_NC_MODE_CNTL"/>
1649 <reg32 offset="0xAE10" name="SP_PERFCTR_SP_SEL_0"/>
1650 <reg32 offset="0xAE11" name="SP_PERFCTR_SP_SEL_1"/>
1651 <reg32 offset="0xAE12" name="SP_PERFCTR_SP_SEL_2"/>
1652 <reg32 offset="0xAE13" name="SP_PERFCTR_SP_SEL_3"/>
1653 <reg32 offset="0xAE14" name="SP_PERFCTR_SP_SEL_4"/>
1654 <reg32 offset="0xAE15" name="SP_PERFCTR_SP_SEL_5"/>
1655 <reg32 offset="0xAE16" name="SP_PERFCTR_SP_SEL_6"/>
1656 <reg32 offset="0xAE17" name="SP_PERFCTR_SP_SEL_7"/>
1657 <reg32 offset="0xAE18" name="SP_PERFCTR_SP_SEL_8"/>
1658 <reg32 offset="0xAE19" name="SP_PERFCTR_SP_SEL_9"/>
1659 <reg32 offset="0xAE1A" name="SP_PERFCTR_SP_SEL_10"/>
1660 <reg32 offset="0xAE1B" name="SP_PERFCTR_SP_SEL_11"/>
1661 <reg32 offset="0xAE1C" name="SP_PERFCTR_SP_SEL_12"/>
1662 <reg32 offset="0xAE1D" name="SP_PERFCTR_SP_SEL_13"/>
1663 <reg32 offset="0xAE1E" name="SP_PERFCTR_SP_SEL_14"/>
1664 <reg32 offset="0xAE1F" name="SP_PERFCTR_SP_SEL_15"/>
1665 <reg32 offset="0xAE20" name="SP_PERFCTR_SP_SEL_16"/>
1666 <reg32 offset="0xAE21" name="SP_PERFCTR_SP_SEL_17"/>
1667 <reg32 offset="0xAE22" name="SP_PERFCTR_SP_SEL_18"/>
1668 <reg32 offset="0xAE23" name="SP_PERFCTR_SP_SEL_19"/>
1669 <reg32 offset="0xAE24" name="SP_PERFCTR_SP_SEL_20"/>
1670 <reg32 offset="0xAE25" name="SP_PERFCTR_SP_SEL_21"/>
1671 <reg32 offset="0xAE26" name="SP_PERFCTR_SP_SEL_22"/>
1672 <reg32 offset="0xAE27" name="SP_PERFCTR_SP_SEL_23"/>
1673 <reg32 offset="0xB601" name="TPL1_ADDR_MODE_CNTL" type="a5xx_address_mode"/>
1674 <reg32 offset="0xB604" name="TPL1_NC_MODE_CNTL"/>
1675 <reg32 offset="0xB608" name="TPL1_BICUBIC_WEIGHTS_TABLE_0"/>
1676 <reg32 offset="0xB609" name="TPL1_BICUBIC_WEIGHTS_TABLE_1"/>
1677 <reg32 offset="0xB60A" name="TPL1_BICUBIC_WEIGHTS_TABLE_2"/>
1678 <reg32 offset="0xB60B" name="TPL1_BICUBIC_WEIGHTS_TABLE_3"/>
1679 <reg32 offset="0xB60C" name="TPL1_BICUBIC_WEIGHTS_TABLE_4"/>
1680 <reg32 offset="0xB610" name="TPL1_PERFCTR_TP_SEL_0"/>
1681 <reg32 offset="0xB611" name="TPL1_PERFCTR_TP_SEL_1"/>
1682 <reg32 offset="0xB612" name="TPL1_PERFCTR_TP_SEL_2"/>
1683 <reg32 offset="0xB613" name="TPL1_PERFCTR_TP_SEL_3"/>
1684 <reg32 offset="0xB614" name="TPL1_PERFCTR_TP_SEL_4"/>
1685 <reg32 offset="0xB615" name="TPL1_PERFCTR_TP_SEL_5"/>
1686 <reg32 offset="0xB616" name="TPL1_PERFCTR_TP_SEL_6"/>
1687 <reg32 offset="0xB617" name="TPL1_PERFCTR_TP_SEL_7"/>
1688 <reg32 offset="0xB618" name="TPL1_PERFCTR_TP_SEL_8"/>
1689 <reg32 offset="0xB619" name="TPL1_PERFCTR_TP_SEL_9"/>
1690 <reg32 offset="0xB61A" name="TPL1_PERFCTR_TP_SEL_10"/>
1691 <reg32 offset="0xB61B" name="TPL1_PERFCTR_TP_SEL_11"/>
1692 <reg32 offset="0x3000" name="VBIF_VERSION"/>
1693 <reg32 offset="0x3001" name="VBIF_CLKON">
1694 <bitfield pos="1" name="FORCE_ON_TESTBUS" type="boolean"/>
1695 </reg32>
1696 <reg32 offset="0x302A" name="VBIF_GATE_OFF_WRREQ_EN"/>
1697 <reg32 offset="0x3080" name="VBIF_XIN_HALT_CTRL0"/>
1698 <reg32 offset="0x3081" name="VBIF_XIN_HALT_CTRL1"/>
1699 <reg32 offset="0x3084" name="VBIF_TEST_BUS_OUT_CTRL"/>
1700 <reg32 offset="0x3085" name="VBIF_TEST_BUS1_CTRL0"/>
1701 <reg32 offset="0x3086" name="VBIF_TEST_BUS1_CTRL1">
1702 <bitfield low="0" high="3" name="DATA_SEL"/>
1703 </reg32>
1704 <reg32 offset="0x3087" name="VBIF_TEST_BUS2_CTRL0"/>
1705 <reg32 offset="0x3088" name="VBIF_TEST_BUS2_CTRL1">
1706 <bitfield low="0" high="8" name="DATA_SEL"/>
1707 </reg32>
1708 <reg32 offset="0x308c" name="VBIF_TEST_BUS_OUT"/>
1709 <reg32 offset="0x30d0" name="VBIF_PERF_CNT_SEL0"/>
1710 <reg32 offset="0x30d1" name="VBIF_PERF_CNT_SEL1"/>
1711 <reg32 offset="0x30d2" name="VBIF_PERF_CNT_SEL2"/>
1712 <reg32 offset="0x30d3" name="VBIF_PERF_CNT_SEL3"/>
1713 <reg32 offset="0x30d8" name="VBIF_PERF_CNT_LOW0"/>
1714 <reg32 offset="0x30d9" name="VBIF_PERF_CNT_LOW1"/>
1715 <reg32 offset="0x30da" name="VBIF_PERF_CNT_LOW2"/>
1716 <reg32 offset="0x30db" name="VBIF_PERF_CNT_LOW3"/>
1717 <reg32 offset="0x30e0" name="VBIF_PERF_CNT_HIGH0"/>
1718 <reg32 offset="0x30e1" name="VBIF_PERF_CNT_HIGH1"/>
1719 <reg32 offset="0x30e2" name="VBIF_PERF_CNT_HIGH2"/>
1720 <reg32 offset="0x30e3" name="VBIF_PERF_CNT_HIGH3"/>
1721 <reg32 offset="0x3100" name="VBIF_PERF_PWR_CNT_EN0"/>
1722 <reg32 offset="0x3101" name="VBIF_PERF_PWR_CNT_EN1"/>
1723 <reg32 offset="0x3102" name="VBIF_PERF_PWR_CNT_EN2"/>
1724 <reg32 offset="0x3110" name="VBIF_PERF_PWR_CNT_LOW0"/>
1725 <reg32 offset="0x3111" name="VBIF_PERF_PWR_CNT_LOW1"/>
1726 <reg32 offset="0x3112" name="VBIF_PERF_PWR_CNT_LOW2"/>
1727 <reg32 offset="0x3118" name="VBIF_PERF_PWR_CNT_HIGH0"/>
1728 <reg32 offset="0x3119" name="VBIF_PERF_PWR_CNT_HIGH1"/>
1729 <reg32 offset="0x311a" name="VBIF_PERF_PWR_CNT_HIGH2"/>
1730
1731 <reg32 offset="0x3c02" name="GBIF_SCACHE_CNTL1"/>
1732 <reg32 offset="0x3c03" name="GBIF_QSB_SIDE0"/>
1733 <reg32 offset="0x3c04" name="GBIF_QSB_SIDE1"/>
1734 <reg32 offset="0x3c05" name="GBIF_QSB_SIDE2"/>
1735 <reg32 offset="0x3c06" name="GBIF_QSB_SIDE3"/>
1736 <reg32 offset="0x3c45" name="GBIF_HALT"/>
1737 <reg32 offset="0x3c46" name="GBIF_HALT_ACK"/>
1738 <reg32 offset="0x3cc0" name="GBIF_PERF_PWR_CNT_EN"/>
1739 <reg32 offset="0x3cc2" name="GBIF_PERF_CNT_SEL"/>
1740 <reg32 offset="0x3cc3" name="GBIF_PERF_PWR_CNT_SEL"/>
1741 <reg32 offset="0x3cc4" name="GBIF_PERF_CNT_LOW0"/>
1742 <reg32 offset="0x3cc5" name="GBIF_PERF_CNT_LOW1"/>
1743 <reg32 offset="0x3cc6" name="GBIF_PERF_CNT_LOW2"/>
1744 <reg32 offset="0x3cc7" name="GBIF_PERF_CNT_LOW3"/>
1745 <reg32 offset="0x3cc8" name="GBIF_PERF_CNT_HIGH0"/>
1746 <reg32 offset="0x3cc9" name="GBIF_PERF_CNT_HIGH1"/>
1747 <reg32 offset="0x3cca" name="GBIF_PERF_CNT_HIGH2"/>
1748 <reg32 offset="0x3ccb" name="GBIF_PERF_CNT_HIGH3"/>
1749 <reg32 offset="0x3ccc" name="GBIF_PWR_CNT_LOW0"/>
1750 <reg32 offset="0x3ccd" name="GBIF_PWR_CNT_LOW1"/>
1751 <reg32 offset="0x3cce" name="GBIF_PWR_CNT_LOW2"/>
1752 <reg32 offset="0x3ccf" name="GBIF_PWR_CNT_HIGH0"/>
1753 <reg32 offset="0x3cd0" name="GBIF_PWR_CNT_HIGH1"/>
1754 <reg32 offset="0x3cd1" name="GBIF_PWR_CNT_HIGH2"/>
1755
1756 <!-- move/rename these.. -->
1757
1758 <reg32 offset="0xb4d1" name="SP_WINDOW_OFFSET" type="adreno_reg_xy"/>
1759 <reg32 offset="0xb307" name="SP_TP_WINDOW_OFFSET" type="adreno_reg_xy"/>
1760
1761 <reg32 offset="0x0c02" name="VSC_BIN_SIZE">
1762 <bitfield name="WIDTH" low="0" high="7" shr="5" type="uint"/>
1763 <bitfield name="HEIGHT" low="8" high="16" shr="4" type="uint"/>
1764 </reg32>
1765 <reg32 offset="0x0c03" name="VSC_DRAW_STRM_SIZE_ADDRESS_LO"/>
1766 <reg32 offset="0x0c04" name="VSC_DRAW_STRM_SIZE_ADDRESS_HI"/>
1767 <reg64 offset="0x0c03" name="VSC_DRAW_STRM_SIZE_ADDRESS" type="waddress"/>
1768 <reg32 offset="0x0c06" name="VSC_BIN_COUNT">
1769 <bitfield name="NX" low="1" high="10" type="uint"/>
1770 <bitfield name="NY" low="11" high="20" type="uint"/>
1771 </reg32>
1772 <array offset="0x0c10" name="VSC_PIPE_CONFIG" stride="1" length="32">
1773 <reg32 offset="0x0" name="REG">
1774 <doc>
1775 Configures the mapping between VSC_PIPE buffer and
1776 bin, X/Y specify the bin index in the horiz/vert
1777 direction (0,0 is upper left, 0,1 is leftmost bin
1778 on second row, and so on). W/H specify the number
1779 of bins assigned to this VSC_PIPE in the horiz/vert
1780 dimension.
1781 </doc>
1782 <bitfield name="X" low="0" high="9" type="uint"/>
1783 <bitfield name="Y" low="10" high="19" type="uint"/>
1784 <bitfield name="W" low="20" high="25" type="uint"/>
1785 <bitfield name="H" low="26" high="31" type="uint"/>
1786 </reg32>
1787 </array>
1788 <!--
1789 HW binning primitive & draw streams, which enable draws and primitives
1790 within a draw to be skipped in the main tile pass. See:
1791 https://github.com/freedreno/freedreno/wiki/Visibility-Stream-Format
1792
1793 Compared to a5xx and earlier, we just program the address of the first
1794 stream and hw adds (pipe_num * VSC_*_STRM_PITCH)
1795
1796 LIMIT is set to PITCH - 64, to make room for a bit of overflow
1797 -->
1798 <reg32 offset="0x0c30" name="VSC_PRIM_STRM_ADDRESS_LO"/>
1799 <reg32 offset="0x0c31" name="VSC_PRIM_STRM_ADDRESS_HI"/>
1800 <reg64 offset="0x0c30" name="VSC_PRIM_STRM_ADDRESS" type="waddress"/>
1801 <reg32 offset="0x0c32" name="VSC_PRIM_STRM_PITCH"/>
1802 <reg32 offset="0x0c33" name="VSC_PRIM_STRM_LIMIT"/>
1803 <reg32 offset="0x0c34" name="VSC_DRAW_STRM_ADDRESS_LO"/>
1804 <reg32 offset="0x0c35" name="VSC_DRAW_STRM_ADDRESS_HI"/>
1805 <reg64 offset="0x0c34" name="VSC_DRAW_STRM_ADDRESS" type="waddress"/>
1806 <reg32 offset="0x0c36" name="VSC_DRAW_STRM_PITCH"/>
1807 <reg32 offset="0x0c37" name="VSC_DRAW_STRM_LIMIT"/>
1808
1809 <array offset="0x0c38" name="VSC_STATE" stride="1" length="32">
1810 <doc>
1811 Seems to be a bitmap of which tiles mapped to the VSC
1812 pipe contain geometry.
1813
1814 I suppose we can connect a maximum of 32 tiles to a
1815 single VSC pipe.
1816 </doc>
1817 <reg32 offset="0x0" name="REG"/>
1818 </array>
1819
1820 <array offset="0x0c58" name="VSC_PRIM_STRM_SIZE" stride="1" length="32">
1821 <doc>
1822 Has the size of data written to corresponding VSC_PRIM_STRM
1823 buffer.
1824 </doc>
1825 <reg32 offset="0x0" name="REG"/>
1826 </array>
1827
1828 <array offset="0x0c78" name="VSC_DRAW_STRM_SIZE" stride="1" length="32">
1829 <doc>
1830 Has the size of data written to corresponding VSC pipe, ie.
1831 same thing that is written out to VSC_DRAW_STRM_SIZE_ADDRESS_LO/HI
1832 </doc>
1833 <reg32 offset="0x0" name="REG"/>
1834 </array>
1835
1836 <!-- always 0x03200000 ? -->
1837 <reg32 offset="0x0e12" name="UCHE_UNKNOWN_0E12"/>
1838
1839 <!-- adreno_reg_xy has 15 bits per coordinate, but a6xx registers only have 14 -->
1840 <bitset name="a6xx_reg_xy" inline="yes">
1841 <bitfield name="X" low="0" high="13" type="uint"/>
1842 <bitfield name="Y" low="16" high="29" type="uint"/>
1843 </bitset>
1844
1845 <reg32 offset="0x8000" name="GRAS_CL_CNTL">
1846 <bitfield name="CLIP_DISABLE" pos="0" type="boolean"/>
1847 <bitfield name="ZNEAR_CLIP_DISABLE" pos="1" type="boolean"/>
1848 <bitfield name="ZFAR_CLIP_DISABLE" pos="2" type="boolean"/>
1849 <!-- set with depthClampEnable, not clear what it does -->
1850 <bitfield name="UNK5" pos="5" type="boolean"/>
1851 <!-- controls near z clip behavior (set for vulkan) -->
1852 <bitfield name="ZERO_GB_SCALE_Z" pos="6" type="boolean"/>
1853 <!-- guess based on a3xx and meaning of bits 8 and 9
1854 if the guess is right then this is related to point sprite clipping -->
1855 <bitfield name="VP_CLIP_CODE_IGNORE" pos="7" type="boolean"/>
1856 <bitfield name="VP_XFORM_DISABLE" pos="8" type="boolean"/>
1857 <bitfield name="PERSP_DIVISION_DISABLE" pos="9" type="boolean"/>
1858 </reg32>
1859
1860 <bitset name="a6xx_gras_xs_cl_cntl" inline="yes">
1861 <bitfield name="CLIP_MASK" low="0" high="7"/>
1862 <bitfield name="CULL_MASK" low="8" high="15"/>
1863 </bitset>
1864 <reg32 offset="0x8001" name="GRAS_VS_CL_CNTL" type="a6xx_gras_xs_cl_cntl"/>
1865 <reg32 offset="0x8002" name="GRAS_DS_CL_CNTL" type="a6xx_gras_xs_cl_cntl"/>
1866 <reg32 offset="0x8003" name="GRAS_GS_CL_CNTL" type="a6xx_gras_xs_cl_cntl"/>
1867 <reg32 offset="0x8004" name="GRAS_MAX_LAYER_INDEX" low="0" high="10" type="uint"/>
1868
1869 <reg32 offset="0x8005" name="GRAS_CNTL">
1870 <!-- see also RB_RENDER_CONTROL0 -->
1871 <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
1872 <!-- b1 set for interpolateAtCentroid() -->
1873 <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>
1874 <!-- b2 set instead of b0 when running in per-sample mode -->
1875 <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>
1876 <!--
1877 b3 set for interpolateAt{Offset,Sample}() if not in per-sample
1878 mode, and frag_face
1879 -->
1880 <bitfield name="SIZE" pos="3" type="boolean"/>
1881 <bitfield name="UNK4" pos="4" type="boolean"/>
1882 <!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
1883 <bitfield name="SIZE_PERSAMP" pos="5" type="boolean"/>
1884 <bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
1885 </reg32>
1886 <reg32 offset="0x8006" name="GRAS_CL_GUARDBAND_CLIP_ADJ">
1887 <bitfield name="HORZ" low="0" high="8" type="uint"/>
1888 <bitfield name="VERT" low="10" high="18" type="uint"/>
1889 </reg32>
1890 <!-- 0x8006-0x800f invalid -->
1891 <array offset="0x8010" name="GRAS_CL_VPORT" stride="6" length="16">
1892 <reg32 offset="0" name="XOFFSET" type="float"/>
1893 <reg32 offset="1" name="XSCALE" type="float"/>
1894 <reg32 offset="2" name="YOFFSET" type="float"/>
1895 <reg32 offset="3" name="YSCALE" type="float"/>
1896 <reg32 offset="4" name="ZOFFSET" type="float"/>
1897 <reg32 offset="5" name="ZSCALE" type="float"/>
1898 </array>
1899 <array offset="0x8070" name="GRAS_CL_Z_CLAMP" stride="2" length="16">
1900 <reg32 offset="0" name="MIN" type="float"/>
1901 <reg32 offset="1" name="MAX" type="float"/>
1902 </array>
1903
1904 <reg32 offset="0x8090" name="GRAS_SU_CNTL">
1905 <bitfield name="CULL_FRONT" pos="0" type="boolean"/>
1906 <bitfield name="CULL_BACK" pos="1" type="boolean"/>
1907 <bitfield name="FRONT_CW" pos="2" type="boolean"/>
1908 <bitfield name="LINEHALFWIDTH" low="3" high="10" radix="2" type="fixed"/>
1909 <bitfield name="POLY_OFFSET" pos="11" type="boolean"/>
1910 <bitfield name="UNK12" pos="12"/>
1911 <bitfield name="MSAA_ENABLE" pos="13" type="boolean"/>
1912 <bitfield name="UNK15" low="15" high="22"/>
1913 </reg32>
1914 <reg32 offset="0x8091" name="GRAS_SU_POINT_MINMAX">
1915 <bitfield name="MIN" low="0" high="15" type="ufixed" radix="4"/>
1916 <bitfield name="MAX" low="16" high="31" type="ufixed" radix="4"/>
1917 </reg32>
1918 <reg32 offset="0x8092" name="GRAS_SU_POINT_SIZE" low="0" high="15" type="fixed" radix="4"/>
1919 <!-- 0x8093 invalid -->
1920 <reg32 offset="0x8094" name="GRAS_SU_DEPTH_PLANE_CNTL">
1921 <bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/>
1922 </reg32>
1923 <reg32 offset="0x8095" name="GRAS_SU_POLY_OFFSET_SCALE" type="float"/>
1924 <reg32 offset="0x8096" name="GRAS_SU_POLY_OFFSET_OFFSET" type="float"/>
1925 <reg32 offset="0x8097" name="GRAS_SU_POLY_OFFSET_OFFSET_CLAMP" type="float"/>
1926 <!-- duplicates RB_DEPTH_BUFFER_INFO: -->
1927 <reg32 offset="0x8098" name="GRAS_SU_DEPTH_BUFFER_INFO">
1928 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
1929 <bitfield name="UNK3" pos="3"/>
1930 </reg32>
1931
1932 <reg32 offset="0x8099" name="GRAS_UNKNOWN_8099" low="0" high="5"/>
1933 <reg32 offset="0x809a" name="GRAS_UNKNOWN_809A" low="0" high="1"/>
1934
1935 <bitset name="a6xx_gras_layer_cntl" inline="yes">
1936 <bitfield name="WRITES_LAYER" pos="0" type="boolean"/>
1937 <bitfield name="WRITES_VIEW" pos="1" type="boolean"/>
1938 </bitset>
1939 <reg32 offset="0x809b" name="GRAS_VS_LAYER_CNTL" type="a6xx_gras_layer_cntl"/>
1940 <reg32 offset="0x809c" name="GRAS_GS_LAYER_CNTL" type="a6xx_gras_layer_cntl"/>
1941 <reg32 offset="0x809d" name="GRAS_DS_LAYER_CNTL" type="a6xx_gras_layer_cntl"/>
1942 <!-- 0x809e/0x809f invalid -->
1943 <reg32 offset="0x80a0" name="GRAS_UNKNOWN_80A0" low="0" high="12"/>
1944 <reg32 offset="0x80a1" name="GRAS_BIN_CONTROL">
1945 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
1946 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
1947 <bitfield name="BINNING_PASS" pos="18" type="boolean"/>
1948 <bitfield name="UNK19" pos="19"/>
1949 <bitfield name="UNK20" pos="20"/>
1950 <bitfield name="USE_VIZ" pos="21" type="boolean"/>
1951 <bitfield name="UNK22" low="22" high="27"/>
1952 </reg32>
1953
1954 <reg32 offset="0x80a2" name="GRAS_RAS_MSAA_CNTL">
1955 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1956 <bitfield name="UNK2" pos="2"/>
1957 <bitfield name="UNK3" pos="3"/>
1958 </reg32>
1959 <reg32 offset="0x80a3" name="GRAS_DEST_MSAA_CNTL">
1960 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
1961 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
1962 </reg32>
1963
1964 <bitset name="a6xx_sample_config" inline="yes">
1965 <bitfield name="UNK0" pos="0"/>
1966 <bitfield name="LOCATION_ENABLE" pos="1" type="boolean"/>
1967 </bitset>
1968
1969 <bitset name="a6xx_sample_locations" inline="yes">
1970 <bitfield name="SAMPLE_0_X" low="0" high="3" radix="4" type="fixed"/>
1971 <bitfield name="SAMPLE_0_Y" low="4" high="7" radix="4" type="fixed"/>
1972 <bitfield name="SAMPLE_1_X" low="8" high="11" radix="4" type="fixed"/>
1973 <bitfield name="SAMPLE_1_Y" low="12" high="15" radix="4" type="fixed"/>
1974 <bitfield name="SAMPLE_2_X" low="16" high="19" radix="4" type="fixed"/>
1975 <bitfield name="SAMPLE_2_Y" low="20" high="23" radix="4" type="fixed"/>
1976 <bitfield name="SAMPLE_3_X" low="24" high="27" radix="4" type="fixed"/>
1977 <bitfield name="SAMPLE_3_Y" low="28" high="31" radix="4" type="fixed"/>
1978 </bitset>
1979
1980 <reg32 offset="0x80a4" name="GRAS_SAMPLE_CONFIG" type="a6xx_sample_config"/>
1981 <reg32 offset="0x80a5" name="GRAS_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
1982 <reg32 offset="0x80a6" name="GRAS_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
1983 <!-- 0x80a7-0x80ae invalid -->
1984 <reg32 offset="0x80af" name="GRAS_UNKNOWN_80AF" pos="0"/>
1985
1986 <bitset name="a6xx_scissor_xy" inline="yes">
1987 <bitfield name="X" low="0" high="15" type="uint"/>
1988 <bitfield name="Y" low="16" high="31" type="uint"/>
1989 </bitset>
1990 <array offset="0x80b0" name="GRAS_SC_SCREEN_SCISSOR" stride="2" length="16">
1991 <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/>
1992 <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/>
1993 </array>
1994 <array offset="0x80d0" name="GRAS_SC_VIEWPORT_SCISSOR" stride="2" length="16">
1995 <reg32 offset="0" name="TL" type="a6xx_scissor_xy"/>
1996 <reg32 offset="1" name="BR" type="a6xx_scissor_xy"/>
1997 </array>
1998
1999 <reg32 offset="0x80f0" name="GRAS_SC_WINDOW_SCISSOR_TL" type="a6xx_reg_xy"/>
2000 <reg32 offset="0x80f1" name="GRAS_SC_WINDOW_SCISSOR_BR" type="a6xx_reg_xy"/>
2001 <!-- 0x80f2-0x80ff invalid -->
2002
2003 <reg32 offset="0x8100" name="GRAS_LRZ_CNTL">
2004 <!--
2005 These bits seems to mostly fit.. but wouldn't hurt to have a 2nd
2006 look when we get around to enabling lrz
2007 -->
2008 <bitfield name="ENABLE" pos="0" type="boolean"/>
2009 <doc>LRZ write also disabled for blend/etc.</doc>
2010 <bitfield name="LRZ_WRITE" pos="1" type="boolean"/>
2011 <doc>update MAX instead of MIN value, ie. GL_GREATER/GL_GEQUAL</doc>
2012 <bitfield name="GREATER" pos="2" type="boolean"/>
2013 <bitfield name="FC_ENABLE" pos="3" type="boolean"/>
2014 <!-- set when depth-test + depth-write enabled -->
2015 <bitfield name="Z_TEST_ENABLE" pos="4" type="boolean"/>
2016 <bitfield name="UNK5" low="5" high="9"/>
2017 </reg32>
2018 <reg32 offset="0x8101" name="GRAS_UNKNOWN_8101" low="0" high="2"/>
2019 <reg32 offset="0x8102" name="GRAS_2D_BLIT_INFO">
2020 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
2021 </reg32>
2022 <reg32 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE_LO"/>
2023 <reg32 offset="0x8104" name="GRAS_LRZ_BUFFER_BASE_HI"/>
2024 <reg64 offset="0x8103" name="GRAS_LRZ_BUFFER_BASE" align="256" type="waddress"/>
2025 <reg32 offset="0x8105" name="GRAS_LRZ_BUFFER_PITCH">
2026 <!-- TODO: fix the shr fields -->
2027 <bitfield name="PITCH" low="0" high="7" shr="5" type="uint"/>
2028 <bitfield name="ARRAY_PITCH" low="10" high="28" shr="4" type="uint"/>
2029 </reg32>
2030
2031 <!--
2032 The LRZ "fast clear" buffer is initialized to zero's by blob, and
2033 read/written when GRAS_LRZ_CNTL.FC_ENABLE (b3) is set. It appears
2034 to store 1b/block. It appears that '0' means block has original
2035 depth clear value, and '1' means that the corresponding block in
2036 LRZ has been modified. Ignoring alignment/padding, the size is
2037 given by the formula:
2038
2039 // calculate LRZ size from depth size:
2040 if (nr_samples == 4) {
2041 width *= 2;
2042 height *= 2;
2043 } else if (nr_samples == 2) {
2044 height *= 2;
2045 }
2046
2047 lrz_width = div_round_up(width, 8);
2048 lrz_heigh = div_round_up(height, 8);
2049
2050 // calculate # of blocks:
2051 nblocksx = div_round_up(lrz_width, 16);
2052 nblocksy = div_round_up(lrz_height, 4);
2053
2054 // fast-clear buffer is 1bit/block:
2055 fc_sz = div_round_up(nblocksx * nblocksy, 8);
2056
2057 In practice the blob seems to switch off FC_ENABLE once the size
2058 increases beyond 1 page. Not sure if that is an actual limit or
2059 not.
2060 -->
2061 <reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO"/>
2062 <reg32 offset="0x8107" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI"/>
2063 <reg32 offset="0x8106" name="GRAS_LRZ_FAST_CLEAR_BUFFER_BASE" align="64" type="waddress"/>
2064 <!-- 0x8108 invalid -->
2065 <reg32 offset="0x8109" name="GRAS_SAMPLE_CNTL">
2066 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
2067 </reg32>
2068 <reg32 offset="0x810a" name="GRAS_UNKNOWN_810A">
2069 <bitfield name="UNK0" low="0" high="10" type="uint"/>
2070 <bitfield name="UNK16" low="16" high="26" type="uint"/>
2071 <bitfield name="UNK28" low="28" high="31" type="uint"/>
2072 </reg32>
2073
2074 <!-- 0x810b-0x810f invalid -->
2075
2076 <reg32 offset="0x8110" name="GRAS_UNKNOWN_8110" low="0" high="1"/>
2077
2078 <!-- 0x8111-0x83ff invalid -->
2079
2080 <enum name="a6xx_rotation">
2081 <value value="0x0" name="ROTATE_0"/>
2082 <value value="0x1" name="ROTATE_90"/>
2083 <value value="0x2" name="ROTATE_180"/>
2084 <value value="0x3" name="ROTATE_270"/>
2085 <value value="0x4" name="ROTATE_HFLIP"/>
2086 <value value="0x5" name="ROTATE_VFLIP"/>
2087 </enum>
2088
2089 <bitset name="a6xx_2d_blit_cntl" inline="yes">
2090 <bitfield name="ROTATE" low="0" high="2" type="a6xx_rotation"/>
2091 <bitfield name="UNK3" low="3" high="6"/>
2092 <bitfield name="SOLID_COLOR" pos="7" type="boolean"/>
2093 <bitfield name="COLOR_FORMAT" low="8" high="15" type="a6xx_format"/>
2094 <bitfield name="SCISSOR" pos="16" type="boolean"/>
2095 <bitfield name="UNK17" low="17" high="18"/>
2096 <!-- required when blitting D24S8/D24X8 -->
2097 <bitfield name="D24S8" pos="19" type="boolean"/>
2098 <!-- some sort of channel mask, disabled channels are set to zero ? -->
2099 <bitfield name="MASK" low="20" high="23"/>
2100 <bitfield name="IFMT" low="24" high="28" type="a6xx_2d_ifmt"/>
2101 <bitfield name="UNK29" pos="29"/>
2102 </bitset>
2103
2104 <reg32 offset="0x8400" name="GRAS_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/>
2105 <!-- note: the low 8 bits for src coords are valid, probably fixed point
2106 it would be a bit weird though, since we subtract 1 from BR coords
2107 apparently signed, gallium driver uses negative coords and it works?
2108 -->
2109 <reg32 offset="0x8401" name="GRAS_2D_SRC_TL_X" low="8" high="24" type="int"/>
2110 <reg32 offset="0x8402" name="GRAS_2D_SRC_BR_X" low="8" high="24" type="int"/>
2111 <reg32 offset="0x8403" name="GRAS_2D_SRC_TL_Y" low="8" high="24" type="int"/>
2112 <reg32 offset="0x8404" name="GRAS_2D_SRC_BR_Y" low="8" high="24" type="int"/>
2113 <reg32 offset="0x8405" name="GRAS_2D_DST_TL" type="a6xx_reg_xy"/>
2114 <reg32 offset="0x8406" name="GRAS_2D_DST_BR" type="a6xx_reg_xy"/>
2115 <reg32 offset="0x8407" name="GRAS_2D_UNKNOWN_8407" low="0" high="31"/>
2116 <reg32 offset="0x8408" name="GRAS_2D_UNKNOWN_8408" low="0" high="31"/>
2117 <reg32 offset="0x8409" name="GRAS_2D_UNKNOWN_8409" low="0" high="31"/>
2118 <reg32 offset="0x840a" name="GRAS_2D_RESOLVE_CNTL_1" type="a6xx_reg_xy"/>
2119 <reg32 offset="0x840b" name="GRAS_2D_RESOLVE_CNTL_2" type="a6xx_reg_xy"/>
2120 <!-- 0x840c-0x85ff invalid -->
2121
2122 <!-- always 0x880 ? (and 0 in a640/a650 traces?) -->
2123 <reg32 offset="0x8600" name="GRAS_UNKNOWN_8600" low="0" high="12" />
2124 <reg32 offset="0x8601" name="GRAS_ADDR_MODE_CNTL" pos="0" type="a5xx_address_mode"/>
2125 <reg32 offset="0x8610" name="GRAS_PERFCTR_TSE_SEL_0"/>
2126 <reg32 offset="0x8611" name="GRAS_PERFCTR_TSE_SEL_1"/>
2127 <reg32 offset="0x8612" name="GRAS_PERFCTR_TSE_SEL_2"/>
2128 <reg32 offset="0x8613" name="GRAS_PERFCTR_TSE_SEL_3"/>
2129 <reg32 offset="0x8614" name="GRAS_PERFCTR_RAS_SEL_0"/>
2130 <reg32 offset="0x8615" name="GRAS_PERFCTR_RAS_SEL_1"/>
2131 <reg32 offset="0x8616" name="GRAS_PERFCTR_RAS_SEL_2"/>
2132 <reg32 offset="0x8617" name="GRAS_PERFCTR_RAS_SEL_3"/>
2133 <reg32 offset="0x8618" name="GRAS_PERFCTR_LRZ_SEL_0"/>
2134 <reg32 offset="0x8619" name="GRAS_PERFCTR_LRZ_SEL_1"/>
2135 <reg32 offset="0x861A" name="GRAS_PERFCTR_LRZ_SEL_2"/>
2136 <reg32 offset="0x861B" name="GRAS_PERFCTR_LRZ_SEL_3"/>
2137
2138 <!-- note 0x8620-0x87ff are not all invalid
2139 (in particular, 0x8631/0x8632 have 0x3fff3fff mask and would be xy coords)
2140 -->
2141
2142 <!-- same as GRAS_BIN_CONTROL, but without bit 27: -->
2143 <reg32 offset="0x8800" name="RB_BIN_CONTROL">
2144 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
2145 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
2146 <bitfield name="BINNING_PASS" pos="18" type="boolean"/>
2147 <bitfield name="UNK19" pos="19"/>
2148 <bitfield name="UNK20" pos="20"/>
2149 <bitfield name="USE_VIZ" pos="21" type="boolean"/>
2150 <bitfield name="UNK22" low="22" high="26"/>
2151 </reg32>
2152 <reg32 offset="0x8801" name="RB_RENDER_CNTL">
2153 <bitfield name="UNK3" pos="3" type="boolean"/>
2154 <!-- always set: ?? -->
2155 <bitfield name="UNK4" pos="4" type="boolean"/>
2156 <bitfield name="UNK5" low="5" high="6"/>
2157 <!-- set during binning pass: -->
2158 <bitfield name="BINNING" pos="7" type="boolean"/>
2159 <bitfield name="UNK8" low="8" high="12"/>
2160 <!-- bit seems to be set whenever depth buffer enabled: -->
2161 <bitfield name="FLAG_DEPTH" pos="14" type="boolean"/>
2162 <!-- bitmask of MRTs using UBWC flag buffer: -->
2163 <bitfield name="FLAG_MRTS" low="16" high="23"/>
2164 </reg32>
2165 <reg32 offset="0x8802" name="RB_RAS_MSAA_CNTL">
2166 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
2167 <bitfield name="UNK2" pos="2"/>
2168 <bitfield name="UNK3" pos="3"/>
2169 </reg32>
2170 <reg32 offset="0x8803" name="RB_DEST_MSAA_CNTL">
2171 <bitfield name="SAMPLES" low="0" high="1" type="a3xx_msaa_samples"/>
2172 <bitfield name="MSAA_DISABLE" pos="2" type="boolean"/>
2173 </reg32>
2174
2175 <reg32 offset="0x8804" name="RB_SAMPLE_CONFIG" type="a6xx_sample_config"/>
2176 <reg32 offset="0x8805" name="RB_SAMPLE_LOCATION_0" type="a6xx_sample_locations"/>
2177 <reg32 offset="0x8806" name="RB_SAMPLE_LOCATION_1" type="a6xx_sample_locations"/>
2178 <!-- 0x8807-0x8808 invalid -->
2179 <!--
2180 note: maybe not actually called RB_RENDER_CONTROLn (since RB_RENDER_CNTL
2181 name comes from kernel and is probably right)
2182 -->
2183 <reg32 offset="0x8809" name="RB_RENDER_CONTROL0">
2184 <!-- see also GRAS_CNTL -->
2185 <bitfield name="IJ_PERSP_PIXEL" pos="0" type="boolean"/>
2186 <!-- b1 set for interpolateAtCentroid() -->
2187 <bitfield name="IJ_PERSP_CENTROID" pos="1" type="boolean"/>
2188 <!-- b2 set instead of b0 when running in per-sample mode -->
2189 <bitfield name="IJ_PERSP_SAMPLE" pos="2" type="boolean"/>
2190 <!--
2191 b3 set for interpolateAt{Offset,Sample}() if not in per-sample
2192 mode, and frag_face
2193 -->
2194 <bitfield name="SIZE" pos="3" type="boolean"/>
2195 <bitfield name="UNK4" pos="4" type="boolean"/>
2196 <!-- b5 set ofr interpolateAt{Offset,Sample}() if in per-sample mode -->
2197 <bitfield name="SIZE_PERSAMP" pos="5" type="boolean"/>
2198 <bitfield name="COORD_MASK" low="6" high="9" type="hex"/>
2199 <bitfield name="UNK10" pos="10" type="boolean"/>
2200 </reg32>
2201 <reg32 offset="0x880a" name="RB_RENDER_CONTROL1">
2202 <!-- enable bits for various FS sysvalue regs: -->
2203 <bitfield name="SAMPLEMASK" pos="0" type="boolean"/>
2204 <bitfield name="UNK1" pos="1" type="boolean"/>
2205 <bitfield name="FACENESS" pos="2" type="boolean"/>
2206 <bitfield name="SAMPLEID" pos="3" type="boolean"/>
2207 <!-- b4 and b5 set in per-sample mode: -->
2208 <bitfield name="UNK4" pos="4" type="boolean"/>
2209 <bitfield name="UNK5" pos="5" type="boolean"/>
2210 <bitfield name="SIZE" pos="6" type="boolean"/>
2211 <bitfield name="UNK7" pos="7" type="boolean"/>
2212 <bitfield name="UNK8" pos="8" type="boolean"/>
2213 </reg32>
2214
2215 <reg32 offset="0x880b" name="RB_FS_OUTPUT_CNTL0">
2216 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="0" type="boolean"/>
2217 <bitfield name="FRAG_WRITES_Z" pos="1" type="boolean"/>
2218 <bitfield name="FRAG_WRITES_SAMPMASK" pos="2" type="boolean"/>
2219 <bitfield name="FRAG_WRITES_STENCILREF" pos="3" type="boolean"/>
2220 </reg32>
2221 <reg32 offset="0x880c" name="RB_FS_OUTPUT_CNTL1">
2222 <bitfield name="MRT" low="0" high="3" type="uint"/>
2223 </reg32>
2224 <reg32 offset="0x880d" name="RB_RENDER_COMPONENTS">
2225 <bitfield name="RT0" low="0" high="3"/>
2226 <bitfield name="RT1" low="4" high="7"/>
2227 <bitfield name="RT2" low="8" high="11"/>
2228 <bitfield name="RT3" low="12" high="15"/>
2229 <bitfield name="RT4" low="16" high="19"/>
2230 <bitfield name="RT5" low="20" high="23"/>
2231 <bitfield name="RT6" low="24" high="27"/>
2232 <bitfield name="RT7" low="28" high="31"/>
2233 </reg32>
2234 <reg32 offset="0x880e" name="RB_DITHER_CNTL">
2235 <bitfield name="DITHER_MODE_MRT0" low="0" high="1" type="adreno_rb_dither_mode"/>
2236 <bitfield name="DITHER_MODE_MRT1" low="2" high="3" type="adreno_rb_dither_mode"/>
2237 <bitfield name="DITHER_MODE_MRT2" low="4" high="5" type="adreno_rb_dither_mode"/>
2238 <bitfield name="DITHER_MODE_MRT3" low="6" high="7" type="adreno_rb_dither_mode"/>
2239 <bitfield name="DITHER_MODE_MRT4" low="8" high="9" type="adreno_rb_dither_mode"/>
2240 <bitfield name="DITHER_MODE_MRT5" low="10" high="11" type="adreno_rb_dither_mode"/>
2241 <bitfield name="DITHER_MODE_MRT6" low="12" high="12" type="adreno_rb_dither_mode"/>
2242 <bitfield name="DITHER_MODE_MRT7" low="14" high="15" type="adreno_rb_dither_mode"/>
2243 </reg32>
2244 <reg32 offset="0x880f" name="RB_SRGB_CNTL">
2245 <!-- Same as SP_SRGB_CNTL -->
2246 <bitfield name="SRGB_MRT0" pos="0" type="boolean"/>
2247 <bitfield name="SRGB_MRT1" pos="1" type="boolean"/>
2248 <bitfield name="SRGB_MRT2" pos="2" type="boolean"/>
2249 <bitfield name="SRGB_MRT3" pos="3" type="boolean"/>
2250 <bitfield name="SRGB_MRT4" pos="4" type="boolean"/>
2251 <bitfield name="SRGB_MRT5" pos="5" type="boolean"/>
2252 <bitfield name="SRGB_MRT6" pos="6" type="boolean"/>
2253 <bitfield name="SRGB_MRT7" pos="7" type="boolean"/>
2254 </reg32>
2255
2256 <reg32 offset="0x8810" name="RB_SAMPLE_CNTL">
2257 <bitfield name="PER_SAMP_MODE" pos="0" type="boolean"/>
2258 </reg32>
2259 <reg32 offset="0x8811" name="RB_UNKNOWN_8811" low="4" high="6"/>
2260 <!-- 0x8812-0x8817 invalid -->
2261 <!-- always 0x0 ? -->
2262 <reg32 offset="0x8818" name="RB_UNKNOWN_8818" low="0" high="6"/>
2263 <!-- 0x8819-0x881e all 32 bits -->
2264 <reg32 offset="0x8819" name="RB_UNKNOWN_8819"/>
2265 <reg32 offset="0x881a" name="RB_UNKNOWN_881A"/>
2266 <reg32 offset="0x881b" name="RB_UNKNOWN_881B"/>
2267 <reg32 offset="0x881c" name="RB_UNKNOWN_881C"/>
2268 <reg32 offset="0x881d" name="RB_UNKNOWN_881D"/>
2269 <reg32 offset="0x881e" name="RB_UNKNOWN_881E"/>
2270 <!-- 0x881f invalid -->
2271 <array offset="0x8820" name="RB_MRT" stride="8" length="8">
2272 <reg32 offset="0x0" name="CONTROL">
2273 <bitfield name="BLEND" pos="0" type="boolean"/>
2274 <bitfield name="BLEND2" pos="1" type="boolean"/>
2275 <bitfield name="ROP_ENABLE" pos="2" type="boolean"/>
2276 <bitfield name="ROP_CODE" low="3" high="6" type="a3xx_rop_code"/>
2277 <bitfield name="COMPONENT_ENABLE" low="7" high="10" type="hex"/>
2278 </reg32>
2279 <reg32 offset="0x1" name="BLEND_CONTROL">
2280 <bitfield name="RGB_SRC_FACTOR" low="0" high="4" type="adreno_rb_blend_factor"/>
2281 <bitfield name="RGB_BLEND_OPCODE" low="5" high="7" type="a3xx_rb_blend_opcode"/>
2282 <bitfield name="RGB_DEST_FACTOR" low="8" high="12" type="adreno_rb_blend_factor"/>
2283 <bitfield name="ALPHA_SRC_FACTOR" low="16" high="20" type="adreno_rb_blend_factor"/>
2284 <bitfield name="ALPHA_BLEND_OPCODE" low="21" high="23" type="a3xx_rb_blend_opcode"/>
2285 <bitfield name="ALPHA_DEST_FACTOR" low="24" high="28" type="adreno_rb_blend_factor"/>
2286 </reg32>
2287 <reg32 offset="0x2" name="BUF_INFO">
2288 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
2289 <bitfield name="COLOR_TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
2290 <bitfield name="UNK10" pos="10"/>
2291 <bitfield name="COLOR_SWAP" low="13" high="14" type="a3xx_color_swap"/>
2292 </reg32>
2293 <!--
2294 at least in gmem, things seem to be aligned to pitch of 64..
2295 maybe an artifact of tiled format used in gmem?
2296 -->
2297 <reg32 offset="0x3" name="PITCH" shr="6" high="15" type="uint"/>
2298 <reg32 offset="0x4" name="ARRAY_PITCH" shr="6" high="28" type="uint"/>
2299 <!--
2300 Compared to a5xx and before, we configure both a GMEM base and
2301 external base. Not sure if this is to facilitate GMEM save/
2302 restore for context switch, or just to simplify state setup to
2303 not have to care about GMEM vs BYPASS mode.
2304 -->
2305 <reg32 offset="0x5" name="BASE_LO"/>
2306 <reg32 offset="0x6" name="BASE_HI"/>
2307
2308 <!-- maybe something in low bits since alignment of 1 doesn't make sense? -->
2309 <reg64 offset="0x5" name="BASE" type="waddress" align="1"/>
2310
2311 <reg32 offset="0x7" name="BASE_GMEM" low="12" high="31" shr="12"/>
2312 </array>
2313
2314 <reg32 offset="0x8860" name="RB_BLEND_RED_F32" type="float"/>
2315 <reg32 offset="0x8861" name="RB_BLEND_GREEN_F32" type="float"/>
2316 <reg32 offset="0x8862" name="RB_BLEND_BLUE_F32" type="float"/>
2317 <reg32 offset="0x8863" name="RB_BLEND_ALPHA_F32" type="float"/>
2318 <reg32 offset="0x8864" name="RB_ALPHA_CONTROL">
2319 <bitfield name="ALPHA_REF" low="0" high="7" type="hex"/>
2320 <bitfield name="ALPHA_TEST" pos="8" type="boolean"/>
2321 <bitfield name="ALPHA_TEST_FUNC" low="9" high="11" type="adreno_compare_func"/>
2322 </reg32>
2323 <reg32 offset="0x8865" name="RB_BLEND_CNTL">
2324 <!-- per-mrt enable bit -->
2325 <bitfield name="ENABLE_BLEND" low="0" high="7"/>
2326 <bitfield name="INDEPENDENT_BLEND" pos="8" type="boolean"/>
2327 <bitfield name="DUAL_COLOR_IN_ENABLE" pos="9" type="boolean"/>
2328 <bitfield name="ALPHA_TO_COVERAGE" pos="10" type="boolean"/>
2329 <bitfield name="ALPHA_TO_ONE" pos="11" type="boolean"/>
2330 <bitfield name="SAMPLE_MASK" low="16" high="31"/>
2331 </reg32>
2332 <!-- 0x8866-0x886f invalid -->
2333 <reg32 offset="0x8870" name="RB_DEPTH_PLANE_CNTL">
2334 <bitfield name="Z_MODE" low="0" high="1" type="a6xx_ztest_mode"/>
2335 </reg32>
2336
2337 <reg32 offset="0x8871" name="RB_DEPTH_CNTL">
2338 <bitfield name="Z_ENABLE" pos="0" type="boolean"/>
2339 <bitfield name="Z_WRITE_ENABLE" pos="1" type="boolean"/>
2340 <bitfield name="ZFUNC" low="2" high="4" type="adreno_compare_func"/>
2341 <bitfield name="Z_CLAMP_ENABLE" pos="5" type="boolean"/>
2342 <doc>
2343 Z_TEST_ENABLE bit is set for zfunc other than GL_ALWAYS or GL_NEVER
2344 also set when Z_BOUNDS_ENABLE is set
2345 </doc>
2346 <bitfield name="Z_TEST_ENABLE" pos="6" type="boolean"/>
2347 <bitfield name="Z_BOUNDS_ENABLE" pos="7" type="boolean"/>
2348 </reg32>
2349 <!-- duplicates GRAS_SU_DEPTH_BUFFER_INFO: -->
2350 <reg32 offset="0x8872" name="RB_DEPTH_BUFFER_INFO">
2351 <bitfield name="DEPTH_FORMAT" low="0" high="2" type="a6xx_depth_format"/>
2352 <bitfield name="UNK3" low="3" high="4"/>
2353 </reg32>
2354 <reg32 offset="0x8873" name="RB_DEPTH_BUFFER_PITCH" low="0" high="13" shr="6" type="uint"/>
2355 <reg32 offset="0x8874" name="RB_DEPTH_BUFFER_ARRAY_PITCH" low="0" high="27" shr="6" type="uint"/>
2356 <reg32 offset="0x8875" name="RB_DEPTH_BUFFER_BASE_LO"/>
2357 <reg32 offset="0x8876" name="RB_DEPTH_BUFFER_BASE_HI"/>
2358 <reg64 offset="0x8875" name="RB_DEPTH_BUFFER_BASE" type="waddress" align="64"/>
2359 <reg32 offset="0x8877" name="RB_DEPTH_BUFFER_BASE_GMEM" low="12" high="31" shr="12"/>
2360
2361 <reg32 offset="0x8878" name="RB_Z_BOUNDS_MIN" type="float"/>
2362 <reg32 offset="0x8879" name="RB_Z_BOUNDS_MAX" type="float"/>
2363 <!-- 0x887a-0x887f invalid -->
2364 <reg32 offset="0x8880" name="RB_STENCIL_CONTROL">
2365 <bitfield name="STENCIL_ENABLE" pos="0" type="boolean"/>
2366 <bitfield name="STENCIL_ENABLE_BF" pos="1" type="boolean"/>
2367 <!--
2368 set for stencil operations that require read from stencil
2369 buffer, but not for example for stencil clear (which does
2370 not require read).. so guessing this is analogous to
2371 READ_DEST_ENABLE for color buffer..
2372 -->
2373 <bitfield name="STENCIL_READ" pos="2" type="boolean"/>
2374 <bitfield name="FUNC" low="8" high="10" type="adreno_compare_func"/>
2375 <bitfield name="FAIL" low="11" high="13" type="adreno_stencil_op"/>
2376 <bitfield name="ZPASS" low="14" high="16" type="adreno_stencil_op"/>
2377 <bitfield name="ZFAIL" low="17" high="19" type="adreno_stencil_op"/>
2378 <bitfield name="FUNC_BF" low="20" high="22" type="adreno_compare_func"/>
2379 <bitfield name="FAIL_BF" low="23" high="25" type="adreno_stencil_op"/>
2380 <bitfield name="ZPASS_BF" low="26" high="28" type="adreno_stencil_op"/>
2381 <bitfield name="ZFAIL_BF" low="29" high="31" type="adreno_stencil_op"/>
2382 </reg32>
2383 <reg32 offset="0x8881" name="RB_STENCIL_INFO">
2384 <bitfield name="SEPARATE_STENCIL" pos="0" type="boolean"/>
2385 <bitfield name="UNK1" pos="1" type="boolean"/>
2386 </reg32>
2387 <reg32 offset="0x8882" name="RB_STENCIL_BUFFER_PITCH" low="0" high="11" shr="6" type="uint"/>
2388 <reg32 offset="0x8883" name="RB_STENCIL_BUFFER_ARRAY_PITCH" low="0" high="23" shr="6" type="uint"/>
2389 <reg32 offset="0x8884" name="RB_STENCIL_BUFFER_BASE_LO"/>
2390 <reg32 offset="0x8885" name="RB_STENCIL_BUFFER_BASE_HI"/>
2391 <reg64 offset="0x8884" name="RB_STENCIL_BUFFER_BASE" type="waddress" align="64"/>
2392 <reg32 offset="0x8886" name="RB_STENCIL_BUFFER_BASE_GMEM" low="12" high="31" shr="12"/>
2393 <reg32 offset="0x8887" name="RB_STENCILREF">
2394 <bitfield name="REF" low="0" high="7"/>
2395 <bitfield name="BFREF" low="8" high="15"/>
2396 </reg32>
2397 <reg32 offset="0x8888" name="RB_STENCILMASK">
2398 <bitfield name="MASK" low="0" high="7"/>
2399 <bitfield name="BFMASK" low="8" high="15"/>
2400 </reg32>
2401 <reg32 offset="0x8889" name="RB_STENCILWRMASK">
2402 <bitfield name="WRMASK" low="0" high="7"/>
2403 <bitfield name="BFWRMASK" low="8" high="15"/>
2404 </reg32>
2405 <!-- 0x888a-0x888f invalid -->
2406 <reg32 offset="0x8890" name="RB_WINDOW_OFFSET" type="a6xx_reg_xy"/>
2407 <reg32 offset="0x8891" name="RB_SAMPLE_COUNT_CONTROL">
2408 <bitfield name="UNK0" pos="0" type="boolean"/>
2409 <bitfield name="COPY" pos="1" type="boolean"/>
2410 </reg32>
2411 <!-- 0x8892-0x8897 invalid -->
2412 <reg32 offset="0x8898" name="RB_LRZ_CNTL">
2413 <bitfield name="ENABLE" pos="0" type="boolean"/>
2414 </reg32>
2415 <!-- 0x8899-0x88bf invalid -->
2416 <!-- clamps depth value for depth test/write -->
2417 <reg32 offset="0x88c0" name="RB_Z_CLAMP_MIN" type="float"/>
2418 <reg32 offset="0x88c1" name="RB_Z_CLAMP_MAX" type="float"/>
2419 <!-- 0x88c2-0x88cf invalid-->
2420 <reg32 offset="0x88d0" name="RB_UNKNOWN_88D0">
2421 <bitfield name="UNK0" low="0" high="12"/>
2422 <bitfield name="UNK16" low="16" high="26"/>
2423 </reg32>
2424 <reg32 offset="0x88d1" name="RB_BLIT_SCISSOR_TL" type="a6xx_reg_xy"/>
2425 <reg32 offset="0x88d2" name="RB_BLIT_SCISSOR_BR" type="a6xx_reg_xy"/>
2426 <!-- weird to duplicate other regs from same block?? -->
2427 <reg32 offset="0x88d3" name="RB_BIN_CONTROL2">
2428 <bitfield name="BINW" low="0" high="5" shr="5" type="uint"/>
2429 <bitfield name="BINH" low="8" high="14" shr="4" type="uint"/>
2430 </reg32>
2431 <reg32 offset="0x88d4" name="RB_WINDOW_OFFSET2" type="a6xx_reg_xy"/>
2432 <reg32 offset="0x88d5" name="RB_MSAA_CNTL">
2433 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
2434 </reg32>
2435 <reg32 offset="0x88d6" name="RB_BLIT_BASE_GMEM" low="12" high="31" shr="12"/>
2436 <!-- s/DST_FORMAT/DST_INFO/ probably: -->
2437 <reg32 offset="0x88d7" name="RB_BLIT_DST_INFO">
2438 <bitfield name="TILE_MODE" low="0" high="1" type="a6xx_tile_mode"/>
2439 <bitfield name="FLAGS" pos="2" type="boolean"/>
2440 <bitfield name="SAMPLES" low="3" high="4" type="a3xx_msaa_samples"/>
2441 <bitfield name="COLOR_SWAP" low="5" high="6" type="a3xx_color_swap"/>
2442 <bitfield name="COLOR_FORMAT" low="7" high="14" type="a6xx_format"/>
2443 <bitfield name="UNK15" pos="15" type="boolean"/>
2444 </reg32>
2445 <reg64 offset="0x88d8" name="RB_BLIT_DST" type="waddress" align="64"/>
2446 <reg32 offset="0x88d8" name="RB_BLIT_DST_LO"/>
2447 <reg32 offset="0x88d9" name="RB_BLIT_DST_HI"/>
2448 <reg32 offset="0x88da" name="RB_BLIT_DST_PITCH" low="0" high="15" shr="6" type="uint"/>
2449 <!-- array-pitch is size of layer -->
2450 <reg32 offset="0x88db" name="RB_BLIT_DST_ARRAY_PITCH" low="0" high="28" shr="6" type="uint"/>
2451 <reg64 offset="0x88dc" name="RB_BLIT_FLAG_DST" type="waddress" align="64"/>
2452 <reg32 offset="0x88dc" name="RB_BLIT_FLAG_DST_LO"/>
2453 <reg32 offset="0x88dd" name="RB_BLIT_FLAG_DST_HI"/>
2454 <reg32 offset="0x88de" name="RB_BLIT_FLAG_DST_PITCH">
2455 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2456 <bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/>
2457 </reg32>
2458
2459 <reg32 offset="0x88df" name="RB_BLIT_CLEAR_COLOR_DW0"/>
2460 <reg32 offset="0x88e0" name="RB_BLIT_CLEAR_COLOR_DW1"/>
2461 <reg32 offset="0x88e1" name="RB_BLIT_CLEAR_COLOR_DW2"/>
2462 <reg32 offset="0x88e2" name="RB_BLIT_CLEAR_COLOR_DW3"/>
2463
2464 <!-- seems somewhat similar to what we called RB_CLEAR_CNTL on a5xx: -->
2465 <reg32 offset="0x88e3" name="RB_BLIT_INFO">
2466 <bitfield name="UNK0" pos="0" type="boolean"/> <!-- s8 stencil restore/clear? But also color restore? -->
2467 <bitfield name="GMEM" pos="1" type="boolean"/> <!-- set for restore and clear to gmem? -->
2468 <bitfield name="INTEGER" pos="2" type="boolean"/> <!-- probably -->
2469 <bitfield name="DEPTH" pos="3" type="boolean"/> <!-- z16/z32/z24s8/x24x8 clear or resolve? -->
2470 <doc>
2471 For clearing depth/stencil
2472 1 - depth
2473 2 - stencil
2474 3 - depth+stencil
2475 For clearing color buffer:
2476 then probably a component mask, I always see 0xf
2477 </doc>
2478 <bitfield name="CLEAR_MASK" low="4" high="7"/>
2479 <bitfield name="UNK8" low="8" high="9"/>
2480 <bitfield name="UNK12" low="12" high="15"/>
2481 </reg32>
2482 <!-- 0x88e4-0x88ef invalid -->
2483 <!-- always 0x0 ? -->
2484 <reg32 offset="0x88f0" name="RB_UNKNOWN_88F0" low="0" high="11"/>
2485 <!-- could be for separate stencil? (or may not be a flag buffer at all) -->
2486 <reg64 offset="0x88f1" name="RB_UNK_FLAG_BUFFER_BASE" type="waddress" align="64"/>
2487 <reg32 offset="0x88f3" name="RB_UNK_FLAG_BUFFER_PITCH">
2488 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2489 <bitfield name="ARRAY_PITCH" low="11" high="23" shr="7" type="uint"/>
2490 </reg32>
2491 <reg32 offset="0x88f4" name="RB_UNKNOWN_88F4" low="0" high="2"/>
2492 <!-- 0x88f5-0x88ff invalid -->
2493 <reg32 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE_LO"/>
2494 <reg32 offset="0x8901" name="RB_DEPTH_FLAG_BUFFER_BASE_HI"/>
2495 <reg64 offset="0x8900" name="RB_DEPTH_FLAG_BUFFER_BASE" type="waddress" align="64"/>
2496 <reg32 offset="0x8902" name="RB_DEPTH_FLAG_BUFFER_PITCH">
2497 <bitfield name="PITCH" low="0" high="6" shr="6" type="uint"/>
2498 <!-- TODO: actually part of array pitch -->
2499 <bitfield name="UNK8" low="8" high="10"/>
2500 <bitfield name="ARRAY_PITCH" low="11" high="27" shr="7" type="uint"/>
2501 </reg32>
2502 <array offset="0x8903" name="RB_MRT_FLAG_BUFFER" stride="3" length="8">
2503 <reg32 offset="0" name="ADDR_LO"/>
2504 <reg32 offset="1" name="ADDR_HI"/>
2505 <reg64 offset="0" name="ADDR" type="waddress" align="64"/>
2506 <reg32 offset="2" name="PITCH">
2507 <bitfield name="PITCH" low="0" high="10" shr="6" type="uint"/>
2508 <bitfield name="ARRAY_PITCH" low="11" high="28" shr="7" type="uint"/>
2509 </reg32>
2510 </array>
2511 <!-- 0x891b-0x8926 invalid -->
2512 <reg32 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR_LO"/>
2513 <reg32 offset="0x8928" name="RB_SAMPLE_COUNT_ADDR_HI"/>
2514 <reg64 offset="0x8927" name="RB_SAMPLE_COUNT_ADDR" type="waddress" align="16"/>
2515 <!-- 0x8929-0x89ff invalid -->
2516
2517 <!-- TODO: there are some registers in the 0x8a00-0x8bff range -->
2518
2519 <reg32 offset="0x8c00" name="RB_2D_BLIT_CNTL" type="a6xx_2d_blit_cntl"/>
2520 <reg32 offset="0x8c01" name="RB_2D_UNKNOWN_8C01" low="0" high="31"/>
2521
2522 <bitset name="a6xx_2d_surf_info" inline="yes">
2523 <bitfield name="COLOR_FORMAT" low="0" high="7" type="a6xx_format"/>
2524 <bitfield name="TILE_MODE" low="8" high="9" type="a6xx_tile_mode"/>
2525 <bitfield name="COLOR_SWAP" low="10" high="11" type="a3xx_color_swap"/>
2526 <bitfield name="FLAGS" pos="12" type="boolean"/>
2527 <bitfield name="SRGB" pos="13" type="boolean"/>
2528 <!-- the rest is only for src -->
2529 <bitfield name="SAMPLES" low="14" high="15" type="a3xx_msaa_samples"/>
2530 <bitfield name="FILTER" pos="16" type="boolean"/>
2531 <bitfield name="SAMPLES_AVERAGE" pos="18" type="boolean"/>
2532 <