src/freedreno/registers/adreno/adreno_control_regs.xml

   1 <?xml version="1.0" encoding="UTF-8"?>
   2 <database xmlns="http://nouveau.freedesktop.org/"
   3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
   4 xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
   5
   6 <!--
   7         This documents the internal register space used by the CP firmware since
   8         the afuc instruction set was introduced.
   9 -->
  10
  11 <domain name="A5XX_CONTROL_REG" width="32">
  12         <reg64 name="IB1_BASE" offset="0x0b0"/>
  13         <reg32 name="IB1_DWORDS" offset="0x0b2"/>
  14         <reg64 name="IB2_BASE" offset="0x0b4"/>
  15         <reg32 name="IB2_DWORDS" offset="0x0b6"/>
  16
  17         <doc>
  18                 To use these, write the address and number of dwords, then read
  19                 the result from $addr.
  20         </doc>
  21         <reg64 name="MEM_READ_ADDR" offset="0x0b8"/>
  22         <reg32 name="MEM_READ_DWORDS" offset="0x0ba"/>
  23 </domain>
  24
  25 <domain name="A6XX_CONTROL_REG" width="32">
  26         <reg32 name="RB_RPTR" offset="0x001"/>
  27         <doc>
  28                 Instruction to jump to when the CP is preempted to perform a
  29                 context switch, initialized to entry 15 of the jump table at
  30                 bootup.
  31         </doc>
  32         <reg32 name="PREEMPT_INSTR" offset="0x004"/>
  33
  34         <reg64 name="IB1_BASE" offset="0x010"/>
  35         <reg32 name="IB1_DWORDS" offset="0x012"/>
  36         <reg64 name="IB2_BASE" offset="0x014"/>
  37         <reg32 name="IB2_DWORDS" offset="0x016"/>
  38
  39         <reg64 name="MEM_READ_ADDR" offset="0x018"/>
  40         <reg32 name="MEM_READ_DWORDS" offset="0x01a"/>
  41
  42         <reg32 name="REG_WRITE_ADDR" offset="0x024"/>
  43         <doc>
  44                 Writing to this triggers a register write and auto-increments
  45                 REG_WRITE_ADDR.
  46         </doc>
  47         <reg32 name="REG_WRITE" offset="0x025"/>
  48
  49         <doc> After setting these, read result from $addr2 </doc>
  50         <reg32 name="REG_READ_DWORDS" offset="0x026"/>
  51         <reg32 name="REG_READ_ADDR" offset="0x027"/>
  52
  53         <doc>
  54                 Write to increase WFI_PEND_CTR, decremented by WFI_PEND_DECR
  55                 pipe register.
  56         </doc>
  57         <reg32 name="WFI_PEND_INCR" offset="0x030"/>
  58         <reg32 name="QUERY_PEND_INCR" offset="0x031"/>
  59         <reg32 name="CACHE_FLUSH_PEND_INCR" offset="0x031"/>
  60
  61         <reg32 name="WFI_PEND_CTR" offset="0x038"/>
  62         <reg32 name="QUERY_PEND_CTR" offset="0x039"/>
  63         <reg32 name="CACHE_FLUSH_PEND_CTR" offset="0x03a"/>
  64
  65         <reg32 name="DRAW_STATE_SEL" offset="0x041"/>
  66         <reg32 name="DRAW_STATE_ACTIVE_BITMASK" offset="0x049"/>
  67         <reg32 name="DRAW_STATE_SET" offset="0x04a"/>
  68
  69         <doc> Controls whether RB, IB1, or IB2 is executed </doc>
  70         <reg32 name="IB_LEVEL" offset="0x054"/>
  71
  72         <doc> Controls high 32 bits used by load and store afuc instructions </doc>
  73         <reg32 name="LOAD_STORE_HI" offset="0x058"/>
  74
  75         <doc> Used to initialize the jump table for handling packets at bootup </doc>
  76         <reg32 name="PACKET_TABLE_WRITE_ADDR" offset="0x060"/>
  77         <reg32 name="PACKET_TABLE_WRITE" offset="0x061"/>
  78
  79         <reg32 name="PREEMPT_ENABLE" offset="0x071"/>
  80         <reg32 name="SECURE_MODE" offset="0x075"/>
  81
  82         <!--
  83                 Note: I think that registers above 0x100 are actually just a
  84                 scratch space which can be used by firmware however it wants,
  85                 so these might change if the the firmware is updated.
  86         -->
  87
  88         <doc>
  89                 These are addresses of various preemption records for the
  90                 current context. When context switching, the CP will save the
  91                 current state into these buffers, restore the state of the
  92                 next context from the buffers in the corresponding
  93                 CP_CONTEXT_SWITCH_PRIV_* registers written by the kernel,
  94                 then set these internal registers to the contents of
  95                 those registers. The kernel sets the initial values via
  96                 CP_SET_PSEUDO_REG on startup, and from then on the firmware
  97                 keeps track of them.
  98         </doc>
  99         <reg64 name="SAVE_REGISTER_SMMU_INFO" offset="0x110"/>
 100         <reg64 name="SAVE_REGISTER_PRIV_NON_SECURE" offset="0x112"/>
 101         <reg64 name="SAVE_REGISTER_PRIV_SECURE" offset="0x114"/>
 102         <reg64 name="SAVE_REGISTER_NON_PRIV" offset="0x116"/>
 103         <reg64 name="SAVE_REGISTER_COUNTER" offset="0x118"/>
 104
 105         <doc>
 106                 Used only during preemption, saved and restored from the "info"
 107                 field of a6xx_preemption_record. From the downstream kernel:
 108
 109                 "Type of record. Written non-zero (usually) by CP.
 110                 we must set to zero for all ringbuffers."
 111         </doc>
 112
 113         <reg32 name="PREEMPTION_INFO" offset="0x126"/>
 114
 115         <doc>
 116                 Set by SET_MARKER, used to conditionally execute
 117                 CP_COND_REG_EXEC and draw states.
 118         </doc>
 119         <reg32 name="MODE_BITMASK" offset="0x12b"/>
 120
 121         <reg32 name="SCRATCH_REG0" offset="0x170"/>
 122         <reg32 name="SCRATCH_REG1" offset="0x171"/>
 123         <reg32 name="SCRATCH_REG2" offset="0x172"/>
 124         <reg32 name="SCRATCH_REG3" offset="0x173"/>
 125         <reg32 name="SCRATCH_REG4" offset="0x174"/>
 126         <reg32 name="SCRATCH_REG5" offset="0x175"/>
 127         <reg32 name="SCRATCH_REG6" offset="0x176"/>
 128         <reg32 name="SCRATCH_REG7" offset="0x177"/>
 129 </domain>
 130
 131 </database>