src/freedreno/registers/adreno/adreno_pipe_regs.xml

   1 <?xml version="1.0" encoding="UTF-8"?>
   2 <database xmlns="http://nouveau.freedesktop.org/"
   3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
   4 xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
   5
   6 <!--
   7         Pipe registers are a special kind of registers used by SQE on a6xxx, and
   8         on a5xx by the ME, to control the CP. They only exist inside the CP, can
   9         only be written to, and use the high 8 bits of the $addr register. For
  10         example, this is how CP_WAIT_MEM_WRITES is implemented on a6xx:
  11
  12 CP_WAIT_MEM_WRITES:
  13         053b: 8b1d0084  mov $addr, 0x0084 << 24
  14         053c: d8000000  waitin
  15         053d: 981f0806  mov $01, $data
  16
  17         and on a5xx ME:
  18
  19 CP_WAIT_MEM_WRITES:
  20         05c3: 8b1d00c4  mov $addr, 0x00c4 << 24
  21         05c4: d8000000  waitin
  22         05c5: 981f0806  mov $01, $data
  23
  24         This writes to pipe register 0x84, or 0xc4 on a5xx. In this case the
  25         value written is ignored, but for other registers it isn't.
  26
  27         Note that on a6xx, pipe register writes are pipelined together with
  28         regular register writes in what replaced the MEQ.
  29 -->
  30
  31 <bitset name="void" inline="yes">
  32         <doc>Special type to mark registers with no payload.</doc>
  33 </bitset>
  34
  35 <domain name="A6XX_PIPE_REG" width="32">
  36         <!-- This replaces CP_WFI_PEND_CTR on a3xx-a5xx -->
  37         <reg32 name="WFI_PEND_DECR" offset="0x81" type="void"/>
  38         <!-- This is only used for WRITE_PRIMITIVE_COUNTS/ZPASS_DONE events -->
  39         <reg32 name="QUERY_PEND_DECR" offset="0x82" type="void"/>
  40         <reg32 name="WAIT_MEM_WRITES" offset="0x84" type="void"/>
  41
  42         <!-- Replaces CP_ME_NRT_ADDR/DATA on a3xx-a5xx -->
  43         <reg64 name="NRT_ADDR" offset="0xa0"/>
  44         <reg32 name="NRT_DATA" offset="0xa2"/>
  45
  46         <reg32 name="EVENT_CMD" offset="0xe7">
  47                 <enum name="a6xx_event_type">
  48                         <value value="0" name="UNK_EVENT"/> <!-- sometimes used with binning draws? -->
  49                         <value value="1" name="EVENT"/>
  50                         <value value="2" name="DRAW"/>
  51                         <value value="3" name="DISPATCH"/>
  52                 </enum>
  53                 <bitfield name="EVENT_TYPE" low="0" high="1" type="a6xx_event_type"/>
  54                 <!-- set for all *_TS events (i.e. ones that write something) -->
  55                 <bitfield name="TS_WRITE" pos="2" type="boolean"/>
  56                 <!-- Decrement CACHE_FLUSH_PEND_CTR when event happens -->
  57                 <bitfield name="CACHE_FLUSH_PEND_DECR" pos="3" type="boolean"/>
  58         </reg32>
  59         <reg64 name="EVENT_TS_ADDR" offset="0xe8"/>
  60         <reg32 name="EVENT_TS_CTRL" offset="0xea">
  61                 <bitfield name="TIMESTAMP" pos="1" type="boolean"/>
  62                 <bitfield name="INTERRUPT" pos="2" type="boolean"/>
  63                 <enum name="a6xx_ts_event">
  64                         <value value="1" name="CACHE_FLUSH"/>
  65                         <value value="2" name="WT_DONE"/>
  66                         <value value="3" name="RB_DONE"/>
  67                         <value value="4" name="CCU_FLUSH_DEPTH"/>
  68                         <value value="5" name="CCU_FLUSH_COLOR"/>
  69                         <value value="6" name="CCU_RESOLVE"/>
  70                 </enum>
  71                 <bitfield name="EVENT" low="8" high="10" type="a6xx_ts_event"/>
  72         </reg32>
  73         <!-- data to write when !EVENT_TS_CTRL::TIMESTAMP -->
  74         <reg32 name="EVENT_TS_DATA" offset="0xeb"/>
  75 </domain>
  76
  77 </database>