144e716685305ec355b5ff225c80307e6ed0339f
[mesa.git] / src / freedreno / registers / adreno / adreno_pm4.xml
1 <?xml version="1.0" encoding="UTF-8"?>
2 <database xmlns="http://nouveau.freedesktop.org/"
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
5
6 <enum name="vgt_event_type">
7 <value name="VS_DEALLOC" value="0"/>
8 <value name="PS_DEALLOC" value="1"/>
9 <value name="VS_DONE_TS" value="2"/>
10 <value name="PS_DONE_TS" value="3"/>
11 <value name="CACHE_FLUSH_TS" value="4"/>
12 <value name="CONTEXT_DONE" value="5"/>
13 <value name="CACHE_FLUSH" value="6"/>
14 <value name="VIZQUERY_START" value="7" varset="chip" variants="A2XX"/>
15 <value name="HLSQ_FLUSH" value="7" varset="chip" variants="A3XX-A4XX"/>
16 <value name="VIZQUERY_END" value="8" varset="chip" variants="A2XX"/>
17 <value name="SC_WAIT_WC" value="9"/>
18 <value name="WRITE_PRIMITIVE_COUNTS" value="9" varset="chip" variants="A6XX"/>
19 <value name="START_PRIMITIVE_CTRS" value="11" varset="chip" variants="A6XX"/>
20 <value name="STOP_PRIMITIVE_CTRS" value="12" varset="chip" variants="A6XX"/>
21 <value name="RST_PIX_CNT" value="13"/>
22 <value name="RST_VTX_CNT" value="14"/>
23 <value name="TILE_FLUSH" value="15"/>
24 <value name="STAT_EVENT" value="16"/>
25 <value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="20" varset="chip" variants="A2XX-A4XX"/>
26 <value name="ZPASS_DONE" value="21"/>
27 <value name="CACHE_FLUSH_AND_INV_EVENT" value="22" varset="chip" variants="A2XX"/>
28 <value name="RB_DONE_TS" value="22" varset="chip" variants="A3XX-"/>
29 <value name="PERFCOUNTER_START" value="23" varset="chip" variants="A2XX-A4XX"/>
30 <value name="PERFCOUNTER_STOP" value="24" varset="chip" variants="A2XX-A4XX"/>
31 <value name="VS_FETCH_DONE" value="27"/>
32 <value name="FACENESS_FLUSH" value="28" varset="chip" variants="A2XX-A4XX"/>
33
34 <!-- a5xx events -->
35 <value name="WT_DONE_TS" value="8" varset="chip" variants="A5XX-"/>
36 <value name="FLUSH_SO_0" value="17" varset="chip" variants="A5XX-"/>
37 <value name="FLUSH_SO_1" value="18" varset="chip" variants="A5XX-"/>
38 <value name="FLUSH_SO_2" value="19" varset="chip" variants="A5XX-"/>
39 <value name="FLUSH_SO_3" value="20" varset="chip" variants="A5XX-"/>
40 <value name="PC_CCU_INVALIDATE_DEPTH" value="24" varset="chip" variants="A5XX-"/>
41 <value name="PC_CCU_INVALIDATE_COLOR" value="25" varset="chip" variants="A5XX-"/>
42 <value name="PC_CCU_RESOLVE_TS" value="26" varset="chip" variants="A6XX"/>
43 <value name="PC_CCU_FLUSH_DEPTH_TS" value="28" varset="chip" variants="A5XX-"/>
44 <value name="PC_CCU_FLUSH_COLOR_TS" value="29" varset="chip" variants="A5XX-"/>
45 <value name="BLIT" value="30" varset="chip" variants="A5XX-"/>
46 <value name="UNK_25" value="37" varset="chip" variants="A5XX"/>
47 <value name="LRZ_FLUSH" value="38" varset="chip" variants="A5XX-"/>
48 <value name="BLIT_OP_FILL_2D" value="39" varset="chip" variants="A5XX-"/>
49 <value name="BLIT_OP_COPY_2D" value="40" varset="chip" variants="A5XX-"/>
50 <value name="BLIT_OP_SCALE_2D" value="42" varset="chip" variants="A5XX-"/>
51 <value name="CONTEXT_DONE_2D" value="43" varset="chip" variants="A5XX-"/>
52 <value name="UNK_2C" value="44" varset="chip" variants="A5XX-"/>
53 <value name="UNK_2D" value="45" varset="chip" variants="A5XX-"/>
54
55 <!-- a6xx events -->
56 <value name="CACHE_INVALIDATE" value="49" varset="chip" variants="A6XX"/>
57 </enum>
58
59 <enum name="pc_di_primtype">
60 <value name="DI_PT_NONE" value="0"/>
61 <!-- POINTLIST_PSIZE is used on a3xx/a4xx when gl_PointSize is written: -->
62 <value name="DI_PT_POINTLIST_PSIZE" value="1"/>
63 <value name="DI_PT_LINELIST" value="2"/>
64 <value name="DI_PT_LINESTRIP" value="3"/>
65 <value name="DI_PT_TRILIST" value="4"/>
66 <value name="DI_PT_TRIFAN" value="5"/>
67 <value name="DI_PT_TRISTRIP" value="6"/>
68 <value name="DI_PT_LINELOOP" value="7"/> <!-- a22x, a3xx -->
69 <value name="DI_PT_RECTLIST" value="8"/>
70 <value name="DI_PT_POINTLIST" value="9"/>
71 <value name="DI_PT_LINE_ADJ" value="0xa"/>
72 <value name="DI_PT_LINESTRIP_ADJ" value="0xb"/>
73 <value name="DI_PT_TRI_ADJ" value="0xc"/>
74 <value name="DI_PT_TRISTRIP_ADJ" value="0xd"/>
75
76 <value name="DI_PT_PATCHES0" value="0x1f"/>
77 <value name="DI_PT_PATCHES1" value="0x20"/>
78 <value name="DI_PT_PATCHES2" value="0x21"/>
79 <value name="DI_PT_PATCHES3" value="0x22"/>
80 <value name="DI_PT_PATCHES4" value="0x23"/>
81 <value name="DI_PT_PATCHES5" value="0x24"/>
82 <value name="DI_PT_PATCHES6" value="0x25"/>
83 <value name="DI_PT_PATCHES7" value="0x26"/>
84 <value name="DI_PT_PATCHES8" value="0x27"/>
85 <value name="DI_PT_PATCHES9" value="0x28"/>
86 <value name="DI_PT_PATCHES10" value="0x29"/>
87 <value name="DI_PT_PATCHES11" value="0x2a"/>
88 <value name="DI_PT_PATCHES12" value="0x2b"/>
89 <value name="DI_PT_PATCHES13" value="0x2c"/>
90 <value name="DI_PT_PATCHES14" value="0x2d"/>
91 <value name="DI_PT_PATCHES15" value="0x2e"/>
92 <value name="DI_PT_PATCHES16" value="0x2f"/>
93 <value name="DI_PT_PATCHES17" value="0x30"/>
94 <value name="DI_PT_PATCHES18" value="0x31"/>
95 <value name="DI_PT_PATCHES19" value="0x32"/>
96 <value name="DI_PT_PATCHES20" value="0x33"/>
97 <value name="DI_PT_PATCHES21" value="0x34"/>
98 <value name="DI_PT_PATCHES22" value="0x35"/>
99 <value name="DI_PT_PATCHES23" value="0x36"/>
100 <value name="DI_PT_PATCHES24" value="0x37"/>
101 <value name="DI_PT_PATCHES25" value="0x38"/>
102 <value name="DI_PT_PATCHES26" value="0x39"/>
103 <value name="DI_PT_PATCHES27" value="0x3a"/>
104 <value name="DI_PT_PATCHES28" value="0x3b"/>
105 <value name="DI_PT_PATCHES29" value="0x3c"/>
106 <value name="DI_PT_PATCHES30" value="0x3d"/>
107 <value name="DI_PT_PATCHES31" value="0x3e"/>
108 </enum>
109
110 <enum name="pc_di_src_sel">
111 <value name="DI_SRC_SEL_DMA" value="0"/>
112 <value name="DI_SRC_SEL_IMMEDIATE" value="1"/>
113 <value name="DI_SRC_SEL_AUTO_INDEX" value="2"/>
114 <value name="DI_SRC_SEL_AUTO_XFB" value="3"/>
115 </enum>
116
117 <enum name="pc_di_face_cull_sel">
118 <value name="DI_FACE_CULL_NONE" value="0"/>
119 <value name="DI_FACE_CULL_FETCH" value="1"/>
120 <value name="DI_FACE_BACKFACE_CULL" value="2"/>
121 <value name="DI_FACE_FRONTFACE_CULL" value="3"/>
122 </enum>
123
124 <enum name="pc_di_index_size">
125 <value name="INDEX_SIZE_IGN" value="0"/>
126 <value name="INDEX_SIZE_16_BIT" value="0"/>
127 <value name="INDEX_SIZE_32_BIT" value="1"/>
128 <value name="INDEX_SIZE_8_BIT" value="2"/>
129 <value name="INDEX_SIZE_INVALID"/>
130 </enum>
131
132 <enum name="pc_di_vis_cull_mode">
133 <value name="IGNORE_VISIBILITY" value="0"/>
134 <value name="USE_VISIBILITY" value="1"/>
135 </enum>
136
137 <enum name="adreno_pm4_packet_type">
138 <value name="CP_TYPE0_PKT" value="0x00000000"/>
139 <value name="CP_TYPE1_PKT" value="0x40000000"/>
140 <value name="CP_TYPE2_PKT" value="0x80000000"/>
141 <value name="CP_TYPE3_PKT" value="0xc0000000"/>
142 <value name="CP_TYPE4_PKT" value="0x40000000"/>
143 <value name="CP_TYPE7_PKT" value="0x70000000"/>
144 </enum>
145
146 <!--
147 Note that in some cases, the same packet id is recycled on a later
148 generation, so variants attribute is used to distinguish. They
149 may not be completely accurate, we would probably have to analyze
150 the pfp and me/pm4 firmware to verify the packet is actually
151 handled on a particular generation. But it is at least enough to
152 disambiguate the packet-id's that were re-used for different
153 packets starting with a5xx.
154 -->
155 <enum name="adreno_pm4_type3_packets">
156 <doc>initialize CP's micro-engine</doc>
157 <value name="CP_ME_INIT" value="0x48"/>
158 <doc>skip N 32-bit words to get to the next packet</doc>
159 <value name="CP_NOP" value="0x10"/>
160 <doc>
161 indirect buffer dispatch. prefetch parser uses this packet
162 type to determine whether to pre-fetch the IB
163 </doc>
164 <value name="CP_PREEMPT_ENABLE" value="0x1c"/>
165 <value name="CP_PREEMPT_TOKEN" value="0x1e"/>
166 <value name="CP_INDIRECT_BUFFER" value="0x3f"/>
167 <doc>
168 Takes the same arguments as CP_INDIRECT_BUFFER, but jumps to
169 another buffer at the same level. Must be at the end of IB, and
170 doesn't work with draw state IB's.
171 </doc>
172 <value name="CP_INDIRECT_BUFFER_CHAIN" value="0x57" varset="chip" variants="A5XX-"/>
173 <doc>indirect buffer dispatch. same as IB, but init is pipelined</doc>
174 <value name="CP_INDIRECT_BUFFER_PFD" value="0x37"/>
175 <doc>wait for the IDLE state of the engine</doc>
176 <value name="CP_WAIT_FOR_IDLE" value="0x26"/>
177 <doc>wait until a register or memory location is a specific value</doc>
178 <value name="CP_WAIT_REG_MEM" value="0x3c"/>
179 <doc>wait until a register location is equal to a specific value</doc>
180 <value name="CP_WAIT_REG_EQ" value="0x52"/>
181 <doc>wait until a register location is >= a specific value</doc>
182 <value name="CP_WAIT_REG_GTE" value="0x53" varset="chip" variants="A2XX-A4XX"/>
183 <doc>wait until a read completes</doc>
184 <value name="CP_WAIT_UNTIL_READ" value="0x5c" varset="chip" variants="A2XX-A4XX"/>
185 <doc>wait until all base/size writes from an IB_PFD packet have completed</doc>
186 <value name="CP_WAIT_IB_PFD_COMPLETE" value="0x5d"/>
187 <doc>register read/modify/write</doc>
188 <value name="CP_REG_RMW" value="0x21"/>
189 <doc>Set binning configuration registers</doc>
190 <value name="CP_SET_BIN_DATA" value="0x2f" varset="chip" variants="A2XX-A4XX"/>
191 <value name="CP_SET_BIN_DATA5" value="0x2f" varset="chip" variants="A5XX-"/>
192 <doc>reads register in chip and writes to memory</doc>
193 <value name="CP_REG_TO_MEM" value="0x3e"/>
194 <doc>write N 32-bit words to memory</doc>
195 <value name="CP_MEM_WRITE" value="0x3d"/>
196 <doc>write CP_PROG_COUNTER value to memory</doc>
197 <value name="CP_MEM_WRITE_CNTR" value="0x4f"/>
198 <doc>conditional execution of a sequence of packets</doc>
199 <value name="CP_COND_EXEC" value="0x44"/>
200 <doc>conditional write to memory or register</doc>
201 <value name="CP_COND_WRITE" value="0x45" varset="chip" variants="A2XX-A4XX"/>
202 <value name="CP_COND_WRITE5" value="0x45" varset="chip" variants="A5XX-"/>
203 <doc>generate an event that creates a write to memory when completed</doc>
204 <value name="CP_EVENT_WRITE" value="0x46"/>
205 <doc>generate a VS|PS_done event</doc>
206 <value name="CP_EVENT_WRITE_SHD" value="0x58"/>
207 <doc>generate a cache flush done event</doc>
208 <value name="CP_EVENT_WRITE_CFL" value="0x59"/>
209 <doc>generate a z_pass done event</doc>
210 <value name="CP_EVENT_WRITE_ZPD" value="0x5b"/>
211 <doc>
212 not sure the real name, but this seems to be what is used for
213 opencl, instead of CP_DRAW_INDX..
214 </doc>
215 <value name="CP_RUN_OPENCL" value="0x31"/>
216 <doc>initiate fetch of index buffer and draw</doc>
217 <value name="CP_DRAW_INDX" value="0x22"/>
218 <doc>draw using supplied indices in packet</doc>
219 <value name="CP_DRAW_INDX_2" value="0x36" varset="chip" variants="A2XX-A4XX"/> <!-- this is something different on a6xx and unused on a5xx -->
220 <doc>initiate fetch of index buffer and binIDs and draw</doc>
221 <value name="CP_DRAW_INDX_BIN" value="0x34" varset="chip" variants="A2XX-A4XX"/>
222 <doc>initiate fetch of bin IDs and draw using supplied indices</doc>
223 <value name="CP_DRAW_INDX_2_BIN" value="0x35" varset="chip" variants="A2XX-A4XX"/>
224 <doc>begin/end initiator for viz query extent processing</doc>
225 <value name="CP_VIZ_QUERY" value="0x23" varset="chip" variants="A2XX-A4XX"/>
226 <doc>fetch state sub-blocks and initiate shader code DMAs</doc>
227 <value name="CP_SET_STATE" value="0x25"/>
228 <doc>load constant into chip and to memory</doc>
229 <value name="CP_SET_CONSTANT" value="0x2d"/>
230 <doc>load sequencer instruction memory (pointer-based)</doc>
231 <value name="CP_IM_LOAD" value="0x27"/>
232 <doc>load sequencer instruction memory (code embedded in packet)</doc>
233 <value name="CP_IM_LOAD_IMMEDIATE" value="0x2b"/>
234 <doc>load constants from a location in memory</doc>
235 <value name="CP_LOAD_CONSTANT_CONTEXT" value="0x2e" varset="chip" variants="A2XX"/>
236 <doc>selective invalidation of state pointers</doc>
237 <value name="CP_INVALIDATE_STATE" value="0x3b"/>
238 <doc>dynamically changes shader instruction memory partition</doc>
239 <value name="CP_SET_SHADER_BASES" value="0x4a" varset="chip" variants="A2XX-A4XX"/>
240 <doc>sets the 64-bit BIN_MASK register in the PFP</doc>
241 <value name="CP_SET_BIN_MASK" value="0x50" varset="chip" variants="A2XX-A4XX"/>
242 <doc>sets the 64-bit BIN_SELECT register in the PFP</doc>
243 <value name="CP_SET_BIN_SELECT" value="0x51"/>
244 <doc>updates the current context, if needed</doc>
245 <value name="CP_CONTEXT_UPDATE" value="0x5e"/>
246 <doc>generate interrupt from the command stream</doc>
247 <value name="CP_INTERRUPT" value="0x40"/>
248 <doc>copy sequencer instruction memory to system memory</doc>
249 <value name="CP_IM_STORE" value="0x2c" varset="chip" variants="A2XX"/>
250
251 <!-- For a20x -->
252 <!-- TODO handle variants..
253 <doc>
254 Program an offset that will added to the BIN_BASE value of
255 the 3D_DRAW_INDX_BIN packet
256 </doc>
257 <value name="CP_SET_BIN_BASE_OFFSET" value="0x4b"/>
258 -->
259
260 <!-- for a22x -->
261 <doc>
262 sets draw initiator flags register in PFP, gets bitwise-ORed into
263 every draw initiator
264 </doc>
265 <value name="CP_SET_DRAW_INIT_FLAGS" value="0x4b"/>
266 <doc>sets the register protection mode</doc>
267 <value name="CP_SET_PROTECTED_MODE" value="0x5f"/>
268
269 <value name="CP_BOOTSTRAP_UCODE" value="0x6f"/>
270
271 <!-- for a3xx -->
272 <doc>load high level sequencer command</doc>
273 <value name="CP_LOAD_STATE" value="0x30" varset="chip" variants="A3XX"/>
274 <value name="CP_LOAD_STATE4" value="0x30" varset="chip" variants="A4XX-A5XX"/>
275 <doc>Conditionally load a IB based on a flag, prefetch enabled</doc>
276 <value name="CP_COND_INDIRECT_BUFFER_PFE" value="0x3a"/>
277 <doc>Conditionally load a IB based on a flag, prefetch disabled</doc>
278 <value name="CP_COND_INDIRECT_BUFFER_PFD" value="0x32" varset="chip" variants="A3XX"/>
279 <doc>Load a buffer with pre-fetch enabled</doc>
280 <value name="CP_INDIRECT_BUFFER_PFE" value="0x3f" varset="chip" variants="A5XX"/>
281 <doc>Set bin (?)</doc>
282 <value name="CP_SET_BIN" value="0x4c" varset="chip" variants="A2XX"/>
283
284 <doc>test 2 memory locations to dword values specified</doc>
285 <value name="CP_TEST_TWO_MEMS" value="0x71"/>
286
287 <doc>Write register, ignoring context state for context sensitive registers</doc>
288 <value name="CP_REG_WR_NO_CTXT" value="0x78"/>
289
290 <doc>Record the real-time when this packet is processed by PFP</doc>
291 <value name="CP_RECORD_PFP_TIMESTAMP" value="0x11"/>
292
293 <!-- Used to switch GPU between secure and non-secure modes -->
294 <value name="CP_SET_SECURE_MODE" value="0x66"/>
295
296 <doc>PFP waits until the FIFO between the PFP and the ME is empty</doc>
297 <value name="CP_WAIT_FOR_ME" value="0x13"/>
298
299 <!-- for a4xx -->
300 <doc>
301 Used a bit like CP_SET_CONSTANT on a2xx, but can write multiple
302 groups of registers. Looks like it can be used to create state
303 objects in GPU memory, and on state change only emit pointer
304 (via CP_SET_DRAW_STATE), which should be nice for reducing CPU
305 overhead:
306
307 (A4x) save PM4 stream pointers to execute upon a visible draw
308 </doc>
309 <value name="CP_SET_DRAW_STATE" value="0x43" varset="chip" variants="A4XX-"/>
310 <value name="CP_DRAW_INDX_OFFSET" value="0x38"/>
311 <value name="CP_DRAW_INDIRECT" value="0x28" varset="chip" variants="A4XX-"/>
312 <value name="CP_DRAW_INDX_INDIRECT" value="0x29" varset="chip" variants="A4XX-"/>
313 <value name="CP_DRAW_INDIRECT_MULTI" value="0x2a" varset="chip" variants="A6XX"/>
314 <value name="CP_DRAW_AUTO" value="0x24"/>
315
316 <doc>
317 Enable or disable predication globally. Also resets the
318 predicate to "passing" and the local bit to enabled when
319 enabling global predication.
320 </doc>
321 <value name="CP_DRAW_PRED_ENABLE_GLOBAL" value="0x19"/>
322
323 <doc>
324 Enable or disable predication locally. Unlike globally enabling
325 predication, this packet doesn't touch any other state.
326 Predication only happens when enabled globally and locally and a
327 predicate has been set. This should be used for internal draws
328 which aren't supposed to use the predication state:
329
330 CP_DRAW_PRED_ENABLE_LOCAL(0)
331 ... do draw...
332 CP_DRAW_PRED_ENABLE_LOCAL(1)
333 </doc>
334 <value name="CP_DRAW_PRED_ENABLE_LOCAL" value="0x1a"/>
335
336 <doc>
337 Latch a draw predicate into the internal register.
338 </doc>
339 <value name="CP_DRAW_PRED_SET" value="0x4e"/>
340
341 <doc>
342 for A4xx
343 Write to register with address that does not fit into type-0 pkt
344 </doc>
345 <value name="CP_WIDE_REG_WRITE" value="0x74" varset="chip" variants="A4XX"/>
346
347 <doc>copy from ME scratch RAM to a register</doc>
348 <value name="CP_SCRATCH_TO_REG" value="0x4d"/>
349
350 <doc>Copy from REG to ME scratch RAM</doc>
351 <value name="CP_REG_TO_SCRATCH" value="0x4a"/>
352
353 <doc>Wait for memory writes to complete</doc>
354 <value name="CP_WAIT_MEM_WRITES" value="0x12"/>
355
356 <doc>Conditional execution based on register comparison</doc>
357 <value name="CP_COND_REG_EXEC" value="0x47"/>
358
359 <doc>Memory to REG copy</doc>
360 <value name="CP_MEM_TO_REG" value="0x42"/>
361
362 <value name="CP_EXEC_CS_INDIRECT" value="0x41" varset="chip" variants="A4XX-"/>
363 <value name="CP_EXEC_CS" value="0x33"/>
364
365 <doc>
366 for a5xx
367 </doc>
368 <value name="CP_PERFCOUNTER_ACTION" value="0x50" varset="chip" variants="A5XX"/>
369 <!-- switches SMMU pagetable, used on a5xx+ only -->
370 <value name="CP_SMMU_TABLE_UPDATE" value="0x53" varset="chip" variants="A5XX-"/>
371 <!-- for a6xx -->
372 <doc>Tells CP the current mode of GPU operation</doc>
373 <value name="CP_SET_MARKER" value="0x65" varset="chip" variants="A6XX"/>
374 <doc>Instruct CP to set a few internal CP registers</doc>
375 <value name="CP_SET_PSEUDO_REG" value="0x56" varset="chip" variants="A6XX"/>
376 <!--
377 pairs of regid and value.. seems to be used to program some TF
378 related regs:
379 -->
380 <value name="CP_CONTEXT_REG_BUNCH" value="0x5c" varset="chip" variants="A5XX-"/>
381 <!-- A5XX Enable yield in RB only -->
382 <value name="CP_YIELD_ENABLE" value="0x1c" varset="chip" variants="A5XX"/>
383 <value name="CP_SKIP_IB2_ENABLE_GLOBAL" value="0x1d" varset="chip" variants="A5XX-"/>
384 <value name="CP_SKIP_IB2_ENABLE_LOCAL" value="0x23" varset="chip" variants="A5XX-"/>
385 <value name="CP_SET_SUBDRAW_SIZE" value="0x35" varset="chip" variants="A5XX-"/>
386 <value name="CP_SET_VISIBILITY_OVERRIDE" value="0x64" varset="chip" variants="A5XX-"/>
387 <!-- Enable/Disable/Defer A5x global preemption model -->
388 <value name="CP_PREEMPT_ENABLE_GLOBAL" value="0x69" varset="chip" variants="A5XX"/>
389 <!-- Enable/Disable A5x local preemption model -->
390 <value name="CP_PREEMPT_ENABLE_LOCAL" value="0x6a" varset="chip" variants="A5XX"/>
391 <!-- Yield token on a5xx similar to CP_PREEMPT on a4xx -->
392 <value name="CP_CONTEXT_SWITCH_YIELD" value="0x6b" varset="chip" variants="A5XX"/>
393 <!-- Inform CP about current render mode (needed for a5xx preemption) -->
394 <value name="CP_SET_RENDER_MODE" value="0x6c" varset="chip" variants="A5XX"/>
395 <value name="CP_COMPUTE_CHECKPOINT" value="0x6e" varset="chip" variants="A5XX"/>
396 <!-- check if this works on earlier.. -->
397 <value name="CP_MEM_TO_MEM" value="0x73" varset="chip" variants="A5XX-"/>
398 <value name="CP_BLIT" value="0x2c" varset="chip" variants="A5XX-"/>
399
400 <!-- Test specified bit in specified register and set predicate -->
401 <value name="CP_REG_TEST" value="0x39" varset="chip" variants="A5XX-"/>
402
403 <!--
404 Seems to set the mode flags which control which CP_SET_DRAW_STATE
405 packets are executed, based on their ENABLE_MASK values
406
407 CP_SET_MODE w/ payload of 0x1 seems to cause CP_SET_DRAW_STATE
408 packets w/ ENABLE_MASK & 0x6 to execute immediately
409 -->
410 <value name="CP_SET_MODE" value="0x63" varset="chip" variants="A6XX"/>
411
412 <!--
413 Seems like there are now separate blocks of state for VS vs FS/CS
414 (probably these amounts to geometry vs fragments so that geometry
415 stage of the pipeline for next draw can start while fragment stage
416 of current draw is still running. The format of the payload of the
417 packets is the same, the only difference is the offsets of the regs
418 the firmware code that handles the packet writes.
419
420 Note that for CL, starting with a6xx, the preferred # of local
421 threads is no longer the same as the max, implying that the shader
422 core can now run warps from unrelated shaders (ie.
423 CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE vs
424 CL_KERNEL_WORK_GROUP_SIZE)
425 -->
426 <value name="CP_LOAD_STATE6_GEOM" value="0x32" varset="chip" variants="A6XX"/>
427 <value name="CP_LOAD_STATE6_FRAG" value="0x34" varset="chip" variants="A6XX"/>
428 <!--
429 Note: For IBO state (Image/SSBOs) which have shared state across
430 shader stages, for 3d pipeline CP_LOAD_STATE6 is used. But for
431 compute shaders, CP_LOAD_STATE6_FRAG is used. Possibly they are
432 interchangable.
433 -->
434 <value name="CP_LOAD_STATE6" value="0x36" varset="chip" variants="A6XX"/>
435
436 <!-- internal packets: -->
437 <value name="IN_IB_PREFETCH_END" value="0x17" varset="chip" variants="A2XX"/>
438 <value name="IN_SUBBLK_PREFETCH" value="0x1f" varset="chip" variants="A2XX"/>
439 <value name="IN_INSTR_PREFETCH" value="0x20" varset="chip" variants="A2XX"/>
440 <value name="IN_INSTR_MATCH" value="0x47" varset="chip" variants="A2XX"/>
441 <value name="IN_CONST_PREFETCH" value="0x49" varset="chip" variants="A2XX"/>
442 <value name="IN_INCR_UPDT_STATE" value="0x55" varset="chip" variants="A2XX"/>
443 <value name="IN_INCR_UPDT_CONST" value="0x56" varset="chip" variants="A2XX"/>
444 <value name="IN_INCR_UPDT_INSTR" value="0x57" varset="chip" variants="A2XX"/>
445
446 <!-- jmptable entry used to handle type4 packet on a5xx+: -->
447 <value name="PKT4" value="0x04" varset="chip" variants="A5XX-"/>
448
449 <!-- TODO do these exist on A5xx? -->
450 <value name="CP_SCRATCH_WRITE" value="0x4c" varset="chip" variants="A6XX"/>
451 <value name="CP_REG_TO_MEM_OFFSET_MEM" value="0x74" varset="chip" variants="A6XX"/>
452 <value name="CP_REG_TO_MEM_OFFSET_REG" value="0x72" varset="chip" variants="A6XX"/>
453 <value name="CP_WAIT_MEM_GTE" value="0x14" varset="chip" variants="A6XX"/>
454 <value name="CP_WAIT_TWO_REGS" value="0x70" varset="chip" variants="A6XX"/>
455 <value name="CP_MEMCPY" value="0x75" varset="chip" variants="A6XX"/>
456 <value name="CP_SET_BIN_DATA5_OFFSET" value="0x2e" varset="chip" variants="A6XX"/>
457 <value name="CP_SET_CTXSWITCH_IB" value="0x55" varset="chip" variants="A6XX"/>
458
459 <!--
460 Seems to always have the payload:
461 00000002 00008801 00004010
462 or:
463 00000002 00008801 00004090
464 or:
465 00000002 00008801 00000010
466 00000002 00008801 00010010
467 00000002 00008801 00d64010
468 ...
469 Note set for compute shaders..
470 Is 0x8801 a register offset?
471 This appears to be a special sort of register write packet
472 more or less, but the firmware has some special handling..
473 Seems like it intercepts/modifies certain register offsets,
474 but others are treated like a normal PKT4 reg write. I
475 guess there are some registers that the fw controls certain
476 bits.
477 -->
478 <value name="CP_REG_WRITE" value="0x6d" varset="chip" variants="A6XX"/>
479
480 </enum>
481
482
483 <domain name="CP_LOAD_STATE" width="32">
484 <doc>Load state, a3xx (and later?)</doc>
485 <enum name="adreno_state_block">
486 <value name="SB_VERT_TEX" value="0"/>
487 <value name="SB_VERT_MIPADDR" value="1"/>
488 <value name="SB_FRAG_TEX" value="2"/>
489 <value name="SB_FRAG_MIPADDR" value="3"/>
490 <value name="SB_VERT_SHADER" value="4"/>
491 <value name="SB_GEOM_SHADER" value="5"/>
492 <value name="SB_FRAG_SHADER" value="6"/>
493 <value name="SB_COMPUTE_SHADER" value="7"/>
494 </enum>
495 <enum name="adreno_state_type">
496 <value name="ST_SHADER" value="0"/>
497 <value name="ST_CONSTANTS" value="1"/>
498 </enum>
499 <enum name="adreno_state_src">
500 <value name="SS_DIRECT" value="0">
501 <doc>inline with the CP_LOAD_STATE packet</doc>
502 </value>
503 <value name="SS_INVALID_ALL_IC" value="2"/>
504 <value name="SS_INVALID_PART_IC" value="3"/>
505 <value name="SS_INDIRECT" value="4">
506 <doc>in buffer pointed to by EXT_SRC_ADDR</doc>
507 </value>
508 <value name="SS_INDIRECT_TCM" value="5"/>
509 <value name="SS_INDIRECT_STM" value="6"/>
510 </enum>
511 <reg32 offset="0" name="0">
512 <bitfield name="DST_OFF" low="0" high="15" type="uint"/>
513 <bitfield name="STATE_SRC" low="16" high="18" type="adreno_state_src"/>
514 <bitfield name="STATE_BLOCK" low="19" high="21" type="adreno_state_block"/>
515 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
516 </reg32>
517 <reg32 offset="1" name="1">
518 <bitfield name="STATE_TYPE" low="0" high="1" type="adreno_state_type"/>
519 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
520 </reg32>
521 </domain>
522
523 <domain name="CP_LOAD_STATE4" width="32" varset="chip">
524 <doc>Load state, a4xx+</doc>
525 <enum name="a4xx_state_block">
526 <!--
527 unknown: 0x7 and 0xf <- seen in compute shader
528
529 STATE_BLOCK = 0x6, STATE_TYPE = 0x2 possibly used for preemption?
530 Seen in some GL shaders. Payload is NUM_UNIT dwords, and it contains
531 the gpuaddr of the following shader constants block. DST_OFF seems
532 to specify which shader stage:
533
534 16 -> vert
535 36 -> tcs
536 56 -> tes
537 76 -> geom
538 96 -> frag
539
540 Example:
541
542 opcode: CP_LOAD_STATE4 (30) (12 dwords)
543 { DST_OFF = 16 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = 0x6 | NUM_UNIT = 4 }
544 { STATE_TYPE = 0x2 | EXT_SRC_ADDR = 0 }
545 { EXT_SRC_ADDR_HI = 0 }
546 0000: c0264100 00000000 00000000 00000000
547 0000: 70b0000b 01180010 00000002 00000000 c0264100 00000000 00000000 00000000
548
549 opcode: CP_LOAD_STATE4 (30) (4 dwords)
550 { DST_OFF = 16 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
551 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0xc0264100 }
552 { EXT_SRC_ADDR_HI = 0 }
553 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000
554 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000
555 0000: 00000040 0000000c 00000000 00000000 00000000 00000000 00000000 00000000
556
557 STATE_BLOCK = 0x6, STATE_TYPE = 0x1, seen in compute shader. NUM_UNITS * 2 dwords.
558
559 -->
560 <value name="SB4_VS_TEX" value="0x0"/>
561 <value name="SB4_HS_TEX" value="0x1"/> <!-- aka. TCS -->
562 <value name="SB4_DS_TEX" value="0x2"/> <!-- aka. TES -->
563 <value name="SB4_GS_TEX" value="0x3"/>
564 <value name="SB4_FS_TEX" value="0x4"/>
565 <value name="SB4_CS_TEX" value="0x5"/>
566 <value name="SB4_VS_SHADER" value="0x8"/>
567 <value name="SB4_HS_SHADER" value="0x9"/>
568 <value name="SB4_DS_SHADER" value="0xa"/>
569 <value name="SB4_GS_SHADER" value="0xb"/>
570 <value name="SB4_FS_SHADER" value="0xc"/>
571 <value name="SB4_CS_SHADER" value="0xd"/>
572 <!--
573 for SSBO, STATE_TYPE=0 appears to be addresses (four dwords each),
574 STATE_TYPE=1 sizes, STATE_TYPE=2 addresses again (two dwords each)
575
576 Compute has it's own dedicated SSBO state, it seems, but the rest
577 of the stages share state
578 -->
579 <value name="SB4_SSBO" value="0xe"/>
580 <value name="SB4_CS_SSBO" value="0xf"/>
581 </enum>
582 <enum name="a4xx_state_type">
583 <value name="ST4_SHADER" value="0"/>
584 <value name="ST4_CONSTANTS" value="1"/>
585 <value name="ST4_UBO" value="2"/>
586 </enum>
587 <enum name="a4xx_state_src">
588 <value name="SS4_DIRECT" value="0"/>
589 <value name="SS4_INDIRECT" value="2"/>
590 </enum>
591 <reg32 offset="0" name="0">
592 <bitfield name="DST_OFF" low="0" high="13" type="uint"/>
593 <bitfield name="STATE_SRC" low="16" high="17" type="a4xx_state_src"/>
594 <bitfield name="STATE_BLOCK" low="18" high="21" type="a4xx_state_block"/>
595 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
596 </reg32>
597 <reg32 offset="1" name="1">
598 <bitfield name="STATE_TYPE" low="0" high="1" type="a4xx_state_type"/>
599 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
600 </reg32>
601 <reg32 offset="2" name="2" varset="chip" variants="A5XX-">
602 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
603 </reg32>
604 </domain>
605
606 <!-- looks basically same CP_LOAD_STATE4 -->
607 <domain name="CP_LOAD_STATE6" width="32" varset="chip">
608 <doc>Load state, a6xx+</doc>
609 <enum name="a6xx_state_block">
610 <value name="SB6_VS_TEX" value="0x0"/>
611 <value name="SB6_HS_TEX" value="0x1"/> <!-- aka. TCS -->
612 <value name="SB6_DS_TEX" value="0x2"/> <!-- aka. TES -->
613 <value name="SB6_GS_TEX" value="0x3"/>
614 <value name="SB6_FS_TEX" value="0x4"/>
615 <value name="SB6_CS_TEX" value="0x5"/>
616 <value name="SB6_VS_SHADER" value="0x8"/>
617 <value name="SB6_HS_SHADER" value="0x9"/>
618 <value name="SB6_DS_SHADER" value="0xa"/>
619 <value name="SB6_GS_SHADER" value="0xb"/>
620 <value name="SB6_FS_SHADER" value="0xc"/>
621 <value name="SB6_CS_SHADER" value="0xd"/>
622 <value name="SB6_IBO" value="0xe"/>
623 <value name="SB6_CS_IBO" value="0xf"/>
624 </enum>
625 <enum name="a6xx_state_type">
626 <value name="ST6_SHADER" value="0"/>
627 <value name="ST6_CONSTANTS" value="1"/>
628 <value name="ST6_UBO" value="2"/>
629 <value name="ST6_IBO" value="3"/>
630 </enum>
631 <enum name="a6xx_state_src">
632 <value name="SS6_DIRECT" value="0"/>
633 <value name="SS6_BINDLESS" value="1"/> <!-- TODO does this exist on a4xx/a5xx? -->
634 <value name="SS6_INDIRECT" value="2"/>
635 <doc>
636 SS6_UBO used by the a6xx vulkan blob with tesselation constants
637 in this case, EXT_SRC_ADDR is (ubo_id shl 16 | offset)
638 to load constants from a UBO loaded with DST_OFF = 14 and offset 0,
639 EXT_SRC_ADDR = 0xe0000
640 (offset is a guess, should be in bytes given that maxUniformBufferRange=64k)
641 </doc>
642 <value name="SS6_UBO" value="3"/>
643 </enum>
644 <reg32 offset="0" name="0">
645 <bitfield name="DST_OFF" low="0" high="13" type="uint"/>
646 <bitfield name="STATE_TYPE" low="14" high="15" type="a6xx_state_type"/>
647 <bitfield name="STATE_SRC" low="16" high="17" type="a6xx_state_src"/>
648 <bitfield name="STATE_BLOCK" low="18" high="21" type="a6xx_state_block"/>
649 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
650 </reg32>
651 <reg32 offset="1" name="1">
652 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
653 </reg32>
654 <reg32 offset="2" name="2">
655 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
656 </reg32>
657 <reg64 offset="1" name="EXT_SRC_ADDR" type="address"/>
658 </domain>
659
660 <bitset name="vgt_draw_initiator" inline="yes">
661 <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
662 <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
663 <bitfield name="VIS_CULL" low="9" high="10" type="pc_di_vis_cull_mode"/>
664 <bitfield name="INDEX_SIZE" pos="11" type="pc_di_index_size"/>
665 <bitfield name="NOT_EOP" pos="12" type="boolean"/>
666 <bitfield name="SMALL_INDEX" pos="13" type="boolean"/>
667 <bitfield name="PRE_DRAW_INITIATOR_ENABLE" pos="14" type="boolean"/>
668 <bitfield name="NUM_INSTANCES" low="24" high="31" type="uint"/>
669 </bitset>
670
671 <!-- changed on a4xx: -->
672 <enum name="a4xx_index_size">
673 <value name="INDEX4_SIZE_8_BIT" value="0"/>
674 <value name="INDEX4_SIZE_16_BIT" value="1"/>
675 <value name="INDEX4_SIZE_32_BIT" value="2"/>
676 </enum>
677
678 <enum name="a6xx_patch_type">
679 <value name="TESS_QUADS" value="0"/>
680 <value name="TESS_TRIANGLES" value="1"/>
681 <value name="TESS_ISOLINES" value="2"/>
682 </enum>
683
684 <bitset name="vgt_draw_initiator_a4xx" inline="yes">
685 <!-- When the 0x20 bit is set, it's the number of patch vertices - 1 -->
686 <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
687 <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
688 <bitfield name="VIS_CULL" low="8" high="9" type="pc_di_vis_cull_mode"/>
689 <bitfield name="INDEX_SIZE" low="10" high="11" type="a4xx_index_size"/>
690 <bitfield name="PATCH_TYPE" low="12" high="13" type="a6xx_patch_type"/>
691 <bitfield name="GS_ENABLE" pos="16" type="boolean"/>
692 <bitfield name="TESS_ENABLE" pos="17" type="boolean"/>
693 </bitset>
694
695 <domain name="CP_DRAW_INDX" width="32">
696 <reg32 offset="0" name="0">
697 <bitfield name="VIZ_QUERY" low="0" high="31"/>
698 </reg32>
699 <reg32 offset="1" name="1" type="vgt_draw_initiator"/>
700 <reg32 offset="2" name="2">
701 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
702 </reg32>
703 <reg32 offset="3" name="3">
704 <bitfield name="INDX_BASE" low="0" high="31"/>
705 </reg32>
706 <reg32 offset="4" name="4">
707 <bitfield name="INDX_SIZE" low="0" high="31"/>
708 </reg32>
709 </domain>
710
711 <domain name="CP_DRAW_INDX_2" width="32">
712 <reg32 offset="0" name="0">
713 <bitfield name="VIZ_QUERY" low="0" high="31"/>
714 </reg32>
715 <reg32 offset="1" name="1" type="vgt_draw_initiator"/>
716 <reg32 offset="2" name="2">
717 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
718 </reg32>
719 <!-- followed by NUM_INDICES indices.. -->
720 </domain>
721
722 <domain name="CP_DRAW_INDX_OFFSET" width="32">
723 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
724 <reg32 offset="1" name="1">
725 <bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/>
726 </reg32>
727 <reg32 offset="2" name="2">
728 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
729 </reg32>
730 <reg32 offset="3" name="3">
731 <bitfield name="FIRST_INDX" low="0" high="31"/>
732 </reg32>
733
734 <stripe varset="chip" variants="A5XX-">
735 <reg32 offset="4" name="4">
736 <bitfield name="INDX_BASE_LO" low="0" high="31"/>
737 </reg32>
738 <reg32 offset="5" name="5">
739 <bitfield name="INDX_BASE_HI" low="0" high="31"/>
740 </reg32>
741 <reg64 offset="4" name="INDX_BASE" type="address"/>
742 <reg32 offset="6" name="6">
743 <!-- max # of elements in index buffer -->
744 <bitfield name="MAX_INDICES" low="0" high="31"/>
745 </reg32>
746 </stripe>
747
748 <reg32 offset="4" name="4">
749 <bitfield name="INDX_BASE" low="0" high="31" type="address"/>
750 </reg32>
751
752 <reg32 offset="5" name="5">
753 <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/>
754 </reg32>
755 </domain>
756
757 <domain name="CP_DRAW_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
758 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
759 <stripe varset="chip" variants="A4XX">
760 <reg32 offset="1" name="1">
761 <bitfield name="INDIRECT" low="0" high="31"/>
762 </reg32>
763 </stripe>
764 <stripe varset="chip" variants="A5XX-">
765 <reg32 offset="1" name="1">
766 <bitfield name="INDIRECT_LO" low="0" high="31"/>
767 </reg32>
768 <reg32 offset="2" name="2">
769 <bitfield name="INDIRECT_HI" low="0" high="31"/>
770 </reg32>
771 <reg64 offset="1" name="INDIRECT" type="address"/>
772 </stripe>
773 </domain>
774
775 <domain name="CP_DRAW_INDX_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
776 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
777 <stripe varset="chip" variants="A4XX">
778 <reg32 offset="1" name="1">
779 <bitfield name="INDX_BASE" low="0" high="31"/>
780 </reg32>
781 <reg32 offset="2" name="2">
782 <!-- max # of bytes in index buffer -->
783 <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/>
784 </reg32>
785 <reg32 offset="3" name="3">
786 <bitfield name="INDIRECT" low="0" high="31"/>
787 </reg32>
788 </stripe>
789 <stripe varset="chip" variants="A5XX-">
790 <reg32 offset="1" name="1">
791 <bitfield name="INDX_BASE_LO" low="0" high="31"/>
792 </reg32>
793 <reg32 offset="2" name="2">
794 <bitfield name="INDX_BASE_HI" low="0" high="31"/>
795 </reg32>
796 <reg64 offset="1" name="INDX_BASE" type="address"/>
797 <reg32 offset="3" name="3">
798 <!-- max # of elements in index buffer -->
799 <bitfield name="MAX_INDICES" low="0" high="31" type="uint"/>
800 </reg32>
801 <reg32 offset="4" name="4">
802 <bitfield name="INDIRECT_LO" low="0" high="31"/>
803 </reg32>
804 <reg32 offset="5" name="5">
805 <bitfield name="INDIRECT_HI" low="0" high="31"/>
806 </reg32>
807 <reg64 offset="4" name="INDIRECT" type="address"/>
808 </stripe>
809 </domain>
810
811 <domain name="CP_DRAW_INDIRECT_MULTI" width="32" varset="chip" prefix="chip" variants="A6XX-">
812 <enum name="a6xx_draw_indirect_opcode">
813 <value name="INDIRECT_OP_NORMAL" value="0x2"/>
814 <value name="INDIRECT_OP_INDEXED" value="0x4"/>
815 <value name="INDIRECT_OP_INDIRECT_COUNT" value="0x6"/>
816 <value name="INDIRECT_OP_INDIRECT_COUNT_INDEXED" value="0x7"/>
817 </enum>
818 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
819 <reg32 offset="1" name="1">
820 <bitfield name="OPCODE" low="0" high="3" type="a6xx_draw_indirect_opcode" addvariant="yes"/>
821 <doc>
822 DST_OFF same as in CP_LOAD_STATE6 - vec4 VS const at this offset will
823 be updated for each draw to {draw_id, first_vertex, first_instance, 0}
824 value of 0 disables it
825 </doc>
826 <bitfield name="DST_OFF" low="8" high="21" type="hex"/>
827 </reg32>
828 <reg32 offset="2" name="DRAW_COUNT" type="uint"/>
829 <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_NORMAL">
830 <reg64 offset="3" name="INDIRECT" type="address"/>
831 <reg32 offset="5" name="STRIDE" type="uint"/>
832 </stripe>
833 <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_INDEXED">
834 <reg64 offset="3" name="INDEX" type="address"/>
835 <reg32 offset="5" name="MAX_INDICES" type="uint"/>
836 <reg64 offset="6" name="INDIRECT" type="address"/>
837 <reg32 offset="8" name="STRIDE" type="uint"/>
838 </stripe>
839 <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_INDIRECT_COUNT">
840 <reg64 offset="3" name="INDIRECT" type="address"/>
841 <reg64 offset="5" name="INDIRECT_COUNT" type="address"/>
842 <reg32 offset="7" name="STRIDE" type="uint"/>
843 </stripe>
844 <stripe varset="a6xx_draw_indirect_opcode" variants="INDIRECT_OP_INDIRECT_COUNT_INDEXED">
845 <reg64 offset="3" name="INDEX" type="address"/>
846 <reg32 offset="5" name="MAX_INDICES" type="uint"/>
847 <reg64 offset="6" name="INDIRECT" type="address"/>
848 <reg64 offset="8" name="INDIRECT_COUNT" type="address"/>
849 <reg32 offset="10" name="STRIDE" type="uint"/>
850 </stripe>
851 </domain>
852
853 <domain name="CP_DRAW_PRED_ENABLE_GLOBAL" width="32" varset="chip">
854 <reg32 offset="0" name="0">
855 <bitfield name="ENABLE" pos="0" type="boolean"/>
856 </reg32>
857 </domain>
858
859 <domain name="CP_DRAW_PRED_ENABLE_LOCAL" width="32" varset="chip">
860 <reg32 offset="0" name="0">
861 <bitfield name="ENABLE" pos="0" type="boolean"/>
862 </reg32>
863 </domain>
864
865 <domain name="CP_DRAW_PRED_SET" width="32" varset="chip">
866 <enum name="cp_draw_pred_src">
867 <!--
868 Sources 1-4 seem to be about combining reading
869 SO/primitive queries and setting the predicate, which is
870 a DX11-specific optimization (since in DX11 you can only
871 predicate on the result of queries).
872 -->
873 <value name="PRED_SRC_MEM" value="5">
874 <doc>
875 Read a 64-bit value at the given address and
876 test if it equals/doesn't equal 0.
877 </doc>
878 </value>
879 </enum>
880 <enum name="cp_draw_pred_test">
881 <value name="NE_0_PASS" value="0"/>
882 <value name="EQ_0_PASS" value="1"/>
883 </enum>
884 <reg32 offset="0" name="0">
885 <bitfield name="SRC" low="4" high="7" type="cp_draw_pred_src"/>
886 <bitfield name="TEST" pos="8" type="cp_draw_pred_test"/>
887 </reg32>
888 <reg64 offset="1" name="MEM_ADDR" type="address"/>
889 </domain>
890
891 <domain name="CP_SET_DRAW_STATE" width="32" varset="chip" variants="A4XX-">
892 <array offset="0" stride="3" length="100">
893 <reg32 offset="0" name="0">
894 <bitfield name="COUNT" low="0" high="15" type="uint"/>
895 <bitfield name="DIRTY" pos="16" type="boolean"/>
896 <bitfield name="DISABLE" pos="17" type="boolean"/>
897 <bitfield name="DISABLE_ALL_GROUPS" pos="18" type="boolean"/>
898 <bitfield name="LOAD_IMMED" pos="19" type="boolean"/>
899 <bitfield name="BINNING" pos="20" varset="chip" variants="A6XX-" type="boolean"/>
900 <bitfield name="GMEM" pos="21" varset="chip" variants="A6XX-" type="boolean"/>
901 <bitfield name="SYSMEM" pos="22" varset="chip" variants="A6XX-" type="boolean"/>
902 <bitfield name="GROUP_ID" low="24" high="28" type="uint"/>
903 </reg32>
904 <reg32 offset="1" name="1">
905 <bitfield name="ADDR_LO" low="0" high="31" type="hex"/>
906 </reg32>
907 <reg32 offset="2" name="2" varset="chip" variants="A5XX-">
908 <bitfield name="ADDR_HI" low="0" high="31" type="hex"/>
909 </reg32>
910 </array>
911 </domain>
912
913 <domain name="CP_SET_BIN" width="32">
914 <doc>value at offset 0 always seems to be 0x00000000..</doc>
915 <reg32 offset="0" name="0"/>
916 <reg32 offset="1" name="1">
917 <bitfield name="X1" low="0" high="15" type="uint"/>
918 <bitfield name="Y1" low="16" high="31" type="uint"/>
919 </reg32>
920 <reg32 offset="2" name="2">
921 <bitfield name="X2" low="0" high="15" type="uint"/>
922 <bitfield name="Y2" low="16" high="31" type="uint"/>
923 </reg32>
924 </domain>
925
926 <domain name="CP_SET_BIN_DATA" width="32">
927 <reg32 offset="0" name="0">
928 <!-- corresponds to VSC_PIPE[n].DATA_ADDR -->
929 <bitfield name="BIN_DATA_ADDR" low="0" high="31" type="hex"/>
930 </reg32>
931 <reg32 offset="1" name="1">
932 <!-- seesm to correspond to VSC_SIZE_ADDRESS -->
933 <bitfield name="BIN_SIZE_ADDRESS" low="0" high="31"/>
934 </reg32>
935 </domain>
936
937 <domain name="CP_SET_BIN_DATA5" width="32">
938 <reg32 offset="0" name="0">
939 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
940 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
941 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
942 <bitfield name="VSC_N" low="22" high="26" type="uint"/>
943 </reg32>
944 <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
945 <reg32 offset="1" name="1">
946 <bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/>
947 </reg32>
948 <reg32 offset="2" name="2">
949 <bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/>
950 </reg32>
951 <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
952 <reg32 offset="3" name="3">
953 <bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/>
954 </reg32>
955 <reg32 offset="4" name="4">
956 <bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/>
957 </reg32>
958 <!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: -->
959 <reg32 offset="5" name="5">
960 <bitfield name="BIN_PRIM_STRM_LO" low="0" high="31"/>
961 </reg32>
962 <reg32 offset="6" name="6">
963 <bitfield name="BIN_PRIM_STRM_HI" low="0" high="31"/>
964 </reg32>
965 </domain>
966
967 <domain name="CP_SET_BIN_DATA5_OFFSET" width="32">
968 <doc>
969 Like CP_SET_BIN_DATA5, but set the pointers as offsets from the
970 pointers stored in VSC_PIPE_{DATA,DATA2,SIZE}_ADDRESS. Useful
971 for Vulkan where these values aren't known when the command
972 stream is recorded.
973 </doc>
974 <reg32 offset="0" name="0">
975 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
976 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
977 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
978 <bitfield name="VSC_N" low="22" high="26" type="uint"/>
979 </reg32>
980 <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
981 <reg32 offset="1" name="1">
982 <bitfield name="BIN_DATA_OFFSET" low="0" high="31" type="uint"/>
983 </reg32>
984 <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
985 <reg32 offset="2" name="2">
986 <bitfield name="BIN_SIZE_OFFSET" low="0" high="31" type="uint"/>
987 </reg32>
988 <!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS -->
989 <reg32 offset="3" name="3">
990 <bitfield name="BIN_DATA2_OFFSET" low="0" high="31" type="uint"/>
991 </reg32>
992 </domain>
993
994 <domain name="CP_REG_RMW" width="32">
995 <doc>
996 Modifies DST_REG using two sources that can either be registers
997 or immediates. If SRC1_ADD is set, then do the following:
998
999 $dst = (($dst &amp; $src0) rot $rotate) + $src1
1000
1001 Otherwise:
1002
1003 $dst = (($dst &amp; $src0) rot $rotate) | $src1
1004
1005 Here "rot" means rotate left.
1006 </doc>
1007 <reg32 offset="0" name="0">
1008 <bitfield name="DST_REG" low="0" high="17" type="hex"/>
1009 <bitfield name="ROTATE" low="24" high="28" type="uint"/>
1010 <bitfield name="SRC1_ADD" pos="29" type="boolean"/>
1011 <bitfield name="SRC1_IS_REG" pos="30" type="boolean"/>
1012 <bitfield name="SRC0_IS_REG" pos="31" type="boolean"/>
1013 </reg32>
1014 <reg32 offset="1" name="1">
1015 <bitfield name="SRC0" low="0" high="31" type="uint"/>
1016 </reg32>
1017 <reg32 offset="2" name="2">
1018 <bitfield name="SRC1" low="0" high="31" type="uint"/>
1019 </reg32>
1020 </domain>
1021
1022 <domain name="CP_REG_TO_MEM" width="32">
1023 <reg32 offset="0" name="0">
1024 <bitfield name="REG" low="0" high="17" type="hex"/>
1025 <!-- number of registers/dwords copied is max(CNT, 1). -->
1026 <bitfield name="CNT" low="18" high="29" type="uint"/>
1027 <bitfield name="64B" pos="30" type="boolean"/>
1028 <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
1029 </reg32>
1030 <reg32 offset="1" name="1">
1031 <bitfield name="DEST" low="0" high="31"/>
1032 </reg32>
1033 <reg32 offset="2" name="2" varset="chip" variants="A5XX-">
1034 <bitfield name="DEST_HI" low="0" high="31"/>
1035 </reg32>
1036 </domain>
1037
1038 <domain name="CP_REG_TO_MEM_OFFSET_REG" width="32">
1039 <doc>
1040 Like CP_REG_TO_MEM, but the memory address to write to can be
1041 offsetted using either one or two registers or scratch
1042 registers.
1043 </doc>
1044 <reg32 offset="0" name="0">
1045 <bitfield name="REG" low="0" high="17" type="hex"/>
1046 <!-- number of registers/dwords copied is max(CNT, 1). -->
1047 <bitfield name="CNT" low="18" high="29" type="uint"/>
1048 <bitfield name="64B" pos="30" type="boolean"/>
1049 <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
1050 </reg32>
1051 <reg32 offset="1" name="1">
1052 <bitfield name="DEST" low="0" high="31"/>
1053 </reg32>
1054 <reg32 offset="2" name="2" varset="chip" variants="A5XX-">
1055 <bitfield name="DEST_HI" low="0" high="31"/>
1056 </reg32>
1057 <reg32 offset="3" name="3">
1058 <bitfield name="OFFSET0" low="0" high="17" type="hex"/>
1059 <bitfield name="OFFSET0_SCRATCH" pos="19" type="boolean"/>
1060 </reg32>
1061 <!-- followed by an optional identical OFFSET1 dword -->
1062 </domain>
1063
1064 <domain name="CP_REG_TO_MEM_OFFSET_MEM" width="32">
1065 <doc>
1066 Like CP_REG_TO_MEM, but the memory address to write to can be
1067 offsetted using a DWORD in memory.
1068 </doc>
1069 <reg32 offset="0" name="0">
1070 <bitfield name="REG" low="0" high="17" type="hex"/>
1071 <!-- number of registers/dwords copied is max(CNT, 1). -->
1072 <bitfield name="CNT" low="18" high="29" type="uint"/>
1073 <bitfield name="64B" pos="30" type="boolean"/>
1074 <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
1075 </reg32>
1076 <reg32 offset="1" name="1">
1077 <bitfield name="DEST" low="0" high="31"/>
1078 </reg32>
1079 <reg32 offset="2" name="2" varset="chip" variants="A5XX-">
1080 <bitfield name="DEST_HI" low="0" high="31"/>
1081 </reg32>
1082 <reg32 offset="3" name="3">
1083 <bitfield name="OFFSET_LO" low="0" high="31" type="hex"/>
1084 </reg32>
1085 <reg32 offset="4" name="4">
1086 <bitfield name="OFFSET_HI" low="0" high="31" type="hex"/>
1087 </reg32>
1088 </domain>
1089
1090 <domain name="CP_MEM_TO_REG" width="32">
1091 <reg32 offset="0" name="0">
1092 <bitfield name="REG" low="0" high="17" type="hex"/>
1093 <!-- number of registers/dwords copied is max(CNT, 1). -->
1094 <bitfield name="CNT" low="19" high="29" type="uint"/>
1095 <!-- shift each DWORD left by 2 while copying -->
1096 <bitfield name="SHIFT_BY_2" pos="30" type="boolean"/>
1097 <!-- does the same thing as CP_MEM_TO_MEM::UNK31 -->
1098 <bitfield name="UNK31" pos="31" type="boolean"/>
1099 </reg32>
1100 <reg32 offset="1" name="1">
1101 <bitfield name="SRC" low="0" high="31"/>
1102 </reg32>
1103 <reg32 offset="2" name="2" varset="chip" variants="A5XX-">
1104 <bitfield name="SRC_HI" low="0" high="31"/>
1105 </reg32>
1106 </domain>
1107
1108 <domain name="CP_MEM_TO_MEM" width="32">
1109 <reg32 offset="0" name="0">
1110 <!--
1111 not sure how many src operands we have, but the low
1112 bits negate the n'th src argument.
1113 -->
1114 <bitfield name="NEG_A" pos="0" type="boolean"/>
1115 <bitfield name="NEG_B" pos="1" type="boolean"/>
1116 <bitfield name="NEG_C" pos="2" type="boolean"/>
1117
1118 <!-- if set treat src/dst as 64bit values -->
1119 <bitfield name="DOUBLE" pos="29" type="boolean"/>
1120 <!-- execute CP_WAIT_FOR_MEM_WRITES beforehand -->
1121 <bitfield name="WAIT_FOR_MEM_WRITES" pos="30" type="boolean"/>
1122 <!-- some other kind of wait -->
1123 <bitfield name="UNK31" pos="31" type="boolean"/>
1124 </reg32>
1125 <!--
1126 followed by sequence of addresses.. the first is the
1127 destination and the rest are N src addresses which are
1128 summed (after being negated if NEG_x bit set) allowing
1129 to do things like 'result += end - start' (which turns
1130 out to be useful for queries and accumulating results
1131 across multiple tiles)
1132 -->
1133 </domain>
1134
1135 <domain name="CP_MEMCPY" width="32">
1136 <reg32 offset="0" name="0">
1137 <bitfield name="DWORDS" low="0" high="31" type="uint"/>
1138 </reg32>
1139 <reg32 offset="1" name="1">
1140 <bitfield name="SRC_LO" low="0" high="31" type="hex"/>
1141 </reg32>
1142 <reg32 offset="2" name="2">
1143 <bitfield name="SRC_HI" low="0" high="31" type="hex"/>
1144 </reg32>
1145 <reg32 offset="3" name="3">
1146 <bitfield name="DST_LO" low="0" high="31" type="hex"/>
1147 </reg32>
1148 <reg32 offset="4" name="4">
1149 <bitfield name="DST_HI" low="0" high="31" type="hex"/>
1150 </reg32>
1151 </domain>
1152
1153 <domain name="CP_REG_TO_SCRATCH" width="32">
1154 <reg32 offset="0" name="0">
1155 <bitfield name="REG" low="0" high="17" type="hex"/>
1156 <bitfield name="SCRATCH" low="20" high="22" type="uint"/>
1157 <!-- number of registers/dwords copied is CNT + 1. -->
1158 <bitfield name="CNT" low="24" high="26" type="uint"/>
1159 </reg32>
1160 </domain>
1161
1162 <domain name="CP_SCRATCH_TO_REG" width="32">
1163 <reg32 offset="0" name="0">
1164 <bitfield name="REG" low="0" high="17" type="hex"/>
1165 <!-- note: CP_MEM_TO_REG always sets this when writing to the register -->
1166 <bitfield name="UNK18" pos="18" type="boolean"/>
1167 <bitfield name="SCRATCH" low="20" high="22" type="uint"/>
1168 <!-- number of registers/dwords copied is CNT + 1. -->
1169 <bitfield name="CNT" low="24" high="26" type="uint"/>
1170 </reg32>
1171 </domain>
1172
1173 <domain name="CP_SCRATCH_WRITE" width="32">
1174 <reg32 offset="0" name="0">
1175 <bitfield name="SCRATCH" low="20" high="22" type="uint"/>
1176 </reg32>
1177 <!-- followed by one or more DWORDs to write to scratch registers -->
1178 </domain>
1179
1180 <domain name="CP_MEM_WRITE" width="32">
1181 <reg32 offset="0" name="0">
1182 <bitfield name="ADDR_LO" low="0" high="31"/>
1183 </reg32>
1184 <reg32 offset="1" name="1">
1185 <bitfield name="ADDR_HI" low="0" high="31"/>
1186 </reg32>
1187 <!-- followed by the DWORDs to write -->
1188 </domain>
1189
1190 <enum name="cp_cond_function">
1191 <value value="0" name="WRITE_ALWAYS"/>
1192 <value value="1" name="WRITE_LT"/>
1193 <value value="2" name="WRITE_LE"/>
1194 <value value="3" name="WRITE_EQ"/>
1195 <value value="4" name="WRITE_NE"/>
1196 <value value="5" name="WRITE_GE"/>
1197 <value value="6" name="WRITE_GT"/>
1198 </enum>
1199
1200 <domain name="CP_COND_WRITE" width="32">
1201 <reg32 offset="0" name="0">
1202 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
1203 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
1204 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
1205 </reg32>
1206 <reg32 offset="1" name="1">
1207 <bitfield name="POLL_ADDR" low="0" high="31" type="hex"/>
1208 </reg32>
1209 <reg32 offset="2" name="2">
1210 <bitfield name="REF" low="0" high="31"/>
1211 </reg32>
1212 <reg32 offset="3" name="3">
1213 <bitfield name="MASK" low="0" high="31"/>
1214 </reg32>
1215 <reg32 offset="4" name="4">
1216 <bitfield name="WRITE_ADDR" low="0" high="31" type="hex"/>
1217 </reg32>
1218 <reg32 offset="5" name="5">
1219 <bitfield name="WRITE_DATA" low="0" high="31"/>
1220 </reg32>
1221 </domain>
1222
1223 <domain name="CP_COND_WRITE5" width="32">
1224 <reg32 offset="0" name="0">
1225 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
1226 <bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/>
1227 <!-- if both POLL_MEMORY and POLL_SCRATCH are false, it polls a register at POLL_ADDR_LO instead. -->
1228 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
1229 <bitfield name="POLL_SCRATCH" pos="5" type="boolean"/>
1230 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
1231 </reg32>
1232 <reg32 offset="1" name="1">
1233 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
1234 </reg32>
1235 <reg32 offset="2" name="2">
1236 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
1237 </reg32>
1238 <reg32 offset="3" name="3">
1239 <bitfield name="REF" low="0" high="31"/>
1240 </reg32>
1241 <reg32 offset="4" name="4">
1242 <bitfield name="MASK" low="0" high="31"/>
1243 </reg32>
1244 <reg32 offset="5" name="5">
1245 <bitfield name="WRITE_ADDR_LO" low="0" high="31" type="hex"/>
1246 </reg32>
1247 <reg32 offset="6" name="6">
1248 <bitfield name="WRITE_ADDR_HI" low="0" high="31" type="hex"/>
1249 </reg32>
1250 <reg32 offset="7" name="7">
1251 <bitfield name="WRITE_DATA" low="0" high="31"/>
1252 </reg32>
1253 </domain>
1254
1255 <domain name="CP_WAIT_MEM_GTE" width="32">
1256 <doc>
1257 Wait until a memory value is greater than or equal to the
1258 reference, using signed comparison.
1259 </doc>
1260 <reg32 offset="0" name="0">
1261 <!-- Reserved for flags, presumably? Unused in FW -->
1262 <bitfield name="RESERVED" low="0" high="31" type="hex"/>
1263 </reg32>
1264 <reg32 offset="1" name="1">
1265 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
1266 </reg32>
1267 <reg32 offset="2" name="2">
1268 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
1269 </reg32>
1270 <reg32 offset="3" name="3">
1271 <bitfield name="REF" low="0" high="31"/>
1272 </reg32>
1273 </domain>
1274
1275 <domain name="CP_WAIT_REG_MEM" width="32">
1276 <doc>
1277 This uses the same internal comparison as CP_COND_WRITE,
1278 but waits until the comparison is true instead. It busy-loops in
1279 the CP for the given number of cycles before trying again.
1280 </doc>
1281 <reg32 offset="0" name="0">
1282 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
1283 <bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/>
1284 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
1285 <bitfield name="POLL_SCRATCH" pos="5" type="boolean"/>
1286 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
1287 </reg32>
1288 <reg32 offset="1" name="1">
1289 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
1290 </reg32>
1291 <reg32 offset="2" name="2">
1292 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
1293 </reg32>
1294 <reg32 offset="3" name="3">
1295 <bitfield name="REF" low="0" high="31"/>
1296 </reg32>
1297 <reg32 offset="4" name="4">
1298 <bitfield name="MASK" low="0" high="31"/>
1299 </reg32>
1300 <reg32 offset="5" name="5">
1301 <bitfield name="DELAY_LOOP_CYCLES" low="0" high="31"/>
1302 </reg32>
1303 </domain>
1304
1305 <domain name="CP_WAIT_TWO_REGS" width="32">
1306 <doc>
1307 Waits for REG0 to not be 0 or REG1 to not equal REF
1308 </doc>
1309 <reg32 offset="0" name="0">
1310 <bitfield name="REG0" low="0" high="17" type="hex"/>
1311 </reg32>
1312 <reg32 offset="1" name="1">
1313 <bitfield name="REG1" low="0" high="17" type="hex"/>
1314 </reg32>
1315 <reg32 offset="2" name="2">
1316 <bitfield name="REF" low="0" high="31" type="uint"/>
1317 </reg32>
1318 </domain>
1319
1320 <domain name="CP_DISPATCH_COMPUTE" width="32">
1321 <reg32 offset="0" name="0"/>
1322 <reg32 offset="1" name="1">
1323 <bitfield name="X" low="0" high="31"/>
1324 </reg32>
1325 <reg32 offset="2" name="2">
1326 <bitfield name="Y" low="0" high="31"/>
1327 </reg32>
1328 <reg32 offset="3" name="3">
1329 <bitfield name="Z" low="0" high="31"/>
1330 </reg32>
1331 </domain>
1332
1333 <domain name="CP_SET_RENDER_MODE" width="32">
1334 <enum name="render_mode_cmd">
1335 <value value="1" name="BYPASS"/>
1336 <value value="2" name="BINNING"/>
1337 <value value="3" name="GMEM"/>
1338 <value value="5" name="BLIT2D"/>
1339 <!-- placeholder name.. used when CP_BLIT packets with BLIT_OP_SCALE?? -->
1340 <value value="7" name="BLIT2DSCALE"/>
1341 <!-- 8 set before going back to BYPASS exiting 2D -->
1342 <value value="8" name="END2D"/>
1343 </enum>
1344 <reg32 offset="0" name="0">
1345 <bitfield name="MODE" low="0" high="8" type="render_mode_cmd"/>
1346 <!--
1347 normally 0x1/0x3, sometimes see 0x5/0x8 with unknown registers in
1348 0x21xx range.. possibly (at least some) a5xx variants have a
1349 2d core?
1350 -->
1351 </reg32>
1352 <!-- I think first buffer is for GPU to save context in case of ctx switch? -->
1353 <reg32 offset="1" name="1">
1354 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1355 </reg32>
1356 <reg32 offset="2" name="2">
1357 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1358 </reg32>
1359 <reg32 offset="3" name="3">
1360 <!--
1361 set when in GMEM.. maybe indicates GMEM contents need to be
1362 preserved on ctx switch?
1363 -->
1364 <bitfield name="VSC_ENABLE" pos="3" type="boolean"/>
1365 <bitfield name="GMEM_ENABLE" pos="4" type="boolean"/>
1366 </reg32>
1367 <reg32 offset="4" name="4"/>
1368 <!-- second buffer looks like some cmdstream.. length in dwords: -->
1369 <reg32 offset="5" name="5">
1370 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
1371 </reg32>
1372 <reg32 offset="6" name="6">
1373 <bitfield name="ADDR_1_LO" low="0" high="31"/>
1374 </reg32>
1375 <reg32 offset="7" name="7">
1376 <bitfield name="ADDR_1_HI" low="0" high="31"/>
1377 </reg32>
1378 </domain>
1379
1380 <!-- this looks fairly similar to CP_SET_RENDER_MODE minus first dword -->
1381 <domain name="CP_COMPUTE_CHECKPOINT" width="32">
1382 <!-- I think first buffer is for GPU to save context in case of ctx switch? -->
1383 <reg32 offset="0" name="0">
1384 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1385 </reg32>
1386 <reg32 offset="1" name="1">
1387 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1388 </reg32>
1389 <reg32 offset="2" name="2">
1390 </reg32>
1391 <!-- second buffer looks like some cmdstream.. length in dwords: -->
1392 <reg32 offset="3" name="3">
1393 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
1394 </reg32>
1395 <reg32 offset="4" name="4"/>
1396 <reg32 offset="5" name="5">
1397 <bitfield name="ADDR_1_LO" low="0" high="31"/>
1398 </reg32>
1399 <reg32 offset="6" name="6">
1400 <bitfield name="ADDR_1_HI" low="0" high="31"/>
1401 </reg32>
1402 <reg32 offset="7" name="7"/>
1403 </domain>
1404
1405 <domain name="CP_PERFCOUNTER_ACTION" width="32">
1406 <reg32 offset="0" name="0">
1407 </reg32>
1408 <reg32 offset="1" name="1">
1409 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1410 </reg32>
1411 <reg32 offset="2" name="2">
1412 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1413 </reg32>
1414 </domain>
1415
1416 <domain name="CP_EVENT_WRITE" width="32">
1417 <reg32 offset="0" name="0">
1418 <bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/>
1419 <!-- when set, write back timestamp instead of value from packet: -->
1420 <bitfield name="TIMESTAMP" pos="30" type="boolean"/>
1421 <bitfield name="IRQ" pos="31" type="boolean"/>
1422 </reg32>
1423 <!--
1424 TODO what is gpuaddr for, seems to be all 0's.. maybe needed for
1425 context switch?
1426 -->
1427 <reg32 offset="1" name="1">
1428 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1429 </reg32>
1430 <reg32 offset="2" name="2">
1431 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1432 </reg32>
1433 <reg32 offset="3" name="3">
1434 <!-- ??? -->
1435 </reg32>
1436 </domain>
1437
1438 <domain name="CP_BLIT" width="32">
1439 <enum name="cp_blit_cmd">
1440 <value value="0" name="BLIT_OP_FILL"/>
1441 <value value="1" name="BLIT_OP_COPY"/>
1442 <value value="3" name="BLIT_OP_SCALE"/> <!-- used for mipmap generation -->
1443 </enum>
1444 <reg32 offset="0" name="0">
1445 <bitfield name="OP" low="0" high="3" type="cp_blit_cmd"/>
1446 </reg32>
1447 <reg32 offset="1" name="1">
1448 <bitfield name="SRC_X1" low="0" high="13" type="uint"/>
1449 <bitfield name="SRC_Y1" low="16" high="29" type="uint"/>
1450 </reg32>
1451 <reg32 offset="2" name="2">
1452 <bitfield name="SRC_X2" low="0" high="13" type="uint"/>
1453 <bitfield name="SRC_Y2" low="16" high="29" type="uint"/>
1454 </reg32>
1455 <reg32 offset="3" name="3">
1456 <bitfield name="DST_X1" low="0" high="13" type="uint"/>
1457 <bitfield name="DST_Y1" low="16" high="29" type="uint"/>
1458 </reg32>
1459 <reg32 offset="4" name="4">
1460 <bitfield name="DST_X2" low="0" high="13" type="uint"/>
1461 <bitfield name="DST_Y2" low="16" high="29" type="uint"/>
1462 </reg32>
1463 </domain>
1464
1465 <domain name="CP_EXEC_CS" width="32">
1466 <reg32 offset="0" name="0">
1467 </reg32>
1468 <reg32 offset="1" name="1">
1469 <bitfield name="NGROUPS_X" low="0" high="31" type="uint"/>
1470 </reg32>
1471 <reg32 offset="2" name="2">
1472 <bitfield name="NGROUPS_Y" low="0" high="31" type="uint"/>
1473 </reg32>
1474 <reg32 offset="3" name="3">
1475 <bitfield name="NGROUPS_Z" low="0" high="31" type="uint"/>
1476 </reg32>
1477 </domain>
1478
1479 <domain name="CP_EXEC_CS_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
1480 <reg32 offset="0" name="0">
1481 </reg32>
1482 <stripe varset="chip" variants="A4XX">
1483 <reg32 offset="1" name="1">
1484 <bitfield name="ADDR" low="0" high="31"/>
1485 </reg32>
1486 <reg32 offset="2" name="2">
1487 <!-- localsize is value minus one: -->
1488 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
1489 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
1490 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
1491 </reg32>
1492 </stripe>
1493 <stripe varset="chip" variants="A5XX-">
1494 <reg32 offset="1" name="1">
1495 <bitfield name="ADDR_LO" low="0" high="31"/>
1496 </reg32>
1497 <reg32 offset="2" name="2">
1498 <bitfield name="ADDR_HI" low="0" high="31"/>
1499 </reg32>
1500 <reg32 offset="3" name="3">
1501 <!-- localsize is value minus one: -->
1502 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
1503 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
1504 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
1505 </reg32>
1506 </stripe>
1507 </domain>
1508
1509 <domain name="CP_SET_MARKER" width="32" varset="chip" prefix="chip" variants="A6XX-">
1510 <doc>Tell CP the current operation mode, indicates save and restore procedure</doc>
1511 <enum name="a6xx_render_mode">
1512 <value value="1" name="RM6_BYPASS"/>
1513 <value value="2" name="RM6_BINNING"/>
1514 <value value="4" name="RM6_GMEM"/>
1515 <value value="5" name="RM6_ENDVIS"/>
1516 <value value="6" name="RM6_RESOLVE"/>
1517 <value value="7" name="RM6_YIELD"/>
1518 <value value="8" name="RM6_COMPUTE"/>
1519 <value value="0xc" name="RM6_BLIT2DSCALE"/> <!-- no-op (at least on current sqe fw) -->
1520
1521 <!--
1522 These values come from a6xx_set_marker() in the
1523 downstream kernel, and they can only be set by the kernel
1524 -->
1525 <value value="0xd" name="RM6_IB1LIST_START"/>
1526 <value value="0xe" name="RM6_IB1LIST_END"/>
1527 <!-- IFPC - inter-frame power collapse -->
1528 <value value="0x100" name="RM6_IFPC_ENABLE"/>
1529 <value value="0x101" name="RM6_IFPC_DISABLE"/>
1530 </enum>
1531 <reg32 offset="0" name="0">
1532 <!--
1533 NOTE: blob driver and some versions of freedreno/turnip set
1534 b4, which is unused (at least by current sqe fw), but interferes
1535 with parsing if we extend the size of the bitfield to include
1536 b8 (only sent by kernel mode driver). Really, the way the
1537 parsing works in the firmware, only b0-b3 are considered, but
1538 if b8 is set, the low bits are interpreted differently. To
1539 model this, without getting confused by spurious b4, this is
1540 described as two overlapping bitfields:
1541 -->
1542 <bitfield name="MODE" low="0" high="8" type="a6xx_render_mode"/>
1543 <bitfield name="MARKER" low="0" high="3" type="a6xx_render_mode"/>
1544 </reg32>
1545 </domain>
1546
1547 <domain name="CP_SET_PSEUDO_REG" width="32" varset="chip" prefix="chip" variants="A6XX-">
1548 <doc>Set internal CP registers, used to indicate context save data addresses</doc>
1549 <enum name="pseudo_reg">
1550 <value value="0" name="SMMU_INFO"/>
1551 <value value="1" name="NON_SECURE_SAVE_ADDR"/>
1552 <value value="2" name="SECURE_SAVE_ADDR"/>
1553 <value value="3" name="NON_PRIV_SAVE_ADDR"/>
1554 <value value="4" name="COUNTER"/>
1555 </enum>
1556 <array offset="0" stride="3" length="100">
1557 <reg32 offset="0" name="0">
1558 <bitfield name="PSEUDO_REG" low="0" high="2" type="pseudo_reg"/>
1559 </reg32>
1560 <reg32 offset="1" name="1">
1561 <bitfield name="LO" low="0" high="31"/>
1562 </reg32>
1563 <reg32 offset="2" name="2">
1564 <bitfield name="HI" low="0" high="31"/>
1565 </reg32>
1566 </array>
1567 </domain>
1568
1569 <domain name="CP_REG_TEST" width="32" varset="chip" prefix="chip" variants="A6XX-">
1570 <doc>
1571 Tests bit in specified register and sets predicate for CP_COND_REG_EXEC.
1572 So:
1573
1574 opcode: CP_REG_TEST (39) (2 dwords)
1575 { REG = 0xc10 | BIT = 0 }
1576 0000: 70b90001 00000c10
1577 opcode: CP_COND_REG_EXEC (47) (3 dwords)
1578 0000: 70c70002 10000000 00000004
1579 opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
1580
1581 Will execute the CP_INDIRECT_BUFFER only if b0 in the register at
1582 offset 0x0c10 is 1
1583 </doc>
1584 <reg32 offset="0" name="0">
1585 <!-- the register to test -->
1586 <bitfield name="REG" low="0" high="17"/>
1587 <!-- the bit to test -->
1588 <bitfield name="BIT" low="20" high="24" type="uint"/>
1589 <!-- execute CP_WAIT_FOR_ME beforehand -->
1590 <bitfield name="WAIT_FOR_ME" pos="25" type="boolean"/>
1591 </reg32>
1592 </domain>
1593
1594 <!-- I *think* this existed at least as far back as a4xx -->
1595 <domain name="CP_COND_REG_EXEC" width="32">
1596 <enum name="compare_mode">
1597 <!-- use the predicate bit set by CP_REG_TEST -->
1598 <value value="1" name="PRED_TEST"/>
1599 <!-- compare two registers directly for equality -->
1600 <value value="2" name="REG_COMPARE"/>
1601 <!-- test if certain render modes are set via CP_SET_MARKER -->
1602 <value value="3" name="RENDER_MODE" varset="chip" variants="A6XX-"/>
1603 </enum>
1604 <reg32 offset="0" name="0">
1605 <bitfield name="REG0" low="0" high="17" type="hex"/>
1606
1607 <!--
1608 Note: these bits have the same meaning, and use the same
1609 internal mechanism as the bits in CP_SET_DRAW_STATE.
1610 When RENDER_MODE is selected, they're used as
1611 a bitmask of which modes pass the test.
1612 -->
1613
1614 <!-- RM6_BINNING -->
1615 <bitfield name="BINNING" pos="25" varset="chip" variants="A6XX-" type="boolean"/>
1616 <!-- all others -->
1617 <bitfield name="GMEM" pos="26" varset="chip" variants="A6XX-" type="boolean"/>
1618 <!-- RM6_BYPASS -->
1619 <bitfield name="SYSMEM" pos="27" varset="chip" variants="A6XX-" type="boolean"/>
1620
1621 <bitfield name="MODE" low="28" high="31" type="compare_mode"/>
1622 </reg32>
1623
1624 <!-- in REG_COMPARE mode, there's an extra DWORD here with REG1 -->
1625
1626 <reg32 offset="1" name="1">
1627 <bitfield name="DWORDS" low="0" high="31" type="uint"/>
1628 </reg32>
1629 </domain>
1630
1631 <domain name="CP_COND_EXEC" width="32">
1632 <doc>
1633 Executes the following DWORDs of commands if the dword at ADDR0
1634 is not equal to 0 and the dword at ADDR1 is less than REF
1635 (signed comparison).
1636 </doc>
1637 <reg32 offset="0" name="0">
1638 <bitfield name="ADDR0_LO" low="0" high="31"/>
1639 </reg32>
1640 <reg32 offset="1" name="1">
1641 <bitfield name="ADDR0_HI" low="0" high="31"/>
1642 </reg32>
1643 <reg32 offset="2" name="2">
1644 <bitfield name="ADDR1_LO" low="0" high="31"/>
1645 </reg32>
1646 <reg32 offset="3" name="3">
1647 <bitfield name="ADDR1_HI" low="0" high="31"/>
1648 </reg32>
1649 <reg32 offset="4" name="4">
1650 <bitfield name="REF" low="0" high="31"/>
1651 </reg32>
1652 <reg32 offset="5" name="5">
1653 <bitfield name="DWORDS" low="0" high="31" type="uint"/>
1654 </reg32>
1655 </domain>
1656
1657 <domain name="CP_SET_CTXSWITCH_IB" width="32">
1658 <doc>
1659 Used by the userspace driver to set various IB's which are
1660 executed during context save/restore for handling
1661 state that isn't restored by the
1662 context switch routine itself.
1663 </doc>
1664 <enum name="ctxswitch_ib">
1665 <value name="RESTORE_IB" value="0">
1666 <doc>Executed unconditionally when switching back to the context.</doc>
1667 </value>
1668 <value name="YIELD_RESTORE_IB" value="1">
1669 <doc>
1670 Executed when switching back after switching
1671 away during execution of
1672 a CP_SET_MARKER packet with RM6_YIELD as the
1673 payload *and* the normal save routine was
1674 bypassed for a shorter one. I think this is
1675 connected to the "skipsaverestore" bit set by
1676 the kernel when preempting.
1677 </doc>
1678 </value>
1679 <value name="SAVE_IB" value="2">
1680 <doc>
1681 Executed when switching away from the context,
1682 except for context switches initiated via
1683 CP_YIELD.
1684 </doc>
1685 </value>
1686 <value name="RB_SAVE_IB" value="3">
1687 <doc>
1688 This can only be set by the RB (i.e. the kernel)
1689 and executes with protected mode off, but
1690 is otherwise similar to SAVE_IB.
1691 </doc>
1692 </value>
1693 </enum>
1694 <reg32 offset="0" name="0">
1695 <bitfield name="ADDR_LO" low="0" high="31"/>
1696 </reg32>
1697 <reg32 offset="1" name="1">
1698 <bitfield name="ADDR_HI" low="0" high="31"/>
1699 </reg32>
1700 <reg32 offset="2" name="2">
1701 <bitfield name="DWORDS" low="0" high="19" type="uint"/>
1702 <bitfield name="TYPE" low="20" high="21" type="ctxswitch_ib"/>
1703 </reg32>
1704 </domain>
1705
1706 <domain name="CP_REG_WRITE" width="32">
1707 <enum name="reg_tracker">
1708 <doc>
1709 Keep shadow copies of these registers and only set them
1710 when drawing, avoiding redundant writes:
1711 - VPC_CNTL_0
1712 - HLSQ_CONTROL_1_REG
1713 - HLSQ_UNKNOWN_B980
1714 </doc>
1715 <value name="TRACK_CNTL_REG" value="0x1"/>
1716 <doc>
1717 Track RB_RENDER_CNTL, and insert a WFI in the following
1718 situation:
1719 - There is a write that disables binning
1720 - There was a draw with binning left enabled, but in
1721 BYPASS mode
1722 Presumably this is a hang workaround?
1723 </doc>
1724 <value name="TRACK_RENDER_CNTL" value="0x2"/>
1725 <doc>
1726 Do a mysterious CP_EVENT_WRITE 0x3f when the low bit of
1727 the data to write is 0. Used by the Vulkan blob with
1728 PC_UNKNOWN_9B07, but this isn't predicated on particular
1729 register(s) like the others.
1730 </doc>
1731 <value name="UNK_EVENT_WRITE" value="0x4"/>
1732 </enum>
1733 <reg32 offset="0" name="0">
1734 <bitfield name="TRACKER" low="0" high="2" type="reg_tracker"/>
1735 </reg32>
1736 </domain>
1737
1738 <domain name="CP_SMMU_TABLE_UPDATE" width="32">
1739 <doc>
1740 Note that the SMMU's definition of TTBRn can take different forms
1741 depending on the pgtable format. But a5xx+ only uses aarch64
1742 format.
1743 </doc>
1744 <reg32 offset="0" name="0">
1745 <bitfield name="TTBR0_LO" low="0" high="31"/>
1746 </reg32>
1747 <reg32 offset="1" name="1">
1748 <bitfield name="TTBR0_HI" low="0" high="15"/>
1749 <bitfield name="ASID" low="16" high="31"/>
1750 </reg32>
1751 <reg32 offset="2" name="2">
1752 <doc>Unused, does not apply to aarch64 pgtable format</doc>
1753 <bitfield name="CONTEXTIDR" low="0" high="31"/>
1754 </reg32>
1755 <reg32 offset="3" name="3">
1756 <bitfield name="CONTEXTBANK" low="0" high="31"/>
1757 </reg32>
1758 </domain>
1759
1760 </database>
1761