src/freedreno/registers/adreno_common.xml

   1 <?xml version="1.0" encoding="UTF-8"?>
   2 <database xmlns="http://nouveau.freedesktop.org/"
   3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
   4 xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
   5
   6 <enum name="chip" bare="yes">
   7         <value name="A2XX"/>
   8         <value name="A3XX"/>
   9         <value name="A4XX"/>
  10         <value name="A5XX"/>
  11         <value name="A6XX"/>
  12 </enum>
  13
  14 <enum name="adreno_pa_su_sc_draw">
  15         <value name="PC_DRAW_POINTS" value="0"/>
  16         <value name="PC_DRAW_LINES" value="1"/>
  17         <value name="PC_DRAW_TRIANGLES" value="2"/>
  18 </enum>
  19
  20 <enum name="adreno_compare_func">
  21         <value name="FUNC_NEVER" value="0"/>
  22         <value name="FUNC_LESS" value="1"/>
  23         <value name="FUNC_EQUAL" value="2"/>
  24         <value name="FUNC_LEQUAL" value="3"/>
  25         <value name="FUNC_GREATER" value="4"/>
  26         <value name="FUNC_NOTEQUAL" value="5"/>
  27         <value name="FUNC_GEQUAL" value="6"/>
  28         <value name="FUNC_ALWAYS" value="7"/>
  29 </enum>
  30
  31 <enum name="adreno_stencil_op">
  32         <value name="STENCIL_KEEP" value="0"/>
  33         <value name="STENCIL_ZERO" value="1"/>
  34         <value name="STENCIL_REPLACE" value="2"/>
  35         <value name="STENCIL_INCR_CLAMP" value="3"/>
  36         <value name="STENCIL_DECR_CLAMP" value="4"/>
  37         <value name="STENCIL_INVERT" value="5"/>
  38         <value name="STENCIL_INCR_WRAP" value="6"/>
  39         <value name="STENCIL_DECR_WRAP" value="7"/>
  40 </enum>
  41
  42 <enum name="adreno_rb_blend_factor">
  43         <value name="FACTOR_ZERO" value="0"/>
  44         <value name="FACTOR_ONE" value="1"/>
  45         <value name="FACTOR_SRC_COLOR" value="4"/>
  46         <value name="FACTOR_ONE_MINUS_SRC_COLOR" value="5"/>
  47         <value name="FACTOR_SRC_ALPHA" value="6"/>
  48         <value name="FACTOR_ONE_MINUS_SRC_ALPHA" value="7"/>
  49         <value name="FACTOR_DST_COLOR" value="8"/>
  50         <value name="FACTOR_ONE_MINUS_DST_COLOR" value="9"/>
  51         <value name="FACTOR_DST_ALPHA" value="10"/>
  52         <value name="FACTOR_ONE_MINUS_DST_ALPHA" value="11"/>
  53         <value name="FACTOR_CONSTANT_COLOR" value="12"/>
  54         <value name="FACTOR_ONE_MINUS_CONSTANT_COLOR" value="13"/>
  55         <value name="FACTOR_CONSTANT_ALPHA" value="14"/>
  56         <value name="FACTOR_ONE_MINUS_CONSTANT_ALPHA" value="15"/>
  57         <value name="FACTOR_SRC_ALPHA_SATURATE" value="16"/>
  58         <value name="FACTOR_SRC1_COLOR" value="20"/>
  59         <value name="FACTOR_ONE_MINUS_SRC1_COLOR" value="21"/>
  60         <value name="FACTOR_SRC1_ALPHA" value="22"/>
  61         <value name="FACTOR_ONE_MINUS_SRC1_ALPHA" value="23"/>
  62 </enum>
  63
  64 <bitset name="adreno_rb_stencilrefmask" inline="yes">
  65         <bitfield name="STENCILREF" low="0" high="7" type="hex"/>
  66         <bitfield name="STENCILMASK" low="8" high="15" type="hex"/>
  67         <bitfield name="STENCILWRITEMASK" low="16" high="23" type="hex"/>
  68 </bitset>
  69
  70 <enum name="adreno_rb_surface_endian">
  71         <value name="ENDIAN_NONE" value="0"/>
  72         <value name="ENDIAN_8IN16" value="1"/>
  73         <value name="ENDIAN_8IN32" value="2"/>
  74         <value name="ENDIAN_16IN32" value="3"/>
  75         <value name="ENDIAN_8IN64" value="4"/>
  76         <value name="ENDIAN_8IN128" value="5"/>
  77 </enum>
  78
  79 <enum name="adreno_rb_dither_mode">
  80         <value name="DITHER_DISABLE" value="0"/>
  81         <value name="DITHER_ALWAYS" value="1"/>
  82         <value name="DITHER_IF_ALPHA_OFF" value="2"/>
  83 </enum>
  84
  85 <enum name="adreno_rb_depth_format">
  86         <value name="DEPTHX_16" value="0"/>
  87         <value name="DEPTHX_24_8" value="1"/>
  88         <value name="DEPTHX_32" value="2"/>
  89 </enum>
  90
  91 <enum name="adreno_rb_copy_control_mode">
  92         <value name="RB_COPY_RESOLVE" value="1"/>
  93         <value name="RB_COPY_CLEAR" value="2"/>
  94         <value name="RB_COPY_DEPTH_STENCIL" value="5"/>  <!-- not sure if this is part of MODE or another bitfield?? -->
  95 </enum>
  96
  97 <bitset name="adreno_reg_xy" inline="yes">
  98         <bitfield name="WINDOW_OFFSET_DISABLE" pos="31" type="boolean"/>
  99         <bitfield name="X" low="0" high="14" type="uint"/>
 100         <bitfield name="Y" low="16" high="30" type="uint"/>
 101 </bitset>
 102
 103 <bitset name="adreno_cp_protect" inline="yes">
 104         <bitfield name="BASE_ADDR" low="0" high="16"/>
 105         <bitfield name="MASK_LEN" low="24" high="28"/>
 106         <bitfield name="TRAP_WRITE" pos="29"/>
 107         <bitfield name="TRAP_READ" pos="30"/>
 108 </bitset>
 109
 110 <domain name="AXXX" width="32">
 111         <brief>Registers in common between a2xx and a3xx</brief>
 112
 113         <reg32 offset="0x01c0" name="CP_RB_BASE"/>
 114         <reg32 offset="0x01c1" name="CP_RB_CNTL">
 115                 <bitfield name="BUFSZ" low="0" high="5"/>
 116                 <bitfield name="BLKSZ" low="8" high="13"/>
 117                 <bitfield name="BUF_SWAP" low="16" high="17"/>
 118                 <bitfield name="POLL_EN" pos="20" type="boolean"/>
 119                 <bitfield name="NO_UPDATE" pos="27" type="boolean"/>
 120                 <bitfield name="RPTR_WR_EN" pos="31" type="boolean"/>
 121         </reg32>
 122         <reg32 offset="0x01c3" name="CP_RB_RPTR_ADDR">
 123                 <bitfield name="SWAP" low="0" high="1" type="uint"/>
 124                 <bitfield name="ADDR" low="2" high="31" shr="2"/>
 125         </reg32>
 126         <reg32 offset="0x01c4" name="CP_RB_RPTR" type="uint"/>
 127         <reg32 offset="0x01c5" name="CP_RB_WPTR" type="uint"/>
 128         <reg32 offset="0x01c6" name="CP_RB_WPTR_DELAY"/>
 129         <reg32 offset="0x01c7" name="CP_RB_RPTR_WR"/>
 130         <reg32 offset="0x01c8" name="CP_RB_WPTR_BASE"/>
 131         <reg32 offset="0x01d5" name="CP_QUEUE_THRESHOLDS">
 132                 <bitfield name="CSQ_IB1_START" low="0" high="3" type="uint"/>
 133                 <bitfield name="CSQ_IB2_START" low="8" high="11" type="uint"/>
 134                 <bitfield name="CSQ_ST_START" low="16" high="19" type="uint"/>
 135         </reg32>
 136         <reg32 offset="0x01d6" name="CP_MEQ_THRESHOLDS">
 137                 <bitfield name="MEQ_END" low="16" high="20" type="uint"/>
 138                 <bitfield name="ROQ_END" low="24" high="28" type="uint"/>
 139         </reg32>
 140         <reg32 offset="0x01d7" name="CP_CSQ_AVAIL">
 141                 <bitfield name="RING" low="0" high="6" type="uint"/>
 142                 <bitfield name="IB1" low="8" high="14" type="uint"/>
 143                 <bitfield name="IB2" low="16" high="22" type="uint"/>
 144         </reg32>
 145         <reg32 offset="0x01d8" name="CP_STQ_AVAIL">
 146                 <bitfield name="ST" low="0" high="6" type="uint"/>
 147         </reg32>
 148         <reg32 offset="0x01d9" name="CP_MEQ_AVAIL">
 149                 <bitfield name="MEQ" low="0" high="4" type="uint"/>
 150         </reg32>
 151         <reg32 offset="0x01dc" name="SCRATCH_UMSK">
 152                 <bitfield name="UMSK" low="0" high="7" type="uint"/>
 153                 <bitfield name="SWAP" low="16" high="17" type="uint"/>
 154         </reg32>
 155         <reg32 offset="0x01dd" name="SCRATCH_ADDR"/>
 156         <reg32 offset="0x01ea" name="CP_ME_RDADDR"/>
 157
 158         <reg32 offset="0x01ec" name="CP_STATE_DEBUG_INDEX"/>
 159         <reg32 offset="0x01ed" name="CP_STATE_DEBUG_DATA"/>
 160         <reg32 offset="0x01f2" name="CP_INT_CNTL">
 161                 <bitfield name="SW_INT_MASK" pos="19" type="boolean"/>
 162                 <bitfield name="T0_PACKET_IN_IB_MASK" pos="23" type="boolean"/>
 163                 <bitfield name="OPCODE_ERROR_MASK" pos="24" type="boolean"/>
 164                 <bitfield name="PROTECTED_MODE_ERROR_MASK" pos="25" type="boolean"/>
 165                 <bitfield name="RESERVED_BIT_ERROR_MASK" pos="26" type="boolean"/>
 166                 <bitfield name="IB_ERROR_MASK" pos="27" type="boolean"/>
 167                 <bitfield name="IB2_INT_MASK" pos="29" type="boolean"/>
 168                 <bitfield name="IB1_INT_MASK" pos="30" type="boolean"/>
 169                 <bitfield name="RB_INT_MASK" pos="31" type="boolean"/>
 170         </reg32>
 171         <reg32 offset="0x01f3" name="CP_INT_STATUS"/>
 172         <reg32 offset="0x01f4" name="CP_INT_ACK"/>
 173         <reg32 offset="0x01f6" name="CP_ME_CNTL">
 174                 <bitfield name="BUSY" pos="29" type="boolean"/>
 175                 <bitfield name="HALT" pos="28" type="boolean"/>
 176         </reg32>
 177         <reg32 offset="0x01f7" name="CP_ME_STATUS"/>
 178         <reg32 offset="0x01f8" name="CP_ME_RAM_WADDR"/>
 179         <reg32 offset="0x01f9" name="CP_ME_RAM_RADDR"/>
 180         <reg32 offset="0x01fa" name="CP_ME_RAM_DATA"/>
 181         <reg32 offset="0x01fc" name="CP_DEBUG">
 182                 <bitfield name="PREDICATE_DISABLE" pos="23" type="boolean"/>
 183                 <bitfield name="PROG_END_PTR_ENABLE" pos="24" type="boolean"/>
 184                 <bitfield name="MIU_128BIT_WRITE_ENABLE" pos="25" type="boolean"/>
 185                 <bitfield name="PREFETCH_PASS_NOPS" pos="26" type="boolean"/>
 186                 <bitfield name="DYNAMIC_CLK_DISABLE" pos="27" type="boolean"/>
 187                 <bitfield name="PREFETCH_MATCH_DISABLE" pos="28" type="boolean"/>
 188                 <bitfield name="SIMPLE_ME_FLOW_CONTROL" pos="30" type="boolean"/>
 189                 <bitfield name="MIU_WRITE_PACK_DISABLE" pos="31" type="boolean"/>
 190         </reg32>
 191         <reg32 offset="0x01fd" name="CP_CSQ_RB_STAT">
 192                 <bitfield name="RPTR" low="0" high="6" type="uint"/>
 193                 <bitfield name="WPTR" low="16" high="22" type="uint"/>
 194         </reg32>
 195         <reg32 offset="0x01fe" name="CP_CSQ_IB1_STAT">
 196                 <bitfield name="RPTR" low="0" high="6" type="uint"/>
 197                 <bitfield name="WPTR" low="16" high="22" type="uint"/>
 198         </reg32>
 199         <reg32 offset="0x01ff" name="CP_CSQ_IB2_STAT">
 200                 <bitfield name="RPTR" low="0" high="6" type="uint"/>
 201                 <bitfield name="WPTR" low="16" high="22" type="uint"/>
 202         </reg32>
 203
 204         <reg32 offset="0x0440" name="CP_NON_PREFETCH_CNTRS"/>
 205         <reg32 offset="0x0443" name="CP_STQ_ST_STAT"/>
 206         <reg32 offset="0x044d" name="CP_ST_BASE"/>
 207         <reg32 offset="0x044e" name="CP_ST_BUFSZ"/>
 208         <reg32 offset="0x044f" name="CP_MEQ_STAT"/>
 209         <reg32 offset="0x0452" name="CP_MIU_TAG_STAT"/>
 210         <reg32 offset="0x0454" name="CP_BIN_MASK_LO"/>
 211         <reg32 offset="0x0455" name="CP_BIN_MASK_HI"/>
 212         <reg32 offset="0x0456" name="CP_BIN_SELECT_LO"/>
 213         <reg32 offset="0x0457" name="CP_BIN_SELECT_HI"/>
 214         <reg32 offset="0x0458" name="CP_IB1_BASE"/>
 215         <reg32 offset="0x0459" name="CP_IB1_BUFSZ"/>
 216         <reg32 offset="0x045a" name="CP_IB2_BASE"/>
 217         <reg32 offset="0x045b" name="CP_IB2_BUFSZ"/>
 218         <reg32 offset="0x047f" name="CP_STAT">
 219                 <bitfield pos="31" name="CP_BUSY"/>
 220                 <bitfield pos="30" name="VS_EVENT_FIFO_BUSY"/>
 221                 <bitfield pos="29" name="PS_EVENT_FIFO_BUSY"/>
 222                 <bitfield pos="28" name="CF_EVENT_FIFO_BUSY"/>
 223                 <bitfield pos="27" name="RB_EVENT_FIFO_BUSY"/>
 224                 <bitfield pos="26" name="ME_BUSY"/>
 225                 <bitfield pos="25" name="MIU_WR_C_BUSY"/>
 226                 <bitfield pos="23" name="CP_3D_BUSY"/>
 227                 <bitfield pos="22" name="CP_NRT_BUSY"/>
 228                 <bitfield pos="21" name="RBIU_SCRATCH_BUSY"/>
 229                 <bitfield pos="20" name="RCIU_ME_BUSY"/>
 230                 <bitfield pos="19" name="RCIU_PFP_BUSY"/>
 231                 <bitfield pos="18" name="MEQ_RING_BUSY"/>
 232                 <bitfield pos="17" name="PFP_BUSY"/>
 233                 <bitfield pos="16" name="ST_QUEUE_BUSY"/>
 234                 <bitfield pos="13" name="INDIRECT2_QUEUE_BUSY"/>
 235                 <bitfield pos="12" name="INDIRECTS_QUEUE_BUSY"/>
 236                 <bitfield pos="11" name="RING_QUEUE_BUSY"/>
 237                 <bitfield pos="10" name="CSF_BUSY"/>
 238                 <bitfield pos="9"  name="CSF_ST_BUSY"/>
 239                 <bitfield pos="8"  name="EVENT_BUSY"/>
 240                 <bitfield pos="7"  name="CSF_INDIRECT2_BUSY"/>
 241                 <bitfield pos="6"  name="CSF_INDIRECTS_BUSY"/>
 242                 <bitfield pos="5"  name="CSF_RING_BUSY"/>
 243                 <bitfield pos="4"  name="RCIU_BUSY"/>
 244                 <bitfield pos="3"  name="RBIU_BUSY"/>
 245                 <bitfield pos="2"  name="MIU_RD_RETURN_BUSY"/>
 246                 <bitfield pos="1"  name="MIU_RD_REQ_BUSY"/>
 247                 <bitfield pos="0"  name="MIU_WR_BUSY"/>
 248         </reg32>
 249         <reg32 offset="0x0578" name="CP_SCRATCH_REG0" type="uint"/>
 250         <reg32 offset="0x0579" name="CP_SCRATCH_REG1" type="uint"/>
 251         <reg32 offset="0x057a" name="CP_SCRATCH_REG2" type="uint"/>
 252         <reg32 offset="0x057b" name="CP_SCRATCH_REG3" type="uint"/>
 253         <reg32 offset="0x057c" name="CP_SCRATCH_REG4" type="uint"/>
 254         <reg32 offset="0x057d" name="CP_SCRATCH_REG5" type="uint"/>
 255         <reg32 offset="0x057e" name="CP_SCRATCH_REG6" type="uint"/>
 256         <reg32 offset="0x057f" name="CP_SCRATCH_REG7" type="uint"/>
 257
 258         <reg32 offset="0x0600" name="CP_ME_VS_EVENT_SRC"/>
 259         <reg32 offset="0x0601" name="CP_ME_VS_EVENT_ADDR"/>
 260         <reg32 offset="0x0602" name="CP_ME_VS_EVENT_DATA"/>
 261         <reg32 offset="0x0603" name="CP_ME_VS_EVENT_ADDR_SWM"/>
 262         <reg32 offset="0x0604" name="CP_ME_VS_EVENT_DATA_SWM"/>
 263         <reg32 offset="0x0605" name="CP_ME_PS_EVENT_SRC"/>
 264         <reg32 offset="0x0606" name="CP_ME_PS_EVENT_ADDR"/>
 265         <reg32 offset="0x0607" name="CP_ME_PS_EVENT_DATA"/>
 266         <reg32 offset="0x0608" name="CP_ME_PS_EVENT_ADDR_SWM"/>
 267         <reg32 offset="0x0609" name="CP_ME_PS_EVENT_DATA_SWM"/>
 268         <reg32 offset="0x060a" name="CP_ME_CF_EVENT_SRC"/>
 269         <reg32 offset="0x060b" name="CP_ME_CF_EVENT_ADDR"/>
 270         <reg32 offset="0x060c" name="CP_ME_CF_EVENT_DATA" type="uint"/>
 271         <reg32 offset="0x060d" name="CP_ME_NRT_ADDR"/>
 272         <reg32 offset="0x060e" name="CP_ME_NRT_DATA"/>
 273         <reg32 offset="0x0612" name="CP_ME_VS_FETCH_DONE_SRC"/>
 274         <reg32 offset="0x0613" name="CP_ME_VS_FETCH_DONE_ADDR"/>
 275         <reg32 offset="0x0614" name="CP_ME_VS_FETCH_DONE_DATA"/>
 276
 277 </domain>
 278
 279 <!--
 280         Common between A3xx and A4xx:
 281  -->
 282
 283 <enum name="a3xx_regid">
 284   <value name="REGID_UNUSED" value="0xfc"/>
 285 </enum>
 286
 287 <enum name="a3xx_rop_code">
 288         <value name="ROP_CLEAR"         value="0"/>
 289         <value name="ROP_NOR"           value="1"/>
 290         <value name="ROP_AND_INVERTED"  value="2"/>
 291         <value name="ROP_COPY_INVERTED" value="3"/>
 292         <value name="ROP_AND_REVERSE"   value="4"/>
 293         <value name="ROP_INVERT"        value="5"/>
 294         <value name="ROP_XOR"           value="6"/>
 295         <value name="ROP_NAND"          value="7"/>
 296         <value name="ROP_AND"           value="8"/>
 297         <value name="ROP_EQUIV"         value="9"/>
 298         <value name="ROP_NOOP"          value="10"/>
 299         <value name="ROP_OR_INVERTED"   value="11"/>
 300         <value name="ROP_COPY"          value="12"/>
 301         <value name="ROP_OR_REVERSE"    value="13"/>
 302         <value name="ROP_OR"            value="14"/>
 303         <value name="ROP_SET"           value="15"/>
 304 </enum>
 305
 306 <enum name="a3xx_render_mode">
 307         <value name="RB_RENDERING_PASS" value="0"/>
 308         <value name="RB_TILING_PASS" value="1"/>
 309         <value name="RB_RESOLVE_PASS" value="2"/>
 310         <value name="RB_COMPUTE_PASS" value="3"/>
 311 </enum>
 312
 313 <enum name="a3xx_msaa_samples">
 314         <value name="MSAA_ONE" value="0"/>
 315         <value name="MSAA_TWO" value="1"/>
 316         <value name="MSAA_FOUR" value="2"/>
 317         <value name="MSAA_EIGHT" value="3"/>
 318 </enum>
 319
 320 <enum name="a3xx_threadmode">
 321         <value value="0" name="MULTI"/>
 322         <value value="1" name="SINGLE"/>
 323 </enum>
 324
 325 <enum name="a3xx_instrbuffermode">
 326         <!--
 327         When shader size goes above ~128 or so, blob switches to '0'
 328         and doesn't emit shader in cmdstream.  When either is '0' it
 329         doesn't get emitted via CP_LOAD_STATE.  When only one is
 330         '0' the other gets size 256-others_size.  So I think that:
 331                 BUFFER => execute out of state memory
 332                 CACHE  => use available state memory as local cache
 333         NOTE that when CACHE mode, also set CACHEINVALID flag!
 334
 335         TODO check if that 256 size is same for all a3xx
 336          -->
 337         <value value="0" name="CACHE"/>
 338         <value value="1" name="BUFFER"/>
 339 </enum>
 340
 341 <enum name="a3xx_threadsize">
 342         <value value="0" name="TWO_QUADS"/>
 343         <value value="1" name="FOUR_QUADS"/>
 344 </enum>
 345
 346 <enum name="a3xx_color_swap">
 347         <value name="WZYX" value="0"/>
 348         <value name="WXYZ" value="1"/>
 349         <value name="ZYXW" value="2"/>
 350         <value name="XYZW" value="3"/>
 351 </enum>
 352
 353 <enum name="a3xx_rb_blend_opcode">
 354         <value name="BLEND_DST_PLUS_SRC" value="0"/>
 355         <value name="BLEND_SRC_MINUS_DST" value="1"/>
 356         <value name="BLEND_DST_MINUS_SRC" value="2"/>
 357         <value name="BLEND_MIN_DST_SRC" value="3"/>
 358         <value name="BLEND_MAX_DST_SRC" value="4"/>
 359 </enum>
 360
 361 <enum name="a4xx_tess_spacing">
 362         <value name="EQUAL_SPACING" value="0"/>
 363         <value name="ODD_SPACING" value="2"/>
 364         <value name="EVEN_SPACING" value="3"/>
 365 </enum>
 366
 367 </database>
 368