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freedreno: Fix CP_COND_REG_EXEC bit positions
[mesa.git] / src / freedreno / registers / adreno_pm4.xml
1 <?xml version="1.0" encoding="UTF-8"?>
2 <database xmlns="http://nouveau.freedesktop.org/"
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
5
6 <enum name="vgt_event_type">
7 <value name="VS_DEALLOC" value="0"/>
8 <value name="PS_DEALLOC" value="1"/>
9 <value name="VS_DONE_TS" value="2"/>
10 <value name="PS_DONE_TS" value="3"/>
11 <value name="CACHE_FLUSH_TS" value="4"/>
12 <value name="CONTEXT_DONE" value="5"/>
13 <value name="CACHE_FLUSH" value="6"/>
14 <value name="HLSQ_FLUSH" value="7"/> <!-- on a3xx -->
15 <value name="VIZQUERY_START" value="7"/> <!-- on a2xx (??) -->
16 <value name="VIZQUERY_END" value="8"/>
17 <value name="SC_WAIT_WC" value="9"/>
18 <value name="WRITE_PRIMITIVE_COUNTS" value="9" variants="A6XX"/>
19 <value name="START_PRIMITIVE_CTRS" value="11" variants="A6XX"/>
20 <value name="STOP_PRIMITIVE_CTRS" value="12" variants="A6XX"/>
21 <value name="RST_PIX_CNT" value="13"/>
22 <value name="RST_VTX_CNT" value="14"/>
23 <value name="TILE_FLUSH" value="15"/>
24 <value name="STAT_EVENT" value="16"/>
25 <value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="20" variants="A2XX,A3XX,A4XX"/>
26 <value name="ZPASS_DONE" value="21"/>
27 <value name="CACHE_FLUSH_AND_INV_EVENT" value="22"/>
28 <value name="PERFCOUNTER_START" value="23" variants="A2XX,A3XX,A4XX"/>
29 <value name="PERFCOUNTER_STOP" value="24" variants="A2XX,A3XX,A4XX"/>
30 <value name="VS_FETCH_DONE" value="27"/>
31 <value name="FACENESS_FLUSH" value="28" variants="A2XX,A3XX,A4XX"/>
32
33 <!-- a5xx events -->
34 <value name="FLUSH_SO_0" value="17" variants="A5XX,A6XX"/>
35 <value name="FLUSH_SO_1" value="18" variants="A5XX,A6XX"/>
36 <value name="FLUSH_SO_2" value="19" variants="A5XX,A6XX"/>
37 <value name="FLUSH_SO_3" value="20" variants="A5XX,A6XX"/>
38 <value name="PC_CCU_INVALIDATE_DEPTH" value="24" variants="A5XX,A6XX"/>
39 <value name="PC_CCU_INVALIDATE_COLOR" value="25" variants="A5XX,A6XX"/>
40 <value name="UNK_1C" value="28" variants="A5XX,A6XX"/>
41 <value name="UNK_1D" value="29" variants="A5XX,A6XX"/>
42 <value name="BLIT" value="30" variants="A5XX,A6XX"/>
43 <value name="UNK_25" value="37" variants="A5XX"/>
44 <value name="LRZ_FLUSH" value="38" variants="A5XX,A6XX"/>
45 <value name="UNK_2C" value="44" variants="A5XX"/>
46 <value name="UNK_2D" value="45" variants="A5XX"/>
47
48 <!-- a6xx events -->
49 <value name="CACHE_INVALIDATE" value="49" variants="A6XX"/>
50 </enum>
51
52 <enum name="pc_di_primtype">
53 <value name="DI_PT_NONE" value="0"/>
54 <!-- POINTLIST_PSIZE is used on a3xx/a4xx when gl_PointSize is written: -->
55 <value name="DI_PT_POINTLIST_PSIZE" value="1"/>
56 <value name="DI_PT_LINELIST" value="2"/>
57 <value name="DI_PT_LINESTRIP" value="3"/>
58 <value name="DI_PT_TRILIST" value="4"/>
59 <value name="DI_PT_TRIFAN" value="5"/>
60 <value name="DI_PT_TRISTRIP" value="6"/>
61 <value name="DI_PT_LINELOOP" value="7"/> <!-- a22x, a3xx -->
62 <value name="DI_PT_RECTLIST" value="8"/>
63 <value name="DI_PT_POINTLIST" value="9"/>
64 <value name="DI_PT_LINE_ADJ" value="0xa"/>
65 <value name="DI_PT_LINESTRIP_ADJ" value="0xb"/>
66 <value name="DI_PT_TRI_ADJ" value="0xc"/>
67 <value name="DI_PT_TRISTRIP_ADJ" value="0xd"/>
68
69 <value name="DI_PT_PATCHES0" value="0x1f"/>
70 <value name="DI_PT_PATCHES1" value="0x20"/>
71 <value name="DI_PT_PATCHES2" value="0x21"/>
72 <value name="DI_PT_PATCHES3" value="0x22"/>
73 <value name="DI_PT_PATCHES4" value="0x23"/>
74 <value name="DI_PT_PATCHES5" value="0x24"/>
75 <value name="DI_PT_PATCHES6" value="0x25"/>
76 <value name="DI_PT_PATCHES7" value="0x26"/>
77 <value name="DI_PT_PATCHES8" value="0x27"/>
78 <value name="DI_PT_PATCHES9" value="0x28"/>
79 <value name="DI_PT_PATCHES10" value="0x29"/>
80 <value name="DI_PT_PATCHES11" value="0x2a"/>
81 <value name="DI_PT_PATCHES12" value="0x2b"/>
82 <value name="DI_PT_PATCHES13" value="0x2c"/>
83 <value name="DI_PT_PATCHES14" value="0x2d"/>
84 <value name="DI_PT_PATCHES15" value="0x2e"/>
85 <value name="DI_PT_PATCHES16" value="0x2f"/>
86 <value name="DI_PT_PATCHES17" value="0x30"/>
87 <value name="DI_PT_PATCHES18" value="0x31"/>
88 <value name="DI_PT_PATCHES19" value="0x32"/>
89 <value name="DI_PT_PATCHES20" value="0x33"/>
90 <value name="DI_PT_PATCHES21" value="0x34"/>
91 <value name="DI_PT_PATCHES22" value="0x35"/>
92 <value name="DI_PT_PATCHES23" value="0x36"/>
93 <value name="DI_PT_PATCHES24" value="0x37"/>
94 <value name="DI_PT_PATCHES25" value="0x38"/>
95 <value name="DI_PT_PATCHES26" value="0x39"/>
96 <value name="DI_PT_PATCHES27" value="0x3a"/>
97 <value name="DI_PT_PATCHES28" value="0x3b"/>
98 <value name="DI_PT_PATCHES29" value="0x3c"/>
99 <value name="DI_PT_PATCHES30" value="0x3d"/>
100 <value name="DI_PT_PATCHES31" value="0x3e"/>
101 </enum>
102
103 <enum name="pc_di_src_sel">
104 <value name="DI_SRC_SEL_DMA" value="0"/>
105 <value name="DI_SRC_SEL_IMMEDIATE" value="1"/>
106 <value name="DI_SRC_SEL_AUTO_INDEX" value="2"/>
107 <value name="DI_SRC_SEL_RESERVED" value="3"/>
108 </enum>
109
110 <enum name="pc_di_face_cull_sel">
111 <value name="DI_FACE_CULL_NONE" value="0"/>
112 <value name="DI_FACE_CULL_FETCH" value="1"/>
113 <value name="DI_FACE_BACKFACE_CULL" value="2"/>
114 <value name="DI_FACE_FRONTFACE_CULL" value="3"/>
115 </enum>
116
117 <enum name="pc_di_index_size">
118 <value name="INDEX_SIZE_IGN" value="0"/>
119 <value name="INDEX_SIZE_16_BIT" value="0"/>
120 <value name="INDEX_SIZE_32_BIT" value="1"/>
121 <value name="INDEX_SIZE_8_BIT" value="2"/>
122 <value name="INDEX_SIZE_INVALID"/>
123 </enum>
124
125 <enum name="pc_di_vis_cull_mode">
126 <value name="IGNORE_VISIBILITY" value="0"/>
127 <value name="USE_VISIBILITY" value="1"/>
128 </enum>
129
130 <enum name="adreno_pm4_packet_type">
131 <value name="CP_TYPE0_PKT" value="0x00000000"/>
132 <value name="CP_TYPE1_PKT" value="0x40000000"/>
133 <value name="CP_TYPE2_PKT" value="0x80000000"/>
134 <value name="CP_TYPE3_PKT" value="0xc0000000"/>
135 <value name="CP_TYPE4_PKT" value="0x40000000"/>
136 <value name="CP_TYPE7_PKT" value="0x70000000"/>
137 </enum>
138
139 <!--
140 Note that in some cases, the same packet id is recycled on a later
141 generation, so variants attribute is used to distinguish. They
142 may not be completely accurate, we would probably have to analyze
143 the pfp and me/pm4 firmware to verify the packet is actually
144 handled on a particular generation. But it is at least enough to
145 disambiguate the packet-id's that were re-used for different
146 packets starting with a5xx.
147 -->
148 <enum name="adreno_pm4_type3_packets">
149 <doc>initialize CP's micro-engine</doc>
150 <value name="CP_ME_INIT" value="0x48"/>
151 <doc>skip N 32-bit words to get to the next packet</doc>
152 <value name="CP_NOP" value="0x10"/>
153 <doc>
154 indirect buffer dispatch. prefetch parser uses this packet
155 type to determine whether to pre-fetch the IB
156 </doc>
157 <value name="CP_PREEMPT_ENABLE" value="0x1c"/>
158 <value name="CP_PREEMPT_TOKEN" value="0x1e"/>
159 <value name="CP_INDIRECT_BUFFER" value="0x3f"/>
160 <doc>
161 Takes the same arguments as CP_INDIRECT_BUFFER, but jumps to
162 another buffer at the same level. Must be at the end of IB, and
163 doesn't work with draw state IB's.
164 </doc>
165 <value name="CP_INDIRECT_BUFFER_CHAIN" value="0x57" variants="A5XX-"/>
166 <doc>indirect buffer dispatch. same as IB, but init is pipelined</doc>
167 <value name="CP_INDIRECT_BUFFER_PFD" value="0x37"/>
168 <doc>wait for the IDLE state of the engine</doc>
169 <value name="CP_WAIT_FOR_IDLE" value="0x26"/>
170 <doc>wait until a register or memory location is a specific value</doc>
171 <value name="CP_WAIT_REG_MEM" value="0x3c"/>
172 <doc>wait until a register location is equal to a specific value</doc>
173 <value name="CP_WAIT_REG_EQ" value="0x52"/>
174 <doc>wait until a register location is >= a specific value</doc>
175 <value name="CP_WAIT_REG_GTE" value="0x53" variants="A2XX,A3XX,A4XX"/>
176 <doc>wait until a read completes</doc>
177 <value name="CP_WAIT_UNTIL_READ" value="0x5c" variants="A2XX,A3XX,A4XX"/>
178 <doc>wait until all base/size writes from an IB_PFD packet have completed</doc>
179 <value name="CP_WAIT_IB_PFD_COMPLETE" value="0x5d"/>
180 <doc>register read/modify/write</doc>
181 <value name="CP_REG_RMW" value="0x21"/>
182 <doc>Set binning configuration registers</doc>
183 <value name="CP_SET_BIN_DATA" value="0x2f" variants="A2XX,A3XX,A4XX"/>
184 <value name="CP_SET_BIN_DATA5" value="0x2f" variants="A5XX,A6XX"/>
185 <doc>reads register in chip and writes to memory</doc>
186 <value name="CP_REG_TO_MEM" value="0x3e"/>
187 <doc>write N 32-bit words to memory</doc>
188 <value name="CP_MEM_WRITE" value="0x3d"/>
189 <doc>write CP_PROG_COUNTER value to memory</doc>
190 <value name="CP_MEM_WRITE_CNTR" value="0x4f"/>
191 <doc>conditional execution of a sequence of packets</doc>
192 <value name="CP_COND_EXEC" value="0x44"/>
193 <doc>conditional write to memory or register</doc>
194 <value name="CP_COND_WRITE" value="0x45" variants="A2XX,A3XX,A4XX"/>
195 <value name="CP_COND_WRITE5" value="0x45" variants="A5XX,A6XX"/>
196 <doc>generate an event that creates a write to memory when completed</doc>
197 <value name="CP_EVENT_WRITE" value="0x46"/>
198 <doc>generate a VS|PS_done event</doc>
199 <value name="CP_EVENT_WRITE_SHD" value="0x58"/>
200 <doc>generate a cache flush done event</doc>
201 <value name="CP_EVENT_WRITE_CFL" value="0x59"/>
202 <doc>generate a z_pass done event</doc>
203 <value name="CP_EVENT_WRITE_ZPD" value="0x5b"/>
204 <doc>
205 not sure the real name, but this seems to be what is used for
206 opencl, instead of CP_DRAW_INDX..
207 </doc>
208 <value name="CP_RUN_OPENCL" value="0x31"/>
209 <doc>initiate fetch of index buffer and draw</doc>
210 <value name="CP_DRAW_INDX" value="0x22"/>
211 <doc>draw using supplied indices in packet</doc>
212 <value name="CP_DRAW_INDX_2" value="0x36" variants="A2XX,A3XX,A4XX"/> <!-- this is something different on a6xx and unused on a5xx -->
213 <doc>initiate fetch of index buffer and binIDs and draw</doc>
214 <value name="CP_DRAW_INDX_BIN" value="0x34" variants="A2XX,A3XX,A4XX"/>
215 <doc>initiate fetch of bin IDs and draw using supplied indices</doc>
216 <value name="CP_DRAW_INDX_2_BIN" value="0x35" variants="A2XX,A3XX,A4XX"/>
217 <doc>begin/end initiator for viz query extent processing</doc>
218 <value name="CP_VIZ_QUERY" value="0x23" variants="A2XX,A3XX,A4XX"/>
219 <doc>fetch state sub-blocks and initiate shader code DMAs</doc>
220 <value name="CP_SET_STATE" value="0x25"/>
221 <doc>load constant into chip and to memory</doc>
222 <value name="CP_SET_CONSTANT" value="0x2d"/>
223 <doc>load sequencer instruction memory (pointer-based)</doc>
224 <value name="CP_IM_LOAD" value="0x27"/>
225 <doc>load sequencer instruction memory (code embedded in packet)</doc>
226 <value name="CP_IM_LOAD_IMMEDIATE" value="0x2b"/>
227 <doc>load constants from a location in memory</doc>
228 <value name="CP_LOAD_CONSTANT_CONTEXT" value="0x2e" variants="A2XX"/>
229 <doc>selective invalidation of state pointers</doc>
230 <value name="CP_INVALIDATE_STATE" value="0x3b"/>
231 <doc>dynamically changes shader instruction memory partition</doc>
232 <value name="CP_SET_SHADER_BASES" value="0x4a" variants="A2XX,A3XX,A4XX"/>
233 <doc>sets the 64-bit BIN_MASK register in the PFP</doc>
234 <value name="CP_SET_BIN_MASK" value="0x50" variants="A2XX,A3XX,A4XX"/>
235 <doc>sets the 64-bit BIN_SELECT register in the PFP</doc>
236 <value name="CP_SET_BIN_SELECT" value="0x51"/>
237 <doc>updates the current context, if needed</doc>
238 <value name="CP_CONTEXT_UPDATE" value="0x5e"/>
239 <doc>generate interrupt from the command stream</doc>
240 <value name="CP_INTERRUPT" value="0x40"/>
241 <doc>copy sequencer instruction memory to system memory</doc>
242 <value name="CP_IM_STORE" value="0x2c" variants="A2XX"/>
243
244 <!-- For a20x -->
245 <!-- TODO handle variants..
246 <doc>
247 Program an offset that will added to the BIN_BASE value of
248 the 3D_DRAW_INDX_BIN packet
249 </doc>
250 <value name="CP_SET_BIN_BASE_OFFSET" value="0x4b"/>
251 -->
252
253 <!-- for a22x -->
254 <doc>
255 sets draw initiator flags register in PFP, gets bitwise-ORed into
256 every draw initiator
257 </doc>
258 <value name="CP_SET_DRAW_INIT_FLAGS" value="0x4b"/>
259 <doc>sets the register protection mode</doc>
260 <value name="CP_SET_PROTECTED_MODE" value="0x5f"/>
261
262 <value name="CP_BOOTSTRAP_UCODE" value="0x6f"/>
263
264 <!-- for a3xx -->
265 <doc>load high level sequencer command</doc>
266 <value name="CP_LOAD_STATE" value="0x30" variants="A3XX"/>
267 <value name="CP_LOAD_STATE4" value="0x30" variants="A4XX,A5XX"/>
268 <doc>Conditionally load a IB based on a flag, prefetch enabled</doc>
269 <value name="CP_COND_INDIRECT_BUFFER_PFE" value="0x3a"/>
270 <doc>Conditionally load a IB based on a flag, prefetch disabled</doc>
271 <value name="CP_COND_INDIRECT_BUFFER_PFD" value="0x32" variants="A3XX"/>
272 <doc>Load a buffer with pre-fetch enabled</doc>
273 <value name="CP_INDIRECT_BUFFER_PFE" value="0x3f" variants="A5XX"/>
274 <doc>Set bin (?)</doc>
275 <value name="CP_SET_BIN" value="0x4c" variants="A2XX"/>
276
277 <doc>test 2 memory locations to dword values specified</doc>
278 <value name="CP_TEST_TWO_MEMS" value="0x71"/>
279
280 <doc>Write register, ignoring context state for context sensitive registers</doc>
281 <value name="CP_REG_WR_NO_CTXT" value="0x78"/>
282
283 <doc>Record the real-time when this packet is processed by PFP</doc>
284 <value name="CP_RECORD_PFP_TIMESTAMP" value="0x11"/>
285
286 <!-- Used to switch GPU between secure and non-secure modes -->
287 <value name="CP_SET_SECURE_MODE" value="0x66"/>
288
289 <doc>PFP waits until the FIFO between the PFP and the ME is empty</doc>
290 <value name="CP_WAIT_FOR_ME" value="0x13"/>
291
292 <!-- for a4xx -->
293 <doc>
294 Used a bit like CP_SET_CONSTANT on a2xx, but can write multiple
295 groups of registers. Looks like it can be used to create state
296 objects in GPU memory, and on state change only emit pointer
297 (via CP_SET_DRAW_STATE), which should be nice for reducing CPU
298 overhead:
299
300 (A4x) save PM4 stream pointers to execute upon a visible draw
301 </doc>
302 <value name="CP_SET_DRAW_STATE" value="0x43" variants="A4XX,A5XX,A6XX"/>
303 <value name="CP_DRAW_INDX_OFFSET" value="0x38"/>
304 <value name="CP_DRAW_INDIRECT" value="0x28" variants="A4XX,A5XX,A6XX"/>
305 <value name="CP_DRAW_INDX_INDIRECT" value="0x29" variants="A4XX,A5XX,A6XX"/>
306 <value name="CP_DRAW_AUTO" value="0x24"/>
307
308 <value name="CP_UNKNOWN_19" value="0x19"/>
309
310 <doc>set to 1 for fastclear..:</doc>
311 <value name="CP_UNKNOWN_1A" value="0x1a"/>
312
313 <value name="CP_UNKNOWN_4E" value="0x4e"/>
314
315 <doc>
316 for A4xx
317 Write to register with address that does not fit into type-0 pkt
318 </doc>
319 <value name="CP_WIDE_REG_WRITE" value="0x74" variants="A4XX"/>
320
321 <doc>copy from ME scratch RAM to a register</doc>
322 <value name="CP_SCRATCH_TO_REG" value="0x4d"/>
323
324 <doc>Copy from REG to ME scratch RAM</doc>
325 <value name="CP_REG_TO_SCRATCH" value="0x4a"/>
326
327 <doc>Wait for memory writes to complete</doc>
328 <value name="CP_WAIT_MEM_WRITES" value="0x12"/>
329
330 <doc>Conditional execution based on register comparison</doc>
331 <value name="CP_COND_REG_EXEC" value="0x47"/>
332
333 <doc>Memory to REG copy</doc>
334 <value name="CP_MEM_TO_REG" value="0x42"/>
335
336 <value name="CP_EXEC_CS_INDIRECT" value="0x41" variants="A4XX,A5XX,A6XX"/>
337 <value name="CP_EXEC_CS" value="0x33"/>
338
339 <doc>
340 for a5xx
341 </doc>
342 <value name="CP_PERFCOUNTER_ACTION" value="0x50" variants="A5XX"/>
343 <!-- switches SMMU pagetable, used on a5xx only -->
344 <value name="CP_SMMU_TABLE_UPDATE" value="0x53" variants="A5XX,A6XX"/>
345 <!-- for a6xx -->
346 <doc>Tells CP the current mode of GPU operation</doc>
347 <value name="CP_SET_MARKER" value="0x65" variants="A6XX"/>
348 <doc>Instruct CP to set a few internal CP registers</doc>
349 <value name="CP_SET_PSEUDO_REG" value="0x56" variants="A6XX"/>
350 <!--
351 pairs of regid and value.. seems to be used to program some TF
352 related regs:
353 -->
354 <value name="CP_CONTEXT_REG_BUNCH" value="0x5c" variants="A5XX,A6XX"/>
355 <!-- A5XX Enable yield in RB only -->
356 <value name="CP_YIELD_ENABLE" value="0x1c" variants="A5XX"/>
357 <value name="CP_SKIP_IB2_ENABLE_GLOBAL" value="0x1d" variants="A5XX,A6XX"/>
358 <value name="CP_SKIP_IB2_ENABLE_LOCAL" value="0x23" variants="A5XX,A6XX"/>
359 <value name="CP_SET_SUBDRAW_SIZE" value="0x35" variants="A5XX,A6XX"/>
360 <value name="CP_SET_VISIBILITY_OVERRIDE" value="0x64" variants="A5XX,A6XX"/>
361 <!-- Enable/Disable/Defer A5x global preemption model -->
362 <value name="CP_PREEMPT_ENABLE_GLOBAL" value="0x69" variants="A5XX"/>
363 <!-- Enable/Disable A5x local preemption model -->
364 <value name="CP_PREEMPT_ENABLE_LOCAL" value="0x6a" variants="A5XX"/>
365 <!-- Yield token on a5xx similar to CP_PREEMPT on a4xx -->
366 <value name="CP_CONTEXT_SWITCH_YIELD" value="0x6b" variants="A5XX"/>
367 <!-- Inform CP about current render mode (needed for a5xx preemption) -->
368 <value name="CP_SET_RENDER_MODE" value="0x6c" variants="A5XX"/>
369 <value name="CP_COMPUTE_CHECKPOINT" value="0x6e" variants="A5XX"/>
370 <!-- check if this works on earlier.. -->
371 <value name="CP_MEM_TO_MEM" value="0x73" variants="A5XX,A6XX"/>
372 <value name="CP_BLIT" value="0x2c" variants="A5XX,A6XX"/>
373
374 <!-- Test specified bit in specified register and set predicate -->
375 <value name="CP_REG_TEST" value="0x39" variants="A5XX,A6XX"/>
376
377 <!--
378 Seems to set the mode flags which control which CP_SET_DRAW_STATE
379 packets are executed, based on their ENABLE_MASK values
380
381 CP_SET_MODE w/ payload of 0x1 seems to cause CP_SET_DRAW_STATE
382 packets w/ ENABLE_MASK & 0x6 to execute immediately
383 -->
384 <value name="CP_SET_MODE" value="0x63" variants="A6XX"/>
385
386 <!--
387 Seems like there are now separate blocks of state for VS vs FS/CS
388 (probably these amounts to geometry vs fragments so that geometry
389 stage of the pipeline for next draw can start while fragment stage
390 of current draw is still running. The format of the payload of the
391 packets is the same, the only difference is the offsets of the regs
392 the firmware code that handles the packet writes.
393
394 Note that for CL, starting with a6xx, the preferred # of local
395 threads is no longer the same as the max, implying that the shader
396 core can now run warps from unrelated shaders (ie.
397 CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE vs
398 CL_KERNEL_WORK_GROUP_SIZE)
399 -->
400 <value name="CP_LOAD_STATE6_GEOM" value="0x32" variants="A6XX"/>
401 <value name="CP_LOAD_STATE6_FRAG" value="0x34" variants="A6XX"/>
402 <!--
403 Note: For IBO state (Image/SSBOs) which have shared state across
404 shader stages, for 3d pipeline CP_LOAD_STATE6 is used. But for
405 compute shaders, CP_LOAD_STATE6_FRAG is used. Possibly they are
406 interchangable.
407 -->
408 <value name="CP_LOAD_STATE6" value="0x36" variants="A6XX"/>
409
410 <!-- internal packets: -->
411 <value name="IN_IB_PREFETCH_END" value="0x17" variants="A2XX"/>
412 <value name="IN_SUBBLK_PREFETCH" value="0x1f" variants="A2XX"/>
413 <value name="IN_INSTR_PREFETCH" value="0x20" variants="A2XX"/>
414 <value name="IN_INSTR_MATCH" value="0x47" variants="A2XX"/>
415 <value name="IN_CONST_PREFETCH" value="0x49" variants="A2XX"/>
416 <value name="IN_INCR_UPDT_STATE" value="0x55" variants="A2XX"/>
417 <value name="IN_INCR_UPDT_CONST" value="0x56" variants="A2XX"/>
418 <value name="IN_INCR_UPDT_INSTR" value="0x57" variants="A2XX"/>
419
420 <!-- jmptable entry used to handle type4 packet on a5xx+: -->
421 <value name="PKT4" value="0x04" variants="A5XX,A6XX"/>
422
423 <!-- TODO do these exist on A5xx? -->
424 <value name="CP_SCRATCH_WRITE" value="0x4c" variants="A6XX"/>
425 <value name="CP_REG_TO_MEM_OFFSET_MEM" value="0x74" variants="A6XX"/>
426 <value name="CP_REG_TO_MEM_OFFSET_REG" value="0x72" variants="A6XX"/>
427 <value name="CP_WAIT_MEM_GTE" value="0x14" variants="A6XX"/>
428 <value name="CP_WAIT_TWO_REGS" value="0x70" variants="A6XX"/>
429 <value name="CP_MEMCPY" value="0x75" variants="A6XX"/>
430 <value name="CP_SET_BIN_DATA5_OFFSET" value="0x2e" variants="A6XX"/>
431 <value name="CP_SET_CTXSWITCH_IB" value="0x55" variants="A6XX"/>
432
433 <!--
434 Seems to always have the payload:
435 00000002 00008801 00004010
436 or:
437 00000002 00008801 00004090
438 or:
439 00000002 00008801 00000010
440 00000002 00008801 00010010
441 00000002 00008801 00d64010
442 ...
443 Note set for compute shaders..
444 Is 0x8801 a register offset?
445 This appears to be a special sort of register write packet
446 more or less, but the firmware has some special handling..
447 Seems like it intercepts/modifies certain register offsets,
448 but others are treated like a normal PKT4 reg write. I
449 guess there are some registers that the fw controls certain
450 bits.
451 -->
452 <value name="CP_REG_WRITE" value="0x6d" variants="A6XX"/>
453
454 </enum>
455
456
457 <domain name="CP_LOAD_STATE" width="32">
458 <doc>Load state, a3xx (and later?)</doc>
459 <enum name="adreno_state_block">
460 <value name="SB_VERT_TEX" value="0"/>
461 <value name="SB_VERT_MIPADDR" value="1"/>
462 <value name="SB_FRAG_TEX" value="2"/>
463 <value name="SB_FRAG_MIPADDR" value="3"/>
464 <value name="SB_VERT_SHADER" value="4"/>
465 <value name="SB_GEOM_SHADER" value="5"/>
466 <value name="SB_FRAG_SHADER" value="6"/>
467 <value name="SB_COMPUTE_SHADER" value="7"/>
468 </enum>
469 <enum name="adreno_state_type">
470 <value name="ST_SHADER" value="0"/>
471 <value name="ST_CONSTANTS" value="1"/>
472 </enum>
473 <enum name="adreno_state_src">
474 <value name="SS_DIRECT" value="0">
475 <doc>inline with the CP_LOAD_STATE packet</doc>
476 </value>
477 <value name="SS_INVALID_ALL_IC" value="2"/>
478 <value name="SS_INVALID_PART_IC" value="3"/>
479 <value name="SS_INDIRECT" value="4">
480 <doc>in buffer pointed to by EXT_SRC_ADDR</doc>
481 </value>
482 <value name="SS_INDIRECT_TCM" value="5"/>
483 <value name="SS_INDIRECT_STM" value="6"/>
484 </enum>
485 <reg32 offset="0" name="0">
486 <bitfield name="DST_OFF" low="0" high="15" type="uint"/>
487 <bitfield name="STATE_SRC" low="16" high="18" type="adreno_state_src"/>
488 <bitfield name="STATE_BLOCK" low="19" high="21" type="adreno_state_block"/>
489 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
490 </reg32>
491 <reg32 offset="1" name="1">
492 <bitfield name="STATE_TYPE" low="0" high="1" type="adreno_state_type"/>
493 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
494 </reg32>
495 </domain>
496
497 <domain name="CP_LOAD_STATE4" width="32" varset="chip">
498 <doc>Load state, a4xx+</doc>
499 <enum name="a4xx_state_block">
500 <!--
501 unknown: 0x7 and 0xf <- seen in compute shader
502
503 STATE_BLOCK = 0x6, STATE_TYPE = 0x2 possibly used for preemption?
504 Seen in some GL shaders. Payload is NUM_UNIT dwords, and it contains
505 the gpuaddr of the following shader constants block. DST_OFF seems
506 to specify which shader stage:
507
508 16 -> vert
509 36 -> tcs
510 56 -> tes
511 76 -> geom
512 96 -> frag
513
514 Example:
515
516 opcode: CP_LOAD_STATE4 (30) (12 dwords)
517 { DST_OFF = 16 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = 0x6 | NUM_UNIT = 4 }
518 { STATE_TYPE = 0x2 | EXT_SRC_ADDR = 0 }
519 { EXT_SRC_ADDR_HI = 0 }
520 0000: c0264100 00000000 00000000 00000000
521 0000: 70b0000b 01180010 00000002 00000000 c0264100 00000000 00000000 00000000
522
523 opcode: CP_LOAD_STATE4 (30) (4 dwords)
524 { DST_OFF = 16 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
525 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0xc0264100 }
526 { EXT_SRC_ADDR_HI = 0 }
527 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000
528 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000
529 0000: 00000040 0000000c 00000000 00000000 00000000 00000000 00000000 00000000
530
531 STATE_BLOCK = 0x6, STATE_TYPE = 0x1, seen in compute shader. NUM_UNITS * 2 dwords.
532
533 -->
534 <value name="SB4_VS_TEX" value="0x0"/>
535 <value name="SB4_HS_TEX" value="0x1"/> <!-- aka. TCS -->
536 <value name="SB4_DS_TEX" value="0x2"/> <!-- aka. TES -->
537 <value name="SB4_GS_TEX" value="0x3"/>
538 <value name="SB4_FS_TEX" value="0x4"/>
539 <value name="SB4_CS_TEX" value="0x5"/>
540 <value name="SB4_VS_SHADER" value="0x8"/>
541 <value name="SB4_HS_SHADER" value="0x9"/>
542 <value name="SB4_DS_SHADER" value="0xa"/>
543 <value name="SB4_GS_SHADER" value="0xb"/>
544 <value name="SB4_FS_SHADER" value="0xc"/>
545 <value name="SB4_CS_SHADER" value="0xd"/>
546 <!--
547 for SSBO, STATE_TYPE=0 appears to be addresses (four dwords each),
548 STATE_TYPE=1 sizes, STATE_TYPE=2 addresses again (two dwords each)
549
550 Compute has it's own dedicated SSBO state, it seems, but the rest
551 of the stages share state
552 -->
553 <value name="SB4_SSBO" value="0xe"/>
554 <value name="SB4_CS_SSBO" value="0xf"/>
555 </enum>
556 <enum name="a4xx_state_type">
557 <value name="ST4_SHADER" value="0"/>
558 <value name="ST4_CONSTANTS" value="1"/>
559 <value name="ST4_UBO" value="2"/>
560 </enum>
561 <enum name="a4xx_state_src">
562 <value name="SS4_DIRECT" value="0"/>
563 <value name="SS4_INDIRECT" value="2"/>
564 </enum>
565 <reg32 offset="0" name="0">
566 <bitfield name="DST_OFF" low="0" high="13" type="uint"/>
567 <bitfield name="STATE_SRC" low="16" high="17" type="a4xx_state_src"/>
568 <bitfield name="STATE_BLOCK" low="18" high="21" type="a4xx_state_block"/>
569 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
570 </reg32>
571 <reg32 offset="1" name="1">
572 <bitfield name="STATE_TYPE" low="0" high="1" type="a4xx_state_type"/>
573 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
574 </reg32>
575 <reg32 offset="2" name="2" variants="A5XX-">
576 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
577 </reg32>
578 </domain>
579
580 <!-- looks basically same CP_LOAD_STATE4 -->
581 <domain name="CP_LOAD_STATE6" width="32" varset="chip">
582 <doc>Load state, a6xx+</doc>
583 <enum name="a6xx_state_block">
584 <value name="SB6_VS_TEX" value="0x0"/>
585 <value name="SB6_HS_TEX" value="0x1"/> <!-- aka. TCS -->
586 <value name="SB6_DS_TEX" value="0x2"/> <!-- aka. TES -->
587 <value name="SB6_GS_TEX" value="0x3"/>
588 <value name="SB6_FS_TEX" value="0x4"/>
589 <value name="SB6_CS_TEX" value="0x5"/>
590 <value name="SB6_VS_SHADER" value="0x8"/>
591 <value name="SB6_HS_SHADER" value="0x9"/>
592 <value name="SB6_DS_SHADER" value="0xa"/>
593 <value name="SB6_GS_SHADER" value="0xb"/>
594 <value name="SB6_FS_SHADER" value="0xc"/>
595 <value name="SB6_CS_SHADER" value="0xd"/>
596 <value name="SB6_IBO" value="0xe"/>
597 <value name="SB6_CS_IBO" value="0xf"/>
598 </enum>
599 <enum name="a6xx_state_type">
600 <value name="ST6_SHADER" value="0"/>
601 <value name="ST6_CONSTANTS" value="1"/>
602 <value name="ST6_UBO" value="2"/>
603 <value name="ST6_IBO" value="3"/>
604 </enum>
605 <enum name="a6xx_state_src">
606 <value name="SS6_DIRECT" value="0"/>
607 <value name="SS6_INDIRECT" value="2"/>
608 </enum>
609 <reg32 offset="0" name="0">
610 <bitfield name="DST_OFF" low="0" high="13" type="uint"/>
611 <bitfield name="STATE_TYPE" low="14" high="15" type="a6xx_state_type"/>
612 <bitfield name="STATE_SRC" low="16" high="17" type="a6xx_state_src"/>
613 <bitfield name="STATE_BLOCK" low="18" high="21" type="a6xx_state_block"/>
614 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
615 </reg32>
616 <reg32 offset="1" name="1">
617 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
618 </reg32>
619 <reg32 offset="2" name="2">
620 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
621 </reg32>
622 </domain>
623
624 <bitset name="vgt_draw_initiator" inline="yes">
625 <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
626 <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
627 <bitfield name="VIS_CULL" low="9" high="10" type="pc_di_vis_cull_mode"/>
628 <bitfield name="INDEX_SIZE" pos="11" type="pc_di_index_size"/>
629 <bitfield name="NOT_EOP" pos="12" type="boolean"/>
630 <bitfield name="SMALL_INDEX" pos="13" type="boolean"/>
631 <bitfield name="PRE_DRAW_INITIATOR_ENABLE" pos="14" type="boolean"/>
632 <bitfield name="NUM_INSTANCES" low="24" high="31" type="uint"/>
633 </bitset>
634
635 <!-- changed on a4xx: -->
636 <enum name="a4xx_index_size">
637 <value name="INDEX4_SIZE_8_BIT" value="0"/>
638 <value name="INDEX4_SIZE_16_BIT" value="1"/>
639 <value name="INDEX4_SIZE_32_BIT" value="2"/>
640 </enum>
641
642 <enum name="a6xx_patch_type">
643 <value name="TESS_QUADS" value="0"/>
644 <value name="TESS_TRIANGLES" value="1"/>
645 <value name="TESS_ISOLINES" value="2"/>
646 </enum>
647
648 <bitset name="vgt_draw_initiator_a4xx" inline="yes">
649 <!-- When the 0x20 bit is set, it's the number of patch vertices - 1 -->
650 <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
651 <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
652 <bitfield name="VIS_CULL" low="8" high="9" type="pc_di_vis_cull_mode"/>
653 <bitfield name="INDEX_SIZE" low="10" high="11" type="a4xx_index_size"/>
654 <bitfield name="PATCH_TYPE" low="12" high="13" type="a6xx_patch_type"/>
655 <bitfield name="GS_ENABLE" pos="16" type="boolean"/>
656 <bitfield name="TESS_ENABLE" pos="17" type="boolean"/>
657 </bitset>
658
659 <domain name="CP_DRAW_INDX" width="32">
660 <reg32 offset="0" name="0">
661 <bitfield name="VIZ_QUERY" low="0" high="31"/>
662 </reg32>
663 <reg32 offset="1" name="1" type="vgt_draw_initiator"/>
664 <reg32 offset="2" name="2">
665 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
666 </reg32>
667 <reg32 offset="3" name="3">
668 <bitfield name="INDX_BASE" low="0" high="31"/>
669 </reg32>
670 <reg32 offset="4" name="4">
671 <bitfield name="INDX_SIZE" low="0" high="31"/>
672 </reg32>
673 </domain>
674
675 <domain name="CP_DRAW_INDX_2" width="32">
676 <reg32 offset="0" name="0">
677 <bitfield name="VIZ_QUERY" low="0" high="31"/>
678 </reg32>
679 <reg32 offset="1" name="1" type="vgt_draw_initiator"/>
680 <reg32 offset="2" name="2">
681 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
682 </reg32>
683 <!-- followed by NUM_INDICES indices.. -->
684 </domain>
685
686 <domain name="CP_DRAW_INDX_OFFSET" width="32">
687 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
688 <reg32 offset="1" name="1">
689 <bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/>
690 </reg32>
691 <reg32 offset="2" name="2">
692 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
693 </reg32>
694 <reg32 offset="3" name="3">
695 </reg32>
696
697 <stripe variants="A5XX-">
698 <reg32 offset="4" name="4">
699 <bitfield name="INDX_BASE_LO" low="0" high="31"/>
700 </reg32>
701 <reg32 offset="5" name="5">
702 <bitfield name="INDX_BASE_HI" low="0" high="31"/>
703 </reg32>
704 <reg32 offset="6" name="6">
705 <bitfield name="INDX_SIZE" low="0" high="31"/>
706 </reg32>
707 </stripe>
708
709 <reg32 offset="4" name="4">
710 <bitfield name="INDX_BASE" low="0" high="31"/>
711 </reg32>
712
713 <reg32 offset="5" name="5">
714 <bitfield name="INDX_SIZE" low="0" high="31"/>
715 </reg32>
716 </domain>
717
718 <domain name="CP_DRAW_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
719 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
720 <reg32 offset="1" name="1">
721 <bitfield name="INDIRECT" low="0" high="31"/>
722 </reg32>
723 <stripe variants="A5XX-">
724 <reg32 offset="2" name="2">
725 <bitfield name="INDIRECT_HI" low="0" high="31"/>
726 </reg32>
727 </stripe>
728 </domain>
729
730 <domain name="CP_DRAW_INDX_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
731 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
732 <stripe variants="A4XX">
733 <reg32 offset="1" name="1">
734 <bitfield name="INDX_BASE" low="0" high="31"/>
735 </reg32>
736 <reg32 offset="2" name="2">
737 <!-- max # of bytes in index buffer -->
738 <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/>
739 </reg32>
740 <reg32 offset="3" name="3">
741 <bitfield name="INDIRECT" low="0" high="31"/>
742 </reg32>
743 </stripe>
744 <stripe variants="A5XX-">
745 <reg32 offset="1" name="1">
746 <bitfield name="INDX_BASE_LO" low="0" high="31"/>
747 </reg32>
748 <reg32 offset="2" name="2">
749 <bitfield name="INDX_BASE_HI" low="0" high="31"/>
750 </reg32>
751 <reg32 offset="3" name="3">
752 <!-- max # of elements in index buffer -->
753 <bitfield name="MAX_INDICES" low="0" high="31" type="uint"/>
754 </reg32>
755 <reg32 offset="4" name="4">
756 <bitfield name="INDIRECT_LO" low="0" high="31"/>
757 </reg32>
758 <reg32 offset="5" name="5">
759 <bitfield name="INDIRECT_HI" low="0" high="31"/>
760 </reg32>
761 </stripe>
762 </domain>
763
764 <domain name="CP_SET_DRAW_STATE" width="32" varset="chip" variants="A4XX-">
765 <array offset="0" name="" stride="3" length="100">
766 <reg32 offset="0" name="0">
767 <bitfield name="COUNT" low="0" high="15" type="uint"/>
768 <bitfield name="DIRTY" pos="16" type="boolean"/>
769 <bitfield name="DISABLE" pos="17" type="boolean"/>
770 <bitfield name="DISABLE_ALL_GROUPS" pos="18" type="boolean"/>
771 <bitfield name="LOAD_IMMED" pos="19" type="boolean"/>
772 <bitfield name="BINNING" pos="20" variants="A6XX-" type="boolean"/>
773 <bitfield name="GMEM" pos="21" variants="A6XX-" type="boolean"/>
774 <bitfield name="SYSMEM" pos="22" variants="A6XX-" type="boolean"/>
775 <bitfield name="GROUP_ID" low="24" high="28" type="uint"/>
776 </reg32>
777 <reg32 offset="1" name="1">
778 <bitfield name="ADDR_LO" low="0" high="31" type="hex"/>
779 </reg32>
780 <reg32 offset="2" name="2" variants="A5XX-">
781 <bitfield name="ADDR_HI" low="0" high="31" type="hex"/>
782 </reg32>
783 </array>
784 </domain>
785
786 <domain name="CP_SET_BIN" width="32">
787 <doc>value at offset 0 always seems to be 0x00000000..</doc>
788 <reg32 offset="0" name="0"/>
789 <reg32 offset="1" name="1">
790 <bitfield name="X1" low="0" high="15" type="uint"/>
791 <bitfield name="Y1" low="16" high="31" type="uint"/>
792 </reg32>
793 <reg32 offset="2" name="2">
794 <bitfield name="X2" low="0" high="15" type="uint"/>
795 <bitfield name="Y2" low="16" high="31" type="uint"/>
796 </reg32>
797 </domain>
798
799 <domain name="CP_SET_BIN_DATA" width="32">
800 <reg32 offset="0" name="0">
801 <!-- corresponds to VSC_PIPE[n].DATA_ADDR -->
802 <bitfield name="BIN_DATA_ADDR" low="0" high="31" type="hex"/>
803 </reg32>
804 <reg32 offset="1" name="1">
805 <!-- seesm to correspond to VSC_SIZE_ADDRESS -->
806 <bitfield name="BIN_SIZE_ADDRESS" low="0" high="31"/>
807 </reg32>
808 </domain>
809
810 <domain name="CP_SET_BIN_DATA5" width="32">
811 <reg32 offset="0" name="0">
812 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
813 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
814 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
815 <bitfield name="VSC_N" low="22" high="26" type="uint"/>
816 </reg32>
817 <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
818 <reg32 offset="1" name="1">
819 <bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/>
820 </reg32>
821 <reg32 offset="2" name="2">
822 <bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/>
823 </reg32>
824 <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
825 <reg32 offset="3" name="3">
826 <bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/>
827 </reg32>
828 <reg32 offset="4" name="4">
829 <bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/>
830 </reg32>
831 <!-- what is this new address? -->
832 <reg32 offset="5" name="5">
833 <bitfield name="BIN_DATA_ADDR2_LO" low="0" high="31"/>
834 </reg32>
835 <reg32 offset="6" name="6">
836 <bitfield name="BIN_DATA_ADDR2_LO" low="0" high="31"/>
837 </reg32>
838 </domain>
839
840 <domain name="CP_SET_BIN_DATA5_OFFSET" width="32">
841 <doc>
842 Like CP_SET_BIN_DATA5, but set the pointers as offsets from the
843 pointers stored in VSC_PIPE_{DATA,DATA2,SIZE}_ADDRESS. Useful
844 for Vulkan where these values aren't known when the command
845 stream is recorded.
846 </doc>
847 <reg32 offset="0" name="0">
848 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
849 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
850 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
851 <bitfield name="VSC_N" low="22" high="26" type="uint"/>
852 </reg32>
853 <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
854 <reg32 offset="1" name="1">
855 <bitfield name="BIN_DATA_OFFSET" low="0" high="31" type="uint"/>
856 </reg32>
857 <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
858 <reg32 offset="2" name="2">
859 <bitfield name="BIN_SIZE_OFFSET" low="0" high="31" type="uint"/>
860 </reg32>
861 <!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS -->
862 <reg32 offset="3" name="3">
863 <bitfield name="BIN_DATA2_OFFSET" low="0" high="31" type="uint"/>
864 </reg32>
865 </domain>
866
867 <domain name="CP_REG_RMW" width="32">
868 <doc>
869 Modifies DST_REG using two sources that can either be registers
870 or immediates. If SRC1_ADD is set, then do the following:
871
872 $dst = (($dst &amp; $src0) rot $rotate) + $src1
873
874 Otherwise:
875
876 $dst = (($dst &amp; $src0) rot $rotate) | $src1
877
878 Here "rot" means rotate left.
879 </doc>
880 <reg32 offset="0" name="0">
881 <bitfield name="DST_REG" low="0" high="17" type="hex"/>
882 <bitfield name="ROTATE" low="24" high="28" type="uint"/>
883 <bitfield name="SRC1_ADD" pos="29" type="boolean"/>
884 <bitfield name="SRC1_IS_REG" pos="30" type="boolean"/>
885 <bitfield name="SRC0_IS_REG" pos="31" type="boolean"/>
886 </reg32>
887 <reg32 offset="1" name="1">
888 <bitfield name="SRC0" low="0" high="31" type="uint"/>
889 </reg32>
890 <reg32 offset="2" name="2">
891 <bitfield name="SRC1" low="0" high="31" type="uint"/>
892 </reg32>
893 </domain>
894
895 <domain name="CP_REG_TO_MEM" width="32">
896 <reg32 offset="0" name="0">
897 <bitfield name="REG" low="0" high="15" type="hex"/>
898 <!-- number of registers/dwords copied is max(CNT, 1). -->
899 <bitfield name="CNT" low="18" high="29" type="uint"/>
900 <bitfield name="64B" pos="30" type="boolean"/>
901 <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
902 </reg32>
903 <reg32 offset="1" name="1">
904 <bitfield name="DEST" low="0" high="31"/>
905 </reg32>
906 <reg32 offset="2" name="2" variants="A5XX-">
907 <bitfield name="DEST_HI" low="0" high="31"/>
908 </reg32>
909 </domain>
910
911 <domain name="CP_REG_TO_MEM_OFFSET_REG" width="32">
912 <doc>
913 Like CP_REG_TO_MEM, but the memory address to write to can be
914 offsetted using either one or two registers or scratch
915 registers.
916 </doc>
917 <reg32 offset="0" name="0">
918 <bitfield name="REG" low="0" high="15" type="hex"/>
919 <!-- number of registers/dwords copied is max(CNT, 1). -->
920 <bitfield name="CNT" low="18" high="29" type="uint"/>
921 <bitfield name="64B" pos="30" type="boolean"/>
922 <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
923 </reg32>
924 <reg32 offset="1" name="1">
925 <bitfield name="DEST" low="0" high="31"/>
926 </reg32>
927 <reg32 offset="2" name="2" variants="A5XX-">
928 <bitfield name="DEST_HI" low="0" high="31"/>
929 </reg32>
930 <reg32 offset="3" name="3">
931 <bitfield name="OFFSET0" low="0" high="17" type="hex"/>
932 <bitfield name="OFFSET0_SCRATCH" pos="19" type="boolean"/>
933 </reg32>
934 <!-- followed by an optional identical OFFSET1 dword -->
935 </domain>
936
937 <domain name="CP_REG_TO_MEM_OFFSET_MEM" width="32">
938 <doc>
939 Like CP_REG_TO_MEM, but the memory address to write to can be
940 offsetted using a DWORD in memory.
941 </doc>
942 <reg32 offset="0" name="0">
943 <bitfield name="REG" low="0" high="15" type="hex"/>
944 <!-- number of registers/dwords copied is max(CNT, 1). -->
945 <bitfield name="CNT" low="18" high="29" type="uint"/>
946 <bitfield name="64B" pos="30" type="boolean"/>
947 <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
948 </reg32>
949 <reg32 offset="1" name="1">
950 <bitfield name="DEST" low="0" high="31"/>
951 </reg32>
952 <reg32 offset="2" name="2" variants="A5XX-">
953 <bitfield name="DEST_HI" low="0" high="31"/>
954 </reg32>
955 <reg32 offset="3" name="3">
956 <bitfield name="OFFSET_LO" low="0" high="31" type="hex"/>
957 </reg32>
958 <reg32 offset="4" name="4">
959 <bitfield name="OFFSET_HI" low="0" high="31" type="hex"/>
960 </reg32>
961 </domain>
962
963 <domain name="CP_MEM_TO_REG" width="32">
964 <reg32 offset="0" name="0">
965 <bitfield name="REG" low="0" high="15" type="hex"/>
966 <!-- number of registers/dwords copied is max(CNT, 1). -->
967 <bitfield name="CNT" low="19" high="29" type="uint"/>
968 <!-- shift each DWORD left by 2 while copying -->
969 <bitfield name="SHIFT_BY_2" pos="30" type="boolean"/>
970 <!-- does the same thing as CP_MEM_TO_MEM::UNK31 -->
971 <bitfield name="UNK31" pos="31" type="boolean"/>
972 </reg32>
973 <reg32 offset="1" name="1">
974 <bitfield name="SRC" low="0" high="31"/>
975 </reg32>
976 <reg32 offset="2" name="2" variants="A5XX-">
977 <bitfield name="SRC_HI" low="0" high="31"/>
978 </reg32>
979 </domain>
980
981 <domain name="CP_MEM_TO_MEM" width="32">
982 <reg32 offset="0" name="0">
983 <!--
984 not sure how many src operands we have, but the low
985 bits negate the n'th src argument.
986 -->
987 <bitfield name="NEG_A" pos="0" type="boolean"/>
988 <bitfield name="NEG_B" pos="1" type="boolean"/>
989 <bitfield name="NEG_C" pos="2" type="boolean"/>
990
991 <!-- if set treat src/dst as 64bit values -->
992 <bitfield name="DOUBLE" pos="29" type="boolean"/>
993 <!-- execute CP_WAIT_FOR_MEM_WRITES beforehand -->
994 <bitfield name="WAIT_FOR_MEM_WRITES" pos="30" type="boolean"/>
995 <!-- some other kind of wait -->
996 <bitfield name="UNK31" pos="31" type="boolean"/>
997 </reg32>
998 <!--
999 followed by sequence of addresses.. the first is the
1000 destination and the rest are N src addresses which are
1001 summed (after being negated if NEG_x bit set) allowing
1002 to do things like 'result += end - start' (which turns
1003 out to be useful for queries and accumulating results
1004 across multiple tiles)
1005 -->
1006 </domain>
1007
1008 <domain name="CP_MEMCPY" width="32">
1009 <reg32 offset="0" name="0">
1010 <bitfield name="DWORDS" low="0" high="31" type="uint"/>
1011 </reg32>
1012 <reg32 offset="1" name="1">
1013 <bitfield name="SRC_LO" low="0" high="31" type="hex"/>
1014 </reg32>
1015 <reg32 offset="2" name="2">
1016 <bitfield name="SRC_HI" low="0" high="31" type="hex"/>
1017 </reg32>
1018 <reg32 offset="3" name="3">
1019 <bitfield name="DST_LO" low="0" high="31" type="hex"/>
1020 </reg32>
1021 <reg32 offset="4" name="4">
1022 <bitfield name="DST_HI" low="0" high="31" type="hex"/>
1023 </reg32>
1024 </domain>
1025
1026 <domain name="CP_REG_TO_SCRATCH" width="32">
1027 <reg32 offset="0" name="0">
1028 <bitfield name="REG" low="0" high="17" type="hex"/>
1029 <bitfield name="SCRATCH" low="20" high="22" type="uint"/>
1030 <!-- number of registers/dwords copied is CNT + 1. -->
1031 <bitfield name="CNT" low="24" high="26" type="uint"/>
1032 </reg32>
1033 </domain>
1034
1035 <domain name="CP_SCRATCH_TO_REG" width="32">
1036 <reg32 offset="0" name="0">
1037 <bitfield name="REG" low="0" high="17" type="hex"/>
1038 <!-- note: CP_MEM_TO_REG always sets this when writing to the register -->
1039 <bitfield name="UNK18" pos="18" type="boolean"/>
1040 <bitfield name="SCRATCH" low="20" high="22" type="uint"/>
1041 <!-- number of registers/dwords copied is CNT + 1. -->
1042 <bitfield name="CNT" low="24" high="26" type="uint"/>
1043 </reg32>
1044 </domain>
1045
1046 <domain name="CP_SCRATCH_WRITE" width="32">
1047 <reg32 offset="0" name="0">
1048 <bitfield name="SCRATCH" low="20" high="22" type="uint"/>
1049 </reg32>
1050 <!-- followed by one or more DWORDs to write to scratch registers -->
1051 </domain>
1052
1053 <domain name="CP_MEM_WRITE" width="32">
1054 <reg32 offset="0" name="0">
1055 <bitfield name="ADDR_LO" low="0" high="31"/>
1056 </reg32>
1057 <reg32 offset="1" name="1">
1058 <bitfield name="ADDR_HI" low="0" high="31"/>
1059 </reg32>
1060 <!-- followed by the DWORDs to write -->
1061 </domain>
1062
1063 <enum name="cp_cond_function">
1064 <value value="0" name="WRITE_ALWAYS"/>
1065 <value value="1" name="WRITE_LT"/>
1066 <value value="2" name="WRITE_LE"/>
1067 <value value="3" name="WRITE_EQ"/>
1068 <value value="4" name="WRITE_NE"/>
1069 <value value="5" name="WRITE_GE"/>
1070 <value value="6" name="WRITE_GT"/>
1071 </enum>
1072
1073 <domain name="CP_COND_WRITE" width="32">
1074 <reg32 offset="0" name="0">
1075 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
1076 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
1077 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
1078 </reg32>
1079 <reg32 offset="1" name="1">
1080 <bitfield name="POLL_ADDR" low="0" high="31" type="hex"/>
1081 </reg32>
1082 <reg32 offset="2" name="2">
1083 <bitfield name="REF" low="0" high="31"/>
1084 </reg32>
1085 <reg32 offset="3" name="3">
1086 <bitfield name="MASK" low="0" high="31"/>
1087 </reg32>
1088 <reg32 offset="4" name="4">
1089 <bitfield name="WRITE_ADDR" low="0" high="31" type="hex"/>
1090 </reg32>
1091 <reg32 offset="5" name="5">
1092 <bitfield name="WRITE_DATA" low="0" high="31"/>
1093 </reg32>
1094 </domain>
1095
1096 <domain name="CP_COND_WRITE5" width="32">
1097 <reg32 offset="0" name="0">
1098 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
1099 <bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/>
1100 <!-- if both POLL_MEMORY and POLL_SCRATCH are false, it polls a register at POLL_ADDR_LO instead. -->
1101 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
1102 <bitfield name="POLL_SCRATCH" pos="5" type="boolean"/>
1103 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
1104 </reg32>
1105 <reg32 offset="1" name="1">
1106 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
1107 </reg32>
1108 <reg32 offset="2" name="2">
1109 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
1110 </reg32>
1111 <reg32 offset="3" name="3">
1112 <bitfield name="REF" low="0" high="31"/>
1113 </reg32>
1114 <reg32 offset="4" name="4">
1115 <bitfield name="MASK" low="0" high="31"/>
1116 </reg32>
1117 <reg32 offset="5" name="5">
1118 <bitfield name="WRITE_ADDR_LO" low="0" high="31" type="hex"/>
1119 </reg32>
1120 <reg32 offset="6" name="6">
1121 <bitfield name="WRITE_ADDR_HI" low="0" high="31" type="hex"/>
1122 </reg32>
1123 <reg32 offset="7" name="7">
1124 <bitfield name="WRITE_DATA" low="0" high="31"/>
1125 </reg32>
1126 </domain>
1127
1128 <domain name="CP_WAIT_MEM_GTE" width="32">
1129 <doc>
1130 Wait until a memory value is greater than or equal to the
1131 reference, using signed comparison.
1132 </doc>
1133 <reg32 offset="0" name="0">
1134 <!-- Reserved for flags, presumably? Unused in FW -->
1135 <bitfield name="RESERVED" low="0" high="31" type="hex"/>
1136 </reg32>
1137 <reg32 offset="1" name="1">
1138 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
1139 </reg32>
1140 <reg32 offset="2" name="2">
1141 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
1142 </reg32>
1143 <reg32 offset="3" name="3">
1144 <bitfield name="REF" low="0" high="31"/>
1145 </reg32>
1146 </domain>
1147
1148 <domain name="CP_WAIT_REG_MEM" width="32">
1149 <doc>
1150 This uses the same internal comparison as CP_COND_WRITE,
1151 but waits until the comparison is true instead. It busy-loops in
1152 the CP for the given number of cycles before trying again.
1153 </doc>
1154 <reg32 offset="0" name="0">
1155 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
1156 <bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/>
1157 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
1158 <bitfield name="POLL_SCRATCH" pos="5" type="boolean"/>
1159 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
1160 </reg32>
1161 <reg32 offset="1" name="1">
1162 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
1163 </reg32>
1164 <reg32 offset="2" name="2">
1165 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
1166 </reg32>
1167 <reg32 offset="3" name="3">
1168 <bitfield name="REF" low="0" high="31"/>
1169 </reg32>
1170 <reg32 offset="4" name="4">
1171 <bitfield name="MASK" low="0" high="31"/>
1172 </reg32>
1173 <reg32 offset="5" name="5">
1174 <bitfield name="DELAY_LOOP_CYCLES" low="0" high="31"/>
1175 </reg32>
1176 </domain>
1177
1178 <domain name="CP_WAIT_TWO_REGS" width="32">
1179 <doc>
1180 Waits for REG0 to not be 0 or REG1 to not equal REF
1181 </doc>
1182 <reg32 offset="0" name="0">
1183 <bitfield name="REG0" low="0" high="17" type="hex"/>
1184 </reg32>
1185 <reg32 offset="1" name="1">
1186 <bitfield name="REG1" low="0" high="17" type="hex"/>
1187 </reg32>
1188 <reg32 offset="2" name="2">
1189 <bitfield name="REF" low="0" high="31" type="uint"/>
1190 </reg32>
1191 </domain>
1192
1193 <domain name="CP_DISPATCH_COMPUTE" width="32">
1194 <reg32 offset="0" name="0"/>
1195 <reg32 offset="1" name="1">
1196 <bitfield name="X" low="0" high="31"/>
1197 </reg32>
1198 <reg32 offset="2" name="2">
1199 <bitfield name="Y" low="0" high="31"/>
1200 </reg32>
1201 <reg32 offset="3" name="3">
1202 <bitfield name="Z" low="0" high="31"/>
1203 </reg32>
1204 </domain>
1205
1206 <domain name="CP_SET_RENDER_MODE" width="32">
1207 <enum name="render_mode_cmd">
1208 <value value="1" name="BYPASS"/>
1209 <value value="2" name="BINNING"/>
1210 <value value="3" name="GMEM"/>
1211 <value value="5" name="BLIT2D"/>
1212 <!-- placeholder name.. used when CP_BLIT packets with BLIT_OP_SCALE?? -->
1213 <value value="7" name="BLIT2DSCALE"/>
1214 <!-- 8 set before going back to BYPASS exiting 2D -->
1215 <value value="8" name="END2D"/>
1216 </enum>
1217 <reg32 offset="0" name="0">
1218 <bitfield name="MODE" low="0" high="8" type="render_mode_cmd"/>
1219 <!--
1220 normally 0x1/0x3, sometimes see 0x5/0x8 with unknown registers in
1221 0x21xx range.. possibly (at least some) a5xx variants have a
1222 2d core?
1223 -->
1224 </reg32>
1225 <!-- I think first buffer is for GPU to save context in case of ctx switch? -->
1226 <reg32 offset="1" name="1">
1227 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1228 </reg32>
1229 <reg32 offset="2" name="2">
1230 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1231 </reg32>
1232 <reg32 offset="3" name="3">
1233 <!--
1234 set when in GMEM.. maybe indicates GMEM contents need to be
1235 preserved on ctx switch?
1236 -->
1237 <bitfield name="VSC_ENABLE" pos="3" type="boolean"/>
1238 <bitfield name="GMEM_ENABLE" pos="4" type="boolean"/>
1239 </reg32>
1240 <reg32 offset="4" name="4"/>
1241 <!-- second buffer looks like some cmdstream.. length in dwords: -->
1242 <reg32 offset="5" name="5">
1243 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
1244 </reg32>
1245 <reg32 offset="6" name="6">
1246 <bitfield name="ADDR_1_LO" low="0" high="31"/>
1247 </reg32>
1248 <reg32 offset="7" name="7">
1249 <bitfield name="ADDR_1_HI" low="0" high="31"/>"
1250 </reg32>
1251 </domain>
1252
1253 <!-- this looks fairly similar to CP_SET_RENDER_MODE minus first dword -->
1254 <domain name="CP_COMPUTE_CHECKPOINT" width="32">
1255 <!-- I think first buffer is for GPU to save context in case of ctx switch? -->
1256 <reg32 offset="0" name="0">
1257 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1258 </reg32>
1259 <reg32 offset="1" name="1">
1260 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1261 </reg32>
1262 <reg32 offset="2" name="2">
1263 </reg32>
1264 <!-- second buffer looks like some cmdstream.. length in dwords: -->
1265 <reg32 offset="3" name="3">
1266 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
1267 </reg32>
1268 <reg32 offset="4" name="4"/>
1269 <reg32 offset="5" name="5">
1270 <bitfield name="ADDR_1_LO" low="0" high="31"/>
1271 </reg32>
1272 <reg32 offset="6" name="6">
1273 <bitfield name="ADDR_1_HI" low="0" high="31"/>"
1274 </reg32>
1275 <reg32 offset="7" name="7"/>
1276 </domain>
1277
1278 <domain name="CP_PERFCOUNTER_ACTION" width="32">
1279 <reg32 offset="0" name="0">
1280 </reg32>
1281 <reg32 offset="1" name="1">
1282 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1283 </reg32>
1284 <reg32 offset="2" name="2">
1285 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1286 </reg32>
1287 </domain>
1288
1289 <domain name="CP_EVENT_WRITE" width="32">
1290 <reg32 offset="0" name="0">
1291 <bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/>
1292 <!-- when set, write back timestamp instead of value from packet: -->
1293 <bitfield name="TIMESTAMP" pos="30" type="boolean"/>
1294 </reg32>
1295 <!--
1296 TODO what is gpuaddr for, seems to be all 0's.. maybe needed for
1297 context switch?
1298 -->
1299 <reg32 offset="1" name="1">
1300 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1301 </reg32>
1302 <reg32 offset="2" name="2">
1303 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1304 </reg32>
1305 <reg32 offset="3" name="3">
1306 <!-- ??? -->
1307 </reg32>
1308 </domain>
1309
1310 <domain name="CP_BLIT" width="32">
1311 <enum name="cp_blit_cmd">
1312 <value value="0" name="BLIT_OP_FILL"/>
1313 <value value="1" name="BLIT_OP_COPY"/>
1314 <value value="3" name="BLIT_OP_SCALE"/> <!-- used for mipmap generation -->
1315 </enum>
1316 <reg32 offset="0" name="0">
1317 <bitfield name="OP" low="0" high="3" type="cp_blit_cmd"/>
1318 </reg32>
1319 <reg32 offset="1" name="1">
1320 <bitfield name="SRC_X1" low="0" high="13" type="uint"/>
1321 <bitfield name="SRC_Y1" low="16" high="29" type="uint"/>
1322 </reg32>
1323 <reg32 offset="2" name="2">
1324 <bitfield name="SRC_X2" low="0" high="13" type="uint"/>
1325 <bitfield name="SRC_Y2" low="16" high="29" type="uint"/>
1326 </reg32>
1327 <reg32 offset="3" name="3">
1328 <bitfield name="DST_X1" low="0" high="13" type="uint"/>
1329 <bitfield name="DST_Y1" low="16" high="29" type="uint"/>
1330 </reg32>
1331 <reg32 offset="4" name="4">
1332 <bitfield name="DST_X2" low="0" high="13" type="uint"/>
1333 <bitfield name="DST_Y2" low="16" high="29" type="uint"/>
1334 </reg32>
1335 </domain>
1336
1337 <domain name="CP_EXEC_CS" width="32">
1338 <reg32 offset="0" name="0">
1339 </reg32>
1340 <reg32 offset="1" name="1">
1341 <bitfield name="NGROUPS_X" low="0" high="31" type="uint"/>
1342 </reg32>
1343 <reg32 offset="2" name="2">
1344 <bitfield name="NGROUPS_Y" low="0" high="31" type="uint"/>
1345 </reg32>
1346 <reg32 offset="3" name="3">
1347 <bitfield name="NGROUPS_Z" low="0" high="31" type="uint"/>
1348 </reg32>
1349 </domain>
1350
1351 <domain name="CP_EXEC_CS_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
1352 <reg32 offset="0" name="0">
1353 </reg32>
1354 <stripe variants="A4XX">
1355 <reg32 offset="1" name="1">
1356 <bitfield name="ADDR" low="0" high="31"/>
1357 </reg32>
1358 <reg32 offset="2" name="2">
1359 <!-- localsize is value minus one: -->
1360 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
1361 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
1362 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
1363 </reg32>
1364 </stripe>
1365 <stripe variants="A5XX-">
1366 <reg32 offset="1" name="1">
1367 <bitfield name="ADDR_LO" low="0" high="31"/>
1368 </reg32>
1369 <reg32 offset="2" name="2">
1370 <bitfield name="ADDR_HI" low="0" high="31"/>
1371 </reg32>
1372 <reg32 offset="3" name="3">
1373 <!-- localsize is value minus one: -->
1374 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
1375 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
1376 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
1377 </reg32>
1378 </stripe>
1379 </domain>
1380
1381 <domain name="CP_SET_MARKER" width="32" varset="chip" prefix="chip" variants="A6XX-">
1382 <doc>Tell CP the current operation mode, indicates save and restore procedure</doc>
1383 <enum name="a6xx_render_mode">
1384 <value value="1" name="RM6_BYPASS"/>
1385 <value value="2" name="RM6_BINNING"/>
1386 <value value="4" name="RM6_GMEM"/>
1387 <value value="5" name="RM6_BLIT2D"/>
1388 <value value="6" name="RM6_RESOLVE"/>
1389 <value value="7" name="RM6_YIELD"/>
1390 <value value="0xc" name="RM6_BLIT2DSCALE"/>
1391
1392 <!--
1393 These values come from a6xx_set_marker() in the
1394 downstream kernel, and they can only be set by the kernel
1395 -->
1396 <value value="0xd" name="RM6_IB1LIST_START"/>
1397 <value value="0xe" name="RM6_IB1LIST_END"/>
1398 <!-- IFPC - inter-frame power collapse -->
1399 <value value="0x100" name="RM6_IFPC_ENABLE"/>
1400 <value value="0x101" name="RM6_IFPC_DISABLE"/>
1401 </enum>
1402 <reg32 offset="0" name="0">
1403 <bitfield name="MARKER" low="0" high="3"/>
1404 <bitfield name="MODE" low="0" high="8" type="a6xx_render_mode"/>
1405 </reg32>
1406 </domain>
1407
1408 <domain name="CP_SET_PSEUDO_REG" width="32" varset="chip" prefix="chip" variants="A6XX-">
1409 <doc>Set internal CP registers, used to indicate context save data addresses</doc>
1410 <enum name="pseudo_reg">
1411 <value value="0" name="SMMU_INFO"/>
1412 <value value="1" name="NON_SECURE_SAVE_ADDR"/>
1413 <value value="2" name="SECURE_SAVE_ADDR"/>
1414 <value value="3" name="NON_PRIV_SAVE_ADDR"/>
1415 <value value="4" name="COUNTER"/>
1416 </enum>
1417 <array offset="0" name="" stride="3" length="100">
1418 <reg32 offset="0" name="0">
1419 <bitfield name="PSEUDO_REG" low="0" high="2" type="pseudo_reg"/>
1420 </reg32>
1421 <reg32 offset="1" name="1">
1422 <bitfield name="LO" low="0" high="31"/>
1423 </reg32>
1424 <reg32 offset="2" name="2">
1425 <bitfield name="HI" low="0" high="31"/>
1426 </reg32>
1427 </array>
1428 </domain>
1429
1430 <domain name="CP_REG_TEST" width="32" varset="chip" prefix="chip" variants="A6XX-">
1431 <doc>
1432 Tests bit in specified register and sets predicate for CP_COND_REG_EXEC.
1433 So:
1434
1435 opcode: CP_REG_TEST (39) (2 dwords)
1436 { REG = 0xc10 | BIT = 0 }
1437 0000: 70b90001 00000c10
1438 opcode: CP_COND_REG_EXEC (47) (3 dwords)
1439 0000: 70c70002 10000000 00000004
1440 opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
1441
1442 Will execute the CP_INDIRECT_BUFFER only if b0 in the register at
1443 offset 0x0c10 is 1
1444 </doc>
1445 <reg32 offset="0" name="0">
1446 <!-- the register to test -->
1447 <bitfield name="REG" low="0" high="11"/>
1448 <!-- the bit to test -->
1449 <bitfield name="BIT" low="20" high="24" type="uint"/>
1450 <!-- execute CP_WAIT_FOR_ME beforehand -->
1451 <bitfield name="WAIT_FOR_ME" pos="25" type="boolean"/>
1452 </reg32>
1453 </domain>
1454
1455 <!-- I *think* this existed at least as far back as a4xx -->
1456 <domain name="CP_COND_REG_EXEC" width="32">
1457 <enum name="compare_mode">
1458 <!-- use the predicate bit set by CP_REG_TEST -->
1459 <value value="1" name="PRED_TEST"/>
1460 <!-- compare two registers directly for equality -->
1461 <value value="2" name="REG_COMPARE"/>
1462 <!-- test if certain render modes are set via CP_SET_MARKER -->
1463 <value value="3" name="RENDER_MODE" variants="A6XX-"/>
1464 </enum>
1465 <reg32 offset="0" name="0">
1466 <bitfield name="REG0" low="0" high="17" type="hex"/>
1467
1468 <!--
1469 Note: these bits have the same meaning, and use the same
1470 internal mechanism as the bits in CP_SET_DRAW_STATE.
1471 When RENDER_MODE is selected, they're used as
1472 a bitmask of which modes pass the test.
1473 -->
1474
1475 <!-- RM6_BINNING -->
1476 <bitfield name="BINNING" pos="25" variants="A6XX-" type="boolean"/>
1477 <!-- all others -->
1478 <bitfield name="GMEM" pos="26" variants="A6XX-" type="boolean"/>
1479 <!-- RM6_BYPASS -->
1480 <bitfield name="SYSMEM" pos="27" variants="A6XX-" type="boolean"/>
1481
1482 <bitfield name="MODE" low="28" high="31" type="compare_mode"/>
1483 </reg32>
1484
1485 <!-- in REG_COMPARE mode, there's an extra DWORD here with REG1 -->
1486
1487 <reg32 offset="1" name="1">
1488 <bitfield name="DWORDS" low="0" high="31" type="uint"/>
1489 </reg32>
1490 </domain>
1491
1492 <domain name="CP_COND_EXEC" width="32">
1493 <doc>
1494 Executes the following DWORDs of commands if the dword at ADDR0
1495 is not equal to 0 and the dword at ADDR1 is less than REF
1496 (signed comparison).
1497 </doc>
1498 <reg32 offset="0" name="0">
1499 <bitfield name="ADDR0_LO" low="0" high="31"/>
1500 </reg32>
1501 <reg32 offset="1" name="1">
1502 <bitfield name="ADDR0_HI" low="0" high="31"/>
1503 </reg32>
1504 <reg32 offset="2" name="2">
1505 <bitfield name="ADDR1_LO" low="0" high="31"/>
1506 </reg32>
1507 <reg32 offset="3" name="3">
1508 <bitfield name="ADDR1_HI" low="0" high="31"/>
1509 </reg32>
1510 <reg32 offset="4" name="4">
1511 <bitfield name="REF" low="0" high="31"/>
1512 </reg32>
1513 <reg32 offset="1" name="1">
1514 <bitfield name="DWORDS" low="0" high="31" type="uint"/>
1515 </reg32>
1516 </domain>
1517
1518 <domain name="CP_SET_CTXSWITCH_IB" width="32">
1519 <doc>
1520 Used by the userspace driver to set various IB's which are
1521 executed during context save/restore for handling
1522 state that isn't restored by the
1523 context switch routine itself.
1524 </doc>
1525 <enum name="ctxswitch_ib">
1526 <value name="RESTORE_IB" value="0">
1527 <doc>Executed unconditionally when switching back to the context.</doc>
1528 </value>
1529 <value name="YIELD_RESTORE_IB" value="1">
1530 <doc>
1531 Executed when switching back after switching
1532 away during execution of
1533 a CP_SET_MARKER packet with RM6_YIELD as the
1534 payload *and* the normal save routine was
1535 bypassed for a shorter one. I think this is
1536 connected to the "skipsaverestore" bit set by
1537 the kernel when preempting.
1538 </doc>
1539 </value>
1540 <value name="SAVE_IB" value="2">
1541 <doc>
1542 Executed when switching away from the context,
1543 except for context switches initiated via
1544 CP_YIELD.
1545 </doc>
1546 </value>
1547 <value name="RB_SAVE_IB" value="3">
1548 <doc>
1549 This can only be set by the RB (i.e. the kernel)
1550 and executes with protected mode off, but
1551 is otherwise similar to SAVE_IB.
1552 </doc>
1553 </value>
1554 </enum>
1555 <reg32 offset="0" name="0">
1556 <bitfield name="ADDR_LO" low="0" high="31"/>
1557 </reg32>
1558 <reg32 offset="1" name="1">
1559 <bitfield name="ADDR_HI" low="0" high="31"/>
1560 </reg32>
1561 <reg32 offset="2" name="2">
1562 <bitfield name="DWORDS" low="0" high="19" type="uint"/>
1563 <bitfield name="TYPE" low="20" high="21" type="ctxswitch_ib"/>
1564 </reg32>
1565 </domain>
1566
1567 </database>
1568