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[mesa.git] / src / freedreno / registers / adreno_pm4.xml
1 <?xml version="1.0" encoding="UTF-8"?>
2 <database xmlns="http://nouveau.freedesktop.org/"
3 xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance"
4 xsi:schemaLocation="http://nouveau.freedesktop.org/ rules-ng.xsd">
5
6 <enum name="vgt_event_type">
7 <value name="VS_DEALLOC" value="0"/>
8 <value name="PS_DEALLOC" value="1"/>
9 <value name="VS_DONE_TS" value="2"/>
10 <value name="PS_DONE_TS" value="3"/>
11 <value name="CACHE_FLUSH_TS" value="4"/>
12 <value name="CONTEXT_DONE" value="5"/>
13 <value name="CACHE_FLUSH" value="6"/>
14 <value name="VIZQUERY_START" value="7" variants="A2XX"/>
15 <value name="HLSQ_FLUSH" value="7" variants="A3XX,A4XX"/>
16 <value name="VIZQUERY_END" value="8" variants="A2XX"/>
17 <value name="SC_WAIT_WC" value="9"/>
18 <value name="WRITE_PRIMITIVE_COUNTS" value="9" variants="A6XX"/>
19 <value name="START_PRIMITIVE_CTRS" value="11" variants="A6XX"/>
20 <value name="STOP_PRIMITIVE_CTRS" value="12" variants="A6XX"/>
21 <value name="RST_PIX_CNT" value="13"/>
22 <value name="RST_VTX_CNT" value="14"/>
23 <value name="TILE_FLUSH" value="15"/>
24 <value name="STAT_EVENT" value="16"/>
25 <value name="CACHE_FLUSH_AND_INV_TS_EVENT" value="20" variants="A2XX,A3XX,A4XX"/>
26 <value name="ZPASS_DONE" value="21"/>
27 <value name="CACHE_FLUSH_AND_INV_EVENT" value="22" variants="A2XX"/>
28 <value name="RB_DONE_TS" value="22" variants="A3XX-"/>
29 <value name="PERFCOUNTER_START" value="23" variants="A2XX,A3XX,A4XX"/>
30 <value name="PERFCOUNTER_STOP" value="24" variants="A2XX,A3XX,A4XX"/>
31 <value name="VS_FETCH_DONE" value="27"/>
32 <value name="FACENESS_FLUSH" value="28" variants="A2XX,A3XX,A4XX"/>
33
34 <!-- a5xx events -->
35 <value name="WT_DONE_TS" value="8" variants="A5XX,A6XX"/>
36 <value name="FLUSH_SO_0" value="17" variants="A5XX,A6XX"/>
37 <value name="FLUSH_SO_1" value="18" variants="A5XX,A6XX"/>
38 <value name="FLUSH_SO_2" value="19" variants="A5XX,A6XX"/>
39 <value name="FLUSH_SO_3" value="20" variants="A5XX,A6XX"/>
40 <value name="PC_CCU_INVALIDATE_DEPTH" value="24" variants="A5XX,A6XX"/>
41 <value name="PC_CCU_INVALIDATE_COLOR" value="25" variants="A5XX,A6XX"/>
42 <value name="PC_CCU_RESOLVE_TS" value="26" variants="A6XX"/>
43 <value name="PC_CCU_FLUSH_DEPTH_TS" value="28" variants="A5XX,A6XX"/>
44 <value name="PC_CCU_FLUSH_COLOR_TS" value="29" variants="A5XX,A6XX"/>
45 <value name="BLIT" value="30" variants="A5XX,A6XX"/>
46 <value name="UNK_25" value="37" variants="A5XX"/>
47 <value name="LRZ_FLUSH" value="38" variants="A5XX,A6XX"/>
48 <value name="BLIT_OP_FILL_2D" value="39" variants="A5XX,A6XX"/>
49 <value name="BLIT_OP_COPY_2D" value="40" variants="A5XX,A6XX"/>
50 <value name="BLIT_OP_SCALE_2D" value="42" variants="A5XX,A6XX"/>
51 <value name="CONTEXT_DONE_2D" value="43" variants="A5XX,A6XX"/>
52 <value name="UNK_2C" value="44" variants="A5XX"/>
53 <value name="UNK_2D" value="45" variants="A5XX"/>
54
55 <!-- a6xx events -->
56 <value name="CACHE_INVALIDATE" value="49" variants="A6XX"/>
57 </enum>
58
59 <enum name="pc_di_primtype">
60 <value name="DI_PT_NONE" value="0"/>
61 <!-- POINTLIST_PSIZE is used on a3xx/a4xx when gl_PointSize is written: -->
62 <value name="DI_PT_POINTLIST_PSIZE" value="1"/>
63 <value name="DI_PT_LINELIST" value="2"/>
64 <value name="DI_PT_LINESTRIP" value="3"/>
65 <value name="DI_PT_TRILIST" value="4"/>
66 <value name="DI_PT_TRIFAN" value="5"/>
67 <value name="DI_PT_TRISTRIP" value="6"/>
68 <value name="DI_PT_LINELOOP" value="7"/> <!-- a22x, a3xx -->
69 <value name="DI_PT_RECTLIST" value="8"/>
70 <value name="DI_PT_POINTLIST" value="9"/>
71 <value name="DI_PT_LINE_ADJ" value="0xa"/>
72 <value name="DI_PT_LINESTRIP_ADJ" value="0xb"/>
73 <value name="DI_PT_TRI_ADJ" value="0xc"/>
74 <value name="DI_PT_TRISTRIP_ADJ" value="0xd"/>
75
76 <value name="DI_PT_PATCHES0" value="0x1f"/>
77 <value name="DI_PT_PATCHES1" value="0x20"/>
78 <value name="DI_PT_PATCHES2" value="0x21"/>
79 <value name="DI_PT_PATCHES3" value="0x22"/>
80 <value name="DI_PT_PATCHES4" value="0x23"/>
81 <value name="DI_PT_PATCHES5" value="0x24"/>
82 <value name="DI_PT_PATCHES6" value="0x25"/>
83 <value name="DI_PT_PATCHES7" value="0x26"/>
84 <value name="DI_PT_PATCHES8" value="0x27"/>
85 <value name="DI_PT_PATCHES9" value="0x28"/>
86 <value name="DI_PT_PATCHES10" value="0x29"/>
87 <value name="DI_PT_PATCHES11" value="0x2a"/>
88 <value name="DI_PT_PATCHES12" value="0x2b"/>
89 <value name="DI_PT_PATCHES13" value="0x2c"/>
90 <value name="DI_PT_PATCHES14" value="0x2d"/>
91 <value name="DI_PT_PATCHES15" value="0x2e"/>
92 <value name="DI_PT_PATCHES16" value="0x2f"/>
93 <value name="DI_PT_PATCHES17" value="0x30"/>
94 <value name="DI_PT_PATCHES18" value="0x31"/>
95 <value name="DI_PT_PATCHES19" value="0x32"/>
96 <value name="DI_PT_PATCHES20" value="0x33"/>
97 <value name="DI_PT_PATCHES21" value="0x34"/>
98 <value name="DI_PT_PATCHES22" value="0x35"/>
99 <value name="DI_PT_PATCHES23" value="0x36"/>
100 <value name="DI_PT_PATCHES24" value="0x37"/>
101 <value name="DI_PT_PATCHES25" value="0x38"/>
102 <value name="DI_PT_PATCHES26" value="0x39"/>
103 <value name="DI_PT_PATCHES27" value="0x3a"/>
104 <value name="DI_PT_PATCHES28" value="0x3b"/>
105 <value name="DI_PT_PATCHES29" value="0x3c"/>
106 <value name="DI_PT_PATCHES30" value="0x3d"/>
107 <value name="DI_PT_PATCHES31" value="0x3e"/>
108 </enum>
109
110 <enum name="pc_di_src_sel">
111 <value name="DI_SRC_SEL_DMA" value="0"/>
112 <value name="DI_SRC_SEL_IMMEDIATE" value="1"/>
113 <value name="DI_SRC_SEL_AUTO_INDEX" value="2"/>
114 <value name="DI_SRC_SEL_AUTO_XFB" value="3"/>
115 </enum>
116
117 <enum name="pc_di_face_cull_sel">
118 <value name="DI_FACE_CULL_NONE" value="0"/>
119 <value name="DI_FACE_CULL_FETCH" value="1"/>
120 <value name="DI_FACE_BACKFACE_CULL" value="2"/>
121 <value name="DI_FACE_FRONTFACE_CULL" value="3"/>
122 </enum>
123
124 <enum name="pc_di_index_size">
125 <value name="INDEX_SIZE_IGN" value="0"/>
126 <value name="INDEX_SIZE_16_BIT" value="0"/>
127 <value name="INDEX_SIZE_32_BIT" value="1"/>
128 <value name="INDEX_SIZE_8_BIT" value="2"/>
129 <value name="INDEX_SIZE_INVALID"/>
130 </enum>
131
132 <enum name="pc_di_vis_cull_mode">
133 <value name="IGNORE_VISIBILITY" value="0"/>
134 <value name="USE_VISIBILITY" value="1"/>
135 </enum>
136
137 <enum name="adreno_pm4_packet_type">
138 <value name="CP_TYPE0_PKT" value="0x00000000"/>
139 <value name="CP_TYPE1_PKT" value="0x40000000"/>
140 <value name="CP_TYPE2_PKT" value="0x80000000"/>
141 <value name="CP_TYPE3_PKT" value="0xc0000000"/>
142 <value name="CP_TYPE4_PKT" value="0x40000000"/>
143 <value name="CP_TYPE7_PKT" value="0x70000000"/>
144 </enum>
145
146 <!--
147 Note that in some cases, the same packet id is recycled on a later
148 generation, so variants attribute is used to distinguish. They
149 may not be completely accurate, we would probably have to analyze
150 the pfp and me/pm4 firmware to verify the packet is actually
151 handled on a particular generation. But it is at least enough to
152 disambiguate the packet-id's that were re-used for different
153 packets starting with a5xx.
154 -->
155 <enum name="adreno_pm4_type3_packets">
156 <doc>initialize CP's micro-engine</doc>
157 <value name="CP_ME_INIT" value="0x48"/>
158 <doc>skip N 32-bit words to get to the next packet</doc>
159 <value name="CP_NOP" value="0x10"/>
160 <doc>
161 indirect buffer dispatch. prefetch parser uses this packet
162 type to determine whether to pre-fetch the IB
163 </doc>
164 <value name="CP_PREEMPT_ENABLE" value="0x1c"/>
165 <value name="CP_PREEMPT_TOKEN" value="0x1e"/>
166 <value name="CP_INDIRECT_BUFFER" value="0x3f"/>
167 <doc>
168 Takes the same arguments as CP_INDIRECT_BUFFER, but jumps to
169 another buffer at the same level. Must be at the end of IB, and
170 doesn't work with draw state IB's.
171 </doc>
172 <value name="CP_INDIRECT_BUFFER_CHAIN" value="0x57" variants="A5XX-"/>
173 <doc>indirect buffer dispatch. same as IB, but init is pipelined</doc>
174 <value name="CP_INDIRECT_BUFFER_PFD" value="0x37"/>
175 <doc>wait for the IDLE state of the engine</doc>
176 <value name="CP_WAIT_FOR_IDLE" value="0x26"/>
177 <doc>wait until a register or memory location is a specific value</doc>
178 <value name="CP_WAIT_REG_MEM" value="0x3c"/>
179 <doc>wait until a register location is equal to a specific value</doc>
180 <value name="CP_WAIT_REG_EQ" value="0x52"/>
181 <doc>wait until a register location is >= a specific value</doc>
182 <value name="CP_WAIT_REG_GTE" value="0x53" variants="A2XX,A3XX,A4XX"/>
183 <doc>wait until a read completes</doc>
184 <value name="CP_WAIT_UNTIL_READ" value="0x5c" variants="A2XX,A3XX,A4XX"/>
185 <doc>wait until all base/size writes from an IB_PFD packet have completed</doc>
186 <value name="CP_WAIT_IB_PFD_COMPLETE" value="0x5d"/>
187 <doc>register read/modify/write</doc>
188 <value name="CP_REG_RMW" value="0x21"/>
189 <doc>Set binning configuration registers</doc>
190 <value name="CP_SET_BIN_DATA" value="0x2f" variants="A2XX,A3XX,A4XX"/>
191 <value name="CP_SET_BIN_DATA5" value="0x2f" variants="A5XX,A6XX"/>
192 <doc>reads register in chip and writes to memory</doc>
193 <value name="CP_REG_TO_MEM" value="0x3e"/>
194 <doc>write N 32-bit words to memory</doc>
195 <value name="CP_MEM_WRITE" value="0x3d"/>
196 <doc>write CP_PROG_COUNTER value to memory</doc>
197 <value name="CP_MEM_WRITE_CNTR" value="0x4f"/>
198 <doc>conditional execution of a sequence of packets</doc>
199 <value name="CP_COND_EXEC" value="0x44"/>
200 <doc>conditional write to memory or register</doc>
201 <value name="CP_COND_WRITE" value="0x45" variants="A2XX,A3XX,A4XX"/>
202 <value name="CP_COND_WRITE5" value="0x45" variants="A5XX,A6XX"/>
203 <doc>generate an event that creates a write to memory when completed</doc>
204 <value name="CP_EVENT_WRITE" value="0x46"/>
205 <doc>generate a VS|PS_done event</doc>
206 <value name="CP_EVENT_WRITE_SHD" value="0x58"/>
207 <doc>generate a cache flush done event</doc>
208 <value name="CP_EVENT_WRITE_CFL" value="0x59"/>
209 <doc>generate a z_pass done event</doc>
210 <value name="CP_EVENT_WRITE_ZPD" value="0x5b"/>
211 <doc>
212 not sure the real name, but this seems to be what is used for
213 opencl, instead of CP_DRAW_INDX..
214 </doc>
215 <value name="CP_RUN_OPENCL" value="0x31"/>
216 <doc>initiate fetch of index buffer and draw</doc>
217 <value name="CP_DRAW_INDX" value="0x22"/>
218 <doc>draw using supplied indices in packet</doc>
219 <value name="CP_DRAW_INDX_2" value="0x36" variants="A2XX,A3XX,A4XX"/> <!-- this is something different on a6xx and unused on a5xx -->
220 <doc>initiate fetch of index buffer and binIDs and draw</doc>
221 <value name="CP_DRAW_INDX_BIN" value="0x34" variants="A2XX,A3XX,A4XX"/>
222 <doc>initiate fetch of bin IDs and draw using supplied indices</doc>
223 <value name="CP_DRAW_INDX_2_BIN" value="0x35" variants="A2XX,A3XX,A4XX"/>
224 <doc>begin/end initiator for viz query extent processing</doc>
225 <value name="CP_VIZ_QUERY" value="0x23" variants="A2XX,A3XX,A4XX"/>
226 <doc>fetch state sub-blocks and initiate shader code DMAs</doc>
227 <value name="CP_SET_STATE" value="0x25"/>
228 <doc>load constant into chip and to memory</doc>
229 <value name="CP_SET_CONSTANT" value="0x2d"/>
230 <doc>load sequencer instruction memory (pointer-based)</doc>
231 <value name="CP_IM_LOAD" value="0x27"/>
232 <doc>load sequencer instruction memory (code embedded in packet)</doc>
233 <value name="CP_IM_LOAD_IMMEDIATE" value="0x2b"/>
234 <doc>load constants from a location in memory</doc>
235 <value name="CP_LOAD_CONSTANT_CONTEXT" value="0x2e" variants="A2XX"/>
236 <doc>selective invalidation of state pointers</doc>
237 <value name="CP_INVALIDATE_STATE" value="0x3b"/>
238 <doc>dynamically changes shader instruction memory partition</doc>
239 <value name="CP_SET_SHADER_BASES" value="0x4a" variants="A2XX,A3XX,A4XX"/>
240 <doc>sets the 64-bit BIN_MASK register in the PFP</doc>
241 <value name="CP_SET_BIN_MASK" value="0x50" variants="A2XX,A3XX,A4XX"/>
242 <doc>sets the 64-bit BIN_SELECT register in the PFP</doc>
243 <value name="CP_SET_BIN_SELECT" value="0x51"/>
244 <doc>updates the current context, if needed</doc>
245 <value name="CP_CONTEXT_UPDATE" value="0x5e"/>
246 <doc>generate interrupt from the command stream</doc>
247 <value name="CP_INTERRUPT" value="0x40"/>
248 <doc>copy sequencer instruction memory to system memory</doc>
249 <value name="CP_IM_STORE" value="0x2c" variants="A2XX"/>
250
251 <!-- For a20x -->
252 <!-- TODO handle variants..
253 <doc>
254 Program an offset that will added to the BIN_BASE value of
255 the 3D_DRAW_INDX_BIN packet
256 </doc>
257 <value name="CP_SET_BIN_BASE_OFFSET" value="0x4b"/>
258 -->
259
260 <!-- for a22x -->
261 <doc>
262 sets draw initiator flags register in PFP, gets bitwise-ORed into
263 every draw initiator
264 </doc>
265 <value name="CP_SET_DRAW_INIT_FLAGS" value="0x4b"/>
266 <doc>sets the register protection mode</doc>
267 <value name="CP_SET_PROTECTED_MODE" value="0x5f"/>
268
269 <value name="CP_BOOTSTRAP_UCODE" value="0x6f"/>
270
271 <!-- for a3xx -->
272 <doc>load high level sequencer command</doc>
273 <value name="CP_LOAD_STATE" value="0x30" variants="A3XX"/>
274 <value name="CP_LOAD_STATE4" value="0x30" variants="A4XX,A5XX"/>
275 <doc>Conditionally load a IB based on a flag, prefetch enabled</doc>
276 <value name="CP_COND_INDIRECT_BUFFER_PFE" value="0x3a"/>
277 <doc>Conditionally load a IB based on a flag, prefetch disabled</doc>
278 <value name="CP_COND_INDIRECT_BUFFER_PFD" value="0x32" variants="A3XX"/>
279 <doc>Load a buffer with pre-fetch enabled</doc>
280 <value name="CP_INDIRECT_BUFFER_PFE" value="0x3f" variants="A5XX"/>
281 <doc>Set bin (?)</doc>
282 <value name="CP_SET_BIN" value="0x4c" variants="A2XX"/>
283
284 <doc>test 2 memory locations to dword values specified</doc>
285 <value name="CP_TEST_TWO_MEMS" value="0x71"/>
286
287 <doc>Write register, ignoring context state for context sensitive registers</doc>
288 <value name="CP_REG_WR_NO_CTXT" value="0x78"/>
289
290 <doc>Record the real-time when this packet is processed by PFP</doc>
291 <value name="CP_RECORD_PFP_TIMESTAMP" value="0x11"/>
292
293 <!-- Used to switch GPU between secure and non-secure modes -->
294 <value name="CP_SET_SECURE_MODE" value="0x66"/>
295
296 <doc>PFP waits until the FIFO between the PFP and the ME is empty</doc>
297 <value name="CP_WAIT_FOR_ME" value="0x13"/>
298
299 <!-- for a4xx -->
300 <doc>
301 Used a bit like CP_SET_CONSTANT on a2xx, but can write multiple
302 groups of registers. Looks like it can be used to create state
303 objects in GPU memory, and on state change only emit pointer
304 (via CP_SET_DRAW_STATE), which should be nice for reducing CPU
305 overhead:
306
307 (A4x) save PM4 stream pointers to execute upon a visible draw
308 </doc>
309 <value name="CP_SET_DRAW_STATE" value="0x43" variants="A4XX,A5XX,A6XX"/>
310 <value name="CP_DRAW_INDX_OFFSET" value="0x38"/>
311 <value name="CP_DRAW_INDIRECT" value="0x28" variants="A4XX,A5XX,A6XX"/>
312 <value name="CP_DRAW_INDX_INDIRECT" value="0x29" variants="A4XX,A5XX,A6XX"/>
313 <value name="CP_DRAW_INDIRECT_MULTI" value="0x2a" variants="A6XX"/>
314 <value name="CP_DRAW_AUTO" value="0x24"/>
315
316 <value name="CP_UNKNOWN_19" value="0x19"/>
317
318 <doc>set to 1 for fastclear..:</doc>
319 <value name="CP_UNKNOWN_1A" value="0x1a"/>
320
321 <value name="CP_UNKNOWN_4E" value="0x4e"/>
322
323 <doc>
324 for A4xx
325 Write to register with address that does not fit into type-0 pkt
326 </doc>
327 <value name="CP_WIDE_REG_WRITE" value="0x74" variants="A4XX"/>
328
329 <doc>copy from ME scratch RAM to a register</doc>
330 <value name="CP_SCRATCH_TO_REG" value="0x4d"/>
331
332 <doc>Copy from REG to ME scratch RAM</doc>
333 <value name="CP_REG_TO_SCRATCH" value="0x4a"/>
334
335 <doc>Wait for memory writes to complete</doc>
336 <value name="CP_WAIT_MEM_WRITES" value="0x12"/>
337
338 <doc>Conditional execution based on register comparison</doc>
339 <value name="CP_COND_REG_EXEC" value="0x47"/>
340
341 <doc>Memory to REG copy</doc>
342 <value name="CP_MEM_TO_REG" value="0x42"/>
343
344 <value name="CP_EXEC_CS_INDIRECT" value="0x41" variants="A4XX,A5XX,A6XX"/>
345 <value name="CP_EXEC_CS" value="0x33"/>
346
347 <doc>
348 for a5xx
349 </doc>
350 <value name="CP_PERFCOUNTER_ACTION" value="0x50" variants="A5XX"/>
351 <!-- switches SMMU pagetable, used on a5xx+ only -->
352 <value name="CP_SMMU_TABLE_UPDATE" value="0x53" variants="A5XX,A6XX"/>
353 <!-- for a6xx -->
354 <doc>Tells CP the current mode of GPU operation</doc>
355 <value name="CP_SET_MARKER" value="0x65" variants="A6XX"/>
356 <doc>Instruct CP to set a few internal CP registers</doc>
357 <value name="CP_SET_PSEUDO_REG" value="0x56" variants="A6XX"/>
358 <!--
359 pairs of regid and value.. seems to be used to program some TF
360 related regs:
361 -->
362 <value name="CP_CONTEXT_REG_BUNCH" value="0x5c" variants="A5XX,A6XX"/>
363 <!-- A5XX Enable yield in RB only -->
364 <value name="CP_YIELD_ENABLE" value="0x1c" variants="A5XX"/>
365 <value name="CP_SKIP_IB2_ENABLE_GLOBAL" value="0x1d" variants="A5XX,A6XX"/>
366 <value name="CP_SKIP_IB2_ENABLE_LOCAL" value="0x23" variants="A5XX,A6XX"/>
367 <value name="CP_SET_SUBDRAW_SIZE" value="0x35" variants="A5XX,A6XX"/>
368 <value name="CP_SET_VISIBILITY_OVERRIDE" value="0x64" variants="A5XX,A6XX"/>
369 <!-- Enable/Disable/Defer A5x global preemption model -->
370 <value name="CP_PREEMPT_ENABLE_GLOBAL" value="0x69" variants="A5XX"/>
371 <!-- Enable/Disable A5x local preemption model -->
372 <value name="CP_PREEMPT_ENABLE_LOCAL" value="0x6a" variants="A5XX"/>
373 <!-- Yield token on a5xx similar to CP_PREEMPT on a4xx -->
374 <value name="CP_CONTEXT_SWITCH_YIELD" value="0x6b" variants="A5XX"/>
375 <!-- Inform CP about current render mode (needed for a5xx preemption) -->
376 <value name="CP_SET_RENDER_MODE" value="0x6c" variants="A5XX"/>
377 <value name="CP_COMPUTE_CHECKPOINT" value="0x6e" variants="A5XX"/>
378 <!-- check if this works on earlier.. -->
379 <value name="CP_MEM_TO_MEM" value="0x73" variants="A5XX,A6XX"/>
380 <value name="CP_BLIT" value="0x2c" variants="A5XX,A6XX"/>
381
382 <!-- Test specified bit in specified register and set predicate -->
383 <value name="CP_REG_TEST" value="0x39" variants="A5XX,A6XX"/>
384
385 <!--
386 Seems to set the mode flags which control which CP_SET_DRAW_STATE
387 packets are executed, based on their ENABLE_MASK values
388
389 CP_SET_MODE w/ payload of 0x1 seems to cause CP_SET_DRAW_STATE
390 packets w/ ENABLE_MASK & 0x6 to execute immediately
391 -->
392 <value name="CP_SET_MODE" value="0x63" variants="A6XX"/>
393
394 <!--
395 Seems like there are now separate blocks of state for VS vs FS/CS
396 (probably these amounts to geometry vs fragments so that geometry
397 stage of the pipeline for next draw can start while fragment stage
398 of current draw is still running. The format of the payload of the
399 packets is the same, the only difference is the offsets of the regs
400 the firmware code that handles the packet writes.
401
402 Note that for CL, starting with a6xx, the preferred # of local
403 threads is no longer the same as the max, implying that the shader
404 core can now run warps from unrelated shaders (ie.
405 CL_KERNEL_PREFERRED_WORK_GROUP_SIZE_MULTIPLE vs
406 CL_KERNEL_WORK_GROUP_SIZE)
407 -->
408 <value name="CP_LOAD_STATE6_GEOM" value="0x32" variants="A6XX"/>
409 <value name="CP_LOAD_STATE6_FRAG" value="0x34" variants="A6XX"/>
410 <!--
411 Note: For IBO state (Image/SSBOs) which have shared state across
412 shader stages, for 3d pipeline CP_LOAD_STATE6 is used. But for
413 compute shaders, CP_LOAD_STATE6_FRAG is used. Possibly they are
414 interchangable.
415 -->
416 <value name="CP_LOAD_STATE6" value="0x36" variants="A6XX"/>
417
418 <!-- internal packets: -->
419 <value name="IN_IB_PREFETCH_END" value="0x17" variants="A2XX"/>
420 <value name="IN_SUBBLK_PREFETCH" value="0x1f" variants="A2XX"/>
421 <value name="IN_INSTR_PREFETCH" value="0x20" variants="A2XX"/>
422 <value name="IN_INSTR_MATCH" value="0x47" variants="A2XX"/>
423 <value name="IN_CONST_PREFETCH" value="0x49" variants="A2XX"/>
424 <value name="IN_INCR_UPDT_STATE" value="0x55" variants="A2XX"/>
425 <value name="IN_INCR_UPDT_CONST" value="0x56" variants="A2XX"/>
426 <value name="IN_INCR_UPDT_INSTR" value="0x57" variants="A2XX"/>
427
428 <!-- jmptable entry used to handle type4 packet on a5xx+: -->
429 <value name="PKT4" value="0x04" variants="A5XX,A6XX"/>
430
431 <!-- TODO do these exist on A5xx? -->
432 <value name="CP_SCRATCH_WRITE" value="0x4c" variants="A6XX"/>
433 <value name="CP_REG_TO_MEM_OFFSET_MEM" value="0x74" variants="A6XX"/>
434 <value name="CP_REG_TO_MEM_OFFSET_REG" value="0x72" variants="A6XX"/>
435 <value name="CP_WAIT_MEM_GTE" value="0x14" variants="A6XX"/>
436 <value name="CP_WAIT_TWO_REGS" value="0x70" variants="A6XX"/>
437 <value name="CP_MEMCPY" value="0x75" variants="A6XX"/>
438 <value name="CP_SET_BIN_DATA5_OFFSET" value="0x2e" variants="A6XX"/>
439 <value name="CP_SET_CTXSWITCH_IB" value="0x55" variants="A6XX"/>
440
441 <!--
442 Seems to always have the payload:
443 00000002 00008801 00004010
444 or:
445 00000002 00008801 00004090
446 or:
447 00000002 00008801 00000010
448 00000002 00008801 00010010
449 00000002 00008801 00d64010
450 ...
451 Note set for compute shaders..
452 Is 0x8801 a register offset?
453 This appears to be a special sort of register write packet
454 more or less, but the firmware has some special handling..
455 Seems like it intercepts/modifies certain register offsets,
456 but others are treated like a normal PKT4 reg write. I
457 guess there are some registers that the fw controls certain
458 bits.
459 -->
460 <value name="CP_REG_WRITE" value="0x6d" variants="A6XX"/>
461
462 </enum>
463
464
465 <domain name="CP_LOAD_STATE" width="32">
466 <doc>Load state, a3xx (and later?)</doc>
467 <enum name="adreno_state_block">
468 <value name="SB_VERT_TEX" value="0"/>
469 <value name="SB_VERT_MIPADDR" value="1"/>
470 <value name="SB_FRAG_TEX" value="2"/>
471 <value name="SB_FRAG_MIPADDR" value="3"/>
472 <value name="SB_VERT_SHADER" value="4"/>
473 <value name="SB_GEOM_SHADER" value="5"/>
474 <value name="SB_FRAG_SHADER" value="6"/>
475 <value name="SB_COMPUTE_SHADER" value="7"/>
476 </enum>
477 <enum name="adreno_state_type">
478 <value name="ST_SHADER" value="0"/>
479 <value name="ST_CONSTANTS" value="1"/>
480 </enum>
481 <enum name="adreno_state_src">
482 <value name="SS_DIRECT" value="0">
483 <doc>inline with the CP_LOAD_STATE packet</doc>
484 </value>
485 <value name="SS_INVALID_ALL_IC" value="2"/>
486 <value name="SS_INVALID_PART_IC" value="3"/>
487 <value name="SS_INDIRECT" value="4">
488 <doc>in buffer pointed to by EXT_SRC_ADDR</doc>
489 </value>
490 <value name="SS_INDIRECT_TCM" value="5"/>
491 <value name="SS_INDIRECT_STM" value="6"/>
492 </enum>
493 <reg32 offset="0" name="0">
494 <bitfield name="DST_OFF" low="0" high="15" type="uint"/>
495 <bitfield name="STATE_SRC" low="16" high="18" type="adreno_state_src"/>
496 <bitfield name="STATE_BLOCK" low="19" high="21" type="adreno_state_block"/>
497 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
498 </reg32>
499 <reg32 offset="1" name="1">
500 <bitfield name="STATE_TYPE" low="0" high="1" type="adreno_state_type"/>
501 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
502 </reg32>
503 </domain>
504
505 <domain name="CP_LOAD_STATE4" width="32" varset="chip">
506 <doc>Load state, a4xx+</doc>
507 <enum name="a4xx_state_block">
508 <!--
509 unknown: 0x7 and 0xf <- seen in compute shader
510
511 STATE_BLOCK = 0x6, STATE_TYPE = 0x2 possibly used for preemption?
512 Seen in some GL shaders. Payload is NUM_UNIT dwords, and it contains
513 the gpuaddr of the following shader constants block. DST_OFF seems
514 to specify which shader stage:
515
516 16 -> vert
517 36 -> tcs
518 56 -> tes
519 76 -> geom
520 96 -> frag
521
522 Example:
523
524 opcode: CP_LOAD_STATE4 (30) (12 dwords)
525 { DST_OFF = 16 | STATE_SRC = SS4_DIRECT | STATE_BLOCK = 0x6 | NUM_UNIT = 4 }
526 { STATE_TYPE = 0x2 | EXT_SRC_ADDR = 0 }
527 { EXT_SRC_ADDR_HI = 0 }
528 0000: c0264100 00000000 00000000 00000000
529 0000: 70b0000b 01180010 00000002 00000000 c0264100 00000000 00000000 00000000
530
531 opcode: CP_LOAD_STATE4 (30) (4 dwords)
532 { DST_OFF = 16 | STATE_SRC = SS4_INDIRECT | STATE_BLOCK = SB4_VS_SHADER | NUM_UNIT = 4 }
533 { STATE_TYPE = ST4_CONSTANTS | EXT_SRC_ADDR = 0xc0264100 }
534 { EXT_SRC_ADDR_HI = 0 }
535 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000
536 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000 0.000000
537 0000: 00000040 0000000c 00000000 00000000 00000000 00000000 00000000 00000000
538
539 STATE_BLOCK = 0x6, STATE_TYPE = 0x1, seen in compute shader. NUM_UNITS * 2 dwords.
540
541 -->
542 <value name="SB4_VS_TEX" value="0x0"/>
543 <value name="SB4_HS_TEX" value="0x1"/> <!-- aka. TCS -->
544 <value name="SB4_DS_TEX" value="0x2"/> <!-- aka. TES -->
545 <value name="SB4_GS_TEX" value="0x3"/>
546 <value name="SB4_FS_TEX" value="0x4"/>
547 <value name="SB4_CS_TEX" value="0x5"/>
548 <value name="SB4_VS_SHADER" value="0x8"/>
549 <value name="SB4_HS_SHADER" value="0x9"/>
550 <value name="SB4_DS_SHADER" value="0xa"/>
551 <value name="SB4_GS_SHADER" value="0xb"/>
552 <value name="SB4_FS_SHADER" value="0xc"/>
553 <value name="SB4_CS_SHADER" value="0xd"/>
554 <!--
555 for SSBO, STATE_TYPE=0 appears to be addresses (four dwords each),
556 STATE_TYPE=1 sizes, STATE_TYPE=2 addresses again (two dwords each)
557
558 Compute has it's own dedicated SSBO state, it seems, but the rest
559 of the stages share state
560 -->
561 <value name="SB4_SSBO" value="0xe"/>
562 <value name="SB4_CS_SSBO" value="0xf"/>
563 </enum>
564 <enum name="a4xx_state_type">
565 <value name="ST4_SHADER" value="0"/>
566 <value name="ST4_CONSTANTS" value="1"/>
567 <value name="ST4_UBO" value="2"/>
568 </enum>
569 <enum name="a4xx_state_src">
570 <value name="SS4_DIRECT" value="0"/>
571 <value name="SS4_INDIRECT" value="2"/>
572 </enum>
573 <reg32 offset="0" name="0">
574 <bitfield name="DST_OFF" low="0" high="13" type="uint"/>
575 <bitfield name="STATE_SRC" low="16" high="17" type="a4xx_state_src"/>
576 <bitfield name="STATE_BLOCK" low="18" high="21" type="a4xx_state_block"/>
577 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
578 </reg32>
579 <reg32 offset="1" name="1">
580 <bitfield name="STATE_TYPE" low="0" high="1" type="a4xx_state_type"/>
581 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
582 </reg32>
583 <reg32 offset="2" name="2" variants="A5XX-">
584 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
585 </reg32>
586 </domain>
587
588 <!-- looks basically same CP_LOAD_STATE4 -->
589 <domain name="CP_LOAD_STATE6" width="32" varset="chip">
590 <doc>Load state, a6xx+</doc>
591 <enum name="a6xx_state_block">
592 <value name="SB6_VS_TEX" value="0x0"/>
593 <value name="SB6_HS_TEX" value="0x1"/> <!-- aka. TCS -->
594 <value name="SB6_DS_TEX" value="0x2"/> <!-- aka. TES -->
595 <value name="SB6_GS_TEX" value="0x3"/>
596 <value name="SB6_FS_TEX" value="0x4"/>
597 <value name="SB6_CS_TEX" value="0x5"/>
598 <value name="SB6_VS_SHADER" value="0x8"/>
599 <value name="SB6_HS_SHADER" value="0x9"/>
600 <value name="SB6_DS_SHADER" value="0xa"/>
601 <value name="SB6_GS_SHADER" value="0xb"/>
602 <value name="SB6_FS_SHADER" value="0xc"/>
603 <value name="SB6_CS_SHADER" value="0xd"/>
604 <value name="SB6_IBO" value="0xe"/>
605 <value name="SB6_CS_IBO" value="0xf"/>
606 </enum>
607 <enum name="a6xx_state_type">
608 <value name="ST6_SHADER" value="0"/>
609 <value name="ST6_CONSTANTS" value="1"/>
610 <value name="ST6_UBO" value="2"/>
611 <value name="ST6_IBO" value="3"/>
612 </enum>
613 <enum name="a6xx_state_src">
614 <value name="SS6_DIRECT" value="0"/>
615 <value name="SS6_BINDLESS" value="1"/> <!-- TODO does this exist on a4xx/a5xx? -->
616 <value name="SS6_INDIRECT" value="2"/>
617 <doc>
618 SS6_UBO used by the a6xx vulkan blob with tesselation constants
619 in this case, EXT_SRC_ADDR is (ubo_id shl 16 | offset)
620 to load constants from a UBO loaded with DST_OFF = 14 and offset 0,
621 EXT_SRC_ADDR = 0xe0000
622 (offset is a guess, should be in bytes given that maxUniformBufferRange=64k)
623 </doc>
624 <value name="SS6_UBO" value="3"/>
625 </enum>
626 <reg32 offset="0" name="0">
627 <bitfield name="DST_OFF" low="0" high="13" type="uint"/>
628 <bitfield name="STATE_TYPE" low="14" high="15" type="a6xx_state_type"/>
629 <bitfield name="STATE_SRC" low="16" high="17" type="a6xx_state_src"/>
630 <bitfield name="STATE_BLOCK" low="18" high="21" type="a6xx_state_block"/>
631 <bitfield name="NUM_UNIT" low="22" high="31" type="uint"/>
632 </reg32>
633 <reg32 offset="1" name="1">
634 <bitfield name="EXT_SRC_ADDR" low="2" high="31" shr="2"/>
635 </reg32>
636 <reg32 offset="2" name="2">
637 <bitfield name="EXT_SRC_ADDR_HI" low="0" high="31" shr="0"/>
638 </reg32>
639 <reg64 offset="1" name="EXT_SRC_ADDR" type="address"/>
640 </domain>
641
642 <bitset name="vgt_draw_initiator" inline="yes">
643 <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
644 <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
645 <bitfield name="VIS_CULL" low="9" high="10" type="pc_di_vis_cull_mode"/>
646 <bitfield name="INDEX_SIZE" pos="11" type="pc_di_index_size"/>
647 <bitfield name="NOT_EOP" pos="12" type="boolean"/>
648 <bitfield name="SMALL_INDEX" pos="13" type="boolean"/>
649 <bitfield name="PRE_DRAW_INITIATOR_ENABLE" pos="14" type="boolean"/>
650 <bitfield name="NUM_INSTANCES" low="24" high="31" type="uint"/>
651 </bitset>
652
653 <!-- changed on a4xx: -->
654 <enum name="a4xx_index_size">
655 <value name="INDEX4_SIZE_8_BIT" value="0"/>
656 <value name="INDEX4_SIZE_16_BIT" value="1"/>
657 <value name="INDEX4_SIZE_32_BIT" value="2"/>
658 </enum>
659
660 <enum name="a6xx_patch_type">
661 <value name="TESS_QUADS" value="0"/>
662 <value name="TESS_TRIANGLES" value="1"/>
663 <value name="TESS_ISOLINES" value="2"/>
664 </enum>
665
666 <bitset name="vgt_draw_initiator_a4xx" inline="yes">
667 <!-- When the 0x20 bit is set, it's the number of patch vertices - 1 -->
668 <bitfield name="PRIM_TYPE" low="0" high="5" type="pc_di_primtype"/>
669 <bitfield name="SOURCE_SELECT" low="6" high="7" type="pc_di_src_sel"/>
670 <bitfield name="VIS_CULL" low="8" high="9" type="pc_di_vis_cull_mode"/>
671 <bitfield name="INDEX_SIZE" low="10" high="11" type="a4xx_index_size"/>
672 <bitfield name="PATCH_TYPE" low="12" high="13" type="a6xx_patch_type"/>
673 <bitfield name="GS_ENABLE" pos="16" type="boolean"/>
674 <bitfield name="TESS_ENABLE" pos="17" type="boolean"/>
675 </bitset>
676
677 <domain name="CP_DRAW_INDX" width="32">
678 <reg32 offset="0" name="0">
679 <bitfield name="VIZ_QUERY" low="0" high="31"/>
680 </reg32>
681 <reg32 offset="1" name="1" type="vgt_draw_initiator"/>
682 <reg32 offset="2" name="2">
683 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
684 </reg32>
685 <reg32 offset="3" name="3">
686 <bitfield name="INDX_BASE" low="0" high="31"/>
687 </reg32>
688 <reg32 offset="4" name="4">
689 <bitfield name="INDX_SIZE" low="0" high="31"/>
690 </reg32>
691 </domain>
692
693 <domain name="CP_DRAW_INDX_2" width="32">
694 <reg32 offset="0" name="0">
695 <bitfield name="VIZ_QUERY" low="0" high="31"/>
696 </reg32>
697 <reg32 offset="1" name="1" type="vgt_draw_initiator"/>
698 <reg32 offset="2" name="2">
699 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
700 </reg32>
701 <!-- followed by NUM_INDICES indices.. -->
702 </domain>
703
704 <domain name="CP_DRAW_INDX_OFFSET" width="32">
705 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
706 <reg32 offset="1" name="1">
707 <bitfield name="NUM_INSTANCES" low="0" high="31" type="uint"/>
708 </reg32>
709 <reg32 offset="2" name="2">
710 <bitfield name="NUM_INDICES" low="0" high="31" type="uint"/>
711 </reg32>
712 <reg32 offset="3" name="3">
713 <bitfield name="FIRST_INDX" low="0" high="31"/>
714 </reg32>
715
716 <stripe variants="A5XX-">
717 <reg32 offset="4" name="4">
718 <bitfield name="INDX_BASE_LO" low="0" high="31"/>
719 </reg32>
720 <reg32 offset="5" name="5">
721 <bitfield name="INDX_BASE_HI" low="0" high="31"/>
722 </reg32>
723 <reg64 offset="4" name="INDX_BASE" type="address"/>
724 <reg32 offset="6" name="6">
725 <!-- max # of elements in index buffer -->
726 <bitfield name="MAX_INDICES" low="0" high="31"/>
727 </reg32>
728 </stripe>
729
730 <reg32 offset="4" name="4">
731 <bitfield name="INDX_BASE" low="0" high="31" type="address"/>
732 </reg32>
733
734 <reg32 offset="5" name="5">
735 <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/>
736 </reg32>
737 </domain>
738
739 <domain name="CP_DRAW_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
740 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
741 <stripe variants="A4XX">
742 <reg32 offset="1" name="1">
743 <bitfield name="INDIRECT" low="0" high="31"/>
744 </reg32>
745 </stripe>
746 <stripe variants="A5XX-">
747 <reg32 offset="1" name="1">
748 <bitfield name="INDIRECT_LO" low="0" high="31"/>
749 </reg32>
750 <reg32 offset="2" name="2">
751 <bitfield name="INDIRECT_HI" low="0" high="31"/>
752 </reg32>
753 <reg64 offset="1" name="INDIRECT" type="address"/>
754 </stripe>
755 </domain>
756
757 <domain name="CP_DRAW_INDX_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
758 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
759 <stripe variants="A4XX">
760 <reg32 offset="1" name="1">
761 <bitfield name="INDX_BASE" low="0" high="31"/>
762 </reg32>
763 <reg32 offset="2" name="2">
764 <!-- max # of bytes in index buffer -->
765 <bitfield name="INDX_SIZE" low="0" high="31" type="uint"/>
766 </reg32>
767 <reg32 offset="3" name="3">
768 <bitfield name="INDIRECT" low="0" high="31"/>
769 </reg32>
770 </stripe>
771 <stripe variants="A5XX-">
772 <reg32 offset="1" name="1">
773 <bitfield name="INDX_BASE_LO" low="0" high="31"/>
774 </reg32>
775 <reg32 offset="2" name="2">
776 <bitfield name="INDX_BASE_HI" low="0" high="31"/>
777 </reg32>
778 <reg64 offset="1" name="INDX_BASE" type="address"/>
779 <reg32 offset="3" name="3">
780 <!-- max # of elements in index buffer -->
781 <bitfield name="MAX_INDICES" low="0" high="31" type="uint"/>
782 </reg32>
783 <reg32 offset="4" name="4">
784 <bitfield name="INDIRECT_LO" low="0" high="31"/>
785 </reg32>
786 <reg32 offset="5" name="5">
787 <bitfield name="INDIRECT_HI" low="0" high="31"/>
788 </reg32>
789 <reg64 offset="4" name="INDIRECT" type="address"/>
790 </stripe>
791 </domain>
792
793 <domain name="CP_DRAW_INDIRECT_MULTI" width="32" varset="chip" prefix="chip" variants="A6XX-">
794 <enum name="a6xx_draw_indirect_opcode">
795 <value name="INDIRECT_OP_NORMAL" value="0x2"/>
796 <value name="INDIRECT_OP_INDEXED" value="0x4"/>
797 </enum>
798 <reg32 offset="0" name="0" type="vgt_draw_initiator_a4xx"/>
799 <reg32 offset="1" name="1">
800 <bitfield name="OPCODE" low="0" high="3" type="a6xx_draw_indirect_opcode"/>
801 <doc>
802 DST_OFF same as in CP_LOAD_STATE6 - vec4 VS const at this offset will
803 be updated for each draw to {draw_id, first_vertex, first_instance, 0}
804 value of 0 disables it
805 </doc>
806 <bitfield name="DST_OFF" low="8" high="21" type="hex"/>
807 </reg32>
808 <reg32 offset="2" name="2">
809 <bitfield name="DRAW_COUNT" low="0" high="31" type="hex"/>
810 </reg32>
811 <doc>for opcode 2: indirect address. for opcode 4: index address</doc>
812 <reg64 offset="3" name="ADDRESS_0" type="address"/>
813 <reg32 offset="5" name="5">
814 <doc>for opcode 2: stride. for opcode 4: max_indices</doc>
815 <bitfield name="PARAM_0" low="0" high="31" type="hex"/>
816 </reg32>
817 <doc>last 3 dwords only for opcode 4</doc>
818 <reg64 offset="6" name="INDIRECT" type="address"/>
819 <reg32 offset="8" name="8">
820 <bitfield name="STRIDE" low="0" high="31" type="hex"/>
821 </reg32>
822 </domain>
823
824 <domain name="CP_SET_DRAW_STATE" width="32" varset="chip" variants="A4XX-">
825 <array offset="0" name="" stride="3" length="100">
826 <reg32 offset="0" name="0">
827 <bitfield name="COUNT" low="0" high="15" type="uint"/>
828 <bitfield name="DIRTY" pos="16" type="boolean"/>
829 <bitfield name="DISABLE" pos="17" type="boolean"/>
830 <bitfield name="DISABLE_ALL_GROUPS" pos="18" type="boolean"/>
831 <bitfield name="LOAD_IMMED" pos="19" type="boolean"/>
832 <bitfield name="BINNING" pos="20" variants="A6XX-" type="boolean"/>
833 <bitfield name="GMEM" pos="21" variants="A6XX-" type="boolean"/>
834 <bitfield name="SYSMEM" pos="22" variants="A6XX-" type="boolean"/>
835 <bitfield name="GROUP_ID" low="24" high="28" type="uint"/>
836 </reg32>
837 <reg32 offset="1" name="1">
838 <bitfield name="ADDR_LO" low="0" high="31" type="hex"/>
839 </reg32>
840 <reg32 offset="2" name="2" variants="A5XX-">
841 <bitfield name="ADDR_HI" low="0" high="31" type="hex"/>
842 </reg32>
843 </array>
844 </domain>
845
846 <domain name="CP_SET_BIN" width="32">
847 <doc>value at offset 0 always seems to be 0x00000000..</doc>
848 <reg32 offset="0" name="0"/>
849 <reg32 offset="1" name="1">
850 <bitfield name="X1" low="0" high="15" type="uint"/>
851 <bitfield name="Y1" low="16" high="31" type="uint"/>
852 </reg32>
853 <reg32 offset="2" name="2">
854 <bitfield name="X2" low="0" high="15" type="uint"/>
855 <bitfield name="Y2" low="16" high="31" type="uint"/>
856 </reg32>
857 </domain>
858
859 <domain name="CP_SET_BIN_DATA" width="32">
860 <reg32 offset="0" name="0">
861 <!-- corresponds to VSC_PIPE[n].DATA_ADDR -->
862 <bitfield name="BIN_DATA_ADDR" low="0" high="31" type="hex"/>
863 </reg32>
864 <reg32 offset="1" name="1">
865 <!-- seesm to correspond to VSC_SIZE_ADDRESS -->
866 <bitfield name="BIN_SIZE_ADDRESS" low="0" high="31"/>
867 </reg32>
868 </domain>
869
870 <domain name="CP_SET_BIN_DATA5" width="32">
871 <reg32 offset="0" name="0">
872 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
873 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
874 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
875 <bitfield name="VSC_N" low="22" high="26" type="uint"/>
876 </reg32>
877 <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
878 <reg32 offset="1" name="1">
879 <bitfield name="BIN_DATA_ADDR_LO" low="0" high="31" type="hex"/>
880 </reg32>
881 <reg32 offset="2" name="2">
882 <bitfield name="BIN_DATA_ADDR_HI" low="0" high="31" type="hex"/>
883 </reg32>
884 <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
885 <reg32 offset="3" name="3">
886 <bitfield name="BIN_SIZE_ADDRESS_LO" low="0" high="31"/>
887 </reg32>
888 <reg32 offset="4" name="4">
889 <bitfield name="BIN_SIZE_ADDRESS_HI" low="0" high="31"/>
890 </reg32>
891 <!-- new on a6xx, where BIN_DATA_ADDR is the DRAW_STRM: -->
892 <reg32 offset="5" name="5">
893 <bitfield name="BIN_PRIM_STRM_LO" low="0" high="31"/>
894 </reg32>
895 <reg32 offset="6" name="6">
896 <bitfield name="BIN_PRIM_STRM_HI" low="0" high="31"/>
897 </reg32>
898 </domain>
899
900 <domain name="CP_SET_BIN_DATA5_OFFSET" width="32">
901 <doc>
902 Like CP_SET_BIN_DATA5, but set the pointers as offsets from the
903 pointers stored in VSC_PIPE_{DATA,DATA2,SIZE}_ADDRESS. Useful
904 for Vulkan where these values aren't known when the command
905 stream is recorded.
906 </doc>
907 <reg32 offset="0" name="0">
908 <!-- equiv to PC_VSTREAM_CONTROL.SIZE on a3xx/a4xx: -->
909 <bitfield name="VSC_SIZE" low="16" high="21" type="uint"/>
910 <!-- equiv to PC_VSTREAM_CONTROL.N on a3xx/a4xx: -->
911 <bitfield name="VSC_N" low="22" high="26" type="uint"/>
912 </reg32>
913 <!-- BIN_DATA_ADDR -> VSC_PIPE[p].DATA_ADDRESS -->
914 <reg32 offset="1" name="1">
915 <bitfield name="BIN_DATA_OFFSET" low="0" high="31" type="uint"/>
916 </reg32>
917 <!-- BIN_SIZE_ADDRESS -> VSC_SIZE_ADDRESS + (p * 4)-->
918 <reg32 offset="2" name="2">
919 <bitfield name="BIN_SIZE_OFFSET" low="0" high="31" type="uint"/>
920 </reg32>
921 <!-- BIN_DATA2_ADDR -> VSC_PIPE[p].DATA2_ADDRESS -->
922 <reg32 offset="3" name="3">
923 <bitfield name="BIN_DATA2_OFFSET" low="0" high="31" type="uint"/>
924 </reg32>
925 </domain>
926
927 <domain name="CP_REG_RMW" width="32">
928 <doc>
929 Modifies DST_REG using two sources that can either be registers
930 or immediates. If SRC1_ADD is set, then do the following:
931
932 $dst = (($dst &amp; $src0) rot $rotate) + $src1
933
934 Otherwise:
935
936 $dst = (($dst &amp; $src0) rot $rotate) | $src1
937
938 Here "rot" means rotate left.
939 </doc>
940 <reg32 offset="0" name="0">
941 <bitfield name="DST_REG" low="0" high="17" type="hex"/>
942 <bitfield name="ROTATE" low="24" high="28" type="uint"/>
943 <bitfield name="SRC1_ADD" pos="29" type="boolean"/>
944 <bitfield name="SRC1_IS_REG" pos="30" type="boolean"/>
945 <bitfield name="SRC0_IS_REG" pos="31" type="boolean"/>
946 </reg32>
947 <reg32 offset="1" name="1">
948 <bitfield name="SRC0" low="0" high="31" type="uint"/>
949 </reg32>
950 <reg32 offset="2" name="2">
951 <bitfield name="SRC1" low="0" high="31" type="uint"/>
952 </reg32>
953 </domain>
954
955 <domain name="CP_REG_TO_MEM" width="32">
956 <reg32 offset="0" name="0">
957 <bitfield name="REG" low="0" high="17" type="hex"/>
958 <!-- number of registers/dwords copied is max(CNT, 1). -->
959 <bitfield name="CNT" low="18" high="29" type="uint"/>
960 <bitfield name="64B" pos="30" type="boolean"/>
961 <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
962 </reg32>
963 <reg32 offset="1" name="1">
964 <bitfield name="DEST" low="0" high="31"/>
965 </reg32>
966 <reg32 offset="2" name="2" variants="A5XX-">
967 <bitfield name="DEST_HI" low="0" high="31"/>
968 </reg32>
969 </domain>
970
971 <domain name="CP_REG_TO_MEM_OFFSET_REG" width="32">
972 <doc>
973 Like CP_REG_TO_MEM, but the memory address to write to can be
974 offsetted using either one or two registers or scratch
975 registers.
976 </doc>
977 <reg32 offset="0" name="0">
978 <bitfield name="REG" low="0" high="17" type="hex"/>
979 <!-- number of registers/dwords copied is max(CNT, 1). -->
980 <bitfield name="CNT" low="18" high="29" type="uint"/>
981 <bitfield name="64B" pos="30" type="boolean"/>
982 <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
983 </reg32>
984 <reg32 offset="1" name="1">
985 <bitfield name="DEST" low="0" high="31"/>
986 </reg32>
987 <reg32 offset="2" name="2" variants="A5XX-">
988 <bitfield name="DEST_HI" low="0" high="31"/>
989 </reg32>
990 <reg32 offset="3" name="3">
991 <bitfield name="OFFSET0" low="0" high="17" type="hex"/>
992 <bitfield name="OFFSET0_SCRATCH" pos="19" type="boolean"/>
993 </reg32>
994 <!-- followed by an optional identical OFFSET1 dword -->
995 </domain>
996
997 <domain name="CP_REG_TO_MEM_OFFSET_MEM" width="32">
998 <doc>
999 Like CP_REG_TO_MEM, but the memory address to write to can be
1000 offsetted using a DWORD in memory.
1001 </doc>
1002 <reg32 offset="0" name="0">
1003 <bitfield name="REG" low="0" high="17" type="hex"/>
1004 <!-- number of registers/dwords copied is max(CNT, 1). -->
1005 <bitfield name="CNT" low="18" high="29" type="uint"/>
1006 <bitfield name="64B" pos="30" type="boolean"/>
1007 <bitfield name="ACCUMULATE" pos="31" type="boolean"/>
1008 </reg32>
1009 <reg32 offset="1" name="1">
1010 <bitfield name="DEST" low="0" high="31"/>
1011 </reg32>
1012 <reg32 offset="2" name="2" variants="A5XX-">
1013 <bitfield name="DEST_HI" low="0" high="31"/>
1014 </reg32>
1015 <reg32 offset="3" name="3">
1016 <bitfield name="OFFSET_LO" low="0" high="31" type="hex"/>
1017 </reg32>
1018 <reg32 offset="4" name="4">
1019 <bitfield name="OFFSET_HI" low="0" high="31" type="hex"/>
1020 </reg32>
1021 </domain>
1022
1023 <domain name="CP_MEM_TO_REG" width="32">
1024 <reg32 offset="0" name="0">
1025 <bitfield name="REG" low="0" high="17" type="hex"/>
1026 <!-- number of registers/dwords copied is max(CNT, 1). -->
1027 <bitfield name="CNT" low="19" high="29" type="uint"/>
1028 <!-- shift each DWORD left by 2 while copying -->
1029 <bitfield name="SHIFT_BY_2" pos="30" type="boolean"/>
1030 <!-- does the same thing as CP_MEM_TO_MEM::UNK31 -->
1031 <bitfield name="UNK31" pos="31" type="boolean"/>
1032 </reg32>
1033 <reg32 offset="1" name="1">
1034 <bitfield name="SRC" low="0" high="31"/>
1035 </reg32>
1036 <reg32 offset="2" name="2" variants="A5XX-">
1037 <bitfield name="SRC_HI" low="0" high="31"/>
1038 </reg32>
1039 </domain>
1040
1041 <domain name="CP_MEM_TO_MEM" width="32">
1042 <reg32 offset="0" name="0">
1043 <!--
1044 not sure how many src operands we have, but the low
1045 bits negate the n'th src argument.
1046 -->
1047 <bitfield name="NEG_A" pos="0" type="boolean"/>
1048 <bitfield name="NEG_B" pos="1" type="boolean"/>
1049 <bitfield name="NEG_C" pos="2" type="boolean"/>
1050
1051 <!-- if set treat src/dst as 64bit values -->
1052 <bitfield name="DOUBLE" pos="29" type="boolean"/>
1053 <!-- execute CP_WAIT_FOR_MEM_WRITES beforehand -->
1054 <bitfield name="WAIT_FOR_MEM_WRITES" pos="30" type="boolean"/>
1055 <!-- some other kind of wait -->
1056 <bitfield name="UNK31" pos="31" type="boolean"/>
1057 </reg32>
1058 <!--
1059 followed by sequence of addresses.. the first is the
1060 destination and the rest are N src addresses which are
1061 summed (after being negated if NEG_x bit set) allowing
1062 to do things like 'result += end - start' (which turns
1063 out to be useful for queries and accumulating results
1064 across multiple tiles)
1065 -->
1066 </domain>
1067
1068 <domain name="CP_MEMCPY" width="32">
1069 <reg32 offset="0" name="0">
1070 <bitfield name="DWORDS" low="0" high="31" type="uint"/>
1071 </reg32>
1072 <reg32 offset="1" name="1">
1073 <bitfield name="SRC_LO" low="0" high="31" type="hex"/>
1074 </reg32>
1075 <reg32 offset="2" name="2">
1076 <bitfield name="SRC_HI" low="0" high="31" type="hex"/>
1077 </reg32>
1078 <reg32 offset="3" name="3">
1079 <bitfield name="DST_LO" low="0" high="31" type="hex"/>
1080 </reg32>
1081 <reg32 offset="4" name="4">
1082 <bitfield name="DST_HI" low="0" high="31" type="hex"/>
1083 </reg32>
1084 </domain>
1085
1086 <domain name="CP_REG_TO_SCRATCH" width="32">
1087 <reg32 offset="0" name="0">
1088 <bitfield name="REG" low="0" high="17" type="hex"/>
1089 <bitfield name="SCRATCH" low="20" high="22" type="uint"/>
1090 <!-- number of registers/dwords copied is CNT + 1. -->
1091 <bitfield name="CNT" low="24" high="26" type="uint"/>
1092 </reg32>
1093 </domain>
1094
1095 <domain name="CP_SCRATCH_TO_REG" width="32">
1096 <reg32 offset="0" name="0">
1097 <bitfield name="REG" low="0" high="17" type="hex"/>
1098 <!-- note: CP_MEM_TO_REG always sets this when writing to the register -->
1099 <bitfield name="UNK18" pos="18" type="boolean"/>
1100 <bitfield name="SCRATCH" low="20" high="22" type="uint"/>
1101 <!-- number of registers/dwords copied is CNT + 1. -->
1102 <bitfield name="CNT" low="24" high="26" type="uint"/>
1103 </reg32>
1104 </domain>
1105
1106 <domain name="CP_SCRATCH_WRITE" width="32">
1107 <reg32 offset="0" name="0">
1108 <bitfield name="SCRATCH" low="20" high="22" type="uint"/>
1109 </reg32>
1110 <!-- followed by one or more DWORDs to write to scratch registers -->
1111 </domain>
1112
1113 <domain name="CP_MEM_WRITE" width="32">
1114 <reg32 offset="0" name="0">
1115 <bitfield name="ADDR_LO" low="0" high="31"/>
1116 </reg32>
1117 <reg32 offset="1" name="1">
1118 <bitfield name="ADDR_HI" low="0" high="31"/>
1119 </reg32>
1120 <!-- followed by the DWORDs to write -->
1121 </domain>
1122
1123 <enum name="cp_cond_function">
1124 <value value="0" name="WRITE_ALWAYS"/>
1125 <value value="1" name="WRITE_LT"/>
1126 <value value="2" name="WRITE_LE"/>
1127 <value value="3" name="WRITE_EQ"/>
1128 <value value="4" name="WRITE_NE"/>
1129 <value value="5" name="WRITE_GE"/>
1130 <value value="6" name="WRITE_GT"/>
1131 </enum>
1132
1133 <domain name="CP_COND_WRITE" width="32">
1134 <reg32 offset="0" name="0">
1135 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
1136 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
1137 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
1138 </reg32>
1139 <reg32 offset="1" name="1">
1140 <bitfield name="POLL_ADDR" low="0" high="31" type="hex"/>
1141 </reg32>
1142 <reg32 offset="2" name="2">
1143 <bitfield name="REF" low="0" high="31"/>
1144 </reg32>
1145 <reg32 offset="3" name="3">
1146 <bitfield name="MASK" low="0" high="31"/>
1147 </reg32>
1148 <reg32 offset="4" name="4">
1149 <bitfield name="WRITE_ADDR" low="0" high="31" type="hex"/>
1150 </reg32>
1151 <reg32 offset="5" name="5">
1152 <bitfield name="WRITE_DATA" low="0" high="31"/>
1153 </reg32>
1154 </domain>
1155
1156 <domain name="CP_COND_WRITE5" width="32">
1157 <reg32 offset="0" name="0">
1158 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
1159 <bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/>
1160 <!-- if both POLL_MEMORY and POLL_SCRATCH are false, it polls a register at POLL_ADDR_LO instead. -->
1161 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
1162 <bitfield name="POLL_SCRATCH" pos="5" type="boolean"/>
1163 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
1164 </reg32>
1165 <reg32 offset="1" name="1">
1166 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
1167 </reg32>
1168 <reg32 offset="2" name="2">
1169 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
1170 </reg32>
1171 <reg32 offset="3" name="3">
1172 <bitfield name="REF" low="0" high="31"/>
1173 </reg32>
1174 <reg32 offset="4" name="4">
1175 <bitfield name="MASK" low="0" high="31"/>
1176 </reg32>
1177 <reg32 offset="5" name="5">
1178 <bitfield name="WRITE_ADDR_LO" low="0" high="31" type="hex"/>
1179 </reg32>
1180 <reg32 offset="6" name="6">
1181 <bitfield name="WRITE_ADDR_HI" low="0" high="31" type="hex"/>
1182 </reg32>
1183 <reg32 offset="7" name="7">
1184 <bitfield name="WRITE_DATA" low="0" high="31"/>
1185 </reg32>
1186 </domain>
1187
1188 <domain name="CP_WAIT_MEM_GTE" width="32">
1189 <doc>
1190 Wait until a memory value is greater than or equal to the
1191 reference, using signed comparison.
1192 </doc>
1193 <reg32 offset="0" name="0">
1194 <!-- Reserved for flags, presumably? Unused in FW -->
1195 <bitfield name="RESERVED" low="0" high="31" type="hex"/>
1196 </reg32>
1197 <reg32 offset="1" name="1">
1198 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
1199 </reg32>
1200 <reg32 offset="2" name="2">
1201 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
1202 </reg32>
1203 <reg32 offset="3" name="3">
1204 <bitfield name="REF" low="0" high="31"/>
1205 </reg32>
1206 </domain>
1207
1208 <domain name="CP_WAIT_REG_MEM" width="32">
1209 <doc>
1210 This uses the same internal comparison as CP_COND_WRITE,
1211 but waits until the comparison is true instead. It busy-loops in
1212 the CP for the given number of cycles before trying again.
1213 </doc>
1214 <reg32 offset="0" name="0">
1215 <bitfield name="FUNCTION" low="0" high="2" type="cp_cond_function"/>
1216 <bitfield name="SIGNED_COMPARE" pos="3" type="boolean"/>
1217 <bitfield name="POLL_MEMORY" pos="4" type="boolean"/>
1218 <bitfield name="POLL_SCRATCH" pos="5" type="boolean"/>
1219 <bitfield name="WRITE_MEMORY" pos="8" type="boolean"/>
1220 </reg32>
1221 <reg32 offset="1" name="1">
1222 <bitfield name="POLL_ADDR_LO" low="0" high="31" type="hex"/>
1223 </reg32>
1224 <reg32 offset="2" name="2">
1225 <bitfield name="POLL_ADDR_HI" low="0" high="31" type="hex"/>
1226 </reg32>
1227 <reg32 offset="3" name="3">
1228 <bitfield name="REF" low="0" high="31"/>
1229 </reg32>
1230 <reg32 offset="4" name="4">
1231 <bitfield name="MASK" low="0" high="31"/>
1232 </reg32>
1233 <reg32 offset="5" name="5">
1234 <bitfield name="DELAY_LOOP_CYCLES" low="0" high="31"/>
1235 </reg32>
1236 </domain>
1237
1238 <domain name="CP_WAIT_TWO_REGS" width="32">
1239 <doc>
1240 Waits for REG0 to not be 0 or REG1 to not equal REF
1241 </doc>
1242 <reg32 offset="0" name="0">
1243 <bitfield name="REG0" low="0" high="17" type="hex"/>
1244 </reg32>
1245 <reg32 offset="1" name="1">
1246 <bitfield name="REG1" low="0" high="17" type="hex"/>
1247 </reg32>
1248 <reg32 offset="2" name="2">
1249 <bitfield name="REF" low="0" high="31" type="uint"/>
1250 </reg32>
1251 </domain>
1252
1253 <domain name="CP_DISPATCH_COMPUTE" width="32">
1254 <reg32 offset="0" name="0"/>
1255 <reg32 offset="1" name="1">
1256 <bitfield name="X" low="0" high="31"/>
1257 </reg32>
1258 <reg32 offset="2" name="2">
1259 <bitfield name="Y" low="0" high="31"/>
1260 </reg32>
1261 <reg32 offset="3" name="3">
1262 <bitfield name="Z" low="0" high="31"/>
1263 </reg32>
1264 </domain>
1265
1266 <domain name="CP_SET_RENDER_MODE" width="32">
1267 <enum name="render_mode_cmd">
1268 <value value="1" name="BYPASS"/>
1269 <value value="2" name="BINNING"/>
1270 <value value="3" name="GMEM"/>
1271 <value value="5" name="BLIT2D"/>
1272 <!-- placeholder name.. used when CP_BLIT packets with BLIT_OP_SCALE?? -->
1273 <value value="7" name="BLIT2DSCALE"/>
1274 <!-- 8 set before going back to BYPASS exiting 2D -->
1275 <value value="8" name="END2D"/>
1276 </enum>
1277 <reg32 offset="0" name="0">
1278 <bitfield name="MODE" low="0" high="8" type="render_mode_cmd"/>
1279 <!--
1280 normally 0x1/0x3, sometimes see 0x5/0x8 with unknown registers in
1281 0x21xx range.. possibly (at least some) a5xx variants have a
1282 2d core?
1283 -->
1284 </reg32>
1285 <!-- I think first buffer is for GPU to save context in case of ctx switch? -->
1286 <reg32 offset="1" name="1">
1287 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1288 </reg32>
1289 <reg32 offset="2" name="2">
1290 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1291 </reg32>
1292 <reg32 offset="3" name="3">
1293 <!--
1294 set when in GMEM.. maybe indicates GMEM contents need to be
1295 preserved on ctx switch?
1296 -->
1297 <bitfield name="VSC_ENABLE" pos="3" type="boolean"/>
1298 <bitfield name="GMEM_ENABLE" pos="4" type="boolean"/>
1299 </reg32>
1300 <reg32 offset="4" name="4"/>
1301 <!-- second buffer looks like some cmdstream.. length in dwords: -->
1302 <reg32 offset="5" name="5">
1303 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
1304 </reg32>
1305 <reg32 offset="6" name="6">
1306 <bitfield name="ADDR_1_LO" low="0" high="31"/>
1307 </reg32>
1308 <reg32 offset="7" name="7">
1309 <bitfield name="ADDR_1_HI" low="0" high="31"/>"
1310 </reg32>
1311 </domain>
1312
1313 <!-- this looks fairly similar to CP_SET_RENDER_MODE minus first dword -->
1314 <domain name="CP_COMPUTE_CHECKPOINT" width="32">
1315 <!-- I think first buffer is for GPU to save context in case of ctx switch? -->
1316 <reg32 offset="0" name="0">
1317 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1318 </reg32>
1319 <reg32 offset="1" name="1">
1320 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1321 </reg32>
1322 <reg32 offset="2" name="2">
1323 </reg32>
1324 <!-- second buffer looks like some cmdstream.. length in dwords: -->
1325 <reg32 offset="3" name="3">
1326 <bitfield name="ADDR_1_LEN" low="0" high="31" type="uint"/>
1327 </reg32>
1328 <reg32 offset="4" name="4"/>
1329 <reg32 offset="5" name="5">
1330 <bitfield name="ADDR_1_LO" low="0" high="31"/>
1331 </reg32>
1332 <reg32 offset="6" name="6">
1333 <bitfield name="ADDR_1_HI" low="0" high="31"/>"
1334 </reg32>
1335 <reg32 offset="7" name="7"/>
1336 </domain>
1337
1338 <domain name="CP_PERFCOUNTER_ACTION" width="32">
1339 <reg32 offset="0" name="0">
1340 </reg32>
1341 <reg32 offset="1" name="1">
1342 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1343 </reg32>
1344 <reg32 offset="2" name="2">
1345 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1346 </reg32>
1347 </domain>
1348
1349 <domain name="CP_EVENT_WRITE" width="32">
1350 <reg32 offset="0" name="0">
1351 <bitfield name="EVENT" low="0" high="7" type="vgt_event_type"/>
1352 <!-- when set, write back timestamp instead of value from packet: -->
1353 <bitfield name="TIMESTAMP" pos="30" type="boolean"/>
1354 </reg32>
1355 <!--
1356 TODO what is gpuaddr for, seems to be all 0's.. maybe needed for
1357 context switch?
1358 -->
1359 <reg32 offset="1" name="1">
1360 <bitfield name="ADDR_0_LO" low="0" high="31"/>
1361 </reg32>
1362 <reg32 offset="2" name="2">
1363 <bitfield name="ADDR_0_HI" low="0" high="31"/>
1364 </reg32>
1365 <reg32 offset="3" name="3">
1366 <!-- ??? -->
1367 </reg32>
1368 </domain>
1369
1370 <domain name="CP_BLIT" width="32">
1371 <enum name="cp_blit_cmd">
1372 <value value="0" name="BLIT_OP_FILL"/>
1373 <value value="1" name="BLIT_OP_COPY"/>
1374 <value value="3" name="BLIT_OP_SCALE"/> <!-- used for mipmap generation -->
1375 </enum>
1376 <reg32 offset="0" name="0">
1377 <bitfield name="OP" low="0" high="3" type="cp_blit_cmd"/>
1378 </reg32>
1379 <reg32 offset="1" name="1">
1380 <bitfield name="SRC_X1" low="0" high="13" type="uint"/>
1381 <bitfield name="SRC_Y1" low="16" high="29" type="uint"/>
1382 </reg32>
1383 <reg32 offset="2" name="2">
1384 <bitfield name="SRC_X2" low="0" high="13" type="uint"/>
1385 <bitfield name="SRC_Y2" low="16" high="29" type="uint"/>
1386 </reg32>
1387 <reg32 offset="3" name="3">
1388 <bitfield name="DST_X1" low="0" high="13" type="uint"/>
1389 <bitfield name="DST_Y1" low="16" high="29" type="uint"/>
1390 </reg32>
1391 <reg32 offset="4" name="4">
1392 <bitfield name="DST_X2" low="0" high="13" type="uint"/>
1393 <bitfield name="DST_Y2" low="16" high="29" type="uint"/>
1394 </reg32>
1395 </domain>
1396
1397 <domain name="CP_EXEC_CS" width="32">
1398 <reg32 offset="0" name="0">
1399 </reg32>
1400 <reg32 offset="1" name="1">
1401 <bitfield name="NGROUPS_X" low="0" high="31" type="uint"/>
1402 </reg32>
1403 <reg32 offset="2" name="2">
1404 <bitfield name="NGROUPS_Y" low="0" high="31" type="uint"/>
1405 </reg32>
1406 <reg32 offset="3" name="3">
1407 <bitfield name="NGROUPS_Z" low="0" high="31" type="uint"/>
1408 </reg32>
1409 </domain>
1410
1411 <domain name="CP_EXEC_CS_INDIRECT" width="32" varset="chip" prefix="chip" variants="A4XX-">
1412 <reg32 offset="0" name="0">
1413 </reg32>
1414 <stripe variants="A4XX">
1415 <reg32 offset="1" name="1">
1416 <bitfield name="ADDR" low="0" high="31"/>
1417 </reg32>
1418 <reg32 offset="2" name="2">
1419 <!-- localsize is value minus one: -->
1420 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
1421 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
1422 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
1423 </reg32>
1424 </stripe>
1425 <stripe variants="A5XX-">
1426 <reg32 offset="1" name="1">
1427 <bitfield name="ADDR_LO" low="0" high="31"/>
1428 </reg32>
1429 <reg32 offset="2" name="2">
1430 <bitfield name="ADDR_HI" low="0" high="31"/>
1431 </reg32>
1432 <reg32 offset="3" name="3">
1433 <!-- localsize is value minus one: -->
1434 <bitfield name="LOCALSIZEX" low="2" high="11" type="uint"/>
1435 <bitfield name="LOCALSIZEY" low="12" high="21" type="uint"/>
1436 <bitfield name="LOCALSIZEZ" low="22" high="31" type="uint"/>
1437 </reg32>
1438 </stripe>
1439 </domain>
1440
1441 <domain name="CP_SET_MARKER" width="32" varset="chip" prefix="chip" variants="A6XX-">
1442 <doc>Tell CP the current operation mode, indicates save and restore procedure</doc>
1443 <enum name="a6xx_render_mode">
1444 <value value="1" name="RM6_BYPASS"/>
1445 <value value="2" name="RM6_BINNING"/>
1446 <value value="4" name="RM6_GMEM"/>
1447 <value value="5" name="RM6_ENDVIS"/>
1448 <value value="6" name="RM6_RESOLVE"/>
1449 <value value="7" name="RM6_YIELD"/>
1450 <value value="8" name="RM6_COMPUTE"/>
1451 <value value="0xc" name="RM6_BLIT2DSCALE"/> <!-- no-op (at least on current sqe fw) -->
1452
1453 <!--
1454 These values come from a6xx_set_marker() in the
1455 downstream kernel, and they can only be set by the kernel
1456 -->
1457 <value value="0xd" name="RM6_IB1LIST_START"/>
1458 <value value="0xe" name="RM6_IB1LIST_END"/>
1459 <!-- IFPC - inter-frame power collapse -->
1460 <value value="0x100" name="RM6_IFPC_ENABLE"/>
1461 <value value="0x101" name="RM6_IFPC_DISABLE"/>
1462 </enum>
1463 <reg32 offset="0" name="0">
1464 <!--
1465 NOTE: blob driver and some versions of freedreno/turnip set
1466 b4, which is unused (at least by current sqe fw), but interferes
1467 with parsing if we extend the size of the bitfield to include
1468 b8 (only sent by kernel mode driver). Really, the way the
1469 parsing works in the firmware, only b0-b3 are considered, but
1470 if b8 is set, the low bits are interpreted differently. To
1471 model this, without getting confused by spurious b4, this is
1472 described as two overlapping bitfields:
1473 -->
1474 <bitfield name="MODE" low="0" high="8" type="a6xx_render_mode"/>
1475 <bitfield name="MARKER" low="0" high="3" type="a6xx_render_mode"/>
1476 </reg32>
1477 </domain>
1478
1479 <domain name="CP_SET_PSEUDO_REG" width="32" varset="chip" prefix="chip" variants="A6XX-">
1480 <doc>Set internal CP registers, used to indicate context save data addresses</doc>
1481 <enum name="pseudo_reg">
1482 <value value="0" name="SMMU_INFO"/>
1483 <value value="1" name="NON_SECURE_SAVE_ADDR"/>
1484 <value value="2" name="SECURE_SAVE_ADDR"/>
1485 <value value="3" name="NON_PRIV_SAVE_ADDR"/>
1486 <value value="4" name="COUNTER"/>
1487 </enum>
1488 <array offset="0" name="" stride="3" length="100">
1489 <reg32 offset="0" name="0">
1490 <bitfield name="PSEUDO_REG" low="0" high="2" type="pseudo_reg"/>
1491 </reg32>
1492 <reg32 offset="1" name="1">
1493 <bitfield name="LO" low="0" high="31"/>
1494 </reg32>
1495 <reg32 offset="2" name="2">
1496 <bitfield name="HI" low="0" high="31"/>
1497 </reg32>
1498 </array>
1499 </domain>
1500
1501 <domain name="CP_REG_TEST" width="32" varset="chip" prefix="chip" variants="A6XX-">
1502 <doc>
1503 Tests bit in specified register and sets predicate for CP_COND_REG_EXEC.
1504 So:
1505
1506 opcode: CP_REG_TEST (39) (2 dwords)
1507 { REG = 0xc10 | BIT = 0 }
1508 0000: 70b90001 00000c10
1509 opcode: CP_COND_REG_EXEC (47) (3 dwords)
1510 0000: 70c70002 10000000 00000004
1511 opcode: CP_INDIRECT_BUFFER (3f) (4 dwords)
1512
1513 Will execute the CP_INDIRECT_BUFFER only if b0 in the register at
1514 offset 0x0c10 is 1
1515 </doc>
1516 <reg32 offset="0" name="0">
1517 <!-- the register to test -->
1518 <bitfield name="REG" low="0" high="17"/>
1519 <!-- the bit to test -->
1520 <bitfield name="BIT" low="20" high="24" type="uint"/>
1521 <!-- execute CP_WAIT_FOR_ME beforehand -->
1522 <bitfield name="WAIT_FOR_ME" pos="25" type="boolean"/>
1523 </reg32>
1524 </domain>
1525
1526 <!-- I *think* this existed at least as far back as a4xx -->
1527 <domain name="CP_COND_REG_EXEC" width="32">
1528 <enum name="compare_mode">
1529 <!-- use the predicate bit set by CP_REG_TEST -->
1530 <value value="1" name="PRED_TEST"/>
1531 <!-- compare two registers directly for equality -->
1532 <value value="2" name="REG_COMPARE"/>
1533 <!-- test if certain render modes are set via CP_SET_MARKER -->
1534 <value value="3" name="RENDER_MODE" variants="A6XX-"/>
1535 </enum>
1536 <reg32 offset="0" name="0">
1537 <bitfield name="REG0" low="0" high="17" type="hex"/>
1538
1539 <!--
1540 Note: these bits have the same meaning, and use the same
1541 internal mechanism as the bits in CP_SET_DRAW_STATE.
1542 When RENDER_MODE is selected, they're used as
1543 a bitmask of which modes pass the test.
1544 -->
1545
1546 <!-- RM6_BINNING -->
1547 <bitfield name="BINNING" pos="25" variants="A6XX-" type="boolean"/>
1548 <!-- all others -->
1549 <bitfield name="GMEM" pos="26" variants="A6XX-" type="boolean"/>
1550 <!-- RM6_BYPASS -->
1551 <bitfield name="SYSMEM" pos="27" variants="A6XX-" type="boolean"/>
1552
1553 <bitfield name="MODE" low="28" high="31" type="compare_mode"/>
1554 </reg32>
1555
1556 <!-- in REG_COMPARE mode, there's an extra DWORD here with REG1 -->
1557
1558 <reg32 offset="1" name="1">
1559 <bitfield name="DWORDS" low="0" high="31" type="uint"/>
1560 </reg32>
1561 </domain>
1562
1563 <domain name="CP_COND_EXEC" width="32">
1564 <doc>
1565 Executes the following DWORDs of commands if the dword at ADDR0
1566 is not equal to 0 and the dword at ADDR1 is less than REF
1567 (signed comparison).
1568 </doc>
1569 <reg32 offset="0" name="0">
1570 <bitfield name="ADDR0_LO" low="0" high="31"/>
1571 </reg32>
1572 <reg32 offset="1" name="1">
1573 <bitfield name="ADDR0_HI" low="0" high="31"/>
1574 </reg32>
1575 <reg32 offset="2" name="2">
1576 <bitfield name="ADDR1_LO" low="0" high="31"/>
1577 </reg32>
1578 <reg32 offset="3" name="3">
1579 <bitfield name="ADDR1_HI" low="0" high="31"/>
1580 </reg32>
1581 <reg32 offset="4" name="4">
1582 <bitfield name="REF" low="0" high="31"/>
1583 </reg32>
1584 <reg32 offset="5" name="5">
1585 <bitfield name="DWORDS" low="0" high="31" type="uint"/>
1586 </reg32>
1587 </domain>
1588
1589 <domain name="CP_SET_CTXSWITCH_IB" width="32">
1590 <doc>
1591 Used by the userspace driver to set various IB's which are
1592 executed during context save/restore for handling
1593 state that isn't restored by the
1594 context switch routine itself.
1595 </doc>
1596 <enum name="ctxswitch_ib">
1597 <value name="RESTORE_IB" value="0">
1598 <doc>Executed unconditionally when switching back to the context.</doc>
1599 </value>
1600 <value name="YIELD_RESTORE_IB" value="1">
1601 <doc>
1602 Executed when switching back after switching
1603 away during execution of
1604 a CP_SET_MARKER packet with RM6_YIELD as the
1605 payload *and* the normal save routine was
1606 bypassed for a shorter one. I think this is
1607 connected to the "skipsaverestore" bit set by
1608 the kernel when preempting.
1609 </doc>
1610 </value>
1611 <value name="SAVE_IB" value="2">
1612 <doc>
1613 Executed when switching away from the context,
1614 except for context switches initiated via
1615 CP_YIELD.
1616 </doc>
1617 </value>
1618 <value name="RB_SAVE_IB" value="3">
1619 <doc>
1620 This can only be set by the RB (i.e. the kernel)
1621 and executes with protected mode off, but
1622 is otherwise similar to SAVE_IB.
1623 </doc>
1624 </value>
1625 </enum>
1626 <reg32 offset="0" name="0">
1627 <bitfield name="ADDR_LO" low="0" high="31"/>
1628 </reg32>
1629 <reg32 offset="1" name="1">
1630 <bitfield name="ADDR_HI" low="0" high="31"/>
1631 </reg32>
1632 <reg32 offset="2" name="2">
1633 <bitfield name="DWORDS" low="0" high="19" type="uint"/>
1634 <bitfield name="TYPE" low="20" high="21" type="ctxswitch_ib"/>
1635 </reg32>
1636 </domain>
1637
1638 <domain name="CP_REG_WRITE" width="32">
1639 <enum name="reg_tracker">
1640 <doc>
1641 Keep shadow copies of these registers and only set them
1642 when drawing, avoiding redundant writes:
1643 - VPC_CNTL_0
1644 - HLSQ_CONTROL_1_REG
1645 - HLSQ_UNKNOWN_B980
1646 </doc>
1647 <value name="TRACK_CNTL_REG" value="0x1"/>
1648 <doc>
1649 Track RB_RENDER_CNTL, and insert a WFI in the following
1650 situation:
1651 - There is a write that disables binning
1652 - There was a draw with binning left enabled, but in
1653 BYPASS mode
1654 Presumably this is a hang workaround?
1655 </doc>
1656 <value name="TRACK_RENDER_CNTL" value="0x2"/>
1657 <doc>
1658 Do a mysterious CP_EVENT_WRITE 0x3f when the low bit of
1659 the data to write is 0. Used by the Vulkan blob with
1660 PC_UNKNOWN_9B07, but this isn't predicated on particular
1661 register(s) like the others.
1662 </doc>
1663 <value name="UNK_EVENT_WRITE" value="0x4"/>
1664 </enum>
1665 <reg32 offset="0" name="0">
1666 <bitfield name="TRACKER" low="0" high="2" type="reg_tracker"/>
1667 </reg32>
1668 </domain>
1669
1670 <domain name="CP_SMMU_TABLE_UPDATE" width="32">
1671 <doc>
1672 Note that the SMMU's definition of TTBRn can take different forms
1673 depending on the pgtable format. But a5xx+ only uses aarch64
1674 format.
1675 </doc>
1676 <reg32 offset="0" name="0">
1677 <bitfield name="TTBR0_LO" low="0" high="31"/>
1678 </reg32>
1679 <reg32 offset="1" name="1">
1680 <bitfield name="TTBR0_HI" low="0" high="15"/>
1681 <bitfield name="ASID" low="16" high="31"/>
1682 </reg32>
1683 <reg32 offset="2" name="2">
1684 <doc>Unused, does not apply to aarch64 pgtable format</doc>
1685 <bitfield name="CONTEXTIDR" low="0" high="31"/>
1686 </reg32>
1687 <reg32 offset="3" name="3">
1688 <bitfield name="CONTEXTBANK" low="0" high="31"/>
1689 </reg32>
1690 </domain>
1691
1692 </database>
1693