2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "tu_private.h"
30 #include "registers/adreno_pm4.xml.h"
31 #include "registers/adreno_common.xml.h"
32 #include "registers/a6xx.xml.h"
34 #include "vk_format.h"
40 tu_bo_list_init(struct tu_bo_list
*list
)
42 list
->count
= list
->capacity
= 0;
43 list
->bo_infos
= NULL
;
47 tu_bo_list_destroy(struct tu_bo_list
*list
)
53 tu_bo_list_reset(struct tu_bo_list
*list
)
59 * \a flags consists of MSM_SUBMIT_BO_FLAGS.
62 tu_bo_list_add_info(struct tu_bo_list
*list
,
63 const struct drm_msm_gem_submit_bo
*bo_info
)
65 for (uint32_t i
= 0; i
< list
->count
; ++i
) {
66 if (list
->bo_infos
[i
].handle
== bo_info
->handle
) {
67 assert(list
->bo_infos
[i
].presumed
== bo_info
->presumed
);
68 list
->bo_infos
[i
].flags
|= bo_info
->flags
;
73 /* grow list->bo_infos if needed */
74 if (list
->count
== list
->capacity
) {
75 uint32_t new_capacity
= MAX2(2 * list
->count
, 16);
76 struct drm_msm_gem_submit_bo
*new_bo_infos
= realloc(
77 list
->bo_infos
, new_capacity
* sizeof(struct drm_msm_gem_submit_bo
));
79 return TU_BO_LIST_FAILED
;
80 list
->bo_infos
= new_bo_infos
;
81 list
->capacity
= new_capacity
;
84 list
->bo_infos
[list
->count
] = *bo_info
;
89 tu_bo_list_add(struct tu_bo_list
*list
,
90 const struct tu_bo
*bo
,
93 return tu_bo_list_add_info(list
, &(struct drm_msm_gem_submit_bo
) {
95 .handle
= bo
->gem_handle
,
101 tu_bo_list_merge(struct tu_bo_list
*list
, const struct tu_bo_list
*other
)
103 for (uint32_t i
= 0; i
< other
->count
; i
++) {
104 if (tu_bo_list_add_info(list
, other
->bo_infos
+ i
) == TU_BO_LIST_FAILED
)
105 return VK_ERROR_OUT_OF_HOST_MEMORY
;
112 tu_tiling_config_update_gmem_layout(struct tu_tiling_config
*tiling
,
113 const struct tu_device
*dev
)
115 const uint32_t gmem_size
= dev
->physical_device
->gmem_size
;
118 for (uint32_t i
= 0; i
< tiling
->buffer_count
; i
++) {
120 offset
= align(offset
, 0x4000);
122 tiling
->gmem_offsets
[i
] = offset
;
123 offset
+= tiling
->tile0
.extent
.width
* tiling
->tile0
.extent
.height
*
124 tiling
->buffer_cpp
[i
];
127 return offset
<= gmem_size
? VK_SUCCESS
: VK_ERROR_OUT_OF_DEVICE_MEMORY
;
131 tu_tiling_config_update_tile_layout(struct tu_tiling_config
*tiling
,
132 const struct tu_device
*dev
)
134 const uint32_t tile_align_w
= dev
->physical_device
->tile_align_w
;
135 const uint32_t tile_align_h
= dev
->physical_device
->tile_align_h
;
136 const uint32_t max_tile_width
= 1024; /* A6xx */
138 tiling
->tile0
.offset
= (VkOffset2D
) {
139 .x
= tiling
->render_area
.offset
.x
& ~(tile_align_w
- 1),
140 .y
= tiling
->render_area
.offset
.y
& ~(tile_align_h
- 1),
143 const uint32_t ra_width
=
144 tiling
->render_area
.extent
.width
+
145 (tiling
->render_area
.offset
.x
- tiling
->tile0
.offset
.x
);
146 const uint32_t ra_height
=
147 tiling
->render_area
.extent
.height
+
148 (tiling
->render_area
.offset
.y
- tiling
->tile0
.offset
.y
);
150 /* start from 1 tile */
151 tiling
->tile_count
= (VkExtent2D
) {
155 tiling
->tile0
.extent
= (VkExtent2D
) {
156 .width
= align(ra_width
, tile_align_w
),
157 .height
= align(ra_height
, tile_align_h
),
160 /* do not exceed max tile width */
161 while (tiling
->tile0
.extent
.width
> max_tile_width
) {
162 tiling
->tile_count
.width
++;
163 tiling
->tile0
.extent
.width
=
164 align(ra_width
/ tiling
->tile_count
.width
, tile_align_w
);
167 /* do not exceed gmem size */
168 while (tu_tiling_config_update_gmem_layout(tiling
, dev
) != VK_SUCCESS
) {
169 if (tiling
->tile0
.extent
.width
> tiling
->tile0
.extent
.height
) {
170 tiling
->tile_count
.width
++;
171 tiling
->tile0
.extent
.width
=
172 align(ra_width
/ tiling
->tile_count
.width
, tile_align_w
);
174 tiling
->tile_count
.height
++;
175 tiling
->tile0
.extent
.height
=
176 align(ra_height
/ tiling
->tile_count
.height
, tile_align_h
);
182 tu_tiling_config_update_pipe_layout(struct tu_tiling_config
*tiling
,
183 const struct tu_device
*dev
)
185 const uint32_t max_pipe_count
= 32; /* A6xx */
187 /* start from 1 tile per pipe */
188 tiling
->pipe0
= (VkExtent2D
) {
192 tiling
->pipe_count
= tiling
->tile_count
;
194 /* do not exceed max pipe count vertically */
195 while (tiling
->pipe_count
.height
> max_pipe_count
) {
196 tiling
->pipe0
.height
+= 2;
197 tiling
->pipe_count
.height
=
198 (tiling
->tile_count
.height
+ tiling
->pipe0
.height
- 1) /
199 tiling
->pipe0
.height
;
202 /* do not exceed max pipe count */
203 while (tiling
->pipe_count
.width
* tiling
->pipe_count
.height
>
205 tiling
->pipe0
.width
+= 1;
206 tiling
->pipe_count
.width
=
207 (tiling
->tile_count
.width
+ tiling
->pipe0
.width
- 1) /
213 tu_tiling_config_update_pipes(struct tu_tiling_config
*tiling
,
214 const struct tu_device
*dev
)
216 const uint32_t max_pipe_count
= 32; /* A6xx */
217 const uint32_t used_pipe_count
=
218 tiling
->pipe_count
.width
* tiling
->pipe_count
.height
;
219 const VkExtent2D last_pipe
= {
220 .width
= tiling
->tile_count
.width
% tiling
->pipe0
.width
,
221 .height
= tiling
->tile_count
.height
% tiling
->pipe0
.height
,
224 assert(used_pipe_count
<= max_pipe_count
);
225 assert(max_pipe_count
<= ARRAY_SIZE(tiling
->pipe_config
));
227 for (uint32_t y
= 0; y
< tiling
->pipe_count
.height
; y
++) {
228 for (uint32_t x
= 0; x
< tiling
->pipe_count
.width
; x
++) {
229 const uint32_t pipe_x
= tiling
->pipe0
.width
* x
;
230 const uint32_t pipe_y
= tiling
->pipe0
.height
* y
;
231 const uint32_t pipe_w
= (x
== tiling
->pipe_count
.width
- 1)
233 : tiling
->pipe0
.width
;
234 const uint32_t pipe_h
= (y
== tiling
->pipe_count
.height
- 1)
236 : tiling
->pipe0
.height
;
237 const uint32_t n
= tiling
->pipe_count
.width
* y
+ x
;
239 tiling
->pipe_config
[n
] = A6XX_VSC_PIPE_CONFIG_REG_X(pipe_x
) |
240 A6XX_VSC_PIPE_CONFIG_REG_Y(pipe_y
) |
241 A6XX_VSC_PIPE_CONFIG_REG_W(pipe_w
) |
242 A6XX_VSC_PIPE_CONFIG_REG_H(pipe_h
);
243 tiling
->pipe_sizes
[n
] = CP_SET_BIN_DATA5_0_VSC_SIZE(pipe_w
* pipe_h
);
247 memset(tiling
->pipe_config
+ used_pipe_count
, 0,
248 sizeof(uint32_t) * (max_pipe_count
- used_pipe_count
));
252 tu_tiling_config_update(struct tu_tiling_config
*tiling
,
253 const struct tu_device
*dev
,
254 const uint32_t *buffer_cpp
,
255 uint32_t buffer_count
,
256 const VkRect2D
*render_area
)
258 /* see if there is any real change */
259 const bool ra_changed
=
261 memcmp(&tiling
->render_area
, render_area
, sizeof(*render_area
));
262 const bool buf_changed
= tiling
->buffer_count
!= buffer_count
||
263 memcmp(tiling
->buffer_cpp
, buffer_cpp
,
264 sizeof(*buffer_cpp
) * buffer_count
);
265 if (!ra_changed
&& !buf_changed
)
269 tiling
->render_area
= *render_area
;
272 memcpy(tiling
->buffer_cpp
, buffer_cpp
,
273 sizeof(*buffer_cpp
) * buffer_count
);
274 tiling
->buffer_count
= buffer_count
;
277 tu_tiling_config_update_tile_layout(tiling
, dev
);
278 tu_tiling_config_update_pipe_layout(tiling
, dev
);
279 tu_tiling_config_update_pipes(tiling
, dev
);
283 tu_tiling_config_get_tile(const struct tu_tiling_config
*tiling
,
284 const struct tu_device
*dev
,
287 struct tu_tile
*tile
)
289 /* find the pipe and the slot for tile (tx, ty) */
290 const uint32_t px
= tx
/ tiling
->pipe0
.width
;
291 const uint32_t py
= ty
/ tiling
->pipe0
.height
;
292 const uint32_t sx
= tx
- tiling
->pipe0
.width
* px
;
293 const uint32_t sy
= ty
- tiling
->pipe0
.height
* py
;
295 assert(tx
< tiling
->tile_count
.width
&& ty
< tiling
->tile_count
.height
);
296 assert(px
< tiling
->pipe_count
.width
&& py
< tiling
->pipe_count
.height
);
297 assert(sx
< tiling
->pipe0
.width
&& sy
< tiling
->pipe0
.height
);
299 /* convert to 1D indices */
300 tile
->pipe
= tiling
->pipe_count
.width
* py
+ px
;
301 tile
->slot
= tiling
->pipe0
.width
* sy
+ sx
;
303 /* get the blit area for the tile */
304 tile
->begin
= (VkOffset2D
) {
305 .x
= tiling
->tile0
.offset
.x
+ tiling
->tile0
.extent
.width
* tx
,
306 .y
= tiling
->tile0
.offset
.y
+ tiling
->tile0
.extent
.height
* ty
,
309 (tx
== tiling
->tile_count
.width
- 1)
310 ? tiling
->render_area
.offset
.x
+ tiling
->render_area
.extent
.width
311 : tile
->begin
.x
+ tiling
->tile0
.extent
.width
;
313 (ty
== tiling
->tile_count
.height
- 1)
314 ? tiling
->render_area
.offset
.y
+ tiling
->render_area
.extent
.height
315 : tile
->begin
.y
+ tiling
->tile0
.extent
.height
;
318 enum a3xx_msaa_samples
319 tu_msaa_samples(uint32_t samples
)
331 assert(!"invalid sample count");
336 static enum a4xx_index_size
337 tu6_index_size(VkIndexType type
)
340 case VK_INDEX_TYPE_UINT16
:
341 return INDEX4_SIZE_16_BIT
;
342 case VK_INDEX_TYPE_UINT32
:
343 return INDEX4_SIZE_32_BIT
;
345 unreachable("invalid VkIndexType");
346 return INDEX4_SIZE_8_BIT
;
351 tu6_emit_marker(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
353 tu_cs_emit_write_reg(cs
, cmd
->marker_reg
, ++cmd
->marker_seqno
);
357 tu6_emit_event_write(struct tu_cmd_buffer
*cmd
,
359 enum vgt_event_type event
,
362 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, need_seqno
? 4 : 1);
363 tu_cs_emit(cs
, CP_EVENT_WRITE_0_EVENT(event
));
365 tu_cs_emit_qw(cs
, cmd
->scratch_bo
.iova
);
366 tu_cs_emit(cs
, ++cmd
->scratch_seqno
);
371 tu6_emit_cache_flush(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
373 tu6_emit_event_write(cmd
, cs
, 0x31, false);
377 tu6_emit_lrz_flush(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
379 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
, false);
383 tu6_emit_wfi(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
385 if (cmd
->wait_for_idle
) {
387 cmd
->wait_for_idle
= false;
392 tu6_emit_flag_buffer(struct tu_cs
*cs
, const struct tu_image_view
*iview
)
394 uint64_t va
= tu_image_ubwc_base(iview
->image
, iview
->base_mip
, iview
->base_layer
);
395 uint32_t pitch
= tu_image_ubwc_pitch(iview
->image
, iview
->base_mip
);
396 uint32_t size
= tu_image_ubwc_size(iview
->image
, iview
->base_mip
);
397 if (iview
->image
->ubwc_size
) {
398 tu_cs_emit_qw(cs
, va
);
399 tu_cs_emit(cs
, A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_PITCH(pitch
) |
400 A6XX_RB_DEPTH_FLAG_BUFFER_PITCH_ARRAY_PITCH(size
>> 2));
402 tu_cs_emit_qw(cs
, 0);
408 tu6_emit_zs(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
410 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
411 const struct tu_subpass
*subpass
= cmd
->state
.subpass
;
412 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
414 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
415 if (a
== VK_ATTACHMENT_UNUSED
) {
416 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_BUFFER_INFO
, 6);
417 tu_cs_emit(cs
, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE
));
418 tu_cs_emit(cs
, 0x00000000); /* RB_DEPTH_BUFFER_PITCH */
419 tu_cs_emit(cs
, 0x00000000); /* RB_DEPTH_BUFFER_ARRAY_PITCH */
420 tu_cs_emit(cs
, 0x00000000); /* RB_DEPTH_BUFFER_BASE_LO */
421 tu_cs_emit(cs
, 0x00000000); /* RB_DEPTH_BUFFER_BASE_HI */
422 tu_cs_emit(cs
, 0x00000000); /* RB_DEPTH_BUFFER_BASE_GMEM */
424 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO
, 1);
426 A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(DEPTH6_NONE
));
428 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO
, 5);
429 tu_cs_emit(cs
, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
430 tu_cs_emit(cs
, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
431 tu_cs_emit(cs
, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
432 tu_cs_emit(cs
, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
433 tu_cs_emit(cs
, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
435 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCIL_INFO
, 1);
436 tu_cs_emit(cs
, 0x00000000); /* RB_STENCIL_INFO */
441 uint32_t gmem_index
= 0;
442 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
443 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
444 if (a
!= VK_ATTACHMENT_UNUSED
)
448 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
449 enum a6xx_depth_format fmt
= tu6_pipe2depth(iview
->vk_format
);
451 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_BUFFER_INFO
, 6);
452 tu_cs_emit(cs
, A6XX_RB_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt
));
453 tu_cs_emit(cs
, A6XX_RB_DEPTH_BUFFER_PITCH(tu_image_stride(iview
->image
, iview
->base_mip
)));
454 tu_cs_emit(cs
, A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(iview
->image
->layer_size
));
455 tu_cs_emit_qw(cs
, tu_image_base(iview
->image
, iview
->base_mip
, iview
->base_layer
));
456 tu_cs_emit(cs
, tiling
->gmem_offsets
[gmem_index
]);
458 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SU_DEPTH_BUFFER_INFO
, 1);
459 tu_cs_emit(cs
, A6XX_GRAS_SU_DEPTH_BUFFER_INFO_DEPTH_FORMAT(fmt
));
461 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO
, 3);
462 tu6_emit_flag_buffer(cs
, iview
);
464 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_LRZ_BUFFER_BASE_LO
, 5);
465 tu_cs_emit(cs
, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_LO */
466 tu_cs_emit(cs
, 0x00000000); /* RB_DEPTH_FLAG_BUFFER_BASE_HI */
467 tu_cs_emit(cs
, 0x00000000); /* GRAS_LRZ_BUFFER_PITCH */
468 tu_cs_emit(cs
, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_LO */
469 tu_cs_emit(cs
, 0x00000000); /* GRAS_LRZ_FAST_CLEAR_BUFFER_BASE_HI */
471 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCIL_INFO
, 1);
472 tu_cs_emit(cs
, 0x00000000); /* RB_STENCIL_INFO */
478 tu6_emit_mrt(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
480 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
481 const struct tu_subpass
*subpass
= cmd
->state
.subpass
;
482 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
483 unsigned char mrt_comp
[MAX_RTS
] = { 0 };
484 unsigned srgb_cntl
= 0;
486 uint32_t gmem_index
= 0;
487 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
488 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
489 if (a
== VK_ATTACHMENT_UNUSED
)
492 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
493 const enum a6xx_tile_mode tile_mode
=
494 tu6_get_image_tile_mode(iview
->image
, iview
->base_mip
);
498 if (vk_format_is_srgb(iview
->vk_format
))
499 srgb_cntl
|= (1 << i
);
501 const struct tu_native_format
*format
=
502 tu6_get_native_format(iview
->vk_format
);
503 assert(format
&& format
->rb
>= 0);
505 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_BUF_INFO(i
), 6);
506 tu_cs_emit(cs
, A6XX_RB_MRT_BUF_INFO_COLOR_FORMAT(format
->rb
) |
507 A6XX_RB_MRT_BUF_INFO_COLOR_TILE_MODE(tile_mode
) |
508 A6XX_RB_MRT_BUF_INFO_COLOR_SWAP(format
->swap
));
509 tu_cs_emit(cs
, A6XX_RB_MRT_PITCH(tu_image_stride(iview
->image
, iview
->base_mip
)));
510 tu_cs_emit(cs
, A6XX_RB_MRT_ARRAY_PITCH(iview
->image
->layer_size
));
511 tu_cs_emit_qw(cs
, tu_image_base(iview
->image
, iview
->base_mip
, iview
->base_layer
));
513 cs
, tiling
->gmem_offsets
[gmem_index
++]); /* RB_MRT[i].BASE_GMEM */
515 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_MRT_REG(i
), 1);
516 tu_cs_emit(cs
, A6XX_SP_FS_MRT_REG_COLOR_FORMAT(format
->rb
));
518 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_FLAG_BUFFER(i
), 3);
519 tu6_emit_flag_buffer(cs
, iview
);
522 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_SRGB_CNTL
, 1);
523 tu_cs_emit(cs
, srgb_cntl
);
525 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_SRGB_CNTL
, 1);
526 tu_cs_emit(cs
, srgb_cntl
);
528 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_RENDER_COMPONENTS
, 1);
529 tu_cs_emit(cs
, A6XX_RB_RENDER_COMPONENTS_RT0(mrt_comp
[0]) |
530 A6XX_RB_RENDER_COMPONENTS_RT1(mrt_comp
[1]) |
531 A6XX_RB_RENDER_COMPONENTS_RT2(mrt_comp
[2]) |
532 A6XX_RB_RENDER_COMPONENTS_RT3(mrt_comp
[3]) |
533 A6XX_RB_RENDER_COMPONENTS_RT4(mrt_comp
[4]) |
534 A6XX_RB_RENDER_COMPONENTS_RT5(mrt_comp
[5]) |
535 A6XX_RB_RENDER_COMPONENTS_RT6(mrt_comp
[6]) |
536 A6XX_RB_RENDER_COMPONENTS_RT7(mrt_comp
[7]));
538 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_FS_RENDER_COMPONENTS
, 1);
539 tu_cs_emit(cs
, A6XX_SP_FS_RENDER_COMPONENTS_RT0(mrt_comp
[0]) |
540 A6XX_SP_FS_RENDER_COMPONENTS_RT1(mrt_comp
[1]) |
541 A6XX_SP_FS_RENDER_COMPONENTS_RT2(mrt_comp
[2]) |
542 A6XX_SP_FS_RENDER_COMPONENTS_RT3(mrt_comp
[3]) |
543 A6XX_SP_FS_RENDER_COMPONENTS_RT4(mrt_comp
[4]) |
544 A6XX_SP_FS_RENDER_COMPONENTS_RT5(mrt_comp
[5]) |
545 A6XX_SP_FS_RENDER_COMPONENTS_RT6(mrt_comp
[6]) |
546 A6XX_SP_FS_RENDER_COMPONENTS_RT7(mrt_comp
[7]));
550 tu6_emit_msaa(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
552 const struct tu_subpass
*subpass
= cmd
->state
.subpass
;
553 const enum a3xx_msaa_samples samples
=
554 tu_msaa_samples(subpass
->max_sample_count
);
556 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_TP_RAS_MSAA_CNTL
, 2);
557 tu_cs_emit(cs
, A6XX_SP_TP_RAS_MSAA_CNTL_SAMPLES(samples
));
558 tu_cs_emit(cs
, A6XX_SP_TP_DEST_MSAA_CNTL_SAMPLES(samples
) |
559 COND(samples
== MSAA_ONE
, A6XX_SP_TP_DEST_MSAA_CNTL_MSAA_DISABLE
));
561 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_RAS_MSAA_CNTL
, 2);
562 tu_cs_emit(cs
, A6XX_GRAS_RAS_MSAA_CNTL_SAMPLES(samples
));
563 tu_cs_emit(cs
, A6XX_GRAS_DEST_MSAA_CNTL_SAMPLES(samples
) |
564 COND(samples
== MSAA_ONE
, A6XX_GRAS_DEST_MSAA_CNTL_MSAA_DISABLE
));
566 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_RAS_MSAA_CNTL
, 2);
567 tu_cs_emit(cs
, A6XX_RB_RAS_MSAA_CNTL_SAMPLES(samples
));
568 tu_cs_emit(cs
, A6XX_RB_DEST_MSAA_CNTL_SAMPLES(samples
) |
569 COND(samples
== MSAA_ONE
, A6XX_RB_DEST_MSAA_CNTL_MSAA_DISABLE
));
571 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MSAA_CNTL
, 1);
572 tu_cs_emit(cs
, A6XX_RB_MSAA_CNTL_SAMPLES(samples
));
576 tu6_emit_bin_size(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
, uint32_t flags
)
578 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
579 const uint32_t bin_w
= tiling
->tile0
.extent
.width
;
580 const uint32_t bin_h
= tiling
->tile0
.extent
.height
;
582 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_BIN_CONTROL
, 1);
583 tu_cs_emit(cs
, A6XX_GRAS_BIN_CONTROL_BINW(bin_w
) |
584 A6XX_GRAS_BIN_CONTROL_BINH(bin_h
) | flags
);
586 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BIN_CONTROL
, 1);
587 tu_cs_emit(cs
, A6XX_RB_BIN_CONTROL_BINW(bin_w
) |
588 A6XX_RB_BIN_CONTROL_BINH(bin_h
) | flags
);
590 /* no flag for RB_BIN_CONTROL2... */
591 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BIN_CONTROL2
, 1);
592 tu_cs_emit(cs
, A6XX_RB_BIN_CONTROL2_BINW(bin_w
) |
593 A6XX_RB_BIN_CONTROL2_BINH(bin_h
));
597 tu6_emit_render_cntl(struct tu_cmd_buffer
*cmd
,
602 cntl
|= A6XX_RB_RENDER_CNTL_UNK4
;
604 cntl
|= A6XX_RB_RENDER_CNTL_BINNING
;
606 tu_cs_emit_pkt7(cs
, CP_REG_WRITE
, 3);
608 tu_cs_emit(cs
, REG_A6XX_RB_RENDER_CNTL
);
609 tu_cs_emit(cs
, cntl
);
613 tu6_emit_blit_scissor(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
615 const VkRect2D
*render_area
= &cmd
->state
.tiling_config
.render_area
;
616 const uint32_t x1
= render_area
->offset
.x
;
617 const uint32_t y1
= render_area
->offset
.y
;
618 const uint32_t x2
= x1
+ render_area
->extent
.width
- 1;
619 const uint32_t y2
= y1
+ render_area
->extent
.height
- 1;
621 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLIT_SCISSOR_TL
, 2);
623 A6XX_RB_BLIT_SCISSOR_TL_X(x1
) | A6XX_RB_BLIT_SCISSOR_TL_Y(y1
));
625 A6XX_RB_BLIT_SCISSOR_BR_X(x2
) | A6XX_RB_BLIT_SCISSOR_BR_Y(y2
));
629 tu6_emit_blit_info(struct tu_cmd_buffer
*cmd
,
631 const struct tu_image_view
*iview
,
632 uint32_t gmem_offset
,
635 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLIT_INFO
, 1);
636 tu_cs_emit(cs
, blit_info
);
638 const struct tu_native_format
*format
=
639 tu6_get_native_format(iview
->vk_format
);
640 assert(format
&& format
->rb
>= 0);
642 enum a6xx_tile_mode tile_mode
=
643 tu6_get_image_tile_mode(iview
->image
, iview
->base_mip
);
644 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLIT_DST_INFO
, 5);
645 tu_cs_emit(cs
, A6XX_RB_BLIT_DST_INFO_TILE_MODE(tile_mode
) |
646 A6XX_RB_BLIT_DST_INFO_SAMPLES(tu_msaa_samples(iview
->image
->samples
)) |
647 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format
->rb
) |
648 A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(format
->swap
) |
649 COND(iview
->image
->ubwc_size
, A6XX_RB_BLIT_DST_INFO_FLAGS
));
650 tu_cs_emit_qw(cs
, tu_image_base(iview
->image
, iview
->base_mip
, iview
->base_layer
));
651 tu_cs_emit(cs
, A6XX_RB_BLIT_DST_PITCH(tu_image_stride(iview
->image
, iview
->base_mip
)));
652 tu_cs_emit(cs
, A6XX_RB_BLIT_DST_ARRAY_PITCH(iview
->image
->layer_size
));
654 if (iview
->image
->ubwc_size
) {
655 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLIT_FLAG_DST_LO
, 3);
656 tu6_emit_flag_buffer(cs
, iview
);
659 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLIT_BASE_GMEM
, 1);
660 tu_cs_emit(cs
, gmem_offset
);
664 tu6_emit_blit_clear(struct tu_cmd_buffer
*cmd
,
666 const struct tu_image_view
*iview
,
667 uint32_t gmem_offset
,
668 const VkClearValue
*clear_value
)
670 const struct tu_native_format
*format
=
671 tu6_get_native_format(iview
->vk_format
);
672 assert(format
&& format
->rb
>= 0);
673 /* must be WZYX; other values are ignored */
674 const enum a3xx_color_swap swap
= WZYX
;
676 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLIT_DST_INFO
, 1);
677 tu_cs_emit(cs
, A6XX_RB_BLIT_DST_INFO_TILE_MODE(TILE6_LINEAR
) |
678 A6XX_RB_BLIT_DST_INFO_SAMPLES(tu_msaa_samples(iview
->image
->samples
)) |
679 A6XX_RB_BLIT_DST_INFO_COLOR_FORMAT(format
->rb
) |
680 A6XX_RB_BLIT_DST_INFO_COLOR_SWAP(swap
));
682 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLIT_INFO
, 1);
683 tu_cs_emit(cs
, A6XX_RB_BLIT_INFO_GMEM
| A6XX_RB_BLIT_INFO_CLEAR_MASK(0xf));
685 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLIT_BASE_GMEM
, 1);
686 tu_cs_emit(cs
, gmem_offset
);
688 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_UNKNOWN_88D0
, 1);
691 /* pack clear_value into WZYX order */
692 uint32_t clear_vals
[4] = { 0 };
693 tu_pack_clear_value(clear_value
, iview
->vk_format
, clear_vals
);
695 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_BLIT_CLEAR_COLOR_DW0
, 4);
696 tu_cs_emit(cs
, clear_vals
[0]);
697 tu_cs_emit(cs
, clear_vals
[1]);
698 tu_cs_emit(cs
, clear_vals
[2]);
699 tu_cs_emit(cs
, clear_vals
[3]);
703 tu6_emit_blit(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
705 tu6_emit_marker(cmd
, cs
);
706 tu6_emit_event_write(cmd
, cs
, BLIT
, false);
707 tu6_emit_marker(cmd
, cs
);
711 tu6_emit_window_scissor(struct tu_cmd_buffer
*cmd
,
718 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_SC_WINDOW_SCISSOR_TL
, 2);
719 tu_cs_emit(cs
, A6XX_GRAS_SC_WINDOW_SCISSOR_TL_X(x1
) |
720 A6XX_GRAS_SC_WINDOW_SCISSOR_TL_Y(y1
));
721 tu_cs_emit(cs
, A6XX_GRAS_SC_WINDOW_SCISSOR_BR_X(x2
) |
722 A6XX_GRAS_SC_WINDOW_SCISSOR_BR_Y(y2
));
724 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_RESOLVE_CNTL_1
, 2);
726 cs
, A6XX_GRAS_RESOLVE_CNTL_1_X(x1
) | A6XX_GRAS_RESOLVE_CNTL_1_Y(y1
));
728 cs
, A6XX_GRAS_RESOLVE_CNTL_2_X(x2
) | A6XX_GRAS_RESOLVE_CNTL_2_Y(y2
));
732 tu6_emit_window_offset(struct tu_cmd_buffer
*cmd
,
737 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_WINDOW_OFFSET
, 1);
738 tu_cs_emit(cs
, A6XX_RB_WINDOW_OFFSET_X(x1
) | A6XX_RB_WINDOW_OFFSET_Y(y1
));
740 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_WINDOW_OFFSET2
, 1);
742 A6XX_RB_WINDOW_OFFSET2_X(x1
) | A6XX_RB_WINDOW_OFFSET2_Y(y1
));
744 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_WINDOW_OFFSET
, 1);
745 tu_cs_emit(cs
, A6XX_SP_WINDOW_OFFSET_X(x1
) | A6XX_SP_WINDOW_OFFSET_Y(y1
));
747 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_TP_WINDOW_OFFSET
, 1);
749 cs
, A6XX_SP_TP_WINDOW_OFFSET_X(x1
) | A6XX_SP_TP_WINDOW_OFFSET_Y(y1
));
753 tu6_emit_tile_select(struct tu_cmd_buffer
*cmd
,
755 const struct tu_tile
*tile
)
757 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
758 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(0x7));
760 tu6_emit_marker(cmd
, cs
);
761 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
762 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM
) | 0x10);
763 tu6_emit_marker(cmd
, cs
);
765 const uint32_t x1
= tile
->begin
.x
;
766 const uint32_t y1
= tile
->begin
.y
;
767 const uint32_t x2
= tile
->end
.x
- 1;
768 const uint32_t y2
= tile
->end
.y
- 1;
769 tu6_emit_window_scissor(cmd
, cs
, x1
, y1
, x2
, y2
);
770 tu6_emit_window_offset(cmd
, cs
, x1
, y1
);
772 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_SO_OVERRIDE
, 1);
773 tu_cs_emit(cs
, A6XX_VPC_SO_OVERRIDE_SO_DISABLE
);
778 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
781 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
787 tu6_emit_tile_load_attachment(struct tu_cmd_buffer
*cmd
,
792 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
793 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
794 const struct tu_attachment_state
*attachments
= cmd
->state
.attachments
;
796 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
797 const struct tu_attachment_state
*att
= attachments
+ a
;
798 if (att
->pending_clear_aspects
) {
799 tu6_emit_blit_clear(cmd
, cs
, iview
,
800 tiling
->gmem_offsets
[gmem_index
],
803 tu6_emit_blit_info(cmd
, cs
, iview
,
804 tiling
->gmem_offsets
[gmem_index
],
805 A6XX_RB_BLIT_INFO_UNK0
| A6XX_RB_BLIT_INFO_GMEM
);
808 tu6_emit_blit(cmd
, cs
);
812 tu6_emit_tile_load(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
814 const struct tu_subpass
*subpass
= cmd
->state
.subpass
;
816 tu6_emit_blit_scissor(cmd
, cs
);
818 uint32_t gmem_index
= 0;
819 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
820 const uint32_t a
= subpass
->color_attachments
[i
].attachment
;
821 if (a
!= VK_ATTACHMENT_UNUSED
)
822 tu6_emit_tile_load_attachment(cmd
, cs
, a
, gmem_index
++);
825 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
826 if (a
!= VK_ATTACHMENT_UNUSED
)
827 tu6_emit_tile_load_attachment(cmd
, cs
, a
, gmem_index
);
831 tu6_emit_tile_store(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
833 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
834 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
840 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
841 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
842 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
843 CP_SET_DRAW_STATE__0_GROUP_ID(0));
844 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
845 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
847 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
850 tu6_emit_marker(cmd
, cs
);
851 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
852 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE
) | 0x10);
853 tu6_emit_marker(cmd
, cs
);
855 tu6_emit_blit_scissor(cmd
, cs
);
857 uint32_t gmem_index
= 0;
858 for (uint32_t i
= 0; i
< cmd
->state
.subpass
->color_count
; ++i
) {
859 uint32_t a
= cmd
->state
.subpass
->color_attachments
[i
].attachment
;
860 if (a
== VK_ATTACHMENT_UNUSED
)
863 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
864 tu6_emit_blit_info(cmd
, cs
, iview
, tiling
->gmem_offsets
[gmem_index
++],
866 tu6_emit_blit(cmd
, cs
);
869 const uint32_t a
= cmd
->state
.subpass
->depth_stencil_attachment
.attachment
;
870 if (a
!= VK_ATTACHMENT_UNUSED
) {
871 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
872 tu6_emit_blit_info(cmd
, cs
, iview
, tiling
->gmem_offsets
[gmem_index
],
874 tu6_emit_blit(cmd
, cs
);
879 tu6_emit_restart_index(struct tu_cs
*cs
, uint32_t restart_index
)
881 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_RESTART_INDEX
, 1);
882 tu_cs_emit(cs
, restart_index
);
886 tu6_init_hw(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
888 VkResult result
= tu_cs_reserve_space(cmd
->device
, cs
, 256);
889 if (result
!= VK_SUCCESS
) {
890 cmd
->record_result
= result
;
894 tu6_emit_cache_flush(cmd
, cs
);
896 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UPDATE_CNTL
, 0xfffff);
898 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_CCU_CNTL
, 0x7c400004);
899 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E04
, 0x00100000);
900 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE04
, 0x8);
901 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE00
, 0);
902 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE0F
, 0x3f);
903 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B605
, 0x44);
904 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B600
, 0x100000);
905 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE00
, 0x80);
906 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE01
, 0);
908 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9600
, 0);
909 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8600
, 0x880);
910 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE04
, 0);
911 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE03
, 0x00000410);
912 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_IBO_COUNT
, 0);
913 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B182
, 0);
914 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BB11
, 0);
915 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_UNKNOWN_0E12
, 0x3200000);
916 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_CLIENT_PF
, 4);
917 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E01
, 0x0);
918 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AB00
, 0x5);
919 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_UNKNOWN_A009
, 0x00000001);
920 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8811
, 0x00000010);
921 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x1f);
923 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_SRGB_CNTL
, 0);
925 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8101
, 0);
926 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_SAMPLE_CNTL
, 0);
927 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8110
, 0);
929 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL0
, 0x401);
930 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL1
, 0);
931 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_FS_OUTPUT_CNTL0
, 0);
932 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_SAMPLE_CNTL
, 0);
933 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8818
, 0);
934 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8819
, 0);
935 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881A
, 0);
936 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881B
, 0);
937 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881C
, 0);
938 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881D
, 0);
939 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881E
, 0);
940 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_88F0
, 0);
942 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9101
, 0xffff00);
943 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9107
, 0);
945 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9236
, 1);
946 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9300
, 0);
948 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_SO_OVERRIDE
,
949 A6XX_VPC_SO_OVERRIDE_SO_DISABLE
);
951 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9801
, 0);
952 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9806
, 0);
953 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9980
, 0);
955 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_6
, 0);
956 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9B07
, 0);
958 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A81B
, 0);
960 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B183
, 0);
962 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8099
, 0);
963 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_809B
, 0);
964 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A0
, 2);
965 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80AF
, 0);
966 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9210
, 0);
967 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9211
, 0);
968 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9602
, 0);
969 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9981
, 0x3);
970 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9E72
, 0);
971 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9108
, 0x3);
972 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_TP_UNKNOWN_B304
, 0);
973 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_TP_UNKNOWN_B309
, 0x000000a2);
974 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8804
, 0);
975 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A4
, 0);
976 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A5
, 0);
977 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A6
, 0);
978 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8805
, 0);
979 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8806
, 0);
980 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8878
, 0);
981 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8879
, 0);
982 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_CONTROL_5_REG
, 0xfc);
984 tu6_emit_marker(cmd
, cs
);
986 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_MODE_CNTL
, 0x00000000);
988 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_UNKNOWN_A008
, 0);
990 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x0000001f);
992 /* we don't use this yet.. probably best to disable.. */
993 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
994 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
995 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
996 CP_SET_DRAW_STATE__0_GROUP_ID(0));
997 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
998 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1000 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_SO_BUFFER_BASE_LO(0), 3);
1001 tu_cs_emit(cs
, 0x00000000); /* VPC_SO_BUFFER_BASE_LO_0 */
1002 tu_cs_emit(cs
, 0x00000000); /* VPC_SO_BUFFER_BASE_HI_0 */
1003 tu_cs_emit(cs
, 0x00000000); /* VPC_SO_BUFFER_SIZE_0 */
1005 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_SO_FLUSH_BASE_LO(0), 2);
1006 tu_cs_emit(cs
, 0x00000000); /* VPC_SO_FLUSH_BASE_LO_0 */
1007 tu_cs_emit(cs
, 0x00000000); /* VPC_SO_FLUSH_BASE_HI_0 */
1009 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_SO_BUF_CNTL
, 1);
1010 tu_cs_emit(cs
, 0x00000000); /* VPC_SO_BUF_CNTL */
1012 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_SO_BUFFER_OFFSET(0), 1);
1013 tu_cs_emit(cs
, 0x00000000); /* UNKNOWN_E2AB */
1015 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_SO_BUFFER_BASE_LO(1), 3);
1016 tu_cs_emit(cs
, 0x00000000);
1017 tu_cs_emit(cs
, 0x00000000);
1018 tu_cs_emit(cs
, 0x00000000);
1020 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_SO_BUFFER_OFFSET(1), 6);
1021 tu_cs_emit(cs
, 0x00000000);
1022 tu_cs_emit(cs
, 0x00000000);
1023 tu_cs_emit(cs
, 0x00000000);
1024 tu_cs_emit(cs
, 0x00000000);
1025 tu_cs_emit(cs
, 0x00000000);
1026 tu_cs_emit(cs
, 0x00000000);
1028 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_SO_BUFFER_OFFSET(2), 6);
1029 tu_cs_emit(cs
, 0x00000000);
1030 tu_cs_emit(cs
, 0x00000000);
1031 tu_cs_emit(cs
, 0x00000000);
1032 tu_cs_emit(cs
, 0x00000000);
1033 tu_cs_emit(cs
, 0x00000000);
1034 tu_cs_emit(cs
, 0x00000000);
1036 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_SO_BUFFER_OFFSET(3), 3);
1037 tu_cs_emit(cs
, 0x00000000);
1038 tu_cs_emit(cs
, 0x00000000);
1039 tu_cs_emit(cs
, 0x00000000);
1041 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_HS_CTRL_REG0
, 1);
1042 tu_cs_emit(cs
, 0x00000000);
1044 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_GS_CTRL_REG0
, 1);
1045 tu_cs_emit(cs
, 0x00000000);
1047 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_LRZ_CNTL
, 1);
1048 tu_cs_emit(cs
, 0x00000000);
1050 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_LRZ_CNTL
, 1);
1051 tu_cs_emit(cs
, 0x00000000);
1053 tu_cs_sanity_check(cs
);
1057 tu6_render_begin(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1059 VkResult result
= tu_cs_reserve_space(cmd
->device
, cs
, 256);
1060 if (result
!= VK_SUCCESS
) {
1061 cmd
->record_result
= result
;
1065 tu6_emit_lrz_flush(cmd
, cs
);
1069 tu6_emit_cache_flush(cmd
, cs
);
1071 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1072 tu_cs_emit(cs
, 0x0);
1074 /* 0x10000000 for BYPASS.. 0x7c13c080 for GMEM: */
1075 tu6_emit_wfi(cmd
, cs
);
1076 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_CCU_CNTL
, 1);
1077 tu_cs_emit(cs
, 0x7c400004); /* RB_CCU_CNTL */
1079 tu6_emit_zs(cmd
, cs
);
1080 tu6_emit_mrt(cmd
, cs
);
1081 tu6_emit_msaa(cmd
, cs
);
1086 tu6_emit_bin_size(cmd
, cs
, 0x6000000);
1090 tu6_emit_render_cntl(cmd
, cs
, false);
1092 tu_cs_sanity_check(cs
);
1096 tu6_render_tile(struct tu_cmd_buffer
*cmd
,
1098 const struct tu_tile
*tile
)
1100 const uint32_t render_tile_space
= 64 + tu_cs_get_call_size(&cmd
->draw_cs
);
1101 VkResult result
= tu_cs_reserve_space(cmd
->device
, cs
, render_tile_space
);
1102 if (result
!= VK_SUCCESS
) {
1103 cmd
->record_result
= result
;
1107 tu6_emit_tile_select(cmd
, cs
, tile
);
1108 tu_cs_emit_ib(cs
, &cmd
->state
.tile_load_ib
);
1110 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
1111 cmd
->wait_for_idle
= true;
1113 tu_cs_emit_ib(cs
, &cmd
->state
.tile_store_ib
);
1115 tu_cs_sanity_check(cs
);
1119 tu6_render_end(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1121 const struct tu_subpass
*subpass
= cmd
->state
.subpass
;
1122 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
1124 VkResult result
= tu_cs_reserve_space(cmd
->device
, cs
, 16);
1125 if (result
!= VK_SUCCESS
) {
1126 cmd
->record_result
= result
;
1130 tu_cs_emit_pkt4(cs
, REG_A6XX_GRAS_LRZ_CNTL
, 1);
1131 tu_cs_emit(cs
, A6XX_GRAS_LRZ_CNTL_ENABLE
| A6XX_GRAS_LRZ_CNTL_UNK3
);
1133 tu6_emit_lrz_flush(cmd
, cs
);
1135 tu6_emit_event_write(cmd
, cs
, CACHE_FLUSH_TS
, true);
1137 if (subpass
->has_resolve
) {
1138 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
1139 struct tu_subpass_attachment src_att
= subpass
->color_attachments
[i
];
1140 struct tu_subpass_attachment dst_att
= subpass
->resolve_attachments
[i
];
1142 if (dst_att
.attachment
== VK_ATTACHMENT_UNUSED
)
1145 struct tu_image
*src_img
= fb
->attachments
[src_att
.attachment
].attachment
->image
;
1146 struct tu_image
*dst_img
= fb
->attachments
[dst_att
.attachment
].attachment
->image
;
1148 assert(src_img
->extent
.width
== dst_img
->extent
.width
);
1149 assert(src_img
->extent
.height
== dst_img
->extent
.height
);
1151 tu_bo_list_add(&cmd
->bo_list
, src_img
->bo
, MSM_SUBMIT_BO_READ
);
1152 tu_bo_list_add(&cmd
->bo_list
, dst_img
->bo
, MSM_SUBMIT_BO_WRITE
);
1154 tu_blit(cmd
, &(struct tu_blit
) {
1155 .dst
= tu_blit_surf_whole(dst_img
, 0, 0),
1156 .src
= tu_blit_surf_whole(src_img
, 0, 0),
1162 tu_cs_sanity_check(cs
);
1166 tu_cmd_render_tiles(struct tu_cmd_buffer
*cmd
)
1168 const struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1170 tu6_render_begin(cmd
, &cmd
->cs
);
1172 for (uint32_t y
= 0; y
< tiling
->tile_count
.height
; y
++) {
1173 for (uint32_t x
= 0; x
< tiling
->tile_count
.width
; x
++) {
1174 struct tu_tile tile
;
1175 tu_tiling_config_get_tile(tiling
, cmd
->device
, x
, y
, &tile
);
1176 tu6_render_tile(cmd
, &cmd
->cs
, &tile
);
1180 tu6_render_end(cmd
, &cmd
->cs
);
1184 tu_cmd_prepare_tile_load_ib(struct tu_cmd_buffer
*cmd
)
1186 const uint32_t tile_load_space
= 16 + 32 * MAX_RTS
;
1187 const struct tu_subpass
*subpass
= cmd
->state
.subpass
;
1188 struct tu_attachment_state
*attachments
= cmd
->state
.attachments
;
1189 struct tu_cs sub_cs
;
1191 VkResult result
= tu_cs_begin_sub_stream(cmd
->device
, &cmd
->tile_cs
,
1192 tile_load_space
, &sub_cs
);
1193 if (result
!= VK_SUCCESS
) {
1194 cmd
->record_result
= result
;
1198 /* emit to tile-load sub_cs */
1199 tu6_emit_tile_load(cmd
, &sub_cs
);
1201 cmd
->state
.tile_load_ib
= tu_cs_end_sub_stream(&cmd
->tile_cs
, &sub_cs
);
1203 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
1204 const uint32_t a
= subpass
->color_attachments
[i
].attachment
;
1205 if (a
!= VK_ATTACHMENT_UNUSED
)
1206 attachments
[a
].pending_clear_aspects
= 0;
1211 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer
*cmd
)
1213 const uint32_t tile_store_space
= 32 + 32 * MAX_RTS
;
1214 struct tu_cs sub_cs
;
1216 VkResult result
= tu_cs_begin_sub_stream(cmd
->device
, &cmd
->tile_cs
,
1217 tile_store_space
, &sub_cs
);
1218 if (result
!= VK_SUCCESS
) {
1219 cmd
->record_result
= result
;
1223 /* emit to tile-store sub_cs */
1224 tu6_emit_tile_store(cmd
, &sub_cs
);
1226 cmd
->state
.tile_store_ib
= tu_cs_end_sub_stream(&cmd
->tile_cs
, &sub_cs
);
1230 tu_cmd_update_tiling_config(struct tu_cmd_buffer
*cmd
,
1231 const VkRect2D
*render_area
)
1233 const struct tu_device
*dev
= cmd
->device
;
1234 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
1235 const struct tu_subpass
*subpass
= cmd
->state
.subpass
;
1236 struct tu_tiling_config
*tiling
= &cmd
->state
.tiling_config
;
1238 uint32_t buffer_cpp
[MAX_RTS
+ 2];
1239 uint32_t buffer_count
= 0;
1241 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
1242 const uint32_t a
= subpass
->color_attachments
[i
].attachment
;
1243 if (a
== VK_ATTACHMENT_UNUSED
)
1246 const struct tu_render_pass_attachment
*att
= &pass
->attachments
[a
];
1247 buffer_cpp
[buffer_count
++] =
1248 vk_format_get_blocksize(att
->format
) * att
->samples
;
1251 if (subpass
->depth_stencil_attachment
.attachment
!= VK_ATTACHMENT_UNUSED
) {
1252 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
1253 const struct tu_render_pass_attachment
*att
= &pass
->attachments
[a
];
1256 assert(att
->format
!= VK_FORMAT_D32_SFLOAT_S8_UINT
);
1258 buffer_cpp
[buffer_count
++] =
1259 vk_format_get_blocksize(att
->format
) * att
->samples
;
1262 tu_tiling_config_update(tiling
, dev
, buffer_cpp
, buffer_count
,
1266 const struct tu_dynamic_state default_dynamic_state
= {
1282 .blend_constants
= { 0.0f
, 0.0f
, 0.0f
, 0.0f
},
1288 .stencil_compare_mask
=
1293 .stencil_write_mask
=
1298 .stencil_reference
=
1305 static void UNUSED
/* FINISHME */
1306 tu_bind_dynamic_state(struct tu_cmd_buffer
*cmd_buffer
,
1307 const struct tu_dynamic_state
*src
)
1309 struct tu_dynamic_state
*dest
= &cmd_buffer
->state
.dynamic
;
1310 uint32_t copy_mask
= src
->mask
;
1311 uint32_t dest_mask
= 0;
1313 tu_use_args(cmd_buffer
); /* FINISHME */
1315 /* Make sure to copy the number of viewports/scissors because they can
1316 * only be specified at pipeline creation time.
1318 dest
->viewport
.count
= src
->viewport
.count
;
1319 dest
->scissor
.count
= src
->scissor
.count
;
1320 dest
->discard_rectangle
.count
= src
->discard_rectangle
.count
;
1322 if (copy_mask
& TU_DYNAMIC_VIEWPORT
) {
1323 if (memcmp(&dest
->viewport
.viewports
, &src
->viewport
.viewports
,
1324 src
->viewport
.count
* sizeof(VkViewport
))) {
1325 typed_memcpy(dest
->viewport
.viewports
, src
->viewport
.viewports
,
1326 src
->viewport
.count
);
1327 dest_mask
|= TU_DYNAMIC_VIEWPORT
;
1331 if (copy_mask
& TU_DYNAMIC_SCISSOR
) {
1332 if (memcmp(&dest
->scissor
.scissors
, &src
->scissor
.scissors
,
1333 src
->scissor
.count
* sizeof(VkRect2D
))) {
1334 typed_memcpy(dest
->scissor
.scissors
, src
->scissor
.scissors
,
1335 src
->scissor
.count
);
1336 dest_mask
|= TU_DYNAMIC_SCISSOR
;
1340 if (copy_mask
& TU_DYNAMIC_LINE_WIDTH
) {
1341 if (dest
->line_width
!= src
->line_width
) {
1342 dest
->line_width
= src
->line_width
;
1343 dest_mask
|= TU_DYNAMIC_LINE_WIDTH
;
1347 if (copy_mask
& TU_DYNAMIC_DEPTH_BIAS
) {
1348 if (memcmp(&dest
->depth_bias
, &src
->depth_bias
,
1349 sizeof(src
->depth_bias
))) {
1350 dest
->depth_bias
= src
->depth_bias
;
1351 dest_mask
|= TU_DYNAMIC_DEPTH_BIAS
;
1355 if (copy_mask
& TU_DYNAMIC_BLEND_CONSTANTS
) {
1356 if (memcmp(&dest
->blend_constants
, &src
->blend_constants
,
1357 sizeof(src
->blend_constants
))) {
1358 typed_memcpy(dest
->blend_constants
, src
->blend_constants
, 4);
1359 dest_mask
|= TU_DYNAMIC_BLEND_CONSTANTS
;
1363 if (copy_mask
& TU_DYNAMIC_DEPTH_BOUNDS
) {
1364 if (memcmp(&dest
->depth_bounds
, &src
->depth_bounds
,
1365 sizeof(src
->depth_bounds
))) {
1366 dest
->depth_bounds
= src
->depth_bounds
;
1367 dest_mask
|= TU_DYNAMIC_DEPTH_BOUNDS
;
1371 if (copy_mask
& TU_DYNAMIC_STENCIL_COMPARE_MASK
) {
1372 if (memcmp(&dest
->stencil_compare_mask
, &src
->stencil_compare_mask
,
1373 sizeof(src
->stencil_compare_mask
))) {
1374 dest
->stencil_compare_mask
= src
->stencil_compare_mask
;
1375 dest_mask
|= TU_DYNAMIC_STENCIL_COMPARE_MASK
;
1379 if (copy_mask
& TU_DYNAMIC_STENCIL_WRITE_MASK
) {
1380 if (memcmp(&dest
->stencil_write_mask
, &src
->stencil_write_mask
,
1381 sizeof(src
->stencil_write_mask
))) {
1382 dest
->stencil_write_mask
= src
->stencil_write_mask
;
1383 dest_mask
|= TU_DYNAMIC_STENCIL_WRITE_MASK
;
1387 if (copy_mask
& TU_DYNAMIC_STENCIL_REFERENCE
) {
1388 if (memcmp(&dest
->stencil_reference
, &src
->stencil_reference
,
1389 sizeof(src
->stencil_reference
))) {
1390 dest
->stencil_reference
= src
->stencil_reference
;
1391 dest_mask
|= TU_DYNAMIC_STENCIL_REFERENCE
;
1395 if (copy_mask
& TU_DYNAMIC_DISCARD_RECTANGLE
) {
1396 if (memcmp(&dest
->discard_rectangle
.rectangles
,
1397 &src
->discard_rectangle
.rectangles
,
1398 src
->discard_rectangle
.count
* sizeof(VkRect2D
))) {
1399 typed_memcpy(dest
->discard_rectangle
.rectangles
,
1400 src
->discard_rectangle
.rectangles
,
1401 src
->discard_rectangle
.count
);
1402 dest_mask
|= TU_DYNAMIC_DISCARD_RECTANGLE
;
1408 tu_create_cmd_buffer(struct tu_device
*device
,
1409 struct tu_cmd_pool
*pool
,
1410 VkCommandBufferLevel level
,
1411 VkCommandBuffer
*pCommandBuffer
)
1413 struct tu_cmd_buffer
*cmd_buffer
;
1414 cmd_buffer
= vk_zalloc(&pool
->alloc
, sizeof(*cmd_buffer
), 8,
1415 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1416 if (cmd_buffer
== NULL
)
1417 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1419 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1420 cmd_buffer
->device
= device
;
1421 cmd_buffer
->pool
= pool
;
1422 cmd_buffer
->level
= level
;
1425 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1426 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
1429 /* Init the pool_link so we can safely call list_del when we destroy
1430 * the command buffer
1432 list_inithead(&cmd_buffer
->pool_link
);
1433 cmd_buffer
->queue_family_index
= TU_QUEUE_GENERAL
;
1436 tu_bo_list_init(&cmd_buffer
->bo_list
);
1437 tu_cs_init(&cmd_buffer
->cs
, TU_CS_MODE_GROW
, 4096);
1438 tu_cs_init(&cmd_buffer
->draw_cs
, TU_CS_MODE_GROW
, 4096);
1439 tu_cs_init(&cmd_buffer
->draw_state
, TU_CS_MODE_SUB_STREAM
, 2048);
1440 tu_cs_init(&cmd_buffer
->tile_cs
, TU_CS_MODE_SUB_STREAM
, 1024);
1442 *pCommandBuffer
= tu_cmd_buffer_to_handle(cmd_buffer
);
1444 list_inithead(&cmd_buffer
->upload
.list
);
1446 cmd_buffer
->marker_reg
= REG_A6XX_CP_SCRATCH_REG(
1447 cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
? 7 : 6);
1449 VkResult result
= tu_bo_init_new(device
, &cmd_buffer
->scratch_bo
, 0x1000);
1450 if (result
!= VK_SUCCESS
)
1457 tu_cmd_buffer_destroy(struct tu_cmd_buffer
*cmd_buffer
)
1459 tu_bo_finish(cmd_buffer
->device
, &cmd_buffer
->scratch_bo
);
1461 list_del(&cmd_buffer
->pool_link
);
1463 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++)
1464 free(cmd_buffer
->descriptors
[i
].push_set
.set
.mapped_ptr
);
1466 tu_cs_finish(cmd_buffer
->device
, &cmd_buffer
->cs
);
1467 tu_cs_finish(cmd_buffer
->device
, &cmd_buffer
->draw_cs
);
1468 tu_cs_finish(cmd_buffer
->device
, &cmd_buffer
->draw_state
);
1469 tu_cs_finish(cmd_buffer
->device
, &cmd_buffer
->tile_cs
);
1471 tu_bo_list_destroy(&cmd_buffer
->bo_list
);
1472 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
);
1476 tu_reset_cmd_buffer(struct tu_cmd_buffer
*cmd_buffer
)
1478 cmd_buffer
->wait_for_idle
= true;
1480 cmd_buffer
->record_result
= VK_SUCCESS
;
1482 tu_bo_list_reset(&cmd_buffer
->bo_list
);
1483 tu_cs_reset(cmd_buffer
->device
, &cmd_buffer
->cs
);
1484 tu_cs_reset(cmd_buffer
->device
, &cmd_buffer
->draw_cs
);
1485 tu_cs_reset(cmd_buffer
->device
, &cmd_buffer
->draw_state
);
1486 tu_cs_reset(cmd_buffer
->device
, &cmd_buffer
->tile_cs
);
1488 for (unsigned i
= 0; i
< VK_PIPELINE_BIND_POINT_RANGE_SIZE
; i
++) {
1489 cmd_buffer
->descriptors
[i
].dirty
= 0;
1490 cmd_buffer
->descriptors
[i
].valid
= 0;
1491 cmd_buffer
->descriptors
[i
].push_dirty
= false;
1494 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_INITIAL
;
1496 return cmd_buffer
->record_result
;
1500 tu_cmd_state_setup_attachments(struct tu_cmd_buffer
*cmd_buffer
,
1501 const VkRenderPassBeginInfo
*info
)
1503 struct tu_cmd_state
*state
= &cmd_buffer
->state
;
1504 const struct tu_framebuffer
*fb
= state
->framebuffer
;
1505 const struct tu_render_pass
*pass
= state
->pass
;
1507 for (uint32_t i
= 0; i
< fb
->attachment_count
; ++i
) {
1508 const struct tu_image_view
*iview
= fb
->attachments
[i
].attachment
;
1509 tu_bo_list_add(&cmd_buffer
->bo_list
, iview
->image
->bo
,
1510 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
1513 if (pass
->attachment_count
== 0) {
1514 state
->attachments
= NULL
;
1518 state
->attachments
=
1519 vk_alloc(&cmd_buffer
->pool
->alloc
,
1520 pass
->attachment_count
* sizeof(state
->attachments
[0]), 8,
1521 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1522 if (state
->attachments
== NULL
) {
1523 cmd_buffer
->record_result
= VK_ERROR_OUT_OF_HOST_MEMORY
;
1524 return cmd_buffer
->record_result
;
1527 for (uint32_t i
= 0; i
< pass
->attachment_count
; ++i
) {
1528 const struct tu_render_pass_attachment
*att
= &pass
->attachments
[i
];
1529 VkImageAspectFlags att_aspects
= vk_format_aspects(att
->format
);
1530 VkImageAspectFlags clear_aspects
= 0;
1532 if (att_aspects
== VK_IMAGE_ASPECT_COLOR_BIT
) {
1533 /* color attachment */
1534 if (att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1535 clear_aspects
|= VK_IMAGE_ASPECT_COLOR_BIT
;
1538 /* depthstencil attachment */
1539 if ((att_aspects
& VK_IMAGE_ASPECT_DEPTH_BIT
) &&
1540 att
->load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1541 clear_aspects
|= VK_IMAGE_ASPECT_DEPTH_BIT
;
1542 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
1543 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_DONT_CARE
)
1544 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1546 if ((att_aspects
& VK_IMAGE_ASPECT_STENCIL_BIT
) &&
1547 att
->stencil_load_op
== VK_ATTACHMENT_LOAD_OP_CLEAR
) {
1548 clear_aspects
|= VK_IMAGE_ASPECT_STENCIL_BIT
;
1552 state
->attachments
[i
].pending_clear_aspects
= clear_aspects
;
1553 state
->attachments
[i
].cleared_views
= 0;
1554 if (clear_aspects
&& info
) {
1555 assert(info
->clearValueCount
> i
);
1556 state
->attachments
[i
].clear_value
= info
->pClearValues
[i
];
1559 state
->attachments
[i
].current_layout
= att
->initial_layout
;
1566 tu_AllocateCommandBuffers(VkDevice _device
,
1567 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
1568 VkCommandBuffer
*pCommandBuffers
)
1570 TU_FROM_HANDLE(tu_device
, device
, _device
);
1571 TU_FROM_HANDLE(tu_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
1573 VkResult result
= VK_SUCCESS
;
1576 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
1578 if (!list_is_empty(&pool
->free_cmd_buffers
)) {
1579 struct tu_cmd_buffer
*cmd_buffer
= list_first_entry(
1580 &pool
->free_cmd_buffers
, struct tu_cmd_buffer
, pool_link
);
1582 list_del(&cmd_buffer
->pool_link
);
1583 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1585 result
= tu_reset_cmd_buffer(cmd_buffer
);
1586 cmd_buffer
->_loader_data
.loaderMagic
= ICD_LOADER_MAGIC
;
1587 cmd_buffer
->level
= pAllocateInfo
->level
;
1589 pCommandBuffers
[i
] = tu_cmd_buffer_to_handle(cmd_buffer
);
1591 result
= tu_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
1592 &pCommandBuffers
[i
]);
1594 if (result
!= VK_SUCCESS
)
1598 if (result
!= VK_SUCCESS
) {
1599 tu_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
, i
,
1602 /* From the Vulkan 1.0.66 spec:
1604 * "vkAllocateCommandBuffers can be used to create multiple
1605 * command buffers. If the creation of any of those command
1606 * buffers fails, the implementation must destroy all
1607 * successfully created command buffer objects from this
1608 * command, set all entries of the pCommandBuffers array to
1609 * NULL and return the error."
1611 memset(pCommandBuffers
, 0,
1612 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
1619 tu_FreeCommandBuffers(VkDevice device
,
1620 VkCommandPool commandPool
,
1621 uint32_t commandBufferCount
,
1622 const VkCommandBuffer
*pCommandBuffers
)
1624 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1625 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
1628 if (cmd_buffer
->pool
) {
1629 list_del(&cmd_buffer
->pool_link
);
1630 list_addtail(&cmd_buffer
->pool_link
,
1631 &cmd_buffer
->pool
->free_cmd_buffers
);
1633 tu_cmd_buffer_destroy(cmd_buffer
);
1639 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer
,
1640 VkCommandBufferResetFlags flags
)
1642 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1643 return tu_reset_cmd_buffer(cmd_buffer
);
1647 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer
,
1648 const VkCommandBufferBeginInfo
*pBeginInfo
)
1650 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1651 VkResult result
= VK_SUCCESS
;
1653 if (cmd_buffer
->status
!= TU_CMD_BUFFER_STATUS_INITIAL
) {
1654 /* If the command buffer has already been resetted with
1655 * vkResetCommandBuffer, no need to do it again.
1657 result
= tu_reset_cmd_buffer(cmd_buffer
);
1658 if (result
!= VK_SUCCESS
)
1662 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
1663 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1665 tu_cs_begin(&cmd_buffer
->cs
);
1667 cmd_buffer
->marker_seqno
= 0;
1668 cmd_buffer
->scratch_seqno
= 0;
1670 /* setup initial configuration into command buffer */
1671 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
1672 switch (cmd_buffer
->queue_family_index
) {
1673 case TU_QUEUE_GENERAL
:
1674 tu6_init_hw(cmd_buffer
, &cmd_buffer
->cs
);
1681 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_RECORDING
;
1687 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer
,
1688 uint32_t firstBinding
,
1689 uint32_t bindingCount
,
1690 const VkBuffer
*pBuffers
,
1691 const VkDeviceSize
*pOffsets
)
1693 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1695 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
1697 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1698 cmd
->state
.vb
.buffers
[firstBinding
+ i
] =
1699 tu_buffer_from_handle(pBuffers
[i
]);
1700 cmd
->state
.vb
.offsets
[firstBinding
+ i
] = pOffsets
[i
];
1703 /* VB states depend on VkPipelineVertexInputStateCreateInfo */
1704 cmd
->state
.dirty
|= TU_CMD_DIRTY_VERTEX_BUFFERS
;
1708 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer
,
1710 VkDeviceSize offset
,
1711 VkIndexType indexType
)
1713 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1714 TU_FROM_HANDLE(tu_buffer
, buf
, buffer
);
1716 /* initialize/update the restart index */
1717 if (!cmd
->state
.index_buffer
|| cmd
->state
.index_type
!= indexType
) {
1718 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
1719 VkResult result
= tu_cs_reserve_space(cmd
->device
, draw_cs
, 2);
1720 if (result
!= VK_SUCCESS
) {
1721 cmd
->record_result
= result
;
1725 tu6_emit_restart_index(
1726 draw_cs
, indexType
== VK_INDEX_TYPE_UINT32
? 0xffffffff : 0xffff);
1728 tu_cs_sanity_check(draw_cs
);
1732 if (cmd
->state
.index_buffer
!= buf
)
1733 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1735 cmd
->state
.index_buffer
= buf
;
1736 cmd
->state
.index_offset
= offset
;
1737 cmd
->state
.index_type
= indexType
;
1741 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer
,
1742 VkPipelineBindPoint pipelineBindPoint
,
1743 VkPipelineLayout _layout
,
1745 uint32_t descriptorSetCount
,
1746 const VkDescriptorSet
*pDescriptorSets
,
1747 uint32_t dynamicOffsetCount
,
1748 const uint32_t *pDynamicOffsets
)
1750 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1751 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, _layout
);
1752 unsigned dyn_idx
= 0;
1754 struct tu_descriptor_state
*descriptors_state
=
1755 tu_get_descriptors_state(cmd_buffer
, pipelineBindPoint
);
1757 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
1758 unsigned idx
= i
+ firstSet
;
1759 TU_FROM_HANDLE(tu_descriptor_set
, set
, pDescriptorSets
[i
]);
1761 descriptors_state
->sets
[idx
] = set
;
1762 descriptors_state
->valid
|= (1u << idx
);
1764 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
1765 unsigned idx
= j
+ layout
->set
[i
+ firstSet
].dynamic_offset_start
;
1766 assert(dyn_idx
< dynamicOffsetCount
);
1768 descriptors_state
->dynamic_buffers
[idx
] =
1769 set
->dynamic_descriptors
[j
].va
+ pDynamicOffsets
[dyn_idx
];
1773 cmd_buffer
->state
.dirty
|= TU_CMD_DIRTY_DESCRIPTOR_SETS
;
1777 tu_CmdPushConstants(VkCommandBuffer commandBuffer
,
1778 VkPipelineLayout layout
,
1779 VkShaderStageFlags stageFlags
,
1782 const void *pValues
)
1784 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1785 memcpy((void*) cmd_buffer
->push_constants
+ offset
, pValues
, size
);
1789 tu_EndCommandBuffer(VkCommandBuffer commandBuffer
)
1791 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1793 if (cmd_buffer
->scratch_seqno
) {
1794 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->scratch_bo
,
1795 MSM_SUBMIT_BO_WRITE
);
1798 for (uint32_t i
= 0; i
< cmd_buffer
->draw_cs
.bo_count
; i
++) {
1799 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_cs
.bos
[i
],
1800 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1803 for (uint32_t i
= 0; i
< cmd_buffer
->draw_state
.bo_count
; i
++) {
1804 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_state
.bos
[i
],
1805 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1808 for (uint32_t i
= 0; i
< cmd_buffer
->tile_cs
.bo_count
; i
++) {
1809 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->tile_cs
.bos
[i
],
1810 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1813 tu_cs_end(&cmd_buffer
->cs
);
1815 assert(!cmd_buffer
->state
.attachments
);
1817 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_EXECUTABLE
;
1819 return cmd_buffer
->record_result
;
1823 tu_CmdBindPipeline(VkCommandBuffer commandBuffer
,
1824 VkPipelineBindPoint pipelineBindPoint
,
1825 VkPipeline _pipeline
)
1827 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1828 TU_FROM_HANDLE(tu_pipeline
, pipeline
, _pipeline
);
1830 switch (pipelineBindPoint
) {
1831 case VK_PIPELINE_BIND_POINT_GRAPHICS
:
1832 cmd
->state
.pipeline
= pipeline
;
1833 cmd
->state
.dirty
|= TU_CMD_DIRTY_PIPELINE
;
1835 case VK_PIPELINE_BIND_POINT_COMPUTE
:
1836 tu_finishme("binding compute pipeline");
1839 unreachable("unrecognized pipeline bind point");
1845 tu_CmdSetViewport(VkCommandBuffer commandBuffer
,
1846 uint32_t firstViewport
,
1847 uint32_t viewportCount
,
1848 const VkViewport
*pViewports
)
1850 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1851 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
1853 VkResult result
= tu_cs_reserve_space(cmd
->device
, draw_cs
, 12);
1854 if (result
!= VK_SUCCESS
) {
1855 cmd
->record_result
= result
;
1859 assert(firstViewport
== 0 && viewportCount
== 1);
1860 tu6_emit_viewport(draw_cs
, pViewports
);
1862 tu_cs_sanity_check(draw_cs
);
1866 tu_CmdSetScissor(VkCommandBuffer commandBuffer
,
1867 uint32_t firstScissor
,
1868 uint32_t scissorCount
,
1869 const VkRect2D
*pScissors
)
1871 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1872 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
1874 VkResult result
= tu_cs_reserve_space(cmd
->device
, draw_cs
, 3);
1875 if (result
!= VK_SUCCESS
) {
1876 cmd
->record_result
= result
;
1880 assert(firstScissor
== 0 && scissorCount
== 1);
1881 tu6_emit_scissor(draw_cs
, pScissors
);
1883 tu_cs_sanity_check(draw_cs
);
1887 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer
, float lineWidth
)
1889 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1891 cmd
->state
.dynamic
.line_width
= lineWidth
;
1893 /* line width depends on VkPipelineRasterizationStateCreateInfo */
1894 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH
;
1898 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer
,
1899 float depthBiasConstantFactor
,
1900 float depthBiasClamp
,
1901 float depthBiasSlopeFactor
)
1903 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1904 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
1906 VkResult result
= tu_cs_reserve_space(cmd
->device
, draw_cs
, 4);
1907 if (result
!= VK_SUCCESS
) {
1908 cmd
->record_result
= result
;
1912 tu6_emit_depth_bias(draw_cs
, depthBiasConstantFactor
, depthBiasClamp
,
1913 depthBiasSlopeFactor
);
1915 tu_cs_sanity_check(draw_cs
);
1919 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer
,
1920 const float blendConstants
[4])
1922 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1923 struct tu_cs
*draw_cs
= &cmd
->draw_cs
;
1925 VkResult result
= tu_cs_reserve_space(cmd
->device
, draw_cs
, 5);
1926 if (result
!= VK_SUCCESS
) {
1927 cmd
->record_result
= result
;
1931 tu6_emit_blend_constants(draw_cs
, blendConstants
);
1933 tu_cs_sanity_check(draw_cs
);
1937 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer
,
1938 float minDepthBounds
,
1939 float maxDepthBounds
)
1944 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer
,
1945 VkStencilFaceFlags faceMask
,
1946 uint32_t compareMask
)
1948 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1950 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
1951 cmd
->state
.dynamic
.stencil_compare_mask
.front
= compareMask
;
1952 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
1953 cmd
->state
.dynamic
.stencil_compare_mask
.back
= compareMask
;
1955 /* the front/back compare masks must be updated together */
1956 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
;
1960 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer
,
1961 VkStencilFaceFlags faceMask
,
1964 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1966 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
1967 cmd
->state
.dynamic
.stencil_write_mask
.front
= writeMask
;
1968 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
1969 cmd
->state
.dynamic
.stencil_write_mask
.back
= writeMask
;
1971 /* the front/back write masks must be updated together */
1972 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
;
1976 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer
,
1977 VkStencilFaceFlags faceMask
,
1980 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1982 if (faceMask
& VK_STENCIL_FACE_FRONT_BIT
)
1983 cmd
->state
.dynamic
.stencil_reference
.front
= reference
;
1984 if (faceMask
& VK_STENCIL_FACE_BACK_BIT
)
1985 cmd
->state
.dynamic
.stencil_reference
.back
= reference
;
1987 /* the front/back references must be updated together */
1988 cmd
->state
.dirty
|= TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
;
1992 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer
,
1993 uint32_t commandBufferCount
,
1994 const VkCommandBuffer
*pCmdBuffers
)
1999 tu_CreateCommandPool(VkDevice _device
,
2000 const VkCommandPoolCreateInfo
*pCreateInfo
,
2001 const VkAllocationCallbacks
*pAllocator
,
2002 VkCommandPool
*pCmdPool
)
2004 TU_FROM_HANDLE(tu_device
, device
, _device
);
2005 struct tu_cmd_pool
*pool
;
2007 pool
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*pool
), 8,
2008 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
2010 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2013 pool
->alloc
= *pAllocator
;
2015 pool
->alloc
= device
->alloc
;
2017 list_inithead(&pool
->cmd_buffers
);
2018 list_inithead(&pool
->free_cmd_buffers
);
2020 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
2022 *pCmdPool
= tu_cmd_pool_to_handle(pool
);
2028 tu_DestroyCommandPool(VkDevice _device
,
2029 VkCommandPool commandPool
,
2030 const VkAllocationCallbacks
*pAllocator
)
2032 TU_FROM_HANDLE(tu_device
, device
, _device
);
2033 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2038 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2039 &pool
->cmd_buffers
, pool_link
)
2041 tu_cmd_buffer_destroy(cmd_buffer
);
2044 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2045 &pool
->free_cmd_buffers
, pool_link
)
2047 tu_cmd_buffer_destroy(cmd_buffer
);
2050 vk_free2(&device
->alloc
, pAllocator
, pool
);
2054 tu_ResetCommandPool(VkDevice device
,
2055 VkCommandPool commandPool
,
2056 VkCommandPoolResetFlags flags
)
2058 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2061 list_for_each_entry(struct tu_cmd_buffer
, cmd_buffer
, &pool
->cmd_buffers
,
2064 result
= tu_reset_cmd_buffer(cmd_buffer
);
2065 if (result
!= VK_SUCCESS
)
2073 tu_TrimCommandPool(VkDevice device
,
2074 VkCommandPool commandPool
,
2075 VkCommandPoolTrimFlags flags
)
2077 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2082 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2083 &pool
->free_cmd_buffers
, pool_link
)
2085 tu_cmd_buffer_destroy(cmd_buffer
);
2090 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer
,
2091 const VkRenderPassBeginInfo
*pRenderPassBegin
,
2092 VkSubpassContents contents
)
2094 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
2095 TU_FROM_HANDLE(tu_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2096 TU_FROM_HANDLE(tu_framebuffer
, framebuffer
, pRenderPassBegin
->framebuffer
);
2099 cmd_buffer
->state
.pass
= pass
;
2100 cmd_buffer
->state
.subpass
= pass
->subpasses
;
2101 cmd_buffer
->state
.framebuffer
= framebuffer
;
2103 result
= tu_cmd_state_setup_attachments(cmd_buffer
, pRenderPassBegin
);
2104 if (result
!= VK_SUCCESS
)
2107 tu_cmd_update_tiling_config(cmd_buffer
, &pRenderPassBegin
->renderArea
);
2108 tu_cmd_prepare_tile_load_ib(cmd_buffer
);
2109 tu_cmd_prepare_tile_store_ib(cmd_buffer
);
2111 /* draw_cs should contain entries only for this render pass */
2112 assert(!cmd_buffer
->draw_cs
.entry_count
);
2113 tu_cs_begin(&cmd_buffer
->draw_cs
);
2117 tu_CmdBeginRenderPass2KHR(VkCommandBuffer commandBuffer
,
2118 const VkRenderPassBeginInfo
*pRenderPassBeginInfo
,
2119 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
)
2121 tu_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
2122 pSubpassBeginInfo
->contents
);
2126 tu_CmdNextSubpass(VkCommandBuffer commandBuffer
, VkSubpassContents contents
)
2128 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2130 tu_cmd_render_tiles(cmd
);
2132 cmd
->state
.subpass
++;
2134 tu_cmd_update_tiling_config(cmd
, NULL
);
2135 tu_cmd_prepare_tile_load_ib(cmd
);
2136 tu_cmd_prepare_tile_store_ib(cmd
);
2140 tu_CmdNextSubpass2KHR(VkCommandBuffer commandBuffer
,
2141 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
,
2142 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
2144 tu_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
2150 * Number of vertices.
2155 * Index of the first vertex.
2157 int32_t vertex_offset
;
2160 * First instance id.
2162 uint32_t first_instance
;
2165 * Number of instances.
2167 uint32_t instance_count
;
2170 * First index (indexed draws only).
2172 uint32_t first_index
;
2175 * Whether it's an indexed draw.
2180 * Indirect draw parameters resource.
2182 struct tu_buffer
*indirect
;
2183 uint64_t indirect_offset
;
2187 * Draw count parameters resource.
2189 struct tu_buffer
*count_buffer
;
2190 uint64_t count_buffer_offset
;
2193 enum tu_draw_state_group_id
2195 TU_DRAW_STATE_PROGRAM
,
2196 TU_DRAW_STATE_PROGRAM_BINNING
,
2198 TU_DRAW_STATE_VI_BINNING
,
2202 TU_DRAW_STATE_BLEND
,
2203 TU_DRAW_STATE_VS_CONST
,
2204 TU_DRAW_STATE_FS_CONST
,
2205 TU_DRAW_STATE_VS_TEX
,
2206 TU_DRAW_STATE_FS_TEX
,
2208 TU_DRAW_STATE_COUNT
,
2211 struct tu_draw_state_group
2213 enum tu_draw_state_group_id id
;
2214 uint32_t enable_mask
;
2215 struct tu_cs_entry ib
;
2218 static struct tu_sampler
*
2219 sampler_ptr(struct tu_descriptor_state
*descriptors_state
,
2220 const struct tu_descriptor_map
*map
, unsigned i
)
2222 assert(descriptors_state
->valid
& (1 << map
->set
[i
]));
2224 struct tu_descriptor_set
*set
= descriptors_state
->sets
[map
->set
[i
]];
2225 assert(map
->binding
[i
] < set
->layout
->binding_count
);
2227 const struct tu_descriptor_set_binding_layout
*layout
=
2228 &set
->layout
->binding
[map
->binding
[i
]];
2230 switch (layout
->type
) {
2231 case VK_DESCRIPTOR_TYPE_SAMPLER
:
2232 return (struct tu_sampler
*) &set
->mapped_ptr
[layout
->offset
/ 4];
2233 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2234 return (struct tu_sampler
*) &set
->mapped_ptr
[layout
->offset
/ 4 + A6XX_TEX_CONST_DWORDS
];
2236 unreachable("unimplemented descriptor type");
2242 texture_ptr(struct tu_descriptor_state
*descriptors_state
,
2243 const struct tu_descriptor_map
*map
, unsigned i
)
2245 assert(descriptors_state
->valid
& (1 << map
->set
[i
]));
2247 struct tu_descriptor_set
*set
= descriptors_state
->sets
[map
->set
[i
]];
2248 assert(map
->binding
[i
] < set
->layout
->binding_count
);
2250 const struct tu_descriptor_set_binding_layout
*layout
=
2251 &set
->layout
->binding
[map
->binding
[i
]];
2253 switch (layout
->type
) {
2254 case VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
:
2255 case VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
:
2256 return &set
->mapped_ptr
[layout
->offset
/ 4];
2257 case VK_DESCRIPTOR_TYPE_UNIFORM_TEXEL_BUFFER
:
2258 case VK_DESCRIPTOR_TYPE_STORAGE_TEXEL_BUFFER
:
2259 return &set
->mapped_ptr
[layout
->offset
/ 4];
2261 unreachable("unimplemented descriptor type");
2267 buffer_ptr(struct tu_descriptor_state
*descriptors_state
,
2268 const struct tu_descriptor_map
*map
,
2271 assert(descriptors_state
->valid
& (1 << map
->set
[i
]));
2273 struct tu_descriptor_set
*set
= descriptors_state
->sets
[map
->set
[i
]];
2274 assert(map
->binding
[i
] < set
->layout
->binding_count
);
2276 const struct tu_descriptor_set_binding_layout
*layout
=
2277 &set
->layout
->binding
[map
->binding
[i
]];
2279 switch (layout
->type
) {
2280 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
:
2281 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
:
2282 return descriptors_state
->dynamic_buffers
[layout
->dynamic_offset_offset
];
2283 case VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER
:
2284 case VK_DESCRIPTOR_TYPE_STORAGE_BUFFER
:
2285 return (uint64_t) set
->mapped_ptr
[layout
->offset
/ 4 + 1] << 32 |
2286 set
->mapped_ptr
[layout
->offset
/ 4];
2288 unreachable("unimplemented descriptor type");
2293 static inline uint32_t
2294 tu6_stage2opcode(gl_shader_stage type
)
2297 case MESA_SHADER_VERTEX
:
2298 case MESA_SHADER_TESS_CTRL
:
2299 case MESA_SHADER_TESS_EVAL
:
2300 case MESA_SHADER_GEOMETRY
:
2301 return CP_LOAD_STATE6_GEOM
;
2302 case MESA_SHADER_FRAGMENT
:
2303 case MESA_SHADER_COMPUTE
:
2304 case MESA_SHADER_KERNEL
:
2305 return CP_LOAD_STATE6_FRAG
;
2307 unreachable("bad shader type");
2311 static inline enum a6xx_state_block
2312 tu6_stage2shadersb(gl_shader_stage type
)
2315 case MESA_SHADER_VERTEX
:
2316 return SB6_VS_SHADER
;
2317 case MESA_SHADER_FRAGMENT
:
2318 return SB6_FS_SHADER
;
2319 case MESA_SHADER_COMPUTE
:
2320 case MESA_SHADER_KERNEL
:
2321 return SB6_CS_SHADER
;
2323 unreachable("bad shader type");
2329 tu6_emit_user_consts(struct tu_cs
*cs
, const struct tu_pipeline
*pipeline
,
2330 struct tu_descriptor_state
*descriptors_state
,
2331 gl_shader_stage type
,
2332 uint32_t *push_constants
)
2334 const struct tu_program_descriptor_linkage
*link
=
2335 &pipeline
->program
.link
[type
];
2336 const struct ir3_ubo_analysis_state
*state
= &link
->ubo_state
;
2338 for (uint32_t i
= 0; i
< ARRAY_SIZE(state
->range
); i
++) {
2339 if (state
->range
[i
].start
< state
->range
[i
].end
) {
2340 uint32_t size
= state
->range
[i
].end
- state
->range
[i
].start
;
2341 uint32_t offset
= state
->range
[i
].start
;
2343 /* and even if the start of the const buffer is before
2344 * first_immediate, the end may not be:
2346 size
= MIN2(size
, (16 * link
->constlen
) - state
->range
[i
].offset
);
2351 /* things should be aligned to vec4: */
2352 debug_assert((state
->range
[i
].offset
% 16) == 0);
2353 debug_assert((size
% 16) == 0);
2354 debug_assert((offset
% 16) == 0);
2357 /* push constants */
2358 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + (size
/ 4));
2359 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(state
->range
[i
].offset
/ 16) |
2360 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2361 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2362 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2363 CP_LOAD_STATE6_0_NUM_UNIT(size
/ 16));
2366 for (unsigned i
= 0; i
< size
/ 4; i
++)
2367 tu_cs_emit(cs
, push_constants
[i
+ offset
/ 4]);
2371 uint64_t va
= buffer_ptr(descriptors_state
, &link
->ubo_map
, i
- 1);
2373 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3);
2374 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(state
->range
[i
].offset
/ 16) |
2375 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2376 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
2377 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2378 CP_LOAD_STATE6_0_NUM_UNIT(size
/ 16));
2379 tu_cs_emit_qw(cs
, va
+ offset
);
2385 tu6_emit_ubos(struct tu_cs
*cs
, const struct tu_pipeline
*pipeline
,
2386 struct tu_descriptor_state
*descriptors_state
,
2387 gl_shader_stage type
)
2389 const struct tu_program_descriptor_linkage
*link
=
2390 &pipeline
->program
.link
[type
];
2392 uint32_t num
= MIN2(link
->ubo_map
.num
, link
->const_state
.num_ubos
);
2393 uint32_t anum
= align(num
, 2);
2399 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + (2 * anum
));
2400 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(link
->const_state
.offsets
.ubo
) |
2401 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2402 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2403 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2404 CP_LOAD_STATE6_0_NUM_UNIT(anum
/2));
2405 tu_cs_emit(cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2406 tu_cs_emit(cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2408 for (i
= 0; i
< num
; i
++)
2409 tu_cs_emit_qw(cs
, buffer_ptr(descriptors_state
, &link
->ubo_map
, i
));
2411 for (; i
< anum
; i
++) {
2412 tu_cs_emit(cs
, 0xffffffff);
2413 tu_cs_emit(cs
, 0xffffffff);
2417 static struct tu_cs_entry
2418 tu6_emit_consts(struct tu_cmd_buffer
*cmd
,
2419 const struct tu_pipeline
*pipeline
,
2420 struct tu_descriptor_state
*descriptors_state
,
2421 gl_shader_stage type
)
2424 tu_cs_begin_sub_stream(cmd
->device
, &cmd
->draw_state
, 512, &cs
); /* TODO: maximum size? */
2426 tu6_emit_user_consts(&cs
, pipeline
, descriptors_state
, type
, cmd
->push_constants
);
2427 tu6_emit_ubos(&cs
, pipeline
, descriptors_state
, type
);
2429 return tu_cs_end_sub_stream(&cmd
->draw_state
, &cs
);
2432 static struct tu_cs_entry
2433 tu6_emit_textures(struct tu_device
*device
, struct tu_cs
*draw_state
,
2434 const struct tu_pipeline
*pipeline
,
2435 struct tu_descriptor_state
*descriptors_state
,
2436 gl_shader_stage type
, bool *needs_border
)
2438 const struct tu_program_descriptor_linkage
*link
=
2439 &pipeline
->program
.link
[type
];
2441 uint32_t size
= link
->texture_map
.num
* A6XX_TEX_CONST_DWORDS
+
2442 link
->sampler_map
.num
* A6XX_TEX_SAMP_DWORDS
;
2444 return (struct tu_cs_entry
) {};
2446 unsigned opcode
, tex_samp_reg
, tex_const_reg
, tex_count_reg
;
2447 enum a6xx_state_block sb
;
2450 case MESA_SHADER_VERTEX
:
2452 opcode
= CP_LOAD_STATE6_GEOM
;
2453 tex_samp_reg
= REG_A6XX_SP_VS_TEX_SAMP_LO
;
2454 tex_const_reg
= REG_A6XX_SP_VS_TEX_CONST_LO
;
2455 tex_count_reg
= REG_A6XX_SP_VS_TEX_COUNT
;
2457 case MESA_SHADER_FRAGMENT
:
2459 opcode
= CP_LOAD_STATE6_FRAG
;
2460 tex_samp_reg
= REG_A6XX_SP_FS_TEX_SAMP_LO
;
2461 tex_const_reg
= REG_A6XX_SP_FS_TEX_CONST_LO
;
2462 tex_count_reg
= REG_A6XX_SP_FS_TEX_COUNT
;
2464 case MESA_SHADER_COMPUTE
:
2466 opcode
= CP_LOAD_STATE6_FRAG
;
2467 tex_samp_reg
= REG_A6XX_SP_CS_TEX_SAMP_LO
;
2468 tex_const_reg
= REG_A6XX_SP_CS_TEX_CONST_LO
;
2469 tex_count_reg
= REG_A6XX_SP_CS_TEX_COUNT
;
2472 unreachable("bad state block");
2476 tu_cs_begin_sub_stream(device
, draw_state
, size
, &cs
);
2478 for (unsigned i
= 0; i
< link
->texture_map
.num
; i
++) {
2479 uint32_t *ptr
= texture_ptr(descriptors_state
, &link
->texture_map
, i
);
2481 for (unsigned j
= 0; j
< A6XX_TEX_CONST_DWORDS
; j
++)
2482 tu_cs_emit(&cs
, ptr
[j
]);
2485 for (unsigned i
= 0; i
< link
->sampler_map
.num
; i
++) {
2486 struct tu_sampler
*sampler
= sampler_ptr(descriptors_state
, &link
->sampler_map
, i
);
2488 for (unsigned j
= 0; j
< A6XX_TEX_SAMP_DWORDS
; j
++)
2489 tu_cs_emit(&cs
, sampler
->state
[j
]);
2491 *needs_border
|= sampler
->needs_border
;
2494 struct tu_cs_entry entry
= tu_cs_end_sub_stream(draw_state
, &cs
);
2496 uint64_t tex_addr
= entry
.bo
->iova
+ entry
.offset
;
2497 uint64_t samp_addr
= tex_addr
+ link
->texture_map
.num
* A6XX_TEX_CONST_DWORDS
*4;
2499 tu_cs_begin_sub_stream(device
, draw_state
, 64, &cs
);
2501 /* output sampler state: */
2502 tu_cs_emit_pkt7(&cs
, opcode
, 3);
2503 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
2504 CP_LOAD_STATE6_0_STATE_TYPE(ST6_SHADER
) |
2505 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
2506 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
2507 CP_LOAD_STATE6_0_NUM_UNIT(link
->sampler_map
.num
));
2508 tu_cs_emit_qw(&cs
, samp_addr
); /* SRC_ADDR_LO/HI */
2510 tu_cs_emit_pkt4(&cs
, tex_samp_reg
, 2);
2511 tu_cs_emit_qw(&cs
, samp_addr
); /* SRC_ADDR_LO/HI */
2513 /* emit texture state: */
2514 tu_cs_emit_pkt7(&cs
, opcode
, 3);
2515 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
2516 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2517 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
2518 CP_LOAD_STATE6_0_STATE_BLOCK(sb
) |
2519 CP_LOAD_STATE6_0_NUM_UNIT(link
->texture_map
.num
));
2520 tu_cs_emit_qw(&cs
, tex_addr
); /* SRC_ADDR_LO/HI */
2522 tu_cs_emit_pkt4(&cs
, tex_const_reg
, 2);
2523 tu_cs_emit_qw(&cs
, tex_addr
); /* SRC_ADDR_LO/HI */
2525 tu_cs_emit_pkt4(&cs
, tex_count_reg
, 1);
2526 tu_cs_emit(&cs
, link
->texture_map
.num
);
2528 return tu_cs_end_sub_stream(draw_state
, &cs
);
2532 tu6_emit_border_color(struct tu_cmd_buffer
*cmd
,
2535 const struct tu_pipeline
*pipeline
= cmd
->state
.pipeline
;
2537 #define A6XX_BORDER_COLOR_DWORDS (128/4)
2538 uint32_t size
= A6XX_BORDER_COLOR_DWORDS
*
2539 (pipeline
->program
.link
[MESA_SHADER_VERTEX
].sampler_map
.num
+
2540 pipeline
->program
.link
[MESA_SHADER_FRAGMENT
].sampler_map
.num
) +
2541 A6XX_BORDER_COLOR_DWORDS
- 1; /* room for alignment */
2543 struct tu_cs border_cs
;
2544 tu_cs_begin_sub_stream(cmd
->device
, &cmd
->draw_state
, size
, &border_cs
);
2546 /* TODO: actually fill with border color */
2547 for (unsigned i
= 0; i
< size
; i
++)
2548 tu_cs_emit(&border_cs
, 0);
2550 struct tu_cs_entry entry
= tu_cs_end_sub_stream(&cmd
->draw_state
, &border_cs
);
2552 tu_cs_emit_pkt4(cs
, REG_A6XX_SP_TP_BORDER_COLOR_BASE_ADDR_LO
, 2);
2553 tu_cs_emit_qw(cs
, align(entry
.bo
->iova
+ entry
.offset
, 128));
2557 tu6_bind_draw_states(struct tu_cmd_buffer
*cmd
,
2559 const struct tu_draw_info
*draw
)
2561 const struct tu_pipeline
*pipeline
= cmd
->state
.pipeline
;
2562 const struct tu_dynamic_state
*dynamic
= &cmd
->state
.dynamic
;
2563 struct tu_draw_state_group draw_state_groups
[TU_DRAW_STATE_COUNT
];
2564 uint32_t draw_state_group_count
= 0;
2566 struct tu_descriptor_state
*descriptors_state
=
2567 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_GRAPHICS
];
2569 VkResult result
= tu_cs_reserve_space(cmd
->device
, cs
, 256);
2570 if (result
!= VK_SUCCESS
) {
2571 cmd
->record_result
= result
;
2577 uint32_t pc_primitive_cntl
= 0;
2578 if (pipeline
->ia
.primitive_restart
&& draw
->indexed
)
2579 pc_primitive_cntl
|= A6XX_PC_PRIMITIVE_CNTL_0_PRIMITIVE_RESTART
;
2581 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9806
, 0);
2582 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9990
, 0);
2583 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_UNKNOWN_A008
, 0);
2585 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_0
, 1);
2586 tu_cs_emit(cs
, pc_primitive_cntl
);
2588 if (cmd
->state
.dirty
&
2589 (TU_CMD_DIRTY_PIPELINE
| TU_CMD_DIRTY_DYNAMIC_LINE_WIDTH
) &&
2590 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_LINE_WIDTH
)) {
2591 tu6_emit_gras_su_cntl(cs
, pipeline
->rast
.gras_su_cntl
,
2592 dynamic
->line_width
);
2595 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_STENCIL_COMPARE_MASK
) &&
2596 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_COMPARE_MASK
)) {
2597 tu6_emit_stencil_compare_mask(cs
, dynamic
->stencil_compare_mask
.front
,
2598 dynamic
->stencil_compare_mask
.back
);
2601 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_STENCIL_WRITE_MASK
) &&
2602 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_WRITE_MASK
)) {
2603 tu6_emit_stencil_write_mask(cs
, dynamic
->stencil_write_mask
.front
,
2604 dynamic
->stencil_write_mask
.back
);
2607 if ((cmd
->state
.dirty
& TU_CMD_DIRTY_DYNAMIC_STENCIL_REFERENCE
) &&
2608 (pipeline
->dynamic_state
.mask
& TU_DYNAMIC_STENCIL_REFERENCE
)) {
2609 tu6_emit_stencil_reference(cs
, dynamic
->stencil_reference
.front
,
2610 dynamic
->stencil_reference
.back
);
2613 if (cmd
->state
.dirty
&
2614 (TU_CMD_DIRTY_PIPELINE
| TU_CMD_DIRTY_VERTEX_BUFFERS
)) {
2615 for (uint32_t i
= 0; i
< pipeline
->vi
.count
; i
++) {
2616 const uint32_t binding
= pipeline
->vi
.bindings
[i
];
2617 const uint32_t stride
= pipeline
->vi
.strides
[i
];
2618 const struct tu_buffer
*buf
= cmd
->state
.vb
.buffers
[binding
];
2619 const VkDeviceSize offset
= buf
->bo_offset
+
2620 cmd
->state
.vb
.offsets
[binding
] +
2621 pipeline
->vi
.offsets
[i
];
2622 const VkDeviceSize size
=
2623 offset
< buf
->bo
->size
? buf
->bo
->size
- offset
: 0;
2625 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_FETCH(i
), 4);
2626 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ offset
);
2627 tu_cs_emit(cs
, size
);
2628 tu_cs_emit(cs
, stride
);
2632 if (cmd
->state
.dirty
& TU_CMD_DIRTY_PIPELINE
) {
2633 draw_state_groups
[draw_state_group_count
++] =
2634 (struct tu_draw_state_group
) {
2635 .id
= TU_DRAW_STATE_PROGRAM
,
2637 .ib
= pipeline
->program
.state_ib
,
2639 draw_state_groups
[draw_state_group_count
++] =
2640 (struct tu_draw_state_group
) {
2641 .id
= TU_DRAW_STATE_PROGRAM_BINNING
,
2643 .ib
= pipeline
->program
.binning_state_ib
,
2645 draw_state_groups
[draw_state_group_count
++] =
2646 (struct tu_draw_state_group
) {
2647 .id
= TU_DRAW_STATE_VI
,
2649 .ib
= pipeline
->vi
.state_ib
,
2651 draw_state_groups
[draw_state_group_count
++] =
2652 (struct tu_draw_state_group
) {
2653 .id
= TU_DRAW_STATE_VI_BINNING
,
2655 .ib
= pipeline
->vi
.binning_state_ib
,
2657 draw_state_groups
[draw_state_group_count
++] =
2658 (struct tu_draw_state_group
) {
2659 .id
= TU_DRAW_STATE_VP
,
2661 .ib
= pipeline
->vp
.state_ib
,
2663 draw_state_groups
[draw_state_group_count
++] =
2664 (struct tu_draw_state_group
) {
2665 .id
= TU_DRAW_STATE_RAST
,
2667 .ib
= pipeline
->rast
.state_ib
,
2669 draw_state_groups
[draw_state_group_count
++] =
2670 (struct tu_draw_state_group
) {
2671 .id
= TU_DRAW_STATE_DS
,
2673 .ib
= pipeline
->ds
.state_ib
,
2675 draw_state_groups
[draw_state_group_count
++] =
2676 (struct tu_draw_state_group
) {
2677 .id
= TU_DRAW_STATE_BLEND
,
2679 .ib
= pipeline
->blend
.state_ib
,
2683 if (cmd
->state
.dirty
&
2684 (TU_CMD_DIRTY_PIPELINE
| TU_CMD_DIRTY_DESCRIPTOR_SETS
)) {
2685 bool needs_border
= false;
2687 draw_state_groups
[draw_state_group_count
++] =
2688 (struct tu_draw_state_group
) {
2689 .id
= TU_DRAW_STATE_VS_CONST
,
2691 .ib
= tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_VERTEX
)
2693 draw_state_groups
[draw_state_group_count
++] =
2694 (struct tu_draw_state_group
) {
2695 .id
= TU_DRAW_STATE_FS_CONST
,
2697 .ib
= tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_FRAGMENT
)
2699 draw_state_groups
[draw_state_group_count
++] =
2700 (struct tu_draw_state_group
) {
2701 .id
= TU_DRAW_STATE_VS_TEX
,
2703 .ib
= tu6_emit_textures(cmd
->device
, &cmd
->draw_state
, pipeline
,
2704 descriptors_state
, MESA_SHADER_VERTEX
,
2707 draw_state_groups
[draw_state_group_count
++] =
2708 (struct tu_draw_state_group
) {
2709 .id
= TU_DRAW_STATE_FS_TEX
,
2711 .ib
= tu6_emit_textures(cmd
->device
, &cmd
->draw_state
, pipeline
,
2712 descriptors_state
, MESA_SHADER_FRAGMENT
,
2717 tu6_emit_border_color(cmd
, cs
);
2720 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * draw_state_group_count
);
2721 for (uint32_t i
= 0; i
< draw_state_group_count
; i
++) {
2722 const struct tu_draw_state_group
*group
= &draw_state_groups
[i
];
2724 uint32_t cp_set_draw_state
=
2725 CP_SET_DRAW_STATE__0_COUNT(group
->ib
.size
/ 4) |
2726 CP_SET_DRAW_STATE__0_ENABLE_MASK(group
->enable_mask
) |
2727 CP_SET_DRAW_STATE__0_GROUP_ID(group
->id
);
2729 if (group
->ib
.size
) {
2730 iova
= group
->ib
.bo
->iova
+ group
->ib
.offset
;
2732 cp_set_draw_state
|= CP_SET_DRAW_STATE__0_DISABLE
;
2736 tu_cs_emit(cs
, cp_set_draw_state
);
2737 tu_cs_emit_qw(cs
, iova
);
2740 tu_cs_sanity_check(cs
);
2743 if (cmd
->state
.dirty
& TU_CMD_DIRTY_PIPELINE
) {
2744 tu_bo_list_add(&cmd
->bo_list
, &pipeline
->program
.binary_bo
,
2745 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2746 for (uint32_t i
= 0; i
< pipeline
->cs
.bo_count
; i
++) {
2747 tu_bo_list_add(&cmd
->bo_list
, pipeline
->cs
.bos
[i
],
2748 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2751 if (cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
) {
2752 for (uint32_t i
= 0; i
< MAX_VBS
; i
++) {
2753 const struct tu_buffer
*buf
= cmd
->state
.vb
.buffers
[i
];
2755 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
2758 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DESCRIPTOR_SETS
) {
2760 for_each_bit(i
, descriptors_state
->valid
) {
2761 struct tu_descriptor_set
*set
= descriptors_state
->sets
[i
];
2762 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
)
2763 if (set
->descriptors
[j
]) {
2764 tu_bo_list_add(&cmd
->bo_list
, set
->descriptors
[j
],
2765 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2769 cmd
->state
.dirty
= 0;
2773 tu6_emit_draw_direct(struct tu_cmd_buffer
*cmd
,
2775 const struct tu_draw_info
*draw
)
2778 const enum pc_di_primtype primtype
= cmd
->state
.pipeline
->ia
.primtype
;
2780 tu_cs_emit_pkt4(cs
, REG_A6XX_VFD_INDEX_OFFSET
, 2);
2781 tu_cs_emit(cs
, draw
->vertex_offset
);
2782 tu_cs_emit(cs
, draw
->first_instance
);
2784 /* TODO hw binning */
2785 if (draw
->indexed
) {
2786 const enum a4xx_index_size index_size
=
2787 tu6_index_size(cmd
->state
.index_type
);
2788 const uint32_t index_bytes
=
2789 (cmd
->state
.index_type
== VK_INDEX_TYPE_UINT32
) ? 4 : 2;
2790 const struct tu_buffer
*buf
= cmd
->state
.index_buffer
;
2791 const VkDeviceSize offset
= buf
->bo_offset
+ cmd
->state
.index_offset
+
2792 index_bytes
* draw
->first_index
;
2793 const uint32_t size
= index_bytes
* draw
->count
;
2795 const uint32_t cp_draw_indx
=
2796 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
2797 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_DMA
) |
2798 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(index_size
) |
2799 CP_DRAW_INDX_OFFSET_0_VIS_CULL(IGNORE_VISIBILITY
) | 0x2000;
2801 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 7);
2802 tu_cs_emit(cs
, cp_draw_indx
);
2803 tu_cs_emit(cs
, draw
->instance_count
);
2804 tu_cs_emit(cs
, draw
->count
);
2805 tu_cs_emit(cs
, 0x0); /* XXX */
2806 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ offset
);
2807 tu_cs_emit(cs
, size
);
2809 const uint32_t cp_draw_indx
=
2810 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(primtype
) |
2811 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(DI_SRC_SEL_AUTO_INDEX
) |
2812 CP_DRAW_INDX_OFFSET_0_VIS_CULL(IGNORE_VISIBILITY
) | 0x2000;
2814 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 3);
2815 tu_cs_emit(cs
, cp_draw_indx
);
2816 tu_cs_emit(cs
, draw
->instance_count
);
2817 tu_cs_emit(cs
, draw
->count
);
2822 tu_draw(struct tu_cmd_buffer
*cmd
, const struct tu_draw_info
*draw
)
2824 struct tu_cs
*cs
= &cmd
->draw_cs
;
2826 tu6_bind_draw_states(cmd
, cs
, draw
);
2828 VkResult result
= tu_cs_reserve_space(cmd
->device
, cs
, 32);
2829 if (result
!= VK_SUCCESS
) {
2830 cmd
->record_result
= result
;
2834 if (draw
->indirect
) {
2835 tu_finishme("indirect draw");
2839 /* TODO tu6_emit_marker should pick different regs depending on cs */
2840 tu6_emit_marker(cmd
, cs
);
2841 tu6_emit_draw_direct(cmd
, cs
, draw
);
2842 tu6_emit_marker(cmd
, cs
);
2844 cmd
->wait_for_idle
= true;
2846 tu_cs_sanity_check(cs
);
2850 tu_CmdDraw(VkCommandBuffer commandBuffer
,
2851 uint32_t vertexCount
,
2852 uint32_t instanceCount
,
2853 uint32_t firstVertex
,
2854 uint32_t firstInstance
)
2856 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
2857 struct tu_draw_info info
= {};
2859 info
.count
= vertexCount
;
2860 info
.instance_count
= instanceCount
;
2861 info
.first_instance
= firstInstance
;
2862 info
.vertex_offset
= firstVertex
;
2864 tu_draw(cmd_buffer
, &info
);
2868 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer
,
2869 uint32_t indexCount
,
2870 uint32_t instanceCount
,
2871 uint32_t firstIndex
,
2872 int32_t vertexOffset
,
2873 uint32_t firstInstance
)
2875 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
2876 struct tu_draw_info info
= {};
2878 info
.indexed
= true;
2879 info
.count
= indexCount
;
2880 info
.instance_count
= instanceCount
;
2881 info
.first_index
= firstIndex
;
2882 info
.vertex_offset
= vertexOffset
;
2883 info
.first_instance
= firstInstance
;
2885 tu_draw(cmd_buffer
, &info
);
2889 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer
,
2891 VkDeviceSize offset
,
2895 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
2896 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
2897 struct tu_draw_info info
= {};
2899 info
.count
= drawCount
;
2900 info
.indirect
= buffer
;
2901 info
.indirect_offset
= offset
;
2902 info
.stride
= stride
;
2904 tu_draw(cmd_buffer
, &info
);
2908 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer
,
2910 VkDeviceSize offset
,
2914 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
2915 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
2916 struct tu_draw_info info
= {};
2918 info
.indexed
= true;
2919 info
.count
= drawCount
;
2920 info
.indirect
= buffer
;
2921 info
.indirect_offset
= offset
;
2922 info
.stride
= stride
;
2924 tu_draw(cmd_buffer
, &info
);
2927 struct tu_dispatch_info
2930 * Determine the layout of the grid (in block units) to be used.
2935 * A starting offset for the grid. If unaligned is set, the offset
2936 * must still be aligned.
2938 uint32_t offsets
[3];
2940 * Whether it's an unaligned compute dispatch.
2945 * Indirect compute parameters resource.
2947 struct tu_buffer
*indirect
;
2948 uint64_t indirect_offset
;
2952 tu_dispatch(struct tu_cmd_buffer
*cmd_buffer
,
2953 const struct tu_dispatch_info
*info
)
2958 tu_CmdDispatchBase(VkCommandBuffer commandBuffer
,
2966 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
2967 struct tu_dispatch_info info
= {};
2973 info
.offsets
[0] = base_x
;
2974 info
.offsets
[1] = base_y
;
2975 info
.offsets
[2] = base_z
;
2976 tu_dispatch(cmd_buffer
, &info
);
2980 tu_CmdDispatch(VkCommandBuffer commandBuffer
,
2985 tu_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
2989 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer
,
2991 VkDeviceSize offset
)
2993 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
2994 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
2995 struct tu_dispatch_info info
= {};
2997 info
.indirect
= buffer
;
2998 info
.indirect_offset
= offset
;
3000 tu_dispatch(cmd_buffer
, &info
);
3004 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer
)
3006 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3008 tu_cs_end(&cmd_buffer
->draw_cs
);
3010 tu_cmd_render_tiles(cmd_buffer
);
3012 /* discard draw_cs entries now that the tiles are rendered */
3013 tu_cs_discard_entries(&cmd_buffer
->draw_cs
);
3015 vk_free(&cmd_buffer
->pool
->alloc
, cmd_buffer
->state
.attachments
);
3016 cmd_buffer
->state
.attachments
= NULL
;
3018 cmd_buffer
->state
.pass
= NULL
;
3019 cmd_buffer
->state
.subpass
= NULL
;
3020 cmd_buffer
->state
.framebuffer
= NULL
;
3024 tu_CmdEndRenderPass2KHR(VkCommandBuffer commandBuffer
,
3025 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
3027 tu_CmdEndRenderPass(commandBuffer
);
3030 struct tu_barrier_info
3032 uint32_t eventCount
;
3033 const VkEvent
*pEvents
;
3034 VkPipelineStageFlags srcStageMask
;
3038 tu_barrier(struct tu_cmd_buffer
*cmd_buffer
,
3039 uint32_t memoryBarrierCount
,
3040 const VkMemoryBarrier
*pMemoryBarriers
,
3041 uint32_t bufferMemoryBarrierCount
,
3042 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3043 uint32_t imageMemoryBarrierCount
,
3044 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
3045 const struct tu_barrier_info
*info
)
3050 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer
,
3051 VkPipelineStageFlags srcStageMask
,
3052 VkPipelineStageFlags destStageMask
,
3054 uint32_t memoryBarrierCount
,
3055 const VkMemoryBarrier
*pMemoryBarriers
,
3056 uint32_t bufferMemoryBarrierCount
,
3057 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3058 uint32_t imageMemoryBarrierCount
,
3059 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3061 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3062 struct tu_barrier_info info
;
3064 info
.eventCount
= 0;
3065 info
.pEvents
= NULL
;
3066 info
.srcStageMask
= srcStageMask
;
3068 tu_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
3069 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
3070 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
3074 write_event(struct tu_cmd_buffer
*cmd_buffer
,
3075 struct tu_event
*event
,
3076 VkPipelineStageFlags stageMask
,
3082 tu_CmdSetEvent(VkCommandBuffer commandBuffer
,
3084 VkPipelineStageFlags stageMask
)
3086 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3087 TU_FROM_HANDLE(tu_event
, event
, _event
);
3089 write_event(cmd_buffer
, event
, stageMask
, 1);
3093 tu_CmdResetEvent(VkCommandBuffer commandBuffer
,
3095 VkPipelineStageFlags stageMask
)
3097 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3098 TU_FROM_HANDLE(tu_event
, event
, _event
);
3100 write_event(cmd_buffer
, event
, stageMask
, 0);
3104 tu_CmdWaitEvents(VkCommandBuffer commandBuffer
,
3105 uint32_t eventCount
,
3106 const VkEvent
*pEvents
,
3107 VkPipelineStageFlags srcStageMask
,
3108 VkPipelineStageFlags dstStageMask
,
3109 uint32_t memoryBarrierCount
,
3110 const VkMemoryBarrier
*pMemoryBarriers
,
3111 uint32_t bufferMemoryBarrierCount
,
3112 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3113 uint32_t imageMemoryBarrierCount
,
3114 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3116 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3117 struct tu_barrier_info info
;
3119 info
.eventCount
= eventCount
;
3120 info
.pEvents
= pEvents
;
3121 info
.srcStageMask
= 0;
3123 tu_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
3124 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
3125 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
3129 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer
, uint32_t deviceMask
)