2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
25 * DEALINGS IN THE SOFTWARE.
28 #include "tu_private.h"
30 #include "adreno_pm4.xml.h"
31 #include "adreno_common.xml.h"
33 #include "vk_format.h"
38 tu_bo_list_init(struct tu_bo_list
*list
)
40 list
->count
= list
->capacity
= 0;
41 list
->bo_infos
= NULL
;
45 tu_bo_list_destroy(struct tu_bo_list
*list
)
51 tu_bo_list_reset(struct tu_bo_list
*list
)
57 * \a flags consists of MSM_SUBMIT_BO_FLAGS.
60 tu_bo_list_add_info(struct tu_bo_list
*list
,
61 const struct drm_msm_gem_submit_bo
*bo_info
)
63 assert(bo_info
->handle
!= 0);
65 for (uint32_t i
= 0; i
< list
->count
; ++i
) {
66 if (list
->bo_infos
[i
].handle
== bo_info
->handle
) {
67 assert(list
->bo_infos
[i
].presumed
== bo_info
->presumed
);
68 list
->bo_infos
[i
].flags
|= bo_info
->flags
;
73 /* grow list->bo_infos if needed */
74 if (list
->count
== list
->capacity
) {
75 uint32_t new_capacity
= MAX2(2 * list
->count
, 16);
76 struct drm_msm_gem_submit_bo
*new_bo_infos
= realloc(
77 list
->bo_infos
, new_capacity
* sizeof(struct drm_msm_gem_submit_bo
));
79 return TU_BO_LIST_FAILED
;
80 list
->bo_infos
= new_bo_infos
;
81 list
->capacity
= new_capacity
;
84 list
->bo_infos
[list
->count
] = *bo_info
;
89 tu_bo_list_add(struct tu_bo_list
*list
,
90 const struct tu_bo
*bo
,
93 return tu_bo_list_add_info(list
, &(struct drm_msm_gem_submit_bo
) {
95 .handle
= bo
->gem_handle
,
101 tu_bo_list_merge(struct tu_bo_list
*list
, const struct tu_bo_list
*other
)
103 for (uint32_t i
= 0; i
< other
->count
; i
++) {
104 if (tu_bo_list_add_info(list
, other
->bo_infos
+ i
) == TU_BO_LIST_FAILED
)
105 return VK_ERROR_OUT_OF_HOST_MEMORY
;
112 tu6_emit_event_write(struct tu_cmd_buffer
*cmd
,
114 enum vgt_event_type event
)
116 bool need_seqno
= false;
121 case PC_CCU_FLUSH_DEPTH_TS
:
122 case PC_CCU_FLUSH_COLOR_TS
:
123 case PC_CCU_RESOLVE_TS
:
130 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, need_seqno
? 4 : 1);
131 tu_cs_emit(cs
, CP_EVENT_WRITE_0_EVENT(event
));
133 tu_cs_emit_qw(cs
, global_iova(cmd
, seqno_dummy
));
139 tu6_emit_flushes(struct tu_cmd_buffer
*cmd_buffer
,
141 enum tu_cmd_flush_bits flushes
)
143 /* Experiments show that invalidating CCU while it still has data in it
144 * doesn't work, so make sure to always flush before invalidating in case
145 * any data remains that hasn't yet been made available through a barrier.
146 * However it does seem to work for UCHE.
148 if (flushes
& (TU_CMD_FLAG_CCU_FLUSH_COLOR
|
149 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
))
150 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_FLUSH_COLOR_TS
);
151 if (flushes
& (TU_CMD_FLAG_CCU_FLUSH_DEPTH
|
152 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
))
153 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_FLUSH_DEPTH_TS
);
154 if (flushes
& TU_CMD_FLAG_CCU_INVALIDATE_COLOR
)
155 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_INVALIDATE_COLOR
);
156 if (flushes
& TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
)
157 tu6_emit_event_write(cmd_buffer
, cs
, PC_CCU_INVALIDATE_DEPTH
);
158 if (flushes
& TU_CMD_FLAG_CACHE_FLUSH
)
159 tu6_emit_event_write(cmd_buffer
, cs
, CACHE_FLUSH_TS
);
160 if (flushes
& TU_CMD_FLAG_CACHE_INVALIDATE
)
161 tu6_emit_event_write(cmd_buffer
, cs
, CACHE_INVALIDATE
);
162 if (flushes
& TU_CMD_FLAG_WAIT_MEM_WRITES
)
163 tu_cs_emit_pkt7(cs
, CP_WAIT_MEM_WRITES
, 0);
164 if (flushes
& TU_CMD_FLAG_WAIT_FOR_IDLE
)
166 if (flushes
& TU_CMD_FLAG_WAIT_FOR_ME
)
167 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
170 /* "Normal" cache flushes, that don't require any special handling */
173 tu_emit_cache_flush(struct tu_cmd_buffer
*cmd_buffer
,
176 tu6_emit_flushes(cmd_buffer
, cs
, cmd_buffer
->state
.cache
.flush_bits
);
177 cmd_buffer
->state
.cache
.flush_bits
= 0;
180 /* Renderpass cache flushes */
183 tu_emit_cache_flush_renderpass(struct tu_cmd_buffer
*cmd_buffer
,
186 tu6_emit_flushes(cmd_buffer
, cs
, cmd_buffer
->state
.renderpass_cache
.flush_bits
);
187 cmd_buffer
->state
.renderpass_cache
.flush_bits
= 0;
190 /* Cache flushes for things that use the color/depth read/write path (i.e.
191 * blits and draws). This deals with changing CCU state as well as the usual
196 tu_emit_cache_flush_ccu(struct tu_cmd_buffer
*cmd_buffer
,
198 enum tu_cmd_ccu_state ccu_state
)
200 enum tu_cmd_flush_bits flushes
= cmd_buffer
->state
.cache
.flush_bits
;
202 assert(ccu_state
!= TU_CMD_CCU_UNKNOWN
);
204 /* Changing CCU state must involve invalidating the CCU. In sysmem mode,
205 * the CCU may also contain data that we haven't flushed out yet, so we
206 * also need to flush. Also, in order to program RB_CCU_CNTL, we need to
207 * emit a WFI as it isn't pipelined.
209 if (ccu_state
!= cmd_buffer
->state
.ccu_state
) {
210 if (cmd_buffer
->state
.ccu_state
!= TU_CMD_CCU_GMEM
) {
212 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
213 TU_CMD_FLAG_CCU_FLUSH_DEPTH
;
214 cmd_buffer
->state
.cache
.pending_flush_bits
&= ~(
215 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
216 TU_CMD_FLAG_CCU_FLUSH_DEPTH
);
219 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
|
220 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
|
221 TU_CMD_FLAG_WAIT_FOR_IDLE
;
222 cmd_buffer
->state
.cache
.pending_flush_bits
&= ~(
223 TU_CMD_FLAG_CCU_INVALIDATE_COLOR
|
224 TU_CMD_FLAG_CCU_INVALIDATE_DEPTH
|
225 TU_CMD_FLAG_WAIT_FOR_IDLE
);
228 tu6_emit_flushes(cmd_buffer
, cs
, flushes
);
229 cmd_buffer
->state
.cache
.flush_bits
= 0;
231 if (ccu_state
!= cmd_buffer
->state
.ccu_state
) {
232 struct tu_physical_device
*phys_dev
= cmd_buffer
->device
->physical_device
;
234 A6XX_RB_CCU_CNTL(.offset
=
235 ccu_state
== TU_CMD_CCU_GMEM
?
236 phys_dev
->ccu_offset_gmem
:
237 phys_dev
->ccu_offset_bypass
,
238 .gmem
= ccu_state
== TU_CMD_CCU_GMEM
));
239 cmd_buffer
->state
.ccu_state
= ccu_state
;
244 tu6_emit_zs(struct tu_cmd_buffer
*cmd
,
245 const struct tu_subpass
*subpass
,
248 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
250 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
251 if (a
== VK_ATTACHMENT_UNUSED
) {
253 A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
),
254 A6XX_RB_DEPTH_BUFFER_PITCH(0),
255 A6XX_RB_DEPTH_BUFFER_ARRAY_PITCH(0),
256 A6XX_RB_DEPTH_BUFFER_BASE(0),
257 A6XX_RB_DEPTH_BUFFER_BASE_GMEM(0));
260 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= DEPTH6_NONE
));
263 A6XX_GRAS_LRZ_BUFFER_BASE(0),
264 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
265 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
267 tu_cs_emit_regs(cs
, A6XX_RB_STENCIL_INFO(0));
272 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
273 const struct tu_render_pass_attachment
*attachment
=
274 &cmd
->state
.pass
->attachments
[a
];
275 enum a6xx_depth_format fmt
= tu6_pipe2depth(attachment
->format
);
277 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_BUFFER_INFO
, 6);
278 tu_cs_emit(cs
, A6XX_RB_DEPTH_BUFFER_INFO(.depth_format
= fmt
).value
);
279 tu_cs_image_ref(cs
, iview
, 0);
280 tu_cs_emit(cs
, attachment
->gmem_offset
);
283 A6XX_GRAS_SU_DEPTH_BUFFER_INFO(.depth_format
= fmt
));
285 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_DEPTH_FLAG_BUFFER_BASE_LO
, 3);
286 tu_cs_image_flag_ref(cs
, iview
, 0);
289 A6XX_GRAS_LRZ_BUFFER_BASE(0),
290 A6XX_GRAS_LRZ_BUFFER_PITCH(0),
291 A6XX_GRAS_LRZ_FAST_CLEAR_BUFFER_BASE(0));
293 if (attachment
->format
== VK_FORMAT_S8_UINT
) {
294 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_STENCIL_INFO
, 6);
295 tu_cs_emit(cs
, A6XX_RB_STENCIL_INFO(.separate_stencil
= true).value
);
296 tu_cs_image_ref(cs
, iview
, 0);
297 tu_cs_emit(cs
, attachment
->gmem_offset
);
300 A6XX_RB_STENCIL_INFO(0));
305 tu6_emit_mrt(struct tu_cmd_buffer
*cmd
,
306 const struct tu_subpass
*subpass
,
309 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
311 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
312 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
313 if (a
== VK_ATTACHMENT_UNUSED
)
316 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
318 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_BUF_INFO(i
), 6);
319 tu_cs_emit(cs
, iview
->RB_MRT_BUF_INFO
);
320 tu_cs_image_ref(cs
, iview
, 0);
321 tu_cs_emit(cs
, cmd
->state
.pass
->attachments
[a
].gmem_offset
);
324 A6XX_SP_FS_MRT_REG(i
, .dword
= iview
->SP_FS_MRT_REG
));
326 tu_cs_emit_pkt4(cs
, REG_A6XX_RB_MRT_FLAG_BUFFER_ADDR_LO(i
), 3);
327 tu_cs_image_flag_ref(cs
, iview
, 0);
331 A6XX_RB_SRGB_CNTL(.dword
= subpass
->srgb_cntl
));
333 A6XX_SP_SRGB_CNTL(.dword
= subpass
->srgb_cntl
));
335 tu_cs_emit_regs(cs
, A6XX_GRAS_MAX_LAYER_INDEX(fb
->layers
- 1));
339 tu6_emit_msaa(struct tu_cs
*cs
, VkSampleCountFlagBits vk_samples
)
341 const enum a3xx_msaa_samples samples
= tu_msaa_samples(vk_samples
);
342 bool msaa_disable
= samples
== MSAA_ONE
;
345 A6XX_SP_TP_RAS_MSAA_CNTL(samples
),
346 A6XX_SP_TP_DEST_MSAA_CNTL(.samples
= samples
,
347 .msaa_disable
= msaa_disable
));
350 A6XX_GRAS_RAS_MSAA_CNTL(samples
),
351 A6XX_GRAS_DEST_MSAA_CNTL(.samples
= samples
,
352 .msaa_disable
= msaa_disable
));
355 A6XX_RB_RAS_MSAA_CNTL(samples
),
356 A6XX_RB_DEST_MSAA_CNTL(.samples
= samples
,
357 .msaa_disable
= msaa_disable
));
360 A6XX_RB_MSAA_CNTL(samples
));
364 tu6_emit_bin_size(struct tu_cs
*cs
,
365 uint32_t bin_w
, uint32_t bin_h
, uint32_t flags
)
368 A6XX_GRAS_BIN_CONTROL(.binw
= bin_w
,
373 A6XX_RB_BIN_CONTROL(.binw
= bin_w
,
377 /* no flag for RB_BIN_CONTROL2... */
379 A6XX_RB_BIN_CONTROL2(.binw
= bin_w
,
384 tu6_emit_render_cntl(struct tu_cmd_buffer
*cmd
,
385 const struct tu_subpass
*subpass
,
389 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
391 cntl
|= A6XX_RB_RENDER_CNTL_UNK4
;
393 cntl
|= A6XX_RB_RENDER_CNTL_BINNING
;
395 uint32_t mrts_ubwc_enable
= 0;
396 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
397 uint32_t a
= subpass
->color_attachments
[i
].attachment
;
398 if (a
== VK_ATTACHMENT_UNUSED
)
401 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
402 if (iview
->ubwc_enabled
)
403 mrts_ubwc_enable
|= 1 << i
;
406 cntl
|= A6XX_RB_RENDER_CNTL_FLAG_MRTS(mrts_ubwc_enable
);
408 const uint32_t a
= subpass
->depth_stencil_attachment
.attachment
;
409 if (a
!= VK_ATTACHMENT_UNUSED
) {
410 const struct tu_image_view
*iview
= fb
->attachments
[a
].attachment
;
411 if (iview
->ubwc_enabled
)
412 cntl
|= A6XX_RB_RENDER_CNTL_FLAG_DEPTH
;
415 /* In the !binning case, we need to set RB_RENDER_CNTL in the draw_cs
416 * in order to set it correctly for the different subpasses. However,
417 * that means the packets we're emitting also happen during binning. So
418 * we need to guard the write on !BINNING at CP execution time.
420 tu_cs_reserve(cs
, 3 + 4);
421 tu_cs_emit_pkt7(cs
, CP_COND_REG_EXEC
, 2);
422 tu_cs_emit(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
423 CP_COND_REG_EXEC_0_GMEM
| CP_COND_REG_EXEC_0_SYSMEM
);
424 tu_cs_emit(cs
, CP_COND_REG_EXEC_1_DWORDS(4));
427 tu_cs_emit_pkt7(cs
, CP_REG_WRITE
, 3);
428 tu_cs_emit(cs
, CP_REG_WRITE_0_TRACKER(TRACK_RENDER_CNTL
));
429 tu_cs_emit(cs
, REG_A6XX_RB_RENDER_CNTL
);
430 tu_cs_emit(cs
, cntl
);
434 tu6_emit_blit_scissor(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
, bool align
)
437 const VkRect2D
*render_area
= &cmd
->state
.render_area
;
439 /* Avoid assertion fails with an empty render area at (0, 0) where the
440 * subtraction below wraps around. Empty render areas should be forced to
441 * the sysmem path by use_sysmem_rendering(). It's not even clear whether
442 * an empty scissor here works, and the blob seems to force sysmem too as
443 * it sets something wrong (non-empty) for the scissor.
445 if (render_area
->extent
.width
== 0 ||
446 render_area
->extent
.height
== 0)
449 uint32_t x1
= render_area
->offset
.x
;
450 uint32_t y1
= render_area
->offset
.y
;
451 uint32_t x2
= x1
+ render_area
->extent
.width
- 1;
452 uint32_t y2
= y1
+ render_area
->extent
.height
- 1;
455 x1
= x1
& ~(GMEM_ALIGN_W
- 1);
456 y1
= y1
& ~(GMEM_ALIGN_H
- 1);
457 x2
= ALIGN_POT(x2
+ 1, GMEM_ALIGN_W
) - 1;
458 y2
= ALIGN_POT(y2
+ 1, GMEM_ALIGN_H
) - 1;
462 A6XX_RB_BLIT_SCISSOR_TL(.x
= x1
, .y
= y1
),
463 A6XX_RB_BLIT_SCISSOR_BR(.x
= x2
, .y
= y2
));
467 tu6_emit_window_scissor(struct tu_cs
*cs
,
474 A6XX_GRAS_SC_WINDOW_SCISSOR_TL(.x
= x1
, .y
= y1
),
475 A6XX_GRAS_SC_WINDOW_SCISSOR_BR(.x
= x2
, .y
= y2
));
478 A6XX_GRAS_2D_RESOLVE_CNTL_1(.x
= x1
, .y
= y1
),
479 A6XX_GRAS_2D_RESOLVE_CNTL_2(.x
= x2
, .y
= y2
));
483 tu6_emit_window_offset(struct tu_cs
*cs
, uint32_t x1
, uint32_t y1
)
486 A6XX_RB_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
489 A6XX_RB_WINDOW_OFFSET2(.x
= x1
, .y
= y1
));
492 A6XX_SP_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
495 A6XX_SP_TP_WINDOW_OFFSET(.x
= x1
, .y
= y1
));
499 tu_cs_emit_draw_state(struct tu_cs
*cs
, uint32_t id
, struct tu_draw_state state
)
501 uint32_t enable_mask
;
503 case TU_DRAW_STATE_PROGRAM
:
504 case TU_DRAW_STATE_VI
:
505 case TU_DRAW_STATE_FS_CONST
:
506 /* The blob seems to not enable this (DESC_SETS_LOAD) for binning, even
507 * when resources would actually be used in the binning shader.
508 * Presumably the overhead of prefetching the resources isn't
511 case TU_DRAW_STATE_DESC_SETS_LOAD
:
512 enable_mask
= CP_SET_DRAW_STATE__0_GMEM
|
513 CP_SET_DRAW_STATE__0_SYSMEM
;
515 case TU_DRAW_STATE_PROGRAM_BINNING
:
516 case TU_DRAW_STATE_VI_BINNING
:
517 enable_mask
= CP_SET_DRAW_STATE__0_BINNING
;
519 case TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM
:
520 enable_mask
= CP_SET_DRAW_STATE__0_GMEM
;
522 case TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM
:
523 enable_mask
= CP_SET_DRAW_STATE__0_SYSMEM
;
526 enable_mask
= CP_SET_DRAW_STATE__0_GMEM
|
527 CP_SET_DRAW_STATE__0_SYSMEM
|
528 CP_SET_DRAW_STATE__0_BINNING
;
532 /* We need to reload the descriptors every time the descriptor sets
533 * change. However, the commands we send only depend on the pipeline
534 * because the whole point is to cache descriptors which are used by the
535 * pipeline. There's a problem here, in that the firmware has an
536 * "optimization" which skips executing groups that are set to the same
537 * value as the last draw. This means that if the descriptor sets change
538 * but not the pipeline, we'd try to re-execute the same buffer which
539 * the firmware would ignore and we wouldn't pre-load the new
540 * descriptors. Set the DIRTY bit to avoid this optimization
542 if (id
== TU_DRAW_STATE_DESC_SETS_LOAD
)
543 enable_mask
|= CP_SET_DRAW_STATE__0_DIRTY
;
545 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(state
.size
) |
547 CP_SET_DRAW_STATE__0_GROUP_ID(id
) |
548 COND(!state
.size
, CP_SET_DRAW_STATE__0_DISABLE
));
549 tu_cs_emit_qw(cs
, state
.iova
);
553 use_hw_binning(struct tu_cmd_buffer
*cmd
)
555 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
557 /* XFB commands are emitted for BINNING || SYSMEM, which makes it incompatible
558 * with non-hw binning GMEM rendering. this is required because some of the
559 * XFB commands need to only be executed once
561 if (cmd
->state
.xfb_used
)
564 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_NOBIN
))
567 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_FORCEBIN
))
570 return (fb
->tile_count
.width
* fb
->tile_count
.height
) > 2;
574 use_sysmem_rendering(struct tu_cmd_buffer
*cmd
)
576 if (unlikely(cmd
->device
->physical_device
->instance
->debug_flags
& TU_DEBUG_SYSMEM
))
579 /* can't fit attachments into gmem */
580 if (!cmd
->state
.pass
->gmem_pixels
)
583 if (cmd
->state
.framebuffer
->layers
> 1)
586 /* Use sysmem for empty render areas */
587 if (cmd
->state
.render_area
.extent
.width
== 0 ||
588 cmd
->state
.render_area
.extent
.height
== 0)
598 tu6_emit_tile_select(struct tu_cmd_buffer
*cmd
,
600 uint32_t tx
, uint32_t ty
, uint32_t pipe
, uint32_t slot
)
602 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
604 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
605 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_YIELD
));
607 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
608 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_GMEM
));
610 const uint32_t x1
= fb
->tile0
.width
* tx
;
611 const uint32_t y1
= fb
->tile0
.height
* ty
;
612 const uint32_t x2
= x1
+ fb
->tile0
.width
- 1;
613 const uint32_t y2
= y1
+ fb
->tile0
.height
- 1;
614 tu6_emit_window_scissor(cs
, x1
, y1
, x2
, y2
);
615 tu6_emit_window_offset(cs
, x1
, y1
);
617 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(false));
619 if (use_hw_binning(cmd
)) {
620 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
622 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
625 tu_cs_emit_pkt7(cs
, CP_SET_BIN_DATA5_OFFSET
, 4);
626 tu_cs_emit(cs
, fb
->pipe_sizes
[pipe
] |
627 CP_SET_BIN_DATA5_0_VSC_N(slot
));
628 tu_cs_emit(cs
, pipe
* cmd
->vsc_draw_strm_pitch
);
629 tu_cs_emit(cs
, pipe
* 4);
630 tu_cs_emit(cs
, pipe
* cmd
->vsc_prim_strm_pitch
);
632 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
635 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
638 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
641 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
647 tu6_emit_sysmem_resolve(struct tu_cmd_buffer
*cmd
,
652 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
653 struct tu_image_view
*dst
= fb
->attachments
[a
].attachment
;
654 struct tu_image_view
*src
= fb
->attachments
[gmem_a
].attachment
;
656 tu_resolve_sysmem(cmd
, cs
, src
, dst
, fb
->layers
, &cmd
->state
.render_area
);
660 tu6_emit_sysmem_resolves(struct tu_cmd_buffer
*cmd
,
662 const struct tu_subpass
*subpass
)
664 if (subpass
->resolve_attachments
) {
665 /* From the documentation for vkCmdNextSubpass, section 7.4 "Render Pass
668 * End-of-subpass multisample resolves are treated as color
669 * attachment writes for the purposes of synchronization. That is,
670 * they are considered to execute in the
671 * VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT pipeline stage and
672 * their writes are synchronized with
673 * VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT. Synchronization between
674 * rendering within a subpass and any resolve operations at the end
675 * of the subpass occurs automatically, without need for explicit
676 * dependencies or pipeline barriers. However, if the resolve
677 * attachment is also used in a different subpass, an explicit
678 * dependency is needed.
680 * We use the CP_BLIT path for sysmem resolves, which is really a
681 * transfer command, so we have to manually flush similar to the gmem
682 * resolve case. However, a flush afterwards isn't needed because of the
683 * last sentence and the fact that we're in sysmem mode.
685 tu6_emit_event_write(cmd
, cs
, PC_CCU_FLUSH_COLOR_TS
);
686 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
);
688 /* Wait for the flushes to land before using the 2D engine */
691 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
692 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
693 if (a
== VK_ATTACHMENT_UNUSED
)
696 tu6_emit_sysmem_resolve(cmd
, cs
, a
,
697 subpass
->color_attachments
[i
].attachment
);
703 tu6_emit_tile_store(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
705 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
706 const struct tu_subpass
*subpass
= &pass
->subpasses
[pass
->subpass_count
-1];
708 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
709 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
710 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
711 CP_SET_DRAW_STATE__0_GROUP_ID(0));
712 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
713 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
715 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
718 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
719 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_RESOLVE
));
721 tu6_emit_blit_scissor(cmd
, cs
, true);
723 for (uint32_t a
= 0; a
< pass
->attachment_count
; ++a
) {
724 if (pass
->attachments
[a
].gmem_offset
>= 0)
725 tu_store_gmem_attachment(cmd
, cs
, a
, a
);
728 if (subpass
->resolve_attachments
) {
729 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
730 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
731 if (a
!= VK_ATTACHMENT_UNUSED
)
732 tu_store_gmem_attachment(cmd
, cs
, a
,
733 subpass
->color_attachments
[i
].attachment
);
739 tu6_init_hw(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
741 struct tu_device
*dev
= cmd
->device
;
742 const struct tu_physical_device
*phys_dev
= dev
->physical_device
;
744 tu6_emit_event_write(cmd
, cs
, CACHE_INVALIDATE
);
746 tu_cs_emit_regs(cs
, A6XX_HLSQ_INVALIDATE_CMD(
755 .gfx_shared_const
= true,
756 .cs_shared_const
= true,
757 .gfx_bindless
= 0x1f,
758 .cs_bindless
= 0x1f));
762 cmd
->state
.cache
.pending_flush_bits
&=
763 ~(TU_CMD_FLAG_WAIT_FOR_IDLE
| TU_CMD_FLAG_CACHE_INVALIDATE
);
766 A6XX_RB_CCU_CNTL(.offset
= phys_dev
->ccu_offset_bypass
));
767 cmd
->state
.ccu_state
= TU_CMD_CCU_SYSMEM
;
768 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E04
, 0x00100000);
769 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE04
, 0x8);
770 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE00
, 0);
771 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE0F
, 0x3f);
772 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B605
, 0x44);
773 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B600
, 0x100000);
774 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE00
, 0x80);
775 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE01
, 0);
777 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9600
, 0);
778 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8600
, 0x880);
779 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_UNKNOWN_BE04
, 0);
780 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AE03
, 0x00000410);
781 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_IBO_COUNT
, 0);
782 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B182
, 0);
783 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_SHARED_CONSTS
, 0);
784 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_UNKNOWN_0E12
, 0x3200000);
785 tu_cs_emit_write_reg(cs
, REG_A6XX_UCHE_CLIENT_PF
, 4);
786 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8E01
, 0x0);
787 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A982
, 0);
788 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A9A8
, 0);
789 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_AB00
, 0x5);
791 /* TODO: set A6XX_VFD_ADD_OFFSET_INSTANCE and fix ir3 to avoid adding base instance */
792 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_ADD_OFFSET
, A6XX_VFD_ADD_OFFSET_VERTEX
);
793 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8811
, 0x00000010);
794 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x1f);
796 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_SRGB_CNTL
, 0);
798 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8110
, 0);
800 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL0
, 0x401);
801 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_RENDER_CONTROL1
, 0);
802 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_FS_OUTPUT_CNTL0
, 0);
803 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8818
, 0);
804 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_8819
, 0);
805 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881A
, 0);
806 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881B
, 0);
807 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881C
, 0);
808 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881D
, 0);
809 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_881E
, 0);
810 tu_cs_emit_write_reg(cs
, REG_A6XX_RB_UNKNOWN_88F0
, 0);
812 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9107
, 0);
814 tu_cs_emit_regs(cs
, A6XX_VPC_POINT_COORD_INVERT(false));
815 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9300
, 0);
817 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(true));
819 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9980
, 0);
821 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_PRIMITIVE_CNTL_6
, 0);
822 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9B07
, 0);
824 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_A81B
, 0);
826 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_UNKNOWN_B183
, 0);
828 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_8099
, 0);
829 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80A0
, 2);
830 tu_cs_emit_write_reg(cs
, REG_A6XX_GRAS_UNKNOWN_80AF
, 0);
831 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9210
, 0);
832 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9211
, 0);
833 tu_cs_emit_write_reg(cs
, REG_A6XX_VPC_UNKNOWN_9602
, 0);
834 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_UNKNOWN_9E72
, 0);
835 tu_cs_emit_write_reg(cs
, REG_A6XX_SP_TP_UNKNOWN_B309
, 0x000000a2);
836 tu_cs_emit_write_reg(cs
, REG_A6XX_HLSQ_CONTROL_5_REG
, 0xfc);
838 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_MODE_CNTL
, 0x00000000);
840 tu_cs_emit_write_reg(cs
, REG_A6XX_VFD_UNKNOWN_A008
, 0);
842 tu_cs_emit_write_reg(cs
, REG_A6XX_PC_MODE_CNTL
, 0x0000001f);
844 /* we don't use this yet.. probably best to disable.. */
845 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
846 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
847 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
848 CP_SET_DRAW_STATE__0_GROUP_ID(0));
849 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
850 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
853 A6XX_SP_HS_CTRL_REG0(0));
856 A6XX_SP_GS_CTRL_REG0(0));
859 A6XX_GRAS_LRZ_CNTL(0));
862 A6XX_RB_LRZ_CNTL(0));
865 A6XX_SP_TP_BORDER_COLOR_BASE_ADDR(.bo
= &dev
->global_bo
,
866 .bo_offset
= gb_offset(border_color
)));
868 A6XX_SP_PS_TP_BORDER_COLOR_BASE_ADDR(.bo
= &dev
->global_bo
,
869 .bo_offset
= gb_offset(border_color
)));
872 * use vsc pitches from the largest values used so far with this device
873 * if there hasn't been overflow, there will already be a scratch bo
874 * allocated for these sizes
876 * if overflow is detected, the stream size is increased by 2x
878 mtx_lock(&dev
->vsc_pitch_mtx
);
880 struct tu6_global
*global
= dev
->global_bo
.map
;
882 uint32_t vsc_draw_overflow
= global
->vsc_draw_overflow
;
883 uint32_t vsc_prim_overflow
= global
->vsc_prim_overflow
;
885 if (vsc_draw_overflow
>= dev
->vsc_draw_strm_pitch
)
886 dev
->vsc_draw_strm_pitch
= (dev
->vsc_draw_strm_pitch
- VSC_PAD
) * 2 + VSC_PAD
;
888 if (vsc_prim_overflow
>= dev
->vsc_prim_strm_pitch
)
889 dev
->vsc_prim_strm_pitch
= (dev
->vsc_prim_strm_pitch
- VSC_PAD
) * 2 + VSC_PAD
;
891 cmd
->vsc_prim_strm_pitch
= dev
->vsc_prim_strm_pitch
;
892 cmd
->vsc_draw_strm_pitch
= dev
->vsc_draw_strm_pitch
;
894 mtx_unlock(&dev
->vsc_pitch_mtx
);
896 struct tu_bo
*vsc_bo
;
897 uint32_t size0
= cmd
->vsc_prim_strm_pitch
* MAX_VSC_PIPES
+
898 cmd
->vsc_draw_strm_pitch
* MAX_VSC_PIPES
;
900 tu_get_scratch_bo(dev
, size0
+ MAX_VSC_PIPES
* 4, &vsc_bo
);
903 A6XX_VSC_DRAW_STRM_SIZE_ADDRESS(.bo
= vsc_bo
, .bo_offset
= size0
));
905 A6XX_VSC_PRIM_STRM_ADDRESS(.bo
= vsc_bo
));
907 A6XX_VSC_DRAW_STRM_ADDRESS(.bo
= vsc_bo
,
908 .bo_offset
= cmd
->vsc_prim_strm_pitch
* MAX_VSC_PIPES
));
910 tu_bo_list_add(&cmd
->bo_list
, vsc_bo
, MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
912 tu_cs_sanity_check(cs
);
916 update_vsc_pipe(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
918 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
921 A6XX_VSC_BIN_SIZE(.width
= fb
->tile0
.width
,
922 .height
= fb
->tile0
.height
));
925 A6XX_VSC_BIN_COUNT(.nx
= fb
->tile_count
.width
,
926 .ny
= fb
->tile_count
.height
));
928 tu_cs_emit_pkt4(cs
, REG_A6XX_VSC_PIPE_CONFIG_REG(0), 32);
929 tu_cs_emit_array(cs
, fb
->pipe_config
, 32);
932 A6XX_VSC_PRIM_STRM_PITCH(cmd
->vsc_prim_strm_pitch
),
933 A6XX_VSC_PRIM_STRM_LIMIT(cmd
->vsc_prim_strm_pitch
- VSC_PAD
));
936 A6XX_VSC_DRAW_STRM_PITCH(cmd
->vsc_draw_strm_pitch
),
937 A6XX_VSC_DRAW_STRM_LIMIT(cmd
->vsc_draw_strm_pitch
- VSC_PAD
));
941 emit_vsc_overflow_test(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
943 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
944 const uint32_t used_pipe_count
=
945 fb
->pipe_count
.width
* fb
->pipe_count
.height
;
947 for (int i
= 0; i
< used_pipe_count
; i
++) {
948 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
949 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
950 CP_COND_WRITE5_0_WRITE_MEMORY
);
951 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_DRAW_STRM_SIZE_REG(i
)));
952 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
953 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_draw_strm_pitch
- VSC_PAD
));
954 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
955 tu_cs_emit_qw(cs
, global_iova(cmd
, vsc_draw_overflow
));
956 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(cmd
->vsc_draw_strm_pitch
));
958 tu_cs_emit_pkt7(cs
, CP_COND_WRITE5
, 8);
959 tu_cs_emit(cs
, CP_COND_WRITE5_0_FUNCTION(WRITE_GE
) |
960 CP_COND_WRITE5_0_WRITE_MEMORY
);
961 tu_cs_emit(cs
, CP_COND_WRITE5_1_POLL_ADDR_LO(REG_A6XX_VSC_PRIM_STRM_SIZE_REG(i
)));
962 tu_cs_emit(cs
, CP_COND_WRITE5_2_POLL_ADDR_HI(0));
963 tu_cs_emit(cs
, CP_COND_WRITE5_3_REF(cmd
->vsc_prim_strm_pitch
- VSC_PAD
));
964 tu_cs_emit(cs
, CP_COND_WRITE5_4_MASK(~0));
965 tu_cs_emit_qw(cs
, global_iova(cmd
, vsc_prim_overflow
));
966 tu_cs_emit(cs
, CP_COND_WRITE5_7_WRITE_DATA(cmd
->vsc_prim_strm_pitch
));
969 tu_cs_emit_pkt7(cs
, CP_WAIT_MEM_WRITES
, 0);
973 tu6_emit_binning_pass(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
975 struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
976 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
978 tu6_emit_window_scissor(cs
, 0, 0, fb
->width
- 1, fb
->height
- 1);
980 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
981 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_BINNING
));
983 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
986 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
992 A6XX_VFD_MODE_CNTL(.binning_pass
= true));
994 update_vsc_pipe(cmd
, cs
);
997 A6XX_PC_UNKNOWN_9805(.unknown
= phys_dev
->magic
.PC_UNKNOWN_9805
));
1000 A6XX_SP_UNKNOWN_A0F8(.unknown
= phys_dev
->magic
.SP_UNKNOWN_A0F8
));
1002 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
1003 tu_cs_emit(cs
, UNK_2C
);
1006 A6XX_RB_WINDOW_OFFSET(.x
= 0, .y
= 0));
1009 A6XX_SP_TP_WINDOW_OFFSET(.x
= 0, .y
= 0));
1011 /* emit IB to binning drawcmds: */
1012 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
1014 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3);
1015 tu_cs_emit(cs
, CP_SET_DRAW_STATE__0_COUNT(0) |
1016 CP_SET_DRAW_STATE__0_DISABLE_ALL_GROUPS
|
1017 CP_SET_DRAW_STATE__0_GROUP_ID(0));
1018 tu_cs_emit(cs
, CP_SET_DRAW_STATE__1_ADDR_LO(0));
1019 tu_cs_emit(cs
, CP_SET_DRAW_STATE__2_ADDR_HI(0));
1021 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 1);
1022 tu_cs_emit(cs
, UNK_2D
);
1024 /* This flush is probably required because the VSC, which produces the
1025 * visibility stream, is a client of UCHE, whereas the CP needs to read the
1026 * visibility stream (without caching) to do draw skipping. The
1027 * WFI+WAIT_FOR_ME combination guarantees that the binning commands
1028 * submitted are finished before reading the VSC regs (in
1029 * emit_vsc_overflow_test) or the VSC_DATA buffer directly (implicitly as
1032 tu6_emit_event_write(cmd
, cs
, CACHE_FLUSH_TS
);
1036 tu_cs_emit_pkt7(cs
, CP_WAIT_FOR_ME
, 0);
1038 emit_vsc_overflow_test(cmd
, cs
);
1040 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1041 tu_cs_emit(cs
, 0x0);
1043 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1044 tu_cs_emit(cs
, 0x0);
1047 static struct tu_draw_state
1048 tu_emit_input_attachments(struct tu_cmd_buffer
*cmd
,
1049 const struct tu_subpass
*subpass
,
1052 /* note: we can probably emit input attachments just once for the whole
1053 * renderpass, this would avoid emitting both sysmem/gmem versions
1055 * emit two texture descriptors for each input, as a workaround for
1056 * d24s8, which can be sampled as both float (depth) and integer (stencil)
1057 * tu_shader lowers uint input attachment loads to use the 2nd descriptor
1059 * TODO: a smarter workaround
1062 if (!subpass
->input_count
)
1063 return (struct tu_draw_state
) {};
1065 struct tu_cs_memory texture
;
1066 VkResult result
= tu_cs_alloc(&cmd
->sub_cs
, subpass
->input_count
* 2,
1067 A6XX_TEX_CONST_DWORDS
, &texture
);
1068 assert(result
== VK_SUCCESS
);
1070 for (unsigned i
= 0; i
< subpass
->input_count
* 2; i
++) {
1071 uint32_t a
= subpass
->input_attachments
[i
/ 2].attachment
;
1072 if (a
== VK_ATTACHMENT_UNUSED
)
1075 struct tu_image_view
*iview
=
1076 cmd
->state
.framebuffer
->attachments
[a
].attachment
;
1077 const struct tu_render_pass_attachment
*att
=
1078 &cmd
->state
.pass
->attachments
[a
];
1079 uint32_t *dst
= &texture
.map
[A6XX_TEX_CONST_DWORDS
* i
];
1081 memcpy(dst
, iview
->descriptor
, A6XX_TEX_CONST_DWORDS
* 4);
1083 if (i
% 2 == 1 && att
->format
== VK_FORMAT_D24_UNORM_S8_UINT
) {
1084 /* note this works because spec says fb and input attachments
1085 * must use identity swizzle
1087 dst
[0] &= ~(A6XX_TEX_CONST_0_FMT__MASK
|
1088 A6XX_TEX_CONST_0_SWIZ_X__MASK
| A6XX_TEX_CONST_0_SWIZ_Y__MASK
|
1089 A6XX_TEX_CONST_0_SWIZ_Z__MASK
| A6XX_TEX_CONST_0_SWIZ_W__MASK
);
1090 dst
[0] |= A6XX_TEX_CONST_0_FMT(FMT6_S8Z24_UINT
) |
1091 A6XX_TEX_CONST_0_SWIZ_X(A6XX_TEX_Y
) |
1092 A6XX_TEX_CONST_0_SWIZ_Y(A6XX_TEX_ZERO
) |
1093 A6XX_TEX_CONST_0_SWIZ_Z(A6XX_TEX_ZERO
) |
1094 A6XX_TEX_CONST_0_SWIZ_W(A6XX_TEX_ONE
);
1100 /* patched for gmem */
1101 dst
[0] &= ~(A6XX_TEX_CONST_0_SWAP__MASK
| A6XX_TEX_CONST_0_TILE_MODE__MASK
);
1102 dst
[0] |= A6XX_TEX_CONST_0_TILE_MODE(TILE6_2
);
1104 A6XX_TEX_CONST_2_TYPE(A6XX_TEX_2D
) |
1105 A6XX_TEX_CONST_2_PITCH(cmd
->state
.framebuffer
->tile0
.width
* att
->cpp
);
1107 dst
[4] = cmd
->device
->physical_device
->gmem_base
+ att
->gmem_offset
;
1108 dst
[5] = A6XX_TEX_CONST_5_DEPTH(1);
1109 for (unsigned i
= 6; i
< A6XX_TEX_CONST_DWORDS
; i
++)
1114 struct tu_draw_state ds
= tu_cs_draw_state(&cmd
->sub_cs
, &cs
, 9);
1116 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_FRAG
, 3);
1117 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(0) |
1118 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
1119 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
1120 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_FS_TEX
) |
1121 CP_LOAD_STATE6_0_NUM_UNIT(subpass
->input_count
* 2));
1122 tu_cs_emit_qw(&cs
, texture
.iova
);
1124 tu_cs_emit_pkt4(&cs
, REG_A6XX_SP_FS_TEX_CONST_LO
, 2);
1125 tu_cs_emit_qw(&cs
, texture
.iova
);
1127 tu_cs_emit_regs(&cs
, A6XX_SP_FS_TEX_COUNT(subpass
->input_count
* 2));
1129 assert(cs
.cur
== cs
.end
); /* validate draw state size */
1135 tu_set_input_attachments(struct tu_cmd_buffer
*cmd
, const struct tu_subpass
*subpass
)
1137 struct tu_cs
*cs
= &cmd
->draw_cs
;
1139 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 6);
1140 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_INPUT_ATTACHMENTS_GMEM
,
1141 tu_emit_input_attachments(cmd
, subpass
, true));
1142 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_INPUT_ATTACHMENTS_SYSMEM
,
1143 tu_emit_input_attachments(cmd
, subpass
, false));
1147 tu_emit_renderpass_begin(struct tu_cmd_buffer
*cmd
,
1148 const VkRenderPassBeginInfo
*info
)
1150 struct tu_cs
*cs
= &cmd
->draw_cs
;
1152 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_GMEM
);
1154 tu6_emit_blit_scissor(cmd
, cs
, true);
1156 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1157 tu_load_gmem_attachment(cmd
, cs
, i
, false);
1159 tu6_emit_blit_scissor(cmd
, cs
, false);
1161 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1162 tu_clear_gmem_attachment(cmd
, cs
, i
, info
);
1164 tu_cond_exec_end(cs
);
1166 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_SYSMEM
);
1168 for (uint32_t i
= 0; i
< cmd
->state
.pass
->attachment_count
; ++i
)
1169 tu_clear_sysmem_attachment(cmd
, cs
, i
, info
);
1171 tu_cond_exec_end(cs
);
1175 tu6_sysmem_render_begin(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1177 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
1179 assert(fb
->width
> 0 && fb
->height
> 0);
1180 tu6_emit_window_scissor(cs
, 0, 0, fb
->width
- 1, fb
->height
- 1);
1181 tu6_emit_window_offset(cs
, 0, 0);
1183 tu6_emit_bin_size(cs
, 0, 0, 0xc00000); /* 0xc00000 = BYPASS? */
1185 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1187 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1188 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_BYPASS
));
1190 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1191 tu_cs_emit(cs
, 0x0);
1193 tu_emit_cache_flush_ccu(cmd
, cs
, TU_CMD_CCU_SYSMEM
);
1195 /* enable stream-out, with sysmem there is only one pass: */
1196 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(false));
1198 tu_cs_emit_pkt7(cs
, CP_SET_VISIBILITY_OVERRIDE
, 1);
1199 tu_cs_emit(cs
, 0x1);
1201 tu_cs_emit_pkt7(cs
, CP_SET_MODE
, 1);
1202 tu_cs_emit(cs
, 0x0);
1204 tu_cs_sanity_check(cs
);
1208 tu6_sysmem_render_end(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1210 /* Do any resolves of the last subpass. These are handled in the
1211 * tile_store_ib in the gmem path.
1213 tu6_emit_sysmem_resolves(cmd
, cs
, cmd
->state
.subpass
);
1215 tu_cs_emit_call(cs
, &cmd
->draw_epilogue_cs
);
1217 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1218 tu_cs_emit(cs
, 0x0);
1220 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1222 tu_cs_sanity_check(cs
);
1226 tu6_tile_render_begin(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1228 struct tu_physical_device
*phys_dev
= cmd
->device
->physical_device
;
1230 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1234 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1235 tu_cs_emit(cs
, 0x0);
1237 tu_emit_cache_flush_ccu(cmd
, cs
, TU_CMD_CCU_GMEM
);
1239 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
1240 if (use_hw_binning(cmd
)) {
1241 /* enable stream-out during binning pass: */
1242 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(false));
1244 tu6_emit_bin_size(cs
, fb
->tile0
.width
, fb
->tile0
.height
,
1245 A6XX_RB_BIN_CONTROL_BINNING_PASS
| 0x6000000);
1247 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, cs
, true);
1249 tu6_emit_binning_pass(cmd
, cs
);
1251 /* and disable stream-out for draw pass: */
1252 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(true));
1254 tu6_emit_bin_size(cs
, fb
->tile0
.width
, fb
->tile0
.height
,
1255 A6XX_RB_BIN_CONTROL_USE_VIZ
| 0x6000000);
1258 A6XX_VFD_MODE_CNTL(0));
1260 tu_cs_emit_regs(cs
, A6XX_PC_UNKNOWN_9805(.unknown
= phys_dev
->magic
.PC_UNKNOWN_9805
));
1262 tu_cs_emit_regs(cs
, A6XX_SP_UNKNOWN_A0F8(.unknown
= phys_dev
->magic
.SP_UNKNOWN_A0F8
));
1264 tu_cs_emit_pkt7(cs
, CP_SKIP_IB2_ENABLE_GLOBAL
, 1);
1265 tu_cs_emit(cs
, 0x1);
1267 /* no binning pass, so enable stream-out for draw pass:: */
1268 tu_cs_emit_regs(cs
, A6XX_VPC_SO_DISABLE(false));
1270 tu6_emit_bin_size(cs
, fb
->tile0
.width
, fb
->tile0
.height
, 0x6000000);
1273 tu_cs_sanity_check(cs
);
1277 tu6_render_tile(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1279 tu_cs_emit_call(cs
, &cmd
->draw_cs
);
1281 if (use_hw_binning(cmd
)) {
1282 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
1283 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_ENDVIS
));
1286 tu_cs_emit_ib(cs
, &cmd
->state
.tile_store_ib
);
1288 tu_cs_sanity_check(cs
);
1292 tu6_tile_render_end(struct tu_cmd_buffer
*cmd
, struct tu_cs
*cs
)
1294 tu_cs_emit_call(cs
, &cmd
->draw_epilogue_cs
);
1297 A6XX_GRAS_LRZ_CNTL(0));
1299 tu6_emit_event_write(cmd
, cs
, LRZ_FLUSH
);
1301 tu6_emit_event_write(cmd
, cs
, PC_CCU_RESOLVE_TS
);
1303 tu_cs_sanity_check(cs
);
1307 tu_cmd_render_tiles(struct tu_cmd_buffer
*cmd
)
1309 const struct tu_framebuffer
*fb
= cmd
->state
.framebuffer
;
1311 tu6_tile_render_begin(cmd
, &cmd
->cs
);
1314 for (uint32_t py
= 0; py
< fb
->pipe_count
.height
; py
++) {
1315 for (uint32_t px
= 0; px
< fb
->pipe_count
.width
; px
++, pipe
++) {
1316 uint32_t tx1
= px
* fb
->pipe0
.width
;
1317 uint32_t ty1
= py
* fb
->pipe0
.height
;
1318 uint32_t tx2
= MIN2(tx1
+ fb
->pipe0
.width
, fb
->tile_count
.width
);
1319 uint32_t ty2
= MIN2(ty1
+ fb
->pipe0
.height
, fb
->tile_count
.height
);
1321 for (uint32_t ty
= ty1
; ty
< ty2
; ty
++) {
1322 for (uint32_t tx
= tx1
; tx
< tx2
; tx
++, slot
++) {
1323 tu6_emit_tile_select(cmd
, &cmd
->cs
, tx
, ty
, pipe
, slot
);
1324 tu6_render_tile(cmd
, &cmd
->cs
);
1330 tu6_tile_render_end(cmd
, &cmd
->cs
);
1334 tu_cmd_render_sysmem(struct tu_cmd_buffer
*cmd
)
1336 tu6_sysmem_render_begin(cmd
, &cmd
->cs
);
1338 tu_cs_emit_call(&cmd
->cs
, &cmd
->draw_cs
);
1340 tu6_sysmem_render_end(cmd
, &cmd
->cs
);
1344 tu_cmd_prepare_tile_store_ib(struct tu_cmd_buffer
*cmd
)
1346 const uint32_t tile_store_space
= 11 + (35 * 2) * cmd
->state
.pass
->attachment_count
;
1347 struct tu_cs sub_cs
;
1350 tu_cs_begin_sub_stream(&cmd
->sub_cs
, tile_store_space
, &sub_cs
);
1351 if (result
!= VK_SUCCESS
) {
1352 cmd
->record_result
= result
;
1356 /* emit to tile-store sub_cs */
1357 tu6_emit_tile_store(cmd
, &sub_cs
);
1359 cmd
->state
.tile_store_ib
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &sub_cs
);
1363 tu_create_cmd_buffer(struct tu_device
*device
,
1364 struct tu_cmd_pool
*pool
,
1365 VkCommandBufferLevel level
,
1366 VkCommandBuffer
*pCommandBuffer
)
1368 struct tu_cmd_buffer
*cmd_buffer
;
1370 cmd_buffer
= vk_object_zalloc(&device
->vk
, NULL
, sizeof(*cmd_buffer
),
1371 VK_OBJECT_TYPE_COMMAND_BUFFER
);
1372 if (cmd_buffer
== NULL
)
1373 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1375 cmd_buffer
->device
= device
;
1376 cmd_buffer
->pool
= pool
;
1377 cmd_buffer
->level
= level
;
1380 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1381 cmd_buffer
->queue_family_index
= pool
->queue_family_index
;
1384 /* Init the pool_link so we can safely call list_del when we destroy
1385 * the command buffer
1387 list_inithead(&cmd_buffer
->pool_link
);
1388 cmd_buffer
->queue_family_index
= TU_QUEUE_GENERAL
;
1391 tu_bo_list_init(&cmd_buffer
->bo_list
);
1392 tu_cs_init(&cmd_buffer
->cs
, device
, TU_CS_MODE_GROW
, 4096);
1393 tu_cs_init(&cmd_buffer
->draw_cs
, device
, TU_CS_MODE_GROW
, 4096);
1394 tu_cs_init(&cmd_buffer
->draw_epilogue_cs
, device
, TU_CS_MODE_GROW
, 4096);
1395 tu_cs_init(&cmd_buffer
->sub_cs
, device
, TU_CS_MODE_SUB_STREAM
, 2048);
1397 *pCommandBuffer
= tu_cmd_buffer_to_handle(cmd_buffer
);
1399 list_inithead(&cmd_buffer
->upload
.list
);
1405 tu_cmd_buffer_destroy(struct tu_cmd_buffer
*cmd_buffer
)
1407 list_del(&cmd_buffer
->pool_link
);
1409 tu_cs_finish(&cmd_buffer
->cs
);
1410 tu_cs_finish(&cmd_buffer
->draw_cs
);
1411 tu_cs_finish(&cmd_buffer
->draw_epilogue_cs
);
1412 tu_cs_finish(&cmd_buffer
->sub_cs
);
1414 tu_bo_list_destroy(&cmd_buffer
->bo_list
);
1415 vk_object_free(&cmd_buffer
->device
->vk
, &cmd_buffer
->pool
->alloc
, cmd_buffer
);
1419 tu_reset_cmd_buffer(struct tu_cmd_buffer
*cmd_buffer
)
1421 cmd_buffer
->record_result
= VK_SUCCESS
;
1423 tu_bo_list_reset(&cmd_buffer
->bo_list
);
1424 tu_cs_reset(&cmd_buffer
->cs
);
1425 tu_cs_reset(&cmd_buffer
->draw_cs
);
1426 tu_cs_reset(&cmd_buffer
->draw_epilogue_cs
);
1427 tu_cs_reset(&cmd_buffer
->sub_cs
);
1429 for (unsigned i
= 0; i
< MAX_BIND_POINTS
; i
++)
1430 memset(&cmd_buffer
->descriptors
[i
].sets
, 0, sizeof(cmd_buffer
->descriptors
[i
].sets
));
1432 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_INITIAL
;
1434 return cmd_buffer
->record_result
;
1438 tu_AllocateCommandBuffers(VkDevice _device
,
1439 const VkCommandBufferAllocateInfo
*pAllocateInfo
,
1440 VkCommandBuffer
*pCommandBuffers
)
1442 TU_FROM_HANDLE(tu_device
, device
, _device
);
1443 TU_FROM_HANDLE(tu_cmd_pool
, pool
, pAllocateInfo
->commandPool
);
1445 VkResult result
= VK_SUCCESS
;
1448 for (i
= 0; i
< pAllocateInfo
->commandBufferCount
; i
++) {
1450 if (!list_is_empty(&pool
->free_cmd_buffers
)) {
1451 struct tu_cmd_buffer
*cmd_buffer
= list_first_entry(
1452 &pool
->free_cmd_buffers
, struct tu_cmd_buffer
, pool_link
);
1454 list_del(&cmd_buffer
->pool_link
);
1455 list_addtail(&cmd_buffer
->pool_link
, &pool
->cmd_buffers
);
1457 result
= tu_reset_cmd_buffer(cmd_buffer
);
1458 cmd_buffer
->level
= pAllocateInfo
->level
;
1460 pCommandBuffers
[i
] = tu_cmd_buffer_to_handle(cmd_buffer
);
1462 result
= tu_create_cmd_buffer(device
, pool
, pAllocateInfo
->level
,
1463 &pCommandBuffers
[i
]);
1465 if (result
!= VK_SUCCESS
)
1469 if (result
!= VK_SUCCESS
) {
1470 tu_FreeCommandBuffers(_device
, pAllocateInfo
->commandPool
, i
,
1473 /* From the Vulkan 1.0.66 spec:
1475 * "vkAllocateCommandBuffers can be used to create multiple
1476 * command buffers. If the creation of any of those command
1477 * buffers fails, the implementation must destroy all
1478 * successfully created command buffer objects from this
1479 * command, set all entries of the pCommandBuffers array to
1480 * NULL and return the error."
1482 memset(pCommandBuffers
, 0,
1483 sizeof(*pCommandBuffers
) * pAllocateInfo
->commandBufferCount
);
1490 tu_FreeCommandBuffers(VkDevice device
,
1491 VkCommandPool commandPool
,
1492 uint32_t commandBufferCount
,
1493 const VkCommandBuffer
*pCommandBuffers
)
1495 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
1496 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, pCommandBuffers
[i
]);
1499 if (cmd_buffer
->pool
) {
1500 list_del(&cmd_buffer
->pool_link
);
1501 list_addtail(&cmd_buffer
->pool_link
,
1502 &cmd_buffer
->pool
->free_cmd_buffers
);
1504 tu_cmd_buffer_destroy(cmd_buffer
);
1510 tu_ResetCommandBuffer(VkCommandBuffer commandBuffer
,
1511 VkCommandBufferResetFlags flags
)
1513 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1514 return tu_reset_cmd_buffer(cmd_buffer
);
1517 /* Initialize the cache, assuming all necessary flushes have happened but *not*
1521 tu_cache_init(struct tu_cache_state
*cache
)
1523 cache
->flush_bits
= 0;
1524 cache
->pending_flush_bits
= TU_CMD_FLAG_ALL_INVALIDATE
;
1528 tu_BeginCommandBuffer(VkCommandBuffer commandBuffer
,
1529 const VkCommandBufferBeginInfo
*pBeginInfo
)
1531 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1532 VkResult result
= VK_SUCCESS
;
1534 if (cmd_buffer
->status
!= TU_CMD_BUFFER_STATUS_INITIAL
) {
1535 /* If the command buffer has already been resetted with
1536 * vkResetCommandBuffer, no need to do it again.
1538 result
= tu_reset_cmd_buffer(cmd_buffer
);
1539 if (result
!= VK_SUCCESS
)
1543 memset(&cmd_buffer
->state
, 0, sizeof(cmd_buffer
->state
));
1544 cmd_buffer
->state
.index_size
= 0xff; /* dirty restart index */
1546 tu_cache_init(&cmd_buffer
->state
.cache
);
1547 tu_cache_init(&cmd_buffer
->state
.renderpass_cache
);
1548 cmd_buffer
->usage_flags
= pBeginInfo
->flags
;
1550 tu_cs_begin(&cmd_buffer
->cs
);
1551 tu_cs_begin(&cmd_buffer
->draw_cs
);
1552 tu_cs_begin(&cmd_buffer
->draw_epilogue_cs
);
1554 /* setup initial configuration into command buffer */
1555 if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_PRIMARY
) {
1556 switch (cmd_buffer
->queue_family_index
) {
1557 case TU_QUEUE_GENERAL
:
1558 tu6_init_hw(cmd_buffer
, &cmd_buffer
->cs
);
1563 } else if (cmd_buffer
->level
== VK_COMMAND_BUFFER_LEVEL_SECONDARY
) {
1564 if (pBeginInfo
->flags
& VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
1565 assert(pBeginInfo
->pInheritanceInfo
);
1566 cmd_buffer
->state
.pass
= tu_render_pass_from_handle(pBeginInfo
->pInheritanceInfo
->renderPass
);
1567 cmd_buffer
->state
.subpass
=
1568 &cmd_buffer
->state
.pass
->subpasses
[pBeginInfo
->pInheritanceInfo
->subpass
];
1570 /* When executing in the middle of another command buffer, the CCU
1573 cmd_buffer
->state
.ccu_state
= TU_CMD_CCU_UNKNOWN
;
1577 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_RECORDING
;
1582 /* Sets vertex buffers to HW binding points. We emit VBs in SDS (so that bin
1583 * rendering can skip over unused state), so we need to collect all the
1584 * bindings together into a single state emit at draw time.
1587 tu_CmdBindVertexBuffers(VkCommandBuffer commandBuffer
,
1588 uint32_t firstBinding
,
1589 uint32_t bindingCount
,
1590 const VkBuffer
*pBuffers
,
1591 const VkDeviceSize
*pOffsets
)
1593 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1595 assert(firstBinding
+ bindingCount
<= MAX_VBS
);
1597 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1598 struct tu_buffer
*buf
= tu_buffer_from_handle(pBuffers
[i
]);
1600 cmd
->state
.vb
.buffers
[firstBinding
+ i
] = buf
;
1601 cmd
->state
.vb
.offsets
[firstBinding
+ i
] = pOffsets
[i
];
1603 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1606 cmd
->state
.dirty
|= TU_CMD_DIRTY_VERTEX_BUFFERS
;
1610 tu_CmdBindIndexBuffer(VkCommandBuffer commandBuffer
,
1612 VkDeviceSize offset
,
1613 VkIndexType indexType
)
1615 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1616 TU_FROM_HANDLE(tu_buffer
, buf
, buffer
);
1620 uint32_t index_size
, index_shift
, restart_index
;
1622 switch (indexType
) {
1623 case VK_INDEX_TYPE_UINT16
:
1624 index_size
= INDEX4_SIZE_16_BIT
;
1626 restart_index
= 0xffff;
1628 case VK_INDEX_TYPE_UINT32
:
1629 index_size
= INDEX4_SIZE_32_BIT
;
1631 restart_index
= 0xffffffff;
1633 case VK_INDEX_TYPE_UINT8_EXT
:
1634 index_size
= INDEX4_SIZE_8_BIT
;
1636 restart_index
= 0xff;
1639 unreachable("invalid VkIndexType");
1642 /* initialize/update the restart index */
1643 if (cmd
->state
.index_size
!= index_size
)
1644 tu_cs_emit_regs(&cmd
->draw_cs
, A6XX_PC_RESTART_INDEX(restart_index
));
1646 assert(buf
->size
>= offset
);
1648 cmd
->state
.index_va
= buf
->bo
->iova
+ buf
->bo_offset
+ offset
;
1649 cmd
->state
.max_index_count
= (buf
->size
- offset
) >> index_shift
;
1650 cmd
->state
.index_size
= index_size
;
1652 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1656 tu_CmdBindDescriptorSets(VkCommandBuffer commandBuffer
,
1657 VkPipelineBindPoint pipelineBindPoint
,
1658 VkPipelineLayout _layout
,
1660 uint32_t descriptorSetCount
,
1661 const VkDescriptorSet
*pDescriptorSets
,
1662 uint32_t dynamicOffsetCount
,
1663 const uint32_t *pDynamicOffsets
)
1665 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1666 TU_FROM_HANDLE(tu_pipeline_layout
, layout
, _layout
);
1667 unsigned dyn_idx
= 0;
1669 struct tu_descriptor_state
*descriptors_state
=
1670 tu_get_descriptors_state(cmd
, pipelineBindPoint
);
1672 for (unsigned i
= 0; i
< descriptorSetCount
; ++i
) {
1673 unsigned idx
= i
+ firstSet
;
1674 TU_FROM_HANDLE(tu_descriptor_set
, set
, pDescriptorSets
[i
]);
1676 descriptors_state
->sets
[idx
] = set
;
1678 for(unsigned j
= 0; j
< set
->layout
->dynamic_offset_count
; ++j
, ++dyn_idx
) {
1679 /* update the contents of the dynamic descriptor set */
1680 unsigned src_idx
= j
;
1681 unsigned dst_idx
= j
+ layout
->set
[idx
].dynamic_offset_start
;
1682 assert(dyn_idx
< dynamicOffsetCount
);
1685 &descriptors_state
->dynamic_descriptors
[dst_idx
* A6XX_TEX_CONST_DWORDS
];
1687 &set
->dynamic_descriptors
[src_idx
* A6XX_TEX_CONST_DWORDS
];
1688 uint32_t offset
= pDynamicOffsets
[dyn_idx
];
1690 /* Patch the storage/uniform descriptors right away. */
1691 if (layout
->set
[idx
].layout
->dynamic_ubo
& (1 << j
)) {
1692 /* Note: we can assume here that the addition won't roll over and
1693 * change the SIZE field.
1695 uint64_t va
= src
[0] | ((uint64_t)src
[1] << 32);
1700 memcpy(dst
, src
, A6XX_TEX_CONST_DWORDS
* 4);
1701 /* Note: A6XX_IBO_5_DEPTH is always 0 */
1702 uint64_t va
= dst
[4] | ((uint64_t)dst
[5] << 32);
1709 for (unsigned j
= 0; j
< set
->layout
->buffer_count
; ++j
) {
1710 if (set
->buffers
[j
]) {
1711 tu_bo_list_add(&cmd
->bo_list
, set
->buffers
[j
],
1712 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
1716 if (set
->size
> 0) {
1717 tu_bo_list_add(&cmd
->bo_list
, &set
->pool
->bo
,
1718 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1721 assert(dyn_idx
== dynamicOffsetCount
);
1723 uint32_t sp_bindless_base_reg
, hlsq_bindless_base_reg
, hlsq_invalidate_value
;
1724 uint64_t addr
[MAX_SETS
+ 1] = {};
1725 struct tu_cs
*cs
, state_cs
;
1727 for (uint32_t i
= 0; i
< MAX_SETS
; i
++) {
1728 struct tu_descriptor_set
*set
= descriptors_state
->sets
[i
];
1730 addr
[i
] = set
->va
| 3;
1733 if (layout
->dynamic_offset_count
) {
1734 /* allocate and fill out dynamic descriptor set */
1735 struct tu_cs_memory dynamic_desc_set
;
1736 VkResult result
= tu_cs_alloc(&cmd
->sub_cs
, layout
->dynamic_offset_count
,
1737 A6XX_TEX_CONST_DWORDS
, &dynamic_desc_set
);
1738 assert(result
== VK_SUCCESS
);
1740 memcpy(dynamic_desc_set
.map
, descriptors_state
->dynamic_descriptors
,
1741 layout
->dynamic_offset_count
* A6XX_TEX_CONST_DWORDS
* 4);
1742 addr
[MAX_SETS
] = dynamic_desc_set
.iova
| 3;
1745 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_GRAPHICS
) {
1746 sp_bindless_base_reg
= REG_A6XX_SP_BINDLESS_BASE(0);
1747 hlsq_bindless_base_reg
= REG_A6XX_HLSQ_BINDLESS_BASE(0);
1748 hlsq_invalidate_value
= A6XX_HLSQ_INVALIDATE_CMD_GFX_BINDLESS(0x1f);
1750 cmd
->state
.desc_sets
= tu_cs_draw_state(&cmd
->sub_cs
, &state_cs
, 24);
1751 cmd
->state
.dirty
|= TU_CMD_DIRTY_DESC_SETS_LOAD
| TU_CMD_DIRTY_SHADER_CONSTS
;
1754 assert(pipelineBindPoint
== VK_PIPELINE_BIND_POINT_COMPUTE
);
1756 sp_bindless_base_reg
= REG_A6XX_SP_CS_BINDLESS_BASE(0);
1757 hlsq_bindless_base_reg
= REG_A6XX_HLSQ_CS_BINDLESS_BASE(0);
1758 hlsq_invalidate_value
= A6XX_HLSQ_INVALIDATE_CMD_CS_BINDLESS(0x1f);
1760 cmd
->state
.dirty
|= TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD
;
1764 tu_cs_emit_pkt4(cs
, sp_bindless_base_reg
, 10);
1765 tu_cs_emit_array(cs
, (const uint32_t*) addr
, 10);
1766 tu_cs_emit_pkt4(cs
, hlsq_bindless_base_reg
, 10);
1767 tu_cs_emit_array(cs
, (const uint32_t*) addr
, 10);
1768 tu_cs_emit_regs(cs
, A6XX_HLSQ_INVALIDATE_CMD(.dword
= hlsq_invalidate_value
));
1770 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_GRAPHICS
) {
1771 assert(cs
->cur
== cs
->end
); /* validate draw state size */
1772 tu_cs_emit_pkt7(&cmd
->draw_cs
, CP_SET_DRAW_STATE
, 3);
1773 tu_cs_emit_draw_state(&cmd
->draw_cs
, TU_DRAW_STATE_DESC_SETS
, cmd
->state
.desc_sets
);
1777 void tu_CmdBindTransformFeedbackBuffersEXT(VkCommandBuffer commandBuffer
,
1778 uint32_t firstBinding
,
1779 uint32_t bindingCount
,
1780 const VkBuffer
*pBuffers
,
1781 const VkDeviceSize
*pOffsets
,
1782 const VkDeviceSize
*pSizes
)
1784 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1785 struct tu_cs
*cs
= &cmd
->draw_cs
;
1787 /* using COND_REG_EXEC for xfb commands matches the blob behavior
1788 * presumably there isn't any benefit using a draw state when the
1789 * condition is (SYSMEM | BINNING)
1791 tu_cond_exec_start(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
1792 CP_COND_REG_EXEC_0_SYSMEM
|
1793 CP_COND_REG_EXEC_0_BINNING
);
1795 for (uint32_t i
= 0; i
< bindingCount
; i
++) {
1796 TU_FROM_HANDLE(tu_buffer
, buf
, pBuffers
[i
]);
1797 uint64_t iova
= buf
->bo
->iova
+ pOffsets
[i
];
1798 uint32_t size
= buf
->bo
->size
- pOffsets
[i
];
1799 uint32_t idx
= i
+ firstBinding
;
1801 if (pSizes
&& pSizes
[i
] != VK_WHOLE_SIZE
)
1804 /* BUFFER_BASE is 32-byte aligned, add remaining offset to BUFFER_OFFSET */
1805 uint32_t offset
= iova
& 0x1f;
1806 iova
&= ~(uint64_t) 0x1f;
1808 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_SO_BUFFER_BASE(idx
), 3);
1809 tu_cs_emit_qw(cs
, iova
);
1810 tu_cs_emit(cs
, size
+ offset
);
1812 cmd
->state
.streamout_offset
[idx
] = offset
;
1814 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_WRITE
);
1817 tu_cond_exec_end(cs
);
1821 tu_CmdBeginTransformFeedbackEXT(VkCommandBuffer commandBuffer
,
1822 uint32_t firstCounterBuffer
,
1823 uint32_t counterBufferCount
,
1824 const VkBuffer
*pCounterBuffers
,
1825 const VkDeviceSize
*pCounterBufferOffsets
)
1827 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1828 struct tu_cs
*cs
= &cmd
->draw_cs
;
1830 tu_cond_exec_start(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
1831 CP_COND_REG_EXEC_0_SYSMEM
|
1832 CP_COND_REG_EXEC_0_BINNING
);
1834 /* TODO: only update offset for active buffers */
1835 for (uint32_t i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++)
1836 tu_cs_emit_regs(cs
, A6XX_VPC_SO_BUFFER_OFFSET(i
, cmd
->state
.streamout_offset
[i
]));
1838 for (uint32_t i
= 0; i
< counterBufferCount
; i
++) {
1839 uint32_t idx
= firstCounterBuffer
+ i
;
1840 uint32_t offset
= cmd
->state
.streamout_offset
[idx
];
1842 if (!pCounterBuffers
[i
])
1845 TU_FROM_HANDLE(tu_buffer
, buf
, pCounterBuffers
[i
]);
1847 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
1849 tu_cs_emit_pkt7(cs
, CP_MEM_TO_REG
, 3);
1850 tu_cs_emit(cs
, CP_MEM_TO_REG_0_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(idx
)) |
1851 CP_MEM_TO_REG_0_UNK31
|
1852 CP_MEM_TO_REG_0_CNT(1));
1853 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ pCounterBufferOffsets
[i
]);
1856 tu_cs_emit_pkt7(cs
, CP_REG_RMW
, 3);
1857 tu_cs_emit(cs
, CP_REG_RMW_0_DST_REG(REG_A6XX_VPC_SO_BUFFER_OFFSET(idx
)) |
1858 CP_REG_RMW_0_SRC1_ADD
);
1859 tu_cs_emit_qw(cs
, 0xffffffff);
1860 tu_cs_emit_qw(cs
, offset
);
1864 tu_cond_exec_end(cs
);
1867 void tu_CmdEndTransformFeedbackEXT(VkCommandBuffer commandBuffer
,
1868 uint32_t firstCounterBuffer
,
1869 uint32_t counterBufferCount
,
1870 const VkBuffer
*pCounterBuffers
,
1871 const VkDeviceSize
*pCounterBufferOffsets
)
1873 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1874 struct tu_cs
*cs
= &cmd
->draw_cs
;
1876 tu_cond_exec_start(cs
, CP_COND_REG_EXEC_0_MODE(RENDER_MODE
) |
1877 CP_COND_REG_EXEC_0_SYSMEM
|
1878 CP_COND_REG_EXEC_0_BINNING
);
1880 /* TODO: only flush buffers that need to be flushed */
1881 for (uint32_t i
= 0; i
< IR3_MAX_SO_BUFFERS
; i
++) {
1882 /* note: FLUSH_BASE is always the same, so it could go in init_hw()? */
1883 tu_cs_emit_pkt4(cs
, REG_A6XX_VPC_SO_FLUSH_BASE(i
), 2);
1884 tu_cs_emit_qw(cs
, global_iova(cmd
, flush_base
[i
]));
1885 tu6_emit_event_write(cmd
, cs
, FLUSH_SO_0
+ i
);
1888 for (uint32_t i
= 0; i
< counterBufferCount
; i
++) {
1889 uint32_t idx
= firstCounterBuffer
+ i
;
1890 uint32_t offset
= cmd
->state
.streamout_offset
[idx
];
1892 if (!pCounterBuffers
[i
])
1895 TU_FROM_HANDLE(tu_buffer
, buf
, pCounterBuffers
[i
]);
1897 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_WRITE
);
1899 /* VPC_SO_FLUSH_BASE has dwords counter, but counter should be in bytes */
1900 tu_cs_emit_pkt7(cs
, CP_MEM_TO_REG
, 3);
1901 tu_cs_emit(cs
, CP_MEM_TO_REG_0_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
1902 CP_MEM_TO_REG_0_SHIFT_BY_2
|
1904 CP_MEM_TO_REG_0_UNK31
|
1905 CP_MEM_TO_REG_0_CNT(1));
1906 tu_cs_emit_qw(cs
, global_iova(cmd
, flush_base
[idx
]));
1909 tu_cs_emit_pkt7(cs
, CP_REG_RMW
, 3);
1910 tu_cs_emit(cs
, CP_REG_RMW_0_DST_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
1911 CP_REG_RMW_0_SRC1_ADD
);
1912 tu_cs_emit_qw(cs
, 0xffffffff);
1913 tu_cs_emit_qw(cs
, -offset
);
1916 tu_cs_emit_pkt7(cs
, CP_REG_TO_MEM
, 3);
1917 tu_cs_emit(cs
, CP_REG_TO_MEM_0_REG(REG_A6XX_CP_SCRATCH_REG(0)) |
1918 CP_REG_TO_MEM_0_CNT(1));
1919 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ pCounterBufferOffsets
[i
]);
1922 tu_cond_exec_end(cs
);
1924 cmd
->state
.xfb_used
= true;
1928 tu_CmdPushConstants(VkCommandBuffer commandBuffer
,
1929 VkPipelineLayout layout
,
1930 VkShaderStageFlags stageFlags
,
1933 const void *pValues
)
1935 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
1936 memcpy((void*) cmd
->push_constants
+ offset
, pValues
, size
);
1937 cmd
->state
.dirty
|= TU_CMD_DIRTY_SHADER_CONSTS
;
1940 /* Flush everything which has been made available but we haven't actually
1944 tu_flush_all_pending(struct tu_cache_state
*cache
)
1946 cache
->flush_bits
|= cache
->pending_flush_bits
& TU_CMD_FLAG_ALL_FLUSH
;
1947 cache
->pending_flush_bits
&= ~TU_CMD_FLAG_ALL_FLUSH
;
1951 tu_EndCommandBuffer(VkCommandBuffer commandBuffer
)
1953 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
1955 /* We currently flush CCU at the end of the command buffer, like
1956 * what the blob does. There's implicit synchronization around every
1957 * vkQueueSubmit, but the kernel only flushes the UCHE, and we don't
1958 * know yet if this command buffer will be the last in the submit so we
1959 * have to defensively flush everything else.
1961 * TODO: We could definitely do better than this, since these flushes
1962 * aren't required by Vulkan, but we'd need kernel support to do that.
1963 * Ideally, we'd like the kernel to flush everything afterwards, so that we
1964 * wouldn't have to do any flushes here, and when submitting multiple
1965 * command buffers there wouldn't be any unnecessary flushes in between.
1967 if (cmd_buffer
->state
.pass
) {
1968 tu_flush_all_pending(&cmd_buffer
->state
.renderpass_cache
);
1969 tu_emit_cache_flush_renderpass(cmd_buffer
, &cmd_buffer
->draw_cs
);
1971 tu_flush_all_pending(&cmd_buffer
->state
.cache
);
1972 cmd_buffer
->state
.cache
.flush_bits
|=
1973 TU_CMD_FLAG_CCU_FLUSH_COLOR
|
1974 TU_CMD_FLAG_CCU_FLUSH_DEPTH
;
1975 tu_emit_cache_flush(cmd_buffer
, &cmd_buffer
->cs
);
1978 tu_bo_list_add(&cmd_buffer
->bo_list
, &cmd_buffer
->device
->global_bo
,
1979 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
1981 for (uint32_t i
= 0; i
< cmd_buffer
->draw_cs
.bo_count
; i
++) {
1982 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_cs
.bos
[i
],
1983 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1986 for (uint32_t i
= 0; i
< cmd_buffer
->draw_epilogue_cs
.bo_count
; i
++) {
1987 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->draw_epilogue_cs
.bos
[i
],
1988 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1991 for (uint32_t i
= 0; i
< cmd_buffer
->sub_cs
.bo_count
; i
++) {
1992 tu_bo_list_add(&cmd_buffer
->bo_list
, cmd_buffer
->sub_cs
.bos
[i
],
1993 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
1996 tu_cs_end(&cmd_buffer
->cs
);
1997 tu_cs_end(&cmd_buffer
->draw_cs
);
1998 tu_cs_end(&cmd_buffer
->draw_epilogue_cs
);
2000 cmd_buffer
->status
= TU_CMD_BUFFER_STATUS_EXECUTABLE
;
2002 return cmd_buffer
->record_result
;
2006 tu_cmd_dynamic_state(struct tu_cmd_buffer
*cmd
, uint32_t id
, uint32_t size
)
2010 assert(id
< ARRAY_SIZE(cmd
->state
.dynamic_state
));
2011 cmd
->state
.dynamic_state
[id
] = tu_cs_draw_state(&cmd
->sub_cs
, &cs
, size
);
2013 tu_cs_emit_pkt7(&cmd
->draw_cs
, CP_SET_DRAW_STATE
, 3);
2014 tu_cs_emit_draw_state(&cmd
->draw_cs
, TU_DRAW_STATE_DYNAMIC
+ id
, cmd
->state
.dynamic_state
[id
]);
2020 tu_CmdBindPipeline(VkCommandBuffer commandBuffer
,
2021 VkPipelineBindPoint pipelineBindPoint
,
2022 VkPipeline _pipeline
)
2024 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2025 TU_FROM_HANDLE(tu_pipeline
, pipeline
, _pipeline
);
2027 for (uint32_t i
= 0; i
< pipeline
->cs
.bo_count
; i
++) {
2028 tu_bo_list_add(&cmd
->bo_list
, pipeline
->cs
.bos
[i
],
2029 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2032 if (pipelineBindPoint
== VK_PIPELINE_BIND_POINT_COMPUTE
) {
2033 cmd
->state
.compute_pipeline
= pipeline
;
2034 tu_cs_emit_state_ib(&cmd
->cs
, pipeline
->program
.state
);
2038 assert(pipelineBindPoint
== VK_PIPELINE_BIND_POINT_GRAPHICS
);
2040 cmd
->state
.pipeline
= pipeline
;
2041 cmd
->state
.dirty
|= TU_CMD_DIRTY_DESC_SETS_LOAD
| TU_CMD_DIRTY_SHADER_CONSTS
;
2043 struct tu_cs
*cs
= &cmd
->draw_cs
;
2044 uint32_t mask
= ~pipeline
->dynamic_state_mask
& BITFIELD_MASK(TU_DYNAMIC_STATE_COUNT
);
2047 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * (7 + util_bitcount(mask
)));
2048 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_PROGRAM
, pipeline
->program
.state
);
2049 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_PROGRAM_BINNING
, pipeline
->program
.binning_state
);
2050 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VI
, pipeline
->vi
.state
);
2051 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VI_BINNING
, pipeline
->vi
.binning_state
);
2052 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_RAST
, pipeline
->rast_state
);
2053 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DS
, pipeline
->ds_state
);
2054 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_BLEND
, pipeline
->blend_state
);
2055 for_each_bit(i
, mask
)
2056 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DYNAMIC
+ i
, pipeline
->dynamic_state
[i
]);
2058 /* If the new pipeline requires more VBs than we had previously set up, we
2059 * need to re-emit them in SDS. If it requires the same set or fewer, we
2060 * can just re-use the old SDS.
2062 if (pipeline
->vi
.bindings_used
& ~cmd
->vertex_bindings_set
)
2063 cmd
->state
.dirty
|= TU_CMD_DIRTY_VERTEX_BUFFERS
;
2065 /* dynamic linewidth state depends pipeline state's gras_su_cntl
2066 * so the dynamic state ib must be updated when pipeline changes
2068 if (pipeline
->dynamic_state_mask
& BIT(VK_DYNAMIC_STATE_LINE_WIDTH
)) {
2069 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_LINE_WIDTH
, 2);
2071 cmd
->state
.dynamic_gras_su_cntl
&= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK
;
2072 cmd
->state
.dynamic_gras_su_cntl
|= pipeline
->gras_su_cntl
;
2074 tu_cs_emit_regs(&cs
, A6XX_GRAS_SU_CNTL(.dword
= cmd
->state
.dynamic_gras_su_cntl
));
2079 tu_CmdSetViewport(VkCommandBuffer commandBuffer
,
2080 uint32_t firstViewport
,
2081 uint32_t viewportCount
,
2082 const VkViewport
*pViewports
)
2084 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2085 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_VIEWPORT
, 18);
2087 assert(firstViewport
== 0 && viewportCount
== 1);
2089 tu6_emit_viewport(&cs
, pViewports
);
2093 tu_CmdSetScissor(VkCommandBuffer commandBuffer
,
2094 uint32_t firstScissor
,
2095 uint32_t scissorCount
,
2096 const VkRect2D
*pScissors
)
2098 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2099 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_SCISSOR
, 3);
2101 assert(firstScissor
== 0 && scissorCount
== 1);
2103 tu6_emit_scissor(&cs
, pScissors
);
2107 tu_CmdSetLineWidth(VkCommandBuffer commandBuffer
, float lineWidth
)
2109 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2110 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_LINE_WIDTH
, 2);
2112 cmd
->state
.dynamic_gras_su_cntl
&= ~A6XX_GRAS_SU_CNTL_LINEHALFWIDTH__MASK
;
2113 cmd
->state
.dynamic_gras_su_cntl
|= A6XX_GRAS_SU_CNTL_LINEHALFWIDTH(lineWidth
/ 2.0f
);
2115 tu_cs_emit_regs(&cs
, A6XX_GRAS_SU_CNTL(.dword
= cmd
->state
.dynamic_gras_su_cntl
));
2119 tu_CmdSetDepthBias(VkCommandBuffer commandBuffer
,
2120 float depthBiasConstantFactor
,
2121 float depthBiasClamp
,
2122 float depthBiasSlopeFactor
)
2124 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2125 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_DEPTH_BIAS
, 4);
2127 tu6_emit_depth_bias(&cs
, depthBiasConstantFactor
, depthBiasClamp
, depthBiasSlopeFactor
);
2131 tu_CmdSetBlendConstants(VkCommandBuffer commandBuffer
,
2132 const float blendConstants
[4])
2134 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2135 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_BLEND_CONSTANTS
, 5);
2137 tu_cs_emit_pkt4(&cs
, REG_A6XX_RB_BLEND_RED_F32
, 4);
2138 tu_cs_emit_array(&cs
, (const uint32_t *) blendConstants
, 4);
2142 tu_CmdSetDepthBounds(VkCommandBuffer commandBuffer
,
2143 float minDepthBounds
,
2144 float maxDepthBounds
)
2146 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2147 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_DEPTH_BOUNDS
, 3);
2149 tu_cs_emit_regs(&cs
,
2150 A6XX_RB_Z_BOUNDS_MIN(minDepthBounds
),
2151 A6XX_RB_Z_BOUNDS_MAX(maxDepthBounds
));
2155 update_stencil_mask(uint32_t *value
, VkStencilFaceFlags face
, uint32_t mask
)
2157 if (face
& VK_STENCIL_FACE_FRONT_BIT
)
2158 *value
= (*value
& 0xff00) | (mask
& 0xff);
2159 if (face
& VK_STENCIL_FACE_BACK_BIT
)
2160 *value
= (*value
& 0xff) | (mask
& 0xff) << 8;
2164 tu_CmdSetStencilCompareMask(VkCommandBuffer commandBuffer
,
2165 VkStencilFaceFlags faceMask
,
2166 uint32_t compareMask
)
2168 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2169 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
, 2);
2171 update_stencil_mask(&cmd
->state
.dynamic_stencil_mask
, faceMask
, compareMask
);
2173 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILMASK(.dword
= cmd
->state
.dynamic_stencil_mask
));
2177 tu_CmdSetStencilWriteMask(VkCommandBuffer commandBuffer
,
2178 VkStencilFaceFlags faceMask
,
2181 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2182 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
, 2);
2184 update_stencil_mask(&cmd
->state
.dynamic_stencil_wrmask
, faceMask
, writeMask
);
2186 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILWRMASK(.dword
= cmd
->state
.dynamic_stencil_wrmask
));
2190 tu_CmdSetStencilReference(VkCommandBuffer commandBuffer
,
2191 VkStencilFaceFlags faceMask
,
2194 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2195 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, VK_DYNAMIC_STATE_STENCIL_REFERENCE
, 2);
2197 update_stencil_mask(&cmd
->state
.dynamic_stencil_ref
, faceMask
, reference
);
2199 tu_cs_emit_regs(&cs
, A6XX_RB_STENCILREF(.dword
= cmd
->state
.dynamic_stencil_ref
));
2203 tu_CmdSetSampleLocationsEXT(VkCommandBuffer commandBuffer
,
2204 const VkSampleLocationsInfoEXT
* pSampleLocationsInfo
)
2206 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2207 struct tu_cs cs
= tu_cmd_dynamic_state(cmd
, TU_DYNAMIC_STATE_SAMPLE_LOCATIONS
, 9);
2209 assert(pSampleLocationsInfo
);
2211 tu6_emit_sample_locations(&cs
, pSampleLocationsInfo
);
2215 tu_flush_for_access(struct tu_cache_state
*cache
,
2216 enum tu_cmd_access_mask src_mask
,
2217 enum tu_cmd_access_mask dst_mask
)
2219 enum tu_cmd_flush_bits flush_bits
= 0;
2221 if (src_mask
& TU_ACCESS_HOST_WRITE
) {
2222 /* Host writes are always visible to CP, so only invalidate GPU caches */
2223 cache
->pending_flush_bits
|= TU_CMD_FLAG_GPU_INVALIDATE
;
2226 if (src_mask
& TU_ACCESS_SYSMEM_WRITE
) {
2227 /* Invalidate CP and 2D engine (make it do WFI + WFM if necessary) as
2230 cache
->pending_flush_bits
|= TU_CMD_FLAG_ALL_INVALIDATE
;
2233 if (src_mask
& TU_ACCESS_CP_WRITE
) {
2234 /* Flush the CP write queue. However a WFI shouldn't be necessary as
2235 * WAIT_MEM_WRITES should cover it.
2237 cache
->pending_flush_bits
|=
2238 TU_CMD_FLAG_WAIT_MEM_WRITES
|
2239 TU_CMD_FLAG_GPU_INVALIDATE
|
2240 TU_CMD_FLAG_WAIT_FOR_ME
;
2243 #define SRC_FLUSH(domain, flush, invalidate) \
2244 if (src_mask & TU_ACCESS_##domain##_WRITE) { \
2245 cache->pending_flush_bits |= TU_CMD_FLAG_##flush | \
2246 (TU_CMD_FLAG_ALL_INVALIDATE & ~TU_CMD_FLAG_##invalidate); \
2249 SRC_FLUSH(UCHE
, CACHE_FLUSH
, CACHE_INVALIDATE
)
2250 SRC_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2251 SRC_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2255 #define SRC_INCOHERENT_FLUSH(domain, flush, invalidate) \
2256 if (src_mask & TU_ACCESS_##domain##_INCOHERENT_WRITE) { \
2257 flush_bits |= TU_CMD_FLAG_##flush; \
2258 cache->pending_flush_bits |= \
2259 (TU_CMD_FLAG_ALL_INVALIDATE & ~TU_CMD_FLAG_##invalidate); \
2262 SRC_INCOHERENT_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2263 SRC_INCOHERENT_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2265 #undef SRC_INCOHERENT_FLUSH
2267 /* Treat host & sysmem write accesses the same, since the kernel implicitly
2268 * drains the queue before signalling completion to the host.
2270 if (dst_mask
& (TU_ACCESS_SYSMEM_READ
| TU_ACCESS_SYSMEM_WRITE
|
2271 TU_ACCESS_HOST_READ
| TU_ACCESS_HOST_WRITE
)) {
2272 flush_bits
|= cache
->pending_flush_bits
& TU_CMD_FLAG_ALL_FLUSH
;
2275 #define DST_FLUSH(domain, flush, invalidate) \
2276 if (dst_mask & (TU_ACCESS_##domain##_READ | \
2277 TU_ACCESS_##domain##_WRITE)) { \
2278 flush_bits |= cache->pending_flush_bits & \
2279 (TU_CMD_FLAG_##invalidate | \
2280 (TU_CMD_FLAG_ALL_FLUSH & ~TU_CMD_FLAG_##flush)); \
2283 DST_FLUSH(UCHE
, CACHE_FLUSH
, CACHE_INVALIDATE
)
2284 DST_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2285 DST_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2289 #define DST_INCOHERENT_FLUSH(domain, flush, invalidate) \
2290 if (dst_mask & (TU_ACCESS_##domain##_READ | \
2291 TU_ACCESS_##domain##_WRITE)) { \
2292 flush_bits |= TU_CMD_FLAG_##invalidate | \
2293 (cache->pending_flush_bits & \
2294 (TU_CMD_FLAG_ALL_FLUSH & ~TU_CMD_FLAG_##flush)); \
2297 DST_INCOHERENT_FLUSH(CCU_COLOR
, CCU_FLUSH_COLOR
, CCU_INVALIDATE_COLOR
)
2298 DST_INCOHERENT_FLUSH(CCU_DEPTH
, CCU_FLUSH_DEPTH
, CCU_INVALIDATE_DEPTH
)
2300 #undef DST_INCOHERENT_FLUSH
2302 if (dst_mask
& TU_ACCESS_WFI_READ
) {
2303 flush_bits
|= cache
->pending_flush_bits
&
2304 (TU_CMD_FLAG_ALL_FLUSH
| TU_CMD_FLAG_WAIT_FOR_IDLE
);
2307 if (dst_mask
& TU_ACCESS_WFM_READ
) {
2308 flush_bits
|= cache
->pending_flush_bits
&
2309 (TU_CMD_FLAG_ALL_FLUSH
| TU_CMD_FLAG_WAIT_FOR_ME
);
2312 cache
->flush_bits
|= flush_bits
;
2313 cache
->pending_flush_bits
&= ~flush_bits
;
2316 static enum tu_cmd_access_mask
2317 vk2tu_access(VkAccessFlags flags
, bool gmem
)
2319 enum tu_cmd_access_mask mask
= 0;
2321 /* If the GPU writes a buffer that is then read by an indirect draw
2322 * command, we theoretically need to emit a WFI to wait for any cache
2323 * flushes, and then a WAIT_FOR_ME to wait on the CP for the WFI to
2324 * complete. Waiting for the WFI to complete is performed as part of the
2325 * draw by the firmware, so we just need to execute the WFI.
2327 * Transform feedback counters are read via CP_MEM_TO_REG, which implicitly
2328 * does CP_WAIT_FOR_ME, but we still need a WFI if the GPU writes it.
2331 (VK_ACCESS_INDIRECT_COMMAND_READ_BIT
|
2332 VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT
|
2333 VK_ACCESS_MEMORY_READ_BIT
)) {
2334 mask
|= TU_ACCESS_WFI_READ
;
2338 (VK_ACCESS_INDIRECT_COMMAND_READ_BIT
| /* Read performed by CP */
2339 VK_ACCESS_CONDITIONAL_RENDERING_READ_BIT_EXT
| /* Read performed by CP */
2340 VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_READ_BIT_EXT
| /* Read performed by CP */
2341 VK_ACCESS_MEMORY_READ_BIT
)) {
2342 mask
|= TU_ACCESS_SYSMEM_READ
;
2346 (VK_ACCESS_TRANSFORM_FEEDBACK_COUNTER_WRITE_BIT_EXT
|
2347 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2348 mask
|= TU_ACCESS_CP_WRITE
;
2352 (VK_ACCESS_HOST_READ_BIT
|
2353 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2354 mask
|= TU_ACCESS_HOST_READ
;
2358 (VK_ACCESS_HOST_WRITE_BIT
|
2359 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2360 mask
|= TU_ACCESS_HOST_WRITE
;
2364 (VK_ACCESS_INDEX_READ_BIT
| /* Read performed by PC, I think */
2365 VK_ACCESS_VERTEX_ATTRIBUTE_READ_BIT
| /* Read performed by VFD */
2366 VK_ACCESS_UNIFORM_READ_BIT
| /* Read performed by SP */
2367 /* TODO: Is there a no-cache bit for textures so that we can ignore
2370 VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
| /* Read performed by TP */
2371 VK_ACCESS_SHADER_READ_BIT
| /* Read perfomed by SP/TP */
2372 VK_ACCESS_MEMORY_READ_BIT
)) {
2373 mask
|= TU_ACCESS_UCHE_READ
;
2377 (VK_ACCESS_SHADER_WRITE_BIT
| /* Write performed by SP */
2378 VK_ACCESS_TRANSFORM_FEEDBACK_WRITE_BIT_EXT
| /* Write performed by VPC */
2379 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2380 mask
|= TU_ACCESS_UCHE_WRITE
;
2383 /* When using GMEM, the CCU is always flushed automatically to GMEM, and
2384 * then GMEM is flushed to sysmem. Furthermore, we already had to flush any
2385 * previous writes in sysmem mode when transitioning to GMEM. Therefore we
2386 * can ignore CCU and pretend that color attachments and transfers use
2391 (VK_ACCESS_COLOR_ATTACHMENT_READ_BIT
|
2392 VK_ACCESS_COLOR_ATTACHMENT_READ_NONCOHERENT_BIT_EXT
|
2393 VK_ACCESS_MEMORY_READ_BIT
)) {
2395 mask
|= TU_ACCESS_SYSMEM_READ
;
2397 mask
|= TU_ACCESS_CCU_COLOR_INCOHERENT_READ
;
2401 (VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_READ_BIT
|
2402 VK_ACCESS_MEMORY_READ_BIT
)) {
2404 mask
|= TU_ACCESS_SYSMEM_READ
;
2406 mask
|= TU_ACCESS_CCU_DEPTH_INCOHERENT_READ
;
2410 (VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
|
2411 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2413 mask
|= TU_ACCESS_SYSMEM_WRITE
;
2415 mask
|= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
;
2420 (VK_ACCESS_DEPTH_STENCIL_ATTACHMENT_WRITE_BIT
|
2421 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2423 mask
|= TU_ACCESS_SYSMEM_WRITE
;
2425 mask
|= TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE
;
2429 /* When the dst access is a transfer read/write, it seems we sometimes need
2430 * to insert a WFI after any flushes, to guarantee that the flushes finish
2431 * before the 2D engine starts. However the opposite (i.e. a WFI after
2432 * CP_BLIT and before any subsequent flush) does not seem to be needed, and
2433 * the blob doesn't emit such a WFI.
2437 (VK_ACCESS_TRANSFER_WRITE_BIT
|
2438 VK_ACCESS_MEMORY_WRITE_BIT
)) {
2440 mask
|= TU_ACCESS_SYSMEM_WRITE
;
2442 mask
|= TU_ACCESS_CCU_COLOR_WRITE
;
2444 mask
|= TU_ACCESS_WFI_READ
;
2448 (VK_ACCESS_TRANSFER_READ_BIT
| /* Access performed by TP */
2449 VK_ACCESS_MEMORY_READ_BIT
)) {
2450 mask
|= TU_ACCESS_UCHE_READ
| TU_ACCESS_WFI_READ
;
2458 tu_CmdExecuteCommands(VkCommandBuffer commandBuffer
,
2459 uint32_t commandBufferCount
,
2460 const VkCommandBuffer
*pCmdBuffers
)
2462 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2465 assert(commandBufferCount
> 0);
2467 /* Emit any pending flushes. */
2468 if (cmd
->state
.pass
) {
2469 tu_flush_all_pending(&cmd
->state
.renderpass_cache
);
2470 tu_emit_cache_flush_renderpass(cmd
, &cmd
->draw_cs
);
2472 tu_flush_all_pending(&cmd
->state
.cache
);
2473 tu_emit_cache_flush(cmd
, &cmd
->cs
);
2476 for (uint32_t i
= 0; i
< commandBufferCount
; i
++) {
2477 TU_FROM_HANDLE(tu_cmd_buffer
, secondary
, pCmdBuffers
[i
]);
2479 result
= tu_bo_list_merge(&cmd
->bo_list
, &secondary
->bo_list
);
2480 if (result
!= VK_SUCCESS
) {
2481 cmd
->record_result
= result
;
2485 if (secondary
->usage_flags
&
2486 VK_COMMAND_BUFFER_USAGE_RENDER_PASS_CONTINUE_BIT
) {
2487 assert(tu_cs_is_empty(&secondary
->cs
));
2489 result
= tu_cs_add_entries(&cmd
->draw_cs
, &secondary
->draw_cs
);
2490 if (result
!= VK_SUCCESS
) {
2491 cmd
->record_result
= result
;
2495 result
= tu_cs_add_entries(&cmd
->draw_epilogue_cs
,
2496 &secondary
->draw_epilogue_cs
);
2497 if (result
!= VK_SUCCESS
) {
2498 cmd
->record_result
= result
;
2502 if (secondary
->has_tess
)
2503 cmd
->has_tess
= true;
2505 assert(tu_cs_is_empty(&secondary
->draw_cs
));
2506 assert(tu_cs_is_empty(&secondary
->draw_epilogue_cs
));
2508 for (uint32_t j
= 0; j
< secondary
->cs
.bo_count
; j
++) {
2509 tu_bo_list_add(&cmd
->bo_list
, secondary
->cs
.bos
[j
],
2510 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
2513 tu_cs_add_entries(&cmd
->cs
, &secondary
->cs
);
2516 cmd
->state
.index_size
= secondary
->state
.index_size
; /* for restart index update */
2518 cmd
->state
.dirty
= ~0u; /* TODO: set dirty only what needs to be */
2520 /* After executing secondary command buffers, there may have been arbitrary
2521 * flushes executed, so when we encounter a pipeline barrier with a
2522 * srcMask, we have to assume that we need to invalidate. Therefore we need
2523 * to re-initialize the cache with all pending invalidate bits set.
2525 if (cmd
->state
.pass
) {
2526 tu_cache_init(&cmd
->state
.renderpass_cache
);
2528 tu_cache_init(&cmd
->state
.cache
);
2533 tu_CreateCommandPool(VkDevice _device
,
2534 const VkCommandPoolCreateInfo
*pCreateInfo
,
2535 const VkAllocationCallbacks
*pAllocator
,
2536 VkCommandPool
*pCmdPool
)
2538 TU_FROM_HANDLE(tu_device
, device
, _device
);
2539 struct tu_cmd_pool
*pool
;
2541 pool
= vk_object_alloc(&device
->vk
, pAllocator
, sizeof(*pool
),
2542 VK_OBJECT_TYPE_COMMAND_POOL
);
2544 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
2547 pool
->alloc
= *pAllocator
;
2549 pool
->alloc
= device
->vk
.alloc
;
2551 list_inithead(&pool
->cmd_buffers
);
2552 list_inithead(&pool
->free_cmd_buffers
);
2554 pool
->queue_family_index
= pCreateInfo
->queueFamilyIndex
;
2556 *pCmdPool
= tu_cmd_pool_to_handle(pool
);
2562 tu_DestroyCommandPool(VkDevice _device
,
2563 VkCommandPool commandPool
,
2564 const VkAllocationCallbacks
*pAllocator
)
2566 TU_FROM_HANDLE(tu_device
, device
, _device
);
2567 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2572 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2573 &pool
->cmd_buffers
, pool_link
)
2575 tu_cmd_buffer_destroy(cmd_buffer
);
2578 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2579 &pool
->free_cmd_buffers
, pool_link
)
2581 tu_cmd_buffer_destroy(cmd_buffer
);
2584 vk_object_free(&device
->vk
, pAllocator
, pool
);
2588 tu_ResetCommandPool(VkDevice device
,
2589 VkCommandPool commandPool
,
2590 VkCommandPoolResetFlags flags
)
2592 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2595 list_for_each_entry(struct tu_cmd_buffer
, cmd_buffer
, &pool
->cmd_buffers
,
2598 result
= tu_reset_cmd_buffer(cmd_buffer
);
2599 if (result
!= VK_SUCCESS
)
2607 tu_TrimCommandPool(VkDevice device
,
2608 VkCommandPool commandPool
,
2609 VkCommandPoolTrimFlags flags
)
2611 TU_FROM_HANDLE(tu_cmd_pool
, pool
, commandPool
);
2616 list_for_each_entry_safe(struct tu_cmd_buffer
, cmd_buffer
,
2617 &pool
->free_cmd_buffers
, pool_link
)
2619 tu_cmd_buffer_destroy(cmd_buffer
);
2624 tu_subpass_barrier(struct tu_cmd_buffer
*cmd_buffer
,
2625 const struct tu_subpass_barrier
*barrier
,
2628 /* Note: we don't know until the end of the subpass whether we'll use
2629 * sysmem, so assume sysmem here to be safe.
2631 struct tu_cache_state
*cache
=
2632 external
? &cmd_buffer
->state
.cache
: &cmd_buffer
->state
.renderpass_cache
;
2633 enum tu_cmd_access_mask src_flags
=
2634 vk2tu_access(barrier
->src_access_mask
, false);
2635 enum tu_cmd_access_mask dst_flags
=
2636 vk2tu_access(barrier
->dst_access_mask
, false);
2638 if (barrier
->incoherent_ccu_color
)
2639 src_flags
|= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
;
2640 if (barrier
->incoherent_ccu_depth
)
2641 src_flags
|= TU_ACCESS_CCU_DEPTH_INCOHERENT_WRITE
;
2643 tu_flush_for_access(cache
, src_flags
, dst_flags
);
2647 tu_CmdBeginRenderPass(VkCommandBuffer commandBuffer
,
2648 const VkRenderPassBeginInfo
*pRenderPassBegin
,
2649 VkSubpassContents contents
)
2651 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2652 TU_FROM_HANDLE(tu_render_pass
, pass
, pRenderPassBegin
->renderPass
);
2653 TU_FROM_HANDLE(tu_framebuffer
, fb
, pRenderPassBegin
->framebuffer
);
2655 cmd
->state
.pass
= pass
;
2656 cmd
->state
.subpass
= pass
->subpasses
;
2657 cmd
->state
.framebuffer
= fb
;
2658 cmd
->state
.render_area
= pRenderPassBegin
->renderArea
;
2660 tu_cmd_prepare_tile_store_ib(cmd
);
2662 /* Note: because this is external, any flushes will happen before draw_cs
2663 * gets called. However deferred flushes could have to happen later as part
2666 tu_subpass_barrier(cmd
, &pass
->subpasses
[0].start_barrier
, true);
2667 cmd
->state
.renderpass_cache
.pending_flush_bits
=
2668 cmd
->state
.cache
.pending_flush_bits
;
2669 cmd
->state
.renderpass_cache
.flush_bits
= 0;
2671 tu_emit_renderpass_begin(cmd
, pRenderPassBegin
);
2673 tu6_emit_zs(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
);
2674 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
);
2675 tu6_emit_msaa(&cmd
->draw_cs
, cmd
->state
.subpass
->samples
);
2676 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, &cmd
->draw_cs
, false);
2678 tu_set_input_attachments(cmd
, cmd
->state
.subpass
);
2680 for (uint32_t i
= 0; i
< fb
->attachment_count
; ++i
) {
2681 const struct tu_image_view
*iview
= fb
->attachments
[i
].attachment
;
2682 tu_bo_list_add(&cmd
->bo_list
, iview
->image
->bo
,
2683 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2686 cmd
->state
.dirty
|= TU_CMD_DIRTY_DRAW_STATE
;
2690 tu_CmdBeginRenderPass2(VkCommandBuffer commandBuffer
,
2691 const VkRenderPassBeginInfo
*pRenderPassBeginInfo
,
2692 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
)
2694 tu_CmdBeginRenderPass(commandBuffer
, pRenderPassBeginInfo
,
2695 pSubpassBeginInfo
->contents
);
2699 tu_CmdNextSubpass(VkCommandBuffer commandBuffer
, VkSubpassContents contents
)
2701 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
2702 const struct tu_render_pass
*pass
= cmd
->state
.pass
;
2703 struct tu_cs
*cs
= &cmd
->draw_cs
;
2705 const struct tu_subpass
*subpass
= cmd
->state
.subpass
++;
2707 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_GMEM
);
2709 if (subpass
->resolve_attachments
) {
2710 tu6_emit_blit_scissor(cmd
, cs
, true);
2712 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
2713 uint32_t a
= subpass
->resolve_attachments
[i
].attachment
;
2714 if (a
== VK_ATTACHMENT_UNUSED
)
2717 tu_store_gmem_attachment(cmd
, cs
, a
,
2718 subpass
->color_attachments
[i
].attachment
);
2720 if (pass
->attachments
[a
].gmem_offset
< 0)
2724 * check if the resolved attachment is needed by later subpasses,
2725 * if it is, should be doing a GMEM->GMEM resolve instead of GMEM->MEM->GMEM..
2727 tu_finishme("missing GMEM->GMEM resolve path\n");
2728 tu_load_gmem_attachment(cmd
, cs
, a
, true);
2732 tu_cond_exec_end(cs
);
2734 tu_cond_exec_start(cs
, CP_COND_EXEC_0_RENDER_MODE_SYSMEM
);
2736 tu6_emit_sysmem_resolves(cmd
, cs
, subpass
);
2738 tu_cond_exec_end(cs
);
2740 /* Handle dependencies for the next subpass */
2741 tu_subpass_barrier(cmd
, &cmd
->state
.subpass
->start_barrier
, false);
2743 /* emit mrt/zs/msaa/ubwc state for the subpass that is starting */
2744 tu6_emit_zs(cmd
, cmd
->state
.subpass
, cs
);
2745 tu6_emit_mrt(cmd
, cmd
->state
.subpass
, cs
);
2746 tu6_emit_msaa(cs
, cmd
->state
.subpass
->samples
);
2747 tu6_emit_render_cntl(cmd
, cmd
->state
.subpass
, cs
, false);
2749 tu_set_input_attachments(cmd
, cmd
->state
.subpass
);
2753 tu_CmdNextSubpass2(VkCommandBuffer commandBuffer
,
2754 const VkSubpassBeginInfoKHR
*pSubpassBeginInfo
,
2755 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
2757 tu_CmdNextSubpass(commandBuffer
, pSubpassBeginInfo
->contents
);
2761 tu6_emit_user_consts(struct tu_cs
*cs
, const struct tu_pipeline
*pipeline
,
2762 struct tu_descriptor_state
*descriptors_state
,
2763 gl_shader_stage type
,
2764 uint32_t *push_constants
)
2766 const struct tu_program_descriptor_linkage
*link
=
2767 &pipeline
->program
.link
[type
];
2768 const struct ir3_ubo_analysis_state
*state
= &link
->const_state
.ubo_state
;
2770 if (link
->push_consts
.count
> 0) {
2771 unsigned num_units
= link
->push_consts
.count
;
2772 unsigned offset
= link
->push_consts
.lo
;
2773 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + num_units
* 4);
2774 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
2775 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2776 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2777 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2778 CP_LOAD_STATE6_0_NUM_UNIT(num_units
));
2781 for (unsigned i
= 0; i
< num_units
* 4; i
++)
2782 tu_cs_emit(cs
, push_constants
[i
+ offset
* 4]);
2785 for (uint32_t i
= 0; i
< state
->num_enabled
; i
++) {
2786 uint32_t size
= state
->range
[i
].end
- state
->range
[i
].start
;
2787 uint32_t offset
= state
->range
[i
].start
;
2789 /* and even if the start of the const buffer is before
2790 * first_immediate, the end may not be:
2792 size
= MIN2(size
, (16 * link
->constlen
) - state
->range
[i
].offset
);
2797 /* things should be aligned to vec4: */
2798 debug_assert((state
->range
[i
].offset
% 16) == 0);
2799 debug_assert((size
% 16) == 0);
2800 debug_assert((offset
% 16) == 0);
2802 /* Dig out the descriptor from the descriptor state and read the VA from
2805 assert(state
->range
[i
].ubo
.bindless
);
2806 uint32_t *base
= state
->range
[i
].ubo
.bindless_base
== MAX_SETS
?
2807 descriptors_state
->dynamic_descriptors
:
2808 descriptors_state
->sets
[state
->range
[i
].ubo
.bindless_base
]->mapped_ptr
;
2809 unsigned block
= state
->range
[i
].ubo
.block
;
2810 uint32_t *desc
= base
+ block
* A6XX_TEX_CONST_DWORDS
;
2811 uint64_t va
= desc
[0] | ((uint64_t)(desc
[1] & A6XX_UBO_1_BASE_HI__MASK
) << 32);
2814 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3);
2815 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(state
->range
[i
].offset
/ 16) |
2816 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2817 CP_LOAD_STATE6_0_STATE_SRC(SS6_INDIRECT
) |
2818 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
2819 CP_LOAD_STATE6_0_NUM_UNIT(size
/ 16));
2820 tu_cs_emit_qw(cs
, va
+ offset
);
2824 static struct tu_draw_state
2825 tu6_emit_consts(struct tu_cmd_buffer
*cmd
,
2826 const struct tu_pipeline
*pipeline
,
2827 struct tu_descriptor_state
*descriptors_state
,
2828 gl_shader_stage type
)
2831 tu_cs_begin_sub_stream(&cmd
->sub_cs
, 512, &cs
); /* TODO: maximum size? */
2833 tu6_emit_user_consts(&cs
, pipeline
, descriptors_state
, type
, cmd
->push_constants
);
2835 return tu_cs_end_draw_state(&cmd
->sub_cs
, &cs
);
2838 static struct tu_draw_state
2839 tu6_emit_vertex_buffers(struct tu_cmd_buffer
*cmd
,
2840 const struct tu_pipeline
*pipeline
)
2843 tu_cs_begin_sub_stream(&cmd
->sub_cs
, 4 * MAX_VBS
, &cs
);
2846 for_each_bit(binding
, pipeline
->vi
.bindings_used
) {
2847 const struct tu_buffer
*buf
= cmd
->state
.vb
.buffers
[binding
];
2848 const VkDeviceSize offset
= buf
->bo_offset
+
2849 cmd
->state
.vb
.offsets
[binding
];
2851 tu_cs_emit_regs(&cs
,
2852 A6XX_VFD_FETCH_BASE(binding
, .bo
= buf
->bo
, .bo_offset
= offset
),
2853 A6XX_VFD_FETCH_SIZE(binding
, buf
->size
- offset
));
2857 cmd
->vertex_bindings_set
= pipeline
->vi
.bindings_used
;
2859 return tu_cs_end_draw_state(&cmd
->sub_cs
, &cs
);
2863 get_tess_param_bo_size(const struct tu_pipeline
*pipeline
,
2864 uint32_t draw_count
)
2866 /* TODO: For indirect draws, we can't compute the BO size ahead of time.
2867 * Still not sure what to do here, so just allocate a reasonably large
2868 * BO and hope for the best for now. */
2872 /* the tess param BO is pipeline->tess.param_stride bytes per patch,
2873 * which includes both the per-vertex outputs and per-patch outputs
2874 * build_primitive_map in ir3 calculates this stride
2876 uint32_t verts_per_patch
= pipeline
->ia
.primtype
- DI_PT_PATCHES0
;
2877 uint32_t num_patches
= draw_count
/ verts_per_patch
;
2878 return num_patches
* pipeline
->tess
.param_stride
;
2882 get_tess_factor_bo_size(const struct tu_pipeline
*pipeline
,
2883 uint32_t draw_count
)
2885 /* TODO: For indirect draws, we can't compute the BO size ahead of time.
2886 * Still not sure what to do here, so just allocate a reasonably large
2887 * BO and hope for the best for now. */
2891 /* Each distinct patch gets its own tess factor output. */
2892 uint32_t verts_per_patch
= pipeline
->ia
.primtype
- DI_PT_PATCHES0
;
2893 uint32_t num_patches
= draw_count
/ verts_per_patch
;
2894 uint32_t factor_stride
;
2895 switch (pipeline
->tess
.patch_type
) {
2896 case IR3_TESS_ISOLINES
:
2899 case IR3_TESS_TRIANGLES
:
2902 case IR3_TESS_QUADS
:
2906 unreachable("bad tessmode");
2908 return factor_stride
* num_patches
;
2912 tu6_emit_tess_consts(struct tu_cmd_buffer
*cmd
,
2913 uint32_t draw_count
,
2914 const struct tu_pipeline
*pipeline
,
2915 struct tu_draw_state
*state
,
2916 uint64_t *factor_iova
)
2919 VkResult result
= tu_cs_begin_sub_stream(&cmd
->sub_cs
, 16, &cs
);
2920 if (result
!= VK_SUCCESS
)
2923 uint64_t tess_factor_size
= get_tess_factor_bo_size(pipeline
, draw_count
);
2924 uint64_t tess_param_size
= get_tess_param_bo_size(pipeline
, draw_count
);
2925 uint64_t tess_bo_size
= tess_factor_size
+ tess_param_size
;
2926 if (tess_bo_size
> 0) {
2927 struct tu_bo
*tess_bo
;
2928 result
= tu_get_scratch_bo(cmd
->device
, tess_bo_size
, &tess_bo
);
2929 if (result
!= VK_SUCCESS
)
2932 tu_bo_list_add(&cmd
->bo_list
, tess_bo
,
2933 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
2934 uint64_t tess_factor_iova
= tess_bo
->iova
;
2935 uint64_t tess_param_iova
= tess_factor_iova
+ tess_factor_size
;
2937 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_GEOM
, 3 + 4);
2938 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(pipeline
->tess
.hs_bo_regid
) |
2939 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2940 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2941 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_HS_SHADER
) |
2942 CP_LOAD_STATE6_0_NUM_UNIT(1));
2943 tu_cs_emit(&cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2944 tu_cs_emit(&cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2945 tu_cs_emit_qw(&cs
, tess_param_iova
);
2946 tu_cs_emit_qw(&cs
, tess_factor_iova
);
2948 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_GEOM
, 3 + 4);
2949 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(pipeline
->tess
.ds_bo_regid
) |
2950 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
2951 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
2952 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_DS_SHADER
) |
2953 CP_LOAD_STATE6_0_NUM_UNIT(1));
2954 tu_cs_emit(&cs
, CP_LOAD_STATE6_1_EXT_SRC_ADDR(0));
2955 tu_cs_emit(&cs
, CP_LOAD_STATE6_2_EXT_SRC_ADDR_HI(0));
2956 tu_cs_emit_qw(&cs
, tess_param_iova
);
2957 tu_cs_emit_qw(&cs
, tess_factor_iova
);
2959 *factor_iova
= tess_factor_iova
;
2961 *state
= tu_cs_end_draw_state(&cmd
->sub_cs
, &cs
);
2966 tu6_draw_common(struct tu_cmd_buffer
*cmd
,
2969 /* note: draw_count is 0 for indirect */
2970 uint32_t draw_count
)
2972 const struct tu_pipeline
*pipeline
= cmd
->state
.pipeline
;
2975 struct tu_descriptor_state
*descriptors_state
=
2976 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_GRAPHICS
];
2978 tu_emit_cache_flush_renderpass(cmd
, cs
);
2982 tu_cs_emit_regs(cs
, A6XX_PC_PRIMITIVE_CNTL_0(
2983 .primitive_restart
=
2984 pipeline
->ia
.primitive_restart
&& indexed
,
2985 .tess_upper_left_domain_origin
=
2986 pipeline
->tess
.upper_left_domain_origin
));
2988 if (cmd
->state
.dirty
& TU_CMD_DIRTY_SHADER_CONSTS
) {
2989 cmd
->state
.shader_const
[MESA_SHADER_VERTEX
] =
2990 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_VERTEX
);
2991 cmd
->state
.shader_const
[MESA_SHADER_TESS_CTRL
] =
2992 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_TESS_CTRL
);
2993 cmd
->state
.shader_const
[MESA_SHADER_TESS_EVAL
] =
2994 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_TESS_EVAL
);
2995 cmd
->state
.shader_const
[MESA_SHADER_GEOMETRY
] =
2996 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_GEOMETRY
);
2997 cmd
->state
.shader_const
[MESA_SHADER_FRAGMENT
] =
2998 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_FRAGMENT
);
3001 if (cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
)
3002 cmd
->state
.vertex_buffers
= tu6_emit_vertex_buffers(cmd
, pipeline
);
3005 pipeline
->active_stages
& VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
;
3006 struct tu_draw_state tess_consts
= {};
3008 uint64_t tess_factor_iova
= 0;
3010 cmd
->has_tess
= true;
3011 result
= tu6_emit_tess_consts(cmd
, draw_count
, pipeline
, &tess_consts
, &tess_factor_iova
);
3012 if (result
!= VK_SUCCESS
)
3015 /* this sequence matches what the blob does before every tess draw
3016 * PC_TESSFACTOR_ADDR_LO is a non-context register and needs a wfi
3017 * before writing to it
3021 tu_cs_emit_pkt4(cs
, REG_A6XX_PC_TESSFACTOR_ADDR_LO
, 2);
3022 tu_cs_emit_qw(cs
, tess_factor_iova
);
3024 tu_cs_emit_pkt7(cs
, CP_SET_SUBDRAW_SIZE
, 1);
3025 tu_cs_emit(cs
, draw_count
);
3028 /* for the first draw in a renderpass, re-emit all the draw states
3030 * and if a draw-state disabling path (CmdClearAttachments 3D fallback) was
3031 * used, then draw states must be re-emitted. note however this only happens
3032 * in the sysmem path, so this can be skipped this for the gmem path (TODO)
3034 * the two input attachment states are excluded because secondary command
3035 * buffer doesn't have a state ib to restore it, and not re-emitting them
3036 * is OK since CmdClearAttachments won't disable/overwrite them
3038 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DRAW_STATE
) {
3039 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * (TU_DRAW_STATE_COUNT
- 2));
3041 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_PROGRAM
, pipeline
->program
.state
);
3042 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_PROGRAM_BINNING
, pipeline
->program
.binning_state
);
3043 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_TESS
, tess_consts
);
3044 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VI
, pipeline
->vi
.state
);
3045 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VI_BINNING
, pipeline
->vi
.binning_state
);
3046 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_RAST
, pipeline
->rast_state
);
3047 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DS
, pipeline
->ds_state
);
3048 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_BLEND
, pipeline
->blend_state
);
3049 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_VERTEX
]);
3050 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_HS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_TESS_CTRL
]);
3051 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_TESS_EVAL
]);
3052 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_GS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_GEOMETRY
]);
3053 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_FS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_FRAGMENT
]);
3054 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DESC_SETS
, cmd
->state
.desc_sets
);
3055 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DESC_SETS_LOAD
, pipeline
->load_state
);
3056 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VB
, cmd
->state
.vertex_buffers
);
3057 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VS_PARAMS
, cmd
->state
.vs_params
);
3059 for (uint32_t i
= 0; i
< ARRAY_SIZE(cmd
->state
.dynamic_state
); i
++) {
3060 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DYNAMIC
+ i
,
3061 ((pipeline
->dynamic_state_mask
& BIT(i
)) ?
3062 cmd
->state
.dynamic_state
[i
] :
3063 pipeline
->dynamic_state
[i
]));
3067 /* emit draw states that were just updated
3068 * note we eventually don't want to have to emit anything here
3070 uint32_t draw_state_count
=
3072 ((cmd
->state
.dirty
& TU_CMD_DIRTY_SHADER_CONSTS
) ? 5 : 0) +
3073 ((cmd
->state
.dirty
& TU_CMD_DIRTY_DESC_SETS_LOAD
) ? 1 : 0) +
3074 ((cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
) ? 1 : 0) +
3077 tu_cs_emit_pkt7(cs
, CP_SET_DRAW_STATE
, 3 * draw_state_count
);
3079 /* We may need to re-emit tess consts if the current draw call is
3080 * sufficiently larger than the last draw call. */
3082 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_TESS
, tess_consts
);
3083 if (cmd
->state
.dirty
& TU_CMD_DIRTY_SHADER_CONSTS
) {
3084 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_VERTEX
]);
3085 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_HS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_TESS_CTRL
]);
3086 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_TESS_EVAL
]);
3087 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_GS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_GEOMETRY
]);
3088 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_FS_CONST
, cmd
->state
.shader_const
[MESA_SHADER_FRAGMENT
]);
3090 if (cmd
->state
.dirty
& TU_CMD_DIRTY_DESC_SETS_LOAD
)
3091 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_DESC_SETS_LOAD
, pipeline
->load_state
);
3092 if (cmd
->state
.dirty
& TU_CMD_DIRTY_VERTEX_BUFFERS
)
3093 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VB
, cmd
->state
.vertex_buffers
);
3094 tu_cs_emit_draw_state(cs
, TU_DRAW_STATE_VS_PARAMS
, cmd
->state
.vs_params
);
3097 tu_cs_sanity_check(cs
);
3099 /* There are too many graphics dirty bits to list here, so just list the
3100 * bits to preserve instead. The only things not emitted here are
3101 * compute-related state.
3103 cmd
->state
.dirty
&= TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD
;
3108 tu_draw_initiator(struct tu_cmd_buffer
*cmd
, enum pc_di_src_sel src_sel
)
3110 const struct tu_pipeline
*pipeline
= cmd
->state
.pipeline
;
3111 uint32_t initiator
=
3112 CP_DRAW_INDX_OFFSET_0_PRIM_TYPE(pipeline
->ia
.primtype
) |
3113 CP_DRAW_INDX_OFFSET_0_SOURCE_SELECT(src_sel
) |
3114 CP_DRAW_INDX_OFFSET_0_INDEX_SIZE(cmd
->state
.index_size
) |
3115 CP_DRAW_INDX_OFFSET_0_VIS_CULL(USE_VISIBILITY
);
3117 if (pipeline
->active_stages
& VK_SHADER_STAGE_GEOMETRY_BIT
)
3118 initiator
|= CP_DRAW_INDX_OFFSET_0_GS_ENABLE
;
3120 switch (pipeline
->tess
.patch_type
) {
3121 case IR3_TESS_TRIANGLES
:
3122 initiator
|= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_TRIANGLES
) |
3123 CP_DRAW_INDX_OFFSET_0_TESS_ENABLE
;
3125 case IR3_TESS_ISOLINES
:
3126 initiator
|= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_ISOLINES
) |
3127 CP_DRAW_INDX_OFFSET_0_TESS_ENABLE
;
3130 initiator
|= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_QUADS
);
3132 case IR3_TESS_QUADS
:
3133 initiator
|= CP_DRAW_INDX_OFFSET_0_PATCH_TYPE(TESS_QUADS
) |
3134 CP_DRAW_INDX_OFFSET_0_TESS_ENABLE
;
3142 vs_params_offset(struct tu_cmd_buffer
*cmd
)
3144 const struct tu_program_descriptor_linkage
*link
=
3145 &cmd
->state
.pipeline
->program
.link
[MESA_SHADER_VERTEX
];
3146 const struct ir3_const_state
*const_state
= &link
->const_state
;
3148 if (const_state
->offsets
.driver_param
>= link
->constlen
)
3151 /* this layout is required by CP_DRAW_INDIRECT_MULTI */
3152 STATIC_ASSERT(IR3_DP_DRAWID
== 0);
3153 STATIC_ASSERT(IR3_DP_VTXID_BASE
== 1);
3154 STATIC_ASSERT(IR3_DP_INSTID_BASE
== 2);
3156 /* 0 means disabled for CP_DRAW_INDIRECT_MULTI */
3157 assert(const_state
->offsets
.driver_param
!= 0);
3159 return const_state
->offsets
.driver_param
;
3162 static struct tu_draw_state
3163 tu6_emit_vs_params(struct tu_cmd_buffer
*cmd
,
3164 uint32_t vertex_offset
,
3165 uint32_t first_instance
)
3167 uint32_t offset
= vs_params_offset(cmd
);
3170 VkResult result
= tu_cs_begin_sub_stream(&cmd
->sub_cs
, 3 + (offset
? 8 : 0), &cs
);
3171 if (result
!= VK_SUCCESS
) {
3172 cmd
->record_result
= result
;
3173 return (struct tu_draw_state
) {};
3176 /* TODO: don't make a new draw state when it doesn't change */
3178 tu_cs_emit_regs(&cs
,
3179 A6XX_VFD_INDEX_OFFSET(vertex_offset
),
3180 A6XX_VFD_INSTANCE_START_OFFSET(first_instance
));
3183 tu_cs_emit_pkt7(&cs
, CP_LOAD_STATE6_GEOM
, 3 + 4);
3184 tu_cs_emit(&cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
3185 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
3186 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
3187 CP_LOAD_STATE6_0_STATE_BLOCK(SB6_VS_SHADER
) |
3188 CP_LOAD_STATE6_0_NUM_UNIT(1));
3193 tu_cs_emit(&cs
, vertex_offset
);
3194 tu_cs_emit(&cs
, first_instance
);
3198 struct tu_cs_entry entry
= tu_cs_end_sub_stream(&cmd
->sub_cs
, &cs
);
3199 return (struct tu_draw_state
) {entry
.bo
->iova
+ entry
.offset
, entry
.size
/ 4};
3203 tu_CmdDraw(VkCommandBuffer commandBuffer
,
3204 uint32_t vertexCount
,
3205 uint32_t instanceCount
,
3206 uint32_t firstVertex
,
3207 uint32_t firstInstance
)
3209 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3210 struct tu_cs
*cs
= &cmd
->draw_cs
;
3212 cmd
->state
.vs_params
= tu6_emit_vs_params(cmd
, firstVertex
, firstInstance
);
3214 tu6_draw_common(cmd
, cs
, false, vertexCount
);
3216 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 3);
3217 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_AUTO_INDEX
));
3218 tu_cs_emit(cs
, instanceCount
);
3219 tu_cs_emit(cs
, vertexCount
);
3223 tu_CmdDrawIndexed(VkCommandBuffer commandBuffer
,
3224 uint32_t indexCount
,
3225 uint32_t instanceCount
,
3226 uint32_t firstIndex
,
3227 int32_t vertexOffset
,
3228 uint32_t firstInstance
)
3230 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3231 struct tu_cs
*cs
= &cmd
->draw_cs
;
3233 cmd
->state
.vs_params
= tu6_emit_vs_params(cmd
, vertexOffset
, firstInstance
);
3235 tu6_draw_common(cmd
, cs
, true, indexCount
);
3237 tu_cs_emit_pkt7(cs
, CP_DRAW_INDX_OFFSET
, 7);
3238 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_DMA
));
3239 tu_cs_emit(cs
, instanceCount
);
3240 tu_cs_emit(cs
, indexCount
);
3241 tu_cs_emit(cs
, firstIndex
);
3242 tu_cs_emit_qw(cs
, cmd
->state
.index_va
);
3243 tu_cs_emit(cs
, cmd
->state
.max_index_count
);
3246 /* Various firmware bugs/inconsistencies mean that some indirect draw opcodes
3247 * do not wait for WFI's to complete before executing. Add a WAIT_FOR_ME if
3248 * pending for these opcodes. This may result in a few extra WAIT_FOR_ME's
3249 * with these opcodes, but the alternative would add unnecessary WAIT_FOR_ME's
3250 * before draw opcodes that don't need it.
3253 draw_wfm(struct tu_cmd_buffer
*cmd
)
3255 cmd
->state
.renderpass_cache
.flush_bits
|=
3256 cmd
->state
.renderpass_cache
.pending_flush_bits
& TU_CMD_FLAG_WAIT_FOR_ME
;
3257 cmd
->state
.renderpass_cache
.pending_flush_bits
&= ~TU_CMD_FLAG_WAIT_FOR_ME
;
3261 tu_CmdDrawIndirect(VkCommandBuffer commandBuffer
,
3263 VkDeviceSize offset
,
3267 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3268 TU_FROM_HANDLE(tu_buffer
, buf
, _buffer
);
3269 struct tu_cs
*cs
= &cmd
->draw_cs
;
3271 cmd
->state
.vs_params
= (struct tu_draw_state
) {};
3273 /* The latest known a630_sqe.fw fails to wait for WFI before reading the
3274 * indirect buffer when using CP_DRAW_INDIRECT_MULTI, so we have to fall
3275 * back to CP_WAIT_FOR_ME except for a650 which has a fixed firmware.
3277 * TODO: There may be newer a630_sqe.fw released in the future which fixes
3278 * this, if so we should detect it and avoid this workaround.
3280 if (cmd
->device
->physical_device
->gpu_id
!= 650)
3283 tu6_draw_common(cmd
, cs
, false, 0);
3285 tu_cs_emit_pkt7(cs
, CP_DRAW_INDIRECT_MULTI
, 6);
3286 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_AUTO_INDEX
));
3287 tu_cs_emit(cs
, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_NORMAL
) |
3288 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd
)));
3289 tu_cs_emit(cs
, drawCount
);
3290 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ buf
->bo_offset
+ offset
);
3291 tu_cs_emit(cs
, stride
);
3293 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
3297 tu_CmdDrawIndexedIndirect(VkCommandBuffer commandBuffer
,
3299 VkDeviceSize offset
,
3303 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3304 TU_FROM_HANDLE(tu_buffer
, buf
, _buffer
);
3305 struct tu_cs
*cs
= &cmd
->draw_cs
;
3307 cmd
->state
.vs_params
= (struct tu_draw_state
) {};
3309 if (cmd
->device
->physical_device
->gpu_id
!= 650)
3312 tu6_draw_common(cmd
, cs
, true, 0);
3314 tu_cs_emit_pkt7(cs
, CP_DRAW_INDIRECT_MULTI
, 9);
3315 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_DMA
));
3316 tu_cs_emit(cs
, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDEXED
) |
3317 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd
)));
3318 tu_cs_emit(cs
, drawCount
);
3319 tu_cs_emit_qw(cs
, cmd
->state
.index_va
);
3320 tu_cs_emit(cs
, cmd
->state
.max_index_count
);
3321 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ buf
->bo_offset
+ offset
);
3322 tu_cs_emit(cs
, stride
);
3324 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
3328 tu_CmdDrawIndirectCount(VkCommandBuffer commandBuffer
,
3330 VkDeviceSize offset
,
3331 VkBuffer countBuffer
,
3332 VkDeviceSize countBufferOffset
,
3336 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3337 TU_FROM_HANDLE(tu_buffer
, buf
, _buffer
);
3338 TU_FROM_HANDLE(tu_buffer
, count_buf
, countBuffer
);
3339 struct tu_cs
*cs
= &cmd
->draw_cs
;
3341 cmd
->state
.vs_params
= (struct tu_draw_state
) {};
3343 /* It turns out that the firmware we have for a650 only partially fixed the
3344 * problem with CP_DRAW_INDIRECT_MULTI not waiting for WFI's to complete
3345 * before reading indirect parameters. It waits for WFI's before reading
3346 * the draw parameters, but after reading the indirect count :(.
3350 tu6_draw_common(cmd
, cs
, false, 0);
3352 tu_cs_emit_pkt7(cs
, CP_DRAW_INDIRECT_MULTI
, 8);
3353 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_AUTO_INDEX
));
3354 tu_cs_emit(cs
, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDIRECT_COUNT
) |
3355 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd
)));
3356 tu_cs_emit(cs
, drawCount
);
3357 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ buf
->bo_offset
+ offset
);
3358 tu_cs_emit_qw(cs
, count_buf
->bo
->iova
+ count_buf
->bo_offset
+ countBufferOffset
);
3359 tu_cs_emit(cs
, stride
);
3361 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
3362 tu_bo_list_add(&cmd
->bo_list
, count_buf
->bo
, MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
3366 tu_CmdDrawIndexedIndirectCount(VkCommandBuffer commandBuffer
,
3368 VkDeviceSize offset
,
3369 VkBuffer countBuffer
,
3370 VkDeviceSize countBufferOffset
,
3374 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3375 TU_FROM_HANDLE(tu_buffer
, buf
, _buffer
);
3376 TU_FROM_HANDLE(tu_buffer
, count_buf
, countBuffer
);
3377 struct tu_cs
*cs
= &cmd
->draw_cs
;
3379 cmd
->state
.vs_params
= (struct tu_draw_state
) {};
3383 tu6_draw_common(cmd
, cs
, true, 0);
3385 tu_cs_emit_pkt7(cs
, CP_DRAW_INDIRECT_MULTI
, 11);
3386 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_DMA
));
3387 tu_cs_emit(cs
, A6XX_CP_DRAW_INDIRECT_MULTI_1_OPCODE(INDIRECT_OP_INDIRECT_COUNT_INDEXED
) |
3388 A6XX_CP_DRAW_INDIRECT_MULTI_1_DST_OFF(vs_params_offset(cmd
)));
3389 tu_cs_emit(cs
, drawCount
);
3390 tu_cs_emit_qw(cs
, cmd
->state
.index_va
);
3391 tu_cs_emit(cs
, cmd
->state
.max_index_count
);
3392 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ buf
->bo_offset
+ offset
);
3393 tu_cs_emit_qw(cs
, count_buf
->bo
->iova
+ count_buf
->bo_offset
+ countBufferOffset
);
3394 tu_cs_emit(cs
, stride
);
3396 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
3397 tu_bo_list_add(&cmd
->bo_list
, count_buf
->bo
, MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_DUMP
);
3400 void tu_CmdDrawIndirectByteCountEXT(VkCommandBuffer commandBuffer
,
3401 uint32_t instanceCount
,
3402 uint32_t firstInstance
,
3403 VkBuffer _counterBuffer
,
3404 VkDeviceSize counterBufferOffset
,
3405 uint32_t counterOffset
,
3406 uint32_t vertexStride
)
3408 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3409 TU_FROM_HANDLE(tu_buffer
, buf
, _counterBuffer
);
3410 struct tu_cs
*cs
= &cmd
->draw_cs
;
3412 /* All known firmware versions do not wait for WFI's with CP_DRAW_AUTO.
3413 * Plus, for the common case where the counter buffer is written by
3414 * vkCmdEndTransformFeedback, we need to wait for the CP_WAIT_MEM_WRITES to
3415 * complete which means we need a WAIT_FOR_ME anyway.
3419 cmd
->state
.vs_params
= tu6_emit_vs_params(cmd
, 0, firstInstance
);
3421 tu6_draw_common(cmd
, cs
, false, 0);
3423 tu_cs_emit_pkt7(cs
, CP_DRAW_AUTO
, 6);
3424 tu_cs_emit(cs
, tu_draw_initiator(cmd
, DI_SRC_SEL_AUTO_XFB
));
3425 tu_cs_emit(cs
, instanceCount
);
3426 tu_cs_emit_qw(cs
, buf
->bo
->iova
+ buf
->bo_offset
+ counterBufferOffset
);
3427 tu_cs_emit(cs
, counterOffset
);
3428 tu_cs_emit(cs
, vertexStride
);
3430 tu_bo_list_add(&cmd
->bo_list
, buf
->bo
, MSM_SUBMIT_BO_READ
);
3433 struct tu_dispatch_info
3436 * Determine the layout of the grid (in block units) to be used.
3441 * A starting offset for the grid. If unaligned is set, the offset
3442 * must still be aligned.
3444 uint32_t offsets
[3];
3446 * Whether it's an unaligned compute dispatch.
3451 * Indirect compute parameters resource.
3453 struct tu_buffer
*indirect
;
3454 uint64_t indirect_offset
;
3458 tu_emit_compute_driver_params(struct tu_cs
*cs
, struct tu_pipeline
*pipeline
,
3459 const struct tu_dispatch_info
*info
)
3461 gl_shader_stage type
= MESA_SHADER_COMPUTE
;
3462 const struct tu_program_descriptor_linkage
*link
=
3463 &pipeline
->program
.link
[type
];
3464 const struct ir3_const_state
*const_state
= &link
->const_state
;
3465 uint32_t offset
= const_state
->offsets
.driver_param
;
3467 if (link
->constlen
<= offset
)
3470 if (!info
->indirect
) {
3471 uint32_t driver_params
[IR3_DP_CS_COUNT
] = {
3472 [IR3_DP_NUM_WORK_GROUPS_X
] = info
->blocks
[0],
3473 [IR3_DP_NUM_WORK_GROUPS_Y
] = info
->blocks
[1],
3474 [IR3_DP_NUM_WORK_GROUPS_Z
] = info
->blocks
[2],
3475 [IR3_DP_LOCAL_GROUP_SIZE_X
] = pipeline
->compute
.local_size
[0],
3476 [IR3_DP_LOCAL_GROUP_SIZE_Y
] = pipeline
->compute
.local_size
[1],
3477 [IR3_DP_LOCAL_GROUP_SIZE_Z
] = pipeline
->compute
.local_size
[2],
3480 uint32_t num_consts
= MIN2(const_state
->num_driver_params
,
3481 (link
->constlen
- offset
) * 4);
3482 /* push constants */
3483 tu_cs_emit_pkt7(cs
, tu6_stage2opcode(type
), 3 + num_consts
);
3484 tu_cs_emit(cs
, CP_LOAD_STATE6_0_DST_OFF(offset
) |
3485 CP_LOAD_STATE6_0_STATE_TYPE(ST6_CONSTANTS
) |
3486 CP_LOAD_STATE6_0_STATE_SRC(SS6_DIRECT
) |
3487 CP_LOAD_STATE6_0_STATE_BLOCK(tu6_stage2shadersb(type
)) |
3488 CP_LOAD_STATE6_0_NUM_UNIT(num_consts
/ 4));
3492 for (i
= 0; i
< num_consts
; i
++)
3493 tu_cs_emit(cs
, driver_params
[i
]);
3495 tu_finishme("Indirect driver params");
3500 tu_dispatch(struct tu_cmd_buffer
*cmd
,
3501 const struct tu_dispatch_info
*info
)
3503 struct tu_cs
*cs
= &cmd
->cs
;
3504 struct tu_pipeline
*pipeline
= cmd
->state
.compute_pipeline
;
3505 struct tu_descriptor_state
*descriptors_state
=
3506 &cmd
->descriptors
[VK_PIPELINE_BIND_POINT_COMPUTE
];
3508 /* TODO: We could probably flush less if we add a compute_flush_bits
3511 tu_emit_cache_flush(cmd
, cs
);
3513 /* note: no reason to have this in a separate IB */
3514 tu_cs_emit_state_ib(cs
,
3515 tu6_emit_consts(cmd
, pipeline
, descriptors_state
, MESA_SHADER_COMPUTE
));
3517 tu_emit_compute_driver_params(cs
, pipeline
, info
);
3519 if (cmd
->state
.dirty
& TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD
)
3520 tu_cs_emit_state_ib(cs
, pipeline
->load_state
);
3522 cmd
->state
.dirty
&= ~TU_CMD_DIRTY_COMPUTE_DESC_SETS_LOAD
;
3524 tu_cs_emit_pkt7(cs
, CP_SET_MARKER
, 1);
3525 tu_cs_emit(cs
, A6XX_CP_SET_MARKER_0_MODE(RM6_COMPUTE
));
3527 const uint32_t *local_size
= pipeline
->compute
.local_size
;
3528 const uint32_t *num_groups
= info
->blocks
;
3530 A6XX_HLSQ_CS_NDRANGE_0(.kerneldim
= 3,
3531 .localsizex
= local_size
[0] - 1,
3532 .localsizey
= local_size
[1] - 1,
3533 .localsizez
= local_size
[2] - 1),
3534 A6XX_HLSQ_CS_NDRANGE_1(.globalsize_x
= local_size
[0] * num_groups
[0]),
3535 A6XX_HLSQ_CS_NDRANGE_2(.globaloff_x
= 0),
3536 A6XX_HLSQ_CS_NDRANGE_3(.globalsize_y
= local_size
[1] * num_groups
[1]),
3537 A6XX_HLSQ_CS_NDRANGE_4(.globaloff_y
= 0),
3538 A6XX_HLSQ_CS_NDRANGE_5(.globalsize_z
= local_size
[2] * num_groups
[2]),
3539 A6XX_HLSQ_CS_NDRANGE_6(.globaloff_z
= 0));
3542 A6XX_HLSQ_CS_KERNEL_GROUP_X(1),
3543 A6XX_HLSQ_CS_KERNEL_GROUP_Y(1),
3544 A6XX_HLSQ_CS_KERNEL_GROUP_Z(1));
3546 if (info
->indirect
) {
3547 uint64_t iova
= tu_buffer_iova(info
->indirect
) + info
->indirect_offset
;
3549 tu_bo_list_add(&cmd
->bo_list
, info
->indirect
->bo
,
3550 MSM_SUBMIT_BO_READ
| MSM_SUBMIT_BO_WRITE
);
3552 tu_cs_emit_pkt7(cs
, CP_EXEC_CS_INDIRECT
, 4);
3553 tu_cs_emit(cs
, 0x00000000);
3554 tu_cs_emit_qw(cs
, iova
);
3556 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEX(local_size
[0] - 1) |
3557 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEY(local_size
[1] - 1) |
3558 A5XX_CP_EXEC_CS_INDIRECT_3_LOCALSIZEZ(local_size
[2] - 1));
3560 tu_cs_emit_pkt7(cs
, CP_EXEC_CS
, 4);
3561 tu_cs_emit(cs
, 0x00000000);
3562 tu_cs_emit(cs
, CP_EXEC_CS_1_NGROUPS_X(info
->blocks
[0]));
3563 tu_cs_emit(cs
, CP_EXEC_CS_2_NGROUPS_Y(info
->blocks
[1]));
3564 tu_cs_emit(cs
, CP_EXEC_CS_3_NGROUPS_Z(info
->blocks
[2]));
3571 tu_CmdDispatchBase(VkCommandBuffer commandBuffer
,
3579 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3580 struct tu_dispatch_info info
= {};
3586 info
.offsets
[0] = base_x
;
3587 info
.offsets
[1] = base_y
;
3588 info
.offsets
[2] = base_z
;
3589 tu_dispatch(cmd_buffer
, &info
);
3593 tu_CmdDispatch(VkCommandBuffer commandBuffer
,
3598 tu_CmdDispatchBase(commandBuffer
, 0, 0, 0, x
, y
, z
);
3602 tu_CmdDispatchIndirect(VkCommandBuffer commandBuffer
,
3604 VkDeviceSize offset
)
3606 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3607 TU_FROM_HANDLE(tu_buffer
, buffer
, _buffer
);
3608 struct tu_dispatch_info info
= {};
3610 info
.indirect
= buffer
;
3611 info
.indirect_offset
= offset
;
3613 tu_dispatch(cmd_buffer
, &info
);
3617 tu_CmdEndRenderPass(VkCommandBuffer commandBuffer
)
3619 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3621 tu_cs_end(&cmd_buffer
->draw_cs
);
3622 tu_cs_end(&cmd_buffer
->draw_epilogue_cs
);
3624 if (use_sysmem_rendering(cmd_buffer
))
3625 tu_cmd_render_sysmem(cmd_buffer
);
3627 tu_cmd_render_tiles(cmd_buffer
);
3629 /* discard draw_cs and draw_epilogue_cs entries now that the tiles are
3631 tu_cs_discard_entries(&cmd_buffer
->draw_cs
);
3632 tu_cs_begin(&cmd_buffer
->draw_cs
);
3633 tu_cs_discard_entries(&cmd_buffer
->draw_epilogue_cs
);
3634 tu_cs_begin(&cmd_buffer
->draw_epilogue_cs
);
3636 cmd_buffer
->state
.cache
.pending_flush_bits
|=
3637 cmd_buffer
->state
.renderpass_cache
.pending_flush_bits
;
3638 tu_subpass_barrier(cmd_buffer
, &cmd_buffer
->state
.pass
->end_barrier
, true);
3640 cmd_buffer
->state
.pass
= NULL
;
3641 cmd_buffer
->state
.subpass
= NULL
;
3642 cmd_buffer
->state
.framebuffer
= NULL
;
3646 tu_CmdEndRenderPass2(VkCommandBuffer commandBuffer
,
3647 const VkSubpassEndInfoKHR
*pSubpassEndInfo
)
3649 tu_CmdEndRenderPass(commandBuffer
);
3652 struct tu_barrier_info
3654 uint32_t eventCount
;
3655 const VkEvent
*pEvents
;
3656 VkPipelineStageFlags srcStageMask
;
3660 tu_barrier(struct tu_cmd_buffer
*cmd
,
3661 uint32_t memoryBarrierCount
,
3662 const VkMemoryBarrier
*pMemoryBarriers
,
3663 uint32_t bufferMemoryBarrierCount
,
3664 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3665 uint32_t imageMemoryBarrierCount
,
3666 const VkImageMemoryBarrier
*pImageMemoryBarriers
,
3667 const struct tu_barrier_info
*info
)
3669 struct tu_cs
*cs
= cmd
->state
.pass
? &cmd
->draw_cs
: &cmd
->cs
;
3670 VkAccessFlags srcAccessMask
= 0;
3671 VkAccessFlags dstAccessMask
= 0;
3673 for (uint32_t i
= 0; i
< memoryBarrierCount
; i
++) {
3674 srcAccessMask
|= pMemoryBarriers
[i
].srcAccessMask
;
3675 dstAccessMask
|= pMemoryBarriers
[i
].dstAccessMask
;
3678 for (uint32_t i
= 0; i
< bufferMemoryBarrierCount
; i
++) {
3679 srcAccessMask
|= pBufferMemoryBarriers
[i
].srcAccessMask
;
3680 dstAccessMask
|= pBufferMemoryBarriers
[i
].dstAccessMask
;
3683 enum tu_cmd_access_mask src_flags
= 0;
3684 enum tu_cmd_access_mask dst_flags
= 0;
3686 for (uint32_t i
= 0; i
< imageMemoryBarrierCount
; i
++) {
3687 TU_FROM_HANDLE(tu_image
, image
, pImageMemoryBarriers
[i
].image
);
3688 VkImageLayout old_layout
= pImageMemoryBarriers
[i
].oldLayout
;
3689 /* For non-linear images, PREINITIALIZED is the same as UNDEFINED */
3690 if (old_layout
== VK_IMAGE_LAYOUT_UNDEFINED
||
3691 (image
->tiling
!= VK_IMAGE_TILING_LINEAR
&&
3692 old_layout
== VK_IMAGE_LAYOUT_PREINITIALIZED
)) {
3693 /* The underlying memory for this image may have been used earlier
3694 * within the same queue submission for a different image, which
3695 * means that there may be old, stale cache entries which are in the
3696 * "wrong" location, which could cause problems later after writing
3697 * to the image. We don't want these entries being flushed later and
3698 * overwriting the actual image, so we need to flush the CCU.
3700 src_flags
|= TU_ACCESS_CCU_COLOR_INCOHERENT_WRITE
;
3702 srcAccessMask
|= pImageMemoryBarriers
[i
].srcAccessMask
;
3703 dstAccessMask
|= pImageMemoryBarriers
[i
].dstAccessMask
;
3706 /* Inside a renderpass, we don't know yet whether we'll be using sysmem
3707 * so we have to use the sysmem flushes.
3709 bool gmem
= cmd
->state
.ccu_state
== TU_CMD_CCU_GMEM
&&
3711 src_flags
|= vk2tu_access(srcAccessMask
, gmem
);
3712 dst_flags
|= vk2tu_access(dstAccessMask
, gmem
);
3714 struct tu_cache_state
*cache
=
3715 cmd
->state
.pass
? &cmd
->state
.renderpass_cache
: &cmd
->state
.cache
;
3716 tu_flush_for_access(cache
, src_flags
, dst_flags
);
3718 for (uint32_t i
= 0; i
< info
->eventCount
; i
++) {
3719 TU_FROM_HANDLE(tu_event
, event
, info
->pEvents
[i
]);
3721 tu_bo_list_add(&cmd
->bo_list
, &event
->bo
, MSM_SUBMIT_BO_READ
);
3723 tu_cs_emit_pkt7(cs
, CP_WAIT_REG_MEM
, 6);
3724 tu_cs_emit(cs
, CP_WAIT_REG_MEM_0_FUNCTION(WRITE_EQ
) |
3725 CP_WAIT_REG_MEM_0_POLL_MEMORY
);
3726 tu_cs_emit_qw(cs
, event
->bo
.iova
); /* POLL_ADDR_LO/HI */
3727 tu_cs_emit(cs
, CP_WAIT_REG_MEM_3_REF(1));
3728 tu_cs_emit(cs
, CP_WAIT_REG_MEM_4_MASK(~0u));
3729 tu_cs_emit(cs
, CP_WAIT_REG_MEM_5_DELAY_LOOP_CYCLES(20));
3734 tu_CmdPipelineBarrier(VkCommandBuffer commandBuffer
,
3735 VkPipelineStageFlags srcStageMask
,
3736 VkPipelineStageFlags dstStageMask
,
3737 VkDependencyFlags dependencyFlags
,
3738 uint32_t memoryBarrierCount
,
3739 const VkMemoryBarrier
*pMemoryBarriers
,
3740 uint32_t bufferMemoryBarrierCount
,
3741 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3742 uint32_t imageMemoryBarrierCount
,
3743 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3745 TU_FROM_HANDLE(tu_cmd_buffer
, cmd_buffer
, commandBuffer
);
3746 struct tu_barrier_info info
;
3748 info
.eventCount
= 0;
3749 info
.pEvents
= NULL
;
3750 info
.srcStageMask
= srcStageMask
;
3752 tu_barrier(cmd_buffer
, memoryBarrierCount
, pMemoryBarriers
,
3753 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
3754 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
3758 write_event(struct tu_cmd_buffer
*cmd
, struct tu_event
*event
,
3759 VkPipelineStageFlags stageMask
, unsigned value
)
3761 struct tu_cs
*cs
= &cmd
->cs
;
3763 /* vkCmdSetEvent/vkCmdResetEvent cannot be called inside a render pass */
3764 assert(!cmd
->state
.pass
);
3766 tu_emit_cache_flush(cmd
, cs
);
3768 tu_bo_list_add(&cmd
->bo_list
, &event
->bo
, MSM_SUBMIT_BO_WRITE
);
3770 /* Flags that only require a top-of-pipe event. DrawIndirect parameters are
3771 * read by the CP, so the draw indirect stage counts as top-of-pipe too.
3773 VkPipelineStageFlags top_of_pipe_flags
=
3774 VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT
|
3775 VK_PIPELINE_STAGE_DRAW_INDIRECT_BIT
;
3777 if (!(stageMask
& ~top_of_pipe_flags
)) {
3778 tu_cs_emit_pkt7(cs
, CP_MEM_WRITE
, 3);
3779 tu_cs_emit_qw(cs
, event
->bo
.iova
); /* ADDR_LO/HI */
3780 tu_cs_emit(cs
, value
);
3782 /* Use a RB_DONE_TS event to wait for everything to complete. */
3783 tu_cs_emit_pkt7(cs
, CP_EVENT_WRITE
, 4);
3784 tu_cs_emit(cs
, CP_EVENT_WRITE_0_EVENT(RB_DONE_TS
));
3785 tu_cs_emit_qw(cs
, event
->bo
.iova
);
3786 tu_cs_emit(cs
, value
);
3791 tu_CmdSetEvent(VkCommandBuffer commandBuffer
,
3793 VkPipelineStageFlags stageMask
)
3795 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3796 TU_FROM_HANDLE(tu_event
, event
, _event
);
3798 write_event(cmd
, event
, stageMask
, 1);
3802 tu_CmdResetEvent(VkCommandBuffer commandBuffer
,
3804 VkPipelineStageFlags stageMask
)
3806 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3807 TU_FROM_HANDLE(tu_event
, event
, _event
);
3809 write_event(cmd
, event
, stageMask
, 0);
3813 tu_CmdWaitEvents(VkCommandBuffer commandBuffer
,
3814 uint32_t eventCount
,
3815 const VkEvent
*pEvents
,
3816 VkPipelineStageFlags srcStageMask
,
3817 VkPipelineStageFlags dstStageMask
,
3818 uint32_t memoryBarrierCount
,
3819 const VkMemoryBarrier
*pMemoryBarriers
,
3820 uint32_t bufferMemoryBarrierCount
,
3821 const VkBufferMemoryBarrier
*pBufferMemoryBarriers
,
3822 uint32_t imageMemoryBarrierCount
,
3823 const VkImageMemoryBarrier
*pImageMemoryBarriers
)
3825 TU_FROM_HANDLE(tu_cmd_buffer
, cmd
, commandBuffer
);
3826 struct tu_barrier_info info
;
3828 info
.eventCount
= eventCount
;
3829 info
.pEvents
= pEvents
;
3830 info
.srcStageMask
= 0;
3832 tu_barrier(cmd
, memoryBarrierCount
, pMemoryBarriers
,
3833 bufferMemoryBarrierCount
, pBufferMemoryBarriers
,
3834 imageMemoryBarrierCount
, pImageMemoryBarriers
, &info
);
3838 tu_CmdSetDeviceMask(VkCommandBuffer commandBuffer
, uint32_t deviceMask
)