turnip: Fix error handling of DRM_MSM_GEM_INFO ioctls.
[mesa.git] / src / freedreno / vulkan / tu_drm.c
1 /*
2 * Copyright © 2018 Google, Inc.
3 * Copyright © 2015 Intel Corporation
4 *
5 * Permission is hereby granted, free of charge, to any person obtaining a
6 * copy of this software and associated documentation files (the "Software"),
7 * to deal in the Software without restriction, including without limitation
8 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
9 * and/or sell copies of the Software, and to permit persons to whom the
10 * Software is furnished to do so, subject to the following conditions:
11 *
12 * The above copyright notice and this permission notice (including the next
13 * paragraph) shall be included in all copies or substantial portions of the
14 * Software.
15 *
16 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
17 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
18 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
19 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
20 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
21 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER
22 * DEALINGS IN THE SOFTWARE.
23 */
24
25 #include "tu_private.h"
26
27 #include <errno.h>
28 #include <fcntl.h>
29 #include <stdint.h>
30 #include <sys/ioctl.h>
31 #include <xf86drm.h>
32
33 #include "drm-uapi/msm_drm.h"
34
35 static int
36 tu_drm_get_param(const struct tu_physical_device *dev,
37 uint32_t param,
38 uint64_t *value)
39 {
40 /* Technically this requires a pipe, but the kernel only supports one pipe
41 * anyway at the time of writing and most of these are clearly pipe
42 * independent. */
43 struct drm_msm_param req = {
44 .pipe = MSM_PIPE_3D0,
45 .param = param,
46 };
47
48 int ret = drmCommandWriteRead(dev->local_fd, DRM_MSM_GET_PARAM, &req,
49 sizeof(req));
50 if (ret)
51 return ret;
52
53 *value = req.value;
54
55 return 0;
56 }
57
58 int
59 tu_drm_get_gpu_id(const struct tu_physical_device *dev, uint32_t *id)
60 {
61 uint64_t value;
62 int ret = tu_drm_get_param(dev, MSM_PARAM_GPU_ID, &value);
63 if (ret)
64 return ret;
65
66 *id = value;
67 return 0;
68 }
69
70 int
71 tu_drm_get_gmem_size(const struct tu_physical_device *dev, uint32_t *size)
72 {
73 uint64_t value;
74 int ret = tu_drm_get_param(dev, MSM_PARAM_GMEM_SIZE, &value);
75 if (ret)
76 return ret;
77
78 *size = value;
79 return 0;
80 }
81
82 int
83 tu_drm_get_gmem_base(const struct tu_physical_device *dev, uint64_t *base)
84 {
85 return tu_drm_get_param(dev, MSM_PARAM_GMEM_BASE, base);
86 }
87
88 int
89 tu_drm_submitqueue_new(const struct tu_device *dev,
90 int priority,
91 uint32_t *queue_id)
92 {
93 struct drm_msm_submitqueue req = {
94 .flags = 0,
95 .prio = priority,
96 };
97
98 int ret = drmCommandWriteRead(dev->physical_device->local_fd,
99 DRM_MSM_SUBMITQUEUE_NEW, &req, sizeof(req));
100 if (ret)
101 return ret;
102
103 *queue_id = req.id;
104 return 0;
105 }
106
107 void
108 tu_drm_submitqueue_close(const struct tu_device *dev, uint32_t queue_id)
109 {
110 drmCommandWrite(dev->physical_device->local_fd, DRM_MSM_SUBMITQUEUE_CLOSE,
111 &queue_id, sizeof(uint32_t));
112 }
113
114 /**
115 * Return gem handle on success. Return 0 on failure.
116 */
117 uint32_t
118 tu_gem_new(const struct tu_device *dev, uint64_t size, uint32_t flags)
119 {
120 struct drm_msm_gem_new req = {
121 .size = size,
122 .flags = flags,
123 };
124
125 int ret = drmCommandWriteRead(dev->physical_device->local_fd,
126 DRM_MSM_GEM_NEW, &req, sizeof(req));
127 if (ret)
128 return 0;
129
130 return req.handle;
131 }
132
133 uint32_t
134 tu_gem_import_dmabuf(const struct tu_device *dev, int prime_fd, uint64_t size)
135 {
136 /* lseek() to get the real size */
137 off_t real_size = lseek(prime_fd, 0, SEEK_END);
138 lseek(prime_fd, 0, SEEK_SET);
139 if (real_size < 0 || (uint64_t) real_size < size)
140 return 0;
141
142 uint32_t gem_handle;
143 int ret = drmPrimeFDToHandle(dev->physical_device->local_fd, prime_fd,
144 &gem_handle);
145 if (ret)
146 return 0;
147
148 return gem_handle;
149 }
150
151 int
152 tu_gem_export_dmabuf(const struct tu_device *dev, uint32_t gem_handle)
153 {
154 int prime_fd;
155 int ret = drmPrimeHandleToFD(dev->physical_device->local_fd, gem_handle,
156 DRM_CLOEXEC, &prime_fd);
157
158 return ret == 0 ? prime_fd : -1;
159 }
160
161 void
162 tu_gem_close(const struct tu_device *dev, uint32_t gem_handle)
163 {
164 struct drm_gem_close req = {
165 .handle = gem_handle,
166 };
167
168 drmIoctl(dev->physical_device->local_fd, DRM_IOCTL_GEM_CLOSE, &req);
169 }
170
171 /** Helper for DRM_MSM_GEM_INFO, returns 0 on error. */
172 static uint64_t
173 tu_gem_info(const struct tu_device *dev, uint32_t gem_handle, uint32_t info)
174 {
175 struct drm_msm_gem_info req = {
176 .handle = gem_handle,
177 .info = info,
178 };
179
180 int ret = drmCommandWriteRead(dev->physical_device->local_fd,
181 DRM_MSM_GEM_INFO, &req, sizeof(req));
182 if (ret < 0)
183 return 0;
184
185 return req.value;
186 }
187
188 /** Returns the offset for CPU-side mmap of the gem handle.
189 *
190 * Returns 0 on error (an invalid mmap offset in the DRM UBI).
191 */
192 uint64_t
193 tu_gem_info_offset(const struct tu_device *dev, uint32_t gem_handle)
194 {
195 return tu_gem_info(dev, gem_handle, MSM_INFO_GET_OFFSET);
196 }
197
198 /** Returns the the iova of the BO in GPU memory.
199 *
200 * Returns 0 on error (an invalid iova in the MSM DRM UABI).
201 */
202 uint64_t
203 tu_gem_info_iova(const struct tu_device *dev, uint32_t gem_handle)
204 {
205 return tu_gem_info(dev, gem_handle, MSM_INFO_GET_IOVA);
206 }